ehci.c revision 1.118.2.1
1 /* $NetBSD: ehci.c,v 1.118.2.1 2007/02/21 13:26:41 tron Exp $ */ 2 3 /* 4 * Copyright (c) 2004,2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 41 * 42 * The EHCI 1.0 spec can be found at 43 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 44 * and the USB 2.0 spec at 45 * http://www.usb.org/developers/docs/usb_20.zip 46 * 47 */ 48 49 /* 50 * TODO: 51 * 1) hold off explorations by companion controllers until ehci has started. 52 * 53 * 2) The EHCI driver lacks support for isochronous transfers, so 54 * devices using them don't work. 55 * 56 * 3) The hub driver needs to handle and schedule the transaction translator, 57 * to assign place in frame where different devices get to go. See chapter 58 * on hubs in USB 2.0 for details. 59 * 60 * 4) command failures are not recovered correctly 61 */ 62 63 #include <sys/cdefs.h> 64 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.118.2.1 2007/02/21 13:26:41 tron Exp $"); 65 66 #include "ohci.h" 67 #include "uhci.h" 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/kernel.h> 72 #include <sys/malloc.h> 73 #include <sys/device.h> 74 #include <sys/select.h> 75 #include <sys/proc.h> 76 #include <sys/queue.h> 77 78 #include <machine/bus.h> 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usb_mem.h> 85 #include <dev/usb/usb_quirks.h> 86 87 #include <dev/usb/ehcireg.h> 88 #include <dev/usb/ehcivar.h> 89 90 #ifdef EHCI_DEBUG 91 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 92 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 93 int ehcidebug = 0; 94 #ifndef __NetBSD__ 95 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 96 #endif 97 #else 98 #define DPRINTF(x) 99 #define DPRINTFN(n,x) 100 #endif 101 102 struct ehci_pipe { 103 struct usbd_pipe pipe; 104 int nexttoggle; 105 106 ehci_soft_qh_t *sqh; 107 union { 108 ehci_soft_qtd_t *qtd; 109 /* ehci_soft_itd_t *itd; */ 110 } tail; 111 union { 112 /* Control pipe */ 113 struct { 114 usb_dma_t reqdma; 115 u_int length; 116 } ctl; 117 /* Interrupt pipe */ 118 struct { 119 u_int length; 120 } intr; 121 /* Bulk pipe */ 122 struct { 123 u_int length; 124 } bulk; 125 /* Iso pipe */ 126 /* XXX */ 127 } u; 128 }; 129 130 Static void ehci_shutdown(void *); 131 Static void ehci_power(int, void *); 132 133 Static usbd_status ehci_open(usbd_pipe_handle); 134 Static void ehci_poll(struct usbd_bus *); 135 Static void ehci_softintr(void *); 136 Static int ehci_intr1(ehci_softc_t *); 137 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 138 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 139 Static void ehci_idone(struct ehci_xfer *); 140 Static void ehci_timeout(void *); 141 Static void ehci_timeout_task(void *); 142 Static void ehci_intrlist_timeout(void *); 143 144 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 145 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 146 147 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 148 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 149 150 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 151 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 152 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 153 Static void ehci_root_ctrl_close(usbd_pipe_handle); 154 Static void ehci_root_ctrl_done(usbd_xfer_handle); 155 156 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 157 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 158 Static void ehci_root_intr_abort(usbd_xfer_handle); 159 Static void ehci_root_intr_close(usbd_pipe_handle); 160 Static void ehci_root_intr_done(usbd_xfer_handle); 161 162 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 163 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 164 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 165 Static void ehci_device_ctrl_close(usbd_pipe_handle); 166 Static void ehci_device_ctrl_done(usbd_xfer_handle); 167 168 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 169 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 170 Static void ehci_device_bulk_abort(usbd_xfer_handle); 171 Static void ehci_device_bulk_close(usbd_pipe_handle); 172 Static void ehci_device_bulk_done(usbd_xfer_handle); 173 174 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 175 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 176 Static void ehci_device_intr_abort(usbd_xfer_handle); 177 Static void ehci_device_intr_close(usbd_pipe_handle); 178 Static void ehci_device_intr_done(usbd_xfer_handle); 179 180 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 181 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 182 Static void ehci_device_isoc_abort(usbd_xfer_handle); 183 Static void ehci_device_isoc_close(usbd_pipe_handle); 184 Static void ehci_device_isoc_done(usbd_xfer_handle); 185 186 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 187 Static void ehci_noop(usbd_pipe_handle pipe); 188 189 Static int ehci_str(usb_string_descriptor_t *, int, const char *); 190 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 191 Static void ehci_pcd_able(ehci_softc_t *, int); 192 Static void ehci_pcd_enable(void *); 193 Static void ehci_disown(ehci_softc_t *, int, int); 194 195 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 196 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 197 198 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 199 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 200 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 201 ehci_softc_t *, int, int, usbd_xfer_handle, 202 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 203 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 204 ehci_soft_qtd_t *); 205 206 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 207 208 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 209 int ival); 210 211 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 212 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 213 ehci_soft_qh_t *); 214 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 215 Static void ehci_sync_hc(ehci_softc_t *); 216 217 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 218 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 219 220 #ifdef EHCI_DEBUG 221 Static void ehci_dump_regs(ehci_softc_t *); 222 void ehci_dump(void); 223 Static ehci_softc_t *theehci; 224 Static void ehci_dump_link(ehci_link_t, int); 225 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 226 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 227 Static void ehci_dump_qtd(ehci_qtd_t *); 228 Static void ehci_dump_sqh(ehci_soft_qh_t *); 229 #ifdef DIAGNOSTIC 230 Static void ehci_dump_exfer(struct ehci_xfer *); 231 #endif 232 #endif 233 234 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 235 236 #define EHCI_INTR_ENDPT 1 237 238 #define ehci_add_intr_list(sc, ex) \ 239 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext); 240 #define ehci_del_intr_list(ex) \ 241 do { \ 242 LIST_REMOVE((ex), inext); \ 243 (ex)->inext.le_prev = NULL; \ 244 } while (0) 245 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL) 246 247 Static struct usbd_bus_methods ehci_bus_methods = { 248 ehci_open, 249 ehci_softintr, 250 ehci_poll, 251 ehci_allocm, 252 ehci_freem, 253 ehci_allocx, 254 ehci_freex, 255 }; 256 257 Static struct usbd_pipe_methods ehci_root_ctrl_methods = { 258 ehci_root_ctrl_transfer, 259 ehci_root_ctrl_start, 260 ehci_root_ctrl_abort, 261 ehci_root_ctrl_close, 262 ehci_noop, 263 ehci_root_ctrl_done, 264 }; 265 266 Static struct usbd_pipe_methods ehci_root_intr_methods = { 267 ehci_root_intr_transfer, 268 ehci_root_intr_start, 269 ehci_root_intr_abort, 270 ehci_root_intr_close, 271 ehci_noop, 272 ehci_root_intr_done, 273 }; 274 275 Static struct usbd_pipe_methods ehci_device_ctrl_methods = { 276 ehci_device_ctrl_transfer, 277 ehci_device_ctrl_start, 278 ehci_device_ctrl_abort, 279 ehci_device_ctrl_close, 280 ehci_noop, 281 ehci_device_ctrl_done, 282 }; 283 284 Static struct usbd_pipe_methods ehci_device_intr_methods = { 285 ehci_device_intr_transfer, 286 ehci_device_intr_start, 287 ehci_device_intr_abort, 288 ehci_device_intr_close, 289 ehci_device_clear_toggle, 290 ehci_device_intr_done, 291 }; 292 293 Static struct usbd_pipe_methods ehci_device_bulk_methods = { 294 ehci_device_bulk_transfer, 295 ehci_device_bulk_start, 296 ehci_device_bulk_abort, 297 ehci_device_bulk_close, 298 ehci_device_clear_toggle, 299 ehci_device_bulk_done, 300 }; 301 302 Static struct usbd_pipe_methods ehci_device_isoc_methods = { 303 ehci_device_isoc_transfer, 304 ehci_device_isoc_start, 305 ehci_device_isoc_abort, 306 ehci_device_isoc_close, 307 ehci_noop, 308 ehci_device_isoc_done, 309 }; 310 311 static uint8_t revbits[EHCI_MAX_POLLRATE] = { 312 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 313 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 314 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 315 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 316 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 317 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 318 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 319 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 320 }; 321 322 usbd_status 323 ehci_init(ehci_softc_t *sc) 324 { 325 u_int32_t vers, sparams, cparams, hcr; 326 u_int i; 327 usbd_status err; 328 ehci_soft_qh_t *sqh; 329 u_int ncomp; 330 331 DPRINTF(("ehci_init: start\n")); 332 #ifdef EHCI_DEBUG 333 theehci = sc; 334 #endif 335 336 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 337 338 vers = EREAD2(sc, EHCI_HCIVERSION); 339 aprint_normal("%s: EHCI version %x.%x\n", USBDEVNAME(sc->sc_bus.bdev), 340 vers >> 8, vers & 0xff); 341 342 sparams = EREAD4(sc, EHCI_HCSPARAMS); 343 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 344 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 345 ncomp = EHCI_HCS_N_CC(sparams); 346 if (ncomp != sc->sc_ncomp) { 347 aprint_error("%s: wrong number of companions (%d != %d)\n", 348 USBDEVNAME(sc->sc_bus.bdev), 349 ncomp, sc->sc_ncomp); 350 #if NOHCI == 0 || NUHCI == 0 351 aprint_error("%s: ohci or uhci probably not configured\n", 352 USBDEVNAME(sc->sc_bus.bdev)); 353 #endif 354 if (ncomp < sc->sc_ncomp) 355 sc->sc_ncomp = ncomp; 356 } 357 if (sc->sc_ncomp > 0) { 358 aprint_normal("%s: companion controller%s, %d port%s each:", 359 USBDEVNAME(sc->sc_bus.bdev), sc->sc_ncomp!=1 ? "s" : "", 360 EHCI_HCS_N_PCC(sparams), 361 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 362 for (i = 0; i < sc->sc_ncomp; i++) 363 aprint_normal(" %s", USBDEVNAME(sc->sc_comps[i]->bdev)); 364 aprint_normal("\n"); 365 } 366 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 367 cparams = EREAD4(sc, EHCI_HCCPARAMS); 368 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 369 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 370 371 if (EHCI_HCC_64BIT(cparams)) { 372 /* MUST clear segment register if 64 bit capable. */ 373 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 374 } 375 376 sc->sc_bus.usbrev = USBREV_2_0; 377 378 usb_setup_reserve(sc, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 379 USB_MEM_RESERVE); 380 381 /* Reset the controller */ 382 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 383 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 384 usb_delay_ms(&sc->sc_bus, 1); 385 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 386 for (i = 0; i < 100; i++) { 387 usb_delay_ms(&sc->sc_bus, 1); 388 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 389 if (!hcr) 390 break; 391 } 392 if (hcr) { 393 aprint_error("%s: reset timeout\n", 394 USBDEVNAME(sc->sc_bus.bdev)); 395 return (USBD_IOERROR); 396 } 397 398 /* XXX need proper intr scheduling */ 399 sc->sc_rand = 96; 400 401 /* frame list size at default, read back what we got and use that */ 402 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 403 case 0: sc->sc_flsize = 1024; break; 404 case 1: sc->sc_flsize = 512; break; 405 case 2: sc->sc_flsize = 256; break; 406 case 3: return (USBD_IOERROR); 407 } 408 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 409 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 410 if (err) 411 return (err); 412 DPRINTF(("%s: flsize=%d\n", USBDEVNAME(sc->sc_bus.bdev),sc->sc_flsize)); 413 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 414 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 415 416 /* Set up the bus struct. */ 417 sc->sc_bus.methods = &ehci_bus_methods; 418 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 419 420 sc->sc_powerhook = powerhook_establish(USBDEVNAME(sc->sc_bus.bdev), 421 ehci_power, sc); 422 sc->sc_shutdownhook = shutdownhook_establish(ehci_shutdown, sc); 423 424 sc->sc_eintrs = EHCI_NORMAL_INTRS; 425 426 /* 427 * Allocate the interrupt dummy QHs. These are arranged to give poll 428 * intervals that are powers of 2 times 1ms. 429 */ 430 for (i = 0; i < EHCI_INTRQHS; i++) { 431 sqh = ehci_alloc_sqh(sc); 432 if (sqh == NULL) { 433 err = USBD_NOMEM; 434 goto bad1; 435 } 436 sc->sc_islots[i].sqh = sqh; 437 } 438 for (i = 0; i < EHCI_INTRQHS; i++) { 439 sqh = sc->sc_islots[i].sqh; 440 if (i == 0) { 441 /* The last (1ms) QH terminates. */ 442 sqh->qh.qh_link = EHCI_NULL; 443 sqh->next = NULL; 444 } else { 445 /* Otherwise the next QH has half the poll interval */ 446 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 447 sqh->qh.qh_link = htole32(sqh->next->physaddr | 448 EHCI_LINK_QH); 449 } 450 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 451 sqh->qh.qh_curqtd = EHCI_NULL; 452 sqh->next = NULL; 453 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 454 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 455 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 456 sqh->sqtd = NULL; 457 } 458 /* Point the frame list at the last level (128ms). */ 459 for (i = 0; i < sc->sc_flsize; i++) { 460 int j; 461 462 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 463 revbits[i & (EHCI_MAX_POLLRATE-1)]; 464 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 465 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 466 i)].sqh->physaddr); 467 } 468 469 /* Allocate dummy QH that starts the async list. */ 470 sqh = ehci_alloc_sqh(sc); 471 if (sqh == NULL) { 472 err = USBD_NOMEM; 473 goto bad1; 474 } 475 /* Fill the QH */ 476 sqh->qh.qh_endp = 477 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 478 sqh->qh.qh_link = 479 htole32(sqh->physaddr | EHCI_LINK_QH); 480 sqh->qh.qh_curqtd = EHCI_NULL; 481 sqh->next = NULL; 482 /* Fill the overlay qTD */ 483 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 484 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 485 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 486 sqh->sqtd = NULL; 487 #ifdef EHCI_DEBUG 488 if (ehcidebug) { 489 ehci_dump_sqh(sqh); 490 } 491 #endif 492 493 /* Point to async list */ 494 sc->sc_async_head = sqh; 495 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 496 497 usb_callout_init(sc->sc_tmo_pcd); 498 usb_callout_init(sc->sc_tmo_intrlist); 499 500 lockinit(&sc->sc_doorbell_lock, PZERO, "ehcidb", 0, 0); 501 502 /* Turn on controller */ 503 EOWRITE4(sc, EHCI_USBCMD, 504 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 505 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 506 EHCI_CMD_ASE | 507 EHCI_CMD_PSE | 508 EHCI_CMD_RS); 509 510 /* Take over port ownership */ 511 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 512 513 for (i = 0; i < 100; i++) { 514 usb_delay_ms(&sc->sc_bus, 1); 515 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 516 if (!hcr) 517 break; 518 } 519 if (hcr) { 520 aprint_error("%s: run timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 521 return (USBD_IOERROR); 522 } 523 524 /* Enable interrupts */ 525 DPRINTFN(1,("ehci_init: enabling\n")); 526 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 527 528 return (USBD_NORMAL_COMPLETION); 529 530 #if 0 531 bad2: 532 ehci_free_sqh(sc, sc->sc_async_head); 533 #endif 534 bad1: 535 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 536 return (err); 537 } 538 539 int 540 ehci_intr(void *v) 541 { 542 ehci_softc_t *sc = v; 543 544 if (sc == NULL || sc->sc_dying) 545 return (0); 546 547 /* If we get an interrupt while polling, then just ignore it. */ 548 if (sc->sc_bus.use_polling) { 549 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 550 551 if (intrs) 552 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 553 #ifdef DIAGNOSTIC 554 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 555 #endif 556 return (0); 557 } 558 559 return (ehci_intr1(sc)); 560 } 561 562 Static int 563 ehci_intr1(ehci_softc_t *sc) 564 { 565 u_int32_t intrs, eintrs; 566 567 DPRINTFN(20,("ehci_intr1: enter\n")); 568 569 /* In case the interrupt occurs before initialization has completed. */ 570 if (sc == NULL) { 571 #ifdef DIAGNOSTIC 572 printf("ehci_intr1: sc == NULL\n"); 573 #endif 574 return (0); 575 } 576 577 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 578 if (!intrs) 579 return (0); 580 581 eintrs = intrs & sc->sc_eintrs; 582 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 583 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 584 (u_int)eintrs)); 585 if (!eintrs) 586 return (0); 587 588 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 589 sc->sc_bus.intr_context++; 590 sc->sc_bus.no_intrs++; 591 if (eintrs & EHCI_STS_IAA) { 592 DPRINTF(("ehci_intr1: door bell\n")); 593 wakeup(&sc->sc_async_head); 594 eintrs &= ~EHCI_STS_IAA; 595 } 596 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 597 DPRINTFN(5,("ehci_intr1: %s %s\n", 598 eintrs & EHCI_STS_INT ? "INT" : "", 599 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 600 usb_schedsoftintr(&sc->sc_bus); 601 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 602 } 603 if (eintrs & EHCI_STS_HSE) { 604 printf("%s: unrecoverable error, controller halted\n", 605 USBDEVNAME(sc->sc_bus.bdev)); 606 /* XXX what else */ 607 } 608 if (eintrs & EHCI_STS_PCD) { 609 ehci_pcd(sc, sc->sc_intrxfer); 610 /* 611 * Disable PCD interrupt for now, because it will be 612 * on until the port has been reset. 613 */ 614 ehci_pcd_able(sc, 0); 615 /* Do not allow RHSC interrupts > 1 per second */ 616 usb_callout(sc->sc_tmo_pcd, hz, ehci_pcd_enable, sc); 617 eintrs &= ~EHCI_STS_PCD; 618 } 619 620 sc->sc_bus.intr_context--; 621 622 if (eintrs != 0) { 623 /* Block unprocessed interrupts. */ 624 sc->sc_eintrs &= ~eintrs; 625 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 626 printf("%s: blocking intrs 0x%x\n", 627 USBDEVNAME(sc->sc_bus.bdev), eintrs); 628 } 629 630 return (1); 631 } 632 633 void 634 ehci_pcd_able(ehci_softc_t *sc, int on) 635 { 636 DPRINTFN(4, ("ehci_pcd_able: on=%d\n", on)); 637 if (on) 638 sc->sc_eintrs |= EHCI_STS_PCD; 639 else 640 sc->sc_eintrs &= ~EHCI_STS_PCD; 641 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 642 } 643 644 void 645 ehci_pcd_enable(void *v_sc) 646 { 647 ehci_softc_t *sc = v_sc; 648 649 ehci_pcd_able(sc, 1); 650 } 651 652 void 653 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 654 { 655 usbd_pipe_handle pipe; 656 u_char *p; 657 int i, m; 658 659 if (xfer == NULL) { 660 /* Just ignore the change. */ 661 return; 662 } 663 664 pipe = xfer->pipe; 665 666 p = KERNADDR(&xfer->dmabuf, 0); 667 m = min(sc->sc_noport, xfer->length * 8 - 1); 668 memset(p, 0, xfer->length); 669 for (i = 1; i <= m; i++) { 670 /* Pick out CHANGE bits from the status reg. */ 671 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 672 p[i/8] |= 1 << (i%8); 673 } 674 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 675 xfer->actlen = xfer->length; 676 xfer->status = USBD_NORMAL_COMPLETION; 677 678 usb_transfer_complete(xfer); 679 } 680 681 void 682 ehci_softintr(void *v) 683 { 684 ehci_softc_t *sc = v; 685 struct ehci_xfer *ex, *nextex; 686 687 DPRINTFN(10,("%s: ehci_softintr (%d)\n", USBDEVNAME(sc->sc_bus.bdev), 688 sc->sc_bus.intr_context)); 689 690 sc->sc_bus.intr_context++; 691 692 /* 693 * The only explanation I can think of for why EHCI is as brain dead 694 * as UHCI interrupt-wise is that Intel was involved in both. 695 * An interrupt just tells us that something is done, we have no 696 * clue what, so we need to scan through all active transfers. :-( 697 */ 698 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 699 nextex = LIST_NEXT(ex, inext); 700 ehci_check_intr(sc, ex); 701 } 702 703 /* Schedule a callout to catch any dropped transactions. */ 704 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 705 !LIST_EMPTY(&sc->sc_intrhead)) 706 usb_callout(sc->sc_tmo_intrlist, hz, 707 ehci_intrlist_timeout, sc); 708 709 #ifdef USB_USE_SOFTINTR 710 if (sc->sc_softwake) { 711 sc->sc_softwake = 0; 712 wakeup(&sc->sc_softwake); 713 } 714 #endif /* USB_USE_SOFTINTR */ 715 716 sc->sc_bus.intr_context--; 717 } 718 719 /* Check for an interrupt. */ 720 void 721 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 722 { 723 ehci_soft_qtd_t *sqtd, *lsqtd; 724 u_int32_t status; 725 726 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 727 728 if (ex->sqtdstart == NULL) { 729 printf("ehci_check_intr: sqtdstart=NULL\n"); 730 return; 731 } 732 lsqtd = ex->sqtdend; 733 #ifdef DIAGNOSTIC 734 if (lsqtd == NULL) { 735 printf("ehci_check_intr: lsqtd==0\n"); 736 return; 737 } 738 #endif 739 /* 740 * If the last TD is still active we need to check whether there 741 * is a an error somewhere in the middle, or whether there was a 742 * short packet (SPD and not ACTIVE). 743 */ 744 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 745 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 746 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 747 status = le32toh(sqtd->qtd.qtd_status); 748 /* If there's an active QTD the xfer isn't done. */ 749 if (status & EHCI_QTD_ACTIVE) 750 break; 751 /* Any kind of error makes the xfer done. */ 752 if (status & EHCI_QTD_HALTED) 753 goto done; 754 /* We want short packets, and it is short: it's done */ 755 if (EHCI_QTD_GET_BYTES(status) != 0) 756 goto done; 757 } 758 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 759 ex, ex->sqtdstart)); 760 return; 761 } 762 done: 763 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 764 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 765 ehci_idone(ex); 766 } 767 768 void 769 ehci_idone(struct ehci_xfer *ex) 770 { 771 usbd_xfer_handle xfer = &ex->xfer; 772 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 773 ehci_soft_qtd_t *sqtd, *lsqtd; 774 u_int32_t status = 0, nstatus = 0; 775 int actlen; 776 777 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 778 #ifdef DIAGNOSTIC 779 { 780 int s = splhigh(); 781 if (ex->isdone) { 782 splx(s); 783 #ifdef EHCI_DEBUG 784 printf("ehci_idone: ex is done!\n "); 785 ehci_dump_exfer(ex); 786 #else 787 printf("ehci_idone: ex=%p is done!\n", ex); 788 #endif 789 return; 790 } 791 ex->isdone = 1; 792 splx(s); 793 } 794 #endif 795 796 if (xfer->status == USBD_CANCELLED || 797 xfer->status == USBD_TIMEOUT) { 798 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 799 return; 800 } 801 802 #ifdef EHCI_DEBUG 803 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 804 if (ehcidebug > 10) 805 ehci_dump_sqtds(ex->sqtdstart); 806 #endif 807 808 /* The transfer is done, compute actual length and status. */ 809 lsqtd = ex->sqtdend; 810 actlen = 0; 811 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd=sqtd->nextqtd) { 812 nstatus = le32toh(sqtd->qtd.qtd_status); 813 if (nstatus & EHCI_QTD_ACTIVE) 814 break; 815 816 status = nstatus; 817 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 818 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 819 } 820 821 /* 822 * If there are left over TDs we need to update the toggle. 823 * The default pipe doesn't need it since control transfers 824 * start the toggle at 0 every time. 825 * For a short transfer we need to update the toggle for the missing 826 * packets within the qTD. 827 */ 828 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 829 xfer->pipe->device->default_pipe != xfer->pipe) { 830 DPRINTFN(2, ("ehci_idone: need toggle update " 831 "status=%08x nstatus=%08x\n", status, nstatus)); 832 #if 0 833 ehci_dump_sqh(epipe->sqh); 834 ehci_dump_sqtds(ex->sqtdstart); 835 #endif 836 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 837 } 838 839 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 840 xfer->length, actlen, status)); 841 xfer->actlen = actlen; 842 if (status & EHCI_QTD_HALTED) { 843 #ifdef EHCI_DEBUG 844 char sbuf[128]; 845 846 bitmask_snprintf((u_int32_t)status, 847 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 848 "\3MISSED\1PINGSTATE", sbuf, sizeof(sbuf)); 849 850 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 851 "status 0x%s\n", 852 xfer->pipe->device->address, 853 xfer->pipe->endpoint->edesc->bEndpointAddress, 854 sbuf)); 855 if (ehcidebug > 2) { 856 ehci_dump_sqh(epipe->sqh); 857 ehci_dump_sqtds(ex->sqtdstart); 858 } 859 #endif 860 /* low&full speed has an extra error flag */ 861 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 862 EHCI_QH_SPEED_HIGH) 863 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 864 else 865 status &= EHCI_QTD_STATERRS; 866 if (status == 0) /* no other errors means a stall */ 867 xfer->status = USBD_STALLED; 868 else 869 xfer->status = USBD_IOERROR; /* more info XXX */ 870 /* XXX need to reset TT on missed microframe */ 871 if (status & EHCI_QTD_MISSEDMICRO) { 872 ehci_softc_t *sc = (ehci_softc_t *) 873 xfer->pipe->device->bus; 874 875 printf("%s: missed microframe, TT reset not " 876 "implemented, hub might be inoperational\n", 877 USBDEVNAME(sc->sc_bus.bdev)); 878 } 879 } else { 880 xfer->status = USBD_NORMAL_COMPLETION; 881 } 882 883 usb_transfer_complete(xfer); 884 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 885 } 886 887 /* 888 * Wait here until controller claims to have an interrupt. 889 * Then call ehci_intr and return. Use timeout to avoid waiting 890 * too long. 891 */ 892 void 893 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 894 { 895 int timo; 896 u_int32_t intrs; 897 898 xfer->status = USBD_IN_PROGRESS; 899 for (timo = xfer->timeout; timo >= 0; timo--) { 900 usb_delay_ms(&sc->sc_bus, 1); 901 if (sc->sc_dying) 902 break; 903 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 904 sc->sc_eintrs; 905 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 906 #ifdef EHCI_DEBUG 907 if (ehcidebug > 15) 908 ehci_dump_regs(sc); 909 #endif 910 if (intrs) { 911 ehci_intr1(sc); 912 if (xfer->status != USBD_IN_PROGRESS) 913 return; 914 } 915 } 916 917 /* Timeout */ 918 DPRINTF(("ehci_waitintr: timeout\n")); 919 xfer->status = USBD_TIMEOUT; 920 usb_transfer_complete(xfer); 921 /* XXX should free TD */ 922 } 923 924 void 925 ehci_poll(struct usbd_bus *bus) 926 { 927 ehci_softc_t *sc = (ehci_softc_t *)bus; 928 #ifdef EHCI_DEBUG 929 static int last; 930 int new; 931 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 932 if (new != last) { 933 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 934 last = new; 935 } 936 #endif 937 938 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 939 ehci_intr1(sc); 940 } 941 942 int 943 ehci_detach(struct ehci_softc *sc, int flags) 944 { 945 int rv = 0; 946 947 if (sc->sc_child != NULL) 948 rv = config_detach(sc->sc_child, flags); 949 950 if (rv != 0) 951 return (rv); 952 953 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 954 usb_uncallout(sc->sc_tmo_pcd, ehci_pcd_enable, sc); 955 956 if (sc->sc_powerhook != NULL) 957 powerhook_disestablish(sc->sc_powerhook); 958 if (sc->sc_shutdownhook != NULL) 959 shutdownhook_disestablish(sc->sc_shutdownhook); 960 961 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 962 963 /* XXX free other data structures XXX */ 964 965 return (rv); 966 } 967 968 969 int 970 ehci_activate(device_ptr_t self, enum devact act) 971 { 972 struct ehci_softc *sc = (struct ehci_softc *)self; 973 int rv = 0; 974 975 switch (act) { 976 case DVACT_ACTIVATE: 977 return (EOPNOTSUPP); 978 979 case DVACT_DEACTIVATE: 980 if (sc->sc_child != NULL) 981 rv = config_deactivate(sc->sc_child); 982 sc->sc_dying = 1; 983 break; 984 } 985 return (rv); 986 } 987 988 /* 989 * Handle suspend/resume. 990 * 991 * We need to switch to polling mode here, because this routine is 992 * called from an interrupt context. This is all right since we 993 * are almost suspended anyway. 994 */ 995 void 996 ehci_power(int why, void *v) 997 { 998 ehci_softc_t *sc = v; 999 u_int32_t cmd, hcr; 1000 int s, i; 1001 1002 #ifdef EHCI_DEBUG 1003 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why)); 1004 if (ehcidebug > 0) 1005 ehci_dump_regs(sc); 1006 #endif 1007 1008 s = splhardusb(); 1009 switch (why) { 1010 case PWR_SUSPEND: 1011 case PWR_STANDBY: 1012 sc->sc_bus.use_polling++; 1013 1014 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1015 1016 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1017 EOWRITE4(sc, EHCI_USBCMD, cmd); 1018 1019 for (i = 0; i < 100; i++) { 1020 hcr = EOREAD4(sc, EHCI_USBSTS) & 1021 (EHCI_STS_ASS | EHCI_STS_PSS); 1022 if (hcr == 0) 1023 break; 1024 1025 usb_delay_ms(&sc->sc_bus, 1); 1026 } 1027 if (hcr != 0) { 1028 printf("%s: reset timeout\n", 1029 USBDEVNAME(sc->sc_bus.bdev)); 1030 } 1031 1032 cmd &= ~EHCI_CMD_RS; 1033 EOWRITE4(sc, EHCI_USBCMD, cmd); 1034 1035 for (i = 0; i < 100; i++) { 1036 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1037 if (hcr == EHCI_STS_HCH) 1038 break; 1039 1040 usb_delay_ms(&sc->sc_bus, 1); 1041 } 1042 if (hcr != EHCI_STS_HCH) { 1043 printf("%s: config timeout\n", 1044 USBDEVNAME(sc->sc_bus.bdev)); 1045 } 1046 1047 sc->sc_bus.use_polling--; 1048 break; 1049 1050 case PWR_RESUME: 1051 sc->sc_bus.use_polling++; 1052 1053 /* restore things in case the bios sucks */ 1054 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1055 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1056 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1057 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1058 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1059 1060 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1061 1062 for (i = 0; i < 100; i++) { 1063 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1064 if (hcr != EHCI_STS_HCH) 1065 break; 1066 1067 usb_delay_ms(&sc->sc_bus, 1); 1068 } 1069 if (hcr == EHCI_STS_HCH) { 1070 printf("%s: config timeout\n", 1071 USBDEVNAME(sc->sc_bus.bdev)); 1072 } 1073 1074 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1075 1076 sc->sc_bus.use_polling--; 1077 break; 1078 case PWR_SOFTSUSPEND: 1079 case PWR_SOFTSTANDBY: 1080 case PWR_SOFTRESUME: 1081 break; 1082 } 1083 splx(s); 1084 1085 #ifdef EHCI_DEBUG 1086 DPRINTF(("ehci_power: sc=%p\n", sc)); 1087 if (ehcidebug > 0) 1088 ehci_dump_regs(sc); 1089 #endif 1090 } 1091 1092 /* 1093 * Shut down the controller when the system is going down. 1094 */ 1095 void 1096 ehci_shutdown(void *v) 1097 { 1098 ehci_softc_t *sc = v; 1099 1100 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1101 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1102 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1103 } 1104 1105 usbd_status 1106 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1107 { 1108 struct ehci_softc *sc = (struct ehci_softc *)bus; 1109 usbd_status err; 1110 1111 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1112 if (err == USBD_NOMEM) 1113 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1114 #ifdef EHCI_DEBUG 1115 if (err) 1116 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1117 #endif 1118 return (err); 1119 } 1120 1121 void 1122 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1123 { 1124 struct ehci_softc *sc = (struct ehci_softc *)bus; 1125 1126 if (dma->block->flags & USB_DMA_RESERVE) { 1127 usb_reserve_freem(&((struct ehci_softc *)bus)->sc_dma_reserve, 1128 dma); 1129 return; 1130 } 1131 usb_freemem(&sc->sc_bus, dma); 1132 } 1133 1134 usbd_xfer_handle 1135 ehci_allocx(struct usbd_bus *bus) 1136 { 1137 struct ehci_softc *sc = (struct ehci_softc *)bus; 1138 usbd_xfer_handle xfer; 1139 1140 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1141 if (xfer != NULL) { 1142 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1143 #ifdef DIAGNOSTIC 1144 if (xfer->busy_free != XFER_FREE) { 1145 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1146 xfer->busy_free); 1147 } 1148 #endif 1149 } else { 1150 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1151 } 1152 if (xfer != NULL) { 1153 memset(xfer, 0, sizeof(struct ehci_xfer)); 1154 #ifdef DIAGNOSTIC 1155 EXFER(xfer)->isdone = 1; 1156 xfer->busy_free = XFER_BUSY; 1157 #endif 1158 } 1159 return (xfer); 1160 } 1161 1162 void 1163 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1164 { 1165 struct ehci_softc *sc = (struct ehci_softc *)bus; 1166 1167 #ifdef DIAGNOSTIC 1168 if (xfer->busy_free != XFER_BUSY) { 1169 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1170 xfer->busy_free); 1171 } 1172 xfer->busy_free = XFER_FREE; 1173 if (!EXFER(xfer)->isdone) { 1174 printf("ehci_freex: !isdone\n"); 1175 } 1176 #endif 1177 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1178 } 1179 1180 Static void 1181 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1182 { 1183 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1184 1185 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1186 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1187 #ifdef USB_DEBUG 1188 if (ehcidebug) 1189 usbd_dump_pipe(pipe); 1190 #endif 1191 epipe->nexttoggle = 0; 1192 } 1193 1194 Static void 1195 ehci_noop(usbd_pipe_handle pipe) 1196 { 1197 } 1198 1199 #ifdef EHCI_DEBUG 1200 void 1201 ehci_dump_regs(ehci_softc_t *sc) 1202 { 1203 int i; 1204 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1205 EOREAD4(sc, EHCI_USBCMD), 1206 EOREAD4(sc, EHCI_USBSTS), 1207 EOREAD4(sc, EHCI_USBINTR)); 1208 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1209 EOREAD4(sc, EHCI_FRINDEX), 1210 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1211 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1212 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1213 for (i = 1; i <= sc->sc_noport; i++) 1214 printf("port %d status=0x%08x\n", i, 1215 EOREAD4(sc, EHCI_PORTSC(i))); 1216 } 1217 1218 /* 1219 * Unused function - this is meant to be called from a kernel 1220 * debugger. 1221 */ 1222 void 1223 ehci_dump() 1224 { 1225 ehci_dump_regs(theehci); 1226 } 1227 1228 void 1229 ehci_dump_link(ehci_link_t link, int type) 1230 { 1231 link = le32toh(link); 1232 printf("0x%08x", link); 1233 if (link & EHCI_LINK_TERMINATE) 1234 printf("<T>"); 1235 else { 1236 printf("<"); 1237 if (type) { 1238 switch (EHCI_LINK_TYPE(link)) { 1239 case EHCI_LINK_ITD: printf("ITD"); break; 1240 case EHCI_LINK_QH: printf("QH"); break; 1241 case EHCI_LINK_SITD: printf("SITD"); break; 1242 case EHCI_LINK_FSTN: printf("FSTN"); break; 1243 } 1244 } 1245 printf(">"); 1246 } 1247 } 1248 1249 void 1250 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1251 { 1252 int i; 1253 u_int32_t stop; 1254 1255 stop = 0; 1256 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1257 ehci_dump_sqtd(sqtd); 1258 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1259 } 1260 if (sqtd) 1261 printf("dump aborted, too many TDs\n"); 1262 } 1263 1264 void 1265 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1266 { 1267 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1268 ehci_dump_qtd(&sqtd->qtd); 1269 } 1270 1271 void 1272 ehci_dump_qtd(ehci_qtd_t *qtd) 1273 { 1274 u_int32_t s; 1275 char sbuf[128]; 1276 1277 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1278 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1279 printf("\n"); 1280 s = le32toh(qtd->qtd_status); 1281 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1282 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1283 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1284 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1285 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1286 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1287 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1288 EHCI_QTD_GET_PID(s), sbuf); 1289 for (s = 0; s < 5; s++) 1290 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1291 } 1292 1293 void 1294 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1295 { 1296 ehci_qh_t *qh = &sqh->qh; 1297 u_int32_t endp, endphub; 1298 1299 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1300 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1301 endp = le32toh(qh->qh_endp); 1302 printf(" endp=0x%08x\n", endp); 1303 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1304 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1305 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1306 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1307 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1308 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1309 EHCI_QH_GET_NRL(endp)); 1310 endphub = le32toh(qh->qh_endphub); 1311 printf(" endphub=0x%08x\n", endphub); 1312 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1313 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1314 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1315 EHCI_QH_GET_MULT(endphub)); 1316 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1317 printf("Overlay qTD:\n"); 1318 ehci_dump_qtd(&qh->qh_qtd); 1319 } 1320 1321 #ifdef DIAGNOSTIC 1322 Static void 1323 ehci_dump_exfer(struct ehci_xfer *ex) 1324 { 1325 printf("ehci_dump_exfer: ex=%p\n", ex); 1326 } 1327 #endif 1328 #endif 1329 1330 usbd_status 1331 ehci_open(usbd_pipe_handle pipe) 1332 { 1333 usbd_device_handle dev = pipe->device; 1334 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 1335 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1336 u_int8_t addr = dev->address; 1337 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1338 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1339 ehci_soft_qh_t *sqh; 1340 usbd_status err; 1341 int s; 1342 int ival, speed, naks; 1343 int hshubaddr, hshubport; 1344 1345 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1346 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1347 1348 if (dev->myhsport) { 1349 hshubaddr = dev->myhsport->parent->address; 1350 hshubport = dev->myhsport->portno; 1351 } else { 1352 hshubaddr = 0; 1353 hshubport = 0; 1354 } 1355 1356 if (sc->sc_dying) 1357 return (USBD_IOERROR); 1358 1359 epipe->nexttoggle = 0; 1360 1361 if (addr == sc->sc_addr) { 1362 switch (ed->bEndpointAddress) { 1363 case USB_CONTROL_ENDPOINT: 1364 pipe->methods = &ehci_root_ctrl_methods; 1365 break; 1366 case UE_DIR_IN | EHCI_INTR_ENDPT: 1367 pipe->methods = &ehci_root_intr_methods; 1368 break; 1369 default: 1370 return (USBD_INVAL); 1371 } 1372 return (USBD_NORMAL_COMPLETION); 1373 } 1374 1375 /* XXX All this stuff is only valid for async. */ 1376 switch (dev->speed) { 1377 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1378 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1379 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1380 default: panic("ehci_open: bad device speed %d", dev->speed); 1381 } 1382 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1383 printf("%s: *** WARNING: opening low/full speed isoc device, " 1384 "this does not work yet.\n", 1385 USBDEVNAME(sc->sc_bus.bdev)); 1386 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1387 hshubaddr, hshubport)); 1388 return USBD_INVAL; 1389 } 1390 1391 naks = 8; /* XXX */ 1392 sqh = ehci_alloc_sqh(sc); 1393 if (sqh == NULL) 1394 return (USBD_NOMEM); 1395 /* qh_link filled when the QH is added */ 1396 sqh->qh.qh_endp = htole32( 1397 EHCI_QH_SET_ADDR(addr) | 1398 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1399 EHCI_QH_SET_EPS(speed) | 1400 EHCI_QH_DTC | 1401 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1402 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1403 EHCI_QH_CTL : 0) | 1404 EHCI_QH_SET_NRL(naks) 1405 ); 1406 sqh->qh.qh_endphub = htole32( 1407 EHCI_QH_SET_MULT(1) | 1408 EHCI_QH_SET_HUBA(hshubaddr) | 1409 EHCI_QH_SET_PORT(hshubport) | 1410 EHCI_QH_SET_CMASK(0x08) | /* XXX */ 1411 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1412 ); 1413 sqh->qh.qh_curqtd = EHCI_NULL; 1414 /* Fill the overlay qTD */ 1415 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1416 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1417 sqh->qh.qh_qtd.qtd_status = htole32(0); 1418 1419 epipe->sqh = sqh; 1420 1421 switch (xfertype) { 1422 case UE_CONTROL: 1423 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1424 0, &epipe->u.ctl.reqdma); 1425 #ifdef EHCI_DEBUG 1426 if (err) 1427 printf("ehci_open: usb_allocmem()=%d\n", err); 1428 #endif 1429 if (err) 1430 goto bad; 1431 pipe->methods = &ehci_device_ctrl_methods; 1432 s = splusb(); 1433 ehci_add_qh(sqh, sc->sc_async_head); 1434 splx(s); 1435 break; 1436 case UE_BULK: 1437 pipe->methods = &ehci_device_bulk_methods; 1438 s = splusb(); 1439 ehci_add_qh(sqh, sc->sc_async_head); 1440 splx(s); 1441 break; 1442 case UE_INTERRUPT: 1443 pipe->methods = &ehci_device_intr_methods; 1444 ival = pipe->interval; 1445 if (ival == USBD_DEFAULT_INTERVAL) { 1446 if (speed == EHCI_QH_SPEED_HIGH) { 1447 if (ed->bInterval > 16) { 1448 /* 1449 * illegal with high-speed, but there 1450 * were documentation bugs in the spec, 1451 * so be generous 1452 */ 1453 ival = 256; 1454 } else 1455 ival = (1 << (ed->bInterval - 1)) / 8; 1456 } else 1457 ival = ed->bInterval; 1458 } 1459 err = ehci_device_setintr(sc, sqh, ival); 1460 if (err) 1461 goto bad; 1462 break; 1463 case UE_ISOCHRONOUS: 1464 pipe->methods = &ehci_device_isoc_methods; 1465 /* FALLTHROUGH */ 1466 default: 1467 err = USBD_INVAL; 1468 goto bad; 1469 } 1470 return (USBD_NORMAL_COMPLETION); 1471 1472 bad: 1473 ehci_free_sqh(sc, sqh); 1474 return (err); 1475 } 1476 1477 /* 1478 * Add an ED to the schedule. Called at splusb(). 1479 */ 1480 void 1481 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1482 { 1483 SPLUSBCHECK; 1484 1485 sqh->next = head->next; 1486 sqh->qh.qh_link = head->qh.qh_link; 1487 head->next = sqh; 1488 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1489 1490 #ifdef EHCI_DEBUG 1491 if (ehcidebug > 5) { 1492 printf("ehci_add_qh:\n"); 1493 ehci_dump_sqh(sqh); 1494 } 1495 #endif 1496 } 1497 1498 /* 1499 * Remove an ED from the schedule. Called at splusb(). 1500 */ 1501 void 1502 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1503 { 1504 ehci_soft_qh_t *p; 1505 1506 SPLUSBCHECK; 1507 /* XXX */ 1508 for (p = head; p != NULL && p->next != sqh; p = p->next) 1509 ; 1510 if (p == NULL) 1511 panic("ehci_rem_qh: ED not found"); 1512 p->next = sqh->next; 1513 p->qh.qh_link = sqh->qh.qh_link; 1514 1515 ehci_sync_hc(sc); 1516 } 1517 1518 void 1519 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1520 { 1521 int i; 1522 u_int32_t status; 1523 1524 /* Save toggle bit and ping status. */ 1525 status = sqh->qh.qh_qtd.qtd_status & 1526 htole32(EHCI_QTD_TOGGLE_MASK | 1527 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1528 /* Set HALTED to make hw leave it alone. */ 1529 sqh->qh.qh_qtd.qtd_status = 1530 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1531 sqh->qh.qh_curqtd = 0; 1532 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1533 sqh->qh.qh_qtd.qtd_altnext = 0; 1534 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1535 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1536 sqh->sqtd = sqtd; 1537 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1538 sqh->qh.qh_qtd.qtd_status = status; 1539 } 1540 1541 /* 1542 * Ensure that the HC has released all references to the QH. We do this 1543 * by asking for a Async Advance Doorbell interrupt and then we wait for 1544 * the interrupt. 1545 * To make this easier we first obtain exclusive use of the doorbell. 1546 */ 1547 void 1548 ehci_sync_hc(ehci_softc_t *sc) 1549 { 1550 int s, error; 1551 1552 if (sc->sc_dying) { 1553 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1554 return; 1555 } 1556 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1557 usb_lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE, NULL); /* get doorbell */ 1558 s = splhardusb(); 1559 /* ask for doorbell */ 1560 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1561 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1562 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1563 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1564 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1565 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1566 splx(s); 1567 usb_lockmgr(&sc->sc_doorbell_lock, LK_RELEASE, NULL); /* release doorbell */ 1568 #ifdef DIAGNOSTIC 1569 if (error) 1570 printf("ehci_sync_hc: tsleep() = %d\n", error); 1571 #endif 1572 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1573 } 1574 1575 /***********/ 1576 1577 /* 1578 * Data structures and routines to emulate the root hub. 1579 */ 1580 Static usb_device_descriptor_t ehci_devd = { 1581 USB_DEVICE_DESCRIPTOR_SIZE, 1582 UDESC_DEVICE, /* type */ 1583 {0x00, 0x02}, /* USB version */ 1584 UDCLASS_HUB, /* class */ 1585 UDSUBCLASS_HUB, /* subclass */ 1586 UDPROTO_HSHUBSTT, /* protocol */ 1587 64, /* max packet */ 1588 {0},{0},{0x00,0x01}, /* device id */ 1589 1,2,0, /* string indicies */ 1590 1 /* # of configurations */ 1591 }; 1592 1593 Static usb_device_qualifier_t ehci_odevd = { 1594 USB_DEVICE_DESCRIPTOR_SIZE, 1595 UDESC_DEVICE_QUALIFIER, /* type */ 1596 {0x00, 0x02}, /* USB version */ 1597 UDCLASS_HUB, /* class */ 1598 UDSUBCLASS_HUB, /* subclass */ 1599 UDPROTO_FSHUB, /* protocol */ 1600 64, /* max packet */ 1601 1, /* # of configurations */ 1602 0 1603 }; 1604 1605 Static usb_config_descriptor_t ehci_confd = { 1606 USB_CONFIG_DESCRIPTOR_SIZE, 1607 UDESC_CONFIG, 1608 {USB_CONFIG_DESCRIPTOR_SIZE + 1609 USB_INTERFACE_DESCRIPTOR_SIZE + 1610 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1611 1, 1612 1, 1613 0, 1614 UC_SELF_POWERED, 1615 0 /* max power */ 1616 }; 1617 1618 Static usb_interface_descriptor_t ehci_ifcd = { 1619 USB_INTERFACE_DESCRIPTOR_SIZE, 1620 UDESC_INTERFACE, 1621 0, 1622 0, 1623 1, 1624 UICLASS_HUB, 1625 UISUBCLASS_HUB, 1626 UIPROTO_HSHUBSTT, 1627 0 1628 }; 1629 1630 Static usb_endpoint_descriptor_t ehci_endpd = { 1631 USB_ENDPOINT_DESCRIPTOR_SIZE, 1632 UDESC_ENDPOINT, 1633 UE_DIR_IN | EHCI_INTR_ENDPT, 1634 UE_INTERRUPT, 1635 {8, 0}, /* max packet */ 1636 12 1637 }; 1638 1639 Static usb_hub_descriptor_t ehci_hubd = { 1640 USB_HUB_DESCRIPTOR_SIZE, 1641 UDESC_HUB, 1642 0, 1643 {0,0}, 1644 0, 1645 0, 1646 {""}, 1647 {""}, 1648 }; 1649 1650 Static int 1651 ehci_str(usb_string_descriptor_t *p, int l, const char *s) 1652 { 1653 int i; 1654 1655 if (l == 0) 1656 return (0); 1657 p->bLength = 2 * strlen(s) + 2; 1658 if (l == 1) 1659 return (1); 1660 p->bDescriptorType = UDESC_STRING; 1661 l -= 2; 1662 for (i = 0; s[i] && l > 1; i++, l -= 2) 1663 USETW2(p->bString[i], 0, s[i]); 1664 return (2*i+2); 1665 } 1666 1667 /* 1668 * Simulate a hardware hub by handling all the necessary requests. 1669 */ 1670 Static usbd_status 1671 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1672 { 1673 usbd_status err; 1674 1675 /* Insert last in queue. */ 1676 err = usb_insert_transfer(xfer); 1677 if (err) 1678 return (err); 1679 1680 /* Pipe isn't running, start first */ 1681 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1682 } 1683 1684 Static usbd_status 1685 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1686 { 1687 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 1688 usb_device_request_t *req; 1689 void *buf = NULL; 1690 int port, i; 1691 int s, len, value, index, l, totlen = 0; 1692 usb_port_status_t ps; 1693 usb_hub_descriptor_t hubd; 1694 usbd_status err; 1695 u_int32_t v; 1696 1697 if (sc->sc_dying) 1698 return (USBD_IOERROR); 1699 1700 #ifdef DIAGNOSTIC 1701 if (!(xfer->rqflags & URQ_REQUEST)) 1702 /* XXX panic */ 1703 return (USBD_INVAL); 1704 #endif 1705 req = &xfer->request; 1706 1707 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1708 req->bmRequestType, req->bRequest)); 1709 1710 len = UGETW(req->wLength); 1711 value = UGETW(req->wValue); 1712 index = UGETW(req->wIndex); 1713 1714 if (len != 0) 1715 buf = KERNADDR(&xfer->dmabuf, 0); 1716 1717 #define C(x,y) ((x) | ((y) << 8)) 1718 switch(C(req->bRequest, req->bmRequestType)) { 1719 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1720 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1721 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1722 /* 1723 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1724 * for the integrated root hub. 1725 */ 1726 break; 1727 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1728 if (len > 0) { 1729 *(u_int8_t *)buf = sc->sc_conf; 1730 totlen = 1; 1731 } 1732 break; 1733 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1734 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 1735 if (len == 0) 1736 break; 1737 switch(value >> 8) { 1738 case UDESC_DEVICE: 1739 if ((value & 0xff) != 0) { 1740 err = USBD_IOERROR; 1741 goto ret; 1742 } 1743 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1744 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1745 memcpy(buf, &ehci_devd, l); 1746 break; 1747 /* 1748 * We can't really operate at another speed, but the spec says 1749 * we need this descriptor. 1750 */ 1751 case UDESC_DEVICE_QUALIFIER: 1752 if ((value & 0xff) != 0) { 1753 err = USBD_IOERROR; 1754 goto ret; 1755 } 1756 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1757 memcpy(buf, &ehci_odevd, l); 1758 break; 1759 /* 1760 * We can't really operate at another speed, but the spec says 1761 * we need this descriptor. 1762 */ 1763 case UDESC_OTHER_SPEED_CONFIGURATION: 1764 case UDESC_CONFIG: 1765 if ((value & 0xff) != 0) { 1766 err = USBD_IOERROR; 1767 goto ret; 1768 } 1769 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1770 memcpy(buf, &ehci_confd, l); 1771 ((usb_config_descriptor_t *)buf)->bDescriptorType = 1772 value >> 8; 1773 buf = (char *)buf + l; 1774 len -= l; 1775 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1776 totlen += l; 1777 memcpy(buf, &ehci_ifcd, l); 1778 buf = (char *)buf + l; 1779 len -= l; 1780 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1781 totlen += l; 1782 memcpy(buf, &ehci_endpd, l); 1783 break; 1784 case UDESC_STRING: 1785 *(u_int8_t *)buf = 0; 1786 totlen = 1; 1787 switch (value & 0xff) { 1788 case 0: /* Language table */ 1789 totlen = ehci_str(buf, len, "\001"); 1790 break; 1791 case 1: /* Vendor */ 1792 totlen = ehci_str(buf, len, sc->sc_vendor); 1793 break; 1794 case 2: /* Product */ 1795 totlen = ehci_str(buf, len, "EHCI root hub"); 1796 break; 1797 } 1798 break; 1799 default: 1800 err = USBD_IOERROR; 1801 goto ret; 1802 } 1803 break; 1804 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1805 if (len > 0) { 1806 *(u_int8_t *)buf = 0; 1807 totlen = 1; 1808 } 1809 break; 1810 case C(UR_GET_STATUS, UT_READ_DEVICE): 1811 if (len > 1) { 1812 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1813 totlen = 2; 1814 } 1815 break; 1816 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1817 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1818 if (len > 1) { 1819 USETW(((usb_status_t *)buf)->wStatus, 0); 1820 totlen = 2; 1821 } 1822 break; 1823 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1824 if (value >= USB_MAX_DEVICES) { 1825 err = USBD_IOERROR; 1826 goto ret; 1827 } 1828 sc->sc_addr = value; 1829 break; 1830 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1831 if (value != 0 && value != 1) { 1832 err = USBD_IOERROR; 1833 goto ret; 1834 } 1835 sc->sc_conf = value; 1836 break; 1837 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1838 break; 1839 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1840 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1841 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1842 err = USBD_IOERROR; 1843 goto ret; 1844 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1845 break; 1846 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1847 break; 1848 /* Hub requests */ 1849 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1850 break; 1851 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1852 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 1853 "port=%d feature=%d\n", 1854 index, value)); 1855 if (index < 1 || index > sc->sc_noport) { 1856 err = USBD_IOERROR; 1857 goto ret; 1858 } 1859 port = EHCI_PORTSC(index); 1860 v = EOREAD4(sc, port); 1861 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 1862 v &= ~EHCI_PS_CLEAR; 1863 switch(value) { 1864 case UHF_PORT_ENABLE: 1865 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 1866 break; 1867 case UHF_PORT_SUSPEND: 1868 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 1869 break; 1870 case UHF_PORT_POWER: 1871 if (sc->sc_hasppc) 1872 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 1873 break; 1874 case UHF_PORT_TEST: 1875 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 1876 "%d\n", index)); 1877 break; 1878 case UHF_PORT_INDICATOR: 1879 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 1880 "%d\n", index)); 1881 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 1882 break; 1883 case UHF_C_PORT_CONNECTION: 1884 EOWRITE4(sc, port, v | EHCI_PS_CSC); 1885 break; 1886 case UHF_C_PORT_ENABLE: 1887 EOWRITE4(sc, port, v | EHCI_PS_PEC); 1888 break; 1889 case UHF_C_PORT_SUSPEND: 1890 /* how? */ 1891 break; 1892 case UHF_C_PORT_OVER_CURRENT: 1893 EOWRITE4(sc, port, v | EHCI_PS_OCC); 1894 break; 1895 case UHF_C_PORT_RESET: 1896 sc->sc_isreset[index] = 0; 1897 break; 1898 default: 1899 err = USBD_IOERROR; 1900 goto ret; 1901 } 1902 #if 0 1903 switch(value) { 1904 case UHF_C_PORT_CONNECTION: 1905 case UHF_C_PORT_ENABLE: 1906 case UHF_C_PORT_SUSPEND: 1907 case UHF_C_PORT_OVER_CURRENT: 1908 case UHF_C_PORT_RESET: 1909 /* Enable RHSC interrupt if condition is cleared. */ 1910 if ((OREAD4(sc, port) >> 16) == 0) 1911 ehci_pcd_able(sc, 1); 1912 break; 1913 default: 1914 break; 1915 } 1916 #endif 1917 break; 1918 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1919 if (len == 0) 1920 break; 1921 if ((value & 0xff) != 0) { 1922 err = USBD_IOERROR; 1923 goto ret; 1924 } 1925 hubd = ehci_hubd; 1926 hubd.bNbrPorts = sc->sc_noport; 1927 v = EOREAD4(sc, EHCI_HCSPARAMS); 1928 USETW(hubd.wHubCharacteristics, 1929 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 1930 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 1931 ? UHD_PORT_IND : 0); 1932 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 1933 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 1934 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 1935 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 1936 l = min(len, hubd.bDescLength); 1937 totlen = l; 1938 memcpy(buf, &hubd, l); 1939 break; 1940 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1941 if (len != 4) { 1942 err = USBD_IOERROR; 1943 goto ret; 1944 } 1945 memset(buf, 0, len); /* ? XXX */ 1946 totlen = len; 1947 break; 1948 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1949 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 1950 index)); 1951 if (index < 1 || index > sc->sc_noport) { 1952 err = USBD_IOERROR; 1953 goto ret; 1954 } 1955 if (len != 4) { 1956 err = USBD_IOERROR; 1957 goto ret; 1958 } 1959 v = EOREAD4(sc, EHCI_PORTSC(index)); 1960 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 1961 v)); 1962 i = UPS_HIGH_SPEED; 1963 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 1964 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 1965 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 1966 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 1967 if (v & EHCI_PS_PR) i |= UPS_RESET; 1968 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 1969 USETW(ps.wPortStatus, i); 1970 i = 0; 1971 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 1972 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 1973 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 1974 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 1975 USETW(ps.wPortChange, i); 1976 l = min(len, sizeof ps); 1977 memcpy(buf, &ps, l); 1978 totlen = l; 1979 break; 1980 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1981 err = USBD_IOERROR; 1982 goto ret; 1983 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1984 break; 1985 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1986 if (index < 1 || index > sc->sc_noport) { 1987 err = USBD_IOERROR; 1988 goto ret; 1989 } 1990 port = EHCI_PORTSC(index); 1991 v = EOREAD4(sc, port); 1992 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 1993 v &= ~EHCI_PS_CLEAR; 1994 switch(value) { 1995 case UHF_PORT_ENABLE: 1996 EOWRITE4(sc, port, v | EHCI_PS_PE); 1997 break; 1998 case UHF_PORT_SUSPEND: 1999 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2000 break; 2001 case UHF_PORT_RESET: 2002 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2003 index)); 2004 if (EHCI_PS_IS_LOWSPEED(v)) { 2005 /* Low speed device, give up ownership. */ 2006 ehci_disown(sc, index, 1); 2007 break; 2008 } 2009 /* Start reset sequence. */ 2010 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2011 EOWRITE4(sc, port, v | EHCI_PS_PR); 2012 /* Wait for reset to complete. */ 2013 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2014 if (sc->sc_dying) { 2015 err = USBD_IOERROR; 2016 goto ret; 2017 } 2018 /* Terminate reset sequence. */ 2019 EOWRITE4(sc, port, v); 2020 /* Wait for HC to complete reset. */ 2021 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2022 if (sc->sc_dying) { 2023 err = USBD_IOERROR; 2024 goto ret; 2025 } 2026 v = EOREAD4(sc, port); 2027 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2028 if (v & EHCI_PS_PR) { 2029 printf("%s: port reset timeout\n", 2030 USBDEVNAME(sc->sc_bus.bdev)); 2031 return (USBD_TIMEOUT); 2032 } 2033 if (!(v & EHCI_PS_PE)) { 2034 /* Not a high speed device, give up ownership.*/ 2035 ehci_disown(sc, index, 0); 2036 break; 2037 } 2038 sc->sc_isreset[index] = 1; 2039 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2040 index, v)); 2041 break; 2042 case UHF_PORT_POWER: 2043 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2044 "%d (has PPC = %d)\n", index, 2045 sc->sc_hasppc)); 2046 if (sc->sc_hasppc) 2047 EOWRITE4(sc, port, v | EHCI_PS_PP); 2048 break; 2049 case UHF_PORT_TEST: 2050 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2051 "%d\n", index)); 2052 break; 2053 case UHF_PORT_INDICATOR: 2054 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2055 "%d\n", index)); 2056 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2057 break; 2058 default: 2059 err = USBD_IOERROR; 2060 goto ret; 2061 } 2062 break; 2063 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2064 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2065 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2066 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2067 break; 2068 default: 2069 err = USBD_IOERROR; 2070 goto ret; 2071 } 2072 xfer->actlen = totlen; 2073 err = USBD_NORMAL_COMPLETION; 2074 ret: 2075 xfer->status = err; 2076 s = splusb(); 2077 usb_transfer_complete(xfer); 2078 splx(s); 2079 return (USBD_IN_PROGRESS); 2080 } 2081 2082 void 2083 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2084 { 2085 int port; 2086 u_int32_t v; 2087 2088 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2089 #ifdef DIAGNOSTIC 2090 if (sc->sc_npcomp != 0) { 2091 int i = (index-1) / sc->sc_npcomp; 2092 if (i >= sc->sc_ncomp) 2093 printf("%s: strange port\n", 2094 USBDEVNAME(sc->sc_bus.bdev)); 2095 else 2096 printf("%s: handing over %s speed device on " 2097 "port %d to %s\n", 2098 USBDEVNAME(sc->sc_bus.bdev), 2099 lowspeed ? "low" : "full", 2100 index, USBDEVNAME(sc->sc_comps[i]->bdev)); 2101 } else { 2102 printf("%s: npcomp == 0\n", USBDEVNAME(sc->sc_bus.bdev)); 2103 } 2104 #endif 2105 port = EHCI_PORTSC(index); 2106 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2107 EOWRITE4(sc, port, v | EHCI_PS_PO); 2108 } 2109 2110 /* Abort a root control request. */ 2111 Static void 2112 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2113 { 2114 /* Nothing to do, all transfers are synchronous. */ 2115 } 2116 2117 /* Close the root pipe. */ 2118 Static void 2119 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2120 { 2121 DPRINTF(("ehci_root_ctrl_close\n")); 2122 /* Nothing to do. */ 2123 } 2124 2125 void 2126 ehci_root_intr_done(usbd_xfer_handle xfer) 2127 { 2128 xfer->hcpriv = NULL; 2129 } 2130 2131 Static usbd_status 2132 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2133 { 2134 usbd_status err; 2135 2136 /* Insert last in queue. */ 2137 err = usb_insert_transfer(xfer); 2138 if (err) 2139 return (err); 2140 2141 /* Pipe isn't running, start first */ 2142 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2143 } 2144 2145 Static usbd_status 2146 ehci_root_intr_start(usbd_xfer_handle xfer) 2147 { 2148 usbd_pipe_handle pipe = xfer->pipe; 2149 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2150 2151 if (sc->sc_dying) 2152 return (USBD_IOERROR); 2153 2154 sc->sc_intrxfer = xfer; 2155 2156 return (USBD_IN_PROGRESS); 2157 } 2158 2159 /* Abort a root interrupt request. */ 2160 Static void 2161 ehci_root_intr_abort(usbd_xfer_handle xfer) 2162 { 2163 int s; 2164 2165 if (xfer->pipe->intrxfer == xfer) { 2166 DPRINTF(("ehci_root_intr_abort: remove\n")); 2167 xfer->pipe->intrxfer = NULL; 2168 } 2169 xfer->status = USBD_CANCELLED; 2170 s = splusb(); 2171 usb_transfer_complete(xfer); 2172 splx(s); 2173 } 2174 2175 /* Close the root pipe. */ 2176 Static void 2177 ehci_root_intr_close(usbd_pipe_handle pipe) 2178 { 2179 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2180 2181 DPRINTF(("ehci_root_intr_close\n")); 2182 2183 sc->sc_intrxfer = NULL; 2184 } 2185 2186 void 2187 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2188 { 2189 xfer->hcpriv = NULL; 2190 } 2191 2192 /************************/ 2193 2194 ehci_soft_qh_t * 2195 ehci_alloc_sqh(ehci_softc_t *sc) 2196 { 2197 ehci_soft_qh_t *sqh; 2198 usbd_status err; 2199 int i, offs; 2200 usb_dma_t dma; 2201 2202 if (sc->sc_freeqhs == NULL) { 2203 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2204 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2205 EHCI_PAGE_SIZE, &dma); 2206 #ifdef EHCI_DEBUG 2207 if (err) 2208 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2209 #endif 2210 if (err) 2211 return (NULL); 2212 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2213 offs = i * EHCI_SQH_SIZE; 2214 sqh = KERNADDR(&dma, offs); 2215 sqh->physaddr = DMAADDR(&dma, offs); 2216 sqh->next = sc->sc_freeqhs; 2217 sc->sc_freeqhs = sqh; 2218 } 2219 } 2220 sqh = sc->sc_freeqhs; 2221 sc->sc_freeqhs = sqh->next; 2222 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2223 sqh->next = NULL; 2224 return (sqh); 2225 } 2226 2227 void 2228 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2229 { 2230 sqh->next = sc->sc_freeqhs; 2231 sc->sc_freeqhs = sqh; 2232 } 2233 2234 ehci_soft_qtd_t * 2235 ehci_alloc_sqtd(ehci_softc_t *sc) 2236 { 2237 ehci_soft_qtd_t *sqtd; 2238 usbd_status err; 2239 int i, offs; 2240 usb_dma_t dma; 2241 int s; 2242 2243 if (sc->sc_freeqtds == NULL) { 2244 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2245 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2246 EHCI_PAGE_SIZE, &dma); 2247 #ifdef EHCI_DEBUG 2248 if (err) 2249 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2250 #endif 2251 if (err) 2252 return (NULL); 2253 s = splusb(); 2254 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2255 offs = i * EHCI_SQTD_SIZE; 2256 sqtd = KERNADDR(&dma, offs); 2257 sqtd->physaddr = DMAADDR(&dma, offs); 2258 sqtd->nextqtd = sc->sc_freeqtds; 2259 sc->sc_freeqtds = sqtd; 2260 } 2261 splx(s); 2262 } 2263 2264 s = splusb(); 2265 sqtd = sc->sc_freeqtds; 2266 sc->sc_freeqtds = sqtd->nextqtd; 2267 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2268 sqtd->nextqtd = NULL; 2269 sqtd->xfer = NULL; 2270 splx(s); 2271 2272 return (sqtd); 2273 } 2274 2275 void 2276 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2277 { 2278 int s; 2279 2280 s = splusb(); 2281 sqtd->nextqtd = sc->sc_freeqtds; 2282 sc->sc_freeqtds = sqtd; 2283 splx(s); 2284 } 2285 2286 usbd_status 2287 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2288 int alen, int rd, usbd_xfer_handle xfer, 2289 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2290 { 2291 ehci_soft_qtd_t *next, *cur; 2292 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2293 u_int32_t qtdstatus; 2294 int len, curlen, mps; 2295 int i, tog; 2296 usb_dma_t *dma = &xfer->dmabuf; 2297 u_int16_t flags = xfer->flags; 2298 2299 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2300 2301 len = alen; 2302 dataphys = DMAADDR(dma, 0); 2303 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2304 qtdstatus = EHCI_QTD_ACTIVE | 2305 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2306 EHCI_QTD_SET_CERR(3) 2307 /* IOC set below */ 2308 /* BYTES set below */ 2309 ; 2310 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2311 tog = epipe->nexttoggle; 2312 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2313 2314 cur = ehci_alloc_sqtd(sc); 2315 *sp = cur; 2316 if (cur == NULL) 2317 goto nomem; 2318 for (;;) { 2319 dataphyspage = EHCI_PAGE(dataphys); 2320 /* The EHCI hardware can handle at most 5 pages. */ 2321 if (dataphyslastpage - dataphyspage < 2322 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2323 /* we can handle it in this QTD */ 2324 curlen = len; 2325 } else { 2326 /* must use multiple TDs, fill as much as possible. */ 2327 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2328 EHCI_PAGE_OFFSET(dataphys); 2329 #ifdef DIAGNOSTIC 2330 if (curlen > len) { 2331 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2332 "len=0x%x offs=0x%x\n", curlen, len, 2333 EHCI_PAGE_OFFSET(dataphys)); 2334 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2335 dataphyslastpage, dataphyspage, 2336 dataphys); 2337 curlen = len; 2338 } 2339 #endif 2340 /* the length must be a multiple of the max size */ 2341 curlen -= curlen % mps; 2342 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2343 "curlen=%d\n", curlen)); 2344 #ifdef DIAGNOSTIC 2345 if (curlen == 0) 2346 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2347 #endif 2348 } 2349 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2350 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2351 dataphys, dataphyslastpage, 2352 len, curlen)); 2353 len -= curlen; 2354 2355 /* 2356 * Allocate another transfer if there's more data left, 2357 * or if force last short transfer flag is set and we're 2358 * allocating a multiple of the max packet size. 2359 */ 2360 if (len != 0 || 2361 ((curlen % mps) == 0 && !rd && curlen != 0 && 2362 (flags & USBD_FORCE_SHORT_XFER))) { 2363 next = ehci_alloc_sqtd(sc); 2364 if (next == NULL) 2365 goto nomem; 2366 nextphys = htole32(next->physaddr); 2367 } else { 2368 next = NULL; 2369 nextphys = EHCI_NULL; 2370 } 2371 2372 for (i = 0; i * EHCI_PAGE_SIZE < 2373 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2374 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2375 if (i != 0) /* use offset only in first buffer */ 2376 a = EHCI_PAGE(a); 2377 cur->qtd.qtd_buffer[i] = htole32(a); 2378 cur->qtd.qtd_buffer_hi[i] = 0; 2379 #ifdef DIAGNOSTIC 2380 if (i >= EHCI_QTD_NBUFFERS) { 2381 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2382 goto nomem; 2383 } 2384 #endif 2385 } 2386 cur->nextqtd = next; 2387 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2388 cur->qtd.qtd_status = 2389 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2390 cur->xfer = xfer; 2391 cur->len = curlen; 2392 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2393 dataphys, dataphys + curlen)); 2394 /* adjust the toggle based on the number of packets in this 2395 qtd */ 2396 if (((curlen + mps - 1) / mps) & 1) { 2397 tog ^= 1; 2398 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2399 } 2400 if (next == NULL) 2401 break; 2402 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2403 dataphys += curlen; 2404 cur = next; 2405 } 2406 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2407 *ep = cur; 2408 epipe->nexttoggle = tog; 2409 2410 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2411 *sp, *ep)); 2412 2413 return (USBD_NORMAL_COMPLETION); 2414 2415 nomem: 2416 /* XXX free chain */ 2417 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2418 return (USBD_NOMEM); 2419 } 2420 2421 Static void 2422 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2423 ehci_soft_qtd_t *sqtdend) 2424 { 2425 ehci_soft_qtd_t *p; 2426 int i; 2427 2428 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2429 sqtd, sqtdend)); 2430 2431 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2432 p = sqtd->nextqtd; 2433 ehci_free_sqtd(sc, sqtd); 2434 } 2435 } 2436 2437 /****************/ 2438 2439 /* 2440 * Close a reqular pipe. 2441 * Assumes that there are no pending transactions. 2442 */ 2443 void 2444 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2445 { 2446 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2447 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2448 ehci_soft_qh_t *sqh = epipe->sqh; 2449 int s; 2450 2451 s = splusb(); 2452 ehci_rem_qh(sc, sqh, head); 2453 splx(s); 2454 ehci_free_sqh(sc, epipe->sqh); 2455 } 2456 2457 /* 2458 * Abort a device request. 2459 * If this routine is called at splusb() it guarantees that the request 2460 * will be removed from the hardware scheduling and that the callback 2461 * for it will be called with USBD_CANCELLED status. 2462 * It's impossible to guarantee that the requested transfer will not 2463 * have happened since the hardware runs concurrently. 2464 * If the transaction has already happened we rely on the ordinary 2465 * interrupt processing to process it. 2466 * XXX This is most probably wrong. 2467 */ 2468 void 2469 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2470 { 2471 #define exfer EXFER(xfer) 2472 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2473 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2474 ehci_soft_qh_t *sqh = epipe->sqh; 2475 ehci_soft_qtd_t *sqtd; 2476 ehci_physaddr_t cur; 2477 u_int32_t qhstatus; 2478 int s; 2479 int hit; 2480 int wake; 2481 2482 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2483 2484 if (sc->sc_dying) { 2485 /* If we're dying, just do the software part. */ 2486 s = splusb(); 2487 xfer->status = status; /* make software ignore it */ 2488 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2489 usb_transfer_complete(xfer); 2490 splx(s); 2491 return; 2492 } 2493 2494 if (xfer->device->bus->intr_context || !curproc) 2495 panic("ehci_abort_xfer: not in process context"); 2496 2497 /* 2498 * If an abort is already in progress then just wait for it to 2499 * complete and return. 2500 */ 2501 if (xfer->hcflags & UXFER_ABORTING) { 2502 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2503 #ifdef DIAGNOSTIC 2504 if (status == USBD_TIMEOUT) 2505 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2506 #endif 2507 /* Override the status which might be USBD_TIMEOUT. */ 2508 xfer->status = status; 2509 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2510 xfer->hcflags |= UXFER_ABORTWAIT; 2511 while (xfer->hcflags & UXFER_ABORTING) 2512 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2513 return; 2514 } 2515 xfer->hcflags |= UXFER_ABORTING; 2516 2517 /* 2518 * Step 1: Make interrupt routine and hardware ignore xfer. 2519 */ 2520 s = splusb(); 2521 xfer->status = status; /* make software ignore it */ 2522 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2523 qhstatus = sqh->qh.qh_qtd.qtd_status; 2524 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2525 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2526 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2527 if (sqtd == exfer->sqtdend) 2528 break; 2529 } 2530 splx(s); 2531 2532 /* 2533 * Step 2: Wait until we know hardware has finished any possible 2534 * use of the xfer. Also make sure the soft interrupt routine 2535 * has run. 2536 */ 2537 ehci_sync_hc(sc); 2538 s = splusb(); 2539 #ifdef USB_USE_SOFTINTR 2540 sc->sc_softwake = 1; 2541 #endif /* USB_USE_SOFTINTR */ 2542 usb_schedsoftintr(&sc->sc_bus); 2543 #ifdef USB_USE_SOFTINTR 2544 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2545 #endif /* USB_USE_SOFTINTR */ 2546 splx(s); 2547 2548 /* 2549 * Step 3: Remove any vestiges of the xfer from the hardware. 2550 * The complication here is that the hardware may have executed 2551 * beyond the xfer we're trying to abort. So as we're scanning 2552 * the TDs of this xfer we check if the hardware points to 2553 * any of them. 2554 */ 2555 s = splusb(); /* XXX why? */ 2556 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2557 hit = 0; 2558 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2559 hit |= cur == sqtd->physaddr; 2560 if (sqtd == exfer->sqtdend) 2561 break; 2562 } 2563 sqtd = sqtd->nextqtd; 2564 /* Zap curqtd register if hardware pointed inside the xfer. */ 2565 if (hit && sqtd != NULL) { 2566 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 2567 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 2568 sqh->qh.qh_qtd.qtd_status = qhstatus; 2569 } else { 2570 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2571 } 2572 2573 /* 2574 * Step 4: Execute callback. 2575 */ 2576 #ifdef DIAGNOSTIC 2577 exfer->isdone = 1; 2578 #endif 2579 wake = xfer->hcflags & UXFER_ABORTWAIT; 2580 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2581 usb_transfer_complete(xfer); 2582 if (wake) 2583 wakeup(&xfer->hcflags); 2584 2585 splx(s); 2586 #undef exfer 2587 } 2588 2589 void 2590 ehci_timeout(void *addr) 2591 { 2592 struct ehci_xfer *exfer = addr; 2593 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 2594 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2595 2596 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 2597 #ifdef USB_DEBUG 2598 if (ehcidebug > 1) 2599 usbd_dump_pipe(exfer->xfer.pipe); 2600 #endif 2601 2602 if (sc->sc_dying) { 2603 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 2604 return; 2605 } 2606 2607 /* Execute the abort in a process context. */ 2608 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 2609 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 2610 USB_TASKQ_HC); 2611 } 2612 2613 void 2614 ehci_timeout_task(void *addr) 2615 { 2616 usbd_xfer_handle xfer = addr; 2617 int s; 2618 2619 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 2620 2621 s = splusb(); 2622 ehci_abort_xfer(xfer, USBD_TIMEOUT); 2623 splx(s); 2624 } 2625 2626 /************************/ 2627 2628 Static usbd_status 2629 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 2630 { 2631 usbd_status err; 2632 2633 /* Insert last in queue. */ 2634 err = usb_insert_transfer(xfer); 2635 if (err) 2636 return (err); 2637 2638 /* Pipe isn't running, start first */ 2639 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2640 } 2641 2642 Static usbd_status 2643 ehci_device_ctrl_start(usbd_xfer_handle xfer) 2644 { 2645 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2646 usbd_status err; 2647 2648 if (sc->sc_dying) 2649 return (USBD_IOERROR); 2650 2651 #ifdef DIAGNOSTIC 2652 if (!(xfer->rqflags & URQ_REQUEST)) { 2653 /* XXX panic */ 2654 printf("ehci_device_ctrl_transfer: not a request\n"); 2655 return (USBD_INVAL); 2656 } 2657 #endif 2658 2659 err = ehci_device_request(xfer); 2660 if (err) 2661 return (err); 2662 2663 if (sc->sc_bus.use_polling) 2664 ehci_waitintr(sc, xfer); 2665 return (USBD_IN_PROGRESS); 2666 } 2667 2668 void 2669 ehci_device_ctrl_done(usbd_xfer_handle xfer) 2670 { 2671 struct ehci_xfer *ex = EXFER(xfer); 2672 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2673 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/ 2674 2675 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 2676 2677 #ifdef DIAGNOSTIC 2678 if (!(xfer->rqflags & URQ_REQUEST)) { 2679 panic("ehci_ctrl_done: not a request"); 2680 } 2681 #endif 2682 2683 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 2684 ehci_del_intr_list(ex); /* remove from active list */ 2685 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 2686 } 2687 2688 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 2689 } 2690 2691 /* Abort a device control request. */ 2692 Static void 2693 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 2694 { 2695 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 2696 ehci_abort_xfer(xfer, USBD_CANCELLED); 2697 } 2698 2699 /* Close a device control pipe. */ 2700 Static void 2701 ehci_device_ctrl_close(usbd_pipe_handle pipe) 2702 { 2703 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2704 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 2705 2706 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 2707 ehci_close_pipe(pipe, sc->sc_async_head); 2708 } 2709 2710 usbd_status 2711 ehci_device_request(usbd_xfer_handle xfer) 2712 { 2713 #define exfer EXFER(xfer) 2714 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2715 usb_device_request_t *req = &xfer->request; 2716 usbd_device_handle dev = epipe->pipe.device; 2717 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 2718 int addr = dev->address; 2719 ehci_soft_qtd_t *setup, *stat, *next; 2720 ehci_soft_qh_t *sqh; 2721 int isread; 2722 int len; 2723 usbd_status err; 2724 int s; 2725 2726 isread = req->bmRequestType & UT_READ; 2727 len = UGETW(req->wLength); 2728 2729 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 2730 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2731 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2732 UGETW(req->wIndex), len, addr, 2733 epipe->pipe.endpoint->edesc->bEndpointAddress)); 2734 2735 setup = ehci_alloc_sqtd(sc); 2736 if (setup == NULL) { 2737 err = USBD_NOMEM; 2738 goto bad1; 2739 } 2740 stat = ehci_alloc_sqtd(sc); 2741 if (stat == NULL) { 2742 err = USBD_NOMEM; 2743 goto bad2; 2744 } 2745 2746 sqh = epipe->sqh; 2747 epipe->u.ctl.length = len; 2748 2749 /* Update device address and length since they may have changed 2750 during the setup of the control pipe in usbd_new_device(). */ 2751 /* XXX This only needs to be done once, but it's too early in open. */ 2752 /* XXXX Should not touch ED here! */ 2753 sqh->qh.qh_endp = 2754 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 2755 htole32( 2756 EHCI_QH_SET_ADDR(addr) | 2757 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 2758 ); 2759 2760 /* Set up data transaction */ 2761 if (len != 0) { 2762 ehci_soft_qtd_t *end; 2763 2764 /* Start toggle at 1. */ 2765 epipe->nexttoggle = 1; 2766 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 2767 &next, &end); 2768 if (err) 2769 goto bad3; 2770 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 2771 end->nextqtd = stat; 2772 end->qtd.qtd_next = 2773 end->qtd.qtd_altnext = htole32(stat->physaddr); 2774 } else { 2775 next = stat; 2776 } 2777 2778 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 2779 2780 /* Clear toggle */ 2781 setup->qtd.qtd_status = htole32( 2782 EHCI_QTD_ACTIVE | 2783 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 2784 EHCI_QTD_SET_CERR(3) | 2785 EHCI_QTD_SET_TOGGLE(0) | 2786 EHCI_QTD_SET_BYTES(sizeof *req) 2787 ); 2788 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 2789 setup->qtd.qtd_buffer_hi[0] = 0; 2790 setup->nextqtd = next; 2791 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 2792 setup->xfer = xfer; 2793 setup->len = sizeof *req; 2794 2795 stat->qtd.qtd_status = htole32( 2796 EHCI_QTD_ACTIVE | 2797 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 2798 EHCI_QTD_SET_CERR(3) | 2799 EHCI_QTD_SET_TOGGLE(1) | 2800 EHCI_QTD_IOC 2801 ); 2802 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 2803 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 2804 stat->nextqtd = NULL; 2805 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 2806 stat->xfer = xfer; 2807 stat->len = 0; 2808 2809 #ifdef EHCI_DEBUG 2810 if (ehcidebug > 5) { 2811 DPRINTF(("ehci_device_request:\n")); 2812 ehci_dump_sqh(sqh); 2813 ehci_dump_sqtds(setup); 2814 } 2815 #endif 2816 2817 exfer->sqtdstart = setup; 2818 exfer->sqtdend = stat; 2819 #ifdef DIAGNOSTIC 2820 if (!exfer->isdone) { 2821 printf("ehci_device_request: not done, exfer=%p\n", exfer); 2822 } 2823 exfer->isdone = 0; 2824 #endif 2825 2826 /* Insert qTD in QH list. */ 2827 s = splusb(); 2828 ehci_set_qh_qtd(sqh, setup); 2829 if (xfer->timeout && !sc->sc_bus.use_polling) { 2830 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 2831 ehci_timeout, xfer); 2832 } 2833 ehci_add_intr_list(sc, exfer); 2834 xfer->status = USBD_IN_PROGRESS; 2835 splx(s); 2836 2837 #ifdef EHCI_DEBUG 2838 if (ehcidebug > 10) { 2839 DPRINTF(("ehci_device_request: status=%x\n", 2840 EOREAD4(sc, EHCI_USBSTS))); 2841 delay(10000); 2842 ehci_dump_regs(sc); 2843 ehci_dump_sqh(sc->sc_async_head); 2844 ehci_dump_sqh(sqh); 2845 ehci_dump_sqtds(setup); 2846 } 2847 #endif 2848 2849 return (USBD_NORMAL_COMPLETION); 2850 2851 bad3: 2852 ehci_free_sqtd(sc, stat); 2853 bad2: 2854 ehci_free_sqtd(sc, setup); 2855 bad1: 2856 DPRINTFN(-1,("ehci_device_request: no memory\n")); 2857 xfer->status = err; 2858 usb_transfer_complete(xfer); 2859 return (err); 2860 #undef exfer 2861 } 2862 2863 /* 2864 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 2865 * qTD status, or miss signalling occasionally under heavy load. If the host 2866 * machine is too fast, we we can miss transaction completion - when we scan 2867 * the active list the transaction still seems to be active. This generally 2868 * exhibits itself as a umass stall that never recovers. 2869 * 2870 * We work around this behaviour by setting up this callback after any softintr 2871 * that completes with transactions still pending, giving us another chance to 2872 * check for completion after the writeback has taken place. 2873 */ 2874 void 2875 ehci_intrlist_timeout(void *arg) 2876 { 2877 ehci_softc_t *sc = arg; 2878 int s = splusb(); 2879 2880 DPRINTF(("ehci_intrlist_timeout\n")); 2881 usb_schedsoftintr(&sc->sc_bus); 2882 2883 splx(s); 2884 } 2885 2886 /************************/ 2887 2888 Static usbd_status 2889 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 2890 { 2891 usbd_status err; 2892 2893 /* Insert last in queue. */ 2894 err = usb_insert_transfer(xfer); 2895 if (err) 2896 return (err); 2897 2898 /* Pipe isn't running, start first */ 2899 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2900 } 2901 2902 usbd_status 2903 ehci_device_bulk_start(usbd_xfer_handle xfer) 2904 { 2905 #define exfer EXFER(xfer) 2906 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2907 usbd_device_handle dev = epipe->pipe.device; 2908 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 2909 ehci_soft_qtd_t *data, *dataend; 2910 ehci_soft_qh_t *sqh; 2911 usbd_status err; 2912 int len, isread, endpt; 2913 int s; 2914 2915 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 2916 xfer, xfer->length, xfer->flags)); 2917 2918 if (sc->sc_dying) 2919 return (USBD_IOERROR); 2920 2921 #ifdef DIAGNOSTIC 2922 if (xfer->rqflags & URQ_REQUEST) 2923 panic("ehci_device_bulk_start: a request"); 2924 #endif 2925 2926 len = xfer->length; 2927 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 2928 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 2929 sqh = epipe->sqh; 2930 2931 epipe->u.bulk.length = len; 2932 2933 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 2934 &dataend); 2935 if (err) { 2936 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 2937 xfer->status = err; 2938 usb_transfer_complete(xfer); 2939 return (err); 2940 } 2941 2942 #ifdef EHCI_DEBUG 2943 if (ehcidebug > 5) { 2944 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 2945 ehci_dump_sqh(sqh); 2946 ehci_dump_sqtds(data); 2947 } 2948 #endif 2949 2950 /* Set up interrupt info. */ 2951 exfer->sqtdstart = data; 2952 exfer->sqtdend = dataend; 2953 #ifdef DIAGNOSTIC 2954 if (!exfer->isdone) { 2955 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 2956 } 2957 exfer->isdone = 0; 2958 #endif 2959 2960 s = splusb(); 2961 ehci_set_qh_qtd(sqh, data); 2962 if (xfer->timeout && !sc->sc_bus.use_polling) { 2963 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 2964 ehci_timeout, xfer); 2965 } 2966 ehci_add_intr_list(sc, exfer); 2967 xfer->status = USBD_IN_PROGRESS; 2968 splx(s); 2969 2970 #ifdef EHCI_DEBUG 2971 if (ehcidebug > 10) { 2972 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 2973 delay(10000); 2974 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 2975 ehci_dump_regs(sc); 2976 #if 0 2977 printf("async_head:\n"); 2978 ehci_dump_sqh(sc->sc_async_head); 2979 #endif 2980 printf("sqh:\n"); 2981 ehci_dump_sqh(sqh); 2982 ehci_dump_sqtds(data); 2983 } 2984 #endif 2985 2986 if (sc->sc_bus.use_polling) 2987 ehci_waitintr(sc, xfer); 2988 2989 return (USBD_IN_PROGRESS); 2990 #undef exfer 2991 } 2992 2993 Static void 2994 ehci_device_bulk_abort(usbd_xfer_handle xfer) 2995 { 2996 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 2997 ehci_abort_xfer(xfer, USBD_CANCELLED); 2998 } 2999 3000 /* 3001 * Close a device bulk pipe. 3002 */ 3003 Static void 3004 ehci_device_bulk_close(usbd_pipe_handle pipe) 3005 { 3006 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3007 3008 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3009 ehci_close_pipe(pipe, sc->sc_async_head); 3010 } 3011 3012 void 3013 ehci_device_bulk_done(usbd_xfer_handle xfer) 3014 { 3015 struct ehci_xfer *ex = EXFER(xfer); 3016 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3017 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/ 3018 3019 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3020 xfer, xfer->actlen)); 3021 3022 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3023 ehci_del_intr_list(ex); /* remove from active list */ 3024 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3025 } 3026 3027 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3028 } 3029 3030 /************************/ 3031 3032 Static usbd_status 3033 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3034 { 3035 struct ehci_soft_islot *isp; 3036 int islot, lev; 3037 3038 /* Find a poll rate that is large enough. */ 3039 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3040 if (EHCI_ILEV_IVAL(lev) <= ival) 3041 break; 3042 3043 /* Pick an interrupt slot at the right level. */ 3044 /* XXX could do better than picking at random */ 3045 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3046 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3047 3048 sqh->islot = islot; 3049 isp = &sc->sc_islots[islot]; 3050 ehci_add_qh(sqh, isp->sqh); 3051 3052 return (USBD_NORMAL_COMPLETION); 3053 } 3054 3055 Static usbd_status 3056 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3057 { 3058 usbd_status err; 3059 3060 /* Insert last in queue. */ 3061 err = usb_insert_transfer(xfer); 3062 if (err) 3063 return (err); 3064 3065 /* 3066 * Pipe isn't running (otherwise err would be USBD_INPROG), 3067 * so start it first. 3068 */ 3069 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3070 } 3071 3072 Static usbd_status 3073 ehci_device_intr_start(usbd_xfer_handle xfer) 3074 { 3075 #define exfer EXFER(xfer) 3076 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3077 usbd_device_handle dev = xfer->pipe->device; 3078 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3079 ehci_soft_qtd_t *data, *dataend; 3080 ehci_soft_qh_t *sqh; 3081 usbd_status err; 3082 int len, isread, endpt; 3083 int s; 3084 3085 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3086 xfer, xfer->length, xfer->flags)); 3087 3088 if (sc->sc_dying) 3089 return (USBD_IOERROR); 3090 3091 #ifdef DIAGNOSTIC 3092 if (xfer->rqflags & URQ_REQUEST) 3093 panic("ehci_device_intr_start: a request"); 3094 #endif 3095 3096 len = xfer->length; 3097 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3098 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3099 sqh = epipe->sqh; 3100 3101 epipe->u.intr.length = len; 3102 3103 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3104 &dataend); 3105 if (err) { 3106 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3107 xfer->status = err; 3108 usb_transfer_complete(xfer); 3109 return (err); 3110 } 3111 3112 #ifdef EHCI_DEBUG 3113 if (ehcidebug > 5) { 3114 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3115 ehci_dump_sqh(sqh); 3116 ehci_dump_sqtds(data); 3117 } 3118 #endif 3119 3120 /* Set up interrupt info. */ 3121 exfer->sqtdstart = data; 3122 exfer->sqtdend = dataend; 3123 #ifdef DIAGNOSTIC 3124 if (!exfer->isdone) { 3125 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3126 } 3127 exfer->isdone = 0; 3128 #endif 3129 3130 s = splusb(); 3131 ehci_set_qh_qtd(sqh, data); 3132 if (xfer->timeout && !sc->sc_bus.use_polling) { 3133 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3134 ehci_timeout, xfer); 3135 } 3136 ehci_add_intr_list(sc, exfer); 3137 xfer->status = USBD_IN_PROGRESS; 3138 splx(s); 3139 3140 #ifdef EHCI_DEBUG 3141 if (ehcidebug > 10) { 3142 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3143 delay(10000); 3144 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3145 ehci_dump_regs(sc); 3146 printf("sqh:\n"); 3147 ehci_dump_sqh(sqh); 3148 ehci_dump_sqtds(data); 3149 } 3150 #endif 3151 3152 if (sc->sc_bus.use_polling) 3153 ehci_waitintr(sc, xfer); 3154 3155 return (USBD_IN_PROGRESS); 3156 #undef exfer 3157 } 3158 3159 Static void 3160 ehci_device_intr_abort(usbd_xfer_handle xfer) 3161 { 3162 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3163 if (xfer->pipe->intrxfer == xfer) { 3164 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3165 xfer->pipe->intrxfer = NULL; 3166 } 3167 ehci_abort_xfer(xfer, USBD_CANCELLED); 3168 } 3169 3170 Static void 3171 ehci_device_intr_close(usbd_pipe_handle pipe) 3172 { 3173 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3174 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3175 struct ehci_soft_islot *isp; 3176 3177 isp = &sc->sc_islots[epipe->sqh->islot]; 3178 ehci_close_pipe(pipe, isp->sqh); 3179 } 3180 3181 Static void 3182 ehci_device_intr_done(usbd_xfer_handle xfer) 3183 { 3184 #define exfer EXFER(xfer) 3185 struct ehci_xfer *ex = EXFER(xfer); 3186 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3187 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3188 ehci_soft_qtd_t *data, *dataend; 3189 ehci_soft_qh_t *sqh; 3190 usbd_status err; 3191 int len, isread, endpt, s; 3192 3193 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3194 xfer, xfer->actlen)); 3195 3196 if (xfer->pipe->repeat) { 3197 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3198 3199 len = epipe->u.intr.length; 3200 xfer->length = len; 3201 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3202 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3203 sqh = epipe->sqh; 3204 3205 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3206 &data, &dataend); 3207 if (err) { 3208 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3209 xfer->status = err; 3210 return; 3211 } 3212 3213 /* Set up interrupt info. */ 3214 exfer->sqtdstart = data; 3215 exfer->sqtdend = dataend; 3216 #ifdef DIAGNOSTIC 3217 if (!exfer->isdone) { 3218 printf("ehci_device_intr_done: not done, ex=%p\n", 3219 exfer); 3220 } 3221 exfer->isdone = 0; 3222 #endif 3223 3224 s = splusb(); 3225 ehci_set_qh_qtd(sqh, data); 3226 if (xfer->timeout && !sc->sc_bus.use_polling) { 3227 usb_callout(xfer->timeout_handle, 3228 mstohz(xfer->timeout), ehci_timeout, xfer); 3229 } 3230 splx(s); 3231 3232 xfer->status = USBD_IN_PROGRESS; 3233 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3234 ehci_del_intr_list(ex); /* remove from active list */ 3235 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3236 } 3237 #undef exfer 3238 } 3239 3240 /************************/ 3241 3242 Static usbd_status 3243 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3244 { 3245 return USBD_IOERROR; 3246 } 3247 Static usbd_status 3248 ehci_device_isoc_start(usbd_xfer_handle xfer) 3249 { 3250 return USBD_IOERROR; 3251 } 3252 Static void 3253 ehci_device_isoc_abort(usbd_xfer_handle xfer) 3254 { 3255 } 3256 Static void 3257 ehci_device_isoc_close(usbd_pipe_handle pipe) 3258 { 3259 } 3260 Static void 3261 ehci_device_isoc_done(usbd_xfer_handle xfer) 3262 { 3263 } 3264
Indexes created Thu Oct 02 01:09:59 GMT 2025