ehci.c revision 1.118.2.1.2.1
1 /* $NetBSD: ehci.c,v 1.118.2.1.2.1 2008/09/04 08:46:45 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004,2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 41 * 42 * The EHCI 1.0 spec can be found at 43 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 44 * and the USB 2.0 spec at 45 * http://www.usb.org/developers/docs/usb_20.zip 46 * 47 */ 48 49 /* 50 * TODO: 51 * 1) hold off explorations by companion controllers until ehci has started. 52 * 53 * 2) The EHCI driver lacks support for isochronous transfers, so 54 * devices using them don't work. 55 * 56 * 3) The hub driver needs to handle and schedule the transaction translator, 57 * to assign place in frame where different devices get to go. See chapter 58 * on hubs in USB 2.0 for details. 59 * 60 * 4) command failures are not recovered correctly 61 */ 62 63 #include <sys/cdefs.h> 64 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.118.2.1.2.1 2008/09/04 08:46:45 skrll Exp $"); 65 66 #include "ohci.h" 67 #include "uhci.h" 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/kernel.h> 72 #include <sys/malloc.h> 73 #include <sys/device.h> 74 #include <sys/select.h> 75 #include <sys/proc.h> 76 #include <sys/queue.h> 77 78 #include <machine/bus.h> 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usb_mem.h> 85 #include <dev/usb/usb_quirks.h> 86 87 #include <dev/usb/ehcireg.h> 88 #include <dev/usb/ehcivar.h> 89 90 #ifdef EHCI_DEBUG 91 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 92 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 93 int ehcidebug = 0; 94 #ifndef __NetBSD__ 95 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 96 #endif 97 #else 98 #define DPRINTF(x) 99 #define DPRINTFN(n,x) 100 #endif 101 102 struct ehci_pipe { 103 struct usbd_pipe pipe; 104 int nexttoggle; 105 106 ehci_soft_qh_t *sqh; 107 union { 108 ehci_soft_qtd_t *qtd; 109 /* ehci_soft_itd_t *itd; */ 110 } tail; 111 union { 112 /* Control pipe */ 113 struct { 114 usb_dma_t reqdma; 115 u_int length; 116 } ctl; 117 /* Interrupt pipe */ 118 struct { 119 u_int length; 120 } intr; 121 /* Bulk pipe */ 122 struct { 123 u_int length; 124 } bulk; 125 /* Iso pipe */ 126 /* XXX */ 127 } u; 128 }; 129 130 Static void ehci_shutdown(void *); 131 Static void ehci_power(int, void *); 132 133 Static usbd_status ehci_open(usbd_pipe_handle); 134 Static void ehci_poll(struct usbd_bus *); 135 Static void ehci_softintr(void *); 136 Static int ehci_intr1(ehci_softc_t *); 137 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 138 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 139 Static void ehci_idone(struct ehci_xfer *); 140 Static void ehci_timeout(void *); 141 Static void ehci_timeout_task(void *); 142 Static void ehci_intrlist_timeout(void *); 143 144 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 145 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 146 147 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 148 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 149 150 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 151 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 152 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 153 Static void ehci_root_ctrl_close(usbd_pipe_handle); 154 Static void ehci_root_ctrl_done(usbd_xfer_handle); 155 156 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 157 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 158 Static void ehci_root_intr_abort(usbd_xfer_handle); 159 Static void ehci_root_intr_close(usbd_pipe_handle); 160 Static void ehci_root_intr_done(usbd_xfer_handle); 161 162 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 163 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 164 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 165 Static void ehci_device_ctrl_close(usbd_pipe_handle); 166 Static void ehci_device_ctrl_done(usbd_xfer_handle); 167 168 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 169 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 170 Static void ehci_device_bulk_abort(usbd_xfer_handle); 171 Static void ehci_device_bulk_close(usbd_pipe_handle); 172 Static void ehci_device_bulk_done(usbd_xfer_handle); 173 174 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 175 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 176 Static void ehci_device_intr_abort(usbd_xfer_handle); 177 Static void ehci_device_intr_close(usbd_pipe_handle); 178 Static void ehci_device_intr_done(usbd_xfer_handle); 179 180 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 181 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 182 Static void ehci_device_isoc_abort(usbd_xfer_handle); 183 Static void ehci_device_isoc_close(usbd_pipe_handle); 184 Static void ehci_device_isoc_done(usbd_xfer_handle); 185 186 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 187 Static void ehci_noop(usbd_pipe_handle pipe); 188 189 Static int ehci_str(usb_string_descriptor_t *, int, const char *); 190 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 191 Static void ehci_pcd_able(ehci_softc_t *, int); 192 Static void ehci_pcd_enable(void *); 193 Static void ehci_disown(ehci_softc_t *, int, int); 194 195 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 196 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 197 198 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 199 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 200 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 201 ehci_softc_t *, int, int, usbd_xfer_handle, 202 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 203 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 204 ehci_soft_qtd_t *); 205 206 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 207 208 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 209 int ival); 210 211 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 212 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 213 ehci_soft_qh_t *); 214 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 215 Static void ehci_sync_hc(ehci_softc_t *); 216 217 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 218 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 219 220 #ifdef EHCI_DEBUG 221 Static void ehci_dump_regs(ehci_softc_t *); 222 void ehci_dump(void); 223 Static ehci_softc_t *theehci; 224 Static void ehci_dump_link(ehci_link_t, int); 225 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 226 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 227 Static void ehci_dump_qtd(ehci_qtd_t *); 228 Static void ehci_dump_sqh(ehci_soft_qh_t *); 229 #ifdef DIAGNOSTIC 230 Static void ehci_dump_exfer(struct ehci_xfer *); 231 #endif 232 #endif 233 234 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 235 236 #define EHCI_INTR_ENDPT 1 237 238 #define ehci_add_intr_list(sc, ex) \ 239 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext); 240 #define ehci_del_intr_list(ex) \ 241 do { \ 242 LIST_REMOVE((ex), inext); \ 243 (ex)->inext.le_prev = NULL; \ 244 } while (0) 245 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL) 246 247 Static struct usbd_bus_methods ehci_bus_methods = { 248 ehci_open, 249 ehci_softintr, 250 ehci_poll, 251 ehci_allocm, 252 ehci_freem, 253 ehci_allocx, 254 ehci_freex, 255 }; 256 257 Static struct usbd_pipe_methods ehci_root_ctrl_methods = { 258 ehci_root_ctrl_transfer, 259 ehci_root_ctrl_start, 260 ehci_root_ctrl_abort, 261 ehci_root_ctrl_close, 262 ehci_noop, 263 ehci_root_ctrl_done, 264 }; 265 266 Static struct usbd_pipe_methods ehci_root_intr_methods = { 267 ehci_root_intr_transfer, 268 ehci_root_intr_start, 269 ehci_root_intr_abort, 270 ehci_root_intr_close, 271 ehci_noop, 272 ehci_root_intr_done, 273 }; 274 275 Static struct usbd_pipe_methods ehci_device_ctrl_methods = { 276 ehci_device_ctrl_transfer, 277 ehci_device_ctrl_start, 278 ehci_device_ctrl_abort, 279 ehci_device_ctrl_close, 280 ehci_noop, 281 ehci_device_ctrl_done, 282 }; 283 284 Static struct usbd_pipe_methods ehci_device_intr_methods = { 285 ehci_device_intr_transfer, 286 ehci_device_intr_start, 287 ehci_device_intr_abort, 288 ehci_device_intr_close, 289 ehci_device_clear_toggle, 290 ehci_device_intr_done, 291 }; 292 293 Static struct usbd_pipe_methods ehci_device_bulk_methods = { 294 ehci_device_bulk_transfer, 295 ehci_device_bulk_start, 296 ehci_device_bulk_abort, 297 ehci_device_bulk_close, 298 ehci_device_clear_toggle, 299 ehci_device_bulk_done, 300 }; 301 302 Static struct usbd_pipe_methods ehci_device_isoc_methods = { 303 ehci_device_isoc_transfer, 304 ehci_device_isoc_start, 305 ehci_device_isoc_abort, 306 ehci_device_isoc_close, 307 ehci_noop, 308 ehci_device_isoc_done, 309 }; 310 311 static uint8_t revbits[EHCI_MAX_POLLRATE] = { 312 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 313 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 314 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 315 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 316 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 317 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 318 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 319 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 320 }; 321 322 usbd_status 323 ehci_init(ehci_softc_t *sc) 324 { 325 u_int32_t vers, sparams, cparams, hcr; 326 u_int i; 327 usbd_status err; 328 ehci_soft_qh_t *sqh; 329 u_int ncomp; 330 331 DPRINTF(("ehci_init: start\n")); 332 #ifdef EHCI_DEBUG 333 theehci = sc; 334 #endif 335 336 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 337 338 vers = EREAD2(sc, EHCI_HCIVERSION); 339 aprint_normal("%s: EHCI version %x.%x\n", USBDEVNAME(sc->sc_bus.bdev), 340 vers >> 8, vers & 0xff); 341 342 sparams = EREAD4(sc, EHCI_HCSPARAMS); 343 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 344 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 345 ncomp = EHCI_HCS_N_CC(sparams); 346 if (ncomp != sc->sc_ncomp) { 347 aprint_error("%s: wrong number of companions (%d != %d)\n", 348 USBDEVNAME(sc->sc_bus.bdev), 349 ncomp, sc->sc_ncomp); 350 #if NOHCI == 0 || NUHCI == 0 351 aprint_error("%s: ohci or uhci probably not configured\n", 352 USBDEVNAME(sc->sc_bus.bdev)); 353 #endif 354 if (ncomp < sc->sc_ncomp) 355 sc->sc_ncomp = ncomp; 356 } 357 if (sc->sc_ncomp > 0) { 358 aprint_normal("%s: companion controller%s, %d port%s each:", 359 USBDEVNAME(sc->sc_bus.bdev), sc->sc_ncomp!=1 ? "s" : "", 360 EHCI_HCS_N_PCC(sparams), 361 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 362 for (i = 0; i < sc->sc_ncomp; i++) 363 aprint_normal(" %s", USBDEVNAME(sc->sc_comps[i]->bdev)); 364 aprint_normal("\n"); 365 } 366 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 367 cparams = EREAD4(sc, EHCI_HCCPARAMS); 368 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 369 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 370 371 if (EHCI_HCC_64BIT(cparams)) { 372 /* MUST clear segment register if 64 bit capable. */ 373 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 374 } 375 376 sc->sc_bus.usbrev = USBREV_2_0; 377 378 usb_setup_reserve(sc, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 379 USB_MEM_RESERVE); 380 381 /* Reset the controller */ 382 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 383 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 384 usb_delay_ms(&sc->sc_bus, 1); 385 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 386 for (i = 0; i < 100; i++) { 387 usb_delay_ms(&sc->sc_bus, 1); 388 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 389 if (!hcr) 390 break; 391 } 392 if (hcr) { 393 aprint_error("%s: reset timeout\n", 394 USBDEVNAME(sc->sc_bus.bdev)); 395 return (USBD_IOERROR); 396 } 397 398 /* XXX need proper intr scheduling */ 399 sc->sc_rand = 96; 400 401 /* frame list size at default, read back what we got and use that */ 402 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 403 case 0: sc->sc_flsize = 1024; break; 404 case 1: sc->sc_flsize = 512; break; 405 case 2: sc->sc_flsize = 256; break; 406 case 3: return (USBD_IOERROR); 407 } 408 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 409 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 410 if (err) 411 return (err); 412 DPRINTF(("%s: flsize=%d\n", USBDEVNAME(sc->sc_bus.bdev),sc->sc_flsize)); 413 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 414 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 415 416 /* Set up the bus struct. */ 417 sc->sc_bus.methods = &ehci_bus_methods; 418 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 419 420 sc->sc_powerhook = powerhook_establish(USBDEVNAME(sc->sc_bus.bdev), 421 ehci_power, sc); 422 sc->sc_shutdownhook = shutdownhook_establish(ehci_shutdown, sc); 423 424 sc->sc_eintrs = EHCI_NORMAL_INTRS; 425 426 /* 427 * Allocate the interrupt dummy QHs. These are arranged to give poll 428 * intervals that are powers of 2 times 1ms. 429 */ 430 for (i = 0; i < EHCI_INTRQHS; i++) { 431 sqh = ehci_alloc_sqh(sc); 432 if (sqh == NULL) { 433 err = USBD_NOMEM; 434 goto bad1; 435 } 436 sc->sc_islots[i].sqh = sqh; 437 } 438 for (i = 0; i < EHCI_INTRQHS; i++) { 439 sqh = sc->sc_islots[i].sqh; 440 if (i == 0) { 441 /* The last (1ms) QH terminates. */ 442 sqh->qh.qh_link = EHCI_NULL; 443 sqh->next = NULL; 444 } else { 445 /* Otherwise the next QH has half the poll interval */ 446 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 447 sqh->qh.qh_link = htole32(sqh->next->physaddr | 448 EHCI_LINK_QH); 449 } 450 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 451 sqh->qh.qh_curqtd = EHCI_NULL; 452 sqh->next = NULL; 453 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 454 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 455 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 456 sqh->sqtd = NULL; 457 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 458 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 459 } 460 /* Point the frame list at the last level (128ms). */ 461 for (i = 0; i < sc->sc_flsize; i++) { 462 int j; 463 464 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 465 revbits[i & (EHCI_MAX_POLLRATE-1)]; 466 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 467 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 468 i)].sqh->physaddr); 469 } 470 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 471 BUS_DMASYNC_PREWRITE); 472 473 /* Allocate dummy QH that starts the async list. */ 474 sqh = ehci_alloc_sqh(sc); 475 if (sqh == NULL) { 476 err = USBD_NOMEM; 477 goto bad1; 478 } 479 /* Fill the QH */ 480 sqh->qh.qh_endp = 481 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 482 sqh->qh.qh_link = 483 htole32(sqh->physaddr | EHCI_LINK_QH); 484 sqh->qh.qh_curqtd = EHCI_NULL; 485 sqh->next = NULL; 486 /* Fill the overlay qTD */ 487 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 488 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 489 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 490 sqh->sqtd = NULL; 491 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 492 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 493 #ifdef EHCI_DEBUG 494 if (ehcidebug) { 495 ehci_dump_sqh(sqh); 496 } 497 #endif 498 499 /* Point to async list */ 500 sc->sc_async_head = sqh; 501 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 502 503 usb_callout_init(sc->sc_tmo_pcd); 504 usb_callout_init(sc->sc_tmo_intrlist); 505 506 lockinit(&sc->sc_doorbell_lock, PZERO, "ehcidb", 0, 0); 507 508 /* Turn on controller */ 509 EOWRITE4(sc, EHCI_USBCMD, 510 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 511 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 512 EHCI_CMD_ASE | 513 EHCI_CMD_PSE | 514 EHCI_CMD_RS); 515 516 /* Take over port ownership */ 517 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 518 519 for (i = 0; i < 100; i++) { 520 usb_delay_ms(&sc->sc_bus, 1); 521 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 522 if (!hcr) 523 break; 524 } 525 if (hcr) { 526 aprint_error("%s: run timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 527 return (USBD_IOERROR); 528 } 529 530 /* Enable interrupts */ 531 DPRINTFN(1,("ehci_init: enabling\n")); 532 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 533 534 return (USBD_NORMAL_COMPLETION); 535 536 #if 0 537 bad2: 538 ehci_free_sqh(sc, sc->sc_async_head); 539 #endif 540 bad1: 541 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 542 return (err); 543 } 544 545 int 546 ehci_intr(void *v) 547 { 548 ehci_softc_t *sc = v; 549 550 if (sc == NULL || sc->sc_dying) 551 return (0); 552 553 /* If we get an interrupt while polling, then just ignore it. */ 554 if (sc->sc_bus.use_polling) { 555 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 556 557 if (intrs) 558 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 559 #ifdef DIAGNOSTIC 560 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 561 #endif 562 return (0); 563 } 564 565 return (ehci_intr1(sc)); 566 } 567 568 Static int 569 ehci_intr1(ehci_softc_t *sc) 570 { 571 u_int32_t intrs, eintrs; 572 573 DPRINTFN(20,("ehci_intr1: enter\n")); 574 575 /* In case the interrupt occurs before initialization has completed. */ 576 if (sc == NULL) { 577 #ifdef DIAGNOSTIC 578 printf("ehci_intr1: sc == NULL\n"); 579 #endif 580 return (0); 581 } 582 583 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 584 if (!intrs) 585 return (0); 586 587 eintrs = intrs & sc->sc_eintrs; 588 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 589 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 590 (u_int)eintrs)); 591 if (!eintrs) 592 return (0); 593 594 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 595 sc->sc_bus.intr_context++; 596 sc->sc_bus.no_intrs++; 597 if (eintrs & EHCI_STS_IAA) { 598 DPRINTF(("ehci_intr1: door bell\n")); 599 wakeup(&sc->sc_async_head); 600 eintrs &= ~EHCI_STS_IAA; 601 } 602 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 603 DPRINTFN(5,("ehci_intr1: %s %s\n", 604 eintrs & EHCI_STS_INT ? "INT" : "", 605 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 606 usb_schedsoftintr(&sc->sc_bus); 607 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 608 } 609 if (eintrs & EHCI_STS_HSE) { 610 printf("%s: unrecoverable error, controller halted\n", 611 USBDEVNAME(sc->sc_bus.bdev)); 612 /* XXX what else */ 613 } 614 if (eintrs & EHCI_STS_PCD) { 615 ehci_pcd(sc, sc->sc_intrxfer); 616 /* 617 * Disable PCD interrupt for now, because it will be 618 * on until the port has been reset. 619 */ 620 ehci_pcd_able(sc, 0); 621 /* Do not allow RHSC interrupts > 1 per second */ 622 usb_callout(sc->sc_tmo_pcd, hz, ehci_pcd_enable, sc); 623 eintrs &= ~EHCI_STS_PCD; 624 } 625 626 sc->sc_bus.intr_context--; 627 628 if (eintrs != 0) { 629 /* Block unprocessed interrupts. */ 630 sc->sc_eintrs &= ~eintrs; 631 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 632 printf("%s: blocking intrs 0x%x\n", 633 USBDEVNAME(sc->sc_bus.bdev), eintrs); 634 } 635 636 return (1); 637 } 638 639 void 640 ehci_pcd_able(ehci_softc_t *sc, int on) 641 { 642 DPRINTFN(4, ("ehci_pcd_able: on=%d\n", on)); 643 if (on) 644 sc->sc_eintrs |= EHCI_STS_PCD; 645 else 646 sc->sc_eintrs &= ~EHCI_STS_PCD; 647 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 648 } 649 650 void 651 ehci_pcd_enable(void *v_sc) 652 { 653 ehci_softc_t *sc = v_sc; 654 655 ehci_pcd_able(sc, 1); 656 } 657 658 void 659 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 660 { 661 usbd_pipe_handle pipe; 662 u_char *p; 663 int i, m; 664 665 if (xfer == NULL) { 666 /* Just ignore the change. */ 667 return; 668 } 669 670 pipe = xfer->pipe; 671 672 p = KERNADDR(&xfer->dmabuf, 0); 673 m = min(sc->sc_noport, xfer->length * 8 - 1); 674 memset(p, 0, xfer->length); 675 for (i = 1; i <= m; i++) { 676 /* Pick out CHANGE bits from the status reg. */ 677 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 678 p[i/8] |= 1 << (i%8); 679 } 680 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 681 xfer->actlen = xfer->length; 682 xfer->status = USBD_NORMAL_COMPLETION; 683 684 usb_transfer_complete(xfer); 685 } 686 687 void 688 ehci_softintr(void *v) 689 { 690 ehci_softc_t *sc = v; 691 struct ehci_xfer *ex, *nextex; 692 693 DPRINTFN(10,("%s: ehci_softintr (%d)\n", USBDEVNAME(sc->sc_bus.bdev), 694 sc->sc_bus.intr_context)); 695 696 sc->sc_bus.intr_context++; 697 698 /* 699 * The only explanation I can think of for why EHCI is as brain dead 700 * as UHCI interrupt-wise is that Intel was involved in both. 701 * An interrupt just tells us that something is done, we have no 702 * clue what, so we need to scan through all active transfers. :-( 703 */ 704 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 705 nextex = LIST_NEXT(ex, inext); 706 ehci_check_intr(sc, ex); 707 } 708 709 /* Schedule a callout to catch any dropped transactions. */ 710 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 711 !LIST_EMPTY(&sc->sc_intrhead)) 712 usb_callout(sc->sc_tmo_intrlist, hz, 713 ehci_intrlist_timeout, sc); 714 715 #ifdef USB_USE_SOFTINTR 716 if (sc->sc_softwake) { 717 sc->sc_softwake = 0; 718 wakeup(&sc->sc_softwake); 719 } 720 #endif /* USB_USE_SOFTINTR */ 721 722 sc->sc_bus.intr_context--; 723 } 724 725 /* Check for an interrupt. */ 726 void 727 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 728 { 729 ehci_soft_qtd_t *sqtd, *lsqtd; 730 u_int32_t status; 731 732 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 733 734 if (ex->sqtdstart == NULL) { 735 printf("ehci_check_intr: sqtdstart=NULL\n"); 736 return; 737 } 738 lsqtd = ex->sqtdend; 739 #ifdef DIAGNOSTIC 740 if (lsqtd == NULL) { 741 printf("ehci_check_intr: lsqtd==0\n"); 742 return; 743 } 744 #endif 745 /* 746 * If the last TD is still active we need to check whether there 747 * is a an error somewhere in the middle, or whether there was a 748 * short packet (SPD and not ACTIVE). 749 */ 750 usb_syncmem(&lsqtd->dma, 751 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 752 sizeof(lsqtd->qtd.qtd_status), 753 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 754 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 755 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 756 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 757 usb_syncmem(&sqtd->dma, 758 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 759 sizeof(sqtd->qtd.qtd_status), 760 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 761 status = le32toh(sqtd->qtd.qtd_status); 762 usb_syncmem(&sqtd->dma, 763 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 764 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 765 /* If there's an active QTD the xfer isn't done. */ 766 if (status & EHCI_QTD_ACTIVE) 767 break; 768 /* Any kind of error makes the xfer done. */ 769 if (status & EHCI_QTD_HALTED) 770 goto done; 771 /* We want short packets, and it is short: it's done */ 772 if (EHCI_QTD_GET_BYTES(status) != 0) 773 goto done; 774 } 775 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 776 ex, ex->sqtdstart)); 777 usb_syncmem(&lsqtd->dma, 778 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 779 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 780 return; 781 } 782 done: 783 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 784 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 785 ehci_idone(ex); 786 } 787 788 void 789 ehci_idone(struct ehci_xfer *ex) 790 { 791 usbd_xfer_handle xfer = &ex->xfer; 792 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 793 ehci_soft_qtd_t *sqtd, *lsqtd; 794 u_int32_t status = 0, nstatus = 0; 795 int actlen; 796 797 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 798 #ifdef DIAGNOSTIC 799 { 800 int s = splhigh(); 801 if (ex->isdone) { 802 splx(s); 803 #ifdef EHCI_DEBUG 804 printf("ehci_idone: ex is done!\n "); 805 ehci_dump_exfer(ex); 806 #else 807 printf("ehci_idone: ex=%p is done!\n", ex); 808 #endif 809 return; 810 } 811 ex->isdone = 1; 812 splx(s); 813 } 814 #endif 815 816 if (xfer->status == USBD_CANCELLED || 817 xfer->status == USBD_TIMEOUT) { 818 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 819 return; 820 } 821 822 #ifdef EHCI_DEBUG 823 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 824 if (ehcidebug > 10) 825 ehci_dump_sqtds(ex->sqtdstart); 826 #endif 827 828 /* The transfer is done, compute actual length and status. */ 829 lsqtd = ex->sqtdend; 830 actlen = 0; 831 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd=sqtd->nextqtd) { 832 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 833 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 834 nstatus = le32toh(sqtd->qtd.qtd_status); 835 if (nstatus & EHCI_QTD_ACTIVE) 836 break; 837 838 status = nstatus; 839 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 840 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 841 } 842 843 /* 844 * If there are left over TDs we need to update the toggle. 845 * The default pipe doesn't need it since control transfers 846 * start the toggle at 0 every time. 847 * For a short transfer we need to update the toggle for the missing 848 * packets within the qTD. 849 */ 850 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 851 xfer->pipe->device->default_pipe != xfer->pipe) { 852 DPRINTFN(2, ("ehci_idone: need toggle update " 853 "status=%08x nstatus=%08x\n", status, nstatus)); 854 #if 0 855 ehci_dump_sqh(epipe->sqh); 856 ehci_dump_sqtds(ex->sqtdstart); 857 #endif 858 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 859 } 860 861 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 862 xfer->length, actlen, status)); 863 xfer->actlen = actlen; 864 if (status & EHCI_QTD_HALTED) { 865 #ifdef EHCI_DEBUG 866 char sbuf[128]; 867 868 bitmask_snprintf((u_int32_t)status, 869 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 870 "\3MISSED\1PINGSTATE", sbuf, sizeof(sbuf)); 871 872 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 873 "status 0x%s\n", 874 xfer->pipe->device->address, 875 xfer->pipe->endpoint->edesc->bEndpointAddress, 876 sbuf)); 877 if (ehcidebug > 2) { 878 ehci_dump_sqh(epipe->sqh); 879 ehci_dump_sqtds(ex->sqtdstart); 880 } 881 #endif 882 /* low&full speed has an extra error flag */ 883 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 884 EHCI_QH_SPEED_HIGH) 885 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 886 else 887 status &= EHCI_QTD_STATERRS; 888 if (status == 0) /* no other errors means a stall */ 889 xfer->status = USBD_STALLED; 890 else 891 xfer->status = USBD_IOERROR; /* more info XXX */ 892 /* XXX need to reset TT on missed microframe */ 893 if (status & EHCI_QTD_MISSEDMICRO) { 894 ehci_softc_t *sc = (ehci_softc_t *) 895 xfer->pipe->device->bus; 896 897 printf("%s: missed microframe, TT reset not " 898 "implemented, hub might be inoperational\n", 899 USBDEVNAME(sc->sc_bus.bdev)); 900 } 901 } else { 902 xfer->status = USBD_NORMAL_COMPLETION; 903 } 904 905 usb_transfer_complete(xfer); 906 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 907 } 908 909 /* 910 * Wait here until controller claims to have an interrupt. 911 * Then call ehci_intr and return. Use timeout to avoid waiting 912 * too long. 913 */ 914 void 915 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 916 { 917 int timo; 918 u_int32_t intrs; 919 920 xfer->status = USBD_IN_PROGRESS; 921 for (timo = xfer->timeout; timo >= 0; timo--) { 922 usb_delay_ms(&sc->sc_bus, 1); 923 if (sc->sc_dying) 924 break; 925 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 926 sc->sc_eintrs; 927 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 928 #ifdef EHCI_DEBUG 929 if (ehcidebug > 15) 930 ehci_dump_regs(sc); 931 #endif 932 if (intrs) { 933 ehci_intr1(sc); 934 if (xfer->status != USBD_IN_PROGRESS) 935 return; 936 } 937 } 938 939 /* Timeout */ 940 DPRINTF(("ehci_waitintr: timeout\n")); 941 xfer->status = USBD_TIMEOUT; 942 usb_transfer_complete(xfer); 943 /* XXX should free TD */ 944 } 945 946 void 947 ehci_poll(struct usbd_bus *bus) 948 { 949 ehci_softc_t *sc = (ehci_softc_t *)bus; 950 #ifdef EHCI_DEBUG 951 static int last; 952 int new; 953 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 954 if (new != last) { 955 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 956 last = new; 957 } 958 #endif 959 960 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 961 ehci_intr1(sc); 962 } 963 964 int 965 ehci_detach(struct ehci_softc *sc, int flags) 966 { 967 int rv = 0; 968 969 if (sc->sc_child != NULL) 970 rv = config_detach(sc->sc_child, flags); 971 972 if (rv != 0) 973 return (rv); 974 975 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 976 usb_uncallout(sc->sc_tmo_pcd, ehci_pcd_enable, sc); 977 978 if (sc->sc_powerhook != NULL) 979 powerhook_disestablish(sc->sc_powerhook); 980 if (sc->sc_shutdownhook != NULL) 981 shutdownhook_disestablish(sc->sc_shutdownhook); 982 983 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 984 985 /* XXX free other data structures XXX */ 986 987 return (rv); 988 } 989 990 991 int 992 ehci_activate(device_ptr_t self, enum devact act) 993 { 994 struct ehci_softc *sc = (struct ehci_softc *)self; 995 int rv = 0; 996 997 switch (act) { 998 case DVACT_ACTIVATE: 999 return (EOPNOTSUPP); 1000 1001 case DVACT_DEACTIVATE: 1002 if (sc->sc_child != NULL) 1003 rv = config_deactivate(sc->sc_child); 1004 sc->sc_dying = 1; 1005 break; 1006 } 1007 return (rv); 1008 } 1009 1010 /* 1011 * Handle suspend/resume. 1012 * 1013 * We need to switch to polling mode here, because this routine is 1014 * called from an interrupt context. This is all right since we 1015 * are almost suspended anyway. 1016 */ 1017 void 1018 ehci_power(int why, void *v) 1019 { 1020 ehci_softc_t *sc = v; 1021 u_int32_t cmd, hcr; 1022 int s, i; 1023 1024 #ifdef EHCI_DEBUG 1025 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why)); 1026 if (ehcidebug > 0) 1027 ehci_dump_regs(sc); 1028 #endif 1029 1030 s = splhardusb(); 1031 switch (why) { 1032 case PWR_SUSPEND: 1033 case PWR_STANDBY: 1034 sc->sc_bus.use_polling++; 1035 1036 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1037 1038 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1039 EOWRITE4(sc, EHCI_USBCMD, cmd); 1040 1041 for (i = 0; i < 100; i++) { 1042 hcr = EOREAD4(sc, EHCI_USBSTS) & 1043 (EHCI_STS_ASS | EHCI_STS_PSS); 1044 if (hcr == 0) 1045 break; 1046 1047 usb_delay_ms(&sc->sc_bus, 1); 1048 } 1049 if (hcr != 0) { 1050 printf("%s: reset timeout\n", 1051 USBDEVNAME(sc->sc_bus.bdev)); 1052 } 1053 1054 cmd &= ~EHCI_CMD_RS; 1055 EOWRITE4(sc, EHCI_USBCMD, cmd); 1056 1057 for (i = 0; i < 100; i++) { 1058 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1059 if (hcr == EHCI_STS_HCH) 1060 break; 1061 1062 usb_delay_ms(&sc->sc_bus, 1); 1063 } 1064 if (hcr != EHCI_STS_HCH) { 1065 printf("%s: config timeout\n", 1066 USBDEVNAME(sc->sc_bus.bdev)); 1067 } 1068 1069 sc->sc_bus.use_polling--; 1070 break; 1071 1072 case PWR_RESUME: 1073 sc->sc_bus.use_polling++; 1074 1075 /* restore things in case the bios sucks */ 1076 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1077 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1078 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1079 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1080 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1081 1082 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1083 1084 for (i = 0; i < 100; i++) { 1085 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1086 if (hcr != EHCI_STS_HCH) 1087 break; 1088 1089 usb_delay_ms(&sc->sc_bus, 1); 1090 } 1091 if (hcr == EHCI_STS_HCH) { 1092 printf("%s: config timeout\n", 1093 USBDEVNAME(sc->sc_bus.bdev)); 1094 } 1095 1096 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1097 1098 sc->sc_bus.use_polling--; 1099 break; 1100 case PWR_SOFTSUSPEND: 1101 case PWR_SOFTSTANDBY: 1102 case PWR_SOFTRESUME: 1103 break; 1104 } 1105 splx(s); 1106 1107 #ifdef EHCI_DEBUG 1108 DPRINTF(("ehci_power: sc=%p\n", sc)); 1109 if (ehcidebug > 0) 1110 ehci_dump_regs(sc); 1111 #endif 1112 } 1113 1114 /* 1115 * Shut down the controller when the system is going down. 1116 */ 1117 void 1118 ehci_shutdown(void *v) 1119 { 1120 ehci_softc_t *sc = v; 1121 1122 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1123 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1124 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1125 } 1126 1127 usbd_status 1128 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1129 { 1130 struct ehci_softc *sc = (struct ehci_softc *)bus; 1131 usbd_status err; 1132 1133 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1134 if (err == USBD_NOMEM) 1135 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1136 #ifdef EHCI_DEBUG 1137 if (err) 1138 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1139 #endif 1140 return (err); 1141 } 1142 1143 void 1144 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1145 { 1146 struct ehci_softc *sc = (struct ehci_softc *)bus; 1147 1148 if (dma->block->flags & USB_DMA_RESERVE) { 1149 usb_reserve_freem(&((struct ehci_softc *)bus)->sc_dma_reserve, 1150 dma); 1151 return; 1152 } 1153 usb_freemem(&sc->sc_bus, dma); 1154 } 1155 1156 usbd_xfer_handle 1157 ehci_allocx(struct usbd_bus *bus) 1158 { 1159 struct ehci_softc *sc = (struct ehci_softc *)bus; 1160 usbd_xfer_handle xfer; 1161 1162 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1163 if (xfer != NULL) { 1164 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1165 #ifdef DIAGNOSTIC 1166 if (xfer->busy_free != XFER_FREE) { 1167 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1168 xfer->busy_free); 1169 } 1170 #endif 1171 } else { 1172 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1173 } 1174 if (xfer != NULL) { 1175 memset(xfer, 0, sizeof(struct ehci_xfer)); 1176 #ifdef DIAGNOSTIC 1177 EXFER(xfer)->isdone = 1; 1178 xfer->busy_free = XFER_BUSY; 1179 #endif 1180 } 1181 return (xfer); 1182 } 1183 1184 void 1185 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1186 { 1187 struct ehci_softc *sc = (struct ehci_softc *)bus; 1188 1189 #ifdef DIAGNOSTIC 1190 if (xfer->busy_free != XFER_BUSY) { 1191 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1192 xfer->busy_free); 1193 } 1194 xfer->busy_free = XFER_FREE; 1195 if (!EXFER(xfer)->isdone) { 1196 printf("ehci_freex: !isdone\n"); 1197 } 1198 #endif 1199 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1200 } 1201 1202 Static void 1203 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1204 { 1205 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1206 1207 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1208 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1209 #ifdef USB_DEBUG 1210 if (ehcidebug) 1211 usbd_dump_pipe(pipe); 1212 #endif 1213 epipe->nexttoggle = 0; 1214 } 1215 1216 Static void 1217 ehci_noop(usbd_pipe_handle pipe) 1218 { 1219 } 1220 1221 #ifdef EHCI_DEBUG 1222 void 1223 ehci_dump_regs(ehci_softc_t *sc) 1224 { 1225 int i; 1226 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1227 EOREAD4(sc, EHCI_USBCMD), 1228 EOREAD4(sc, EHCI_USBSTS), 1229 EOREAD4(sc, EHCI_USBINTR)); 1230 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1231 EOREAD4(sc, EHCI_FRINDEX), 1232 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1233 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1234 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1235 for (i = 1; i <= sc->sc_noport; i++) 1236 printf("port %d status=0x%08x\n", i, 1237 EOREAD4(sc, EHCI_PORTSC(i))); 1238 } 1239 1240 /* 1241 * Unused function - this is meant to be called from a kernel 1242 * debugger. 1243 */ 1244 void 1245 ehci_dump() 1246 { 1247 ehci_dump_regs(theehci); 1248 } 1249 1250 void 1251 ehci_dump_link(ehci_link_t link, int type) 1252 { 1253 link = le32toh(link); 1254 printf("0x%08x", link); 1255 if (link & EHCI_LINK_TERMINATE) 1256 printf("<T>"); 1257 else { 1258 printf("<"); 1259 if (type) { 1260 switch (EHCI_LINK_TYPE(link)) { 1261 case EHCI_LINK_ITD: printf("ITD"); break; 1262 case EHCI_LINK_QH: printf("QH"); break; 1263 case EHCI_LINK_SITD: printf("SITD"); break; 1264 case EHCI_LINK_FSTN: printf("FSTN"); break; 1265 } 1266 } 1267 printf(">"); 1268 } 1269 } 1270 1271 void 1272 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1273 { 1274 int i; 1275 u_int32_t stop; 1276 1277 stop = 0; 1278 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1279 ehci_dump_sqtd(sqtd); 1280 usb_syncmem(&sqtd->dma, 1281 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1282 sizeof(sqtd->qtd), 1283 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1284 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1285 usb_syncmem(&sqtd->dma, 1286 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1287 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1288 } 1289 if (sqtd) 1290 printf("dump aborted, too many TDs\n"); 1291 } 1292 1293 void 1294 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1295 { 1296 usb_syncmem(&sqtd->dma, sqtd->offs, 1297 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1298 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1299 ehci_dump_qtd(&sqtd->qtd); 1300 usb_syncmem(&sqtd->dma, sqtd->offs, 1301 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1302 } 1303 1304 void 1305 ehci_dump_qtd(ehci_qtd_t *qtd) 1306 { 1307 u_int32_t s; 1308 char sbuf[128]; 1309 1310 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1311 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1312 printf("\n"); 1313 s = le32toh(qtd->qtd_status); 1314 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1315 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1316 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1317 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1318 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1319 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1320 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1321 EHCI_QTD_GET_PID(s), sbuf); 1322 for (s = 0; s < 5; s++) 1323 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1324 } 1325 1326 void 1327 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1328 { 1329 ehci_qh_t *qh = &sqh->qh; 1330 u_int32_t endp, endphub; 1331 1332 usb_syncmem(&sqh->dma, sqh->offs, 1333 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1334 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1335 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1336 endp = le32toh(qh->qh_endp); 1337 printf(" endp=0x%08x\n", endp); 1338 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1339 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1340 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1341 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1342 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1343 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1344 EHCI_QH_GET_NRL(endp)); 1345 endphub = le32toh(qh->qh_endphub); 1346 printf(" endphub=0x%08x\n", endphub); 1347 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1348 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1349 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1350 EHCI_QH_GET_MULT(endphub)); 1351 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1352 printf("Overlay qTD:\n"); 1353 ehci_dump_qtd(&qh->qh_qtd); 1354 usb_syncmem(&sqh->dma, sqh->offs, 1355 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1356 } 1357 1358 #ifdef DIAGNOSTIC 1359 Static void 1360 ehci_dump_exfer(struct ehci_xfer *ex) 1361 { 1362 printf("ehci_dump_exfer: ex=%p\n", ex); 1363 } 1364 #endif 1365 #endif 1366 1367 usbd_status 1368 ehci_open(usbd_pipe_handle pipe) 1369 { 1370 usbd_device_handle dev = pipe->device; 1371 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 1372 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1373 u_int8_t addr = dev->address; 1374 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1375 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1376 ehci_soft_qh_t *sqh; 1377 usbd_status err; 1378 int s; 1379 int ival, speed, naks; 1380 int hshubaddr, hshubport; 1381 1382 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1383 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1384 1385 if (dev->myhsport) { 1386 hshubaddr = dev->myhsport->parent->address; 1387 hshubport = dev->myhsport->portno; 1388 } else { 1389 hshubaddr = 0; 1390 hshubport = 0; 1391 } 1392 1393 if (sc->sc_dying) 1394 return (USBD_IOERROR); 1395 1396 epipe->nexttoggle = 0; 1397 1398 if (addr == sc->sc_addr) { 1399 switch (ed->bEndpointAddress) { 1400 case USB_CONTROL_ENDPOINT: 1401 pipe->methods = &ehci_root_ctrl_methods; 1402 break; 1403 case UE_DIR_IN | EHCI_INTR_ENDPT: 1404 pipe->methods = &ehci_root_intr_methods; 1405 break; 1406 default: 1407 return (USBD_INVAL); 1408 } 1409 return (USBD_NORMAL_COMPLETION); 1410 } 1411 1412 /* XXX All this stuff is only valid for async. */ 1413 switch (dev->speed) { 1414 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1415 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1416 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1417 default: panic("ehci_open: bad device speed %d", dev->speed); 1418 } 1419 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1420 printf("%s: *** WARNING: opening low/full speed isoc device, " 1421 "this does not work yet.\n", 1422 USBDEVNAME(sc->sc_bus.bdev)); 1423 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1424 hshubaddr, hshubport)); 1425 return USBD_INVAL; 1426 } 1427 1428 naks = 8; /* XXX */ 1429 sqh = ehci_alloc_sqh(sc); 1430 if (sqh == NULL) 1431 return (USBD_NOMEM); 1432 /* qh_link filled when the QH is added */ 1433 sqh->qh.qh_endp = htole32( 1434 EHCI_QH_SET_ADDR(addr) | 1435 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1436 EHCI_QH_SET_EPS(speed) | 1437 EHCI_QH_DTC | 1438 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1439 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1440 EHCI_QH_CTL : 0) | 1441 EHCI_QH_SET_NRL(naks) 1442 ); 1443 sqh->qh.qh_endphub = htole32( 1444 EHCI_QH_SET_MULT(1) | 1445 EHCI_QH_SET_HUBA(hshubaddr) | 1446 EHCI_QH_SET_PORT(hshubport) | 1447 EHCI_QH_SET_CMASK(0x08) | /* XXX */ 1448 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1449 ); 1450 sqh->qh.qh_curqtd = EHCI_NULL; 1451 /* Fill the overlay qTD */ 1452 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1453 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1454 sqh->qh.qh_qtd.qtd_status = htole32(0); 1455 1456 usb_syncmem(&sqh->dma, sqh->offs, 1457 sizeof(sqh->qh), BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1458 epipe->sqh = sqh; 1459 1460 switch (xfertype) { 1461 case UE_CONTROL: 1462 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1463 0, &epipe->u.ctl.reqdma); 1464 #ifdef EHCI_DEBUG 1465 if (err) 1466 printf("ehci_open: usb_allocmem()=%d\n", err); 1467 #endif 1468 if (err) 1469 goto bad; 1470 pipe->methods = &ehci_device_ctrl_methods; 1471 s = splusb(); 1472 ehci_add_qh(sqh, sc->sc_async_head); 1473 splx(s); 1474 break; 1475 case UE_BULK: 1476 pipe->methods = &ehci_device_bulk_methods; 1477 s = splusb(); 1478 ehci_add_qh(sqh, sc->sc_async_head); 1479 splx(s); 1480 break; 1481 case UE_INTERRUPT: 1482 pipe->methods = &ehci_device_intr_methods; 1483 ival = pipe->interval; 1484 if (ival == USBD_DEFAULT_INTERVAL) { 1485 if (speed == EHCI_QH_SPEED_HIGH) { 1486 if (ed->bInterval > 16) { 1487 /* 1488 * illegal with high-speed, but there 1489 * were documentation bugs in the spec, 1490 * so be generous 1491 */ 1492 ival = 256; 1493 } else 1494 ival = (1 << (ed->bInterval - 1)) / 8; 1495 } else 1496 ival = ed->bInterval; 1497 } 1498 err = ehci_device_setintr(sc, sqh, ival); 1499 if (err) 1500 goto bad; 1501 break; 1502 case UE_ISOCHRONOUS: 1503 pipe->methods = &ehci_device_isoc_methods; 1504 /* FALLTHROUGH */ 1505 default: 1506 err = USBD_INVAL; 1507 goto bad; 1508 } 1509 return (USBD_NORMAL_COMPLETION); 1510 1511 bad: 1512 ehci_free_sqh(sc, sqh); 1513 return (err); 1514 } 1515 1516 /* 1517 * Add an ED to the schedule. Called at splusb(). 1518 */ 1519 void 1520 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1521 { 1522 SPLUSBCHECK; 1523 1524 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1525 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1526 sqh->next = head->next; 1527 sqh->qh.qh_link = head->qh.qh_link; 1528 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1529 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1530 head->next = sqh; 1531 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1532 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1533 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1534 1535 #ifdef EHCI_DEBUG 1536 if (ehcidebug > 5) { 1537 printf("ehci_add_qh:\n"); 1538 ehci_dump_sqh(sqh); 1539 } 1540 #endif 1541 } 1542 1543 /* 1544 * Remove an ED from the schedule. Called at splusb(). 1545 */ 1546 void 1547 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1548 { 1549 ehci_soft_qh_t *p; 1550 1551 SPLUSBCHECK; 1552 /* XXX */ 1553 for (p = head; p != NULL && p->next != sqh; p = p->next) 1554 ; 1555 if (p == NULL) 1556 panic("ehci_rem_qh: ED not found"); 1557 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1558 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1559 p->next = sqh->next; 1560 p->qh.qh_link = sqh->qh.qh_link; 1561 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1562 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1563 1564 ehci_sync_hc(sc); 1565 } 1566 1567 void 1568 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1569 { 1570 int i; 1571 u_int32_t status; 1572 1573 /* Save toggle bit and ping status. */ 1574 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1575 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1576 status = sqh->qh.qh_qtd.qtd_status & 1577 htole32(EHCI_QTD_TOGGLE_MASK | 1578 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1579 /* Set HALTED to make hw leave it alone. */ 1580 sqh->qh.qh_qtd.qtd_status = 1581 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1582 usb_syncmem(&sqh->dma, 1583 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1584 sizeof(sqh->qh.qh_qtd.qtd_status), 1585 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1586 sqh->qh.qh_curqtd = 0; 1587 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1588 sqh->qh.qh_qtd.qtd_altnext = 0; 1589 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1590 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1591 sqh->sqtd = sqtd; 1592 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1593 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1594 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1595 sqh->qh.qh_qtd.qtd_status = status; 1596 usb_syncmem(&sqh->dma, 1597 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1598 sizeof(sqh->qh.qh_qtd.qtd_status), 1599 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1600 } 1601 1602 /* 1603 * Ensure that the HC has released all references to the QH. We do this 1604 * by asking for a Async Advance Doorbell interrupt and then we wait for 1605 * the interrupt. 1606 * To make this easier we first obtain exclusive use of the doorbell. 1607 */ 1608 void 1609 ehci_sync_hc(ehci_softc_t *sc) 1610 { 1611 int s, error; 1612 1613 if (sc->sc_dying) { 1614 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1615 return; 1616 } 1617 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1618 usb_lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE, NULL); /* get doorbell */ 1619 s = splhardusb(); 1620 /* ask for doorbell */ 1621 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1622 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1623 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1624 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1625 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1626 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1627 splx(s); 1628 usb_lockmgr(&sc->sc_doorbell_lock, LK_RELEASE, NULL); /* release doorbell */ 1629 #ifdef DIAGNOSTIC 1630 if (error) 1631 printf("ehci_sync_hc: tsleep() = %d\n", error); 1632 #endif 1633 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1634 } 1635 1636 /***********/ 1637 1638 /* 1639 * Data structures and routines to emulate the root hub. 1640 */ 1641 Static usb_device_descriptor_t ehci_devd = { 1642 USB_DEVICE_DESCRIPTOR_SIZE, 1643 UDESC_DEVICE, /* type */ 1644 {0x00, 0x02}, /* USB version */ 1645 UDCLASS_HUB, /* class */ 1646 UDSUBCLASS_HUB, /* subclass */ 1647 UDPROTO_HSHUBSTT, /* protocol */ 1648 64, /* max packet */ 1649 {0},{0},{0x00,0x01}, /* device id */ 1650 1,2,0, /* string indicies */ 1651 1 /* # of configurations */ 1652 }; 1653 1654 Static usb_device_qualifier_t ehci_odevd = { 1655 USB_DEVICE_DESCRIPTOR_SIZE, 1656 UDESC_DEVICE_QUALIFIER, /* type */ 1657 {0x00, 0x02}, /* USB version */ 1658 UDCLASS_HUB, /* class */ 1659 UDSUBCLASS_HUB, /* subclass */ 1660 UDPROTO_FSHUB, /* protocol */ 1661 64, /* max packet */ 1662 1, /* # of configurations */ 1663 0 1664 }; 1665 1666 Static usb_config_descriptor_t ehci_confd = { 1667 USB_CONFIG_DESCRIPTOR_SIZE, 1668 UDESC_CONFIG, 1669 {USB_CONFIG_DESCRIPTOR_SIZE + 1670 USB_INTERFACE_DESCRIPTOR_SIZE + 1671 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1672 1, 1673 1, 1674 0, 1675 UC_SELF_POWERED, 1676 0 /* max power */ 1677 }; 1678 1679 Static usb_interface_descriptor_t ehci_ifcd = { 1680 USB_INTERFACE_DESCRIPTOR_SIZE, 1681 UDESC_INTERFACE, 1682 0, 1683 0, 1684 1, 1685 UICLASS_HUB, 1686 UISUBCLASS_HUB, 1687 UIPROTO_HSHUBSTT, 1688 0 1689 }; 1690 1691 Static usb_endpoint_descriptor_t ehci_endpd = { 1692 USB_ENDPOINT_DESCRIPTOR_SIZE, 1693 UDESC_ENDPOINT, 1694 UE_DIR_IN | EHCI_INTR_ENDPT, 1695 UE_INTERRUPT, 1696 {8, 0}, /* max packet */ 1697 12 1698 }; 1699 1700 Static usb_hub_descriptor_t ehci_hubd = { 1701 USB_HUB_DESCRIPTOR_SIZE, 1702 UDESC_HUB, 1703 0, 1704 {0,0}, 1705 0, 1706 0, 1707 {""}, 1708 {""}, 1709 }; 1710 1711 Static int 1712 ehci_str(usb_string_descriptor_t *p, int l, const char *s) 1713 { 1714 int i; 1715 1716 if (l == 0) 1717 return (0); 1718 p->bLength = 2 * strlen(s) + 2; 1719 if (l == 1) 1720 return (1); 1721 p->bDescriptorType = UDESC_STRING; 1722 l -= 2; 1723 for (i = 0; s[i] && l > 1; i++, l -= 2) 1724 USETW2(p->bString[i], 0, s[i]); 1725 return (2*i+2); 1726 } 1727 1728 /* 1729 * Simulate a hardware hub by handling all the necessary requests. 1730 */ 1731 Static usbd_status 1732 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1733 { 1734 usbd_status err; 1735 1736 /* Insert last in queue. */ 1737 err = usb_insert_transfer(xfer); 1738 if (err) 1739 return (err); 1740 1741 /* Pipe isn't running, start first */ 1742 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1743 } 1744 1745 Static usbd_status 1746 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1747 { 1748 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 1749 usb_device_request_t *req; 1750 void *buf = NULL; 1751 int port, i; 1752 int s, len, value, index, l, totlen = 0; 1753 usb_port_status_t ps; 1754 usb_hub_descriptor_t hubd; 1755 usbd_status err; 1756 u_int32_t v; 1757 1758 if (sc->sc_dying) 1759 return (USBD_IOERROR); 1760 1761 #ifdef DIAGNOSTIC 1762 if (!(xfer->rqflags & URQ_REQUEST)) 1763 /* XXX panic */ 1764 return (USBD_INVAL); 1765 #endif 1766 req = &xfer->request; 1767 1768 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1769 req->bmRequestType, req->bRequest)); 1770 1771 len = UGETW(req->wLength); 1772 value = UGETW(req->wValue); 1773 index = UGETW(req->wIndex); 1774 1775 if (len != 0) 1776 buf = KERNADDR(&xfer->dmabuf, 0); 1777 1778 #define C(x,y) ((x) | ((y) << 8)) 1779 switch(C(req->bRequest, req->bmRequestType)) { 1780 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1781 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1782 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1783 /* 1784 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1785 * for the integrated root hub. 1786 */ 1787 break; 1788 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1789 if (len > 0) { 1790 *(u_int8_t *)buf = sc->sc_conf; 1791 totlen = 1; 1792 } 1793 break; 1794 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1795 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 1796 if (len == 0) 1797 break; 1798 switch(value >> 8) { 1799 case UDESC_DEVICE: 1800 if ((value & 0xff) != 0) { 1801 err = USBD_IOERROR; 1802 goto ret; 1803 } 1804 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1805 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1806 memcpy(buf, &ehci_devd, l); 1807 break; 1808 /* 1809 * We can't really operate at another speed, but the spec says 1810 * we need this descriptor. 1811 */ 1812 case UDESC_DEVICE_QUALIFIER: 1813 if ((value & 0xff) != 0) { 1814 err = USBD_IOERROR; 1815 goto ret; 1816 } 1817 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1818 memcpy(buf, &ehci_odevd, l); 1819 break; 1820 /* 1821 * We can't really operate at another speed, but the spec says 1822 * we need this descriptor. 1823 */ 1824 case UDESC_OTHER_SPEED_CONFIGURATION: 1825 case UDESC_CONFIG: 1826 if ((value & 0xff) != 0) { 1827 err = USBD_IOERROR; 1828 goto ret; 1829 } 1830 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1831 memcpy(buf, &ehci_confd, l); 1832 ((usb_config_descriptor_t *)buf)->bDescriptorType = 1833 value >> 8; 1834 buf = (char *)buf + l; 1835 len -= l; 1836 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1837 totlen += l; 1838 memcpy(buf, &ehci_ifcd, l); 1839 buf = (char *)buf + l; 1840 len -= l; 1841 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1842 totlen += l; 1843 memcpy(buf, &ehci_endpd, l); 1844 break; 1845 case UDESC_STRING: 1846 *(u_int8_t *)buf = 0; 1847 totlen = 1; 1848 switch (value & 0xff) { 1849 case 0: /* Language table */ 1850 totlen = ehci_str(buf, len, "\001"); 1851 break; 1852 case 1: /* Vendor */ 1853 totlen = ehci_str(buf, len, sc->sc_vendor); 1854 break; 1855 case 2: /* Product */ 1856 totlen = ehci_str(buf, len, "EHCI root hub"); 1857 break; 1858 } 1859 break; 1860 default: 1861 err = USBD_IOERROR; 1862 goto ret; 1863 } 1864 break; 1865 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1866 if (len > 0) { 1867 *(u_int8_t *)buf = 0; 1868 totlen = 1; 1869 } 1870 break; 1871 case C(UR_GET_STATUS, UT_READ_DEVICE): 1872 if (len > 1) { 1873 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1874 totlen = 2; 1875 } 1876 break; 1877 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1878 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1879 if (len > 1) { 1880 USETW(((usb_status_t *)buf)->wStatus, 0); 1881 totlen = 2; 1882 } 1883 break; 1884 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1885 if (value >= USB_MAX_DEVICES) { 1886 err = USBD_IOERROR; 1887 goto ret; 1888 } 1889 sc->sc_addr = value; 1890 break; 1891 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1892 if (value != 0 && value != 1) { 1893 err = USBD_IOERROR; 1894 goto ret; 1895 } 1896 sc->sc_conf = value; 1897 break; 1898 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1899 break; 1900 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1901 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1902 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1903 err = USBD_IOERROR; 1904 goto ret; 1905 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1906 break; 1907 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1908 break; 1909 /* Hub requests */ 1910 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1911 break; 1912 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1913 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 1914 "port=%d feature=%d\n", 1915 index, value)); 1916 if (index < 1 || index > sc->sc_noport) { 1917 err = USBD_IOERROR; 1918 goto ret; 1919 } 1920 port = EHCI_PORTSC(index); 1921 v = EOREAD4(sc, port); 1922 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 1923 v &= ~EHCI_PS_CLEAR; 1924 switch(value) { 1925 case UHF_PORT_ENABLE: 1926 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 1927 break; 1928 case UHF_PORT_SUSPEND: 1929 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 1930 break; 1931 case UHF_PORT_POWER: 1932 if (sc->sc_hasppc) 1933 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 1934 break; 1935 case UHF_PORT_TEST: 1936 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 1937 "%d\n", index)); 1938 break; 1939 case UHF_PORT_INDICATOR: 1940 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 1941 "%d\n", index)); 1942 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 1943 break; 1944 case UHF_C_PORT_CONNECTION: 1945 EOWRITE4(sc, port, v | EHCI_PS_CSC); 1946 break; 1947 case UHF_C_PORT_ENABLE: 1948 EOWRITE4(sc, port, v | EHCI_PS_PEC); 1949 break; 1950 case UHF_C_PORT_SUSPEND: 1951 /* how? */ 1952 break; 1953 case UHF_C_PORT_OVER_CURRENT: 1954 EOWRITE4(sc, port, v | EHCI_PS_OCC); 1955 break; 1956 case UHF_C_PORT_RESET: 1957 sc->sc_isreset[index] = 0; 1958 break; 1959 default: 1960 err = USBD_IOERROR; 1961 goto ret; 1962 } 1963 #if 0 1964 switch(value) { 1965 case UHF_C_PORT_CONNECTION: 1966 case UHF_C_PORT_ENABLE: 1967 case UHF_C_PORT_SUSPEND: 1968 case UHF_C_PORT_OVER_CURRENT: 1969 case UHF_C_PORT_RESET: 1970 /* Enable RHSC interrupt if condition is cleared. */ 1971 if ((OREAD4(sc, port) >> 16) == 0) 1972 ehci_pcd_able(sc, 1); 1973 break; 1974 default: 1975 break; 1976 } 1977 #endif 1978 break; 1979 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1980 if (len == 0) 1981 break; 1982 if ((value & 0xff) != 0) { 1983 err = USBD_IOERROR; 1984 goto ret; 1985 } 1986 hubd = ehci_hubd; 1987 hubd.bNbrPorts = sc->sc_noport; 1988 v = EOREAD4(sc, EHCI_HCSPARAMS); 1989 USETW(hubd.wHubCharacteristics, 1990 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 1991 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 1992 ? UHD_PORT_IND : 0); 1993 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 1994 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 1995 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 1996 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 1997 l = min(len, hubd.bDescLength); 1998 totlen = l; 1999 memcpy(buf, &hubd, l); 2000 break; 2001 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2002 if (len != 4) { 2003 err = USBD_IOERROR; 2004 goto ret; 2005 } 2006 memset(buf, 0, len); /* ? XXX */ 2007 totlen = len; 2008 break; 2009 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2010 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2011 index)); 2012 if (index < 1 || index > sc->sc_noport) { 2013 err = USBD_IOERROR; 2014 goto ret; 2015 } 2016 if (len != 4) { 2017 err = USBD_IOERROR; 2018 goto ret; 2019 } 2020 v = EOREAD4(sc, EHCI_PORTSC(index)); 2021 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2022 v)); 2023 i = UPS_HIGH_SPEED; 2024 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2025 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2026 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2027 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2028 if (v & EHCI_PS_PR) i |= UPS_RESET; 2029 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2030 USETW(ps.wPortStatus, i); 2031 i = 0; 2032 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2033 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2034 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2035 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2036 USETW(ps.wPortChange, i); 2037 l = min(len, sizeof ps); 2038 memcpy(buf, &ps, l); 2039 totlen = l; 2040 break; 2041 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2042 err = USBD_IOERROR; 2043 goto ret; 2044 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2045 break; 2046 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2047 if (index < 1 || index > sc->sc_noport) { 2048 err = USBD_IOERROR; 2049 goto ret; 2050 } 2051 port = EHCI_PORTSC(index); 2052 v = EOREAD4(sc, port); 2053 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2054 v &= ~EHCI_PS_CLEAR; 2055 switch(value) { 2056 case UHF_PORT_ENABLE: 2057 EOWRITE4(sc, port, v | EHCI_PS_PE); 2058 break; 2059 case UHF_PORT_SUSPEND: 2060 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2061 break; 2062 case UHF_PORT_RESET: 2063 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2064 index)); 2065 if (EHCI_PS_IS_LOWSPEED(v)) { 2066 /* Low speed device, give up ownership. */ 2067 ehci_disown(sc, index, 1); 2068 break; 2069 } 2070 /* Start reset sequence. */ 2071 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2072 EOWRITE4(sc, port, v | EHCI_PS_PR); 2073 /* Wait for reset to complete. */ 2074 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2075 if (sc->sc_dying) { 2076 err = USBD_IOERROR; 2077 goto ret; 2078 } 2079 /* Terminate reset sequence. */ 2080 EOWRITE4(sc, port, v); 2081 /* Wait for HC to complete reset. */ 2082 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2083 if (sc->sc_dying) { 2084 err = USBD_IOERROR; 2085 goto ret; 2086 } 2087 v = EOREAD4(sc, port); 2088 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2089 if (v & EHCI_PS_PR) { 2090 printf("%s: port reset timeout\n", 2091 USBDEVNAME(sc->sc_bus.bdev)); 2092 return (USBD_TIMEOUT); 2093 } 2094 if (!(v & EHCI_PS_PE)) { 2095 /* Not a high speed device, give up ownership.*/ 2096 ehci_disown(sc, index, 0); 2097 break; 2098 } 2099 sc->sc_isreset[index] = 1; 2100 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2101 index, v)); 2102 break; 2103 case UHF_PORT_POWER: 2104 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2105 "%d (has PPC = %d)\n", index, 2106 sc->sc_hasppc)); 2107 if (sc->sc_hasppc) 2108 EOWRITE4(sc, port, v | EHCI_PS_PP); 2109 break; 2110 case UHF_PORT_TEST: 2111 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2112 "%d\n", index)); 2113 break; 2114 case UHF_PORT_INDICATOR: 2115 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2116 "%d\n", index)); 2117 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2118 break; 2119 default: 2120 err = USBD_IOERROR; 2121 goto ret; 2122 } 2123 break; 2124 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2125 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2126 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2127 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2128 break; 2129 default: 2130 err = USBD_IOERROR; 2131 goto ret; 2132 } 2133 xfer->actlen = totlen; 2134 err = USBD_NORMAL_COMPLETION; 2135 ret: 2136 xfer->status = err; 2137 s = splusb(); 2138 usb_transfer_complete(xfer); 2139 splx(s); 2140 return (USBD_IN_PROGRESS); 2141 } 2142 2143 void 2144 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2145 { 2146 int port; 2147 u_int32_t v; 2148 2149 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2150 #ifdef DIAGNOSTIC 2151 if (sc->sc_npcomp != 0) { 2152 int i = (index-1) / sc->sc_npcomp; 2153 if (i >= sc->sc_ncomp) 2154 printf("%s: strange port\n", 2155 USBDEVNAME(sc->sc_bus.bdev)); 2156 else 2157 printf("%s: handing over %s speed device on " 2158 "port %d to %s\n", 2159 USBDEVNAME(sc->sc_bus.bdev), 2160 lowspeed ? "low" : "full", 2161 index, USBDEVNAME(sc->sc_comps[i]->bdev)); 2162 } else { 2163 printf("%s: npcomp == 0\n", USBDEVNAME(sc->sc_bus.bdev)); 2164 } 2165 #endif 2166 port = EHCI_PORTSC(index); 2167 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2168 EOWRITE4(sc, port, v | EHCI_PS_PO); 2169 } 2170 2171 /* Abort a root control request. */ 2172 Static void 2173 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2174 { 2175 /* Nothing to do, all transfers are synchronous. */ 2176 } 2177 2178 /* Close the root pipe. */ 2179 Static void 2180 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2181 { 2182 DPRINTF(("ehci_root_ctrl_close\n")); 2183 /* Nothing to do. */ 2184 } 2185 2186 void 2187 ehci_root_intr_done(usbd_xfer_handle xfer) 2188 { 2189 xfer->hcpriv = NULL; 2190 } 2191 2192 Static usbd_status 2193 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2194 { 2195 usbd_status err; 2196 2197 /* Insert last in queue. */ 2198 err = usb_insert_transfer(xfer); 2199 if (err) 2200 return (err); 2201 2202 /* Pipe isn't running, start first */ 2203 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2204 } 2205 2206 Static usbd_status 2207 ehci_root_intr_start(usbd_xfer_handle xfer) 2208 { 2209 usbd_pipe_handle pipe = xfer->pipe; 2210 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2211 2212 if (sc->sc_dying) 2213 return (USBD_IOERROR); 2214 2215 sc->sc_intrxfer = xfer; 2216 2217 return (USBD_IN_PROGRESS); 2218 } 2219 2220 /* Abort a root interrupt request. */ 2221 Static void 2222 ehci_root_intr_abort(usbd_xfer_handle xfer) 2223 { 2224 int s; 2225 2226 if (xfer->pipe->intrxfer == xfer) { 2227 DPRINTF(("ehci_root_intr_abort: remove\n")); 2228 xfer->pipe->intrxfer = NULL; 2229 } 2230 xfer->status = USBD_CANCELLED; 2231 s = splusb(); 2232 usb_transfer_complete(xfer); 2233 splx(s); 2234 } 2235 2236 /* Close the root pipe. */ 2237 Static void 2238 ehci_root_intr_close(usbd_pipe_handle pipe) 2239 { 2240 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2241 2242 DPRINTF(("ehci_root_intr_close\n")); 2243 2244 sc->sc_intrxfer = NULL; 2245 } 2246 2247 void 2248 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2249 { 2250 xfer->hcpriv = NULL; 2251 } 2252 2253 /************************/ 2254 2255 ehci_soft_qh_t * 2256 ehci_alloc_sqh(ehci_softc_t *sc) 2257 { 2258 ehci_soft_qh_t *sqh; 2259 usbd_status err; 2260 int i, offs; 2261 usb_dma_t dma; 2262 2263 if (sc->sc_freeqhs == NULL) { 2264 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2265 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2266 EHCI_PAGE_SIZE, &dma); 2267 #ifdef EHCI_DEBUG 2268 if (err) 2269 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2270 #endif 2271 if (err) 2272 return (NULL); 2273 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2274 offs = i * EHCI_SQH_SIZE; 2275 sqh = KERNADDR(&dma, offs); 2276 sqh->physaddr = DMAADDR(&dma, offs); 2277 sqh->dma = dma; 2278 sqh->offs = offs; 2279 sqh->next = sc->sc_freeqhs; 2280 sc->sc_freeqhs = sqh; 2281 } 2282 } 2283 sqh = sc->sc_freeqhs; 2284 sc->sc_freeqhs = sqh->next; 2285 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2286 sqh->next = NULL; 2287 return (sqh); 2288 } 2289 2290 void 2291 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2292 { 2293 sqh->next = sc->sc_freeqhs; 2294 sc->sc_freeqhs = sqh; 2295 } 2296 2297 ehci_soft_qtd_t * 2298 ehci_alloc_sqtd(ehci_softc_t *sc) 2299 { 2300 ehci_soft_qtd_t *sqtd; 2301 usbd_status err; 2302 int i, offs; 2303 usb_dma_t dma; 2304 int s; 2305 2306 if (sc->sc_freeqtds == NULL) { 2307 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2308 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2309 EHCI_PAGE_SIZE, &dma); 2310 #ifdef EHCI_DEBUG 2311 if (err) 2312 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2313 #endif 2314 if (err) 2315 return (NULL); 2316 s = splusb(); 2317 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2318 offs = i * EHCI_SQTD_SIZE; 2319 sqtd = KERNADDR(&dma, offs); 2320 sqtd->physaddr = DMAADDR(&dma, offs); 2321 sqtd->dma = dma; 2322 sqtd->offs = offs; 2323 sqtd->nextqtd = sc->sc_freeqtds; 2324 sc->sc_freeqtds = sqtd; 2325 } 2326 splx(s); 2327 } 2328 2329 s = splusb(); 2330 sqtd = sc->sc_freeqtds; 2331 sc->sc_freeqtds = sqtd->nextqtd; 2332 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2333 sqtd->nextqtd = NULL; 2334 sqtd->xfer = NULL; 2335 splx(s); 2336 2337 return (sqtd); 2338 } 2339 2340 void 2341 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2342 { 2343 int s; 2344 2345 s = splusb(); 2346 sqtd->nextqtd = sc->sc_freeqtds; 2347 sc->sc_freeqtds = sqtd; 2348 splx(s); 2349 } 2350 2351 usbd_status 2352 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2353 int alen, int rd, usbd_xfer_handle xfer, 2354 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2355 { 2356 ehci_soft_qtd_t *next, *cur; 2357 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2358 u_int32_t qtdstatus; 2359 int len, curlen, mps; 2360 int i, tog; 2361 usb_dma_t *dma = &xfer->dmabuf; 2362 u_int16_t flags = xfer->flags; 2363 2364 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2365 2366 len = alen; 2367 dataphys = DMAADDR(dma, 0); 2368 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2369 qtdstatus = EHCI_QTD_ACTIVE | 2370 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2371 EHCI_QTD_SET_CERR(3) 2372 /* IOC set below */ 2373 /* BYTES set below */ 2374 ; 2375 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2376 tog = epipe->nexttoggle; 2377 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2378 2379 cur = ehci_alloc_sqtd(sc); 2380 *sp = cur; 2381 if (cur == NULL) 2382 goto nomem; 2383 2384 usb_syncmem(dma, 0, alen, 2385 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2386 for (;;) { 2387 dataphyspage = EHCI_PAGE(dataphys); 2388 /* The EHCI hardware can handle at most 5 pages. */ 2389 if (dataphyslastpage - dataphyspage < 2390 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2391 /* we can handle it in this QTD */ 2392 curlen = len; 2393 } else { 2394 /* must use multiple TDs, fill as much as possible. */ 2395 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2396 EHCI_PAGE_OFFSET(dataphys); 2397 #ifdef DIAGNOSTIC 2398 if (curlen > len) { 2399 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2400 "len=0x%x offs=0x%x\n", curlen, len, 2401 EHCI_PAGE_OFFSET(dataphys)); 2402 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2403 dataphyslastpage, dataphyspage, 2404 dataphys); 2405 curlen = len; 2406 } 2407 #endif 2408 /* the length must be a multiple of the max size */ 2409 curlen -= curlen % mps; 2410 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2411 "curlen=%d\n", curlen)); 2412 #ifdef DIAGNOSTIC 2413 if (curlen == 0) 2414 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2415 #endif 2416 } 2417 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2418 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2419 dataphys, dataphyslastpage, 2420 len, curlen)); 2421 len -= curlen; 2422 2423 /* 2424 * Allocate another transfer if there's more data left, 2425 * or if force last short transfer flag is set and we're 2426 * allocating a multiple of the max packet size. 2427 */ 2428 if (len != 0 || 2429 ((curlen % mps) == 0 && !rd && curlen != 0 && 2430 (flags & USBD_FORCE_SHORT_XFER))) { 2431 next = ehci_alloc_sqtd(sc); 2432 if (next == NULL) 2433 goto nomem; 2434 nextphys = htole32(next->physaddr); 2435 } else { 2436 next = NULL; 2437 nextphys = EHCI_NULL; 2438 } 2439 2440 for (i = 0; i * EHCI_PAGE_SIZE < 2441 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2442 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2443 if (i != 0) /* use offset only in first buffer */ 2444 a = EHCI_PAGE(a); 2445 cur->qtd.qtd_buffer[i] = htole32(a); 2446 cur->qtd.qtd_buffer_hi[i] = 0; 2447 #ifdef DIAGNOSTIC 2448 if (i >= EHCI_QTD_NBUFFERS) { 2449 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2450 goto nomem; 2451 } 2452 #endif 2453 } 2454 cur->nextqtd = next; 2455 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2456 cur->qtd.qtd_status = 2457 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2458 cur->xfer = xfer; 2459 cur->len = curlen; 2460 2461 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2462 dataphys, dataphys + curlen)); 2463 /* adjust the toggle based on the number of packets in this 2464 qtd */ 2465 if (((curlen + mps - 1) / mps) & 1) { 2466 tog ^= 1; 2467 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2468 } 2469 if (next == NULL) 2470 break; 2471 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2472 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2473 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2474 dataphys += curlen; 2475 cur = next; 2476 } 2477 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2478 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2479 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2480 *ep = cur; 2481 epipe->nexttoggle = tog; 2482 2483 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2484 *sp, *ep)); 2485 2486 return (USBD_NORMAL_COMPLETION); 2487 2488 nomem: 2489 /* XXX free chain */ 2490 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2491 return (USBD_NOMEM); 2492 } 2493 2494 Static void 2495 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2496 ehci_soft_qtd_t *sqtdend) 2497 { 2498 ehci_soft_qtd_t *p; 2499 int i; 2500 2501 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2502 sqtd, sqtdend)); 2503 2504 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2505 p = sqtd->nextqtd; 2506 ehci_free_sqtd(sc, sqtd); 2507 } 2508 } 2509 2510 /****************/ 2511 2512 /* 2513 * Close a reqular pipe. 2514 * Assumes that there are no pending transactions. 2515 */ 2516 void 2517 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2518 { 2519 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2520 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2521 ehci_soft_qh_t *sqh = epipe->sqh; 2522 int s; 2523 2524 s = splusb(); 2525 ehci_rem_qh(sc, sqh, head); 2526 splx(s); 2527 ehci_free_sqh(sc, epipe->sqh); 2528 } 2529 2530 /* 2531 * Abort a device request. 2532 * If this routine is called at splusb() it guarantees that the request 2533 * will be removed from the hardware scheduling and that the callback 2534 * for it will be called with USBD_CANCELLED status. 2535 * It's impossible to guarantee that the requested transfer will not 2536 * have happened since the hardware runs concurrently. 2537 * If the transaction has already happened we rely on the ordinary 2538 * interrupt processing to process it. 2539 * XXX This is most probably wrong. 2540 */ 2541 void 2542 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2543 { 2544 #define exfer EXFER(xfer) 2545 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2546 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2547 ehci_soft_qh_t *sqh = epipe->sqh; 2548 ehci_soft_qtd_t *sqtd; 2549 ehci_physaddr_t cur; 2550 u_int32_t qhstatus; 2551 int s; 2552 int hit; 2553 int wake; 2554 2555 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2556 2557 if (sc->sc_dying) { 2558 /* If we're dying, just do the software part. */ 2559 s = splusb(); 2560 xfer->status = status; /* make software ignore it */ 2561 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2562 usb_transfer_complete(xfer); 2563 splx(s); 2564 return; 2565 } 2566 2567 if (xfer->device->bus->intr_context || !curproc) 2568 panic("ehci_abort_xfer: not in process context"); 2569 2570 /* 2571 * If an abort is already in progress then just wait for it to 2572 * complete and return. 2573 */ 2574 if (xfer->hcflags & UXFER_ABORTING) { 2575 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2576 #ifdef DIAGNOSTIC 2577 if (status == USBD_TIMEOUT) 2578 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2579 #endif 2580 /* Override the status which might be USBD_TIMEOUT. */ 2581 xfer->status = status; 2582 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2583 xfer->hcflags |= UXFER_ABORTWAIT; 2584 while (xfer->hcflags & UXFER_ABORTING) 2585 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2586 return; 2587 } 2588 xfer->hcflags |= UXFER_ABORTING; 2589 2590 /* 2591 * Step 1: Make interrupt routine and hardware ignore xfer. 2592 */ 2593 s = splusb(); 2594 xfer->status = status; /* make software ignore it */ 2595 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2596 2597 usb_syncmem(&sqh->dma, 2598 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2599 sizeof(sqh->qh.qh_qtd.qtd_status), 2600 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2601 qhstatus = sqh->qh.qh_qtd.qtd_status; 2602 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2603 usb_syncmem(&sqh->dma, 2604 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2605 sizeof(sqh->qh.qh_qtd.qtd_status), 2606 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2607 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2608 usb_syncmem(&sqtd->dma, 2609 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2610 sizeof(sqtd->qtd.qtd_status), 2611 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2612 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2613 usb_syncmem(&sqtd->dma, 2614 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2615 sizeof(sqtd->qtd.qtd_status), 2616 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2617 if (sqtd == exfer->sqtdend) 2618 break; 2619 } 2620 splx(s); 2621 2622 /* 2623 * Step 2: Wait until we know hardware has finished any possible 2624 * use of the xfer. Also make sure the soft interrupt routine 2625 * has run. 2626 */ 2627 ehci_sync_hc(sc); 2628 s = splusb(); 2629 #ifdef USB_USE_SOFTINTR 2630 sc->sc_softwake = 1; 2631 #endif /* USB_USE_SOFTINTR */ 2632 usb_schedsoftintr(&sc->sc_bus); 2633 #ifdef USB_USE_SOFTINTR 2634 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2635 #endif /* USB_USE_SOFTINTR */ 2636 splx(s); 2637 2638 /* 2639 * Step 3: Remove any vestiges of the xfer from the hardware. 2640 * The complication here is that the hardware may have executed 2641 * beyond the xfer we're trying to abort. So as we're scanning 2642 * the TDs of this xfer we check if the hardware points to 2643 * any of them. 2644 */ 2645 s = splusb(); /* XXX why? */ 2646 2647 usb_syncmem(&sqh->dma, 2648 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2649 sizeof(sqh->qh.qh_curqtd), 2650 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2651 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2652 hit = 0; 2653 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2654 hit |= cur == sqtd->physaddr; 2655 if (sqtd == exfer->sqtdend) 2656 break; 2657 } 2658 sqtd = sqtd->nextqtd; 2659 /* Zap curqtd register if hardware pointed inside the xfer. */ 2660 if (hit && sqtd != NULL) { 2661 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 2662 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 2663 usb_syncmem(&sqh->dma, 2664 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2665 sizeof(sqh->qh.qh_curqtd), 2666 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2667 sqh->qh.qh_qtd.qtd_status = qhstatus; 2668 usb_syncmem(&sqh->dma, 2669 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2670 sizeof(sqh->qh.qh_qtd.qtd_status), 2671 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2672 } else { 2673 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2674 } 2675 2676 /* 2677 * Step 4: Execute callback. 2678 */ 2679 #ifdef DIAGNOSTIC 2680 exfer->isdone = 1; 2681 #endif 2682 wake = xfer->hcflags & UXFER_ABORTWAIT; 2683 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2684 usb_transfer_complete(xfer); 2685 if (wake) 2686 wakeup(&xfer->hcflags); 2687 2688 splx(s); 2689 #undef exfer 2690 } 2691 2692 void 2693 ehci_timeout(void *addr) 2694 { 2695 struct ehci_xfer *exfer = addr; 2696 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 2697 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2698 2699 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 2700 #ifdef USB_DEBUG 2701 if (ehcidebug > 1) 2702 usbd_dump_pipe(exfer->xfer.pipe); 2703 #endif 2704 2705 if (sc->sc_dying) { 2706 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 2707 return; 2708 } 2709 2710 /* Execute the abort in a process context. */ 2711 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 2712 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 2713 USB_TASKQ_HC); 2714 } 2715 2716 void 2717 ehci_timeout_task(void *addr) 2718 { 2719 usbd_xfer_handle xfer = addr; 2720 int s; 2721 2722 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 2723 2724 s = splusb(); 2725 ehci_abort_xfer(xfer, USBD_TIMEOUT); 2726 splx(s); 2727 } 2728 2729 /************************/ 2730 2731 Static usbd_status 2732 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 2733 { 2734 usbd_status err; 2735 2736 /* Insert last in queue. */ 2737 err = usb_insert_transfer(xfer); 2738 if (err) 2739 return (err); 2740 2741 /* Pipe isn't running, start first */ 2742 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2743 } 2744 2745 Static usbd_status 2746 ehci_device_ctrl_start(usbd_xfer_handle xfer) 2747 { 2748 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2749 usbd_status err; 2750 2751 if (sc->sc_dying) 2752 return (USBD_IOERROR); 2753 2754 #ifdef DIAGNOSTIC 2755 if (!(xfer->rqflags & URQ_REQUEST)) { 2756 /* XXX panic */ 2757 printf("ehci_device_ctrl_transfer: not a request\n"); 2758 return (USBD_INVAL); 2759 } 2760 #endif 2761 2762 err = ehci_device_request(xfer); 2763 if (err) 2764 return (err); 2765 2766 if (sc->sc_bus.use_polling) 2767 ehci_waitintr(sc, xfer); 2768 return (USBD_IN_PROGRESS); 2769 } 2770 2771 void 2772 ehci_device_ctrl_done(usbd_xfer_handle xfer) 2773 { 2774 struct ehci_xfer *ex = EXFER(xfer); 2775 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2776 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2777 usb_device_request_t *req = &xfer->request; 2778 int len = UGETW(req->wLength); 2779 int rd = req->bmRequestType & UT_READ; 2780 2781 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 2782 2783 #ifdef DIAGNOSTIC 2784 if (!(xfer->rqflags & URQ_REQUEST)) { 2785 panic("ehci_ctrl_done: not a request"); 2786 } 2787 #endif 2788 2789 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 2790 ehci_del_intr_list(ex); /* remove from active list */ 2791 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 2792 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 2793 BUS_DMASYNC_POSTWRITE); 2794 if (len) 2795 usb_syncmem(&xfer->dmabuf, 0, len, 2796 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2797 } 2798 2799 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 2800 } 2801 2802 /* Abort a device control request. */ 2803 Static void 2804 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 2805 { 2806 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 2807 ehci_abort_xfer(xfer, USBD_CANCELLED); 2808 } 2809 2810 /* Close a device control pipe. */ 2811 Static void 2812 ehci_device_ctrl_close(usbd_pipe_handle pipe) 2813 { 2814 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2815 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 2816 2817 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 2818 ehci_close_pipe(pipe, sc->sc_async_head); 2819 } 2820 2821 usbd_status 2822 ehci_device_request(usbd_xfer_handle xfer) 2823 { 2824 #define exfer EXFER(xfer) 2825 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2826 usb_device_request_t *req = &xfer->request; 2827 usbd_device_handle dev = epipe->pipe.device; 2828 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 2829 int addr = dev->address; 2830 ehci_soft_qtd_t *setup, *stat, *next; 2831 ehci_soft_qh_t *sqh; 2832 int isread; 2833 int len; 2834 usbd_status err; 2835 int s; 2836 2837 isread = req->bmRequestType & UT_READ; 2838 len = UGETW(req->wLength); 2839 2840 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 2841 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2842 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2843 UGETW(req->wIndex), len, addr, 2844 epipe->pipe.endpoint->edesc->bEndpointAddress)); 2845 2846 setup = ehci_alloc_sqtd(sc); 2847 if (setup == NULL) { 2848 err = USBD_NOMEM; 2849 goto bad1; 2850 } 2851 stat = ehci_alloc_sqtd(sc); 2852 if (stat == NULL) { 2853 err = USBD_NOMEM; 2854 goto bad2; 2855 } 2856 2857 sqh = epipe->sqh; 2858 epipe->u.ctl.length = len; 2859 2860 /* Update device address and length since they may have changed 2861 during the setup of the control pipe in usbd_new_device(). */ 2862 /* XXX This only needs to be done once, but it's too early in open. */ 2863 /* XXXX Should not touch ED here! */ 2864 sqh->qh.qh_endp = 2865 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 2866 htole32( 2867 EHCI_QH_SET_ADDR(addr) | 2868 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 2869 ); 2870 2871 /* Set up data transaction */ 2872 if (len != 0) { 2873 ehci_soft_qtd_t *end; 2874 2875 /* Start toggle at 1. */ 2876 epipe->nexttoggle = 1; 2877 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 2878 &next, &end); 2879 if (err) 2880 goto bad3; 2881 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 2882 end->nextqtd = stat; 2883 end->qtd.qtd_next = 2884 end->qtd.qtd_altnext = htole32(stat->physaddr); 2885 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 2886 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2887 } else { 2888 next = stat; 2889 } 2890 2891 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 2892 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 2893 2894 /* Clear toggle */ 2895 setup->qtd.qtd_status = htole32( 2896 EHCI_QTD_ACTIVE | 2897 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 2898 EHCI_QTD_SET_CERR(3) | 2899 EHCI_QTD_SET_TOGGLE(0) | 2900 EHCI_QTD_SET_BYTES(sizeof *req) 2901 ); 2902 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 2903 setup->qtd.qtd_buffer_hi[0] = 0; 2904 setup->nextqtd = next; 2905 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 2906 setup->xfer = xfer; 2907 setup->len = sizeof *req; 2908 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 2909 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2910 2911 stat->qtd.qtd_status = htole32( 2912 EHCI_QTD_ACTIVE | 2913 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 2914 EHCI_QTD_SET_CERR(3) | 2915 EHCI_QTD_SET_TOGGLE(1) | 2916 EHCI_QTD_IOC 2917 ); 2918 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 2919 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 2920 stat->nextqtd = NULL; 2921 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 2922 stat->xfer = xfer; 2923 stat->len = 0; 2924 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 2925 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2926 2927 #ifdef EHCI_DEBUG 2928 if (ehcidebug > 5) { 2929 DPRINTF(("ehci_device_request:\n")); 2930 ehci_dump_sqh(sqh); 2931 ehci_dump_sqtds(setup); 2932 } 2933 #endif 2934 2935 exfer->sqtdstart = setup; 2936 exfer->sqtdend = stat; 2937 #ifdef DIAGNOSTIC 2938 if (!exfer->isdone) { 2939 printf("ehci_device_request: not done, exfer=%p\n", exfer); 2940 } 2941 exfer->isdone = 0; 2942 #endif 2943 2944 /* Insert qTD in QH list. */ 2945 s = splusb(); 2946 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 2947 if (xfer->timeout && !sc->sc_bus.use_polling) { 2948 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 2949 ehci_timeout, xfer); 2950 } 2951 ehci_add_intr_list(sc, exfer); 2952 xfer->status = USBD_IN_PROGRESS; 2953 splx(s); 2954 2955 #ifdef EHCI_DEBUG 2956 if (ehcidebug > 10) { 2957 DPRINTF(("ehci_device_request: status=%x\n", 2958 EOREAD4(sc, EHCI_USBSTS))); 2959 delay(10000); 2960 ehci_dump_regs(sc); 2961 ehci_dump_sqh(sc->sc_async_head); 2962 ehci_dump_sqh(sqh); 2963 ehci_dump_sqtds(setup); 2964 } 2965 #endif 2966 2967 return (USBD_NORMAL_COMPLETION); 2968 2969 bad3: 2970 ehci_free_sqtd(sc, stat); 2971 bad2: 2972 ehci_free_sqtd(sc, setup); 2973 bad1: 2974 DPRINTFN(-1,("ehci_device_request: no memory\n")); 2975 xfer->status = err; 2976 usb_transfer_complete(xfer); 2977 return (err); 2978 #undef exfer 2979 } 2980 2981 /* 2982 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 2983 * qTD status, or miss signalling occasionally under heavy load. If the host 2984 * machine is too fast, we we can miss transaction completion - when we scan 2985 * the active list the transaction still seems to be active. This generally 2986 * exhibits itself as a umass stall that never recovers. 2987 * 2988 * We work around this behaviour by setting up this callback after any softintr 2989 * that completes with transactions still pending, giving us another chance to 2990 * check for completion after the writeback has taken place. 2991 */ 2992 void 2993 ehci_intrlist_timeout(void *arg) 2994 { 2995 ehci_softc_t *sc = arg; 2996 int s = splusb(); 2997 2998 DPRINTF(("ehci_intrlist_timeout\n")); 2999 usb_schedsoftintr(&sc->sc_bus); 3000 3001 splx(s); 3002 } 3003 3004 /************************/ 3005 3006 Static usbd_status 3007 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3008 { 3009 usbd_status err; 3010 3011 /* Insert last in queue. */ 3012 err = usb_insert_transfer(xfer); 3013 if (err) 3014 return (err); 3015 3016 /* Pipe isn't running, start first */ 3017 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3018 } 3019 3020 usbd_status 3021 ehci_device_bulk_start(usbd_xfer_handle xfer) 3022 { 3023 #define exfer EXFER(xfer) 3024 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3025 usbd_device_handle dev = epipe->pipe.device; 3026 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3027 ehci_soft_qtd_t *data, *dataend; 3028 ehci_soft_qh_t *sqh; 3029 usbd_status err; 3030 int len, isread, endpt; 3031 int s; 3032 3033 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3034 xfer, xfer->length, xfer->flags)); 3035 3036 if (sc->sc_dying) 3037 return (USBD_IOERROR); 3038 3039 #ifdef DIAGNOSTIC 3040 if (xfer->rqflags & URQ_REQUEST) 3041 panic("ehci_device_bulk_start: a request"); 3042 #endif 3043 3044 len = xfer->length; 3045 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3046 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3047 sqh = epipe->sqh; 3048 3049 epipe->u.bulk.length = len; 3050 3051 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3052 &dataend); 3053 if (err) { 3054 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3055 xfer->status = err; 3056 usb_transfer_complete(xfer); 3057 return (err); 3058 } 3059 3060 #ifdef EHCI_DEBUG 3061 if (ehcidebug > 5) { 3062 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3063 ehci_dump_sqh(sqh); 3064 ehci_dump_sqtds(data); 3065 } 3066 #endif 3067 3068 /* Set up interrupt info. */ 3069 exfer->sqtdstart = data; 3070 exfer->sqtdend = dataend; 3071 #ifdef DIAGNOSTIC 3072 if (!exfer->isdone) { 3073 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3074 } 3075 exfer->isdone = 0; 3076 #endif 3077 3078 s = splusb(); 3079 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3080 if (xfer->timeout && !sc->sc_bus.use_polling) { 3081 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3082 ehci_timeout, xfer); 3083 } 3084 ehci_add_intr_list(sc, exfer); 3085 xfer->status = USBD_IN_PROGRESS; 3086 splx(s); 3087 3088 #ifdef EHCI_DEBUG 3089 if (ehcidebug > 10) { 3090 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3091 delay(10000); 3092 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3093 ehci_dump_regs(sc); 3094 #if 0 3095 printf("async_head:\n"); 3096 ehci_dump_sqh(sc->sc_async_head); 3097 #endif 3098 printf("sqh:\n"); 3099 ehci_dump_sqh(sqh); 3100 ehci_dump_sqtds(data); 3101 } 3102 #endif 3103 3104 if (sc->sc_bus.use_polling) 3105 ehci_waitintr(sc, xfer); 3106 3107 return (USBD_IN_PROGRESS); 3108 #undef exfer 3109 } 3110 3111 Static void 3112 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3113 { 3114 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3115 ehci_abort_xfer(xfer, USBD_CANCELLED); 3116 } 3117 3118 /* 3119 * Close a device bulk pipe. 3120 */ 3121 Static void 3122 ehci_device_bulk_close(usbd_pipe_handle pipe) 3123 { 3124 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3125 3126 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3127 ehci_close_pipe(pipe, sc->sc_async_head); 3128 } 3129 3130 void 3131 ehci_device_bulk_done(usbd_xfer_handle xfer) 3132 { 3133 struct ehci_xfer *ex = EXFER(xfer); 3134 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3135 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3136 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3137 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3138 3139 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3140 xfer, xfer->actlen)); 3141 3142 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3143 ehci_del_intr_list(ex); /* remove from active list */ 3144 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3145 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3146 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3147 } 3148 3149 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3150 } 3151 3152 /************************/ 3153 3154 Static usbd_status 3155 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3156 { 3157 struct ehci_soft_islot *isp; 3158 int islot, lev; 3159 3160 /* Find a poll rate that is large enough. */ 3161 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3162 if (EHCI_ILEV_IVAL(lev) <= ival) 3163 break; 3164 3165 /* Pick an interrupt slot at the right level. */ 3166 /* XXX could do better than picking at random */ 3167 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3168 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3169 3170 sqh->islot = islot; 3171 isp = &sc->sc_islots[islot]; 3172 ehci_add_qh(sqh, isp->sqh); 3173 3174 return (USBD_NORMAL_COMPLETION); 3175 } 3176 3177 Static usbd_status 3178 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3179 { 3180 usbd_status err; 3181 3182 /* Insert last in queue. */ 3183 err = usb_insert_transfer(xfer); 3184 if (err) 3185 return (err); 3186 3187 /* 3188 * Pipe isn't running (otherwise err would be USBD_INPROG), 3189 * so start it first. 3190 */ 3191 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3192 } 3193 3194 Static usbd_status 3195 ehci_device_intr_start(usbd_xfer_handle xfer) 3196 { 3197 #define exfer EXFER(xfer) 3198 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3199 usbd_device_handle dev = xfer->pipe->device; 3200 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3201 ehci_soft_qtd_t *data, *dataend; 3202 ehci_soft_qh_t *sqh; 3203 usbd_status err; 3204 int len, isread, endpt; 3205 int s; 3206 3207 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3208 xfer, xfer->length, xfer->flags)); 3209 3210 if (sc->sc_dying) 3211 return (USBD_IOERROR); 3212 3213 #ifdef DIAGNOSTIC 3214 if (xfer->rqflags & URQ_REQUEST) 3215 panic("ehci_device_intr_start: a request"); 3216 #endif 3217 3218 len = xfer->length; 3219 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3220 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3221 sqh = epipe->sqh; 3222 3223 epipe->u.intr.length = len; 3224 3225 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3226 &dataend); 3227 if (err) { 3228 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3229 xfer->status = err; 3230 usb_transfer_complete(xfer); 3231 return (err); 3232 } 3233 3234 #ifdef EHCI_DEBUG 3235 if (ehcidebug > 5) { 3236 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3237 ehci_dump_sqh(sqh); 3238 ehci_dump_sqtds(data); 3239 } 3240 #endif 3241 3242 /* Set up interrupt info. */ 3243 exfer->sqtdstart = data; 3244 exfer->sqtdend = dataend; 3245 #ifdef DIAGNOSTIC 3246 if (!exfer->isdone) { 3247 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3248 } 3249 exfer->isdone = 0; 3250 #endif 3251 3252 s = splusb(); 3253 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3254 if (xfer->timeout && !sc->sc_bus.use_polling) { 3255 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3256 ehci_timeout, xfer); 3257 } 3258 ehci_add_intr_list(sc, exfer); 3259 xfer->status = USBD_IN_PROGRESS; 3260 splx(s); 3261 3262 #ifdef EHCI_DEBUG 3263 if (ehcidebug > 10) { 3264 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3265 delay(10000); 3266 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3267 ehci_dump_regs(sc); 3268 printf("sqh:\n"); 3269 ehci_dump_sqh(sqh); 3270 ehci_dump_sqtds(data); 3271 } 3272 #endif 3273 3274 if (sc->sc_bus.use_polling) 3275 ehci_waitintr(sc, xfer); 3276 3277 return (USBD_IN_PROGRESS); 3278 #undef exfer 3279 } 3280 3281 Static void 3282 ehci_device_intr_abort(usbd_xfer_handle xfer) 3283 { 3284 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3285 if (xfer->pipe->intrxfer == xfer) { 3286 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3287 xfer->pipe->intrxfer = NULL; 3288 } 3289 ehci_abort_xfer(xfer, USBD_CANCELLED); 3290 } 3291 3292 Static void 3293 ehci_device_intr_close(usbd_pipe_handle pipe) 3294 { 3295 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3296 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3297 struct ehci_soft_islot *isp; 3298 3299 isp = &sc->sc_islots[epipe->sqh->islot]; 3300 ehci_close_pipe(pipe, isp->sqh); 3301 } 3302 3303 Static void 3304 ehci_device_intr_done(usbd_xfer_handle xfer) 3305 { 3306 #define exfer EXFER(xfer) 3307 struct ehci_xfer *ex = EXFER(xfer); 3308 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3309 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3310 ehci_soft_qtd_t *data, *dataend; 3311 ehci_soft_qh_t *sqh; 3312 usbd_status err; 3313 int len, isread, endpt, s; 3314 3315 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3316 xfer, xfer->actlen)); 3317 3318 if (xfer->pipe->repeat) { 3319 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3320 3321 len = epipe->u.intr.length; 3322 xfer->length = len; 3323 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3324 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3325 usb_syncmem(&xfer->dmabuf, 0, len, 3326 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3327 sqh = epipe->sqh; 3328 3329 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3330 &data, &dataend); 3331 if (err) { 3332 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3333 xfer->status = err; 3334 return; 3335 } 3336 3337 /* Set up interrupt info. */ 3338 exfer->sqtdstart = data; 3339 exfer->sqtdend = dataend; 3340 #ifdef DIAGNOSTIC 3341 if (!exfer->isdone) { 3342 printf("ehci_device_intr_done: not done, ex=%p\n", 3343 exfer); 3344 } 3345 exfer->isdone = 0; 3346 #endif 3347 3348 s = splusb(); 3349 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3350 if (xfer->timeout && !sc->sc_bus.use_polling) { 3351 usb_callout(xfer->timeout_handle, 3352 mstohz(xfer->timeout), ehci_timeout, xfer); 3353 } 3354 splx(s); 3355 3356 xfer->status = USBD_IN_PROGRESS; 3357 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3358 ehci_del_intr_list(ex); /* remove from active list */ 3359 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3360 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3361 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3362 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3363 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3364 } 3365 #undef exfer 3366 } 3367 3368 /************************/ 3369 3370 Static usbd_status 3371 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3372 { 3373 return USBD_IOERROR; 3374 } 3375 Static usbd_status 3376 ehci_device_isoc_start(usbd_xfer_handle xfer) 3377 { 3378 return USBD_IOERROR; 3379 } 3380 Static void 3381 ehci_device_isoc_abort(usbd_xfer_handle xfer) 3382 { 3383 } 3384 Static void 3385 ehci_device_isoc_close(usbd_pipe_handle pipe) 3386 { 3387 } 3388 Static void 3389 ehci_device_isoc_done(usbd_xfer_handle xfer) 3390 { 3391 } 3392
Indexes created Thu Oct 02 01:09:59 GMT 2025