ehci.c revision 1.123.12.2
1 /* $NetBSD: ehci.c,v 1.123.12.2 2007/05/31 23:15:16 itohy Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2005, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 41 * 42 * The EHCI 1.0 spec can be found at 43 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 44 * and the USB 2.0 spec at 45 * http://www.usb.org/developers/docs/usb_20.zip 46 * 47 */ 48 49 /* 50 * TODO: 51 * 1) The EHCI driver lacks support for isochronous transfers, so 52 * devices using them don't work. 53 * 54 * 2) Interrupt transfer scheduling does not manage the time available 55 * in each frame, so it is possible for the transfers to overrun 56 * the end of the frame. 57 * 58 * 3) Command failures are not recovered correctly. 59 */ 60 61 #include <sys/cdefs.h> 62 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.123.12.2 2007/05/31 23:15:16 itohy Exp $"); 63 /* __FBSDID("$FreeBSD: /repoman/r/ncvs/src/sys/dev/usb/ehci.c,v 1.52 2006/10/19 01:15:58 iedowse Exp $"); */ 64 65 #if defined(__NetBSD__) || defined(__OpenBSD__) 66 #include "ohci.h" 67 #include "uhci.h" 68 #endif 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/kernel.h> 73 #include <sys/malloc.h> 74 #if defined(__NetBSD__) || defined(__OpenBSD__) 75 #include <sys/device.h> 76 #include <sys/select.h> 77 #elif defined(__FreeBSD__) 78 #include <sys/endian.h> 79 #include <sys/module.h> 80 #include <sys/bus.h> 81 #include <sys/lockmgr.h> 82 #if defined(DIAGNOSTIC) && defined(__i386__) && defined(__FreeBSD__) 83 #include <machine/cpu.h> 84 #endif 85 #endif 86 #include <sys/proc.h> 87 #include <sys/queue.h> 88 #include <sys/sysctl.h> 89 90 #include <machine/bus.h> 91 #include <machine/endian.h> 92 93 #include <dev/usb/usb.h> 94 #include <dev/usb/usbdi.h> 95 #include <dev/usb/usbdivar.h> 96 #include <dev/usb/usb_mem.h> 97 #include <dev/usb/usb_quirks.h> 98 99 #include <dev/usb/ehcireg.h> 100 #include <dev/usb/ehcivar.h> 101 102 #if defined(__FreeBSD__) 103 104 #define delay(d) DELAY(d) 105 #endif 106 107 #ifdef USB_DEBUG 108 /* #define EHCI_DEBUG USB_DEBUG */ 109 #define DPRINTF(x) do { if (ehcidebug) logprintf x; } while (0) 110 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) logprintf x; } while (0) 111 int ehcidebug = 0; 112 #ifdef __FreeBSD__ 113 SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 114 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW, 115 &ehcidebug, 0, "ehci debug level"); 116 #endif 117 #ifndef __NetBSD__ 118 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 119 #endif 120 #else 121 #define DPRINTF(x) 122 #define DPRINTFN(n,x) 123 #endif 124 125 struct ehci_pipe { 126 struct usbd_pipe pipe; 127 128 ehci_soft_qh_t *sqh; 129 union { 130 ehci_soft_qtd_t *qtd; 131 /* ehci_soft_itd_t *itd; */ 132 } tail; 133 union { 134 /* Control pipe */ 135 struct { 136 usb_dma_t reqdma; 137 u_int length; 138 } ctl; 139 /* Interrupt pipe */ 140 struct { 141 u_int length; 142 } intr; 143 /* Bulk pipe */ 144 struct { 145 u_int length; 146 } bulk; 147 /* Iso pipe */ 148 /* XXX */ 149 } u; 150 }; 151 152 Static usbd_status ehci_open(usbd_pipe_handle); 153 Static void ehci_poll(struct usbd_bus *); 154 Static void ehci_softintr(void *); 155 Static int ehci_intr1(ehci_softc_t *); 156 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 157 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 158 Static void ehci_idone(struct ehci_xfer *); 159 Static void ehci_timeout(void *); 160 Static void ehci_timeout_task(void *); 161 Static void ehci_intrlist_timeout(void *); 162 163 Static usbd_status ehci_prealloc(struct ehci_softc *, struct ehci_xfer *, 164 size_t, int); 165 Static usbd_status ehci_allocm(struct usbd_bus *, usbd_xfer_handle, 166 void *, size_t); 167 Static void ehci_freem(struct usbd_bus *, usbd_xfer_handle, 168 enum usbd_waitflg); 169 170 Static usbd_status ehci_map_alloc(usbd_xfer_handle); 171 Static void ehci_map_free(usbd_xfer_handle); 172 Static void ehci_mapm(usbd_xfer_handle, void *, size_t); 173 Static usbd_status ehci_mapm_mbuf(usbd_xfer_handle, struct mbuf *); 174 Static void ehci_unmapm(usbd_xfer_handle); 175 176 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *, usbd_pipe_handle, 177 enum usbd_waitflg); 178 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 179 180 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 181 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 182 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 183 Static void ehci_root_ctrl_close(usbd_pipe_handle); 184 Static void ehci_root_ctrl_done(usbd_xfer_handle); 185 186 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 187 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 188 Static void ehci_root_intr_abort(usbd_xfer_handle); 189 Static void ehci_root_intr_close(usbd_pipe_handle); 190 Static void ehci_root_intr_done(usbd_xfer_handle); 191 192 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 193 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 194 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 195 Static void ehci_device_ctrl_close(usbd_pipe_handle); 196 Static void ehci_device_ctrl_done(usbd_xfer_handle); 197 198 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 199 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 200 Static void ehci_device_bulk_abort(usbd_xfer_handle); 201 Static void ehci_device_bulk_close(usbd_pipe_handle); 202 Static void ehci_device_bulk_done(usbd_xfer_handle); 203 204 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 205 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 206 Static void ehci_device_intr_abort(usbd_xfer_handle); 207 Static void ehci_device_intr_close(usbd_pipe_handle); 208 Static void ehci_device_intr_done(usbd_xfer_handle); 209 210 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 211 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 212 Static void ehci_device_isoc_abort(usbd_xfer_handle); 213 Static void ehci_device_isoc_close(usbd_pipe_handle); 214 Static void ehci_device_isoc_done(usbd_xfer_handle); 215 216 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 217 Static void ehci_noop(usbd_pipe_handle pipe); 218 219 Static int ehci_str(usb_string_descriptor_t *, int, const char *); 220 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 221 Static void ehci_disown(ehci_softc_t *, int, int); 222 223 Static usbd_status ehci_grow_sqtd(ehci_softc_t *); 224 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 225 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 226 227 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 228 Static ehci_soft_qtd_t *ehci_alloc_sqtd_norsv(ehci_softc_t *); 229 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 230 Static void ehci_free_sqtd_norsv(ehci_softc_t *, ehci_soft_qtd_t *); 231 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 232 ehci_softc_t *, int, int, usbd_xfer_handle, 233 ehci_soft_qtd_t *, ehci_soft_qtd_t *, 234 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 235 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qh_t *, 236 ehci_soft_qtd_t *, ehci_soft_qtd_t *); 237 Static void ehci_free_desc_chunks(ehci_softc_t *, 238 struct ehci_mdescs *); 239 240 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 241 242 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 243 int ival); 244 245 Static void ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *, 246 ehci_soft_qh_t *); 247 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 248 ehci_soft_qh_t *); 249 Static void ehci_activate_qh(ehci_softc_t *, ehci_soft_qh_t *, 250 ehci_soft_qtd_t *); 251 Static void ehci_sync_hc(ehci_softc_t *); 252 253 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 254 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 255 256 #ifdef EHCI_DEBUG 257 Static void ehci_dump_regs(ehci_softc_t *); 258 void ehci_dump(void); 259 Static ehci_softc_t *theehci; 260 Static void ehci_dump_link(ehci_link_t, int); 261 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 262 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 263 Static void ehci_dump_qtd(ehci_qtd_t *); 264 Static void ehci_dump_sqh(ehci_soft_qh_t *); 265 #ifdef DIAGNOSTIC 266 Static void ehci_dump_exfer(struct ehci_xfer *); 267 #endif 268 #endif 269 270 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 271 272 #define EHCI_INTR_ENDPT 1 273 274 #define ehci_add_intr_list(sc, ex) \ 275 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext); 276 #define ehci_del_intr_list(ex) \ 277 do { \ 278 LIST_REMOVE((ex), inext); \ 279 (ex)->inext.le_prev = NULL; \ 280 } while (0) 281 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL) 282 283 Static const struct usbd_bus_methods ehci_bus_methods = { 284 ehci_open, 285 ehci_softintr, 286 ehci_poll, 287 ehci_allocm, 288 ehci_freem, 289 ehci_map_alloc, 290 ehci_map_free, 291 ehci_mapm, 292 ehci_mapm_mbuf, 293 ehci_unmapm, 294 ehci_allocx, 295 ehci_freex, 296 }; 297 298 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 299 ehci_root_ctrl_transfer, 300 ehci_root_ctrl_start, 301 ehci_root_ctrl_abort, 302 ehci_root_ctrl_close, 303 ehci_noop, 304 ehci_root_ctrl_done, 305 }; 306 307 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 308 ehci_root_intr_transfer, 309 ehci_root_intr_start, 310 ehci_root_intr_abort, 311 ehci_root_intr_close, 312 ehci_noop, 313 ehci_root_intr_done, 314 }; 315 316 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 317 ehci_device_ctrl_transfer, 318 ehci_device_ctrl_start, 319 ehci_device_ctrl_abort, 320 ehci_device_ctrl_close, 321 ehci_noop, 322 ehci_device_ctrl_done, 323 }; 324 325 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 326 ehci_device_intr_transfer, 327 ehci_device_intr_start, 328 ehci_device_intr_abort, 329 ehci_device_intr_close, 330 ehci_device_clear_toggle, 331 ehci_device_intr_done, 332 }; 333 334 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 335 ehci_device_bulk_transfer, 336 ehci_device_bulk_start, 337 ehci_device_bulk_abort, 338 ehci_device_bulk_close, 339 ehci_device_clear_toggle, 340 ehci_device_bulk_done, 341 }; 342 343 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 344 ehci_device_isoc_transfer, 345 ehci_device_isoc_start, 346 ehci_device_isoc_abort, 347 ehci_device_isoc_close, 348 ehci_noop, 349 ehci_device_isoc_done, 350 }; 351 352 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 353 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 354 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 355 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 356 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 357 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 358 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 359 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 360 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 361 }; 362 363 usbd_status 364 ehci_init(ehci_softc_t *sc) 365 { 366 u_int32_t vers, sparams, cparams, hcr; 367 u_int i; 368 usbd_status err; 369 ehci_soft_qh_t *sqh; 370 u_int ncomp; 371 int lev; 372 373 DPRINTF(("ehci_init: start\n")); 374 #ifdef EHCI_DEBUG 375 theehci = sc; 376 #endif 377 378 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 379 380 vers = EREAD2(sc, EHCI_HCIVERSION); 381 aprint_verbose("%s: EHCI version %x.%x\n", USBDEVNAME(sc->sc_bus.bdev), 382 vers >> 8, vers & 0xff); 383 384 sparams = EREAD4(sc, EHCI_HCSPARAMS); 385 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 386 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 387 ncomp = EHCI_HCS_N_CC(sparams); 388 if (ncomp != sc->sc_ncomp) { 389 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 390 USBDEVNAME(sc->sc_bus.bdev), 391 ncomp, sc->sc_ncomp); 392 if (ncomp < sc->sc_ncomp) 393 sc->sc_ncomp = ncomp; 394 } 395 if (sc->sc_ncomp > 0) { 396 printf("%s: companion controller%s, %d port%s each:", 397 USBDEVNAME(sc->sc_bus.bdev), sc->sc_ncomp!=1 ? "s" : "", 398 EHCI_HCS_N_PCC(sparams), 399 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 400 for (i = 0; i < sc->sc_ncomp; i++) 401 printf(" %s", USBDEVNAME(sc->sc_comps[i]->bdev)); 402 printf("\n"); 403 } 404 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 405 cparams = EREAD4(sc, EHCI_HCCPARAMS); 406 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 407 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 408 409 if (EHCI_HCC_64BIT(cparams)) { 410 /* MUST clear segment register if 64 bit capable. */ 411 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 412 } 413 414 sc->sc_bus.usbrev = USBREV_2_0; 415 usb_dma_tag_init(&sc->sc_dmatag); 416 417 /* Reset the controller */ 418 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 419 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 420 usb_delay_ms(&sc->sc_bus, 1); 421 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 422 for (i = 0; i < 100; i++) { 423 usb_delay_ms(&sc->sc_bus, 1); 424 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 425 if (!hcr) 426 break; 427 } 428 if (hcr) { 429 printf("%s: reset timeout\n", 430 USBDEVNAME(sc->sc_bus.bdev)); 431 return (USBD_IOERROR); 432 } 433 434 /* frame list size at default, read back what we got and use that */ 435 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 436 case 0: sc->sc_flsize = 1024; break; 437 case 1: sc->sc_flsize = 512; break; 438 case 2: sc->sc_flsize = 256; break; 439 case 3: return (USBD_IOERROR); 440 } 441 err = usb_allocmem(&sc->sc_dmatag, sc->sc_flsize * sizeof(ehci_link_t), 442 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 443 if (err) 444 return (err); 445 DPRINTF(("%s: flsize=%d\n", USBDEVNAME(sc->sc_bus.bdev),sc->sc_flsize)); 446 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 447 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 448 449 /* Set up the bus struct. */ 450 sc->sc_bus.methods = &ehci_bus_methods; 451 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 452 453 #if defined(__NetBSD__) || defined(__OpenBSD__) 454 sc->sc_powerhook = powerhook_establish(USBDEVNAME(sc->sc_bus.bdev), 455 ehci_power, sc); 456 sc->sc_shutdownhook = shutdownhook_establish(ehci_shutdown, sc); 457 #endif 458 459 sc->sc_eintrs = EHCI_NORMAL_INTRS; 460 461 /* 462 * Allocate the interrupt dummy QHs. These are arranged to give 463 * poll intervals that are powers of 2 times 1ms. 464 */ 465 for (i = 0; i < EHCI_INTRQHS; i++) { 466 sqh = ehci_alloc_sqh(sc); 467 if (sqh == NULL) { 468 err = USBD_NOMEM; 469 goto bad1; 470 } 471 sc->sc_islots[i].sqh = sqh; 472 } 473 lev = 0; 474 for (i = 0; i < EHCI_INTRQHS; i++) { 475 if (i == EHCI_IQHIDX(lev + 1, 0)) 476 lev++; 477 sqh = sc->sc_islots[i].sqh; 478 if (i == 0) { 479 /* The last (1ms) QH terminates. */ 480 sqh->qh.qh_link = EHCI_NULL; 481 sqh->next = NULL; 482 } else { 483 /* Otherwise the next QH has half the poll interval */ 484 sqh->next = 485 sc->sc_islots[EHCI_IQHIDX(lev - 1, i + 1)].sqh; 486 sqh->qh.qh_link = htole32(EHCI_SQH_DMAADDR(sqh->next) | 487 EHCI_LINK_QH); 488 } 489 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 490 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 491 sqh->qh.qh_curqtd = EHCI_NULL; 492 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 493 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 494 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 495 } 496 /* Point the frame list at the last level (128ms). */ 497 for (i = 0; i < sc->sc_flsize; i++) { 498 int j; 499 500 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 501 revbits[i & (EHCI_MAX_POLLRATE-1)]; 502 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 503 EHCI_SQH_DMAADDR(sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES 504 - 1, i)].sqh)); 505 } 506 EHCI_SQH_SYNC(sc, sqh, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 507 508 /* Allocate dummy QH that starts the async list. */ 509 sqh = ehci_alloc_sqh(sc); 510 if (sqh == NULL) { 511 err = USBD_NOMEM; 512 goto bad1; 513 } 514 /* Fill the QH */ 515 sqh->qh.qh_endp = 516 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 517 sqh->qh.qh_link = 518 htole32(EHCI_SQH_DMAADDR(sqh) | EHCI_LINK_QH); 519 sqh->qh.qh_curqtd = EHCI_NULL; 520 sqh->prev = sqh; /*It's a circular list.. */ 521 sqh->next = sqh; 522 /* Fill the overlay qTD */ 523 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 524 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 525 sqh->qh.qh_qtd.qtd_status = htole32(0); 526 #ifdef EHCI_DEBUG 527 if (ehcidebug) { 528 ehci_dump_sqh(sqh); 529 } 530 #endif 531 EHCI_SQH_SYNC(sc, sqh, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 532 533 /* Point to async list */ 534 sc->sc_async_head = sqh; 535 EOWRITE4(sc, EHCI_ASYNCLISTADDR, EHCI_SQH_DMAADDR(sqh) | EHCI_LINK_QH); 536 537 usb_callout_init(sc->sc_tmo_intrlist); 538 539 lockinit(&sc->sc_doorbell_lock, PZERO, "ehcidb", 0, 0); 540 541 /* Enable interrupts */ 542 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 543 544 /* Turn on controller */ 545 EOWRITE4(sc, EHCI_USBCMD, 546 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 547 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 548 EHCI_CMD_ASE | 549 EHCI_CMD_PSE | 550 EHCI_CMD_RS); 551 552 /* Take over port ownership */ 553 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 554 555 for (i = 0; i < 100; i++) { 556 usb_delay_ms(&sc->sc_bus, 1); 557 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 558 if (!hcr) 559 break; 560 } 561 if (hcr) { 562 printf("%s: run timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 563 return (USBD_IOERROR); 564 } 565 566 /* Enable interrupts */ 567 DPRINTFN(1,("ehci_init: enabling\n")); 568 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 569 570 return (USBD_NORMAL_COMPLETION); 571 572 #if 0 573 bad2: 574 ehci_free_sqh(sc, sc->sc_async_head); 575 #endif 576 bad1: 577 usb_freemem(&sc->sc_dmatag, &sc->sc_fldma); 578 usb_dma_tag_finish(&sc->sc_dmatag); 579 return (err); 580 } 581 582 int 583 ehci_intr(void *v) 584 { 585 ehci_softc_t *sc = v; 586 587 if (sc == NULL || sc->sc_dying) 588 return (0); 589 590 /* If we get an interrupt while polling, then just ignore it. */ 591 if (sc->sc_bus.use_polling) { 592 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 593 594 if (intrs) 595 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 596 #ifdef DIAGNOSTIC 597 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 598 #endif 599 return (0); 600 } 601 602 return (ehci_intr1(sc)); 603 } 604 605 Static int 606 ehci_intr1(ehci_softc_t *sc) 607 { 608 u_int32_t intrs, eintrs; 609 610 DPRINTFN(20,("ehci_intr1: enter\n")); 611 612 /* In case the interrupt occurs before initialization has completed. */ 613 if (sc == NULL) { 614 #ifdef DIAGNOSTIC 615 printf("ehci_intr1: sc == NULL\n"); 616 #endif 617 return (0); 618 } 619 620 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 621 if (!intrs) 622 return (0); 623 624 eintrs = intrs & sc->sc_eintrs; 625 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 626 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 627 (u_int)eintrs)); 628 if (!eintrs) 629 return (0); 630 631 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 632 sc->sc_bus.intr_context++; 633 sc->sc_bus.no_intrs++; 634 if (eintrs & EHCI_STS_IAA) { 635 DPRINTF(("ehci_intr1: door bell\n")); 636 wakeup(&sc->sc_async_head); 637 eintrs &= ~EHCI_STS_IAA; 638 } 639 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 640 DPRINTFN(5,("ehci_intr1: %s %s\n", 641 eintrs & EHCI_STS_INT ? "INT" : "", 642 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 643 usb_schedsoftintr(&sc->sc_bus); 644 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 645 } 646 if (eintrs & EHCI_STS_HSE) { 647 printf("%s: unrecoverable error, controller halted\n", 648 USBDEVNAME(sc->sc_bus.bdev)); 649 /* XXX what else */ 650 } 651 if (eintrs & EHCI_STS_PCD) { 652 ehci_pcd(sc, sc->sc_intrxfer); 653 eintrs &= ~EHCI_STS_PCD; 654 } 655 656 sc->sc_bus.intr_context--; 657 658 if (eintrs != 0) { 659 /* Block unprocessed interrupts. */ 660 sc->sc_eintrs &= ~eintrs; 661 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 662 printf("%s: blocking intrs 0x%x\n", 663 USBDEVNAME(sc->sc_bus.bdev), eintrs); 664 } 665 666 return (1); 667 } 668 669 670 void 671 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 672 { 673 usbd_pipe_handle pipe; 674 u_char *p; 675 int i, m; 676 677 if (xfer == NULL) { 678 /* Just ignore the change. */ 679 return; 680 } 681 682 pipe = xfer->pipe; 683 684 p = xfer->hcbuffer; 685 m = min(sc->sc_noport, xfer->length * 8 - 1); 686 memset(p, 0, xfer->length); 687 for (i = 1; i <= m; i++) { 688 /* Pick out CHANGE bits from the status reg. */ 689 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 690 p[i/8] |= 1 << (i%8); 691 } 692 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 693 xfer->actlen = xfer->length; 694 xfer->status = USBD_NORMAL_COMPLETION; 695 696 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 697 } 698 699 void 700 ehci_softintr(void *v) 701 { 702 ehci_softc_t *sc = v; 703 struct ehci_xfer *ex, *nextex; 704 705 DPRINTFN(10,("%s: ehci_softintr (%d)\n", USBDEVNAME(sc->sc_bus.bdev), 706 sc->sc_bus.intr_context)); 707 708 sc->sc_bus.intr_context++; 709 710 /* 711 * The only explanation I can think of for why EHCI is as brain dead 712 * as UHCI interrupt-wise is that Intel was involved in both. 713 * An interrupt just tells us that something is done, we have no 714 * clue what, so we need to scan through all active transfers. :-( 715 */ 716 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 717 nextex = LIST_NEXT(ex, inext); 718 ehci_check_intr(sc, ex); 719 } 720 721 /* Schedule a callout to catch any dropped transactions. */ 722 if ((sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) && 723 !LIST_EMPTY(&sc->sc_intrhead)) 724 usb_callout(sc->sc_tmo_intrlist, hz / 5, ehci_intrlist_timeout, 725 sc); 726 727 /* Schedule a callout to catch any dropped transactions. */ 728 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 729 !LIST_EMPTY(&sc->sc_intrhead)) 730 usb_callout(sc->sc_tmo_intrlist, hz, 731 ehci_intrlist_timeout, sc); 732 733 #ifdef USB_USE_SOFTINTR 734 if (sc->sc_softwake) { 735 sc->sc_softwake = 0; 736 wakeup(&sc->sc_softwake); 737 } 738 #endif /* USB_USE_SOFTINTR */ 739 740 sc->sc_bus.intr_context--; 741 } 742 743 /* Check for an interrupt. */ 744 void 745 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 746 { 747 ehci_soft_qtd_t *sqtd, *lsqtd; 748 u_int32_t status; 749 750 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 751 752 if (ex->sqtdstart == NULL) { 753 printf("ehci_check_intr: sqtdstart=NULL\n"); 754 return; 755 } 756 lsqtd = ex->sqtdend; 757 #ifdef DIAGNOSTIC 758 if (lsqtd == NULL) { 759 printf("ehci_check_intr: lsqtd==0\n"); 760 return; 761 } 762 #endif 763 /* 764 * If the last TD is still active we need to check whether there 765 * is a an error somewhere in the middle, or whether there was a 766 * short packet (SPD and not ACTIVE). 767 */ 768 EHCI_SQTD_SYNC(sc, lsqtd, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 769 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 770 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 771 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 772 EHCI_SQTD_SYNC(sc, sqtd, 773 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 774 status = le32toh(sqtd->qtd.qtd_status); 775 /* If there's an active QTD the xfer isn't done. */ 776 if (status & EHCI_QTD_ACTIVE) 777 break; 778 /* Any kind of error makes the xfer done. */ 779 if (status & EHCI_QTD_HALTED) 780 goto done; 781 /* We want short packets, and it is short: it's done */ 782 if (EHCI_QTD_GET_BYTES(status) != 0) 783 goto done; 784 } 785 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 786 ex, ex->sqtdstart)); 787 return; 788 } 789 done: 790 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 791 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 792 usb_rem_task(ex->xfer.pipe->device, &ex->abort_task); 793 ehci_idone(ex); 794 } 795 796 void 797 ehci_idone(struct ehci_xfer *ex) 798 { 799 usbd_xfer_handle xfer = &ex->xfer; 800 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 801 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 802 ehci_soft_qtd_t *sqtd, *lsqtd; 803 u_int32_t status = 0, nstatus = 0; 804 ehci_physaddr_t nextphys, altnextphys; 805 ehci_physaddr_t stdma; 806 int actlen, cerr; 807 808 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 809 #ifdef DIAGNOSTIC 810 { 811 int s = splhigh(); 812 if (ex->isdone) { 813 splx(s); 814 #ifdef EHCI_DEBUG 815 printf("ehci_idone: ex is done!\n "); 816 ehci_dump_exfer(ex); 817 #else 818 printf("ehci_idone: ex=%p is done!\n", ex); 819 #endif 820 return; 821 } 822 ex->isdone = 1; 823 splx(s); 824 } 825 #endif 826 827 if (xfer->status == USBD_CANCELLED || 828 xfer->status == USBD_TIMEOUT) { 829 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 830 return; 831 } 832 833 #ifdef EHCI_DEBUG 834 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 835 if (ehcidebug > 10) 836 ehci_dump_sqtds(ex->sqtdstart); 837 #endif 838 839 /* 840 * Make sure that the QH overlay qTD does not reference any 841 * of the qTDs we are about to free. This is probably only 842 * necessary if the transfer is marked as HALTED. 843 */ 844 EHCI_SQH_SYNC(sc, epipe->sqh, 845 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 846 nextphys = EHCI_LINK_ADDR(le32toh(epipe->sqh->qh.qh_qtd.qtd_next)); 847 altnextphys = 848 EHCI_LINK_ADDR(le32toh(epipe->sqh->qh.qh_qtd.qtd_altnext)); 849 for (sqtd = ex->sqtdstart; sqtd != ex->sqtdend->nextqtd; 850 sqtd = sqtd->nextqtd) { 851 stdma = EHCI_SQTD_DMAADDR(sqtd); 852 if (stdma == nextphys) { 853 epipe->sqh->qh.qh_qtd.qtd_next = 854 htole32(EHCI_SQTD_DMAADDR(ex->sqtdend->nextqtd)); 855 DPRINTFN(4, ("ehci_idone: updated overlay next ptr\n")); 856 EHCI_SQH_SYNC(sc, epipe->sqh, 857 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 858 859 } 860 if (stdma == altnextphys) { 861 DPRINTFN(4, 862 ("ehci_idone: updated overlay altnext ptr\n")); 863 epipe->sqh->qh.qh_qtd.qtd_altnext = 864 htole32(EHCI_SQTD_DMAADDR(ex->sqtdend->nextqtd)); 865 EHCI_SQH_SYNC(sc, epipe->sqh, 866 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 867 } 868 } 869 870 /* The transfer is done, compute actual length and status. */ 871 lsqtd = ex->sqtdend; 872 actlen = 0; 873 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd=sqtd->nextqtd) { 874 EHCI_SQTD_SYNC(sc, sqtd, 875 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 876 nstatus = le32toh(sqtd->qtd.qtd_status); 877 if (nstatus & EHCI_QTD_ACTIVE) 878 break; 879 880 status = nstatus; 881 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 882 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 883 } 884 885 cerr = EHCI_QTD_GET_CERR(status); 886 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, " 887 "status=0x%x\n", xfer->length, actlen, cerr, status)); 888 xfer->actlen = actlen; 889 if ((status & EHCI_QTD_HALTED) != 0) { 890 #ifdef EHCI_DEBUG 891 char sbuf[128]; 892 893 bitmask_snprintf((u_int32_t)status, 894 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 895 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 896 897 DPRINTFN(2, 898 ("ehci_idone: error, addr=%d, endpt=0x%02x, " 899 "status 0x%s\n", 900 xfer->pipe->device->address, 901 xfer->pipe->endpoint->edesc->bEndpointAddress, 902 sbuf)); 903 if (ehcidebug > 2) { 904 ehci_dump_sqh(epipe->sqh); 905 ehci_dump_sqtds(ex->sqtdstart); 906 } 907 #endif 908 /* low&full speed has an extra error flag */ 909 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 910 EHCI_QH_SPEED_HIGH) 911 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 912 else 913 status &= EHCI_QTD_STATERRS; 914 if (status == 0) /* no other errors means a stall */ 915 xfer->status = USBD_STALLED; 916 else 917 xfer->status = USBD_IOERROR; /* more info XXX */ 918 /* XXX need to reset TT on missed microframe */ 919 if (status & EHCI_QTD_MISSEDMICRO) { 920 printf("%s: missed microframe, TT reset not " 921 "implemented, hub might be inoperational\n", 922 USBDEVNAME(sc->sc_bus.bdev)); 923 } 924 } else { 925 xfer->status = USBD_NORMAL_COMPLETION; 926 } 927 928 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 929 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 930 } 931 932 /* 933 * Wait here until controller claims to have an interrupt. 934 * Then call ehci_intr and return. Use timeout to avoid waiting 935 * too long. 936 */ 937 void 938 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 939 { 940 int timo; 941 u_int32_t intrs; 942 943 xfer->status = USBD_IN_PROGRESS; 944 for (timo = xfer->timeout; timo >= 0; timo--) { 945 usb_delay_ms(&sc->sc_bus, 1); 946 if (sc->sc_dying) 947 break; 948 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 949 sc->sc_eintrs; 950 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 951 #ifdef EHCI_DEBUG 952 if (ehcidebug > 15) 953 ehci_dump_regs(sc); 954 #endif 955 if (intrs) { 956 ehci_intr1(sc); 957 if (xfer->status != USBD_IN_PROGRESS) 958 return; 959 } 960 } 961 962 /* Timeout */ 963 DPRINTF(("ehci_waitintr: timeout\n")); 964 xfer->status = USBD_TIMEOUT; 965 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 966 /* XXX should free TD */ 967 } 968 969 void 970 ehci_poll(struct usbd_bus *bus) 971 { 972 ehci_softc_t *sc = (ehci_softc_t *)bus; 973 #ifdef EHCI_DEBUG 974 static int last; 975 int new; 976 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 977 if (new != last) { 978 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 979 last = new; 980 } 981 #endif 982 983 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 984 ehci_intr1(sc); 985 } 986 987 int 988 ehci_detach(struct ehci_softc *sc, int flags) 989 { 990 int rv = 0; 991 usbd_xfer_handle xfer; 992 993 #if defined(__NetBSD__) || defined(__OpenBSD__) 994 if (sc->sc_child != NULL) 995 rv = config_detach(sc->sc_child, flags); 996 997 if (rv != 0) 998 return (rv); 999 #else 1000 sc->sc_dying = 1; 1001 #endif 1002 1003 if (sc->sc_bus.methods == NULL) 1004 return (rv); /* attach has been aborted */ 1005 1006 #if defined(__NetBSD__) || defined(__OpenBSD__) 1007 /* Don't touch hardware if it has already been gone. */ 1008 if ((flags & DETACH_FORCE) == 0) 1009 #endif 1010 { 1011 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1012 EOWRITE4(sc, EHCI_USBCMD, 0); 1013 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1014 } 1015 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 1016 1017 #if defined(__NetBSD__) || defined(__OpenBSD__) 1018 if (sc->sc_powerhook != NULL) 1019 powerhook_disestablish(sc->sc_powerhook); 1020 if (sc->sc_shutdownhook != NULL) 1021 shutdownhook_disestablish(sc->sc_shutdownhook); 1022 #endif 1023 1024 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1025 1026 usb_freemem(&sc->sc_dmatag, &sc->sc_fldma); 1027 /* XXX free other data structures XXX */ 1028 1029 while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 1030 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1031 usb_clean_buffer_dma(&sc->sc_dmatag, &EXFER(xfer)->dmabuf); 1032 free(xfer, M_USB); 1033 } 1034 ehci_free_desc_chunks(sc, &sc->sc_sqh_chunks); 1035 ehci_free_desc_chunks(sc, &sc->sc_sqtd_chunks); 1036 usb_dma_tag_finish(&sc->sc_dmatag); 1037 1038 return (rv); 1039 } 1040 1041 Static void 1042 ehci_free_desc_chunks(ehci_softc_t *sc, struct ehci_mdescs *c) 1043 { 1044 struct ehci_mem_desc *em; 1045 1046 while ((em = SIMPLEQ_FIRST(c)) != NULL) { 1047 SIMPLEQ_REMOVE_HEAD(c, em_next); 1048 usb_freemem(&sc->sc_dmatag, &em->em_dma); 1049 } 1050 } 1051 1052 #if defined(__NetBSD__) || defined(__OpenBSD__) 1053 int 1054 ehci_activate(device_t self, enum devact act) 1055 { 1056 struct ehci_softc *sc = (struct ehci_softc *)self; 1057 int rv = 0; 1058 1059 switch (act) { 1060 case DVACT_ACTIVATE: 1061 return (EOPNOTSUPP); 1062 1063 case DVACT_DEACTIVATE: 1064 if (sc->sc_child != NULL) 1065 rv = config_deactivate(sc->sc_child); 1066 sc->sc_dying = 1; 1067 break; 1068 } 1069 return (rv); 1070 } 1071 #endif 1072 1073 /* 1074 * Handle suspend/resume. 1075 * 1076 * We need to switch to polling mode here, because this routine is 1077 * called from an interrupt context. This is all right since we 1078 * are almost suspended anyway. 1079 */ 1080 void 1081 ehci_power(int why, void *v) 1082 { 1083 ehci_softc_t *sc = v; 1084 u_int32_t cmd, hcr; 1085 int s, i; 1086 1087 #ifdef EHCI_DEBUG 1088 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why)); 1089 if (ehcidebug > 0) 1090 ehci_dump_regs(sc); 1091 #endif 1092 1093 s = splhardusb(); 1094 switch (why) { 1095 USB_PWR_CASE_SUSPEND: 1096 sc->sc_bus.use_polling++; 1097 1098 for (i = 1; i <= sc->sc_noport; i++) { 1099 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1100 if ((cmd & EHCI_PS_PO) == 0 && 1101 (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1102 EOWRITE4(sc, EHCI_PORTSC(i), 1103 cmd | EHCI_PS_SUSP); 1104 } 1105 1106 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1107 1108 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1109 EOWRITE4(sc, EHCI_USBCMD, cmd); 1110 1111 for (i = 0; i < 100; i++) { 1112 hcr = EOREAD4(sc, EHCI_USBSTS) & 1113 (EHCI_STS_ASS | EHCI_STS_PSS); 1114 if (hcr == 0) 1115 break; 1116 1117 usb_delay_ms(&sc->sc_bus, 1); 1118 } 1119 if (hcr != 0) { 1120 printf("%s: reset timeout\n", 1121 USBDEVNAME(sc->sc_bus.bdev)); 1122 } 1123 1124 cmd &= ~EHCI_CMD_RS; 1125 EOWRITE4(sc, EHCI_USBCMD, cmd); 1126 1127 for (i = 0; i < 100; i++) { 1128 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1129 if (hcr == EHCI_STS_HCH) 1130 break; 1131 1132 usb_delay_ms(&sc->sc_bus, 1); 1133 } 1134 if (hcr != EHCI_STS_HCH) { 1135 printf("%s: config timeout\n", 1136 USBDEVNAME(sc->sc_bus.bdev)); 1137 } 1138 1139 sc->sc_bus.use_polling--; 1140 break; 1141 1142 USB_PWR_CASE_RESUME: 1143 sc->sc_bus.use_polling++; 1144 1145 /* restore things in case the bios sucks */ 1146 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1147 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1148 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1149 EHCI_SQH_DMAADDR(sc->sc_async_head) | EHCI_LINK_QH); 1150 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1151 1152 hcr = 0; 1153 for (i = 1; i <= sc->sc_noport; i++) { 1154 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1155 if ((cmd & EHCI_PS_PO) == 0 && 1156 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1157 EOWRITE4(sc, EHCI_PORTSC(i), 1158 cmd | EHCI_PS_FPR); 1159 hcr = 1; 1160 } 1161 } 1162 1163 if (hcr) { 1164 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1165 1166 for (i = 1; i <= sc->sc_noport; i++) { 1167 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1168 if ((cmd & EHCI_PS_PO) == 0 && 1169 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1170 EOWRITE4(sc, EHCI_PORTSC(i), 1171 cmd & ~EHCI_PS_FPR); 1172 } 1173 } 1174 1175 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1176 1177 for (i = 0; i < 100; i++) { 1178 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1179 if (hcr != EHCI_STS_HCH) 1180 break; 1181 1182 usb_delay_ms(&sc->sc_bus, 1); 1183 } 1184 if (hcr == EHCI_STS_HCH) { 1185 printf("%s: config timeout\n", 1186 USBDEVNAME(sc->sc_bus.bdev)); 1187 } 1188 1189 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1190 1191 sc->sc_bus.use_polling--; 1192 break; 1193 1194 default: 1195 break; 1196 } 1197 splx(s); 1198 1199 #ifdef EHCI_DEBUG 1200 DPRINTF(("ehci_power: sc=%p\n", sc)); 1201 if (ehcidebug > 0) 1202 ehci_dump_regs(sc); 1203 #endif 1204 } 1205 1206 /* 1207 * Shut down the controller when the system is going down. 1208 */ 1209 void 1210 ehci_shutdown(void *v) 1211 { 1212 ehci_softc_t *sc = v; 1213 1214 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1215 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1216 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1217 } 1218 1219 Static usbd_status 1220 ehci_prealloc(struct ehci_softc *sc, struct ehci_xfer *exfer, 1221 size_t bufsize, int nseg) 1222 { 1223 int seglen, ntd; 1224 int s; 1225 int err; 1226 1227 /* (over) estimate needed number of TDs */ 1228 seglen = 19520; /* 4096*5 - (4096*5 % maxp), when maxp = 976 */ 1229 ntd = bufsize / seglen + nseg; 1230 1231 s = splusb(); 1232 /* pre-allocate QDs */ 1233 /* XXX ITDs */ 1234 while (sc->sc_nfreeqtds < ntd) { 1235 DPRINTF(("%s: qhci_prealloc: need %d QTD (%d cur)\n", 1236 USBDEVNAME(sc->sc_bus.bdev), ntd, sc->sc_nfreeqtds)); 1237 if ((err = ehci_grow_sqtd(sc)) != USBD_NORMAL_COMPLETION) { 1238 splx(s); 1239 return err; 1240 } 1241 } 1242 sc->sc_nfreeqtds -= ntd; 1243 splx(s); 1244 1245 exfer->rsvd_tds = ntd; 1246 1247 return USBD_NORMAL_COMPLETION; 1248 } 1249 1250 usbd_status 1251 ehci_allocm(struct usbd_bus *bus, usbd_xfer_handle xfer, void *buf, size_t size) 1252 { 1253 struct ehci_softc *sc = (struct ehci_softc *)bus; 1254 struct ehci_xfer *exfer = EXFER(xfer); 1255 usbd_status err; 1256 1257 if ((err = usb_alloc_buffer_dma(&sc->sc_dmatag, &exfer->dmabuf, 1258 buf, size, &xfer->hcbuffer)) == USBD_NORMAL_COMPLETION) { 1259 if ((xfer->rqflags & URQ_DEV_MAP_PREPARED) == 0 && 1260 (err = ehci_prealloc(sc, exfer, size, 1261 USB_BUFFER_NSEGS(&exfer->dmabuf))) 1262 != USBD_NORMAL_COMPLETION) { 1263 usb_free_buffer_dma(&sc->sc_dmatag, &exfer->dmabuf, 1264 U_WAITOK); 1265 } 1266 } 1267 #ifdef EHCI_DEBUG 1268 if (err) 1269 printf("ehci_allocm: usb_alloc_buffer_dma()=%d\n", err); 1270 #endif 1271 return (err); 1272 } 1273 1274 void 1275 ehci_freem(struct usbd_bus *bus, usbd_xfer_handle xfer, 1276 enum usbd_waitflg waitflg) 1277 { 1278 struct ehci_softc *sc = (struct ehci_softc *)bus; 1279 struct ehci_xfer *exfer = EXFER(xfer); 1280 int s; 1281 1282 usb_free_buffer_dma(&sc->sc_dmatag, &exfer->dmabuf, waitflg); 1283 1284 /* XXX ITDs */ 1285 1286 s = splusb(); 1287 sc->sc_nfreeqtds += exfer->rsvd_tds; 1288 splx(s); 1289 exfer->rsvd_tds = 0; 1290 } 1291 1292 Static usbd_status 1293 ehci_map_alloc(usbd_xfer_handle xfer) 1294 { 1295 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1296 struct ehci_xfer *exfer = EXFER(xfer); 1297 usbd_status st; 1298 1299 st = usb_alloc_dma_resources(&sc->sc_dmatag, &exfer->dmabuf); 1300 if (st) 1301 return st; 1302 1303 if ((st = ehci_prealloc(sc, exfer, MAXPHYS, USB_DMA_NSEG))) { 1304 usb_free_dma_resources(&sc->sc_dmatag, &exfer->dmabuf); 1305 } 1306 1307 return st; 1308 } 1309 1310 Static void 1311 ehci_map_free(usbd_xfer_handle xfer) 1312 { 1313 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1314 struct ehci_xfer *exfer = EXFER(xfer); 1315 int s; 1316 1317 USB_KASSERT(xfer->rqflags & URQ_DEV_MAP_PREPARED); 1318 1319 usb_free_dma_resources(&sc->sc_dmatag, &exfer->dmabuf); 1320 1321 /* XXX ITDs */ 1322 1323 s = splusb(); 1324 sc->sc_nfreeqtds += exfer->rsvd_tds; 1325 splx(s); 1326 exfer->rsvd_tds = 0; 1327 } 1328 1329 Static void 1330 ehci_mapm(usbd_xfer_handle xfer, void *buf, size_t size) 1331 { 1332 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1333 struct ehci_xfer *exfer = EXFER(xfer); 1334 1335 usb_map_dma(&sc->sc_dmatag, &exfer->dmabuf, buf, size); 1336 } 1337 1338 Static usbd_status 1339 ehci_mapm_mbuf(usbd_xfer_handle xfer, struct mbuf *chain) 1340 { 1341 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1342 struct ehci_xfer *exfer = EXFER(xfer); 1343 1344 return (usb_map_mbuf_dma(&sc->sc_dmatag, &exfer->dmabuf, chain)); 1345 } 1346 1347 Static void 1348 ehci_unmapm(usbd_xfer_handle xfer) 1349 { 1350 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1351 struct ehci_xfer *exfer = EXFER(xfer); 1352 1353 usb_unmap_dma(&sc->sc_dmatag, &exfer->dmabuf); 1354 } 1355 1356 usbd_xfer_handle 1357 ehci_allocx(struct usbd_bus *bus, usbd_pipe_handle pipe, 1358 enum usbd_waitflg waitflg) 1359 { 1360 struct ehci_softc *sc = (struct ehci_softc *)bus; 1361 usbd_xfer_handle xfer; 1362 1363 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1364 if (xfer != NULL) { 1365 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1366 #ifdef DIAGNOSTIC 1367 if (xfer->busy_free != XFER_FREE) { 1368 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1369 xfer->busy_free); 1370 } 1371 #endif 1372 } else { 1373 xfer = malloc(sizeof(struct ehci_xfer), M_USB, 1374 waitflg == U_WAITOK ? M_WAITOK : M_NOWAIT); 1375 } 1376 if (xfer != NULL) { 1377 memset(xfer, 0, sizeof(struct ehci_xfer)); 1378 usb_init_task(&EXFER(xfer)->abort_task, ehci_timeout_task, 1379 xfer); 1380 EXFER(xfer)->ehci_xfer_flags = 0; 1381 EXFER(xfer)->rsvd_tds = 0; 1382 #ifdef DIAGNOSTIC 1383 EXFER(xfer)->isdone = 1; 1384 xfer->busy_free = XFER_BUSY; 1385 #endif 1386 } 1387 return (xfer); 1388 } 1389 1390 void 1391 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1392 { 1393 struct ehci_softc *sc = (struct ehci_softc *)bus; 1394 1395 #ifdef DIAGNOSTIC 1396 if (xfer->busy_free != XFER_BUSY) { 1397 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1398 xfer->busy_free); 1399 } 1400 xfer->busy_free = XFER_FREE; 1401 if (!EXFER(xfer)->isdone) { 1402 printf("ehci_freex: !isdone\n"); 1403 } 1404 #endif 1405 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1406 } 1407 1408 Static void 1409 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1410 { 1411 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1412 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 1413 1414 EHCI_SQH_SYNC(sc, epipe->sqh, 1415 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1416 1417 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1418 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1419 #ifdef USB_DEBUG 1420 if (ehcidebug) 1421 usbd_dump_pipe(pipe); 1422 #endif 1423 USB_KASSERT2((epipe->sqh->qh.qh_qtd.qtd_status & 1424 htole32(EHCI_QTD_ACTIVE)) == 0, 1425 ("ehci_device_clear_toggle: queue active")); 1426 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK); 1427 EHCI_SQH_SYNC(sc, epipe->sqh, 1428 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1429 } 1430 1431 Static void 1432 ehci_noop(usbd_pipe_handle pipe) 1433 { 1434 } 1435 1436 #ifdef EHCI_DEBUG 1437 void 1438 ehci_dump_regs(ehci_softc_t *sc) 1439 { 1440 int i; 1441 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1442 EOREAD4(sc, EHCI_USBCMD), 1443 EOREAD4(sc, EHCI_USBSTS), 1444 EOREAD4(sc, EHCI_USBINTR)); 1445 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1446 EOREAD4(sc, EHCI_FRINDEX), 1447 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1448 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1449 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1450 for (i = 1; i <= sc->sc_noport; i++) 1451 printf("port %d status=0x%08x\n", i, 1452 EOREAD4(sc, EHCI_PORTSC(i))); 1453 } 1454 1455 /* 1456 * Unused function - this is meant to be called from a kernel 1457 * debugger. 1458 */ 1459 void 1460 ehci_dump() 1461 { 1462 ehci_dump_regs(theehci); 1463 } 1464 1465 void 1466 ehci_dump_link(ehci_link_t link, int type) 1467 { 1468 link = le32toh(link); 1469 printf("0x%08x", link); 1470 if (link & EHCI_LINK_TERMINATE) 1471 printf("<T>"); 1472 else { 1473 printf("<"); 1474 if (type) { 1475 switch (EHCI_LINK_TYPE(link)) { 1476 case EHCI_LINK_ITD: printf("ITD"); break; 1477 case EHCI_LINK_QH: printf("QH"); break; 1478 case EHCI_LINK_SITD: printf("SITD"); break; 1479 case EHCI_LINK_FSTN: printf("FSTN"); break; 1480 } 1481 } 1482 printf(">"); 1483 } 1484 } 1485 1486 void 1487 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1488 { 1489 int i; 1490 u_int32_t stop; 1491 1492 stop = 0; 1493 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1494 ehci_dump_sqtd(sqtd); 1495 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1496 } 1497 if (sqtd) 1498 printf("dump aborted, too many TDs\n"); 1499 } 1500 1501 void 1502 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1503 { 1504 printf("QTD(%p) at 0x%08x:\n", sqtd, EHCI_SQTD_DMAADDR(sqtd)); 1505 ehci_dump_qtd(&sqtd->qtd); 1506 } 1507 1508 void 1509 ehci_dump_qtd(ehci_qtd_t *qtd) 1510 { 1511 u_int32_t s; 1512 char sbuf[128]; 1513 1514 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1515 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1516 printf("\n"); 1517 s = le32toh(qtd->qtd_status); 1518 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1519 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1520 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1521 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1522 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1523 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1524 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1525 EHCI_QTD_GET_PID(s), sbuf); 1526 for (s = 0; s < 5; s++) 1527 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1528 } 1529 1530 void 1531 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1532 { 1533 ehci_qh_t *qh = &sqh->qh; 1534 u_int32_t endp, endphub; 1535 1536 printf("QH(%p) at 0x%08x:\n", sqh, EHCI_SQH_DMAADDR(sqh)); 1537 printf(" sqtd=%p inactivesqtd=%p\n", sqh->sqtd, sqh->inactivesqtd); 1538 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1539 endp = le32toh(qh->qh_endp); 1540 printf(" endp=0x%08x\n", endp); 1541 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1542 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1543 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1544 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1545 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1546 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1547 EHCI_QH_GET_NRL(endp)); 1548 endphub = le32toh(qh->qh_endphub); 1549 printf(" endphub=0x%08x\n", endphub); 1550 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1551 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1552 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1553 EHCI_QH_GET_MULT(endphub)); 1554 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1555 printf("Overlay qTD:\n"); 1556 ehci_dump_qtd(&qh->qh_qtd); 1557 } 1558 1559 #ifdef DIAGNOSTIC 1560 Static void 1561 ehci_dump_exfer(struct ehci_xfer *ex) 1562 { 1563 printf("ehci_dump_exfer: ex=%p\n", ex); 1564 } 1565 #endif 1566 #endif 1567 1568 usbd_status 1569 ehci_open(usbd_pipe_handle pipe) 1570 { 1571 usbd_device_handle dev = pipe->device; 1572 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 1573 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1574 u_int8_t addr = dev->address; 1575 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1576 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1577 ehci_soft_qh_t *sqh; 1578 usbd_status err; 1579 int s; 1580 int ival, speed, naks; 1581 int hshubaddr, hshubport; 1582 1583 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1584 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1585 1586 if (dev->myhsport) { 1587 hshubaddr = dev->myhsport->parent->address; 1588 hshubport = dev->myhsport->portno; 1589 } else { 1590 hshubaddr = 0; 1591 hshubport = 0; 1592 } 1593 1594 if (sc->sc_dying) 1595 return (USBD_IOERROR); 1596 1597 if (addr == sc->sc_addr) { 1598 switch (ed->bEndpointAddress) { 1599 case USB_CONTROL_ENDPOINT: 1600 pipe->methods = &ehci_root_ctrl_methods; 1601 break; 1602 case UE_DIR_IN | EHCI_INTR_ENDPT: 1603 pipe->methods = &ehci_root_intr_methods; 1604 break; 1605 default: 1606 return (USBD_INVAL); 1607 } 1608 return (USBD_NORMAL_COMPLETION); 1609 } 1610 1611 /* XXX All this stuff is only valid for async. */ 1612 switch (dev->speed) { 1613 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1614 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1615 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1616 default: panic("ehci_open: bad device speed %d", dev->speed); 1617 } 1618 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1619 printf("%s: *** WARNING: opening low/full speed isoc device, " 1620 "this does not work yet.\n", 1621 USBDEVNAME(sc->sc_bus.bdev)); 1622 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1623 hshubaddr, hshubport)); 1624 return USBD_INVAL; 1625 } 1626 1627 naks = 8; /* XXX */ 1628 sqh = ehci_alloc_sqh(sc); 1629 if (sqh == NULL) 1630 return (USBD_NOMEM); 1631 /* qh_link filled when the QH is added */ 1632 sqh->qh.qh_endp = htole32( 1633 EHCI_QH_SET_ADDR(addr) | 1634 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1635 EHCI_QH_SET_EPS(speed) | 1636 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) | 1637 EHCI_QH_SET_MPL(UE_MAXPKTSZ(ed)) | 1638 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1639 EHCI_QH_CTL : 0) | 1640 EHCI_QH_SET_NRL(naks) 1641 ); 1642 sqh->qh.qh_endphub = htole32( 1643 EHCI_QH_SET_MULT(1) | 1644 EHCI_QH_SET_HUBA(hshubaddr) | 1645 EHCI_QH_SET_PORT(hshubport) | 1646 EHCI_QH_SET_CMASK(0x1c) | 1647 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0) 1648 ); 1649 sqh->qh.qh_curqtd = EHCI_NULL; 1650 /* The overlay qTD was already set up by ehci_alloc_sqh(). */ 1651 sqh->qh.qh_qtd.qtd_status = 1652 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle)); 1653 1654 epipe->sqh = sqh; 1655 1656 switch (xfertype) { 1657 case UE_CONTROL: 1658 err = usb_allocmem(&sc->sc_dmatag, sizeof(usb_device_request_t), 1659 0, &epipe->u.ctl.reqdma); 1660 #ifdef EHCI_DEBUG 1661 if (err) 1662 printf("ehci_open: usb_allocmem()=%d\n", err); 1663 #endif 1664 if (err) 1665 goto bad; 1666 pipe->methods = &ehci_device_ctrl_methods; 1667 s = splusb(); 1668 ehci_add_qh(sc, sqh, sc->sc_async_head); 1669 splx(s); 1670 break; 1671 case UE_BULK: 1672 pipe->methods = &ehci_device_bulk_methods; 1673 s = splusb(); 1674 ehci_add_qh(sc, sqh, sc->sc_async_head); 1675 splx(s); 1676 break; 1677 case UE_INTERRUPT: 1678 pipe->methods = &ehci_device_intr_methods; 1679 ival = pipe->interval; 1680 if (ival == USBD_DEFAULT_INTERVAL) { 1681 if (speed == EHCI_QH_SPEED_HIGH) { 1682 if (ed->bInterval > 16) { 1683 /* 1684 * illegal with high-speed, but there 1685 * were documentation bugs in the spec, 1686 * so be generous 1687 */ 1688 ival = 256; 1689 } else 1690 ival = (1 << (ed->bInterval - 1)) / 8; 1691 } else 1692 ival = ed->bInterval; 1693 } 1694 err = ehci_device_setintr(sc, sqh, ival); 1695 if (err) 1696 goto bad; 1697 break; 1698 case UE_ISOCHRONOUS: 1699 pipe->methods = &ehci_device_isoc_methods; 1700 /* FALLTHROUGH */ 1701 default: 1702 err = USBD_INVAL; 1703 goto bad; 1704 } 1705 return (USBD_NORMAL_COMPLETION); 1706 1707 bad: 1708 ehci_free_sqh(sc, sqh); 1709 return (err); 1710 } 1711 1712 /* 1713 * Add an ED to the schedule. Called at splusb(). 1714 * If in the async schedule, it will always have a next. 1715 * If in the intr schedule it may not. 1716 */ 1717 void 1718 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1719 { 1720 SPLUSBCHECK; 1721 1722 sqh->next = head->next; 1723 sqh->prev = head; 1724 sqh->qh.qh_link = head->qh.qh_link; 1725 EHCI_SQH_SYNC(sc, sqh, 1726 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1727 head->next = sqh; 1728 if (sqh->next) 1729 sqh->next->prev = sqh; 1730 head->qh.qh_link = htole32(EHCI_SQH_DMAADDR(sqh) | EHCI_LINK_QH); 1731 EHCI_SQH_SYNC(sc, head, 1732 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1733 1734 #ifdef EHCI_DEBUG 1735 if (ehcidebug > 5) { 1736 printf("ehci_add_qh:\n"); 1737 ehci_dump_sqh(sqh); 1738 } 1739 #endif 1740 } 1741 1742 /* 1743 * Remove an ED from the schedule. Called at splusb(). 1744 * Will always have a 'next' if it's in the async list as it's circular. 1745 */ 1746 void 1747 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1748 { 1749 SPLUSBCHECK; 1750 /* XXX */ 1751 sqh->prev->qh.qh_link = sqh->qh.qh_link; 1752 EHCI_SQH_SYNC(sc, sqh->prev, 1753 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1754 sqh->prev->next = sqh->next; 1755 if (sqh->next) 1756 sqh->next->prev = sqh->prev; 1757 ehci_sync_hc(sc); 1758 } 1759 1760 /* Restart a QH following the addition of a qTD. */ 1761 void 1762 ehci_activate_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1763 { 1764 ehci_physaddr_t qtddma; 1765 1766 EHCI_SQTD_SYNC(sc, sqtd, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1767 1768 USB_KASSERT2((sqtd->qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) == 0, 1769 ("ehci_activate_qh: already active")); 1770 1771 /* 1772 * When a QH is idle, the overlay qTD should be marked as not 1773 * halted and not active. This causes the host controller to 1774 * retrieve the real qTD on each pass (rather than just examinig 1775 * the overlay), so it will notice when we activate the qTD. 1776 */ 1777 if (sqtd == sqh->sqtd) { 1778 /* Check that the hardware is in the state we expect. */ 1779 qtddma = EHCI_SQTD_DMAADDR(sqtd); 1780 if (EHCI_LINK_ADDR(le32toh(sqh->qh.qh_qtd.qtd_next)) != 1781 qtddma) { 1782 #ifdef EHCI_DEBUG 1783 printf("ehci_activate_qh: unexpected next ptr\n"); 1784 ehci_dump_sqh(sqh); 1785 ehci_dump_sqtds(sqh->sqtd); 1786 #endif 1787 sqh->qh.qh_qtd.qtd_next = htole32(qtddma); 1788 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1789 } 1790 /* Ensure the flags are correct. */ 1791 sqh->qh.qh_qtd.qtd_status &= htole32(EHCI_QTD_PINGSTATE | 1792 EHCI_QTD_TOGGLE_MASK); 1793 EHCI_SQH_SYNC(sc, sqh, 1794 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1795 } 1796 1797 /* Now activate the qTD. */ 1798 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_ACTIVE); 1799 EHCI_SQTD_SYNC(sc, sqtd, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1800 } 1801 1802 /* 1803 * Ensure that the HC has released all references to the QH. We do this 1804 * by asking for a Async Advance Doorbell interrupt and then we wait for 1805 * the interrupt. 1806 * To make this easier we first obtain exclusive use of the doorbell. 1807 */ 1808 void 1809 ehci_sync_hc(ehci_softc_t *sc) 1810 { 1811 int s, error; 1812 1813 if (sc->sc_dying) { 1814 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1815 return; 1816 } 1817 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1818 /* get doorbell */ 1819 usb_lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE, NULL); 1820 s = splhardusb(); 1821 /* ask for doorbell */ 1822 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1823 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1824 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1825 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1826 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1827 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1828 splx(s); 1829 /* release doorbell */ 1830 usb_lockmgr(&sc->sc_doorbell_lock, LK_RELEASE, NULL); 1831 #ifdef DIAGNOSTIC 1832 if (error) 1833 printf("ehci_sync_hc: tsleep() = %d\n", error); 1834 #endif 1835 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1836 } 1837 1838 /***********/ 1839 1840 /* 1841 * Data structures and routines to emulate the root hub. 1842 */ 1843 Static usb_device_descriptor_t ehci_devd = { 1844 USB_DEVICE_DESCRIPTOR_SIZE, 1845 UDESC_DEVICE, /* type */ 1846 {0x00, 0x02}, /* USB version */ 1847 UDCLASS_HUB, /* class */ 1848 UDSUBCLASS_HUB, /* subclass */ 1849 UDPROTO_HSHUBSTT, /* protocol */ 1850 64, /* max packet */ 1851 {0},{0},{0x00,0x01}, /* device id */ 1852 1,2,0, /* string indicies */ 1853 1 /* # of configurations */ 1854 }; 1855 1856 Static const usb_device_qualifier_t ehci_odevd = { 1857 USB_DEVICE_DESCRIPTOR_SIZE, 1858 UDESC_DEVICE_QUALIFIER, /* type */ 1859 {0x00, 0x02}, /* USB version */ 1860 UDCLASS_HUB, /* class */ 1861 UDSUBCLASS_HUB, /* subclass */ 1862 UDPROTO_FSHUB, /* protocol */ 1863 64, /* max packet */ 1864 1, /* # of configurations */ 1865 0 1866 }; 1867 1868 Static const usb_config_descriptor_t ehci_confd = { 1869 USB_CONFIG_DESCRIPTOR_SIZE, 1870 UDESC_CONFIG, 1871 {USB_CONFIG_DESCRIPTOR_SIZE + 1872 USB_INTERFACE_DESCRIPTOR_SIZE + 1873 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1874 1, 1875 1, 1876 0, 1877 UC_ATTR_MBO | UC_SELF_POWERED, 1878 0 /* max power */ 1879 }; 1880 1881 Static const usb_interface_descriptor_t ehci_ifcd = { 1882 USB_INTERFACE_DESCRIPTOR_SIZE, 1883 UDESC_INTERFACE, 1884 0, 1885 0, 1886 1, 1887 UICLASS_HUB, 1888 UISUBCLASS_HUB, 1889 UIPROTO_HSHUBSTT, 1890 0 1891 }; 1892 1893 Static const usb_endpoint_descriptor_t ehci_endpd = { 1894 USB_ENDPOINT_DESCRIPTOR_SIZE, 1895 UDESC_ENDPOINT, 1896 UE_DIR_IN | EHCI_INTR_ENDPT, 1897 UE_INTERRUPT, 1898 {8, 0}, /* max packet */ 1899 12 1900 }; 1901 1902 Static const usb_hub_descriptor_t ehci_hubd = { 1903 USB_HUB_DESCRIPTOR_SIZE, 1904 UDESC_HUB, 1905 0, 1906 {0,0}, 1907 0, 1908 0, 1909 {""}, 1910 {""}, 1911 }; 1912 1913 Static int 1914 ehci_str(usb_string_descriptor_t *p, int l, const char *s) 1915 { 1916 int i; 1917 1918 if (l == 0) 1919 return (0); 1920 p->bLength = 2 * strlen(s) + 2; 1921 if (l == 1) 1922 return (1); 1923 p->bDescriptorType = UDESC_STRING; 1924 l -= 2; 1925 for (i = 0; s[i] && l > 1; i++, l -= 2) 1926 USETW2(p->bString[i], 0, s[i]); 1927 return (2*i+2); 1928 } 1929 1930 /* 1931 * Simulate a hardware hub by handling all the necessary requests. 1932 */ 1933 Static usbd_status 1934 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1935 { 1936 usbd_status err; 1937 1938 /* Insert last in queue. */ 1939 err = usb_insert_transfer(xfer); 1940 if (err) 1941 return (err); 1942 1943 /* Pipe isn't running, start first */ 1944 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1945 } 1946 1947 Static usbd_status 1948 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1949 { 1950 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 1951 usb_device_request_t *req; 1952 void *buf = NULL; 1953 int port, i; 1954 int s, len, value, index, l, totlen = 0; 1955 usb_port_status_t ps; 1956 usb_hub_descriptor_t hubd; 1957 usbd_status err; 1958 u_int32_t v; 1959 1960 if (sc->sc_dying) 1961 return (USBD_IOERROR); 1962 1963 #ifdef DIAGNOSTIC 1964 if (!(xfer->rqflags & URQ_REQUEST)) 1965 /* XXX panic */ 1966 return (USBD_INVAL); 1967 #endif 1968 req = &xfer->request; 1969 1970 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1971 req->bmRequestType, req->bRequest)); 1972 1973 len = UGETW(req->wLength); 1974 value = UGETW(req->wValue); 1975 index = UGETW(req->wIndex); 1976 1977 if (len != 0) { 1978 /* mbuf transfer is not supported */ 1979 if (xfer->rqflags & URQ_DEV_MAP_MBUF) 1980 return (USBD_INVAL); 1981 buf = xfer->hcbuffer; 1982 } 1983 1984 #define C(x,y) ((x) | ((y) << 8)) 1985 switch(C(req->bRequest, req->bmRequestType)) { 1986 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1987 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1988 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1989 /* 1990 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1991 * for the integrated root hub. 1992 */ 1993 break; 1994 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1995 if (len > 0) { 1996 *(u_int8_t *)buf = sc->sc_conf; 1997 totlen = 1; 1998 } 1999 break; 2000 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2001 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2002 if (len == 0) 2003 break; 2004 switch(value >> 8) { 2005 case UDESC_DEVICE: 2006 if ((value & 0xff) != 0) { 2007 err = USBD_IOERROR; 2008 goto ret; 2009 } 2010 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2011 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2012 memcpy(buf, &ehci_devd, l); 2013 break; 2014 /* 2015 * We can't really operate at another speed, but the spec says 2016 * we need this descriptor. 2017 */ 2018 case UDESC_DEVICE_QUALIFIER: 2019 if ((value & 0xff) != 0) { 2020 err = USBD_IOERROR; 2021 goto ret; 2022 } 2023 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2024 memcpy(buf, &ehci_odevd, l); 2025 break; 2026 /* 2027 * We can't really operate at another speed, but the spec says 2028 * we need this descriptor. 2029 */ 2030 case UDESC_OTHER_SPEED_CONFIGURATION: 2031 case UDESC_CONFIG: 2032 if ((value & 0xff) != 0) { 2033 err = USBD_IOERROR; 2034 goto ret; 2035 } 2036 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2037 memcpy(buf, &ehci_confd, l); 2038 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2039 value >> 8; 2040 buf = (char *)buf + l; 2041 len -= l; 2042 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2043 totlen += l; 2044 memcpy(buf, &ehci_ifcd, l); 2045 buf = (char *)buf + l; 2046 len -= l; 2047 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2048 totlen += l; 2049 memcpy(buf, &ehci_endpd, l); 2050 break; 2051 case UDESC_STRING: 2052 *(u_int8_t *)buf = 0; 2053 totlen = 1; 2054 switch (value & 0xff) { 2055 case 0: /* Language table */ 2056 if (len > 0) 2057 *(u_int8_t *)buf = 4; 2058 if (len >= 4) { 2059 USETW(((usb_string_descriptor_t *)buf)->bString[0], 0x0409); 2060 totlen = 4; 2061 } 2062 break; 2063 case 1: /* Vendor */ 2064 totlen = ehci_str(buf, len, sc->sc_vendor); 2065 break; 2066 case 2: /* Product */ 2067 totlen = ehci_str(buf, len, "EHCI root hub"); 2068 break; 2069 } 2070 break; 2071 default: 2072 err = USBD_IOERROR; 2073 goto ret; 2074 } 2075 break; 2076 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2077 if (len > 0) { 2078 *(u_int8_t *)buf = 0; 2079 totlen = 1; 2080 } 2081 break; 2082 case C(UR_GET_STATUS, UT_READ_DEVICE): 2083 if (len > 1) { 2084 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2085 totlen = 2; 2086 } 2087 break; 2088 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2089 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2090 if (len > 1) { 2091 USETW(((usb_status_t *)buf)->wStatus, 0); 2092 totlen = 2; 2093 } 2094 break; 2095 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2096 if (value >= USB_MAX_DEVICES) { 2097 err = USBD_IOERROR; 2098 goto ret; 2099 } 2100 sc->sc_addr = value; 2101 break; 2102 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2103 if (value != 0 && value != 1) { 2104 err = USBD_IOERROR; 2105 goto ret; 2106 } 2107 sc->sc_conf = value; 2108 break; 2109 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2110 break; 2111 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2112 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2113 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2114 err = USBD_IOERROR; 2115 goto ret; 2116 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2117 break; 2118 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2119 break; 2120 /* Hub requests */ 2121 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2122 break; 2123 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2124 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2125 "port=%d feature=%d\n", 2126 index, value)); 2127 if (index < 1 || index > sc->sc_noport) { 2128 err = USBD_IOERROR; 2129 goto ret; 2130 } 2131 port = EHCI_PORTSC(index); 2132 v = EOREAD4(sc, port); 2133 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2134 v &= ~EHCI_PS_CLEAR; 2135 switch(value) { 2136 case UHF_PORT_ENABLE: 2137 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2138 break; 2139 case UHF_PORT_SUSPEND: 2140 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 2141 break; 2142 case UHF_PORT_POWER: 2143 if (sc->sc_hasppc) 2144 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2145 break; 2146 case UHF_PORT_TEST: 2147 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2148 "%d\n", index)); 2149 break; 2150 case UHF_PORT_INDICATOR: 2151 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2152 "%d\n", index)); 2153 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2154 break; 2155 case UHF_C_PORT_CONNECTION: 2156 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2157 break; 2158 case UHF_C_PORT_ENABLE: 2159 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2160 break; 2161 case UHF_C_PORT_SUSPEND: 2162 /* how? */ 2163 break; 2164 case UHF_C_PORT_OVER_CURRENT: 2165 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2166 break; 2167 case UHF_C_PORT_RESET: 2168 sc->sc_isreset[index] = 0; 2169 break; 2170 default: 2171 err = USBD_IOERROR; 2172 goto ret; 2173 } 2174 #if 0 2175 switch(value) { 2176 case UHF_C_PORT_CONNECTION: 2177 case UHF_C_PORT_ENABLE: 2178 case UHF_C_PORT_SUSPEND: 2179 case UHF_C_PORT_OVER_CURRENT: 2180 case UHF_C_PORT_RESET: 2181 default: 2182 break; 2183 } 2184 #endif 2185 break; 2186 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2187 if (len == 0) 2188 break; 2189 if ((value & 0xff) != 0) { 2190 err = USBD_IOERROR; 2191 goto ret; 2192 } 2193 hubd = ehci_hubd; 2194 hubd.bNbrPorts = sc->sc_noport; 2195 v = EOREAD4(sc, EHCI_HCSPARAMS); 2196 USETW(hubd.wHubCharacteristics, 2197 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2198 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2199 ? UHD_PORT_IND : 0); 2200 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2201 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2202 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2203 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2204 l = min(len, hubd.bDescLength); 2205 totlen = l; 2206 memcpy(buf, &hubd, l); 2207 break; 2208 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2209 if (len != 4) { 2210 err = USBD_IOERROR; 2211 goto ret; 2212 } 2213 memset(buf, 0, len); /* ? XXX */ 2214 totlen = len; 2215 break; 2216 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2217 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2218 index)); 2219 if (index < 1 || index > sc->sc_noport) { 2220 err = USBD_IOERROR; 2221 goto ret; 2222 } 2223 if (len != 4) { 2224 err = USBD_IOERROR; 2225 goto ret; 2226 } 2227 v = EOREAD4(sc, EHCI_PORTSC(index)); 2228 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2229 v)); 2230 i = UPS_HIGH_SPEED; 2231 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2232 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2233 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2234 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2235 if (v & EHCI_PS_PR) i |= UPS_RESET; 2236 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2237 USETW(ps.wPortStatus, i); 2238 i = 0; 2239 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2240 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2241 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2242 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2243 USETW(ps.wPortChange, i); 2244 l = min(len, sizeof ps); 2245 memcpy(buf, &ps, l); 2246 totlen = l; 2247 break; 2248 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2249 err = USBD_IOERROR; 2250 goto ret; 2251 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2252 break; 2253 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2254 if (index < 1 || index > sc->sc_noport) { 2255 err = USBD_IOERROR; 2256 goto ret; 2257 } 2258 port = EHCI_PORTSC(index); 2259 v = EOREAD4(sc, port); 2260 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2261 v &= ~EHCI_PS_CLEAR; 2262 switch(value) { 2263 case UHF_PORT_ENABLE: 2264 EOWRITE4(sc, port, v | EHCI_PS_PE); 2265 break; 2266 case UHF_PORT_SUSPEND: 2267 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2268 break; 2269 case UHF_PORT_RESET: 2270 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2271 index)); 2272 if (EHCI_PS_IS_LOWSPEED(v)) { 2273 /* Low speed device, give up ownership. */ 2274 ehci_disown(sc, index, 1); 2275 break; 2276 } 2277 /* Start reset sequence. */ 2278 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2279 EOWRITE4(sc, port, v | EHCI_PS_PR); 2280 /* Wait for reset to complete. */ 2281 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2282 if (sc->sc_dying) { 2283 err = USBD_IOERROR; 2284 goto ret; 2285 } 2286 /* Terminate reset sequence. */ 2287 EOWRITE4(sc, port, v); 2288 /* Wait for HC to complete reset. */ 2289 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2290 if (sc->sc_dying) { 2291 err = USBD_IOERROR; 2292 goto ret; 2293 } 2294 v = EOREAD4(sc, port); 2295 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2296 if (v & EHCI_PS_PR) { 2297 printf("%s: port reset timeout\n", 2298 USBDEVNAME(sc->sc_bus.bdev)); 2299 return (USBD_TIMEOUT); 2300 } 2301 if (!(v & EHCI_PS_PE)) { 2302 /* Not a high speed device, give up ownership.*/ 2303 ehci_disown(sc, index, 0); 2304 break; 2305 } 2306 sc->sc_isreset[index] = 1; 2307 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2308 index, v)); 2309 break; 2310 case UHF_PORT_POWER: 2311 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2312 "%d (has PPC = %d)\n", index, 2313 sc->sc_hasppc)); 2314 if (sc->sc_hasppc) 2315 EOWRITE4(sc, port, v | EHCI_PS_PP); 2316 break; 2317 case UHF_PORT_TEST: 2318 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2319 "%d\n", index)); 2320 break; 2321 case UHF_PORT_INDICATOR: 2322 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2323 "%d\n", index)); 2324 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2325 break; 2326 default: 2327 err = USBD_IOERROR; 2328 goto ret; 2329 } 2330 break; 2331 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2332 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2333 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2334 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2335 break; 2336 default: 2337 err = USBD_IOERROR; 2338 goto ret; 2339 } 2340 xfer->actlen = totlen; 2341 err = USBD_NORMAL_COMPLETION; 2342 ret: 2343 xfer->status = err; 2344 s = splusb(); 2345 usb_transfer_complete(xfer); 2346 splx(s); 2347 return (USBD_IN_PROGRESS); 2348 } 2349 2350 void 2351 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2352 { 2353 int port; 2354 u_int32_t v; 2355 2356 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2357 #ifdef DIAGNOSTIC 2358 if (sc->sc_npcomp != 0) { 2359 int i = (index-1) / sc->sc_npcomp; 2360 if (i >= sc->sc_ncomp) 2361 printf("%s: strange port\n", 2362 USBDEVNAME(sc->sc_bus.bdev)); 2363 else 2364 printf("%s: handing over %s speed device on " 2365 "port %d to %s\n", 2366 USBDEVNAME(sc->sc_bus.bdev), 2367 lowspeed ? "low" : "full", 2368 index, USBDEVNAME(sc->sc_comps[i]->bdev)); 2369 } else { 2370 printf("%s: npcomp == 0\n", USBDEVNAME(sc->sc_bus.bdev)); 2371 } 2372 #endif 2373 port = EHCI_PORTSC(index); 2374 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2375 EOWRITE4(sc, port, v | EHCI_PS_PO); 2376 } 2377 2378 /* Abort a root control request. */ 2379 Static void 2380 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2381 { 2382 /* Nothing to do, all transfers are synchronous. */ 2383 } 2384 2385 /* Close the root pipe. */ 2386 Static void 2387 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2388 { 2389 DPRINTF(("ehci_root_ctrl_close\n")); 2390 /* Nothing to do. */ 2391 } 2392 2393 void 2394 ehci_root_intr_done(usbd_xfer_handle xfer) 2395 { 2396 } 2397 2398 Static usbd_status 2399 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2400 { 2401 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2402 usbd_status err; 2403 2404 /* Insert last in queue. */ 2405 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 2406 &EXFER(xfer)->dmabuf); 2407 if (err) 2408 return (err); 2409 2410 /* Pipe isn't running, start first */ 2411 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2412 } 2413 2414 Static usbd_status 2415 ehci_root_intr_start(usbd_xfer_handle xfer) 2416 { 2417 usbd_pipe_handle pipe = xfer->pipe; 2418 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2419 2420 if (sc->sc_dying) 2421 return (USBD_IOERROR); 2422 2423 if (xfer->rqflags & URQ_DEV_MAP_MBUF) 2424 return (USBD_INVAL); /* mbuf transfer is not supported */ 2425 2426 sc->sc_intrxfer = xfer; 2427 2428 return (USBD_IN_PROGRESS); 2429 } 2430 2431 /* Abort a root interrupt request. */ 2432 Static void 2433 ehci_root_intr_abort(usbd_xfer_handle xfer) 2434 { 2435 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2436 int s; 2437 2438 if (xfer->pipe->intrxfer == xfer) { 2439 DPRINTF(("ehci_root_intr_abort: remove\n")); 2440 xfer->pipe->intrxfer = NULL; 2441 } 2442 xfer->status = USBD_CANCELLED; 2443 s = splusb(); 2444 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 2445 splx(s); 2446 } 2447 2448 /* Close the root pipe. */ 2449 Static void 2450 ehci_root_intr_close(usbd_pipe_handle pipe) 2451 { 2452 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2453 2454 DPRINTF(("ehci_root_intr_close\n")); 2455 2456 sc->sc_intrxfer = NULL; 2457 } 2458 2459 void 2460 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2461 { 2462 } 2463 2464 /************************/ 2465 2466 ehci_soft_qh_t * 2467 ehci_alloc_sqh(ehci_softc_t *sc) 2468 { 2469 ehci_soft_qh_t *sqh; 2470 ehci_soft_qtd_t *sqtd; 2471 usbd_status err; 2472 int i, offs; 2473 usb_dma_t dma; 2474 struct ehci_mem_desc *em; 2475 2476 if (sc->sc_freeqhs == NULL) { 2477 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2478 err = usb_allocmem(&sc->sc_dmatag, 2479 EHCI_SQH_SIZE*EHCI_SQH_CHUNK + sizeof(struct ehci_mem_desc), 2480 EHCI_PAGE_SIZE, &dma); 2481 #ifdef EHCI_DEBUG 2482 if (err) 2483 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2484 #endif 2485 if (err) 2486 return (NULL); 2487 em = KERNADDR(&dma, EHCI_SQH_SIZE * EHCI_SQH_CHUNK); 2488 em->em_top = KERNADDR(&dma, 0); 2489 em->em_topdma = DMAADDR(&dma, 0); 2490 em->em_dma = dma; 2491 SIMPLEQ_INSERT_HEAD(&sc->sc_sqh_chunks, em, em_next); 2492 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2493 offs = i * EHCI_SQH_SIZE; 2494 sqh = KERNADDR(&dma, offs); 2495 sqh->eh_mdesc = em; 2496 sqh->next = sc->sc_freeqhs; 2497 sc->sc_freeqhs = sqh; 2498 } 2499 } 2500 /* Allocate the initial inactive sqtd. */ 2501 sqtd = ehci_alloc_sqtd_norsv(sc); 2502 if (sqtd == NULL) 2503 return (NULL); 2504 sqtd->qtd.qtd_status = htole32(0); 2505 sqtd->qtd.qtd_next = EHCI_NULL; 2506 sqtd->qtd.qtd_altnext = EHCI_NULL; 2507 2508 sqh = sc->sc_freeqhs; 2509 sc->sc_freeqhs = sqh->next; 2510 2511 /* The overlay QTD should begin zeroed. */ 2512 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(sqtd)); 2513 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2514 sqh->qh.qh_qtd.qtd_status = 0; 2515 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) { 2516 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2517 sqh->qh.qh_qtd.qtd_buffer_hi[i] = 0; 2518 } 2519 sqh->next = NULL; 2520 sqh->prev = NULL; 2521 sqh->sqtd = sqtd; 2522 sqh->inactivesqtd = sqtd; 2523 return (sqh); 2524 } 2525 2526 void 2527 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2528 { 2529 ehci_free_sqtd_norsv(sc, sqh->inactivesqtd); 2530 sqh->next = sc->sc_freeqhs; 2531 sc->sc_freeqhs = sqh; 2532 } 2533 2534 Static usbd_status 2535 ehci_grow_sqtd(ehci_softc_t *sc) 2536 { 2537 usb_dma_t dma; 2538 struct ehci_mem_desc *em; 2539 ehci_soft_qtd_t *sqtd; 2540 usbd_status err; 2541 int i, s, offs; 2542 2543 DPRINTFN(2, ("ehci_grow_sqtd: allocating chunk\n")); 2544 err = usb_allocmem(&sc->sc_dmatag, 2545 EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK + sizeof(struct ehci_mem_desc), 2546 EHCI_PAGE_SIZE, &dma); 2547 #ifdef EHCI_DEBUG 2548 if (err) 2549 printf("ehci_grow_sqtd: usb_allocmem()=%d\n", err); 2550 #endif 2551 if (err) 2552 return (err); 2553 em = KERNADDR(&dma, EHCI_SQTD_SIZE * EHCI_SQTD_CHUNK); 2554 em->em_top = KERNADDR(&dma, 0); 2555 em->em_topdma = DMAADDR(&dma, 0); 2556 em->em_dma = dma; 2557 s = splusb(); 2558 SIMPLEQ_INSERT_HEAD(&sc->sc_sqtd_chunks, em, em_next); 2559 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2560 offs = i * EHCI_SQTD_SIZE; 2561 sqtd = KERNADDR(&dma, offs); 2562 sqtd->et_mdesc = em; 2563 sqtd->nextqtd = sc->sc_freeqtds; 2564 sc->sc_freeqtds = sqtd; 2565 sc->sc_nfreeqtds++; 2566 } 2567 splx(s); 2568 2569 return (USBD_NORMAL_COMPLETION); 2570 } 2571 2572 ehci_soft_qtd_t * 2573 ehci_alloc_sqtd(ehci_softc_t *sc) 2574 { 2575 ehci_soft_qtd_t *sqtd; 2576 int i; 2577 int s; 2578 2579 s = splusb(); 2580 2581 #ifdef DIAGNOSTIC 2582 if (sc->sc_freeqtds == NULL) 2583 panic("ehci_alloc_sqtd: %p %d", 2584 sc->sc_freeqtds, sc->sc_nfreeqtds); 2585 #endif 2586 sqtd = sc->sc_freeqtds; 2587 sc->sc_freeqtds = sqtd->nextqtd; 2588 splx(s); 2589 sqtd->qtd.qtd_next = EHCI_NULL; 2590 sqtd->qtd.qtd_altnext = EHCI_NULL; 2591 sqtd->qtd.qtd_status = 0; 2592 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) { 2593 sqtd->qtd.qtd_buffer[i] = 0; 2594 sqtd->qtd.qtd_buffer_hi[i] = 0; 2595 } 2596 sqtd->nextqtd = NULL; 2597 sqtd->xfer = NULL; 2598 2599 return (sqtd); 2600 } 2601 2602 Static ehci_soft_qtd_t * 2603 ehci_alloc_sqtd_norsv(ehci_softc_t *sc) 2604 { 2605 int s; 2606 2607 s = splusb(); 2608 if (sc->sc_nfreeqtds < 1) 2609 if (ehci_grow_sqtd(sc)) 2610 return (NULL); 2611 sc->sc_nfreeqtds--; 2612 splx(s); 2613 return (ehci_alloc_sqtd(sc)); 2614 } 2615 2616 void 2617 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2618 { 2619 int s; 2620 2621 s = splusb(); 2622 sqtd->nextqtd = sc->sc_freeqtds; 2623 sc->sc_freeqtds = sqtd; 2624 splx(s); 2625 } 2626 2627 Static void 2628 ehci_free_sqtd_norsv(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2629 { 2630 int s; 2631 2632 ehci_free_sqtd(sc, sqtd); 2633 s = splusb(); 2634 sc->sc_nfreeqtds++; 2635 splx(s); 2636 } 2637 2638 usbd_status 2639 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2640 int alen, int rd, usbd_xfer_handle xfer, ehci_soft_qtd_t *start, 2641 ehci_soft_qtd_t *newinactive, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2642 { 2643 ehci_soft_qtd_t *next, *cur; 2644 ehci_physaddr_t dataphys, nextphys; 2645 u_int32_t qtdstatus; 2646 int adj, len, curlen, mps, offset, pagelen, seg, segoff; 2647 int i, iscontrol, forceshort; 2648 struct usb_buffer_dma *ub = &EXFER(xfer)->dmabuf; 2649 bus_dma_segment_t *segs = USB_BUFFER_SEGS(ub); 2650 int nsegs = USB_BUFFER_NSEGS(ub); 2651 2652 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2653 2654 offset = 0; 2655 len = alen; 2656 iscontrol = (epipe->pipe.endpoint->edesc->bmAttributes & UE_XFERTYPE) == 2657 UE_CONTROL; 2658 qtdstatus = EHCI_QTD_ACTIVE | 2659 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2660 EHCI_QTD_SET_CERR(3) 2661 /* IOC set below */ 2662 /* BYTES set below */ 2663 ; 2664 mps = UE_MAXPKTSZ(epipe->pipe.endpoint->edesc); 2665 forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) && 2666 len % mps == 0; 2667 /* 2668 * The control transfer data stage always starts with a toggle of 1. 2669 * For other transfers we let the hardware track the toggle state. 2670 */ 2671 if (iscontrol) 2672 qtdstatus |= EHCI_QTD_SET_TOGGLE(1); 2673 2674 if (start != NULL) { 2675 /* 2676 * If we are given a starting qTD, assume it is linked into 2677 * an active QH so be careful not to mark it active. 2678 */ 2679 cur = start; 2680 *sp = cur; 2681 qtdstatus &= ~EHCI_QTD_ACTIVE; 2682 } else { 2683 cur = ehci_alloc_sqtd(sc); 2684 *sp = cur; 2685 if (cur == NULL) 2686 goto nomem; 2687 } 2688 seg = 0; 2689 segoff = 0; 2690 for (;;) { 2691 curlen = 0; 2692 2693 /* The EHCI hardware can handle at most 5 pages. */ 2694 for (i = 0; i < EHCI_QTD_NBUFFERS && curlen < len; i++) { 2695 USB_KASSERT2(seg < nsegs, 2696 ("ehci_alloc_sqtd_chain: overrun")); 2697 dataphys = segs[seg].ds_addr + segoff; 2698 pagelen = segs[seg].ds_len - segoff; 2699 if (pagelen > len - curlen) 2700 pagelen = len - curlen; 2701 if (pagelen > EHCI_PAGE_SIZE - 2702 EHCI_PAGE_OFFSET(dataphys)) 2703 pagelen = EHCI_PAGE_SIZE - 2704 EHCI_PAGE_OFFSET(dataphys); 2705 segoff += pagelen; 2706 if (segoff >= segs[seg].ds_len) { 2707 USB_KASSERT2(segoff == segs[seg].ds_len, 2708 ("ehci_alloc_sqtd_chain: overlap")); 2709 seg++; 2710 segoff = 0; 2711 } 2712 2713 cur->qtd.qtd_buffer[i] = htole32(dataphys); 2714 cur->qtd.qtd_buffer_hi[i] = 0; 2715 curlen += pagelen; 2716 2717 /* 2718 * Must stop if there is any gap before or after 2719 * the page boundary. 2720 */ 2721 if (EHCI_PAGE_OFFSET(dataphys + pagelen) != 0) 2722 break; 2723 if (seg < nsegs && EHCI_PAGE_OFFSET(segoff + 2724 segs[seg].ds_addr) != 0) 2725 break; 2726 } 2727 /* Adjust down to a multiple of mps if not at the end. */ 2728 if (curlen < len && curlen % mps != 0) { 2729 adj = curlen % mps; 2730 curlen -= adj; 2731 USB_KASSERT2(curlen > 0, 2732 ("ehci_alloc_sqtd_chain: need to copy")); 2733 segoff -= adj; 2734 if (segoff < 0) { 2735 seg--; 2736 segoff += segs[seg].ds_len; 2737 } 2738 USB_KASSERT2(seg >= 0 && segoff >= 0, 2739 ("ehci_alloc_sqtd_chain: adjust to mps")); 2740 } 2741 2742 len -= curlen; 2743 2744 if (len != 0 || forceshort) { 2745 next = ehci_alloc_sqtd(sc); 2746 if (next == NULL) 2747 goto nomem; 2748 nextphys = htole32(EHCI_SQTD_DMAADDR(next)); 2749 } else { 2750 next = NULL; 2751 nextphys = EHCI_NULL; 2752 } 2753 2754 cur->nextqtd = next; 2755 cur->qtd.qtd_next = nextphys; 2756 /* Make sure to stop after a short transfer. */ 2757 cur->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 2758 cur->qtd.qtd_status = 2759 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2760 cur->xfer = xfer; 2761 cur->len = curlen; 2762 DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%d\n", curlen)); 2763 if (iscontrol) { 2764 /* 2765 * adjust the toggle based on the number of packets 2766 * in this qtd 2767 */ 2768 if ((((curlen + mps - 1) / mps) & 1) || curlen == 0) 2769 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2770 } 2771 qtdstatus |= EHCI_QTD_ACTIVE; 2772 if (len == 0) { 2773 if (!forceshort) 2774 break; 2775 forceshort = 0; 2776 } 2777 EHCI_SQTD_SYNC(sc, cur, 2778 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2779 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2780 offset += curlen; 2781 cur = next; 2782 } 2783 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2784 EHCI_SQTD_SYNC(sc, cur, 2785 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2786 *ep = cur; 2787 2788 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2789 *sp, *ep)); 2790 2791 return (USBD_NORMAL_COMPLETION); 2792 2793 nomem: 2794 /* XXX free chain */ 2795 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2796 return (USBD_NOMEM); 2797 } 2798 2799 /* Free the chain starting at sqtd and end at the qTD before sqtdend */ 2800 Static void 2801 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qh_t *sqh, 2802 ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *sqtdend) 2803 { 2804 ehci_soft_qtd_t *p, **prevp; 2805 int i; 2806 2807 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2808 sqtd, sqtdend)); 2809 2810 /* First unlink the chain from the QH's software qTD list. */ 2811 prevp = &sqh->sqtd; 2812 for (p = sqh->sqtd; p != NULL; p = p->nextqtd) { 2813 if (p == sqtd) { 2814 *prevp = sqtdend; 2815 break; 2816 } 2817 prevp = &p->nextqtd; 2818 } 2819 USB_KASSERT2(p != NULL, ("ehci_free_sqtd_chain: chain not found")); 2820 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2821 p = sqtd->nextqtd; 2822 ehci_free_sqtd(sc, sqtd); 2823 } 2824 } 2825 2826 /****************/ 2827 2828 /* 2829 * Close a reqular pipe. 2830 * Assumes that there are no pending transactions. 2831 */ 2832 void 2833 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2834 { 2835 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2836 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2837 ehci_soft_qh_t *sqh = epipe->sqh; 2838 int s; 2839 2840 s = splusb(); 2841 ehci_rem_qh(sc, sqh, head); 2842 splx(s); 2843 pipe->endpoint->savedtoggle = 2844 EHCI_QTD_GET_TOGGLE(le32toh(sqh->qh.qh_qtd.qtd_status)); 2845 ehci_free_sqh(sc, epipe->sqh); 2846 } 2847 2848 /* 2849 * Abort a device request. 2850 * If this routine is called at splusb() it guarantees that the request 2851 * will be removed from the hardware scheduling and that the callback 2852 * for it will be called with USBD_CANCELLED status. 2853 * It's impossible to guarantee that the requested transfer will not 2854 * have happened since the hardware runs concurrently. 2855 * If the transaction has already happened we rely on the ordinary 2856 * interrupt processing to process it. 2857 */ 2858 void 2859 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2860 { 2861 #define exfer EXFER(xfer) 2862 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2863 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2864 ehci_soft_qh_t *sqh = epipe->sqh; 2865 ehci_soft_qtd_t *sqtd, *snext; 2866 ehci_physaddr_t cur, us, next; 2867 int s; 2868 int hit, i; 2869 /* int count = 0; */ 2870 ehci_soft_qh_t *psqh; 2871 2872 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2873 2874 if (sc->sc_dying) { 2875 /* If we're dying, just do the software part. */ 2876 s = splusb(); 2877 xfer->status = status; /* make software ignore it */ 2878 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2879 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 2880 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, 2881 &EXFER(xfer)->dmabuf); 2882 splx(s); 2883 return; 2884 } 2885 2886 if (xfer->device->bus->intr_context || !curproc) 2887 panic("ehci_abort_xfer: not in process context"); 2888 2889 /* 2890 * If an abort is already in progress then just wait for it to 2891 * complete and return. 2892 */ 2893 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 2894 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2895 /* No need to wait if we're aborting from a timeout. */ 2896 if (status == USBD_TIMEOUT) 2897 return; 2898 /* Override the status which might be USBD_TIMEOUT. */ 2899 xfer->status = status; 2900 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2901 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT; 2902 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 2903 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciaw", 0); 2904 return; 2905 } 2906 2907 /* 2908 * Step 1: Make interrupt routine and timeouts ignore xfer. 2909 */ 2910 s = splusb(); 2911 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 2912 xfer->status = status; /* make software ignore it */ 2913 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2914 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 2915 splx(s); 2916 2917 /* 2918 * Step 2: Wait until we know hardware has finished any possible 2919 * use of the xfer. We do this by removing the entire 2920 * queue from the async schedule and waiting for the doorbell. 2921 * Nothing else should be touching the queue now. 2922 */ 2923 psqh = sqh->prev; 2924 ehci_rem_qh(sc, sqh, psqh); 2925 2926 /* 2927 * Step 3: make sure the soft interrupt routine 2928 * has run. This should remove any completed items off the queue. 2929 * The hardware has no reference to completed items (TDs). 2930 * It's safe to remove them at any time. 2931 */ 2932 s = splusb(); 2933 #ifdef USB_USE_SOFTINTR 2934 sc->sc_softwake = 1; 2935 #endif /* USB_USE_SOFTINTR */ 2936 usb_schedsoftintr(&sc->sc_bus); 2937 #ifdef USB_USE_SOFTINTR 2938 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2939 #endif /* USB_USE_SOFTINTR */ 2940 2941 /* 2942 * Step 4: Remove any vestiges of the xfer from the hardware. 2943 * The complication here is that the hardware may have executed 2944 * into or even beyond the xfer we're trying to abort. 2945 * So as we're scanning the TDs of this xfer we check if 2946 * the hardware points to any of them. 2947 * 2948 * first we need to see if there are any transfers 2949 * on this queue before the xfer we are aborting.. we need 2950 * to update any pointers that point to us to point past 2951 * the aborting xfer. (If there is something past us). 2952 * Hardware and software. 2953 */ 2954 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2955 hit = 0; 2956 2957 /* If they initially point here. */ 2958 us = EHCI_SQTD_DMAADDR(exfer->sqtdstart); 2959 2960 /* We will change them to point here */ 2961 snext = exfer->sqtdend->nextqtd; 2962 next = htole32(EHCI_SQTD_DMAADDR(snext)); 2963 2964 /* 2965 * Now loop through any qTDs before us and keep track of the pointer 2966 * that points to us for the end. 2967 */ 2968 sqtd = sqh->sqtd; 2969 while (sqtd && sqtd != exfer->sqtdstart) { 2970 hit |= (cur == EHCI_SQTD_DMAADDR(sqtd)); 2971 if (EHCI_LINK_ADDR(le32toh(sqtd->qtd.qtd_next)) == us) { 2972 sqtd->qtd.qtd_next = next; 2973 EHCI_SQTD_SYNC(sc, sqtd, 2974 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2975 } 2976 if (EHCI_LINK_ADDR(le32toh(sqtd->qtd.qtd_altnext)) == us) { 2977 sqtd->qtd.qtd_altnext = next; 2978 EHCI_SQTD_SYNC(sc, sqtd, 2979 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2980 } 2981 sqtd = sqtd->nextqtd; 2982 } 2983 2984 /* 2985 * If we already saw the active one then we are pretty much done. 2986 * We've done all the relinking we need to do. 2987 */ 2988 if (!hit) { 2989 2990 /* 2991 * Now reinitialise the QH to point to the next qTD 2992 * (if there is one). We only need to do this if 2993 * it was previously pointing to us. 2994 */ 2995 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2996 if (cur == EHCI_SQTD_DMAADDR(sqtd)) { 2997 hit++; 2998 } 2999 if (sqtd == exfer->sqtdend) 3000 break; 3001 } 3002 sqtd = sqtd->nextqtd; 3003 /* 3004 * Only need to alter the QH if it was pointing at a qTD 3005 * that we are removing. 3006 */ 3007 if (hit) { 3008 sqh->qh.qh_qtd.qtd_next = 3009 htole32(EHCI_SQTD_DMAADDR(snext)); 3010 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 3011 sqh->qh.qh_qtd.qtd_status &= 3012 htole32(EHCI_QTD_TOGGLE_MASK); 3013 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) { 3014 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 3015 sqh->qh.qh_qtd.qtd_buffer_hi[i] = 0; 3016 } 3017 } 3018 } 3019 ehci_add_qh(sc, sqh, psqh); 3020 /* 3021 * Step 5: Execute callback. 3022 */ 3023 #ifdef DIAGNOSTIC 3024 exfer->isdone = 1; 3025 #endif 3026 /* Do the wakeup first to avoid touching the xfer after the callback. */ 3027 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTING; 3028 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) { 3029 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT; 3030 wakeup(&exfer->ehci_xfer_flags); 3031 } 3032 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 3033 3034 /* printf("%s: %d TDs aborted\n", __func__, count); */ 3035 splx(s); 3036 #undef exfer 3037 } 3038 3039 void 3040 ehci_timeout(void *addr) 3041 { 3042 struct ehci_xfer *exfer = addr; 3043 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3044 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 3045 3046 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3047 #ifdef USB_DEBUG 3048 if (ehcidebug > 1) 3049 usbd_dump_pipe(exfer->xfer.pipe); 3050 #endif 3051 3052 if (sc->sc_dying) { 3053 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3054 return; 3055 } 3056 3057 /* Execute the abort in a process context. */ 3058 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3059 USB_TASKQ_HC); 3060 } 3061 3062 void 3063 ehci_timeout_task(void *addr) 3064 { 3065 usbd_xfer_handle xfer = addr; 3066 int s; 3067 3068 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3069 3070 s = splusb(); 3071 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3072 splx(s); 3073 } 3074 3075 /* 3076 * Some EHCI chips from VIA / ATI seem to trigger interrupts before writing 3077 * back the qTD status, or miss signalling occasionally under heavy load. 3078 * If the host machine is too fast, we can miss transaction completion - when 3079 * we scan the active list the transaction still seems to be active. This 3080 * generally exhibits itself as a umass stall that never recovers. 3081 * 3082 * We work around this behaviour by setting up this callback after any softintr 3083 * that completes with transactions still pending, giving us another chance to 3084 * check for completion after the writeback has taken place. 3085 */ 3086 void 3087 ehci_intrlist_timeout(void *arg) 3088 { 3089 ehci_softc_t *sc = arg; 3090 int s = splusb(); 3091 3092 DPRINTFN(3, ("ehci_intrlist_timeout\n")); 3093 usb_schedsoftintr(&sc->sc_bus); 3094 3095 splx(s); 3096 } 3097 3098 /************************/ 3099 3100 Static usbd_status 3101 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3102 { 3103 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3104 usbd_status err; 3105 3106 /* Insert last in queue. */ 3107 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3108 &EXFER(xfer)->dmabuf); 3109 if (err) 3110 return (err); 3111 3112 /* Pipe isn't running, start first */ 3113 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3114 } 3115 3116 Static usbd_status 3117 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3118 { 3119 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3120 usbd_status err; 3121 3122 if (sc->sc_dying) 3123 return (USBD_IOERROR); 3124 3125 #ifdef DIAGNOSTIC 3126 if (!(xfer->rqflags & URQ_REQUEST)) { 3127 /* XXX panic */ 3128 printf("ehci_device_ctrl_transfer: not a request\n"); 3129 return (USBD_INVAL); 3130 } 3131 #endif 3132 3133 err = ehci_device_request(xfer); 3134 if (err) 3135 return (err); 3136 3137 if (sc->sc_bus.use_polling) 3138 ehci_waitintr(sc, xfer); 3139 return (USBD_IN_PROGRESS); 3140 } 3141 3142 void 3143 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3144 { 3145 struct ehci_xfer *ex = EXFER(xfer); 3146 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3147 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3148 3149 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3150 3151 #ifdef DIAGNOSTIC 3152 if (!(xfer->rqflags & URQ_REQUEST)) { 3153 panic("ehci_ctrl_done: not a request"); 3154 } 3155 #endif 3156 3157 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3158 ehci_del_intr_list(ex); /* remove from active list */ 3159 ehci_free_sqtd_chain(sc, epipe->sqh, ex->sqtdstart, 3160 ex->sqtdend->nextqtd); 3161 } 3162 3163 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3164 } 3165 3166 /* Abort a device control request. */ 3167 Static void 3168 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3169 { 3170 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3171 ehci_abort_xfer(xfer, USBD_CANCELLED); 3172 } 3173 3174 /* Close a device control pipe. */ 3175 Static void 3176 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3177 { 3178 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3179 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3180 3181 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3182 ehci_close_pipe(pipe, sc->sc_async_head); 3183 usb_freemem(&sc->sc_dmatag, &epipe->u.ctl.reqdma); 3184 } 3185 3186 usbd_status 3187 ehci_device_request(usbd_xfer_handle xfer) 3188 { 3189 #define exfer EXFER(xfer) 3190 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3191 usb_device_request_t *req = &xfer->request; 3192 usbd_device_handle dev = epipe->pipe.device; 3193 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3194 ehci_soft_qtd_t *newinactive, *setup, *stat, *next; 3195 ehci_soft_qh_t *sqh; 3196 int isread; 3197 int len; 3198 usbd_status err; 3199 int s; 3200 3201 isread = req->bmRequestType & UT_READ; 3202 len = UGETW(req->wLength); 3203 3204 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3205 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3206 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3207 UGETW(req->wIndex), len, dev->address, 3208 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3209 3210 newinactive = ehci_alloc_sqtd(sc); 3211 if (newinactive == NULL) { 3212 err = USBD_NOMEM; 3213 goto bad1; 3214 } 3215 newinactive->qtd.qtd_status = htole32(0); 3216 newinactive->qtd.qtd_next = EHCI_NULL; 3217 newinactive->qtd.qtd_altnext = EHCI_NULL; 3218 EHCI_SQTD_SYNC(sc, newinactive, 3219 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3220 stat = ehci_alloc_sqtd(sc); 3221 if (stat == NULL) { 3222 err = USBD_NOMEM; 3223 goto bad2; 3224 } 3225 3226 sqh = epipe->sqh; 3227 setup = sqh->inactivesqtd; 3228 sqh->inactivesqtd = newinactive; 3229 epipe->u.ctl.length = len; 3230 3231 /* Set up data transaction */ 3232 if (len != 0) { 3233 ehci_soft_qtd_t *end; 3234 3235 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3236 NULL, newinactive, &next, &end); 3237 if (err) 3238 goto bad3; 3239 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3240 end->nextqtd = stat; 3241 end->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(stat)); 3242 end->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3243 } else { 3244 next = stat; 3245 } 3246 3247 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3248 3249 /* Clear toggle, and do not activate until complete */ 3250 setup->qtd.qtd_status = htole32( 3251 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3252 EHCI_QTD_SET_CERR(3) | 3253 EHCI_QTD_SET_TOGGLE(0) | 3254 EHCI_QTD_SET_BYTES(sizeof *req) 3255 ); 3256 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3257 setup->qtd.qtd_buffer_hi[0] = 0; 3258 setup->nextqtd = next; 3259 setup->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(next)); 3260 setup->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3261 setup->xfer = xfer; 3262 setup->len = sizeof *req; 3263 EHCI_SQTD_SYNC(sc, setup, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3264 3265 stat->qtd.qtd_status = htole32( 3266 EHCI_QTD_ACTIVE | 3267 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3268 EHCI_QTD_SET_CERR(3) | 3269 EHCI_QTD_SET_TOGGLE(1) | 3270 EHCI_QTD_IOC 3271 ); 3272 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3273 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3274 stat->nextqtd = newinactive; 3275 stat->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3276 stat->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3277 stat->xfer = xfer; 3278 stat->len = 0; 3279 EHCI_SQTD_SYNC(sc, stat, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3280 3281 #ifdef EHCI_DEBUG 3282 if (ehcidebug > 5) { 3283 DPRINTF(("ehci_device_request:\n")); 3284 ehci_dump_sqh(sqh); 3285 ehci_dump_sqtds(setup); 3286 } 3287 #endif 3288 3289 exfer->sqtdstart = setup; 3290 exfer->sqtdend = stat; 3291 #ifdef DIAGNOSTIC 3292 if (!exfer->isdone) { 3293 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3294 } 3295 exfer->isdone = 0; 3296 #endif 3297 3298 /* Activate the new qTD in the QH list. */ 3299 s = splusb(); 3300 ehci_activate_qh(sc, sqh, setup); 3301 if (xfer->timeout && !sc->sc_bus.use_polling) { 3302 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 3303 ehci_timeout, xfer); 3304 } 3305 ehci_add_intr_list(sc, exfer); 3306 xfer->status = USBD_IN_PROGRESS; 3307 splx(s); 3308 3309 #ifdef EHCI_DEBUG 3310 if (ehcidebug > 10) { 3311 DPRINTF(("ehci_device_request: status=%x\n", 3312 EOREAD4(sc, EHCI_USBSTS))); 3313 delay(10000); 3314 ehci_dump_regs(sc); 3315 ehci_dump_sqh(sc->sc_async_head); 3316 ehci_dump_sqh(sqh); 3317 ehci_dump_sqtds(setup); 3318 } 3319 #endif 3320 3321 return (USBD_NORMAL_COMPLETION); 3322 3323 bad3: 3324 sqh->inactivesqtd = setup; 3325 ehci_free_sqtd(sc, stat); 3326 bad2: 3327 ehci_free_sqtd(sc, newinactive); 3328 bad1: 3329 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3330 xfer->status = err; 3331 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, 3332 &EXFER(xfer)->dmabuf); 3333 return (err); 3334 #undef exfer 3335 } 3336 3337 /************************/ 3338 3339 Static usbd_status 3340 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3341 { 3342 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3343 usbd_status err; 3344 3345 /* Insert last in queue. */ 3346 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3347 &EXFER(xfer)->dmabuf); 3348 if (err) 3349 return (err); 3350 3351 /* Pipe isn't running, start first */ 3352 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3353 } 3354 3355 usbd_status 3356 ehci_device_bulk_start(usbd_xfer_handle xfer) 3357 { 3358 #define exfer EXFER(xfer) 3359 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3360 usbd_device_handle dev = epipe->pipe.device; 3361 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3362 ehci_soft_qtd_t *data, *dataend, *newinactive; 3363 ehci_soft_qh_t *sqh; 3364 usbd_status err; 3365 int len, isread, endpt; 3366 int s; 3367 3368 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3369 xfer, xfer->length, xfer->flags)); 3370 3371 if (sc->sc_dying) 3372 return (USBD_IOERROR); 3373 3374 #ifdef DIAGNOSTIC 3375 if (xfer->rqflags & URQ_REQUEST) 3376 panic("ehci_device_bulk_start: a request"); 3377 #endif 3378 3379 len = xfer->length; 3380 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3381 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3382 sqh = epipe->sqh; 3383 3384 epipe->u.bulk.length = len; 3385 3386 newinactive = ehci_alloc_sqtd(sc); 3387 if (newinactive == NULL) { 3388 DPRINTFN(-1,("ehci_device_bulk_start: no sqtd memory\n")); 3389 err = USBD_NOMEM; 3390 xfer->status = err; 3391 usb_transfer_complete(xfer); 3392 return (err); 3393 } 3394 newinactive->qtd.qtd_status = htole32(0); 3395 newinactive->qtd.qtd_next = EHCI_NULL; 3396 newinactive->qtd.qtd_altnext = EHCI_NULL; 3397 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3398 sqh->inactivesqtd, newinactive, &data, &dataend); 3399 if (err) { 3400 DPRINTFN(-1,("ehci_device_bulk_start: no memory\n")); 3401 ehci_free_sqtd(sc, newinactive); 3402 xfer->status = err; 3403 usb_transfer_complete(xfer); 3404 return (err); 3405 } 3406 dataend->nextqtd = newinactive; 3407 dataend->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3408 dataend->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3409 sqh->inactivesqtd = newinactive; 3410 EHCI_SQTD_SYNC(sc, newinactive, 3411 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3412 EHCI_SQTD_SYNC(sc, dataend, 3413 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3414 3415 #ifdef EHCI_DEBUG 3416 if (ehcidebug > 5) { 3417 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3418 ehci_dump_sqh(sqh); 3419 ehci_dump_sqtds(data); 3420 } 3421 #endif 3422 3423 /* Set up interrupt info. */ 3424 exfer->sqtdstart = data; 3425 exfer->sqtdend = dataend; 3426 #ifdef DIAGNOSTIC 3427 if (!exfer->isdone) { 3428 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3429 } 3430 exfer->isdone = 0; 3431 #endif 3432 3433 s = splusb(); 3434 ehci_activate_qh(sc, sqh, data); 3435 if (xfer->timeout && !sc->sc_bus.use_polling) { 3436 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 3437 ehci_timeout, xfer); 3438 } 3439 ehci_add_intr_list(sc, exfer); 3440 xfer->status = USBD_IN_PROGRESS; 3441 splx(s); 3442 3443 #ifdef EHCI_DEBUG 3444 if (ehcidebug > 10) { 3445 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3446 delay(10000); 3447 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3448 ehci_dump_regs(sc); 3449 #if 0 3450 printf("async_head:\n"); 3451 ehci_dump_sqh(sc->sc_async_head); 3452 #endif 3453 printf("sqh:\n"); 3454 ehci_dump_sqh(sqh); 3455 ehci_dump_sqtds(data); 3456 } 3457 #endif 3458 3459 if (sc->sc_bus.use_polling) 3460 ehci_waitintr(sc, xfer); 3461 3462 return (USBD_IN_PROGRESS); 3463 #undef exfer 3464 } 3465 3466 Static void 3467 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3468 { 3469 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3470 ehci_abort_xfer(xfer, USBD_CANCELLED); 3471 } 3472 3473 /* 3474 * Close a device bulk pipe. 3475 */ 3476 Static void 3477 ehci_device_bulk_close(usbd_pipe_handle pipe) 3478 { 3479 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3480 3481 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3482 ehci_close_pipe(pipe, sc->sc_async_head); 3483 } 3484 3485 void 3486 ehci_device_bulk_done(usbd_xfer_handle xfer) 3487 { 3488 struct ehci_xfer *ex = EXFER(xfer); 3489 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3490 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3491 3492 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3493 xfer, xfer->actlen)); 3494 3495 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3496 ehci_del_intr_list(ex); /* remove from active list */ 3497 ehci_free_sqtd_chain(sc, epipe->sqh, ex->sqtdstart, 3498 ex->sqtdend->nextqtd); 3499 } 3500 3501 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3502 } 3503 3504 /************************/ 3505 3506 Static usbd_status 3507 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3508 { 3509 struct ehci_soft_islot *isp; 3510 int islot, lev; 3511 3512 /* Find a poll rate that is large enough. */ 3513 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3514 if (EHCI_ILEV_IVAL(lev) <= ival) 3515 break; 3516 3517 /* Pick an interrupt slot at the right level. */ 3518 /* XXX could do better than picking at random. */ 3519 islot = EHCI_IQHIDX(lev, arc4random()); 3520 3521 sqh->islot = islot; 3522 isp = &sc->sc_islots[islot]; 3523 ehci_add_qh(sc, sqh, isp->sqh); 3524 3525 return (USBD_NORMAL_COMPLETION); 3526 } 3527 3528 Static usbd_status 3529 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3530 { 3531 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3532 usbd_status err; 3533 3534 /* Insert last in queue. */ 3535 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3536 &EXFER(xfer)->dmabuf); 3537 if (err) 3538 return (err); 3539 3540 /* 3541 * Pipe isn't running (otherwise err would be USBD_INPROG), 3542 * so start it first. 3543 */ 3544 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3545 } 3546 3547 Static usbd_status 3548 ehci_device_intr_start(usbd_xfer_handle xfer) 3549 { 3550 #define exfer EXFER(xfer) 3551 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3552 usbd_device_handle dev = xfer->pipe->device; 3553 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3554 ehci_soft_qtd_t *data, *dataend, *newinactive; 3555 ehci_soft_qh_t *sqh; 3556 usbd_status err; 3557 int len, isread, endpt; 3558 int s; 3559 3560 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3561 xfer, xfer->length, xfer->flags)); 3562 3563 if (sc->sc_dying) 3564 return (USBD_IOERROR); 3565 3566 #ifdef DIAGNOSTIC 3567 if (xfer->rqflags & URQ_REQUEST) 3568 panic("ehci_device_intr_start: a request"); 3569 #endif 3570 3571 len = xfer->length; 3572 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3573 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3574 sqh = epipe->sqh; 3575 3576 epipe->u.intr.length = len; 3577 3578 newinactive = ehci_alloc_sqtd(sc); 3579 if (newinactive == NULL) { 3580 DPRINTFN(-1,("ehci_device_intr_start: no sqtd memory\n")); 3581 err = USBD_NOMEM; 3582 xfer->status = err; 3583 usb_transfer_complete(xfer); 3584 return (err); 3585 } 3586 newinactive->qtd.qtd_status = htole32(0); 3587 newinactive->qtd.qtd_next = EHCI_NULL; 3588 newinactive->qtd.qtd_altnext = EHCI_NULL; 3589 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3590 sqh->inactivesqtd, newinactive, &data, &dataend); 3591 if (err) { 3592 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3593 xfer->status = err; 3594 usb_transfer_complete(xfer); 3595 return (err); 3596 } 3597 dataend->nextqtd = newinactive; 3598 dataend->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3599 dataend->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3600 sqh->inactivesqtd = newinactive; 3601 EHCI_SQTD_SYNC(sc, newinactive, 3602 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3603 EHCI_SQTD_SYNC(sc, dataend, 3604 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3605 3606 #ifdef EHCI_DEBUG 3607 if (ehcidebug > 5) { 3608 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3609 ehci_dump_sqh(sqh); 3610 ehci_dump_sqtds(data); 3611 } 3612 #endif 3613 3614 /* Set up interrupt info. */ 3615 exfer->sqtdstart = data; 3616 exfer->sqtdend = dataend; 3617 #ifdef DIAGNOSTIC 3618 if (!exfer->isdone) { 3619 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3620 } 3621 exfer->isdone = 0; 3622 #endif 3623 3624 s = splusb(); 3625 ehci_activate_qh(sc, sqh, data); 3626 if (xfer->timeout && !sc->sc_bus.use_polling) { 3627 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 3628 ehci_timeout, xfer); 3629 } 3630 ehci_add_intr_list(sc, exfer); 3631 xfer->status = USBD_IN_PROGRESS; 3632 splx(s); 3633 3634 #ifdef EHCI_DEBUG 3635 if (ehcidebug > 10) { 3636 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3637 delay(10000); 3638 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3639 ehci_dump_regs(sc); 3640 printf("sqh:\n"); 3641 ehci_dump_sqh(sqh); 3642 ehci_dump_sqtds(data); 3643 } 3644 #endif 3645 3646 if (sc->sc_bus.use_polling) 3647 ehci_waitintr(sc, xfer); 3648 3649 return (USBD_IN_PROGRESS); 3650 #undef exfer 3651 } 3652 3653 Static void 3654 ehci_device_intr_abort(usbd_xfer_handle xfer) 3655 { 3656 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3657 if (xfer->pipe->intrxfer == xfer) { 3658 DPRINTFN(1, ("ehci_device_intr_abort: remove\n")); 3659 xfer->pipe->intrxfer = NULL; 3660 } 3661 ehci_abort_xfer(xfer, USBD_CANCELLED); 3662 } 3663 3664 Static void 3665 ehci_device_intr_close(usbd_pipe_handle pipe) 3666 { 3667 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3668 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3669 struct ehci_soft_islot *isp; 3670 3671 isp = &sc->sc_islots[epipe->sqh->islot]; 3672 ehci_close_pipe(pipe, isp->sqh); 3673 } 3674 3675 Static void 3676 ehci_device_intr_done(usbd_xfer_handle xfer) 3677 { 3678 #define exfer EXFER(xfer) 3679 struct ehci_xfer *ex = EXFER(xfer); 3680 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3681 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3682 ehci_soft_qtd_t *data, *dataend, *newinactive; 3683 ehci_soft_qh_t *sqh; 3684 usbd_status err; 3685 int len, isread, endpt, s; 3686 3687 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3688 xfer, xfer->actlen)); 3689 3690 sqh = epipe->sqh; 3691 if (xfer->pipe->repeat) { 3692 ehci_free_sqtd_chain(sc, sqh, ex->sqtdstart, 3693 ex->sqtdend->nextqtd); 3694 3695 len = epipe->u.intr.length; 3696 xfer->length = len; 3697 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3698 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3699 3700 newinactive = ehci_alloc_sqtd(sc); 3701 if (newinactive == NULL) { 3702 DPRINTFN(-1, 3703 ("ehci_device_intr_done: no sqtd memory\n")); 3704 err = USBD_NOMEM; 3705 xfer->status = err; 3706 return; 3707 } 3708 newinactive->qtd.qtd_status = htole32(0); 3709 newinactive->qtd.qtd_next = EHCI_NULL; 3710 newinactive->qtd.qtd_altnext = EHCI_NULL; 3711 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3712 sqh->inactivesqtd, newinactive, &data, &dataend); 3713 if (err) { 3714 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3715 xfer->status = err; 3716 return; 3717 } 3718 dataend->nextqtd = newinactive; 3719 dataend->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3720 dataend->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3721 sqh->inactivesqtd = newinactive; 3722 EHCI_SQTD_SYNC(sc, newinactive, 3723 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3724 EHCI_SQTD_SYNC(sc, dataend, 3725 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3726 3727 /* Set up interrupt info. */ 3728 exfer->sqtdstart = data; 3729 exfer->sqtdend = dataend; 3730 #ifdef DIAGNOSTIC 3731 if (!exfer->isdone) { 3732 printf("ehci_device_intr_done: not done, ex=%p\n", 3733 exfer); 3734 } 3735 exfer->isdone = 0; 3736 #endif 3737 3738 s = splusb(); 3739 ehci_activate_qh(sc, sqh, data); 3740 if (xfer->timeout && !sc->sc_bus.use_polling) { 3741 usb_callout(xfer->timeout_handle, 3742 MS_TO_TICKS(xfer->timeout), ehci_timeout, xfer); 3743 } 3744 splx(s); 3745 3746 xfer->status = USBD_IN_PROGRESS; 3747 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3748 ehci_del_intr_list(ex); /* remove from active list */ 3749 ehci_free_sqtd_chain(sc, sqh, ex->sqtdstart, 3750 ex->sqtdend->nextqtd); 3751 } 3752 #undef exfer 3753 } 3754 3755 /************************/ 3756 3757 Static usbd_status 3758 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3759 { 3760 return USBD_IOERROR; 3761 } 3762 Static usbd_status 3763 ehci_device_isoc_start(usbd_xfer_handle xfer) 3764 { 3765 return USBD_IOERROR; 3766 } 3767 Static void 3768 ehci_device_isoc_abort(usbd_xfer_handle xfer) 3769 { 3770 } 3771 Static void 3772 ehci_device_isoc_close(usbd_pipe_handle pipe) 3773 { 3774 } 3775 Static void 3776 ehci_device_isoc_done(usbd_xfer_handle xfer) 3777 { 3778 } 3779
Indexes created Wed Oct 01 19:09:53 GMT 2025