ehci.c revision 1.123.12.3
1 /* $NetBSD: ehci.c,v 1.123.12.3 2008/05/21 05:01:45 itohy Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2005, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 41 * 42 * The EHCI 1.0 spec can be found at 43 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 44 * and the USB 2.0 spec at 45 * http://www.usb.org/developers/docs/usb_20.zip 46 * 47 */ 48 49 /* 50 * TODO: 51 * 1) The EHCI driver lacks support for isochronous transfers, so 52 * devices using them don't work. 53 * 54 * 2) Interrupt transfer scheduling does not manage the time available 55 * in each frame, so it is possible for the transfers to overrun 56 * the end of the frame. 57 * 58 * 3) Command failures are not recovered correctly. 59 */ 60 61 #include <sys/cdefs.h> 62 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.123.12.3 2008/05/21 05:01:45 itohy Exp $"); 63 /* __FBSDID("$FreeBSD: /repoman/r/ncvs/src/sys/dev/usb/ehci.c,v 1.52 2006/10/19 01:15:58 iedowse Exp $"); */ 64 65 #if defined(__NetBSD__) || defined(__OpenBSD__) 66 #include "ohci.h" 67 #include "uhci.h" 68 #endif 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/kernel.h> 73 #include <sys/malloc.h> 74 #if defined(__NetBSD__) || defined(__OpenBSD__) 75 #include <sys/device.h> 76 #include <sys/select.h> 77 #elif defined(__FreeBSD__) 78 #include <sys/endian.h> 79 #include <sys/module.h> 80 #include <sys/bus.h> 81 #include <sys/lockmgr.h> 82 #if defined(DIAGNOSTIC) && defined(__i386__) && defined(__FreeBSD__) 83 #include <machine/cpu.h> 84 #endif 85 #endif 86 #include <sys/proc.h> 87 #include <sys/queue.h> 88 #include <sys/sysctl.h> 89 90 #include <machine/bus.h> 91 #include <machine/endian.h> 92 93 #include <dev/usb/usb.h> 94 #include <dev/usb/usbdi.h> 95 #include <dev/usb/usbdivar.h> 96 #include <dev/usb/usb_mem.h> 97 #include <dev/usb/usb_quirks.h> 98 99 #include <dev/usb/ehcireg.h> 100 #include <dev/usb/ehcivar.h> 101 102 #if defined(__FreeBSD__) 103 104 #define delay(d) DELAY(d) 105 #endif 106 107 #ifdef USB_DEBUG 108 /* #define EHCI_DEBUG USB_DEBUG */ 109 #define DPRINTF(x) do { if (ehcidebug) logprintf x; } while (0) 110 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) logprintf x; } while (0) 111 int ehcidebug = 0; 112 #ifdef __FreeBSD__ 113 SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 114 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW, 115 &ehcidebug, 0, "ehci debug level"); 116 #endif 117 #ifndef __NetBSD__ 118 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 119 #endif 120 #else 121 #define DPRINTF(x) 122 #define DPRINTFN(n,x) 123 #endif 124 125 struct ehci_pipe { 126 struct usbd_pipe pipe; 127 128 ehci_soft_qh_t *sqh; 129 union { 130 ehci_soft_qtd_t *qtd; 131 /* ehci_soft_itd_t *itd; */ 132 } tail; 133 union { 134 /* Control pipe */ 135 struct { 136 usb_dma_t reqdma; 137 u_int length; 138 } ctl; 139 /* Interrupt pipe */ 140 struct { 141 u_int length; 142 } intr; 143 /* Bulk pipe */ 144 struct { 145 u_int length; 146 } bulk; 147 /* Iso pipe */ 148 /* XXX */ 149 } u; 150 }; 151 152 Static usbd_status ehci_open(usbd_pipe_handle); 153 Static void ehci_poll(struct usbd_bus *); 154 Static void ehci_softintr(void *); 155 Static int ehci_intr1(ehci_softc_t *); 156 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 157 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 158 Static void ehci_idone(struct ehci_xfer *); 159 Static void ehci_timeout(void *); 160 Static void ehci_timeout_task(void *); 161 Static void ehci_intrlist_timeout(void *); 162 163 Static void ehci_aux_mem_init(struct ehci_aux_mem *); 164 Static usbd_status ehci_aux_mem_alloc(ehci_softc_t *, 165 struct ehci_aux_mem *, 166 int /*naux*/, int /*maxp*/); 167 Static void ehci_aux_mem_free(ehci_softc_t *, 168 struct ehci_aux_mem *); 169 struct aux_desc { 170 void *aux_kern; 171 }; 172 Static bus_addr_t ehci_aux_dma_alloc(struct ehci_aux_mem *, int, 173 struct aux_desc *); 174 Static void ehci_aux_dma_sync(ehci_softc_t *, 175 struct ehci_aux_mem *, int /*op*/); 176 177 Static usbd_status ehci_prealloc(struct ehci_softc *, struct ehci_xfer *, 178 size_t, int); 179 Static usbd_status ehci_allocm(struct usbd_bus *, usbd_xfer_handle, 180 void *, size_t); 181 Static void ehci_freem(struct usbd_bus *, usbd_xfer_handle, 182 enum usbd_waitflg); 183 184 Static usbd_status ehci_map_alloc(usbd_xfer_handle); 185 Static void ehci_map_free(usbd_xfer_handle); 186 Static void ehci_mapm(usbd_xfer_handle, void *, size_t); 187 Static usbd_status ehci_mapm_mbuf(usbd_xfer_handle, struct mbuf *); 188 Static void ehci_unmapm(usbd_xfer_handle); 189 190 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *, usbd_pipe_handle, 191 enum usbd_waitflg); 192 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 193 194 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 195 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 196 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 197 Static void ehci_root_ctrl_close(usbd_pipe_handle); 198 Static void ehci_root_ctrl_done(usbd_xfer_handle); 199 200 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 201 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 202 Static void ehci_root_intr_abort(usbd_xfer_handle); 203 Static void ehci_root_intr_close(usbd_pipe_handle); 204 Static void ehci_root_intr_done(usbd_xfer_handle); 205 206 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 207 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 208 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 209 Static void ehci_device_ctrl_close(usbd_pipe_handle); 210 Static void ehci_device_ctrl_done(usbd_xfer_handle); 211 212 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 213 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 214 Static void ehci_device_bulk_abort(usbd_xfer_handle); 215 Static void ehci_device_bulk_close(usbd_pipe_handle); 216 Static void ehci_device_bulk_done(usbd_xfer_handle); 217 218 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 219 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 220 Static void ehci_device_intr_abort(usbd_xfer_handle); 221 Static void ehci_device_intr_close(usbd_pipe_handle); 222 Static void ehci_device_intr_done(usbd_xfer_handle); 223 224 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 225 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 226 Static void ehci_device_isoc_abort(usbd_xfer_handle); 227 Static void ehci_device_isoc_close(usbd_pipe_handle); 228 Static void ehci_device_isoc_done(usbd_xfer_handle); 229 230 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 231 Static void ehci_noop(usbd_pipe_handle pipe); 232 233 Static int ehci_str(usb_string_descriptor_t *, int, const char *); 234 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 235 Static void ehci_disown(ehci_softc_t *, int, int); 236 237 Static usbd_status ehci_grow_sqtd(ehci_softc_t *); 238 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 239 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 240 241 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 242 Static ehci_soft_qtd_t *ehci_alloc_sqtd_norsv(ehci_softc_t *); 243 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 244 Static void ehci_free_sqtd_norsv(ehci_softc_t *, ehci_soft_qtd_t *); 245 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 246 ehci_softc_t *, int, int, usbd_xfer_handle, 247 ehci_soft_qtd_t *, ehci_soft_qtd_t *, 248 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 249 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qh_t *, 250 ehci_soft_qtd_t *, ehci_soft_qtd_t *); 251 Static void ehci_free_desc_chunks(ehci_softc_t *, 252 struct ehci_mdescs *); 253 254 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 255 256 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 257 int ival); 258 259 Static void ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *, 260 ehci_soft_qh_t *); 261 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 262 ehci_soft_qh_t *); 263 Static void ehci_activate_qh(ehci_softc_t *, ehci_soft_qh_t *, 264 ehci_soft_qtd_t *); 265 Static void ehci_sync_hc(ehci_softc_t *); 266 267 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 268 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 269 270 #ifdef EHCI_DEBUG 271 Static void ehci_dump_regs(ehci_softc_t *); 272 void ehci_dump(void); 273 Static ehci_softc_t *theehci; 274 Static void ehci_dump_link(ehci_link_t, int); 275 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 276 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 277 Static void ehci_dump_qtd(ehci_qtd_t *); 278 Static void ehci_dump_sqh(ehci_soft_qh_t *); 279 #ifdef DIAGNOSTIC 280 Static void ehci_dump_exfer(struct ehci_xfer *); 281 #endif 282 #endif 283 284 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 285 286 #define EHCI_INTR_ENDPT 1 287 288 #define ehci_add_intr_list(sc, ex) \ 289 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext); 290 #define ehci_del_intr_list(ex) \ 291 do { \ 292 LIST_REMOVE((ex), inext); \ 293 (ex)->inext.le_prev = NULL; \ 294 } while (0) 295 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL) 296 297 Static const struct usbd_bus_methods ehci_bus_methods = { 298 ehci_open, 299 ehci_softintr, 300 ehci_poll, 301 ehci_allocm, 302 ehci_freem, 303 ehci_map_alloc, 304 ehci_map_free, 305 ehci_mapm, 306 ehci_mapm_mbuf, 307 ehci_unmapm, 308 ehci_allocx, 309 ehci_freex, 310 }; 311 312 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 313 ehci_root_ctrl_transfer, 314 ehci_root_ctrl_start, 315 ehci_root_ctrl_abort, 316 ehci_root_ctrl_close, 317 ehci_noop, 318 ehci_root_ctrl_done, 319 }; 320 321 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 322 ehci_root_intr_transfer, 323 ehci_root_intr_start, 324 ehci_root_intr_abort, 325 ehci_root_intr_close, 326 ehci_noop, 327 ehci_root_intr_done, 328 }; 329 330 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 331 ehci_device_ctrl_transfer, 332 ehci_device_ctrl_start, 333 ehci_device_ctrl_abort, 334 ehci_device_ctrl_close, 335 ehci_noop, 336 ehci_device_ctrl_done, 337 }; 338 339 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 340 ehci_device_intr_transfer, 341 ehci_device_intr_start, 342 ehci_device_intr_abort, 343 ehci_device_intr_close, 344 ehci_device_clear_toggle, 345 ehci_device_intr_done, 346 }; 347 348 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 349 ehci_device_bulk_transfer, 350 ehci_device_bulk_start, 351 ehci_device_bulk_abort, 352 ehci_device_bulk_close, 353 ehci_device_clear_toggle, 354 ehci_device_bulk_done, 355 }; 356 357 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 358 ehci_device_isoc_transfer, 359 ehci_device_isoc_start, 360 ehci_device_isoc_abort, 361 ehci_device_isoc_close, 362 ehci_noop, 363 ehci_device_isoc_done, 364 }; 365 366 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 367 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 368 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 369 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 370 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 371 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 372 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 373 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 374 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 375 }; 376 377 usbd_status 378 ehci_init(ehci_softc_t *sc) 379 { 380 u_int32_t vers, sparams, cparams, hcr; 381 u_int i; 382 usbd_status err; 383 ehci_soft_qh_t *sqh; 384 u_int ncomp; 385 int lev; 386 387 DPRINTF(("ehci_init: start\n")); 388 #ifdef EHCI_DEBUG 389 theehci = sc; 390 #endif 391 392 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 393 394 vers = EREAD2(sc, EHCI_HCIVERSION); 395 aprint_verbose("%s: EHCI version %x.%x\n", USBDEVNAME(sc->sc_bus.bdev), 396 vers >> 8, vers & 0xff); 397 398 sparams = EREAD4(sc, EHCI_HCSPARAMS); 399 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 400 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 401 ncomp = EHCI_HCS_N_CC(sparams); 402 if (ncomp != sc->sc_ncomp) { 403 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 404 USBDEVNAME(sc->sc_bus.bdev), 405 ncomp, sc->sc_ncomp); 406 if (ncomp < sc->sc_ncomp) 407 sc->sc_ncomp = ncomp; 408 } 409 if (sc->sc_ncomp > 0) { 410 printf("%s: companion controller%s, %d port%s each:", 411 USBDEVNAME(sc->sc_bus.bdev), sc->sc_ncomp!=1 ? "s" : "", 412 EHCI_HCS_N_PCC(sparams), 413 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 414 for (i = 0; i < sc->sc_ncomp; i++) 415 printf(" %s", USBDEVNAME(sc->sc_comps[i]->bdev)); 416 printf("\n"); 417 } 418 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 419 cparams = EREAD4(sc, EHCI_HCCPARAMS); 420 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 421 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 422 423 if (EHCI_HCC_64BIT(cparams)) { 424 /* MUST clear segment register if 64 bit capable. */ 425 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 426 } 427 428 sc->sc_bus.usbrev = USBREV_2_0; 429 usb_dma_tag_init(&sc->sc_dmatag); 430 431 /* Reset the controller */ 432 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 433 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 434 usb_delay_ms(&sc->sc_bus, 1); 435 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 436 for (i = 0; i < 100; i++) { 437 usb_delay_ms(&sc->sc_bus, 1); 438 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 439 if (!hcr) 440 break; 441 } 442 if (hcr) { 443 printf("%s: reset timeout\n", 444 USBDEVNAME(sc->sc_bus.bdev)); 445 return (USBD_IOERROR); 446 } 447 448 /* frame list size at default, read back what we got and use that */ 449 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 450 case 0: sc->sc_flsize = 1024; break; 451 case 1: sc->sc_flsize = 512; break; 452 case 2: sc->sc_flsize = 256; break; 453 case 3: return (USBD_IOERROR); 454 } 455 err = usb_allocmem(&sc->sc_dmatag, sc->sc_flsize * sizeof(ehci_link_t), 456 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 457 if (err) 458 return (err); 459 DPRINTF(("%s: flsize=%d\n", USBDEVNAME(sc->sc_bus.bdev),sc->sc_flsize)); 460 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 461 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 462 463 /* Set up the bus struct. */ 464 sc->sc_bus.methods = &ehci_bus_methods; 465 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 466 467 #if defined(__NetBSD__) || defined(__OpenBSD__) 468 sc->sc_powerhook = powerhook_establish(USBDEVNAME(sc->sc_bus.bdev), 469 ehci_power, sc); 470 sc->sc_shutdownhook = shutdownhook_establish(ehci_shutdown, sc); 471 #endif 472 473 sc->sc_eintrs = EHCI_NORMAL_INTRS; 474 475 /* 476 * Allocate the interrupt dummy QHs. These are arranged to give 477 * poll intervals that are powers of 2 times 1ms. 478 */ 479 for (i = 0; i < EHCI_INTRQHS; i++) { 480 sqh = ehci_alloc_sqh(sc); 481 if (sqh == NULL) { 482 err = USBD_NOMEM; 483 goto bad1; 484 } 485 sc->sc_islots[i].sqh = sqh; 486 } 487 lev = 0; 488 for (i = 0; i < EHCI_INTRQHS; i++) { 489 if (i == EHCI_IQHIDX(lev + 1, 0)) 490 lev++; 491 sqh = sc->sc_islots[i].sqh; 492 if (i == 0) { 493 /* The last (1ms) QH terminates. */ 494 sqh->qh.qh_link = EHCI_NULL; 495 sqh->next = NULL; 496 } else { 497 /* Otherwise the next QH has half the poll interval */ 498 sqh->next = 499 sc->sc_islots[EHCI_IQHIDX(lev - 1, i + 1)].sqh; 500 sqh->qh.qh_link = htole32(EHCI_SQH_DMAADDR(sqh->next) | 501 EHCI_LINK_QH); 502 } 503 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 504 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 505 sqh->qh.qh_curqtd = EHCI_NULL; 506 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 507 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 508 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 509 } 510 /* Point the frame list at the last level (128ms). */ 511 for (i = 0; i < sc->sc_flsize; i++) { 512 int j; 513 514 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 515 revbits[i & (EHCI_MAX_POLLRATE-1)]; 516 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 517 EHCI_SQH_DMAADDR(sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES 518 - 1, i)].sqh)); 519 } 520 EHCI_SQH_SYNC(sc, sqh, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 521 522 /* Allocate dummy QH that starts the async list. */ 523 sqh = ehci_alloc_sqh(sc); 524 if (sqh == NULL) { 525 err = USBD_NOMEM; 526 goto bad1; 527 } 528 /* Fill the QH */ 529 sqh->qh.qh_endp = 530 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 531 sqh->qh.qh_link = 532 htole32(EHCI_SQH_DMAADDR(sqh) | EHCI_LINK_QH); 533 sqh->qh.qh_curqtd = EHCI_NULL; 534 sqh->prev = sqh; /*It's a circular list.. */ 535 sqh->next = sqh; 536 /* Fill the overlay qTD */ 537 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 538 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 539 sqh->qh.qh_qtd.qtd_status = htole32(0); 540 #ifdef EHCI_DEBUG 541 if (ehcidebug) { 542 ehci_dump_sqh(sqh); 543 } 544 #endif 545 EHCI_SQH_SYNC(sc, sqh, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 546 547 /* Point to async list */ 548 sc->sc_async_head = sqh; 549 EOWRITE4(sc, EHCI_ASYNCLISTADDR, EHCI_SQH_DMAADDR(sqh) | EHCI_LINK_QH); 550 551 usb_callout_init(sc->sc_tmo_intrlist); 552 553 lockinit(&sc->sc_doorbell_lock, PZERO, "ehcidb", 0, 0); 554 555 /* Enable interrupts */ 556 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 557 558 /* Turn on controller */ 559 EOWRITE4(sc, EHCI_USBCMD, 560 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 561 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 562 EHCI_CMD_ASE | 563 EHCI_CMD_PSE | 564 EHCI_CMD_RS); 565 566 /* Take over port ownership */ 567 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 568 569 for (i = 0; i < 100; i++) { 570 usb_delay_ms(&sc->sc_bus, 1); 571 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 572 if (!hcr) 573 break; 574 } 575 if (hcr) { 576 printf("%s: run timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 577 return (USBD_IOERROR); 578 } 579 580 /* Enable interrupts */ 581 DPRINTFN(1,("ehci_init: enabling\n")); 582 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 583 584 return (USBD_NORMAL_COMPLETION); 585 586 #if 0 587 bad2: 588 ehci_free_sqh(sc, sc->sc_async_head); 589 #endif 590 bad1: 591 usb_freemem(&sc->sc_dmatag, &sc->sc_fldma); 592 usb_dma_tag_finish(&sc->sc_dmatag); 593 return (err); 594 } 595 596 int 597 ehci_intr(void *v) 598 { 599 ehci_softc_t *sc = v; 600 601 if (sc == NULL || sc->sc_dying) 602 return (0); 603 604 /* If we get an interrupt while polling, then just ignore it. */ 605 if (sc->sc_bus.use_polling) { 606 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 607 608 if (intrs) 609 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 610 #ifdef DIAGNOSTIC 611 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 612 #endif 613 return (0); 614 } 615 616 return (ehci_intr1(sc)); 617 } 618 619 Static int 620 ehci_intr1(ehci_softc_t *sc) 621 { 622 u_int32_t intrs, eintrs; 623 624 DPRINTFN(20,("ehci_intr1: enter\n")); 625 626 /* In case the interrupt occurs before initialization has completed. */ 627 if (sc == NULL) { 628 #ifdef DIAGNOSTIC 629 printf("ehci_intr1: sc == NULL\n"); 630 #endif 631 return (0); 632 } 633 634 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 635 if (!intrs) 636 return (0); 637 638 eintrs = intrs & sc->sc_eintrs; 639 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 640 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 641 (u_int)eintrs)); 642 if (!eintrs) 643 return (0); 644 645 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 646 sc->sc_bus.intr_context++; 647 sc->sc_bus.no_intrs++; 648 if (eintrs & EHCI_STS_IAA) { 649 DPRINTF(("ehci_intr1: door bell\n")); 650 wakeup(&sc->sc_async_head); 651 eintrs &= ~EHCI_STS_IAA; 652 } 653 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 654 DPRINTFN(5,("ehci_intr1: %s %s\n", 655 eintrs & EHCI_STS_INT ? "INT" : "", 656 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 657 usb_schedsoftintr(&sc->sc_bus); 658 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 659 } 660 if (eintrs & EHCI_STS_HSE) { 661 printf("%s: unrecoverable error, controller halted\n", 662 USBDEVNAME(sc->sc_bus.bdev)); 663 /* XXX what else */ 664 } 665 if (eintrs & EHCI_STS_PCD) { 666 ehci_pcd(sc, sc->sc_intrxfer); 667 eintrs &= ~EHCI_STS_PCD; 668 } 669 670 sc->sc_bus.intr_context--; 671 672 if (eintrs != 0) { 673 /* Block unprocessed interrupts. */ 674 sc->sc_eintrs &= ~eintrs; 675 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 676 printf("%s: blocking intrs 0x%x\n", 677 USBDEVNAME(sc->sc_bus.bdev), eintrs); 678 } 679 680 return (1); 681 } 682 683 684 void 685 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 686 { 687 usbd_pipe_handle pipe; 688 u_char *p; 689 int i, m; 690 691 if (xfer == NULL) { 692 /* Just ignore the change. */ 693 return; 694 } 695 696 pipe = xfer->pipe; 697 698 p = xfer->hcbuffer; 699 m = min(sc->sc_noport, xfer->length * 8 - 1); 700 memset(p, 0, xfer->length); 701 for (i = 1; i <= m; i++) { 702 /* Pick out CHANGE bits from the status reg. */ 703 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 704 p[i/8] |= 1 << (i%8); 705 } 706 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 707 xfer->actlen = xfer->length; 708 xfer->status = USBD_NORMAL_COMPLETION; 709 710 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 711 } 712 713 void 714 ehci_softintr(void *v) 715 { 716 ehci_softc_t *sc = v; 717 struct ehci_xfer *ex, *nextex; 718 719 DPRINTFN(10,("%s: ehci_softintr (%d)\n", USBDEVNAME(sc->sc_bus.bdev), 720 sc->sc_bus.intr_context)); 721 722 sc->sc_bus.intr_context++; 723 724 /* 725 * The only explanation I can think of for why EHCI is as brain dead 726 * as UHCI interrupt-wise is that Intel was involved in both. 727 * An interrupt just tells us that something is done, we have no 728 * clue what, so we need to scan through all active transfers. :-( 729 */ 730 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 731 nextex = LIST_NEXT(ex, inext); 732 ehci_check_intr(sc, ex); 733 } 734 735 /* Schedule a callout to catch any dropped transactions. */ 736 if ((sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) && 737 !LIST_EMPTY(&sc->sc_intrhead)) 738 usb_callout(sc->sc_tmo_intrlist, hz / 5, ehci_intrlist_timeout, 739 sc); 740 741 /* Schedule a callout to catch any dropped transactions. */ 742 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 743 !LIST_EMPTY(&sc->sc_intrhead)) 744 usb_callout(sc->sc_tmo_intrlist, hz, 745 ehci_intrlist_timeout, sc); 746 747 #ifdef USB_USE_SOFTINTR 748 if (sc->sc_softwake) { 749 sc->sc_softwake = 0; 750 wakeup(&sc->sc_softwake); 751 } 752 #endif /* USB_USE_SOFTINTR */ 753 754 sc->sc_bus.intr_context--; 755 } 756 757 /* Check for an interrupt. */ 758 void 759 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 760 { 761 ehci_soft_qtd_t *sqtd, *lsqtd; 762 u_int32_t status; 763 764 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 765 766 if (ex->sqtdstart == NULL) { 767 printf("ehci_check_intr: sqtdstart=NULL\n"); 768 return; 769 } 770 lsqtd = ex->sqtdend; 771 #ifdef DIAGNOSTIC 772 if (lsqtd == NULL) { 773 printf("ehci_check_intr: lsqtd==0\n"); 774 return; 775 } 776 #endif 777 /* 778 * If the last TD is still active we need to check whether there 779 * is a an error somewhere in the middle, or whether there was a 780 * short packet (SPD and not ACTIVE). 781 */ 782 EHCI_SQTD_SYNC(sc, lsqtd, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 783 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 784 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 785 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 786 EHCI_SQTD_SYNC(sc, sqtd, 787 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 788 status = le32toh(sqtd->qtd.qtd_status); 789 /* If there's an active QTD the xfer isn't done. */ 790 if (status & EHCI_QTD_ACTIVE) 791 break; 792 /* Any kind of error makes the xfer done. */ 793 if (status & EHCI_QTD_HALTED) 794 goto done; 795 /* We want short packets, and it is short: it's done */ 796 if (EHCI_QTD_GET_BYTES(status) != 0) 797 goto done; 798 } 799 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 800 ex, ex->sqtdstart)); 801 return; 802 } 803 done: 804 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 805 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 806 usb_rem_task(ex->xfer.pipe->device, &ex->abort_task); 807 ehci_idone(ex); 808 } 809 810 void 811 ehci_idone(struct ehci_xfer *ex) 812 { 813 usbd_xfer_handle xfer = &ex->xfer; 814 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 815 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 816 ehci_soft_qtd_t *sqtd, *lsqtd; 817 u_int32_t status = 0, nstatus = 0; 818 ehci_physaddr_t nextphys, altnextphys; 819 ehci_physaddr_t stdma; 820 int actlen, cerr; 821 822 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 823 #ifdef DIAGNOSTIC 824 { 825 int s = splhigh(); 826 if (ex->isdone) { 827 splx(s); 828 #ifdef EHCI_DEBUG 829 printf("ehci_idone: ex is done!\n "); 830 ehci_dump_exfer(ex); 831 #else 832 printf("ehci_idone: ex=%p is done!\n", ex); 833 #endif 834 return; 835 } 836 ex->isdone = 1; 837 splx(s); 838 } 839 #endif 840 841 if (xfer->status == USBD_CANCELLED || 842 xfer->status == USBD_TIMEOUT) { 843 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 844 return; 845 } 846 847 #ifdef EHCI_DEBUG 848 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 849 if (ehcidebug > 10) 850 ehci_dump_sqtds(ex->sqtdstart); 851 #endif 852 853 /* 854 * Make sure that the QH overlay qTD does not reference any 855 * of the qTDs we are about to free. This is probably only 856 * necessary if the transfer is marked as HALTED. 857 */ 858 EHCI_SQH_SYNC(sc, epipe->sqh, 859 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 860 nextphys = EHCI_LINK_ADDR(le32toh(epipe->sqh->qh.qh_qtd.qtd_next)); 861 altnextphys = 862 EHCI_LINK_ADDR(le32toh(epipe->sqh->qh.qh_qtd.qtd_altnext)); 863 for (sqtd = ex->sqtdstart; sqtd != ex->sqtdend->nextqtd; 864 sqtd = sqtd->nextqtd) { 865 stdma = EHCI_SQTD_DMAADDR(sqtd); 866 if (stdma == nextphys) { 867 epipe->sqh->qh.qh_qtd.qtd_next = 868 htole32(EHCI_SQTD_DMAADDR(ex->sqtdend->nextqtd)); 869 DPRINTFN(4, ("ehci_idone: updated overlay next ptr\n")); 870 EHCI_SQH_SYNC(sc, epipe->sqh, 871 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 872 873 } 874 if (stdma == altnextphys) { 875 DPRINTFN(4, 876 ("ehci_idone: updated overlay altnext ptr\n")); 877 epipe->sqh->qh.qh_qtd.qtd_altnext = 878 htole32(EHCI_SQTD_DMAADDR(ex->sqtdend->nextqtd)); 879 EHCI_SQH_SYNC(sc, epipe->sqh, 880 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 881 } 882 } 883 884 /* The transfer is done, compute actual length and status. */ 885 lsqtd = ex->sqtdend; 886 actlen = 0; 887 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd=sqtd->nextqtd) { 888 EHCI_SQTD_SYNC(sc, sqtd, 889 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 890 nstatus = le32toh(sqtd->qtd.qtd_status); 891 if (nstatus & EHCI_QTD_ACTIVE) 892 break; 893 894 status = nstatus; 895 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 896 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 897 } 898 899 cerr = EHCI_QTD_GET_CERR(status); 900 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, " 901 "status=0x%x\n", xfer->length, actlen, cerr, status)); 902 xfer->actlen = actlen; 903 if ((status & EHCI_QTD_HALTED) != 0) { 904 #ifdef EHCI_DEBUG 905 char sbuf[128]; 906 907 bitmask_snprintf((u_int32_t)status, 908 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 909 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 910 911 DPRINTFN(2, 912 ("ehci_idone: error, addr=%d, endpt=0x%02x, " 913 "status 0x%s\n", 914 xfer->pipe->device->address, 915 xfer->pipe->endpoint->edesc->bEndpointAddress, 916 sbuf)); 917 if (ehcidebug > 2) { 918 ehci_dump_sqh(epipe->sqh); 919 ehci_dump_sqtds(ex->sqtdstart); 920 } 921 #endif 922 /* low&full speed has an extra error flag */ 923 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 924 EHCI_QH_SPEED_HIGH) 925 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 926 else 927 status &= EHCI_QTD_STATERRS; 928 if (status == 0) /* no other errors means a stall */ 929 xfer->status = USBD_STALLED; 930 else 931 xfer->status = USBD_IOERROR; /* more info XXX */ 932 /* XXX need to reset TT on missed microframe */ 933 if (status & EHCI_QTD_MISSEDMICRO) { 934 printf("%s: missed microframe, TT reset not " 935 "implemented, hub might be inoperational\n", 936 USBDEVNAME(sc->sc_bus.bdev)); 937 } 938 } else { 939 xfer->status = USBD_NORMAL_COMPLETION; 940 } 941 942 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 943 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 944 } 945 946 /* 947 * Wait here until controller claims to have an interrupt. 948 * Then call ehci_intr and return. Use timeout to avoid waiting 949 * too long. 950 */ 951 void 952 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 953 { 954 int timo; 955 u_int32_t intrs; 956 957 xfer->status = USBD_IN_PROGRESS; 958 for (timo = xfer->timeout; timo >= 0; timo--) { 959 usb_delay_ms(&sc->sc_bus, 1); 960 if (sc->sc_dying) 961 break; 962 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 963 sc->sc_eintrs; 964 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 965 #ifdef EHCI_DEBUG 966 if (ehcidebug > 15) 967 ehci_dump_regs(sc); 968 #endif 969 if (intrs) { 970 ehci_intr1(sc); 971 if (xfer->status != USBD_IN_PROGRESS) 972 return; 973 } 974 } 975 976 /* Timeout */ 977 DPRINTF(("ehci_waitintr: timeout\n")); 978 xfer->status = USBD_TIMEOUT; 979 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 980 /* XXX should free TD */ 981 } 982 983 void 984 ehci_poll(struct usbd_bus *bus) 985 { 986 ehci_softc_t *sc = (ehci_softc_t *)bus; 987 #ifdef EHCI_DEBUG 988 static int last; 989 int new; 990 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 991 if (new != last) { 992 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 993 last = new; 994 } 995 #endif 996 997 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 998 ehci_intr1(sc); 999 } 1000 1001 int 1002 ehci_detach(struct ehci_softc *sc, int flags) 1003 { 1004 int rv = 0; 1005 usbd_xfer_handle xfer; 1006 1007 #if defined(__NetBSD__) || defined(__OpenBSD__) 1008 if (sc->sc_child != NULL) 1009 rv = config_detach(sc->sc_child, flags); 1010 1011 if (rv != 0) 1012 return (rv); 1013 #else 1014 sc->sc_dying = 1; 1015 #endif 1016 1017 if (sc->sc_bus.methods == NULL) 1018 return (rv); /* attach has been aborted */ 1019 1020 #if defined(__NetBSD__) || defined(__OpenBSD__) 1021 /* Don't touch hardware if it has already been gone. */ 1022 if ((flags & DETACH_FORCE) == 0) 1023 #endif 1024 { 1025 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1026 EOWRITE4(sc, EHCI_USBCMD, 0); 1027 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1028 } 1029 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 1030 1031 #if defined(__NetBSD__) || defined(__OpenBSD__) 1032 if (sc->sc_powerhook != NULL) 1033 powerhook_disestablish(sc->sc_powerhook); 1034 if (sc->sc_shutdownhook != NULL) 1035 shutdownhook_disestablish(sc->sc_shutdownhook); 1036 #endif 1037 1038 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1039 1040 usb_freemem(&sc->sc_dmatag, &sc->sc_fldma); 1041 /* XXX free other data structures XXX */ 1042 1043 while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 1044 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1045 usb_clean_buffer_dma(&sc->sc_dmatag, &EXFER(xfer)->dmabuf); 1046 free(xfer, M_USB); 1047 } 1048 ehci_free_desc_chunks(sc, &sc->sc_sqh_chunks); 1049 ehci_free_desc_chunks(sc, &sc->sc_sqtd_chunks); 1050 usb_dma_tag_finish(&sc->sc_dmatag); 1051 1052 return (rv); 1053 } 1054 1055 Static void 1056 ehci_free_desc_chunks(ehci_softc_t *sc, struct ehci_mdescs *c) 1057 { 1058 struct ehci_mem_desc *em; 1059 1060 while ((em = SIMPLEQ_FIRST(c)) != NULL) { 1061 SIMPLEQ_REMOVE_HEAD(c, em_next); 1062 usb_freemem(&sc->sc_dmatag, &em->em_dma); 1063 } 1064 } 1065 1066 #if defined(__NetBSD__) || defined(__OpenBSD__) 1067 int 1068 ehci_activate(device_t self, enum devact act) 1069 { 1070 struct ehci_softc *sc = (struct ehci_softc *)self; 1071 int rv = 0; 1072 1073 switch (act) { 1074 case DVACT_ACTIVATE: 1075 return (EOPNOTSUPP); 1076 1077 case DVACT_DEACTIVATE: 1078 if (sc->sc_child != NULL) 1079 rv = config_deactivate(sc->sc_child); 1080 sc->sc_dying = 1; 1081 break; 1082 } 1083 return (rv); 1084 } 1085 #endif 1086 1087 /* 1088 * Handle suspend/resume. 1089 * 1090 * We need to switch to polling mode here, because this routine is 1091 * called from an interrupt context. This is all right since we 1092 * are almost suspended anyway. 1093 */ 1094 void 1095 ehci_power(int why, void *v) 1096 { 1097 ehci_softc_t *sc = v; 1098 u_int32_t cmd, hcr; 1099 int s, i; 1100 1101 #ifdef EHCI_DEBUG 1102 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why)); 1103 if (ehcidebug > 0) 1104 ehci_dump_regs(sc); 1105 #endif 1106 1107 s = splhardusb(); 1108 switch (why) { 1109 USB_PWR_CASE_SUSPEND: 1110 sc->sc_bus.use_polling++; 1111 1112 for (i = 1; i <= sc->sc_noport; i++) { 1113 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1114 if ((cmd & EHCI_PS_PO) == 0 && 1115 (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1116 EOWRITE4(sc, EHCI_PORTSC(i), 1117 cmd | EHCI_PS_SUSP); 1118 } 1119 1120 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1121 1122 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1123 EOWRITE4(sc, EHCI_USBCMD, cmd); 1124 1125 for (i = 0; i < 100; i++) { 1126 hcr = EOREAD4(sc, EHCI_USBSTS) & 1127 (EHCI_STS_ASS | EHCI_STS_PSS); 1128 if (hcr == 0) 1129 break; 1130 1131 usb_delay_ms(&sc->sc_bus, 1); 1132 } 1133 if (hcr != 0) { 1134 printf("%s: reset timeout\n", 1135 USBDEVNAME(sc->sc_bus.bdev)); 1136 } 1137 1138 cmd &= ~EHCI_CMD_RS; 1139 EOWRITE4(sc, EHCI_USBCMD, cmd); 1140 1141 for (i = 0; i < 100; i++) { 1142 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1143 if (hcr == EHCI_STS_HCH) 1144 break; 1145 1146 usb_delay_ms(&sc->sc_bus, 1); 1147 } 1148 if (hcr != EHCI_STS_HCH) { 1149 printf("%s: config timeout\n", 1150 USBDEVNAME(sc->sc_bus.bdev)); 1151 } 1152 1153 sc->sc_bus.use_polling--; 1154 break; 1155 1156 USB_PWR_CASE_RESUME: 1157 sc->sc_bus.use_polling++; 1158 1159 /* restore things in case the bios sucks */ 1160 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1161 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1162 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1163 EHCI_SQH_DMAADDR(sc->sc_async_head) | EHCI_LINK_QH); 1164 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1165 1166 hcr = 0; 1167 for (i = 1; i <= sc->sc_noport; i++) { 1168 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1169 if ((cmd & EHCI_PS_PO) == 0 && 1170 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1171 EOWRITE4(sc, EHCI_PORTSC(i), 1172 cmd | EHCI_PS_FPR); 1173 hcr = 1; 1174 } 1175 } 1176 1177 if (hcr) { 1178 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1179 1180 for (i = 1; i <= sc->sc_noport; i++) { 1181 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1182 if ((cmd & EHCI_PS_PO) == 0 && 1183 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1184 EOWRITE4(sc, EHCI_PORTSC(i), 1185 cmd & ~EHCI_PS_FPR); 1186 } 1187 } 1188 1189 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1190 1191 for (i = 0; i < 100; i++) { 1192 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1193 if (hcr != EHCI_STS_HCH) 1194 break; 1195 1196 usb_delay_ms(&sc->sc_bus, 1); 1197 } 1198 if (hcr == EHCI_STS_HCH) { 1199 printf("%s: config timeout\n", 1200 USBDEVNAME(sc->sc_bus.bdev)); 1201 } 1202 1203 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1204 1205 sc->sc_bus.use_polling--; 1206 break; 1207 1208 default: 1209 break; 1210 } 1211 splx(s); 1212 1213 #ifdef EHCI_DEBUG 1214 DPRINTF(("ehci_power: sc=%p\n", sc)); 1215 if (ehcidebug > 0) 1216 ehci_dump_regs(sc); 1217 #endif 1218 } 1219 1220 /* 1221 * Shut down the controller when the system is going down. 1222 */ 1223 void 1224 ehci_shutdown(void *v) 1225 { 1226 ehci_softc_t *sc = v; 1227 1228 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1229 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1230 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1231 } 1232 1233 /* 1234 * Allocate a physically contiguous buffer to handle cases where EHCI 1235 * cannot handle a packet because it is not physically contiguous. 1236 */ 1237 Static void 1238 ehci_aux_mem_init(struct ehci_aux_mem *aux) 1239 { 1240 1241 aux->aux_curchunk = aux->aux_chunkoff = aux->aux_naux = 0; 1242 } 1243 1244 Static usbd_status 1245 ehci_aux_mem_alloc(ehci_softc_t *sc, struct ehci_aux_mem *aux, 1246 int naux, int maxp) 1247 { 1248 int nchunk, i, j; 1249 usbd_status err; 1250 1251 USB_KASSERT(aux->aux_nchunk == 0); 1252 1253 nchunk = EHCI_NCHUNK(naux, maxp); 1254 for (i = 0; i < nchunk; i++) { 1255 err = usb_allocmem(&sc->sc_dmatag, EHCI_AUX_CHUNK_SIZE, 1256 EHCI_AUX_CHUNK_SIZE, &aux->aux_chunk_dma[i]); 1257 if (err) { 1258 for (j = 0; j < i; j++) 1259 usb_freemem(&sc->sc_dmatag, 1260 &aux->aux_chunk_dma[j]); 1261 return (err); 1262 } 1263 } 1264 1265 aux->aux_nchunk = nchunk; 1266 ehci_aux_mem_init(aux); 1267 1268 return (USBD_NORMAL_COMPLETION); 1269 } 1270 1271 Static void 1272 ehci_aux_mem_free(ehci_softc_t *sc, struct ehci_aux_mem *aux) 1273 { 1274 int i; 1275 1276 /* sync last aux (just in case, probably a no-op) */ 1277 if (aux->aux_naux) 1278 ehci_aux_dma_sync(sc, aux, BUS_DMASYNC_POSTWRITE); 1279 1280 for (i = 0; i < aux->aux_nchunk; i++) 1281 usb_freemem(&sc->sc_dmatag, &aux->aux_chunk_dma[i]); 1282 1283 aux->aux_nchunk = 0; 1284 } 1285 1286 Static bus_addr_t 1287 ehci_aux_dma_alloc(struct ehci_aux_mem *aux, int len, struct aux_desc *ad) 1288 { 1289 bus_addr_t auxdma; 1290 1291 if (aux->aux_chunkoff + len > EHCI_AUX_CHUNK_SIZE) { 1292 aux->aux_curchunk++; 1293 aux->aux_chunkoff = 0; 1294 } 1295 USB_KASSERT(aux->aux_curchunk < aux->aux_nchunk); 1296 1297 auxdma = 1298 DMAADDR(&aux->aux_chunk_dma[aux->aux_curchunk], aux->aux_chunkoff); 1299 ad->aux_kern = 1300 KERNADDR(&aux->aux_chunk_dma[aux->aux_curchunk], aux->aux_chunkoff); 1301 1302 aux->aux_chunkoff += len; 1303 aux->aux_naux++; 1304 1305 return auxdma; 1306 } 1307 1308 Static void 1309 ehci_aux_dma_sync(ehci_softc_t *sc, struct ehci_aux_mem *aux, int op) 1310 { 1311 int i; 1312 1313 for (i = 0; i < aux->aux_curchunk; i++) 1314 USB_MEM_SYNC(&sc->sc_dmatag, &aux->aux_chunk_dma[i], op); 1315 if (aux->aux_chunkoff) 1316 USB_MEM_SYNC2(&sc->sc_dmatag, &aux->aux_chunk_dma[i], 1317 0, aux->aux_chunkoff, op); 1318 } 1319 1320 Static usbd_status 1321 ehci_prealloc(struct ehci_softc *sc, struct ehci_xfer *exfer, 1322 size_t bufsize, int nseg) 1323 { 1324 usb_endpoint_descriptor_t *endpt; 1325 int maxseg, mps, naux; 1326 int seglen, ntd; 1327 int s; 1328 int err; 1329 1330 endpt = exfer->xfer.pipe->endpoint->edesc; 1331 mps = UE_MAXPKTSZ(endpt); 1332 1333 if (mps == 0) 1334 return (USBD_INVAL); 1335 1336 /* (over) estimate needed number of TDs */ 1337 maxseg = EHCI_PAGE_SIZE * EHCI_QTD_NBUFFERS; 1338 seglen = maxseg - (maxseg % mps); 1339 ntd = bufsize / seglen + nseg; 1340 1341 #if 1 1342 /* allocate aux buffer for non-isoc OUT transfer */ 1343 naux = 0; 1344 if (nseg > 1 && 1345 (endpt->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS && 1346 UE_GET_DIR(endpt->bEndpointAddress) == UE_DIR_OUT) { 1347 /* estimate needed aux segments */ 1348 naux = nseg - 1; 1349 1350 /* pre-allocate aux memory */ 1351 err = ehci_aux_mem_alloc(sc, &exfer->aux, naux, mps); 1352 if (err) 1353 return err; 1354 1355 /* an aux segment will consume a TD */ 1356 ntd += naux; 1357 } 1358 #endif 1359 1360 s = splusb(); 1361 /* pre-allocate QDs */ 1362 /* XXX ITDs */ 1363 while (sc->sc_nfreeqtds < ntd) { 1364 DPRINTF(("%s: qhci_prealloc: need %d QTD (%d cur)\n", 1365 USBDEVNAME(sc->sc_bus.bdev), ntd, sc->sc_nfreeqtds)); 1366 if ((err = ehci_grow_sqtd(sc)) != USBD_NORMAL_COMPLETION) { 1367 splx(s); 1368 ehci_aux_mem_free(sc, &exfer->aux); 1369 return err; 1370 } 1371 } 1372 sc->sc_nfreeqtds -= ntd; 1373 splx(s); 1374 1375 exfer->rsvd_tds = ntd; 1376 1377 return USBD_NORMAL_COMPLETION; 1378 } 1379 1380 usbd_status 1381 ehci_allocm(struct usbd_bus *bus, usbd_xfer_handle xfer, void *buf, size_t size) 1382 { 1383 struct ehci_softc *sc = (struct ehci_softc *)bus; 1384 struct ehci_xfer *exfer = EXFER(xfer); 1385 usbd_status err; 1386 1387 if ((err = usb_alloc_buffer_dma(&sc->sc_dmatag, &exfer->dmabuf, 1388 buf, size, &xfer->hcbuffer)) == USBD_NORMAL_COMPLETION) { 1389 if ((xfer->rqflags & URQ_DEV_MAP_PREPARED) == 0 && 1390 (err = ehci_prealloc(sc, exfer, size, 1391 USB_BUFFER_NSEGS(&exfer->dmabuf))) 1392 != USBD_NORMAL_COMPLETION) { 1393 usb_free_buffer_dma(&sc->sc_dmatag, &exfer->dmabuf, 1394 U_WAITOK); 1395 } 1396 } 1397 #ifdef EHCI_DEBUG 1398 if (err) 1399 printf("ehci_allocm: usb_alloc_buffer_dma()=%d\n", err); 1400 #endif 1401 return (err); 1402 } 1403 1404 void 1405 ehci_freem(struct usbd_bus *bus, usbd_xfer_handle xfer, 1406 enum usbd_waitflg waitflg) 1407 { 1408 struct ehci_softc *sc = (struct ehci_softc *)bus; 1409 struct ehci_xfer *exfer = EXFER(xfer); 1410 int s; 1411 1412 usb_free_buffer_dma(&sc->sc_dmatag, &exfer->dmabuf, waitflg); 1413 1414 if ((xfer->rqflags & URQ_DEV_MAP_PREPARED) == 0) { 1415 /* XXX ITDs */ 1416 1417 s = splusb(); 1418 sc->sc_nfreeqtds += exfer->rsvd_tds; 1419 splx(s); 1420 exfer->rsvd_tds = 0; 1421 ehci_aux_mem_free(sc, &exfer->aux); 1422 } 1423 } 1424 1425 Static usbd_status 1426 ehci_map_alloc(usbd_xfer_handle xfer) 1427 { 1428 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1429 struct ehci_xfer *exfer = EXFER(xfer); 1430 usbd_status st; 1431 1432 st = usb_alloc_dma_resources(&sc->sc_dmatag, &exfer->dmabuf); 1433 if (st) 1434 return st; 1435 1436 if ((st = ehci_prealloc(sc, exfer, MAXPHYS, USB_DMA_NSEG))) { 1437 usb_free_dma_resources(&sc->sc_dmatag, &exfer->dmabuf); 1438 } 1439 1440 return st; 1441 } 1442 1443 Static void 1444 ehci_map_free(usbd_xfer_handle xfer) 1445 { 1446 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1447 struct ehci_xfer *exfer = EXFER(xfer); 1448 int s; 1449 1450 USB_KASSERT(xfer->rqflags & URQ_DEV_MAP_PREPARED); 1451 1452 usb_free_dma_resources(&sc->sc_dmatag, &exfer->dmabuf); 1453 1454 /* XXX ITDs */ 1455 1456 s = splusb(); 1457 sc->sc_nfreeqtds += exfer->rsvd_tds; 1458 splx(s); 1459 exfer->rsvd_tds = 0; 1460 ehci_aux_mem_free(sc, &exfer->aux); 1461 } 1462 1463 Static void 1464 ehci_mapm(usbd_xfer_handle xfer, void *buf, size_t size) 1465 { 1466 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1467 struct ehci_xfer *exfer = EXFER(xfer); 1468 1469 usb_map_dma(&sc->sc_dmatag, &exfer->dmabuf, buf, size); 1470 } 1471 1472 Static usbd_status 1473 ehci_mapm_mbuf(usbd_xfer_handle xfer, struct mbuf *chain) 1474 { 1475 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1476 struct ehci_xfer *exfer = EXFER(xfer); 1477 1478 return (usb_map_mbuf_dma(&sc->sc_dmatag, &exfer->dmabuf, chain)); 1479 } 1480 1481 Static void 1482 ehci_unmapm(usbd_xfer_handle xfer) 1483 { 1484 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1485 struct ehci_xfer *exfer = EXFER(xfer); 1486 1487 usb_unmap_dma(&sc->sc_dmatag, &exfer->dmabuf); 1488 } 1489 1490 usbd_xfer_handle 1491 ehci_allocx(struct usbd_bus *bus, usbd_pipe_handle pipe, 1492 enum usbd_waitflg waitflg) 1493 { 1494 struct ehci_softc *sc = (struct ehci_softc *)bus; 1495 usbd_xfer_handle xfer; 1496 1497 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1498 if (xfer != NULL) { 1499 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1500 #ifdef DIAGNOSTIC 1501 if (xfer->busy_free != XFER_FREE) { 1502 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1503 xfer->busy_free); 1504 } 1505 #endif 1506 } else { 1507 xfer = malloc(sizeof(struct ehci_xfer), M_USB, 1508 waitflg == U_WAITOK ? M_WAITOK : M_NOWAIT); 1509 } 1510 if (xfer != NULL) { 1511 memset(xfer, 0, sizeof(struct ehci_xfer)); 1512 usb_init_task(&EXFER(xfer)->abort_task, ehci_timeout_task, 1513 xfer); 1514 EXFER(xfer)->ehci_xfer_flags = 0; 1515 EXFER(xfer)->rsvd_tds = 0; 1516 #ifdef DIAGNOSTIC 1517 EXFER(xfer)->isdone = 1; 1518 xfer->busy_free = XFER_BUSY; 1519 #endif 1520 } 1521 return (xfer); 1522 } 1523 1524 void 1525 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1526 { 1527 struct ehci_softc *sc = (struct ehci_softc *)bus; 1528 1529 #ifdef DIAGNOSTIC 1530 if (xfer->busy_free != XFER_BUSY) { 1531 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1532 xfer->busy_free); 1533 } 1534 xfer->busy_free = XFER_FREE; 1535 if (!EXFER(xfer)->isdone) { 1536 printf("ehci_freex: !isdone\n"); 1537 } 1538 #endif 1539 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1540 } 1541 1542 Static void 1543 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1544 { 1545 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1546 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 1547 1548 EHCI_SQH_SYNC(sc, epipe->sqh, 1549 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1550 1551 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1552 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1553 #ifdef USB_DEBUG 1554 if (ehcidebug) 1555 usbd_dump_pipe(pipe); 1556 #endif 1557 USB_KASSERT2((epipe->sqh->qh.qh_qtd.qtd_status & 1558 htole32(EHCI_QTD_ACTIVE)) == 0, 1559 ("ehci_device_clear_toggle: queue active")); 1560 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK); 1561 EHCI_SQH_SYNC(sc, epipe->sqh, 1562 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1563 } 1564 1565 Static void 1566 ehci_noop(usbd_pipe_handle pipe) 1567 { 1568 } 1569 1570 #ifdef EHCI_DEBUG 1571 void 1572 ehci_dump_regs(ehci_softc_t *sc) 1573 { 1574 int i; 1575 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1576 EOREAD4(sc, EHCI_USBCMD), 1577 EOREAD4(sc, EHCI_USBSTS), 1578 EOREAD4(sc, EHCI_USBINTR)); 1579 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1580 EOREAD4(sc, EHCI_FRINDEX), 1581 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1582 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1583 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1584 for (i = 1; i <= sc->sc_noport; i++) 1585 printf("port %d status=0x%08x\n", i, 1586 EOREAD4(sc, EHCI_PORTSC(i))); 1587 } 1588 1589 /* 1590 * Unused function - this is meant to be called from a kernel 1591 * debugger. 1592 */ 1593 void 1594 ehci_dump() 1595 { 1596 ehci_dump_regs(theehci); 1597 } 1598 1599 void 1600 ehci_dump_link(ehci_link_t link, int type) 1601 { 1602 link = le32toh(link); 1603 printf("0x%08x", link); 1604 if (link & EHCI_LINK_TERMINATE) 1605 printf("<T>"); 1606 else { 1607 printf("<"); 1608 if (type) { 1609 switch (EHCI_LINK_TYPE(link)) { 1610 case EHCI_LINK_ITD: printf("ITD"); break; 1611 case EHCI_LINK_QH: printf("QH"); break; 1612 case EHCI_LINK_SITD: printf("SITD"); break; 1613 case EHCI_LINK_FSTN: printf("FSTN"); break; 1614 } 1615 } 1616 printf(">"); 1617 } 1618 } 1619 1620 void 1621 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1622 { 1623 int i; 1624 u_int32_t stop; 1625 1626 stop = 0; 1627 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1628 ehci_dump_sqtd(sqtd); 1629 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1630 } 1631 if (sqtd) 1632 printf("dump aborted, too many TDs\n"); 1633 } 1634 1635 void 1636 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1637 { 1638 printf("QTD(%p) at 0x%08x:\n", sqtd, EHCI_SQTD_DMAADDR(sqtd)); 1639 ehci_dump_qtd(&sqtd->qtd); 1640 } 1641 1642 void 1643 ehci_dump_qtd(ehci_qtd_t *qtd) 1644 { 1645 u_int32_t s; 1646 char sbuf[128]; 1647 1648 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1649 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1650 printf("\n"); 1651 s = le32toh(qtd->qtd_status); 1652 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1653 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1654 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1655 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1656 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1657 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1658 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1659 EHCI_QTD_GET_PID(s), sbuf); 1660 for (s = 0; s < 5; s++) 1661 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1662 } 1663 1664 void 1665 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1666 { 1667 ehci_qh_t *qh = &sqh->qh; 1668 u_int32_t endp, endphub; 1669 1670 printf("QH(%p) at 0x%08x:\n", sqh, EHCI_SQH_DMAADDR(sqh)); 1671 printf(" sqtd=%p inactivesqtd=%p\n", sqh->sqtd, sqh->inactivesqtd); 1672 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1673 endp = le32toh(qh->qh_endp); 1674 printf(" endp=0x%08x\n", endp); 1675 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1676 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1677 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1678 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1679 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1680 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1681 EHCI_QH_GET_NRL(endp)); 1682 endphub = le32toh(qh->qh_endphub); 1683 printf(" endphub=0x%08x\n", endphub); 1684 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1685 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1686 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1687 EHCI_QH_GET_MULT(endphub)); 1688 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1689 printf("Overlay qTD:\n"); 1690 ehci_dump_qtd(&qh->qh_qtd); 1691 } 1692 1693 #ifdef DIAGNOSTIC 1694 Static void 1695 ehci_dump_exfer(struct ehci_xfer *ex) 1696 { 1697 printf("ehci_dump_exfer: ex=%p\n", ex); 1698 } 1699 #endif 1700 #endif 1701 1702 usbd_status 1703 ehci_open(usbd_pipe_handle pipe) 1704 { 1705 usbd_device_handle dev = pipe->device; 1706 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 1707 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1708 u_int8_t addr = dev->address; 1709 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1710 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1711 ehci_soft_qh_t *sqh; 1712 usbd_status err; 1713 int s; 1714 int ival, speed, naks; 1715 int hshubaddr, hshubport; 1716 1717 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1718 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1719 1720 if (dev->myhsport) { 1721 hshubaddr = dev->myhsport->parent->address; 1722 hshubport = dev->myhsport->portno; 1723 } else { 1724 hshubaddr = 0; 1725 hshubport = 0; 1726 } 1727 1728 if (sc->sc_dying) 1729 return (USBD_IOERROR); 1730 1731 if (addr == sc->sc_addr) { 1732 switch (ed->bEndpointAddress) { 1733 case USB_CONTROL_ENDPOINT: 1734 pipe->methods = &ehci_root_ctrl_methods; 1735 break; 1736 case UE_DIR_IN | EHCI_INTR_ENDPT: 1737 pipe->methods = &ehci_root_intr_methods; 1738 break; 1739 default: 1740 return (USBD_INVAL); 1741 } 1742 return (USBD_NORMAL_COMPLETION); 1743 } 1744 1745 /* XXX All this stuff is only valid for async. */ 1746 switch (dev->speed) { 1747 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1748 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1749 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1750 default: panic("ehci_open: bad device speed %d", dev->speed); 1751 } 1752 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1753 printf("%s: *** WARNING: opening low/full speed isoc device, " 1754 "this does not work yet.\n", 1755 USBDEVNAME(sc->sc_bus.bdev)); 1756 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1757 hshubaddr, hshubport)); 1758 return USBD_INVAL; 1759 } 1760 1761 naks = 8; /* XXX */ 1762 sqh = ehci_alloc_sqh(sc); 1763 if (sqh == NULL) 1764 return (USBD_NOMEM); 1765 /* qh_link filled when the QH is added */ 1766 sqh->qh.qh_endp = htole32( 1767 EHCI_QH_SET_ADDR(addr) | 1768 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1769 EHCI_QH_SET_EPS(speed) | 1770 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) | 1771 EHCI_QH_SET_MPL(UE_MAXPKTSZ(ed)) | 1772 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1773 EHCI_QH_CTL : 0) | 1774 EHCI_QH_SET_NRL(naks) 1775 ); 1776 sqh->qh.qh_endphub = htole32( 1777 EHCI_QH_SET_MULT(1) | 1778 EHCI_QH_SET_HUBA(hshubaddr) | 1779 EHCI_QH_SET_PORT(hshubport) | 1780 EHCI_QH_SET_CMASK(0x1c) | 1781 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0) 1782 ); 1783 sqh->qh.qh_curqtd = EHCI_NULL; 1784 /* The overlay qTD was already set up by ehci_alloc_sqh(). */ 1785 sqh->qh.qh_qtd.qtd_status = 1786 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle)); 1787 1788 epipe->sqh = sqh; 1789 1790 switch (xfertype) { 1791 case UE_CONTROL: 1792 err = usb_allocmem(&sc->sc_dmatag, sizeof(usb_device_request_t), 1793 0, &epipe->u.ctl.reqdma); 1794 #ifdef EHCI_DEBUG 1795 if (err) 1796 printf("ehci_open: usb_allocmem()=%d\n", err); 1797 #endif 1798 if (err) 1799 goto bad; 1800 pipe->methods = &ehci_device_ctrl_methods; 1801 s = splusb(); 1802 ehci_add_qh(sc, sqh, sc->sc_async_head); 1803 splx(s); 1804 break; 1805 case UE_BULK: 1806 pipe->methods = &ehci_device_bulk_methods; 1807 s = splusb(); 1808 ehci_add_qh(sc, sqh, sc->sc_async_head); 1809 splx(s); 1810 break; 1811 case UE_INTERRUPT: 1812 pipe->methods = &ehci_device_intr_methods; 1813 ival = pipe->interval; 1814 if (ival == USBD_DEFAULT_INTERVAL) { 1815 if (speed == EHCI_QH_SPEED_HIGH) { 1816 if (ed->bInterval > 16) { 1817 /* 1818 * illegal with high-speed, but there 1819 * were documentation bugs in the spec, 1820 * so be generous 1821 */ 1822 ival = 256; 1823 } else 1824 ival = (1 << (ed->bInterval - 1)) / 8; 1825 } else 1826 ival = ed->bInterval; 1827 } 1828 err = ehci_device_setintr(sc, sqh, ival); 1829 if (err) 1830 goto bad; 1831 break; 1832 case UE_ISOCHRONOUS: 1833 pipe->methods = &ehci_device_isoc_methods; 1834 /* FALLTHROUGH */ 1835 default: 1836 err = USBD_INVAL; 1837 goto bad; 1838 } 1839 return (USBD_NORMAL_COMPLETION); 1840 1841 bad: 1842 ehci_free_sqh(sc, sqh); 1843 return (err); 1844 } 1845 1846 /* 1847 * Add an ED to the schedule. Called at splusb(). 1848 * If in the async schedule, it will always have a next. 1849 * If in the intr schedule it may not. 1850 */ 1851 void 1852 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1853 { 1854 SPLUSBCHECK; 1855 1856 sqh->next = head->next; 1857 sqh->prev = head; 1858 sqh->qh.qh_link = head->qh.qh_link; 1859 EHCI_SQH_SYNC(sc, sqh, 1860 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1861 head->next = sqh; 1862 if (sqh->next) 1863 sqh->next->prev = sqh; 1864 head->qh.qh_link = htole32(EHCI_SQH_DMAADDR(sqh) | EHCI_LINK_QH); 1865 EHCI_SQH_SYNC(sc, head, 1866 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1867 1868 #ifdef EHCI_DEBUG 1869 if (ehcidebug > 5) { 1870 printf("ehci_add_qh:\n"); 1871 ehci_dump_sqh(sqh); 1872 } 1873 #endif 1874 } 1875 1876 /* 1877 * Remove an ED from the schedule. Called at splusb(). 1878 * Will always have a 'next' if it's in the async list as it's circular. 1879 */ 1880 void 1881 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1882 { 1883 SPLUSBCHECK; 1884 /* XXX */ 1885 sqh->prev->qh.qh_link = sqh->qh.qh_link; 1886 EHCI_SQH_SYNC(sc, sqh->prev, 1887 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1888 sqh->prev->next = sqh->next; 1889 if (sqh->next) 1890 sqh->next->prev = sqh->prev; 1891 ehci_sync_hc(sc); 1892 } 1893 1894 /* Restart a QH following the addition of a qTD. */ 1895 void 1896 ehci_activate_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1897 { 1898 ehci_physaddr_t qtddma; 1899 1900 EHCI_SQTD_SYNC(sc, sqtd, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1901 1902 USB_KASSERT2((sqtd->qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) == 0, 1903 ("ehci_activate_qh: already active")); 1904 1905 /* 1906 * When a QH is idle, the overlay qTD should be marked as not 1907 * halted and not active. This causes the host controller to 1908 * retrieve the real qTD on each pass (rather than just examinig 1909 * the overlay), so it will notice when we activate the qTD. 1910 */ 1911 if (sqtd == sqh->sqtd) { 1912 /* Check that the hardware is in the state we expect. */ 1913 qtddma = EHCI_SQTD_DMAADDR(sqtd); 1914 if (EHCI_LINK_ADDR(le32toh(sqh->qh.qh_qtd.qtd_next)) != 1915 qtddma) { 1916 #ifdef EHCI_DEBUG 1917 printf("ehci_activate_qh: unexpected next ptr\n"); 1918 ehci_dump_sqh(sqh); 1919 ehci_dump_sqtds(sqh->sqtd); 1920 #endif 1921 sqh->qh.qh_qtd.qtd_next = htole32(qtddma); 1922 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1923 } 1924 /* Ensure the flags are correct. */ 1925 sqh->qh.qh_qtd.qtd_status &= htole32(EHCI_QTD_PINGSTATE | 1926 EHCI_QTD_TOGGLE_MASK); 1927 EHCI_SQH_SYNC(sc, sqh, 1928 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1929 } 1930 1931 /* Now activate the qTD. */ 1932 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_ACTIVE); 1933 EHCI_SQTD_SYNC(sc, sqtd, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1934 } 1935 1936 /* 1937 * Ensure that the HC has released all references to the QH. We do this 1938 * by asking for a Async Advance Doorbell interrupt and then we wait for 1939 * the interrupt. 1940 * To make this easier we first obtain exclusive use of the doorbell. 1941 */ 1942 void 1943 ehci_sync_hc(ehci_softc_t *sc) 1944 { 1945 int s, error; 1946 1947 if (sc->sc_dying) { 1948 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1949 return; 1950 } 1951 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1952 /* get doorbell */ 1953 usb_lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE, NULL); 1954 s = splhardusb(); 1955 /* ask for doorbell */ 1956 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1957 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1958 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1959 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1960 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1961 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1962 splx(s); 1963 /* release doorbell */ 1964 usb_lockmgr(&sc->sc_doorbell_lock, LK_RELEASE, NULL); 1965 #ifdef DIAGNOSTIC 1966 if (error) 1967 printf("ehci_sync_hc: tsleep() = %d\n", error); 1968 #endif 1969 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1970 } 1971 1972 /***********/ 1973 1974 /* 1975 * Data structures and routines to emulate the root hub. 1976 */ 1977 Static usb_device_descriptor_t ehci_devd = { 1978 USB_DEVICE_DESCRIPTOR_SIZE, 1979 UDESC_DEVICE, /* type */ 1980 {0x00, 0x02}, /* USB version */ 1981 UDCLASS_HUB, /* class */ 1982 UDSUBCLASS_HUB, /* subclass */ 1983 UDPROTO_HSHUBSTT, /* protocol */ 1984 64, /* max packet */ 1985 {0},{0},{0x00,0x01}, /* device id */ 1986 1,2,0, /* string indicies */ 1987 1 /* # of configurations */ 1988 }; 1989 1990 Static const usb_device_qualifier_t ehci_odevd = { 1991 USB_DEVICE_DESCRIPTOR_SIZE, 1992 UDESC_DEVICE_QUALIFIER, /* type */ 1993 {0x00, 0x02}, /* USB version */ 1994 UDCLASS_HUB, /* class */ 1995 UDSUBCLASS_HUB, /* subclass */ 1996 UDPROTO_FSHUB, /* protocol */ 1997 64, /* max packet */ 1998 1, /* # of configurations */ 1999 0 2000 }; 2001 2002 Static const usb_config_descriptor_t ehci_confd = { 2003 USB_CONFIG_DESCRIPTOR_SIZE, 2004 UDESC_CONFIG, 2005 {USB_CONFIG_DESCRIPTOR_SIZE + 2006 USB_INTERFACE_DESCRIPTOR_SIZE + 2007 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2008 1, 2009 1, 2010 0, 2011 UC_ATTR_MBO | UC_SELF_POWERED, 2012 0 /* max power */ 2013 }; 2014 2015 Static const usb_interface_descriptor_t ehci_ifcd = { 2016 USB_INTERFACE_DESCRIPTOR_SIZE, 2017 UDESC_INTERFACE, 2018 0, 2019 0, 2020 1, 2021 UICLASS_HUB, 2022 UISUBCLASS_HUB, 2023 UIPROTO_HSHUBSTT, 2024 0 2025 }; 2026 2027 Static const usb_endpoint_descriptor_t ehci_endpd = { 2028 USB_ENDPOINT_DESCRIPTOR_SIZE, 2029 UDESC_ENDPOINT, 2030 UE_DIR_IN | EHCI_INTR_ENDPT, 2031 UE_INTERRUPT, 2032 {8, 0}, /* max packet */ 2033 12 2034 }; 2035 2036 Static const usb_hub_descriptor_t ehci_hubd = { 2037 USB_HUB_DESCRIPTOR_SIZE, 2038 UDESC_HUB, 2039 0, 2040 {0,0}, 2041 0, 2042 0, 2043 {""}, 2044 {""}, 2045 }; 2046 2047 Static int 2048 ehci_str(usb_string_descriptor_t *p, int l, const char *s) 2049 { 2050 int i; 2051 2052 if (l == 0) 2053 return (0); 2054 p->bLength = 2 * strlen(s) + 2; 2055 if (l == 1) 2056 return (1); 2057 p->bDescriptorType = UDESC_STRING; 2058 l -= 2; 2059 for (i = 0; s[i] && l > 1; i++, l -= 2) 2060 USETW2(p->bString[i], 0, s[i]); 2061 return (2*i+2); 2062 } 2063 2064 /* 2065 * Simulate a hardware hub by handling all the necessary requests. 2066 */ 2067 Static usbd_status 2068 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2069 { 2070 usbd_status err; 2071 2072 /* Insert last in queue. */ 2073 err = usb_insert_transfer(xfer); 2074 if (err) 2075 return (err); 2076 2077 /* Pipe isn't running, start first */ 2078 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2079 } 2080 2081 Static usbd_status 2082 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2083 { 2084 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2085 usb_device_request_t *req; 2086 void *buf = NULL; 2087 int port, i; 2088 int s, len, value, index, l, totlen = 0; 2089 usb_port_status_t ps; 2090 usb_hub_descriptor_t hubd; 2091 usbd_status err; 2092 u_int32_t v; 2093 2094 if (sc->sc_dying) 2095 return (USBD_IOERROR); 2096 2097 #ifdef DIAGNOSTIC 2098 if (!(xfer->rqflags & URQ_REQUEST)) 2099 /* XXX panic */ 2100 return (USBD_INVAL); 2101 #endif 2102 req = &xfer->request; 2103 2104 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2105 req->bmRequestType, req->bRequest)); 2106 2107 len = UGETW(req->wLength); 2108 value = UGETW(req->wValue); 2109 index = UGETW(req->wIndex); 2110 2111 if (len != 0) { 2112 /* mbuf transfer is not supported */ 2113 if (xfer->rqflags & URQ_DEV_MAP_MBUF) 2114 return (USBD_INVAL); 2115 buf = xfer->hcbuffer; 2116 } 2117 2118 #define C(x,y) ((x) | ((y) << 8)) 2119 switch(C(req->bRequest, req->bmRequestType)) { 2120 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2121 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2122 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2123 /* 2124 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2125 * for the integrated root hub. 2126 */ 2127 break; 2128 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2129 if (len > 0) { 2130 *(u_int8_t *)buf = sc->sc_conf; 2131 totlen = 1; 2132 } 2133 break; 2134 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2135 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2136 if (len == 0) 2137 break; 2138 switch(value >> 8) { 2139 case UDESC_DEVICE: 2140 if ((value & 0xff) != 0) { 2141 err = USBD_IOERROR; 2142 goto ret; 2143 } 2144 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2145 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2146 memcpy(buf, &ehci_devd, l); 2147 break; 2148 /* 2149 * We can't really operate at another speed, but the spec says 2150 * we need this descriptor. 2151 */ 2152 case UDESC_DEVICE_QUALIFIER: 2153 if ((value & 0xff) != 0) { 2154 err = USBD_IOERROR; 2155 goto ret; 2156 } 2157 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2158 memcpy(buf, &ehci_odevd, l); 2159 break; 2160 /* 2161 * We can't really operate at another speed, but the spec says 2162 * we need this descriptor. 2163 */ 2164 case UDESC_OTHER_SPEED_CONFIGURATION: 2165 case UDESC_CONFIG: 2166 if ((value & 0xff) != 0) { 2167 err = USBD_IOERROR; 2168 goto ret; 2169 } 2170 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2171 memcpy(buf, &ehci_confd, l); 2172 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2173 value >> 8; 2174 buf = (char *)buf + l; 2175 len -= l; 2176 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2177 totlen += l; 2178 memcpy(buf, &ehci_ifcd, l); 2179 buf = (char *)buf + l; 2180 len -= l; 2181 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2182 totlen += l; 2183 memcpy(buf, &ehci_endpd, l); 2184 break; 2185 case UDESC_STRING: 2186 *(u_int8_t *)buf = 0; 2187 totlen = 1; 2188 switch (value & 0xff) { 2189 case 0: /* Language table */ 2190 if (len > 0) 2191 *(u_int8_t *)buf = 4; 2192 if (len >= 4) { 2193 USETW(((usb_string_descriptor_t *)buf)->bString[0], 0x0409); 2194 totlen = 4; 2195 } 2196 break; 2197 case 1: /* Vendor */ 2198 totlen = ehci_str(buf, len, sc->sc_vendor); 2199 break; 2200 case 2: /* Product */ 2201 totlen = ehci_str(buf, len, "EHCI root hub"); 2202 break; 2203 } 2204 break; 2205 default: 2206 err = USBD_IOERROR; 2207 goto ret; 2208 } 2209 break; 2210 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2211 if (len > 0) { 2212 *(u_int8_t *)buf = 0; 2213 totlen = 1; 2214 } 2215 break; 2216 case C(UR_GET_STATUS, UT_READ_DEVICE): 2217 if (len > 1) { 2218 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2219 totlen = 2; 2220 } 2221 break; 2222 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2223 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2224 if (len > 1) { 2225 USETW(((usb_status_t *)buf)->wStatus, 0); 2226 totlen = 2; 2227 } 2228 break; 2229 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2230 if (value >= USB_MAX_DEVICES) { 2231 err = USBD_IOERROR; 2232 goto ret; 2233 } 2234 sc->sc_addr = value; 2235 break; 2236 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2237 if (value != 0 && value != 1) { 2238 err = USBD_IOERROR; 2239 goto ret; 2240 } 2241 sc->sc_conf = value; 2242 break; 2243 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2244 break; 2245 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2246 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2247 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2248 err = USBD_IOERROR; 2249 goto ret; 2250 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2251 break; 2252 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2253 break; 2254 /* Hub requests */ 2255 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2256 break; 2257 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2258 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2259 "port=%d feature=%d\n", 2260 index, value)); 2261 if (index < 1 || index > sc->sc_noport) { 2262 err = USBD_IOERROR; 2263 goto ret; 2264 } 2265 port = EHCI_PORTSC(index); 2266 v = EOREAD4(sc, port); 2267 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2268 v &= ~EHCI_PS_CLEAR; 2269 switch(value) { 2270 case UHF_PORT_ENABLE: 2271 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2272 break; 2273 case UHF_PORT_SUSPEND: 2274 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 2275 break; 2276 case UHF_PORT_POWER: 2277 if (sc->sc_hasppc) 2278 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2279 break; 2280 case UHF_PORT_TEST: 2281 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2282 "%d\n", index)); 2283 break; 2284 case UHF_PORT_INDICATOR: 2285 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2286 "%d\n", index)); 2287 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2288 break; 2289 case UHF_C_PORT_CONNECTION: 2290 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2291 break; 2292 case UHF_C_PORT_ENABLE: 2293 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2294 break; 2295 case UHF_C_PORT_SUSPEND: 2296 /* how? */ 2297 break; 2298 case UHF_C_PORT_OVER_CURRENT: 2299 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2300 break; 2301 case UHF_C_PORT_RESET: 2302 sc->sc_isreset[index] = 0; 2303 break; 2304 default: 2305 err = USBD_IOERROR; 2306 goto ret; 2307 } 2308 #if 0 2309 switch(value) { 2310 case UHF_C_PORT_CONNECTION: 2311 case UHF_C_PORT_ENABLE: 2312 case UHF_C_PORT_SUSPEND: 2313 case UHF_C_PORT_OVER_CURRENT: 2314 case UHF_C_PORT_RESET: 2315 default: 2316 break; 2317 } 2318 #endif 2319 break; 2320 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2321 if (len == 0) 2322 break; 2323 if ((value & 0xff) != 0) { 2324 err = USBD_IOERROR; 2325 goto ret; 2326 } 2327 hubd = ehci_hubd; 2328 hubd.bNbrPorts = sc->sc_noport; 2329 v = EOREAD4(sc, EHCI_HCSPARAMS); 2330 USETW(hubd.wHubCharacteristics, 2331 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2332 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2333 ? UHD_PORT_IND : 0); 2334 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2335 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2336 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2337 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2338 l = min(len, hubd.bDescLength); 2339 totlen = l; 2340 memcpy(buf, &hubd, l); 2341 break; 2342 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2343 if (len != 4) { 2344 err = USBD_IOERROR; 2345 goto ret; 2346 } 2347 memset(buf, 0, len); /* ? XXX */ 2348 totlen = len; 2349 break; 2350 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2351 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2352 index)); 2353 if (index < 1 || index > sc->sc_noport) { 2354 err = USBD_IOERROR; 2355 goto ret; 2356 } 2357 if (len != 4) { 2358 err = USBD_IOERROR; 2359 goto ret; 2360 } 2361 v = EOREAD4(sc, EHCI_PORTSC(index)); 2362 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2363 v)); 2364 i = UPS_HIGH_SPEED; 2365 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2366 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2367 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2368 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2369 if (v & EHCI_PS_PR) i |= UPS_RESET; 2370 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2371 USETW(ps.wPortStatus, i); 2372 i = 0; 2373 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2374 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2375 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2376 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2377 USETW(ps.wPortChange, i); 2378 l = min(len, sizeof ps); 2379 memcpy(buf, &ps, l); 2380 totlen = l; 2381 break; 2382 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2383 err = USBD_IOERROR; 2384 goto ret; 2385 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2386 break; 2387 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2388 if (index < 1 || index > sc->sc_noport) { 2389 err = USBD_IOERROR; 2390 goto ret; 2391 } 2392 port = EHCI_PORTSC(index); 2393 v = EOREAD4(sc, port); 2394 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2395 v &= ~EHCI_PS_CLEAR; 2396 switch(value) { 2397 case UHF_PORT_ENABLE: 2398 EOWRITE4(sc, port, v | EHCI_PS_PE); 2399 break; 2400 case UHF_PORT_SUSPEND: 2401 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2402 break; 2403 case UHF_PORT_RESET: 2404 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2405 index)); 2406 if (EHCI_PS_IS_LOWSPEED(v)) { 2407 /* Low speed device, give up ownership. */ 2408 ehci_disown(sc, index, 1); 2409 break; 2410 } 2411 /* Start reset sequence. */ 2412 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2413 EOWRITE4(sc, port, v | EHCI_PS_PR); 2414 /* Wait for reset to complete. */ 2415 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2416 if (sc->sc_dying) { 2417 err = USBD_IOERROR; 2418 goto ret; 2419 } 2420 /* Terminate reset sequence. */ 2421 EOWRITE4(sc, port, v); 2422 /* Wait for HC to complete reset. */ 2423 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2424 if (sc->sc_dying) { 2425 err = USBD_IOERROR; 2426 goto ret; 2427 } 2428 v = EOREAD4(sc, port); 2429 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2430 if (v & EHCI_PS_PR) { 2431 printf("%s: port reset timeout\n", 2432 USBDEVNAME(sc->sc_bus.bdev)); 2433 return (USBD_TIMEOUT); 2434 } 2435 if (!(v & EHCI_PS_PE)) { 2436 /* Not a high speed device, give up ownership.*/ 2437 ehci_disown(sc, index, 0); 2438 break; 2439 } 2440 sc->sc_isreset[index] = 1; 2441 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2442 index, v)); 2443 break; 2444 case UHF_PORT_POWER: 2445 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2446 "%d (has PPC = %d)\n", index, 2447 sc->sc_hasppc)); 2448 if (sc->sc_hasppc) 2449 EOWRITE4(sc, port, v | EHCI_PS_PP); 2450 break; 2451 case UHF_PORT_TEST: 2452 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2453 "%d\n", index)); 2454 break; 2455 case UHF_PORT_INDICATOR: 2456 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2457 "%d\n", index)); 2458 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2459 break; 2460 default: 2461 err = USBD_IOERROR; 2462 goto ret; 2463 } 2464 break; 2465 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2466 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2467 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2468 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2469 break; 2470 default: 2471 err = USBD_IOERROR; 2472 goto ret; 2473 } 2474 xfer->actlen = totlen; 2475 err = USBD_NORMAL_COMPLETION; 2476 ret: 2477 xfer->status = err; 2478 s = splusb(); 2479 usb_transfer_complete(xfer); 2480 splx(s); 2481 return (USBD_IN_PROGRESS); 2482 } 2483 2484 void 2485 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2486 { 2487 int port; 2488 u_int32_t v; 2489 2490 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2491 #ifdef DIAGNOSTIC 2492 if (sc->sc_npcomp != 0) { 2493 int i = (index-1) / sc->sc_npcomp; 2494 if (i >= sc->sc_ncomp) 2495 printf("%s: strange port\n", 2496 USBDEVNAME(sc->sc_bus.bdev)); 2497 else 2498 printf("%s: handing over %s speed device on " 2499 "port %d to %s\n", 2500 USBDEVNAME(sc->sc_bus.bdev), 2501 lowspeed ? "low" : "full", 2502 index, USBDEVNAME(sc->sc_comps[i]->bdev)); 2503 } else { 2504 printf("%s: npcomp == 0\n", USBDEVNAME(sc->sc_bus.bdev)); 2505 } 2506 #endif 2507 port = EHCI_PORTSC(index); 2508 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2509 EOWRITE4(sc, port, v | EHCI_PS_PO); 2510 } 2511 2512 /* Abort a root control request. */ 2513 Static void 2514 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2515 { 2516 /* Nothing to do, all transfers are synchronous. */ 2517 } 2518 2519 /* Close the root pipe. */ 2520 Static void 2521 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2522 { 2523 DPRINTF(("ehci_root_ctrl_close\n")); 2524 /* Nothing to do. */ 2525 } 2526 2527 void 2528 ehci_root_intr_done(usbd_xfer_handle xfer) 2529 { 2530 } 2531 2532 Static usbd_status 2533 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2534 { 2535 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2536 usbd_status err; 2537 2538 /* Insert last in queue. */ 2539 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 2540 &EXFER(xfer)->dmabuf); 2541 if (err) 2542 return (err); 2543 2544 /* Pipe isn't running, start first */ 2545 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2546 } 2547 2548 Static usbd_status 2549 ehci_root_intr_start(usbd_xfer_handle xfer) 2550 { 2551 usbd_pipe_handle pipe = xfer->pipe; 2552 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2553 2554 if (sc->sc_dying) 2555 return (USBD_IOERROR); 2556 2557 if (xfer->rqflags & URQ_DEV_MAP_MBUF) 2558 return (USBD_INVAL); /* mbuf transfer is not supported */ 2559 2560 sc->sc_intrxfer = xfer; 2561 2562 return (USBD_IN_PROGRESS); 2563 } 2564 2565 /* Abort a root interrupt request. */ 2566 Static void 2567 ehci_root_intr_abort(usbd_xfer_handle xfer) 2568 { 2569 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2570 int s; 2571 2572 if (xfer->pipe->intrxfer == xfer) { 2573 DPRINTF(("ehci_root_intr_abort: remove\n")); 2574 xfer->pipe->intrxfer = NULL; 2575 } 2576 xfer->status = USBD_CANCELLED; 2577 s = splusb(); 2578 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 2579 splx(s); 2580 } 2581 2582 /* Close the root pipe. */ 2583 Static void 2584 ehci_root_intr_close(usbd_pipe_handle pipe) 2585 { 2586 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2587 2588 DPRINTF(("ehci_root_intr_close\n")); 2589 2590 sc->sc_intrxfer = NULL; 2591 } 2592 2593 void 2594 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2595 { 2596 } 2597 2598 /************************/ 2599 2600 ehci_soft_qh_t * 2601 ehci_alloc_sqh(ehci_softc_t *sc) 2602 { 2603 ehci_soft_qh_t *sqh; 2604 ehci_soft_qtd_t *sqtd; 2605 usbd_status err; 2606 int i, offs; 2607 usb_dma_t dma; 2608 struct ehci_mem_desc *em; 2609 2610 if (sc->sc_freeqhs == NULL) { 2611 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2612 err = usb_allocmem(&sc->sc_dmatag, 2613 EHCI_SQH_SIZE*EHCI_SQH_CHUNK + sizeof(struct ehci_mem_desc), 2614 EHCI_PAGE_SIZE, &dma); 2615 #ifdef EHCI_DEBUG 2616 if (err) 2617 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2618 #endif 2619 if (err) 2620 return (NULL); 2621 em = KERNADDR(&dma, EHCI_SQH_SIZE * EHCI_SQH_CHUNK); 2622 em->em_top = KERNADDR(&dma, 0); 2623 em->em_topdma = DMAADDR(&dma, 0); 2624 em->em_dma = dma; 2625 SIMPLEQ_INSERT_HEAD(&sc->sc_sqh_chunks, em, em_next); 2626 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2627 offs = i * EHCI_SQH_SIZE; 2628 sqh = KERNADDR(&dma, offs); 2629 sqh->eh_mdesc = em; 2630 sqh->next = sc->sc_freeqhs; 2631 sc->sc_freeqhs = sqh; 2632 } 2633 } 2634 /* Allocate the initial inactive sqtd. */ 2635 sqtd = ehci_alloc_sqtd_norsv(sc); 2636 if (sqtd == NULL) 2637 return (NULL); 2638 sqtd->qtd.qtd_status = htole32(0); 2639 sqtd->qtd.qtd_next = EHCI_NULL; 2640 sqtd->qtd.qtd_altnext = EHCI_NULL; 2641 2642 sqh = sc->sc_freeqhs; 2643 sc->sc_freeqhs = sqh->next; 2644 2645 /* The overlay QTD should begin zeroed. */ 2646 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(sqtd)); 2647 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2648 sqh->qh.qh_qtd.qtd_status = 0; 2649 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) { 2650 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2651 sqh->qh.qh_qtd.qtd_buffer_hi[i] = 0; 2652 } 2653 sqh->next = NULL; 2654 sqh->prev = NULL; 2655 sqh->sqtd = sqtd; 2656 sqh->inactivesqtd = sqtd; 2657 return (sqh); 2658 } 2659 2660 void 2661 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2662 { 2663 ehci_free_sqtd_norsv(sc, sqh->inactivesqtd); 2664 sqh->next = sc->sc_freeqhs; 2665 sc->sc_freeqhs = sqh; 2666 } 2667 2668 Static usbd_status 2669 ehci_grow_sqtd(ehci_softc_t *sc) 2670 { 2671 usb_dma_t dma; 2672 struct ehci_mem_desc *em; 2673 ehci_soft_qtd_t *sqtd; 2674 usbd_status err; 2675 int i, s, offs; 2676 2677 DPRINTFN(2, ("ehci_grow_sqtd: allocating chunk\n")); 2678 err = usb_allocmem(&sc->sc_dmatag, 2679 EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK + sizeof(struct ehci_mem_desc), 2680 EHCI_PAGE_SIZE, &dma); 2681 #ifdef EHCI_DEBUG 2682 if (err) 2683 printf("ehci_grow_sqtd: usb_allocmem()=%d\n", err); 2684 #endif 2685 if (err) 2686 return (err); 2687 em = KERNADDR(&dma, EHCI_SQTD_SIZE * EHCI_SQTD_CHUNK); 2688 em->em_top = KERNADDR(&dma, 0); 2689 em->em_topdma = DMAADDR(&dma, 0); 2690 em->em_dma = dma; 2691 s = splusb(); 2692 SIMPLEQ_INSERT_HEAD(&sc->sc_sqtd_chunks, em, em_next); 2693 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2694 offs = i * EHCI_SQTD_SIZE; 2695 sqtd = KERNADDR(&dma, offs); 2696 sqtd->et_mdesc = em; 2697 sqtd->nextqtd = sc->sc_freeqtds; 2698 sc->sc_freeqtds = sqtd; 2699 sc->sc_nfreeqtds++; 2700 } 2701 splx(s); 2702 2703 return (USBD_NORMAL_COMPLETION); 2704 } 2705 2706 ehci_soft_qtd_t * 2707 ehci_alloc_sqtd(ehci_softc_t *sc) 2708 { 2709 ehci_soft_qtd_t *sqtd; 2710 int i; 2711 int s; 2712 2713 s = splusb(); 2714 2715 #ifdef DIAGNOSTIC 2716 if (sc->sc_freeqtds == NULL) 2717 panic("ehci_alloc_sqtd: %p %d", 2718 sc->sc_freeqtds, sc->sc_nfreeqtds); 2719 #endif 2720 sqtd = sc->sc_freeqtds; 2721 sc->sc_freeqtds = sqtd->nextqtd; 2722 splx(s); 2723 sqtd->qtd.qtd_next = EHCI_NULL; 2724 sqtd->qtd.qtd_altnext = EHCI_NULL; 2725 sqtd->qtd.qtd_status = 0; 2726 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) { 2727 sqtd->qtd.qtd_buffer[i] = 0; 2728 sqtd->qtd.qtd_buffer_hi[i] = 0; 2729 } 2730 sqtd->nextqtd = NULL; 2731 sqtd->xfer = NULL; 2732 2733 return (sqtd); 2734 } 2735 2736 Static ehci_soft_qtd_t * 2737 ehci_alloc_sqtd_norsv(ehci_softc_t *sc) 2738 { 2739 int s; 2740 2741 s = splusb(); 2742 if (sc->sc_nfreeqtds < 1) 2743 if (ehci_grow_sqtd(sc)) 2744 return (NULL); 2745 sc->sc_nfreeqtds--; 2746 splx(s); 2747 return (ehci_alloc_sqtd(sc)); 2748 } 2749 2750 void 2751 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2752 { 2753 int s; 2754 2755 s = splusb(); 2756 sqtd->nextqtd = sc->sc_freeqtds; 2757 sc->sc_freeqtds = sqtd; 2758 splx(s); 2759 } 2760 2761 Static void 2762 ehci_free_sqtd_norsv(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2763 { 2764 int s; 2765 2766 ehci_free_sqtd(sc, sqtd); 2767 s = splusb(); 2768 sc->sc_nfreeqtds++; 2769 splx(s); 2770 } 2771 2772 usbd_status 2773 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2774 int alen, int rd, usbd_xfer_handle xfer, ehci_soft_qtd_t *start, 2775 ehci_soft_qtd_t *newinactive, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2776 { 2777 usb_endpoint_descriptor_t *endpt; 2778 ehci_soft_qtd_t *next, *cur; 2779 ehci_physaddr_t dataphys, nextphys; 2780 u_int32_t qtdstatus; 2781 int adj, len, curlen, mps, offset, pagelen, seg, segoff; 2782 int i, iscontrol, forceshort; 2783 struct usb_buffer_dma *ub = &EXFER(xfer)->dmabuf; 2784 bus_dma_segment_t *segs = USB_BUFFER_SEGS(ub); 2785 int nsegs = USB_BUFFER_NSEGS(ub); 2786 #if 1 2787 int needaux; 2788 int isread; 2789 union usb_bufptr bufptr; 2790 struct aux_desc ad; 2791 bus_addr_t auxdma; 2792 #endif 2793 2794 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2795 2796 offset = 0; 2797 len = alen; 2798 iscontrol = (epipe->pipe.endpoint->edesc->bmAttributes & UE_XFERTYPE) == 2799 UE_CONTROL; 2800 qtdstatus = EHCI_QTD_ACTIVE | 2801 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2802 EHCI_QTD_SET_CERR(3) 2803 /* IOC set below */ 2804 /* BYTES set below */ 2805 ; 2806 endpt = epipe->pipe.endpoint->edesc; 2807 mps = UE_MAXPKTSZ(endpt); 2808 forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) && 2809 len % mps == 0; 2810 /* 2811 * The control transfer data stage always starts with a toggle of 1. 2812 * For other transfers we let the hardware track the toggle state. 2813 */ 2814 if (iscontrol) 2815 qtdstatus |= EHCI_QTD_SET_TOGGLE(1); 2816 2817 #if 1 2818 /* 2819 * aux memory is possibly required if 2820 * buffer has more than one segments, 2821 * the transfer direction is OUT, 2822 * and 2823 * buffer is an mbuf chain, or 2824 * buffer is not mps aligned 2825 */ 2826 isread = UE_GET_DIR(endpt->bEndpointAddress) == UE_DIR_IN; 2827 needaux = 2828 nsegs > 1 && !isread && 2829 ((xfer->rqflags & URQ_DEV_MAP_MBUF) || 2830 (mps & (mps - 1)) != 0 /* mps is not a power of 2 */ || 2831 (segs[0].ds_addr & (mps - 1)) != 0 /* buffer is unaligned */); 2832 2833 if (needaux) { 2834 usb_bufptr_init(&bufptr, xfer); 2835 if (EXFER(xfer)->aux.aux_naux) { 2836 /* sync previous aux (just in case, probably a no-op) */ 2837 ehci_aux_dma_sync(sc, &EXFER(xfer)->aux, 2838 BUS_DMASYNC_POSTWRITE); 2839 2840 ehci_aux_mem_init(&EXFER(xfer)->aux); 2841 } 2842 } 2843 #endif 2844 2845 if (start != NULL) { 2846 /* 2847 * If we are given a starting qTD, assume it is linked into 2848 * an active QH so be careful not to mark it active. 2849 */ 2850 cur = start; 2851 *sp = cur; 2852 qtdstatus &= ~EHCI_QTD_ACTIVE; 2853 } else { 2854 cur = ehci_alloc_sqtd(sc); 2855 *sp = cur; 2856 if (cur == NULL) 2857 goto nomem; 2858 } 2859 seg = 0; 2860 segoff = 0; 2861 for (;;) { 2862 curlen = 0; 2863 2864 /* The EHCI hardware can handle at most 5 pages. */ 2865 for (i = 0; i < EHCI_QTD_NBUFFERS && curlen < len; i++) { 2866 USB_KASSERT2(seg < nsegs, 2867 ("ehci_alloc_sqtd_chain: overrun")); 2868 dataphys = segs[seg].ds_addr + segoff; 2869 pagelen = segs[seg].ds_len - segoff; 2870 if (pagelen > len - curlen) 2871 pagelen = len - curlen; 2872 if (pagelen > EHCI_PAGE_SIZE - 2873 EHCI_PAGE_OFFSET(dataphys)) 2874 pagelen = EHCI_PAGE_SIZE - 2875 EHCI_PAGE_OFFSET(dataphys); 2876 segoff += pagelen; 2877 if (segoff >= segs[seg].ds_len) { 2878 USB_KASSERT2(segoff == segs[seg].ds_len, 2879 ("ehci_alloc_sqtd_chain: overlap")); 2880 seg++; 2881 segoff = 0; 2882 } 2883 2884 cur->qtd.qtd_buffer[i] = htole32(dataphys); 2885 cur->qtd.qtd_buffer_hi[i] = 0; 2886 curlen += pagelen; 2887 2888 /* 2889 * Must stop if there is any gap before or after 2890 * the page boundary. 2891 */ 2892 if (EHCI_PAGE_OFFSET(dataphys + pagelen) != 0) 2893 break; 2894 if (seg < nsegs && EHCI_PAGE_OFFSET(segoff + 2895 segs[seg].ds_addr) != 0) 2896 break; 2897 } 2898 /* Adjust down to a multiple of mps if not at the end. */ 2899 if (!isread && curlen < len && (adj = curlen % mps) != 0) { 2900 curlen -= adj; 2901 #if 1 2902 if (curlen == 0) { 2903 USB_KASSERT(needaux); 2904 /* need aux -- a packet is not contiguous */ 2905 curlen = len < mps ? len : mps; 2906 auxdma = ehci_aux_dma_alloc(&EXFER(xfer)->aux, 2907 curlen, &ad); 2908 2909 /* prepare aux DMA */ 2910 usb_bufptr_wr(&bufptr, ad.aux_kern, curlen, 2911 xfer->rqflags & URQ_DEV_MAP_MBUF); 2912 cur->qtd.qtd_buffer[i] = htole32(auxdma); 2913 cur->qtd.qtd_buffer_hi[i] = 0; 2914 2915 /* skip handled segments */ 2916 segoff += curlen - adj; 2917 do { 2918 segoff -= segs[seg].ds_len; 2919 seg++; 2920 } while (segoff > segs[seg].ds_len); 2921 2922 } else { 2923 #endif 2924 #if 0 2925 USB_KASSERT2(curlen > 0, 2926 ("ehci_alloc_sqtd_chain: need to copy")); 2927 #endif 2928 segoff -= adj; 2929 if (segoff < 0) { 2930 seg--; 2931 segoff += segs[seg].ds_len; 2932 } 2933 USB_KASSERT2(seg >= 0 && segoff >= 0, 2934 ("ehci_alloc_sqtd_chain: adjust to mps")); 2935 } 2936 } 2937 2938 len -= curlen; 2939 2940 if (len != 0 || forceshort) { 2941 next = ehci_alloc_sqtd(sc); 2942 if (next == NULL) 2943 goto nomem; 2944 nextphys = htole32(EHCI_SQTD_DMAADDR(next)); 2945 } else { 2946 next = NULL; 2947 nextphys = EHCI_NULL; 2948 } 2949 2950 cur->nextqtd = next; 2951 cur->qtd.qtd_next = nextphys; 2952 /* Make sure to stop after a short transfer. */ 2953 cur->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 2954 cur->qtd.qtd_status = 2955 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2956 cur->xfer = xfer; 2957 cur->len = curlen; 2958 DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%d\n", curlen)); 2959 if (iscontrol) { 2960 /* 2961 * adjust the toggle based on the number of packets 2962 * in this qtd 2963 */ 2964 if ((((curlen + mps - 1) / mps) & 1) || curlen == 0) 2965 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2966 } 2967 qtdstatus |= EHCI_QTD_ACTIVE; 2968 if (len == 0) { 2969 if (!forceshort) 2970 break; 2971 forceshort = 0; 2972 } 2973 EHCI_SQTD_SYNC(sc, cur, 2974 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2975 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2976 offset += curlen; 2977 cur = next; 2978 2979 #if 1 2980 if (needaux) 2981 usb_bufptr_advance(&bufptr, curlen, 2982 xfer->rqflags & URQ_DEV_MAP_MBUF); 2983 #endif 2984 } 2985 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2986 EHCI_SQTD_SYNC(sc, cur, 2987 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2988 if (needaux) 2989 ehci_aux_dma_sync(sc, &EXFER(xfer)->aux, BUS_DMASYNC_PREWRITE); 2990 2991 *ep = cur; 2992 2993 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2994 *sp, *ep)); 2995 2996 return (USBD_NORMAL_COMPLETION); 2997 2998 nomem: 2999 /* XXX free chain */ 3000 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 3001 return (USBD_NOMEM); 3002 } 3003 3004 /* Free the chain starting at sqtd and end at the qTD before sqtdend */ 3005 Static void 3006 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qh_t *sqh, 3007 ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *sqtdend) 3008 { 3009 ehci_soft_qtd_t *p, **prevp; 3010 int i; 3011 3012 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 3013 sqtd, sqtdend)); 3014 3015 /* First unlink the chain from the QH's software qTD list. */ 3016 prevp = &sqh->sqtd; 3017 for (p = sqh->sqtd; p != NULL; p = p->nextqtd) { 3018 if (p == sqtd) { 3019 *prevp = sqtdend; 3020 break; 3021 } 3022 prevp = &p->nextqtd; 3023 } 3024 USB_KASSERT2(p != NULL, ("ehci_free_sqtd_chain: chain not found")); 3025 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 3026 p = sqtd->nextqtd; 3027 ehci_free_sqtd(sc, sqtd); 3028 } 3029 } 3030 3031 /****************/ 3032 3033 /* 3034 * Close a reqular pipe. 3035 * Assumes that there are no pending transactions. 3036 */ 3037 void 3038 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3039 { 3040 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3041 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3042 ehci_soft_qh_t *sqh = epipe->sqh; 3043 int s; 3044 3045 s = splusb(); 3046 ehci_rem_qh(sc, sqh, head); 3047 splx(s); 3048 pipe->endpoint->savedtoggle = 3049 EHCI_QTD_GET_TOGGLE(le32toh(sqh->qh.qh_qtd.qtd_status)); 3050 ehci_free_sqh(sc, epipe->sqh); 3051 } 3052 3053 /* 3054 * Abort a device request. 3055 * If this routine is called at splusb() it guarantees that the request 3056 * will be removed from the hardware scheduling and that the callback 3057 * for it will be called with USBD_CANCELLED status. 3058 * It's impossible to guarantee that the requested transfer will not 3059 * have happened since the hardware runs concurrently. 3060 * If the transaction has already happened we rely on the ordinary 3061 * interrupt processing to process it. 3062 */ 3063 void 3064 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3065 { 3066 #define exfer EXFER(xfer) 3067 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3068 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 3069 ehci_soft_qh_t *sqh = epipe->sqh; 3070 ehci_soft_qtd_t *sqtd, *snext; 3071 ehci_physaddr_t cur, us, next; 3072 int s; 3073 int hit, i; 3074 /* int count = 0; */ 3075 ehci_soft_qh_t *psqh; 3076 3077 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 3078 3079 if (sc->sc_dying) { 3080 /* If we're dying, just do the software part. */ 3081 s = splusb(); 3082 xfer->status = status; /* make software ignore it */ 3083 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3084 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 3085 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, 3086 &EXFER(xfer)->dmabuf); 3087 splx(s); 3088 return; 3089 } 3090 3091 if (xfer->device->bus->intr_context || !curproc) 3092 panic("ehci_abort_xfer: not in process context"); 3093 3094 /* 3095 * If an abort is already in progress then just wait for it to 3096 * complete and return. 3097 */ 3098 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 3099 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3100 /* No need to wait if we're aborting from a timeout. */ 3101 if (status == USBD_TIMEOUT) 3102 return; 3103 /* Override the status which might be USBD_TIMEOUT. */ 3104 xfer->status = status; 3105 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3106 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT; 3107 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 3108 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciaw", 0); 3109 return; 3110 } 3111 3112 /* 3113 * Step 1: Make interrupt routine and timeouts ignore xfer. 3114 */ 3115 s = splusb(); 3116 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 3117 xfer->status = status; /* make software ignore it */ 3118 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3119 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 3120 splx(s); 3121 3122 /* 3123 * Step 2: Wait until we know hardware has finished any possible 3124 * use of the xfer. We do this by removing the entire 3125 * queue from the async schedule and waiting for the doorbell. 3126 * Nothing else should be touching the queue now. 3127 */ 3128 psqh = sqh->prev; 3129 ehci_rem_qh(sc, sqh, psqh); 3130 3131 /* 3132 * Step 3: make sure the soft interrupt routine 3133 * has run. This should remove any completed items off the queue. 3134 * The hardware has no reference to completed items (TDs). 3135 * It's safe to remove them at any time. 3136 */ 3137 s = splusb(); 3138 #ifdef USB_USE_SOFTINTR 3139 sc->sc_softwake = 1; 3140 #endif /* USB_USE_SOFTINTR */ 3141 usb_schedsoftintr(&sc->sc_bus); 3142 #ifdef USB_USE_SOFTINTR 3143 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3144 #endif /* USB_USE_SOFTINTR */ 3145 3146 /* 3147 * Step 4: Remove any vestiges of the xfer from the hardware. 3148 * The complication here is that the hardware may have executed 3149 * into or even beyond the xfer we're trying to abort. 3150 * So as we're scanning the TDs of this xfer we check if 3151 * the hardware points to any of them. 3152 * 3153 * first we need to see if there are any transfers 3154 * on this queue before the xfer we are aborting.. we need 3155 * to update any pointers that point to us to point past 3156 * the aborting xfer. (If there is something past us). 3157 * Hardware and software. 3158 */ 3159 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3160 hit = 0; 3161 3162 /* If they initially point here. */ 3163 us = EHCI_SQTD_DMAADDR(exfer->sqtdstart); 3164 3165 /* We will change them to point here */ 3166 snext = exfer->sqtdend->nextqtd; 3167 next = htole32(EHCI_SQTD_DMAADDR(snext)); 3168 3169 /* 3170 * Now loop through any qTDs before us and keep track of the pointer 3171 * that points to us for the end. 3172 */ 3173 sqtd = sqh->sqtd; 3174 while (sqtd && sqtd != exfer->sqtdstart) { 3175 hit |= (cur == EHCI_SQTD_DMAADDR(sqtd)); 3176 if (EHCI_LINK_ADDR(le32toh(sqtd->qtd.qtd_next)) == us) { 3177 sqtd->qtd.qtd_next = next; 3178 EHCI_SQTD_SYNC(sc, sqtd, 3179 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3180 } 3181 if (EHCI_LINK_ADDR(le32toh(sqtd->qtd.qtd_altnext)) == us) { 3182 sqtd->qtd.qtd_altnext = next; 3183 EHCI_SQTD_SYNC(sc, sqtd, 3184 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3185 } 3186 sqtd = sqtd->nextqtd; 3187 } 3188 3189 /* 3190 * If we already saw the active one then we are pretty much done. 3191 * We've done all the relinking we need to do. 3192 */ 3193 if (!hit) { 3194 3195 /* 3196 * Now reinitialise the QH to point to the next qTD 3197 * (if there is one). We only need to do this if 3198 * it was previously pointing to us. 3199 */ 3200 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3201 if (cur == EHCI_SQTD_DMAADDR(sqtd)) { 3202 hit++; 3203 } 3204 if (sqtd == exfer->sqtdend) 3205 break; 3206 } 3207 sqtd = sqtd->nextqtd; 3208 /* 3209 * Only need to alter the QH if it was pointing at a qTD 3210 * that we are removing. 3211 */ 3212 if (hit) { 3213 sqh->qh.qh_qtd.qtd_next = 3214 htole32(EHCI_SQTD_DMAADDR(snext)); 3215 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 3216 sqh->qh.qh_qtd.qtd_status &= 3217 htole32(EHCI_QTD_TOGGLE_MASK); 3218 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) { 3219 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 3220 sqh->qh.qh_qtd.qtd_buffer_hi[i] = 0; 3221 } 3222 } 3223 } 3224 ehci_add_qh(sc, sqh, psqh); 3225 /* 3226 * Step 5: Execute callback. 3227 */ 3228 #ifdef DIAGNOSTIC 3229 exfer->isdone = 1; 3230 #endif 3231 /* Do the wakeup first to avoid touching the xfer after the callback. */ 3232 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTING; 3233 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) { 3234 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT; 3235 wakeup(&exfer->ehci_xfer_flags); 3236 } 3237 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 3238 3239 /* printf("%s: %d TDs aborted\n", __func__, count); */ 3240 splx(s); 3241 #undef exfer 3242 } 3243 3244 void 3245 ehci_timeout(void *addr) 3246 { 3247 struct ehci_xfer *exfer = addr; 3248 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3249 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 3250 3251 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3252 #ifdef USB_DEBUG 3253 if (ehcidebug > 1) 3254 usbd_dump_pipe(exfer->xfer.pipe); 3255 #endif 3256 3257 if (sc->sc_dying) { 3258 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3259 return; 3260 } 3261 3262 /* Execute the abort in a process context. */ 3263 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3264 USB_TASKQ_HC); 3265 } 3266 3267 void 3268 ehci_timeout_task(void *addr) 3269 { 3270 usbd_xfer_handle xfer = addr; 3271 int s; 3272 3273 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3274 3275 s = splusb(); 3276 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3277 splx(s); 3278 } 3279 3280 /* 3281 * Some EHCI chips from VIA / ATI seem to trigger interrupts before writing 3282 * back the qTD status, or miss signalling occasionally under heavy load. 3283 * If the host machine is too fast, we can miss transaction completion - when 3284 * we scan the active list the transaction still seems to be active. This 3285 * generally exhibits itself as a umass stall that never recovers. 3286 * 3287 * We work around this behaviour by setting up this callback after any softintr 3288 * that completes with transactions still pending, giving us another chance to 3289 * check for completion after the writeback has taken place. 3290 */ 3291 void 3292 ehci_intrlist_timeout(void *arg) 3293 { 3294 ehci_softc_t *sc = arg; 3295 int s = splusb(); 3296 3297 DPRINTFN(3, ("ehci_intrlist_timeout\n")); 3298 usb_schedsoftintr(&sc->sc_bus); 3299 3300 splx(s); 3301 } 3302 3303 /************************/ 3304 3305 Static usbd_status 3306 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3307 { 3308 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3309 usbd_status err; 3310 3311 /* Insert last in queue. */ 3312 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3313 &EXFER(xfer)->dmabuf); 3314 if (err) 3315 return (err); 3316 3317 /* Pipe isn't running, start first */ 3318 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3319 } 3320 3321 Static usbd_status 3322 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3323 { 3324 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3325 usbd_status err; 3326 3327 if (sc->sc_dying) 3328 return (USBD_IOERROR); 3329 3330 #ifdef DIAGNOSTIC 3331 if (!(xfer->rqflags & URQ_REQUEST)) { 3332 /* XXX panic */ 3333 printf("ehci_device_ctrl_transfer: not a request\n"); 3334 return (USBD_INVAL); 3335 } 3336 #endif 3337 3338 err = ehci_device_request(xfer); 3339 if (err) 3340 return (err); 3341 3342 if (sc->sc_bus.use_polling) 3343 ehci_waitintr(sc, xfer); 3344 return (USBD_IN_PROGRESS); 3345 } 3346 3347 void 3348 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3349 { 3350 struct ehci_xfer *ex = EXFER(xfer); 3351 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3352 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3353 3354 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3355 3356 #ifdef DIAGNOSTIC 3357 if (!(xfer->rqflags & URQ_REQUEST)) { 3358 panic("ehci_ctrl_done: not a request"); 3359 } 3360 #endif 3361 3362 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3363 ehci_del_intr_list(ex); /* remove from active list */ 3364 ehci_free_sqtd_chain(sc, epipe->sqh, ex->sqtdstart, 3365 ex->sqtdend->nextqtd); 3366 } 3367 3368 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3369 } 3370 3371 /* Abort a device control request. */ 3372 Static void 3373 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3374 { 3375 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3376 ehci_abort_xfer(xfer, USBD_CANCELLED); 3377 } 3378 3379 /* Close a device control pipe. */ 3380 Static void 3381 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3382 { 3383 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3384 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3385 3386 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3387 ehci_close_pipe(pipe, sc->sc_async_head); 3388 usb_freemem(&sc->sc_dmatag, &epipe->u.ctl.reqdma); 3389 } 3390 3391 usbd_status 3392 ehci_device_request(usbd_xfer_handle xfer) 3393 { 3394 #define exfer EXFER(xfer) 3395 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3396 usb_device_request_t *req = &xfer->request; 3397 usbd_device_handle dev = epipe->pipe.device; 3398 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3399 ehci_soft_qtd_t *newinactive, *setup, *stat, *next; 3400 ehci_soft_qh_t *sqh; 3401 int isread; 3402 int len; 3403 usbd_status err; 3404 int s; 3405 3406 isread = req->bmRequestType & UT_READ; 3407 len = UGETW(req->wLength); 3408 3409 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3410 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3411 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3412 UGETW(req->wIndex), len, dev->address, 3413 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3414 3415 newinactive = ehci_alloc_sqtd(sc); 3416 if (newinactive == NULL) { 3417 err = USBD_NOMEM; 3418 goto bad1; 3419 } 3420 newinactive->qtd.qtd_status = htole32(0); 3421 newinactive->qtd.qtd_next = EHCI_NULL; 3422 newinactive->qtd.qtd_altnext = EHCI_NULL; 3423 EHCI_SQTD_SYNC(sc, newinactive, 3424 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3425 stat = ehci_alloc_sqtd(sc); 3426 if (stat == NULL) { 3427 err = USBD_NOMEM; 3428 goto bad2; 3429 } 3430 3431 sqh = epipe->sqh; 3432 setup = sqh->inactivesqtd; 3433 sqh->inactivesqtd = newinactive; 3434 epipe->u.ctl.length = len; 3435 3436 /* Set up data transaction */ 3437 if (len != 0) { 3438 ehci_soft_qtd_t *end; 3439 3440 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3441 NULL, newinactive, &next, &end); 3442 if (err) 3443 goto bad3; 3444 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3445 end->nextqtd = stat; 3446 end->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(stat)); 3447 end->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3448 } else { 3449 next = stat; 3450 } 3451 3452 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3453 3454 /* Clear toggle, and do not activate until complete */ 3455 setup->qtd.qtd_status = htole32( 3456 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3457 EHCI_QTD_SET_CERR(3) | 3458 EHCI_QTD_SET_TOGGLE(0) | 3459 EHCI_QTD_SET_BYTES(sizeof *req) 3460 ); 3461 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3462 setup->qtd.qtd_buffer_hi[0] = 0; 3463 setup->nextqtd = next; 3464 setup->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(next)); 3465 setup->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3466 setup->xfer = xfer; 3467 setup->len = sizeof *req; 3468 EHCI_SQTD_SYNC(sc, setup, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3469 3470 stat->qtd.qtd_status = htole32( 3471 EHCI_QTD_ACTIVE | 3472 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3473 EHCI_QTD_SET_CERR(3) | 3474 EHCI_QTD_SET_TOGGLE(1) | 3475 EHCI_QTD_IOC 3476 ); 3477 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3478 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3479 stat->nextqtd = newinactive; 3480 stat->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3481 stat->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3482 stat->xfer = xfer; 3483 stat->len = 0; 3484 EHCI_SQTD_SYNC(sc, stat, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3485 3486 #ifdef EHCI_DEBUG 3487 if (ehcidebug > 5) { 3488 DPRINTF(("ehci_device_request:\n")); 3489 ehci_dump_sqh(sqh); 3490 ehci_dump_sqtds(setup); 3491 } 3492 #endif 3493 3494 exfer->sqtdstart = setup; 3495 exfer->sqtdend = stat; 3496 #ifdef DIAGNOSTIC 3497 if (!exfer->isdone) { 3498 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3499 } 3500 exfer->isdone = 0; 3501 #endif 3502 3503 /* Activate the new qTD in the QH list. */ 3504 s = splusb(); 3505 ehci_activate_qh(sc, sqh, setup); 3506 if (xfer->timeout && !sc->sc_bus.use_polling) { 3507 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 3508 ehci_timeout, xfer); 3509 } 3510 ehci_add_intr_list(sc, exfer); 3511 xfer->status = USBD_IN_PROGRESS; 3512 splx(s); 3513 3514 #ifdef EHCI_DEBUG 3515 if (ehcidebug > 10) { 3516 DPRINTF(("ehci_device_request: status=%x\n", 3517 EOREAD4(sc, EHCI_USBSTS))); 3518 delay(10000); 3519 ehci_dump_regs(sc); 3520 ehci_dump_sqh(sc->sc_async_head); 3521 ehci_dump_sqh(sqh); 3522 ehci_dump_sqtds(setup); 3523 } 3524 #endif 3525 3526 return (USBD_NORMAL_COMPLETION); 3527 3528 bad3: 3529 sqh->inactivesqtd = setup; 3530 ehci_free_sqtd(sc, stat); 3531 bad2: 3532 ehci_free_sqtd(sc, newinactive); 3533 bad1: 3534 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3535 xfer->status = err; 3536 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, 3537 &EXFER(xfer)->dmabuf); 3538 return (err); 3539 #undef exfer 3540 } 3541 3542 /************************/ 3543 3544 Static usbd_status 3545 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3546 { 3547 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3548 usbd_status err; 3549 3550 /* Insert last in queue. */ 3551 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3552 &EXFER(xfer)->dmabuf); 3553 if (err) 3554 return (err); 3555 3556 /* Pipe isn't running, start first */ 3557 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3558 } 3559 3560 usbd_status 3561 ehci_device_bulk_start(usbd_xfer_handle xfer) 3562 { 3563 #define exfer EXFER(xfer) 3564 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3565 usbd_device_handle dev = epipe->pipe.device; 3566 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3567 ehci_soft_qtd_t *data, *dataend, *newinactive; 3568 ehci_soft_qh_t *sqh; 3569 usbd_status err; 3570 int len, isread, endpt; 3571 int s; 3572 3573 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3574 xfer, xfer->length, xfer->flags)); 3575 3576 if (sc->sc_dying) 3577 return (USBD_IOERROR); 3578 3579 #ifdef DIAGNOSTIC 3580 if (xfer->rqflags & URQ_REQUEST) 3581 panic("ehci_device_bulk_start: a request"); 3582 #endif 3583 3584 len = xfer->length; 3585 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3586 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3587 sqh = epipe->sqh; 3588 3589 epipe->u.bulk.length = len; 3590 3591 newinactive = ehci_alloc_sqtd(sc); 3592 if (newinactive == NULL) { 3593 DPRINTFN(-1,("ehci_device_bulk_start: no sqtd memory\n")); 3594 err = USBD_NOMEM; 3595 xfer->status = err; 3596 usb_transfer_complete(xfer); 3597 return (err); 3598 } 3599 newinactive->qtd.qtd_status = htole32(0); 3600 newinactive->qtd.qtd_next = EHCI_NULL; 3601 newinactive->qtd.qtd_altnext = EHCI_NULL; 3602 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3603 sqh->inactivesqtd, newinactive, &data, &dataend); 3604 if (err) { 3605 DPRINTFN(-1,("ehci_device_bulk_start: no memory\n")); 3606 ehci_free_sqtd(sc, newinactive); 3607 xfer->status = err; 3608 usb_transfer_complete(xfer); 3609 return (err); 3610 } 3611 dataend->nextqtd = newinactive; 3612 dataend->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3613 dataend->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3614 sqh->inactivesqtd = newinactive; 3615 EHCI_SQTD_SYNC(sc, newinactive, 3616 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3617 EHCI_SQTD_SYNC(sc, dataend, 3618 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3619 3620 #ifdef EHCI_DEBUG 3621 if (ehcidebug > 5) { 3622 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3623 ehci_dump_sqh(sqh); 3624 ehci_dump_sqtds(data); 3625 } 3626 #endif 3627 3628 /* Set up interrupt info. */ 3629 exfer->sqtdstart = data; 3630 exfer->sqtdend = dataend; 3631 #ifdef DIAGNOSTIC 3632 if (!exfer->isdone) { 3633 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3634 } 3635 exfer->isdone = 0; 3636 #endif 3637 3638 s = splusb(); 3639 ehci_activate_qh(sc, sqh, data); 3640 if (xfer->timeout && !sc->sc_bus.use_polling) { 3641 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 3642 ehci_timeout, xfer); 3643 } 3644 ehci_add_intr_list(sc, exfer); 3645 xfer->status = USBD_IN_PROGRESS; 3646 splx(s); 3647 3648 #ifdef EHCI_DEBUG 3649 if (ehcidebug > 10) { 3650 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3651 delay(10000); 3652 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3653 ehci_dump_regs(sc); 3654 #if 0 3655 printf("async_head:\n"); 3656 ehci_dump_sqh(sc->sc_async_head); 3657 #endif 3658 printf("sqh:\n"); 3659 ehci_dump_sqh(sqh); 3660 ehci_dump_sqtds(data); 3661 } 3662 #endif 3663 3664 if (sc->sc_bus.use_polling) 3665 ehci_waitintr(sc, xfer); 3666 3667 return (USBD_IN_PROGRESS); 3668 #undef exfer 3669 } 3670 3671 Static void 3672 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3673 { 3674 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3675 ehci_abort_xfer(xfer, USBD_CANCELLED); 3676 } 3677 3678 /* 3679 * Close a device bulk pipe. 3680 */ 3681 Static void 3682 ehci_device_bulk_close(usbd_pipe_handle pipe) 3683 { 3684 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3685 3686 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3687 ehci_close_pipe(pipe, sc->sc_async_head); 3688 } 3689 3690 void 3691 ehci_device_bulk_done(usbd_xfer_handle xfer) 3692 { 3693 struct ehci_xfer *ex = EXFER(xfer); 3694 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3695 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3696 3697 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3698 xfer, xfer->actlen)); 3699 3700 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3701 ehci_del_intr_list(ex); /* remove from active list */ 3702 ehci_free_sqtd_chain(sc, epipe->sqh, ex->sqtdstart, 3703 ex->sqtdend->nextqtd); 3704 } 3705 3706 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3707 } 3708 3709 /************************/ 3710 3711 Static usbd_status 3712 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3713 { 3714 struct ehci_soft_islot *isp; 3715 int islot, lev; 3716 3717 /* Find a poll rate that is large enough. */ 3718 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3719 if (EHCI_ILEV_IVAL(lev) <= ival) 3720 break; 3721 3722 /* Pick an interrupt slot at the right level. */ 3723 /* XXX could do better than picking at random. */ 3724 islot = EHCI_IQHIDX(lev, arc4random()); 3725 3726 sqh->islot = islot; 3727 isp = &sc->sc_islots[islot]; 3728 ehci_add_qh(sc, sqh, isp->sqh); 3729 3730 return (USBD_NORMAL_COMPLETION); 3731 } 3732 3733 Static usbd_status 3734 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3735 { 3736 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3737 usbd_status err; 3738 3739 /* Insert last in queue. */ 3740 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3741 &EXFER(xfer)->dmabuf); 3742 if (err) 3743 return (err); 3744 3745 /* 3746 * Pipe isn't running (otherwise err would be USBD_INPROG), 3747 * so start it first. 3748 */ 3749 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3750 } 3751 3752 Static usbd_status 3753 ehci_device_intr_start(usbd_xfer_handle xfer) 3754 { 3755 #define exfer EXFER(xfer) 3756 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3757 usbd_device_handle dev = xfer->pipe->device; 3758 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3759 ehci_soft_qtd_t *data, *dataend, *newinactive; 3760 ehci_soft_qh_t *sqh; 3761 usbd_status err; 3762 int len, isread, endpt; 3763 int s; 3764 3765 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3766 xfer, xfer->length, xfer->flags)); 3767 3768 if (sc->sc_dying) 3769 return (USBD_IOERROR); 3770 3771 #ifdef DIAGNOSTIC 3772 if (xfer->rqflags & URQ_REQUEST) 3773 panic("ehci_device_intr_start: a request"); 3774 #endif 3775 3776 len = xfer->length; 3777 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3778 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3779 sqh = epipe->sqh; 3780 3781 epipe->u.intr.length = len; 3782 3783 newinactive = ehci_alloc_sqtd(sc); 3784 if (newinactive == NULL) { 3785 DPRINTFN(-1,("ehci_device_intr_start: no sqtd memory\n")); 3786 err = USBD_NOMEM; 3787 xfer->status = err; 3788 usb_transfer_complete(xfer); 3789 return (err); 3790 } 3791 newinactive->qtd.qtd_status = htole32(0); 3792 newinactive->qtd.qtd_next = EHCI_NULL; 3793 newinactive->qtd.qtd_altnext = EHCI_NULL; 3794 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3795 sqh->inactivesqtd, newinactive, &data, &dataend); 3796 if (err) { 3797 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3798 xfer->status = err; 3799 usb_transfer_complete(xfer); 3800 return (err); 3801 } 3802 dataend->nextqtd = newinactive; 3803 dataend->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3804 dataend->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3805 sqh->inactivesqtd = newinactive; 3806 EHCI_SQTD_SYNC(sc, newinactive, 3807 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3808 EHCI_SQTD_SYNC(sc, dataend, 3809 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3810 3811 #ifdef EHCI_DEBUG 3812 if (ehcidebug > 5) { 3813 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3814 ehci_dump_sqh(sqh); 3815 ehci_dump_sqtds(data); 3816 } 3817 #endif 3818 3819 /* Set up interrupt info. */ 3820 exfer->sqtdstart = data; 3821 exfer->sqtdend = dataend; 3822 #ifdef DIAGNOSTIC 3823 if (!exfer->isdone) { 3824 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3825 } 3826 exfer->isdone = 0; 3827 #endif 3828 3829 s = splusb(); 3830 ehci_activate_qh(sc, sqh, data); 3831 if (xfer->timeout && !sc->sc_bus.use_polling) { 3832 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 3833 ehci_timeout, xfer); 3834 } 3835 ehci_add_intr_list(sc, exfer); 3836 xfer->status = USBD_IN_PROGRESS; 3837 splx(s); 3838 3839 #ifdef EHCI_DEBUG 3840 if (ehcidebug > 10) { 3841 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3842 delay(10000); 3843 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3844 ehci_dump_regs(sc); 3845 printf("sqh:\n"); 3846 ehci_dump_sqh(sqh); 3847 ehci_dump_sqtds(data); 3848 } 3849 #endif 3850 3851 if (sc->sc_bus.use_polling) 3852 ehci_waitintr(sc, xfer); 3853 3854 return (USBD_IN_PROGRESS); 3855 #undef exfer 3856 } 3857 3858 Static void 3859 ehci_device_intr_abort(usbd_xfer_handle xfer) 3860 { 3861 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3862 if (xfer->pipe->intrxfer == xfer) { 3863 DPRINTFN(1, ("ehci_device_intr_abort: remove\n")); 3864 xfer->pipe->intrxfer = NULL; 3865 } 3866 ehci_abort_xfer(xfer, USBD_CANCELLED); 3867 } 3868 3869 Static void 3870 ehci_device_intr_close(usbd_pipe_handle pipe) 3871 { 3872 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3873 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3874 struct ehci_soft_islot *isp; 3875 3876 isp = &sc->sc_islots[epipe->sqh->islot]; 3877 ehci_close_pipe(pipe, isp->sqh); 3878 } 3879 3880 Static void 3881 ehci_device_intr_done(usbd_xfer_handle xfer) 3882 { 3883 #define exfer EXFER(xfer) 3884 struct ehci_xfer *ex = EXFER(xfer); 3885 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3886 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3887 ehci_soft_qtd_t *data, *dataend, *newinactive; 3888 ehci_soft_qh_t *sqh; 3889 usbd_status err; 3890 int len, isread, endpt, s; 3891 3892 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3893 xfer, xfer->actlen)); 3894 3895 sqh = epipe->sqh; 3896 if (xfer->pipe->repeat) { 3897 ehci_free_sqtd_chain(sc, sqh, ex->sqtdstart, 3898 ex->sqtdend->nextqtd); 3899 3900 len = epipe->u.intr.length; 3901 xfer->length = len; 3902 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3903 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3904 3905 newinactive = ehci_alloc_sqtd(sc); 3906 if (newinactive == NULL) { 3907 DPRINTFN(-1, 3908 ("ehci_device_intr_done: no sqtd memory\n")); 3909 err = USBD_NOMEM; 3910 xfer->status = err; 3911 return; 3912 } 3913 newinactive->qtd.qtd_status = htole32(0); 3914 newinactive->qtd.qtd_next = EHCI_NULL; 3915 newinactive->qtd.qtd_altnext = EHCI_NULL; 3916 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3917 sqh->inactivesqtd, newinactive, &data, &dataend); 3918 if (err) { 3919 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3920 xfer->status = err; 3921 return; 3922 } 3923 dataend->nextqtd = newinactive; 3924 dataend->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3925 dataend->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3926 sqh->inactivesqtd = newinactive; 3927 EHCI_SQTD_SYNC(sc, newinactive, 3928 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3929 EHCI_SQTD_SYNC(sc, dataend, 3930 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3931 3932 /* Set up interrupt info. */ 3933 exfer->sqtdstart = data; 3934 exfer->sqtdend = dataend; 3935 #ifdef DIAGNOSTIC 3936 if (!exfer->isdone) { 3937 printf("ehci_device_intr_done: not done, ex=%p\n", 3938 exfer); 3939 } 3940 exfer->isdone = 0; 3941 #endif 3942 3943 s = splusb(); 3944 ehci_activate_qh(sc, sqh, data); 3945 if (xfer->timeout && !sc->sc_bus.use_polling) { 3946 usb_callout(xfer->timeout_handle, 3947 MS_TO_TICKS(xfer->timeout), ehci_timeout, xfer); 3948 } 3949 splx(s); 3950 3951 xfer->status = USBD_IN_PROGRESS; 3952 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3953 ehci_del_intr_list(ex); /* remove from active list */ 3954 ehci_free_sqtd_chain(sc, sqh, ex->sqtdstart, 3955 ex->sqtdend->nextqtd); 3956 } 3957 #undef exfer 3958 } 3959 3960 /************************/ 3961 3962 Static usbd_status 3963 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3964 { 3965 return USBD_IOERROR; 3966 } 3967 Static usbd_status 3968 ehci_device_isoc_start(usbd_xfer_handle xfer) 3969 { 3970 return USBD_IOERROR; 3971 } 3972 Static void 3973 ehci_device_isoc_abort(usbd_xfer_handle xfer) 3974 { 3975 } 3976 Static void 3977 ehci_device_isoc_close(usbd_pipe_handle pipe) 3978 { 3979 } 3980 Static void 3981 ehci_device_isoc_done(usbd_xfer_handle xfer) 3982 { 3983 } 3984
Indexes created Wed Oct 01 19:09:53 GMT 2025