ehci.c revision 1.123.12.4
1 /* $NetBSD: ehci.c,v 1.123.12.4 2008/05/21 05:26:13 itohy Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2005, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 41 * 42 * The EHCI 1.0 spec can be found at 43 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 44 * and the USB 2.0 spec at 45 * http://www.usb.org/developers/docs/usb_20.zip 46 * 47 */ 48 49 /* 50 * TODO: 51 * 1) The EHCI driver lacks support for isochronous transfers, so 52 * devices using them don't work. 53 * 54 * 2) Interrupt transfer scheduling does not manage the time available 55 * in each frame, so it is possible for the transfers to overrun 56 * the end of the frame. 57 * 58 * 3) Command failures are not recovered correctly. 59 */ 60 61 #include <sys/cdefs.h> 62 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.123.12.4 2008/05/21 05:26:13 itohy Exp $"); 63 /* __FBSDID("$FreeBSD: /repoman/r/ncvs/src/sys/dev/usb/ehci.c,v 1.52 2006/10/19 01:15:58 iedowse Exp $"); */ 64 65 #if defined(__NetBSD__) || defined(__OpenBSD__) 66 #include "ohci.h" 67 #include "uhci.h" 68 #endif 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/kernel.h> 73 #include <sys/malloc.h> 74 #if defined(__NetBSD__) || defined(__OpenBSD__) 75 #include <sys/device.h> 76 #include <sys/select.h> 77 #elif defined(__FreeBSD__) 78 #include <sys/endian.h> 79 #include <sys/module.h> 80 #include <sys/bus.h> 81 #include <sys/lockmgr.h> 82 #if defined(DIAGNOSTIC) && defined(__i386__) && defined(__FreeBSD__) 83 #include <machine/cpu.h> 84 #endif 85 #endif 86 #include <sys/proc.h> 87 #include <sys/queue.h> 88 #include <sys/sysctl.h> 89 90 #include <machine/bus.h> 91 #include <machine/endian.h> 92 93 #include <dev/usb/usb.h> 94 #include <dev/usb/usbdi.h> 95 #include <dev/usb/usbdivar.h> 96 #include <dev/usb/usb_mem.h> 97 #include <dev/usb/usb_quirks.h> 98 99 #include <dev/usb/ehcireg.h> 100 #include <dev/usb/ehcivar.h> 101 102 #if defined(__FreeBSD__) 103 104 #define delay(d) DELAY(d) 105 #endif 106 107 #ifdef USB_DEBUG 108 /* #define EHCI_DEBUG USB_DEBUG */ 109 #define DPRINTF(x) do { if (ehcidebug) logprintf x; } while (0) 110 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) logprintf x; } while (0) 111 int ehcidebug = 0; 112 #ifdef __FreeBSD__ 113 SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 114 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW, 115 &ehcidebug, 0, "ehci debug level"); 116 #endif 117 #ifndef __NetBSD__ 118 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 119 #endif 120 #else 121 #define DPRINTF(x) 122 #define DPRINTFN(n,x) 123 #endif 124 125 struct ehci_pipe { 126 struct usbd_pipe pipe; 127 128 ehci_soft_qh_t *sqh; 129 union { 130 ehci_soft_qtd_t *qtd; 131 /* ehci_soft_itd_t *itd; */ 132 } tail; 133 union { 134 /* Control pipe */ 135 struct { 136 usb_dma_t reqdma; 137 u_int length; 138 } ctl; 139 /* Interrupt pipe */ 140 struct { 141 u_int length; 142 } intr; 143 /* Bulk pipe */ 144 struct { 145 u_int length; 146 } bulk; 147 /* Iso pipe */ 148 /* XXX */ 149 } u; 150 }; 151 152 Static usbd_status ehci_open(usbd_pipe_handle); 153 Static void ehci_poll(struct usbd_bus *); 154 Static void ehci_softintr(void *); 155 Static int ehci_intr1(ehci_softc_t *); 156 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 157 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 158 Static void ehci_idone(struct ehci_xfer *); 159 Static void ehci_timeout(void *); 160 Static void ehci_timeout_task(void *); 161 Static void ehci_intrlist_timeout(void *); 162 163 Static void ehci_aux_mem_init(struct ehci_aux_mem *); 164 Static usbd_status ehci_aux_mem_alloc(ehci_softc_t *, 165 struct ehci_aux_mem *, 166 int /*naux*/, int /*maxp*/); 167 Static void ehci_aux_mem_free(ehci_softc_t *, 168 struct ehci_aux_mem *); 169 struct aux_desc { 170 void *aux_kern; 171 }; 172 Static bus_addr_t ehci_aux_dma_alloc(struct ehci_aux_mem *, int, 173 struct aux_desc *); 174 Static void ehci_aux_dma_sync(ehci_softc_t *, 175 struct ehci_aux_mem *, int /*op*/); 176 177 Static usbd_status ehci_prealloc(struct ehci_softc *, struct ehci_xfer *, 178 size_t, int); 179 Static usbd_status ehci_allocm(struct usbd_bus *, usbd_xfer_handle, 180 void *, size_t); 181 Static void ehci_freem(struct usbd_bus *, usbd_xfer_handle, 182 enum usbd_waitflg); 183 184 Static usbd_status ehci_map_alloc(usbd_xfer_handle); 185 Static void ehci_map_free(usbd_xfer_handle); 186 Static void ehci_mapm(usbd_xfer_handle, void *, size_t); 187 Static usbd_status ehci_mapm_mbuf(usbd_xfer_handle, struct mbuf *); 188 Static void ehci_unmapm(usbd_xfer_handle); 189 190 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *, usbd_pipe_handle, 191 enum usbd_waitflg); 192 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 193 194 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 195 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 196 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 197 Static void ehci_root_ctrl_close(usbd_pipe_handle); 198 Static void ehci_root_ctrl_done(usbd_xfer_handle); 199 200 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 201 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 202 Static void ehci_root_intr_abort(usbd_xfer_handle); 203 Static void ehci_root_intr_close(usbd_pipe_handle); 204 Static void ehci_root_intr_done(usbd_xfer_handle); 205 206 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 207 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 208 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 209 Static void ehci_device_ctrl_close(usbd_pipe_handle); 210 Static void ehci_device_ctrl_done(usbd_xfer_handle); 211 212 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 213 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 214 Static void ehci_device_bulk_abort(usbd_xfer_handle); 215 Static void ehci_device_bulk_close(usbd_pipe_handle); 216 Static void ehci_device_bulk_done(usbd_xfer_handle); 217 218 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 219 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 220 Static void ehci_device_intr_abort(usbd_xfer_handle); 221 Static void ehci_device_intr_close(usbd_pipe_handle); 222 Static void ehci_device_intr_done(usbd_xfer_handle); 223 224 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 225 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 226 Static void ehci_device_isoc_abort(usbd_xfer_handle); 227 Static void ehci_device_isoc_close(usbd_pipe_handle); 228 Static void ehci_device_isoc_done(usbd_xfer_handle); 229 230 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 231 Static void ehci_noop(usbd_pipe_handle pipe); 232 233 Static int ehci_str(usb_string_descriptor_t *, int, const char *); 234 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 235 Static void ehci_disown(ehci_softc_t *, int, int); 236 237 Static usbd_status ehci_grow_sqtd(ehci_softc_t *); 238 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 239 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 240 241 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 242 Static ehci_soft_qtd_t *ehci_alloc_sqtd_norsv(ehci_softc_t *); 243 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 244 Static void ehci_free_sqtd_norsv(ehci_softc_t *, ehci_soft_qtd_t *); 245 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 246 ehci_softc_t *, int, int, usbd_xfer_handle, 247 ehci_soft_qtd_t *, ehci_soft_qtd_t *, 248 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 249 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qh_t *, 250 ehci_soft_qtd_t *, ehci_soft_qtd_t *); 251 Static void ehci_free_desc_chunks(ehci_softc_t *, 252 struct ehci_mdescs *); 253 254 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 255 256 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 257 int ival); 258 259 Static void ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *, 260 ehci_soft_qh_t *); 261 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 262 ehci_soft_qh_t *); 263 Static void ehci_activate_qh(ehci_softc_t *, ehci_soft_qh_t *, 264 ehci_soft_qtd_t *); 265 Static void ehci_sync_hc(ehci_softc_t *); 266 267 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 268 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 269 270 #ifdef EHCI_DEBUG 271 Static void ehci_dump_regs(ehci_softc_t *); 272 void ehci_dump(void); 273 Static ehci_softc_t *theehci; 274 Static void ehci_dump_link(ehci_link_t, int); 275 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 276 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 277 Static void ehci_dump_qtd(ehci_qtd_t *); 278 Static void ehci_dump_sqh(ehci_soft_qh_t *); 279 #ifdef DIAGNOSTIC 280 Static void ehci_dump_exfer(struct ehci_xfer *); 281 #endif 282 #endif 283 284 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 285 286 #define EHCI_INTR_ENDPT 1 287 288 #define ehci_add_intr_list(sc, ex) \ 289 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext); 290 #define ehci_del_intr_list(ex) \ 291 do { \ 292 LIST_REMOVE((ex), inext); \ 293 (ex)->inext.le_prev = NULL; \ 294 } while (0) 295 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL) 296 297 Static const struct usbd_bus_methods ehci_bus_methods = { 298 ehci_open, 299 ehci_softintr, 300 ehci_poll, 301 ehci_allocm, 302 ehci_freem, 303 ehci_map_alloc, 304 ehci_map_free, 305 ehci_mapm, 306 ehci_mapm_mbuf, 307 ehci_unmapm, 308 ehci_allocx, 309 ehci_freex, 310 }; 311 312 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 313 ehci_root_ctrl_transfer, 314 ehci_root_ctrl_start, 315 ehci_root_ctrl_abort, 316 ehci_root_ctrl_close, 317 ehci_noop, 318 ehci_root_ctrl_done, 319 }; 320 321 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 322 ehci_root_intr_transfer, 323 ehci_root_intr_start, 324 ehci_root_intr_abort, 325 ehci_root_intr_close, 326 ehci_noop, 327 ehci_root_intr_done, 328 }; 329 330 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 331 ehci_device_ctrl_transfer, 332 ehci_device_ctrl_start, 333 ehci_device_ctrl_abort, 334 ehci_device_ctrl_close, 335 ehci_noop, 336 ehci_device_ctrl_done, 337 }; 338 339 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 340 ehci_device_intr_transfer, 341 ehci_device_intr_start, 342 ehci_device_intr_abort, 343 ehci_device_intr_close, 344 ehci_device_clear_toggle, 345 ehci_device_intr_done, 346 }; 347 348 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 349 ehci_device_bulk_transfer, 350 ehci_device_bulk_start, 351 ehci_device_bulk_abort, 352 ehci_device_bulk_close, 353 ehci_device_clear_toggle, 354 ehci_device_bulk_done, 355 }; 356 357 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 358 ehci_device_isoc_transfer, 359 ehci_device_isoc_start, 360 ehci_device_isoc_abort, 361 ehci_device_isoc_close, 362 ehci_noop, 363 ehci_device_isoc_done, 364 }; 365 366 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 367 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 368 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 369 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 370 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 371 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 372 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 373 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 374 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 375 }; 376 377 usbd_status 378 ehci_init(ehci_softc_t *sc) 379 { 380 u_int32_t vers, sparams, cparams, hcr; 381 u_int i; 382 usbd_status err; 383 ehci_soft_qh_t *sqh; 384 u_int ncomp; 385 int lev; 386 387 DPRINTF(("ehci_init: start\n")); 388 #ifdef EHCI_DEBUG 389 theehci = sc; 390 #endif 391 392 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 393 394 vers = EREAD2(sc, EHCI_HCIVERSION); 395 aprint_verbose("%s: EHCI version %x.%x\n", USBDEVNAME(sc->sc_bus.bdev), 396 vers >> 8, vers & 0xff); 397 398 sparams = EREAD4(sc, EHCI_HCSPARAMS); 399 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 400 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 401 ncomp = EHCI_HCS_N_CC(sparams); 402 if (ncomp != sc->sc_ncomp) { 403 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 404 USBDEVNAME(sc->sc_bus.bdev), 405 ncomp, sc->sc_ncomp); 406 if (ncomp < sc->sc_ncomp) 407 sc->sc_ncomp = ncomp; 408 } 409 if (sc->sc_ncomp > 0) { 410 printf("%s: companion controller%s, %d port%s each:", 411 USBDEVNAME(sc->sc_bus.bdev), sc->sc_ncomp!=1 ? "s" : "", 412 EHCI_HCS_N_PCC(sparams), 413 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 414 for (i = 0; i < sc->sc_ncomp; i++) 415 printf(" %s", USBDEVNAME(sc->sc_comps[i]->bdev)); 416 printf("\n"); 417 } 418 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 419 cparams = EREAD4(sc, EHCI_HCCPARAMS); 420 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 421 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 422 423 if (EHCI_HCC_64BIT(cparams)) { 424 /* MUST clear segment register if 64 bit capable. */ 425 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 426 } 427 428 sc->sc_bus.usbrev = USBREV_2_0; 429 usb_dma_tag_init(&sc->sc_dmatag); 430 431 /* Reset the controller */ 432 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 433 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 434 usb_delay_ms(&sc->sc_bus, 1); 435 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 436 for (i = 0; i < 100; i++) { 437 usb_delay_ms(&sc->sc_bus, 1); 438 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 439 if (!hcr) 440 break; 441 } 442 if (hcr) { 443 printf("%s: reset timeout\n", 444 USBDEVNAME(sc->sc_bus.bdev)); 445 return (USBD_IOERROR); 446 } 447 448 /* frame list size at default, read back what we got and use that */ 449 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 450 case 0: sc->sc_flsize = 1024; break; 451 case 1: sc->sc_flsize = 512; break; 452 case 2: sc->sc_flsize = 256; break; 453 case 3: return (USBD_IOERROR); 454 } 455 err = usb_allocmem(&sc->sc_dmatag, sc->sc_flsize * sizeof(ehci_link_t), 456 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 457 if (err) 458 return (err); 459 DPRINTF(("%s: flsize=%d\n", USBDEVNAME(sc->sc_bus.bdev),sc->sc_flsize)); 460 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 461 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 462 463 /* Set up the bus struct. */ 464 sc->sc_bus.methods = &ehci_bus_methods; 465 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 466 467 #if defined(__NetBSD__) || defined(__OpenBSD__) 468 sc->sc_powerhook = powerhook_establish(USBDEVNAME(sc->sc_bus.bdev), 469 ehci_power, sc); 470 sc->sc_shutdownhook = shutdownhook_establish(ehci_shutdown, sc); 471 #endif 472 473 sc->sc_eintrs = EHCI_NORMAL_INTRS; 474 475 /* 476 * Allocate the interrupt dummy QHs. These are arranged to give 477 * poll intervals that are powers of 2 times 1ms. 478 */ 479 for (i = 0; i < EHCI_INTRQHS; i++) { 480 sqh = ehci_alloc_sqh(sc); 481 if (sqh == NULL) { 482 err = USBD_NOMEM; 483 goto bad1; 484 } 485 sc->sc_islots[i].sqh = sqh; 486 } 487 lev = 0; 488 for (i = 0; i < EHCI_INTRQHS; i++) { 489 if (i == EHCI_IQHIDX(lev + 1, 0)) 490 lev++; 491 sqh = sc->sc_islots[i].sqh; 492 if (i == 0) { 493 /* The last (1ms) QH terminates. */ 494 sqh->qh.qh_link = EHCI_NULL; 495 sqh->next = NULL; 496 } else { 497 /* Otherwise the next QH has half the poll interval */ 498 sqh->next = 499 sc->sc_islots[EHCI_IQHIDX(lev - 1, i + 1)].sqh; 500 sqh->qh.qh_link = htole32(EHCI_SQH_DMAADDR(sqh->next) | 501 EHCI_LINK_QH); 502 } 503 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 504 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 505 sqh->qh.qh_curqtd = EHCI_NULL; 506 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 507 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 508 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 509 } 510 /* Point the frame list at the last level (128ms). */ 511 for (i = 0; i < sc->sc_flsize; i++) { 512 int j; 513 514 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 515 revbits[i & (EHCI_MAX_POLLRATE-1)]; 516 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 517 EHCI_SQH_DMAADDR(sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES 518 - 1, i)].sqh)); 519 } 520 EHCI_SQH_SYNC(sc, sqh, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 521 522 /* Allocate dummy QH that starts the async list. */ 523 sqh = ehci_alloc_sqh(sc); 524 if (sqh == NULL) { 525 err = USBD_NOMEM; 526 goto bad1; 527 } 528 /* Fill the QH */ 529 sqh->qh.qh_endp = 530 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 531 sqh->qh.qh_link = 532 htole32(EHCI_SQH_DMAADDR(sqh) | EHCI_LINK_QH); 533 sqh->qh.qh_curqtd = EHCI_NULL; 534 sqh->prev = sqh; /*It's a circular list.. */ 535 sqh->next = sqh; 536 /* Fill the overlay qTD */ 537 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 538 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 539 sqh->qh.qh_qtd.qtd_status = htole32(0); 540 #ifdef EHCI_DEBUG 541 if (ehcidebug) { 542 ehci_dump_sqh(sqh); 543 } 544 #endif 545 EHCI_SQH_SYNC(sc, sqh, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 546 547 /* Point to async list */ 548 sc->sc_async_head = sqh; 549 EOWRITE4(sc, EHCI_ASYNCLISTADDR, EHCI_SQH_DMAADDR(sqh) | EHCI_LINK_QH); 550 551 usb_callout_init(sc->sc_tmo_intrlist); 552 553 lockinit(&sc->sc_doorbell_lock, PZERO, "ehcidb", 0, 0); 554 555 /* Enable interrupts */ 556 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 557 558 /* Turn on controller */ 559 EOWRITE4(sc, EHCI_USBCMD, 560 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 561 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 562 EHCI_CMD_ASE | 563 EHCI_CMD_PSE | 564 EHCI_CMD_RS); 565 566 /* Take over port ownership */ 567 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 568 569 for (i = 0; i < 100; i++) { 570 usb_delay_ms(&sc->sc_bus, 1); 571 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 572 if (!hcr) 573 break; 574 } 575 if (hcr) { 576 printf("%s: run timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 577 return (USBD_IOERROR); 578 } 579 580 /* Enable interrupts */ 581 DPRINTFN(1,("ehci_init: enabling\n")); 582 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 583 584 return (USBD_NORMAL_COMPLETION); 585 586 #if 0 587 bad2: 588 ehci_free_sqh(sc, sc->sc_async_head); 589 #endif 590 bad1: 591 usb_freemem(&sc->sc_dmatag, &sc->sc_fldma); 592 usb_dma_tag_finish(&sc->sc_dmatag); 593 return (err); 594 } 595 596 int 597 ehci_intr(void *v) 598 { 599 ehci_softc_t *sc = v; 600 601 if (sc == NULL || sc->sc_dying) 602 return (0); 603 604 /* If we get an interrupt while polling, then just ignore it. */ 605 if (sc->sc_bus.use_polling) { 606 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 607 608 if (intrs) 609 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 610 #ifdef DIAGNOSTIC 611 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 612 #endif 613 return (0); 614 } 615 616 return (ehci_intr1(sc)); 617 } 618 619 Static int 620 ehci_intr1(ehci_softc_t *sc) 621 { 622 u_int32_t intrs, eintrs; 623 624 DPRINTFN(20,("ehci_intr1: enter\n")); 625 626 /* In case the interrupt occurs before initialization has completed. */ 627 if (sc == NULL) { 628 #ifdef DIAGNOSTIC 629 printf("ehci_intr1: sc == NULL\n"); 630 #endif 631 return (0); 632 } 633 634 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 635 if (!intrs) 636 return (0); 637 638 eintrs = intrs & sc->sc_eintrs; 639 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 640 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 641 (u_int)eintrs)); 642 if (!eintrs) 643 return (0); 644 645 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 646 sc->sc_bus.intr_context++; 647 sc->sc_bus.no_intrs++; 648 if (eintrs & EHCI_STS_IAA) { 649 DPRINTF(("ehci_intr1: door bell\n")); 650 wakeup(&sc->sc_async_head); 651 eintrs &= ~EHCI_STS_IAA; 652 } 653 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 654 DPRINTFN(5,("ehci_intr1: %s %s\n", 655 eintrs & EHCI_STS_INT ? "INT" : "", 656 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 657 usb_schedsoftintr(&sc->sc_bus); 658 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 659 } 660 if (eintrs & EHCI_STS_HSE) { 661 printf("%s: unrecoverable error, controller halted\n", 662 USBDEVNAME(sc->sc_bus.bdev)); 663 /* XXX what else */ 664 } 665 if (eintrs & EHCI_STS_PCD) { 666 ehci_pcd(sc, sc->sc_intrxfer); 667 eintrs &= ~EHCI_STS_PCD; 668 } 669 670 sc->sc_bus.intr_context--; 671 672 if (eintrs != 0) { 673 /* Block unprocessed interrupts. */ 674 sc->sc_eintrs &= ~eintrs; 675 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 676 printf("%s: blocking intrs 0x%x\n", 677 USBDEVNAME(sc->sc_bus.bdev), eintrs); 678 } 679 680 return (1); 681 } 682 683 684 void 685 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 686 { 687 usbd_pipe_handle pipe; 688 u_char *p; 689 int i, m; 690 691 if (xfer == NULL) { 692 /* Just ignore the change. */ 693 return; 694 } 695 696 pipe = xfer->pipe; 697 698 p = xfer->hcbuffer; 699 m = min(sc->sc_noport, xfer->length * 8 - 1); 700 memset(p, 0, xfer->length); 701 for (i = 1; i <= m; i++) { 702 /* Pick out CHANGE bits from the status reg. */ 703 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 704 p[i/8] |= 1 << (i%8); 705 } 706 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 707 xfer->actlen = xfer->length; 708 xfer->status = USBD_NORMAL_COMPLETION; 709 710 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 711 } 712 713 void 714 ehci_softintr(void *v) 715 { 716 ehci_softc_t *sc = v; 717 struct ehci_xfer *ex, *nextex; 718 719 DPRINTFN(10,("%s: ehci_softintr (%d)\n", USBDEVNAME(sc->sc_bus.bdev), 720 sc->sc_bus.intr_context)); 721 722 sc->sc_bus.intr_context++; 723 724 /* 725 * The only explanation I can think of for why EHCI is as brain dead 726 * as UHCI interrupt-wise is that Intel was involved in both. 727 * An interrupt just tells us that something is done, we have no 728 * clue what, so we need to scan through all active transfers. :-( 729 */ 730 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 731 nextex = LIST_NEXT(ex, inext); 732 ehci_check_intr(sc, ex); 733 } 734 735 /* Schedule a callout to catch any dropped transactions. */ 736 if ((sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) && 737 !LIST_EMPTY(&sc->sc_intrhead)) 738 usb_callout(sc->sc_tmo_intrlist, hz / 5, ehci_intrlist_timeout, 739 sc); 740 741 /* Schedule a callout to catch any dropped transactions. */ 742 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 743 !LIST_EMPTY(&sc->sc_intrhead)) 744 usb_callout(sc->sc_tmo_intrlist, hz, 745 ehci_intrlist_timeout, sc); 746 747 #ifdef USB_USE_SOFTINTR 748 if (sc->sc_softwake) { 749 sc->sc_softwake = 0; 750 wakeup(&sc->sc_softwake); 751 } 752 #endif /* USB_USE_SOFTINTR */ 753 754 sc->sc_bus.intr_context--; 755 } 756 757 /* Check for an interrupt. */ 758 void 759 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 760 { 761 ehci_soft_qtd_t *sqtd, *lsqtd; 762 u_int32_t status; 763 764 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 765 766 if (ex->sqtdstart == NULL) { 767 printf("ehci_check_intr: sqtdstart=NULL\n"); 768 return; 769 } 770 lsqtd = ex->sqtdend; 771 #ifdef DIAGNOSTIC 772 if (lsqtd == NULL) { 773 printf("ehci_check_intr: lsqtd==0\n"); 774 return; 775 } 776 #endif 777 /* 778 * If the last TD is still active we need to check whether there 779 * is a an error somewhere in the middle, or whether there was a 780 * short packet (SPD and not ACTIVE). 781 */ 782 EHCI_SQTD_SYNC(sc, lsqtd, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 783 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 784 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 785 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 786 EHCI_SQTD_SYNC(sc, sqtd, 787 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 788 status = le32toh(sqtd->qtd.qtd_status); 789 /* If there's an active QTD the xfer isn't done. */ 790 if (status & EHCI_QTD_ACTIVE) 791 break; 792 /* Any kind of error makes the xfer done. */ 793 if (status & EHCI_QTD_HALTED) 794 goto done; 795 /* We want short packets, and it is short: it's done */ 796 if (EHCI_QTD_GET_BYTES(status) != 0) 797 goto done; 798 } 799 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 800 ex, ex->sqtdstart)); 801 return; 802 } 803 done: 804 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 805 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 806 usb_rem_task(ex->xfer.pipe->device, &ex->abort_task); 807 ehci_idone(ex); 808 } 809 810 void 811 ehci_idone(struct ehci_xfer *ex) 812 { 813 usbd_xfer_handle xfer = &ex->xfer; 814 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 815 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 816 ehci_soft_qtd_t *sqtd, *lsqtd; 817 u_int32_t status = 0, nstatus = 0; 818 ehci_physaddr_t nextphys, altnextphys; 819 ehci_physaddr_t stdma; 820 int actlen, cerr; 821 822 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 823 #ifdef DIAGNOSTIC 824 { 825 int s = splhigh(); 826 if (ex->isdone) { 827 splx(s); 828 #ifdef EHCI_DEBUG 829 printf("ehci_idone: ex is done!\n "); 830 ehci_dump_exfer(ex); 831 #else 832 printf("ehci_idone: ex=%p is done!\n", ex); 833 #endif 834 return; 835 } 836 ex->isdone = 1; 837 splx(s); 838 } 839 #endif 840 841 if (xfer->status == USBD_CANCELLED || 842 xfer->status == USBD_TIMEOUT) { 843 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 844 return; 845 } 846 847 #ifdef EHCI_DEBUG 848 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 849 if (ehcidebug > 10) 850 ehci_dump_sqtds(ex->sqtdstart); 851 #endif 852 853 /* 854 * Make sure that the QH overlay qTD does not reference any 855 * of the qTDs we are about to free. This is probably only 856 * necessary if the transfer is marked as HALTED. 857 */ 858 EHCI_SQH_SYNC(sc, epipe->sqh, 859 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 860 nextphys = EHCI_LINK_ADDR(le32toh(epipe->sqh->qh.qh_qtd.qtd_next)); 861 altnextphys = 862 EHCI_LINK_ADDR(le32toh(epipe->sqh->qh.qh_qtd.qtd_altnext)); 863 for (sqtd = ex->sqtdstart; sqtd != ex->sqtdend->nextqtd; 864 sqtd = sqtd->nextqtd) { 865 stdma = EHCI_SQTD_DMAADDR(sqtd); 866 if (stdma == nextphys) { 867 epipe->sqh->qh.qh_qtd.qtd_next = 868 htole32(EHCI_SQTD_DMAADDR(ex->sqtdend->nextqtd)); 869 DPRINTFN(4, ("ehci_idone: updated overlay next ptr\n")); 870 EHCI_SQH_SYNC(sc, epipe->sqh, 871 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 872 873 } 874 if (stdma == altnextphys) { 875 DPRINTFN(4, 876 ("ehci_idone: updated overlay altnext ptr\n")); 877 epipe->sqh->qh.qh_qtd.qtd_altnext = 878 htole32(EHCI_SQTD_DMAADDR(ex->sqtdend->nextqtd)); 879 EHCI_SQH_SYNC(sc, epipe->sqh, 880 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 881 } 882 } 883 884 /* The transfer is done, compute actual length and status. */ 885 lsqtd = ex->sqtdend; 886 actlen = 0; 887 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd=sqtd->nextqtd) { 888 EHCI_SQTD_SYNC(sc, sqtd, 889 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 890 nstatus = le32toh(sqtd->qtd.qtd_status); 891 if (nstatus & EHCI_QTD_ACTIVE) 892 break; 893 894 status = nstatus; 895 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 896 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 897 } 898 899 cerr = EHCI_QTD_GET_CERR(status); 900 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, " 901 "status=0x%x\n", xfer->length, actlen, cerr, status)); 902 xfer->actlen = actlen; 903 if ((status & EHCI_QTD_HALTED) != 0) { 904 #ifdef EHCI_DEBUG 905 char sbuf[128]; 906 907 bitmask_snprintf((u_int32_t)status, 908 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 909 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 910 911 DPRINTFN(2, 912 ("ehci_idone: error, addr=%d, endpt=0x%02x, " 913 "status 0x%s\n", 914 xfer->pipe->device->address, 915 xfer->pipe->endpoint->edesc->bEndpointAddress, 916 sbuf)); 917 if (ehcidebug > 2) { 918 ehci_dump_sqh(epipe->sqh); 919 ehci_dump_sqtds(ex->sqtdstart); 920 } 921 #endif 922 /* low&full speed has an extra error flag */ 923 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 924 EHCI_QH_SPEED_HIGH) 925 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 926 else 927 status &= EHCI_QTD_STATERRS; 928 if (status == 0) /* no other errors means a stall */ 929 xfer->status = USBD_STALLED; 930 else 931 xfer->status = USBD_IOERROR; /* more info XXX */ 932 /* XXX need to reset TT on missed microframe */ 933 if (status & EHCI_QTD_MISSEDMICRO) { 934 printf("%s: missed microframe, TT reset not " 935 "implemented, hub might be inoperational\n", 936 USBDEVNAME(sc->sc_bus.bdev)); 937 } 938 } else { 939 xfer->status = USBD_NORMAL_COMPLETION; 940 } 941 942 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 943 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 944 } 945 946 /* 947 * Wait here until controller claims to have an interrupt. 948 * Then call ehci_intr and return. Use timeout to avoid waiting 949 * too long. 950 */ 951 void 952 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 953 { 954 int timo; 955 u_int32_t intrs; 956 957 xfer->status = USBD_IN_PROGRESS; 958 for (timo = xfer->timeout; timo >= 0; timo--) { 959 usb_delay_ms(&sc->sc_bus, 1); 960 if (sc->sc_dying) 961 break; 962 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 963 sc->sc_eintrs; 964 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 965 #ifdef EHCI_DEBUG 966 if (ehcidebug > 15) 967 ehci_dump_regs(sc); 968 #endif 969 if (intrs) { 970 ehci_intr1(sc); 971 if (xfer->status != USBD_IN_PROGRESS) 972 return; 973 } 974 } 975 976 /* Timeout */ 977 DPRINTF(("ehci_waitintr: timeout\n")); 978 xfer->status = USBD_TIMEOUT; 979 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 980 /* XXX should free TD */ 981 } 982 983 void 984 ehci_poll(struct usbd_bus *bus) 985 { 986 ehci_softc_t *sc = (ehci_softc_t *)bus; 987 #ifdef EHCI_DEBUG 988 static int last; 989 int new; 990 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 991 if (new != last) { 992 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 993 last = new; 994 } 995 #endif 996 997 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 998 ehci_intr1(sc); 999 } 1000 1001 int 1002 ehci_detach(struct ehci_softc *sc, int flags) 1003 { 1004 int rv = 0; 1005 usbd_xfer_handle xfer; 1006 1007 #if defined(__NetBSD__) || defined(__OpenBSD__) 1008 if (sc->sc_child != NULL) 1009 rv = config_detach(sc->sc_child, flags); 1010 1011 if (rv != 0) 1012 return (rv); 1013 #else 1014 sc->sc_dying = 1; 1015 #endif 1016 1017 if (sc->sc_bus.methods == NULL) 1018 return (rv); /* attach has been aborted */ 1019 1020 #if defined(__NetBSD__) || defined(__OpenBSD__) 1021 /* Don't touch hardware if it has already been gone. */ 1022 if ((flags & DETACH_FORCE) == 0) 1023 #endif 1024 { 1025 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1026 EOWRITE4(sc, EHCI_USBCMD, 0); 1027 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1028 } 1029 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 1030 1031 #if defined(__NetBSD__) || defined(__OpenBSD__) 1032 if (sc->sc_powerhook != NULL) 1033 powerhook_disestablish(sc->sc_powerhook); 1034 if (sc->sc_shutdownhook != NULL) 1035 shutdownhook_disestablish(sc->sc_shutdownhook); 1036 #endif 1037 1038 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1039 1040 usb_freemem(&sc->sc_dmatag, &sc->sc_fldma); 1041 /* XXX free other data structures XXX */ 1042 1043 while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 1044 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1045 usb_clean_buffer_dma(&sc->sc_dmatag, &EXFER(xfer)->dmabuf); 1046 free(xfer, M_USB); 1047 } 1048 ehci_free_desc_chunks(sc, &sc->sc_sqh_chunks); 1049 ehci_free_desc_chunks(sc, &sc->sc_sqtd_chunks); 1050 usb_dma_tag_finish(&sc->sc_dmatag); 1051 1052 return (rv); 1053 } 1054 1055 Static void 1056 ehci_free_desc_chunks(ehci_softc_t *sc, struct ehci_mdescs *c) 1057 { 1058 struct ehci_mem_desc *em; 1059 1060 while ((em = SIMPLEQ_FIRST(c)) != NULL) { 1061 SIMPLEQ_REMOVE_HEAD(c, em_next); 1062 usb_freemem(&sc->sc_dmatag, &em->em_dma); 1063 } 1064 } 1065 1066 #if defined(__NetBSD__) || defined(__OpenBSD__) 1067 int 1068 ehci_activate(device_t self, enum devact act) 1069 { 1070 struct ehci_softc *sc = (struct ehci_softc *)self; 1071 int rv = 0; 1072 1073 switch (act) { 1074 case DVACT_ACTIVATE: 1075 return (EOPNOTSUPP); 1076 1077 case DVACT_DEACTIVATE: 1078 if (sc->sc_child != NULL) 1079 rv = config_deactivate(sc->sc_child); 1080 sc->sc_dying = 1; 1081 break; 1082 } 1083 return (rv); 1084 } 1085 #endif 1086 1087 /* 1088 * Handle suspend/resume. 1089 * 1090 * We need to switch to polling mode here, because this routine is 1091 * called from an interrupt context. This is all right since we 1092 * are almost suspended anyway. 1093 */ 1094 void 1095 ehci_power(int why, void *v) 1096 { 1097 ehci_softc_t *sc = v; 1098 u_int32_t cmd, hcr; 1099 int s, i; 1100 1101 #ifdef EHCI_DEBUG 1102 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why)); 1103 if (ehcidebug > 0) 1104 ehci_dump_regs(sc); 1105 #endif 1106 1107 s = splhardusb(); 1108 switch (why) { 1109 USB_PWR_CASE_SUSPEND: 1110 sc->sc_bus.use_polling++; 1111 1112 for (i = 1; i <= sc->sc_noport; i++) { 1113 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1114 if ((cmd & EHCI_PS_PO) == 0 && 1115 (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1116 EOWRITE4(sc, EHCI_PORTSC(i), 1117 cmd | EHCI_PS_SUSP); 1118 } 1119 1120 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1121 1122 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1123 EOWRITE4(sc, EHCI_USBCMD, cmd); 1124 1125 for (i = 0; i < 100; i++) { 1126 hcr = EOREAD4(sc, EHCI_USBSTS) & 1127 (EHCI_STS_ASS | EHCI_STS_PSS); 1128 if (hcr == 0) 1129 break; 1130 1131 usb_delay_ms(&sc->sc_bus, 1); 1132 } 1133 if (hcr != 0) { 1134 printf("%s: reset timeout\n", 1135 USBDEVNAME(sc->sc_bus.bdev)); 1136 } 1137 1138 cmd &= ~EHCI_CMD_RS; 1139 EOWRITE4(sc, EHCI_USBCMD, cmd); 1140 1141 for (i = 0; i < 100; i++) { 1142 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1143 if (hcr == EHCI_STS_HCH) 1144 break; 1145 1146 usb_delay_ms(&sc->sc_bus, 1); 1147 } 1148 if (hcr != EHCI_STS_HCH) { 1149 printf("%s: config timeout\n", 1150 USBDEVNAME(sc->sc_bus.bdev)); 1151 } 1152 1153 sc->sc_bus.use_polling--; 1154 break; 1155 1156 USB_PWR_CASE_RESUME: 1157 sc->sc_bus.use_polling++; 1158 1159 /* restore things in case the bios sucks */ 1160 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1161 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1162 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1163 EHCI_SQH_DMAADDR(sc->sc_async_head) | EHCI_LINK_QH); 1164 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1165 1166 hcr = 0; 1167 for (i = 1; i <= sc->sc_noport; i++) { 1168 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1169 if ((cmd & EHCI_PS_PO) == 0 && 1170 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1171 EOWRITE4(sc, EHCI_PORTSC(i), 1172 cmd | EHCI_PS_FPR); 1173 hcr = 1; 1174 } 1175 } 1176 1177 if (hcr) { 1178 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1179 1180 for (i = 1; i <= sc->sc_noport; i++) { 1181 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1182 if ((cmd & EHCI_PS_PO) == 0 && 1183 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1184 EOWRITE4(sc, EHCI_PORTSC(i), 1185 cmd & ~EHCI_PS_FPR); 1186 } 1187 } 1188 1189 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1190 1191 for (i = 0; i < 100; i++) { 1192 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1193 if (hcr != EHCI_STS_HCH) 1194 break; 1195 1196 usb_delay_ms(&sc->sc_bus, 1); 1197 } 1198 if (hcr == EHCI_STS_HCH) { 1199 printf("%s: config timeout\n", 1200 USBDEVNAME(sc->sc_bus.bdev)); 1201 } 1202 1203 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1204 1205 sc->sc_bus.use_polling--; 1206 break; 1207 1208 default: 1209 break; 1210 } 1211 splx(s); 1212 1213 #ifdef EHCI_DEBUG 1214 DPRINTF(("ehci_power: sc=%p\n", sc)); 1215 if (ehcidebug > 0) 1216 ehci_dump_regs(sc); 1217 #endif 1218 } 1219 1220 /* 1221 * Shut down the controller when the system is going down. 1222 */ 1223 void 1224 ehci_shutdown(void *v) 1225 { 1226 ehci_softc_t *sc = v; 1227 1228 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1229 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1230 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1231 } 1232 1233 /* 1234 * Allocate a physically contiguous buffer to handle cases where EHCI 1235 * cannot handle a packet because it is not physically contiguous. 1236 */ 1237 Static void 1238 ehci_aux_mem_init(struct ehci_aux_mem *aux) 1239 { 1240 1241 aux->aux_curchunk = aux->aux_chunkoff = aux->aux_naux = 0; 1242 } 1243 1244 Static usbd_status 1245 ehci_aux_mem_alloc(ehci_softc_t *sc, struct ehci_aux_mem *aux, 1246 int naux, int maxp) 1247 { 1248 int nchunk, i, j; 1249 usbd_status err; 1250 1251 USB_KASSERT(aux->aux_nchunk == 0); 1252 1253 nchunk = EHCI_NCHUNK(naux, maxp); 1254 for (i = 0; i < nchunk; i++) { 1255 err = usb_allocmem(&sc->sc_dmatag, EHCI_AUX_CHUNK_SIZE, 1256 EHCI_AUX_CHUNK_SIZE, &aux->aux_chunk_dma[i]); 1257 if (err) { 1258 for (j = 0; j < i; j++) 1259 usb_freemem(&sc->sc_dmatag, 1260 &aux->aux_chunk_dma[j]); 1261 return (err); 1262 } 1263 } 1264 1265 aux->aux_nchunk = nchunk; 1266 ehci_aux_mem_init(aux); 1267 1268 return (USBD_NORMAL_COMPLETION); 1269 } 1270 1271 Static void 1272 ehci_aux_mem_free(ehci_softc_t *sc, struct ehci_aux_mem *aux) 1273 { 1274 int i; 1275 1276 /* sync last aux (just in case, probably a no-op) */ 1277 if (aux->aux_naux) 1278 ehci_aux_dma_sync(sc, aux, BUS_DMASYNC_POSTWRITE); 1279 1280 for (i = 0; i < aux->aux_nchunk; i++) 1281 usb_freemem(&sc->sc_dmatag, &aux->aux_chunk_dma[i]); 1282 1283 aux->aux_nchunk = 0; 1284 } 1285 1286 Static bus_addr_t 1287 ehci_aux_dma_alloc(struct ehci_aux_mem *aux, int len, struct aux_desc *ad) 1288 { 1289 bus_addr_t auxdma; 1290 1291 if (aux->aux_chunkoff + len > EHCI_AUX_CHUNK_SIZE) { 1292 aux->aux_curchunk++; 1293 aux->aux_chunkoff = 0; 1294 } 1295 USB_KASSERT(aux->aux_curchunk < aux->aux_nchunk); 1296 1297 auxdma = 1298 DMAADDR(&aux->aux_chunk_dma[aux->aux_curchunk], aux->aux_chunkoff); 1299 ad->aux_kern = 1300 KERNADDR(&aux->aux_chunk_dma[aux->aux_curchunk], aux->aux_chunkoff); 1301 1302 aux->aux_chunkoff += len; 1303 aux->aux_naux++; 1304 1305 return auxdma; 1306 } 1307 1308 Static void 1309 ehci_aux_dma_sync(ehci_softc_t *sc, struct ehci_aux_mem *aux, int op) 1310 { 1311 int i; 1312 1313 for (i = 0; i < aux->aux_curchunk; i++) 1314 USB_MEM_SYNC(&sc->sc_dmatag, &aux->aux_chunk_dma[i], op); 1315 if (aux->aux_chunkoff) 1316 USB_MEM_SYNC2(&sc->sc_dmatag, &aux->aux_chunk_dma[i], 1317 0, aux->aux_chunkoff, op); 1318 } 1319 1320 Static usbd_status 1321 ehci_prealloc(struct ehci_softc *sc, struct ehci_xfer *exfer, 1322 size_t bufsize, int nseg) 1323 { 1324 usb_endpoint_descriptor_t *endpt; 1325 int maxseg, mps, naux; 1326 int seglen, ntd; 1327 int s; 1328 int err; 1329 1330 endpt = exfer->xfer.pipe->endpoint->edesc; 1331 mps = UE_MAXPKTSZ(endpt); 1332 1333 if (mps == 0) 1334 return (USBD_INVAL); 1335 1336 /* (over) estimate needed number of TDs */ 1337 maxseg = EHCI_PAGE_SIZE * EHCI_QTD_NBUFFERS; 1338 seglen = maxseg - (maxseg % mps); 1339 ntd = bufsize / seglen + nseg; 1340 1341 /* allocate aux buffer for non-isoc OUT transfer */ 1342 naux = 0; 1343 if (nseg > 1 && 1344 (endpt->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS && 1345 UE_GET_DIR(endpt->bEndpointAddress) == UE_DIR_OUT) { 1346 /* estimate needed aux segments */ 1347 naux = nseg - 1; 1348 1349 /* pre-allocate aux memory */ 1350 err = ehci_aux_mem_alloc(sc, &exfer->aux, naux, mps); 1351 if (err) 1352 return err; 1353 1354 /* an aux segment will consume a TD */ 1355 ntd += naux; 1356 } 1357 1358 s = splusb(); 1359 /* pre-allocate QDs */ 1360 /* XXX ITDs */ 1361 while (sc->sc_nfreeqtds < ntd) { 1362 DPRINTF(("%s: qhci_prealloc: need %d QTD (%d cur)\n", 1363 USBDEVNAME(sc->sc_bus.bdev), ntd, sc->sc_nfreeqtds)); 1364 if ((err = ehci_grow_sqtd(sc)) != USBD_NORMAL_COMPLETION) { 1365 splx(s); 1366 ehci_aux_mem_free(sc, &exfer->aux); 1367 return err; 1368 } 1369 } 1370 sc->sc_nfreeqtds -= ntd; 1371 splx(s); 1372 1373 exfer->rsvd_tds = ntd; 1374 1375 return USBD_NORMAL_COMPLETION; 1376 } 1377 1378 usbd_status 1379 ehci_allocm(struct usbd_bus *bus, usbd_xfer_handle xfer, void *buf, size_t size) 1380 { 1381 struct ehci_softc *sc = (struct ehci_softc *)bus; 1382 struct ehci_xfer *exfer = EXFER(xfer); 1383 usbd_status err; 1384 1385 if ((err = usb_alloc_buffer_dma(&sc->sc_dmatag, &exfer->dmabuf, 1386 buf, size, &xfer->hcbuffer)) == USBD_NORMAL_COMPLETION) { 1387 if ((xfer->rqflags & URQ_DEV_MAP_PREPARED) == 0 && 1388 (err = ehci_prealloc(sc, exfer, size, 1389 USB_BUFFER_NSEGS(&exfer->dmabuf))) 1390 != USBD_NORMAL_COMPLETION) { 1391 usb_free_buffer_dma(&sc->sc_dmatag, &exfer->dmabuf, 1392 U_WAITOK); 1393 } 1394 } 1395 #ifdef EHCI_DEBUG 1396 if (err) 1397 printf("ehci_allocm: usb_alloc_buffer_dma()=%d\n", err); 1398 #endif 1399 return (err); 1400 } 1401 1402 void 1403 ehci_freem(struct usbd_bus *bus, usbd_xfer_handle xfer, 1404 enum usbd_waitflg waitflg) 1405 { 1406 struct ehci_softc *sc = (struct ehci_softc *)bus; 1407 struct ehci_xfer *exfer = EXFER(xfer); 1408 int s; 1409 1410 usb_free_buffer_dma(&sc->sc_dmatag, &exfer->dmabuf, waitflg); 1411 1412 if ((xfer->rqflags & URQ_DEV_MAP_PREPARED) == 0) { 1413 /* XXX ITDs */ 1414 1415 s = splusb(); 1416 sc->sc_nfreeqtds += exfer->rsvd_tds; 1417 splx(s); 1418 exfer->rsvd_tds = 0; 1419 ehci_aux_mem_free(sc, &exfer->aux); 1420 } 1421 } 1422 1423 Static usbd_status 1424 ehci_map_alloc(usbd_xfer_handle xfer) 1425 { 1426 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1427 struct ehci_xfer *exfer = EXFER(xfer); 1428 usbd_status st; 1429 1430 st = usb_alloc_dma_resources(&sc->sc_dmatag, &exfer->dmabuf); 1431 if (st) 1432 return st; 1433 1434 if ((st = ehci_prealloc(sc, exfer, MAXPHYS, USB_DMA_NSEG))) { 1435 usb_free_dma_resources(&sc->sc_dmatag, &exfer->dmabuf); 1436 } 1437 1438 return st; 1439 } 1440 1441 Static void 1442 ehci_map_free(usbd_xfer_handle xfer) 1443 { 1444 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1445 struct ehci_xfer *exfer = EXFER(xfer); 1446 int s; 1447 1448 USB_KASSERT(xfer->rqflags & URQ_DEV_MAP_PREPARED); 1449 1450 usb_free_dma_resources(&sc->sc_dmatag, &exfer->dmabuf); 1451 1452 /* XXX ITDs */ 1453 1454 s = splusb(); 1455 sc->sc_nfreeqtds += exfer->rsvd_tds; 1456 splx(s); 1457 exfer->rsvd_tds = 0; 1458 ehci_aux_mem_free(sc, &exfer->aux); 1459 } 1460 1461 Static void 1462 ehci_mapm(usbd_xfer_handle xfer, void *buf, size_t size) 1463 { 1464 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1465 struct ehci_xfer *exfer = EXFER(xfer); 1466 1467 usb_map_dma(&sc->sc_dmatag, &exfer->dmabuf, buf, size); 1468 } 1469 1470 Static usbd_status 1471 ehci_mapm_mbuf(usbd_xfer_handle xfer, struct mbuf *chain) 1472 { 1473 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1474 struct ehci_xfer *exfer = EXFER(xfer); 1475 1476 return (usb_map_mbuf_dma(&sc->sc_dmatag, &exfer->dmabuf, chain)); 1477 } 1478 1479 Static void 1480 ehci_unmapm(usbd_xfer_handle xfer) 1481 { 1482 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1483 struct ehci_xfer *exfer = EXFER(xfer); 1484 1485 usb_unmap_dma(&sc->sc_dmatag, &exfer->dmabuf); 1486 } 1487 1488 usbd_xfer_handle 1489 ehci_allocx(struct usbd_bus *bus, usbd_pipe_handle pipe, 1490 enum usbd_waitflg waitflg) 1491 { 1492 struct ehci_softc *sc = (struct ehci_softc *)bus; 1493 usbd_xfer_handle xfer; 1494 1495 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1496 if (xfer != NULL) { 1497 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1498 #ifdef DIAGNOSTIC 1499 if (xfer->busy_free != XFER_FREE) { 1500 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1501 xfer->busy_free); 1502 } 1503 #endif 1504 } else { 1505 xfer = malloc(sizeof(struct ehci_xfer), M_USB, 1506 waitflg == U_WAITOK ? M_WAITOK : M_NOWAIT); 1507 } 1508 if (xfer != NULL) { 1509 memset(xfer, 0, sizeof(struct ehci_xfer)); 1510 usb_init_task(&EXFER(xfer)->abort_task, ehci_timeout_task, 1511 xfer); 1512 EXFER(xfer)->ehci_xfer_flags = 0; 1513 EXFER(xfer)->rsvd_tds = 0; 1514 #ifdef DIAGNOSTIC 1515 EXFER(xfer)->isdone = 1; 1516 xfer->busy_free = XFER_BUSY; 1517 #endif 1518 } 1519 return (xfer); 1520 } 1521 1522 void 1523 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1524 { 1525 struct ehci_softc *sc = (struct ehci_softc *)bus; 1526 1527 #ifdef DIAGNOSTIC 1528 if (xfer->busy_free != XFER_BUSY) { 1529 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1530 xfer->busy_free); 1531 } 1532 xfer->busy_free = XFER_FREE; 1533 if (!EXFER(xfer)->isdone) { 1534 printf("ehci_freex: !isdone\n"); 1535 } 1536 #endif 1537 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1538 } 1539 1540 Static void 1541 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1542 { 1543 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1544 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 1545 1546 EHCI_SQH_SYNC(sc, epipe->sqh, 1547 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1548 1549 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1550 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1551 #ifdef USB_DEBUG 1552 if (ehcidebug) 1553 usbd_dump_pipe(pipe); 1554 #endif 1555 USB_KASSERT2((epipe->sqh->qh.qh_qtd.qtd_status & 1556 htole32(EHCI_QTD_ACTIVE)) == 0, 1557 ("ehci_device_clear_toggle: queue active")); 1558 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK); 1559 EHCI_SQH_SYNC(sc, epipe->sqh, 1560 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1561 } 1562 1563 Static void 1564 ehci_noop(usbd_pipe_handle pipe) 1565 { 1566 } 1567 1568 #ifdef EHCI_DEBUG 1569 void 1570 ehci_dump_regs(ehci_softc_t *sc) 1571 { 1572 int i; 1573 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1574 EOREAD4(sc, EHCI_USBCMD), 1575 EOREAD4(sc, EHCI_USBSTS), 1576 EOREAD4(sc, EHCI_USBINTR)); 1577 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1578 EOREAD4(sc, EHCI_FRINDEX), 1579 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1580 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1581 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1582 for (i = 1; i <= sc->sc_noport; i++) 1583 printf("port %d status=0x%08x\n", i, 1584 EOREAD4(sc, EHCI_PORTSC(i))); 1585 } 1586 1587 /* 1588 * Unused function - this is meant to be called from a kernel 1589 * debugger. 1590 */ 1591 void 1592 ehci_dump() 1593 { 1594 ehci_dump_regs(theehci); 1595 } 1596 1597 void 1598 ehci_dump_link(ehci_link_t link, int type) 1599 { 1600 link = le32toh(link); 1601 printf("0x%08x", link); 1602 if (link & EHCI_LINK_TERMINATE) 1603 printf("<T>"); 1604 else { 1605 printf("<"); 1606 if (type) { 1607 switch (EHCI_LINK_TYPE(link)) { 1608 case EHCI_LINK_ITD: printf("ITD"); break; 1609 case EHCI_LINK_QH: printf("QH"); break; 1610 case EHCI_LINK_SITD: printf("SITD"); break; 1611 case EHCI_LINK_FSTN: printf("FSTN"); break; 1612 } 1613 } 1614 printf(">"); 1615 } 1616 } 1617 1618 void 1619 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1620 { 1621 int i; 1622 u_int32_t stop; 1623 1624 stop = 0; 1625 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1626 ehci_dump_sqtd(sqtd); 1627 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1628 } 1629 if (sqtd) 1630 printf("dump aborted, too many TDs\n"); 1631 } 1632 1633 void 1634 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1635 { 1636 printf("QTD(%p) at 0x%08x:\n", sqtd, EHCI_SQTD_DMAADDR(sqtd)); 1637 ehci_dump_qtd(&sqtd->qtd); 1638 } 1639 1640 void 1641 ehci_dump_qtd(ehci_qtd_t *qtd) 1642 { 1643 u_int32_t s; 1644 char sbuf[128]; 1645 1646 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1647 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1648 printf("\n"); 1649 s = le32toh(qtd->qtd_status); 1650 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1651 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1652 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1653 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1654 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1655 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1656 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1657 EHCI_QTD_GET_PID(s), sbuf); 1658 for (s = 0; s < 5; s++) 1659 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1660 } 1661 1662 void 1663 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1664 { 1665 ehci_qh_t *qh = &sqh->qh; 1666 u_int32_t endp, endphub; 1667 1668 printf("QH(%p) at 0x%08x:\n", sqh, EHCI_SQH_DMAADDR(sqh)); 1669 printf(" sqtd=%p inactivesqtd=%p\n", sqh->sqtd, sqh->inactivesqtd); 1670 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1671 endp = le32toh(qh->qh_endp); 1672 printf(" endp=0x%08x\n", endp); 1673 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1674 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1675 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1676 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1677 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1678 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1679 EHCI_QH_GET_NRL(endp)); 1680 endphub = le32toh(qh->qh_endphub); 1681 printf(" endphub=0x%08x\n", endphub); 1682 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1683 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1684 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1685 EHCI_QH_GET_MULT(endphub)); 1686 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1687 printf("Overlay qTD:\n"); 1688 ehci_dump_qtd(&qh->qh_qtd); 1689 } 1690 1691 #ifdef DIAGNOSTIC 1692 Static void 1693 ehci_dump_exfer(struct ehci_xfer *ex) 1694 { 1695 printf("ehci_dump_exfer: ex=%p\n", ex); 1696 } 1697 #endif 1698 #endif 1699 1700 usbd_status 1701 ehci_open(usbd_pipe_handle pipe) 1702 { 1703 usbd_device_handle dev = pipe->device; 1704 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 1705 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1706 u_int8_t addr = dev->address; 1707 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1708 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1709 ehci_soft_qh_t *sqh; 1710 usbd_status err; 1711 int s; 1712 int ival, speed, naks; 1713 int hshubaddr, hshubport; 1714 1715 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1716 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1717 1718 if (dev->myhsport) { 1719 hshubaddr = dev->myhsport->parent->address; 1720 hshubport = dev->myhsport->portno; 1721 } else { 1722 hshubaddr = 0; 1723 hshubport = 0; 1724 } 1725 1726 if (sc->sc_dying) 1727 return (USBD_IOERROR); 1728 1729 if (addr == sc->sc_addr) { 1730 switch (ed->bEndpointAddress) { 1731 case USB_CONTROL_ENDPOINT: 1732 pipe->methods = &ehci_root_ctrl_methods; 1733 break; 1734 case UE_DIR_IN | EHCI_INTR_ENDPT: 1735 pipe->methods = &ehci_root_intr_methods; 1736 break; 1737 default: 1738 return (USBD_INVAL); 1739 } 1740 return (USBD_NORMAL_COMPLETION); 1741 } 1742 1743 /* XXX All this stuff is only valid for async. */ 1744 switch (dev->speed) { 1745 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1746 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1747 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1748 default: panic("ehci_open: bad device speed %d", dev->speed); 1749 } 1750 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1751 printf("%s: *** WARNING: opening low/full speed isoc device, " 1752 "this does not work yet.\n", 1753 USBDEVNAME(sc->sc_bus.bdev)); 1754 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1755 hshubaddr, hshubport)); 1756 return USBD_INVAL; 1757 } 1758 1759 naks = 8; /* XXX */ 1760 sqh = ehci_alloc_sqh(sc); 1761 if (sqh == NULL) 1762 return (USBD_NOMEM); 1763 /* qh_link filled when the QH is added */ 1764 sqh->qh.qh_endp = htole32( 1765 EHCI_QH_SET_ADDR(addr) | 1766 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1767 EHCI_QH_SET_EPS(speed) | 1768 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) | 1769 EHCI_QH_SET_MPL(UE_MAXPKTSZ(ed)) | 1770 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1771 EHCI_QH_CTL : 0) | 1772 EHCI_QH_SET_NRL(naks) 1773 ); 1774 sqh->qh.qh_endphub = htole32( 1775 EHCI_QH_SET_MULT(1) | 1776 EHCI_QH_SET_HUBA(hshubaddr) | 1777 EHCI_QH_SET_PORT(hshubport) | 1778 EHCI_QH_SET_CMASK(0x1c) | 1779 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0) 1780 ); 1781 sqh->qh.qh_curqtd = EHCI_NULL; 1782 /* The overlay qTD was already set up by ehci_alloc_sqh(). */ 1783 sqh->qh.qh_qtd.qtd_status = 1784 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle)); 1785 1786 epipe->sqh = sqh; 1787 1788 switch (xfertype) { 1789 case UE_CONTROL: 1790 err = usb_allocmem(&sc->sc_dmatag, sizeof(usb_device_request_t), 1791 0, &epipe->u.ctl.reqdma); 1792 #ifdef EHCI_DEBUG 1793 if (err) 1794 printf("ehci_open: usb_allocmem()=%d\n", err); 1795 #endif 1796 if (err) 1797 goto bad; 1798 pipe->methods = &ehci_device_ctrl_methods; 1799 s = splusb(); 1800 ehci_add_qh(sc, sqh, sc->sc_async_head); 1801 splx(s); 1802 break; 1803 case UE_BULK: 1804 pipe->methods = &ehci_device_bulk_methods; 1805 s = splusb(); 1806 ehci_add_qh(sc, sqh, sc->sc_async_head); 1807 splx(s); 1808 break; 1809 case UE_INTERRUPT: 1810 pipe->methods = &ehci_device_intr_methods; 1811 ival = pipe->interval; 1812 if (ival == USBD_DEFAULT_INTERVAL) { 1813 if (speed == EHCI_QH_SPEED_HIGH) { 1814 if (ed->bInterval > 16) { 1815 /* 1816 * illegal with high-speed, but there 1817 * were documentation bugs in the spec, 1818 * so be generous 1819 */ 1820 ival = 256; 1821 } else 1822 ival = (1 << (ed->bInterval - 1)) / 8; 1823 } else 1824 ival = ed->bInterval; 1825 } 1826 err = ehci_device_setintr(sc, sqh, ival); 1827 if (err) 1828 goto bad; 1829 break; 1830 case UE_ISOCHRONOUS: 1831 pipe->methods = &ehci_device_isoc_methods; 1832 /* FALLTHROUGH */ 1833 default: 1834 err = USBD_INVAL; 1835 goto bad; 1836 } 1837 return (USBD_NORMAL_COMPLETION); 1838 1839 bad: 1840 ehci_free_sqh(sc, sqh); 1841 return (err); 1842 } 1843 1844 /* 1845 * Add an ED to the schedule. Called at splusb(). 1846 * If in the async schedule, it will always have a next. 1847 * If in the intr schedule it may not. 1848 */ 1849 void 1850 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1851 { 1852 SPLUSBCHECK; 1853 1854 sqh->next = head->next; 1855 sqh->prev = head; 1856 sqh->qh.qh_link = head->qh.qh_link; 1857 EHCI_SQH_SYNC(sc, sqh, 1858 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1859 head->next = sqh; 1860 if (sqh->next) 1861 sqh->next->prev = sqh; 1862 head->qh.qh_link = htole32(EHCI_SQH_DMAADDR(sqh) | EHCI_LINK_QH); 1863 EHCI_SQH_SYNC(sc, head, 1864 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1865 1866 #ifdef EHCI_DEBUG 1867 if (ehcidebug > 5) { 1868 printf("ehci_add_qh:\n"); 1869 ehci_dump_sqh(sqh); 1870 } 1871 #endif 1872 } 1873 1874 /* 1875 * Remove an ED from the schedule. Called at splusb(). 1876 * Will always have a 'next' if it's in the async list as it's circular. 1877 */ 1878 void 1879 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1880 { 1881 SPLUSBCHECK; 1882 /* XXX */ 1883 sqh->prev->qh.qh_link = sqh->qh.qh_link; 1884 EHCI_SQH_SYNC(sc, sqh->prev, 1885 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1886 sqh->prev->next = sqh->next; 1887 if (sqh->next) 1888 sqh->next->prev = sqh->prev; 1889 ehci_sync_hc(sc); 1890 } 1891 1892 /* Restart a QH following the addition of a qTD. */ 1893 void 1894 ehci_activate_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1895 { 1896 ehci_physaddr_t qtddma; 1897 1898 EHCI_SQTD_SYNC(sc, sqtd, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1899 1900 USB_KASSERT2((sqtd->qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) == 0, 1901 ("ehci_activate_qh: already active")); 1902 1903 /* 1904 * When a QH is idle, the overlay qTD should be marked as not 1905 * halted and not active. This causes the host controller to 1906 * retrieve the real qTD on each pass (rather than just examinig 1907 * the overlay), so it will notice when we activate the qTD. 1908 */ 1909 if (sqtd == sqh->sqtd) { 1910 /* Check that the hardware is in the state we expect. */ 1911 qtddma = EHCI_SQTD_DMAADDR(sqtd); 1912 if (EHCI_LINK_ADDR(le32toh(sqh->qh.qh_qtd.qtd_next)) != 1913 qtddma) { 1914 #ifdef EHCI_DEBUG 1915 printf("ehci_activate_qh: unexpected next ptr\n"); 1916 ehci_dump_sqh(sqh); 1917 ehci_dump_sqtds(sqh->sqtd); 1918 #endif 1919 sqh->qh.qh_qtd.qtd_next = htole32(qtddma); 1920 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1921 } 1922 /* Ensure the flags are correct. */ 1923 sqh->qh.qh_qtd.qtd_status &= htole32(EHCI_QTD_PINGSTATE | 1924 EHCI_QTD_TOGGLE_MASK); 1925 EHCI_SQH_SYNC(sc, sqh, 1926 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1927 } 1928 1929 /* Now activate the qTD. */ 1930 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_ACTIVE); 1931 EHCI_SQTD_SYNC(sc, sqtd, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1932 } 1933 1934 /* 1935 * Ensure that the HC has released all references to the QH. We do this 1936 * by asking for a Async Advance Doorbell interrupt and then we wait for 1937 * the interrupt. 1938 * To make this easier we first obtain exclusive use of the doorbell. 1939 */ 1940 void 1941 ehci_sync_hc(ehci_softc_t *sc) 1942 { 1943 int s, error; 1944 1945 if (sc->sc_dying) { 1946 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1947 return; 1948 } 1949 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1950 /* get doorbell */ 1951 usb_lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE, NULL); 1952 s = splhardusb(); 1953 /* ask for doorbell */ 1954 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1955 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1956 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1957 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1958 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1959 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1960 splx(s); 1961 /* release doorbell */ 1962 usb_lockmgr(&sc->sc_doorbell_lock, LK_RELEASE, NULL); 1963 #ifdef DIAGNOSTIC 1964 if (error) 1965 printf("ehci_sync_hc: tsleep() = %d\n", error); 1966 #endif 1967 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1968 } 1969 1970 /***********/ 1971 1972 /* 1973 * Data structures and routines to emulate the root hub. 1974 */ 1975 Static usb_device_descriptor_t ehci_devd = { 1976 USB_DEVICE_DESCRIPTOR_SIZE, 1977 UDESC_DEVICE, /* type */ 1978 {0x00, 0x02}, /* USB version */ 1979 UDCLASS_HUB, /* class */ 1980 UDSUBCLASS_HUB, /* subclass */ 1981 UDPROTO_HSHUBSTT, /* protocol */ 1982 64, /* max packet */ 1983 {0},{0},{0x00,0x01}, /* device id */ 1984 1,2,0, /* string indicies */ 1985 1 /* # of configurations */ 1986 }; 1987 1988 Static const usb_device_qualifier_t ehci_odevd = { 1989 USB_DEVICE_DESCRIPTOR_SIZE, 1990 UDESC_DEVICE_QUALIFIER, /* type */ 1991 {0x00, 0x02}, /* USB version */ 1992 UDCLASS_HUB, /* class */ 1993 UDSUBCLASS_HUB, /* subclass */ 1994 UDPROTO_FSHUB, /* protocol */ 1995 64, /* max packet */ 1996 1, /* # of configurations */ 1997 0 1998 }; 1999 2000 Static const usb_config_descriptor_t ehci_confd = { 2001 USB_CONFIG_DESCRIPTOR_SIZE, 2002 UDESC_CONFIG, 2003 {USB_CONFIG_DESCRIPTOR_SIZE + 2004 USB_INTERFACE_DESCRIPTOR_SIZE + 2005 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2006 1, 2007 1, 2008 0, 2009 UC_ATTR_MBO | UC_SELF_POWERED, 2010 0 /* max power */ 2011 }; 2012 2013 Static const usb_interface_descriptor_t ehci_ifcd = { 2014 USB_INTERFACE_DESCRIPTOR_SIZE, 2015 UDESC_INTERFACE, 2016 0, 2017 0, 2018 1, 2019 UICLASS_HUB, 2020 UISUBCLASS_HUB, 2021 UIPROTO_HSHUBSTT, 2022 0 2023 }; 2024 2025 Static const usb_endpoint_descriptor_t ehci_endpd = { 2026 USB_ENDPOINT_DESCRIPTOR_SIZE, 2027 UDESC_ENDPOINT, 2028 UE_DIR_IN | EHCI_INTR_ENDPT, 2029 UE_INTERRUPT, 2030 {8, 0}, /* max packet */ 2031 12 2032 }; 2033 2034 Static const usb_hub_descriptor_t ehci_hubd = { 2035 USB_HUB_DESCRIPTOR_SIZE, 2036 UDESC_HUB, 2037 0, 2038 {0,0}, 2039 0, 2040 0, 2041 {""}, 2042 {""}, 2043 }; 2044 2045 Static int 2046 ehci_str(usb_string_descriptor_t *p, int l, const char *s) 2047 { 2048 int i; 2049 2050 if (l == 0) 2051 return (0); 2052 p->bLength = 2 * strlen(s) + 2; 2053 if (l == 1) 2054 return (1); 2055 p->bDescriptorType = UDESC_STRING; 2056 l -= 2; 2057 for (i = 0; s[i] && l > 1; i++, l -= 2) 2058 USETW2(p->bString[i], 0, s[i]); 2059 return (2*i+2); 2060 } 2061 2062 /* 2063 * Simulate a hardware hub by handling all the necessary requests. 2064 */ 2065 Static usbd_status 2066 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2067 { 2068 usbd_status err; 2069 2070 /* Insert last in queue. */ 2071 err = usb_insert_transfer(xfer); 2072 if (err) 2073 return (err); 2074 2075 /* Pipe isn't running, start first */ 2076 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2077 } 2078 2079 Static usbd_status 2080 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2081 { 2082 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2083 usb_device_request_t *req; 2084 void *buf = NULL; 2085 int port, i; 2086 int s, len, value, index, l, totlen = 0; 2087 usb_port_status_t ps; 2088 usb_hub_descriptor_t hubd; 2089 usbd_status err; 2090 u_int32_t v; 2091 2092 if (sc->sc_dying) 2093 return (USBD_IOERROR); 2094 2095 #ifdef DIAGNOSTIC 2096 if (!(xfer->rqflags & URQ_REQUEST)) 2097 /* XXX panic */ 2098 return (USBD_INVAL); 2099 #endif 2100 req = &xfer->request; 2101 2102 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2103 req->bmRequestType, req->bRequest)); 2104 2105 len = UGETW(req->wLength); 2106 value = UGETW(req->wValue); 2107 index = UGETW(req->wIndex); 2108 2109 if (len != 0) { 2110 /* mbuf transfer is not supported */ 2111 if (xfer->rqflags & URQ_DEV_MAP_MBUF) 2112 return (USBD_INVAL); 2113 buf = xfer->hcbuffer; 2114 } 2115 2116 #define C(x,y) ((x) | ((y) << 8)) 2117 switch(C(req->bRequest, req->bmRequestType)) { 2118 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2119 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2120 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2121 /* 2122 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2123 * for the integrated root hub. 2124 */ 2125 break; 2126 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2127 if (len > 0) { 2128 *(u_int8_t *)buf = sc->sc_conf; 2129 totlen = 1; 2130 } 2131 break; 2132 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2133 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2134 if (len == 0) 2135 break; 2136 switch(value >> 8) { 2137 case UDESC_DEVICE: 2138 if ((value & 0xff) != 0) { 2139 err = USBD_IOERROR; 2140 goto ret; 2141 } 2142 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2143 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2144 memcpy(buf, &ehci_devd, l); 2145 break; 2146 /* 2147 * We can't really operate at another speed, but the spec says 2148 * we need this descriptor. 2149 */ 2150 case UDESC_DEVICE_QUALIFIER: 2151 if ((value & 0xff) != 0) { 2152 err = USBD_IOERROR; 2153 goto ret; 2154 } 2155 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2156 memcpy(buf, &ehci_odevd, l); 2157 break; 2158 /* 2159 * We can't really operate at another speed, but the spec says 2160 * we need this descriptor. 2161 */ 2162 case UDESC_OTHER_SPEED_CONFIGURATION: 2163 case UDESC_CONFIG: 2164 if ((value & 0xff) != 0) { 2165 err = USBD_IOERROR; 2166 goto ret; 2167 } 2168 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2169 memcpy(buf, &ehci_confd, l); 2170 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2171 value >> 8; 2172 buf = (char *)buf + l; 2173 len -= l; 2174 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2175 totlen += l; 2176 memcpy(buf, &ehci_ifcd, l); 2177 buf = (char *)buf + l; 2178 len -= l; 2179 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2180 totlen += l; 2181 memcpy(buf, &ehci_endpd, l); 2182 break; 2183 case UDESC_STRING: 2184 *(u_int8_t *)buf = 0; 2185 totlen = 1; 2186 switch (value & 0xff) { 2187 case 0: /* Language table */ 2188 if (len > 0) 2189 *(u_int8_t *)buf = 4; 2190 if (len >= 4) { 2191 USETW(((usb_string_descriptor_t *)buf)->bString[0], 0x0409); 2192 totlen = 4; 2193 } 2194 break; 2195 case 1: /* Vendor */ 2196 totlen = ehci_str(buf, len, sc->sc_vendor); 2197 break; 2198 case 2: /* Product */ 2199 totlen = ehci_str(buf, len, "EHCI root hub"); 2200 break; 2201 } 2202 break; 2203 default: 2204 err = USBD_IOERROR; 2205 goto ret; 2206 } 2207 break; 2208 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2209 if (len > 0) { 2210 *(u_int8_t *)buf = 0; 2211 totlen = 1; 2212 } 2213 break; 2214 case C(UR_GET_STATUS, UT_READ_DEVICE): 2215 if (len > 1) { 2216 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2217 totlen = 2; 2218 } 2219 break; 2220 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2221 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2222 if (len > 1) { 2223 USETW(((usb_status_t *)buf)->wStatus, 0); 2224 totlen = 2; 2225 } 2226 break; 2227 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2228 if (value >= USB_MAX_DEVICES) { 2229 err = USBD_IOERROR; 2230 goto ret; 2231 } 2232 sc->sc_addr = value; 2233 break; 2234 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2235 if (value != 0 && value != 1) { 2236 err = USBD_IOERROR; 2237 goto ret; 2238 } 2239 sc->sc_conf = value; 2240 break; 2241 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2242 break; 2243 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2244 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2245 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2246 err = USBD_IOERROR; 2247 goto ret; 2248 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2249 break; 2250 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2251 break; 2252 /* Hub requests */ 2253 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2254 break; 2255 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2256 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2257 "port=%d feature=%d\n", 2258 index, value)); 2259 if (index < 1 || index > sc->sc_noport) { 2260 err = USBD_IOERROR; 2261 goto ret; 2262 } 2263 port = EHCI_PORTSC(index); 2264 v = EOREAD4(sc, port); 2265 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2266 v &= ~EHCI_PS_CLEAR; 2267 switch(value) { 2268 case UHF_PORT_ENABLE: 2269 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2270 break; 2271 case UHF_PORT_SUSPEND: 2272 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 2273 break; 2274 case UHF_PORT_POWER: 2275 if (sc->sc_hasppc) 2276 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2277 break; 2278 case UHF_PORT_TEST: 2279 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2280 "%d\n", index)); 2281 break; 2282 case UHF_PORT_INDICATOR: 2283 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2284 "%d\n", index)); 2285 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2286 break; 2287 case UHF_C_PORT_CONNECTION: 2288 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2289 break; 2290 case UHF_C_PORT_ENABLE: 2291 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2292 break; 2293 case UHF_C_PORT_SUSPEND: 2294 /* how? */ 2295 break; 2296 case UHF_C_PORT_OVER_CURRENT: 2297 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2298 break; 2299 case UHF_C_PORT_RESET: 2300 sc->sc_isreset[index] = 0; 2301 break; 2302 default: 2303 err = USBD_IOERROR; 2304 goto ret; 2305 } 2306 #if 0 2307 switch(value) { 2308 case UHF_C_PORT_CONNECTION: 2309 case UHF_C_PORT_ENABLE: 2310 case UHF_C_PORT_SUSPEND: 2311 case UHF_C_PORT_OVER_CURRENT: 2312 case UHF_C_PORT_RESET: 2313 default: 2314 break; 2315 } 2316 #endif 2317 break; 2318 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2319 if (len == 0) 2320 break; 2321 if ((value & 0xff) != 0) { 2322 err = USBD_IOERROR; 2323 goto ret; 2324 } 2325 hubd = ehci_hubd; 2326 hubd.bNbrPorts = sc->sc_noport; 2327 v = EOREAD4(sc, EHCI_HCSPARAMS); 2328 USETW(hubd.wHubCharacteristics, 2329 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2330 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2331 ? UHD_PORT_IND : 0); 2332 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2333 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2334 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2335 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2336 l = min(len, hubd.bDescLength); 2337 totlen = l; 2338 memcpy(buf, &hubd, l); 2339 break; 2340 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2341 if (len != 4) { 2342 err = USBD_IOERROR; 2343 goto ret; 2344 } 2345 memset(buf, 0, len); /* ? XXX */ 2346 totlen = len; 2347 break; 2348 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2349 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2350 index)); 2351 if (index < 1 || index > sc->sc_noport) { 2352 err = USBD_IOERROR; 2353 goto ret; 2354 } 2355 if (len != 4) { 2356 err = USBD_IOERROR; 2357 goto ret; 2358 } 2359 v = EOREAD4(sc, EHCI_PORTSC(index)); 2360 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2361 v)); 2362 i = UPS_HIGH_SPEED; 2363 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2364 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2365 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2366 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2367 if (v & EHCI_PS_PR) i |= UPS_RESET; 2368 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2369 USETW(ps.wPortStatus, i); 2370 i = 0; 2371 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2372 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2373 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2374 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2375 USETW(ps.wPortChange, i); 2376 l = min(len, sizeof ps); 2377 memcpy(buf, &ps, l); 2378 totlen = l; 2379 break; 2380 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2381 err = USBD_IOERROR; 2382 goto ret; 2383 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2384 break; 2385 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2386 if (index < 1 || index > sc->sc_noport) { 2387 err = USBD_IOERROR; 2388 goto ret; 2389 } 2390 port = EHCI_PORTSC(index); 2391 v = EOREAD4(sc, port); 2392 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2393 v &= ~EHCI_PS_CLEAR; 2394 switch(value) { 2395 case UHF_PORT_ENABLE: 2396 EOWRITE4(sc, port, v | EHCI_PS_PE); 2397 break; 2398 case UHF_PORT_SUSPEND: 2399 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2400 break; 2401 case UHF_PORT_RESET: 2402 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2403 index)); 2404 if (EHCI_PS_IS_LOWSPEED(v)) { 2405 /* Low speed device, give up ownership. */ 2406 ehci_disown(sc, index, 1); 2407 break; 2408 } 2409 /* Start reset sequence. */ 2410 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2411 EOWRITE4(sc, port, v | EHCI_PS_PR); 2412 /* Wait for reset to complete. */ 2413 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2414 if (sc->sc_dying) { 2415 err = USBD_IOERROR; 2416 goto ret; 2417 } 2418 /* Terminate reset sequence. */ 2419 EOWRITE4(sc, port, v); 2420 /* Wait for HC to complete reset. */ 2421 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2422 if (sc->sc_dying) { 2423 err = USBD_IOERROR; 2424 goto ret; 2425 } 2426 v = EOREAD4(sc, port); 2427 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2428 if (v & EHCI_PS_PR) { 2429 printf("%s: port reset timeout\n", 2430 USBDEVNAME(sc->sc_bus.bdev)); 2431 return (USBD_TIMEOUT); 2432 } 2433 if (!(v & EHCI_PS_PE)) { 2434 /* Not a high speed device, give up ownership.*/ 2435 ehci_disown(sc, index, 0); 2436 break; 2437 } 2438 sc->sc_isreset[index] = 1; 2439 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2440 index, v)); 2441 break; 2442 case UHF_PORT_POWER: 2443 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2444 "%d (has PPC = %d)\n", index, 2445 sc->sc_hasppc)); 2446 if (sc->sc_hasppc) 2447 EOWRITE4(sc, port, v | EHCI_PS_PP); 2448 break; 2449 case UHF_PORT_TEST: 2450 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2451 "%d\n", index)); 2452 break; 2453 case UHF_PORT_INDICATOR: 2454 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2455 "%d\n", index)); 2456 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2457 break; 2458 default: 2459 err = USBD_IOERROR; 2460 goto ret; 2461 } 2462 break; 2463 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2464 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2465 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2466 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2467 break; 2468 default: 2469 err = USBD_IOERROR; 2470 goto ret; 2471 } 2472 xfer->actlen = totlen; 2473 err = USBD_NORMAL_COMPLETION; 2474 ret: 2475 xfer->status = err; 2476 s = splusb(); 2477 usb_transfer_complete(xfer); 2478 splx(s); 2479 return (USBD_IN_PROGRESS); 2480 } 2481 2482 void 2483 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2484 { 2485 int port; 2486 u_int32_t v; 2487 2488 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2489 #ifdef DIAGNOSTIC 2490 if (sc->sc_npcomp != 0) { 2491 int i = (index-1) / sc->sc_npcomp; 2492 if (i >= sc->sc_ncomp) 2493 printf("%s: strange port\n", 2494 USBDEVNAME(sc->sc_bus.bdev)); 2495 else 2496 printf("%s: handing over %s speed device on " 2497 "port %d to %s\n", 2498 USBDEVNAME(sc->sc_bus.bdev), 2499 lowspeed ? "low" : "full", 2500 index, USBDEVNAME(sc->sc_comps[i]->bdev)); 2501 } else { 2502 printf("%s: npcomp == 0\n", USBDEVNAME(sc->sc_bus.bdev)); 2503 } 2504 #endif 2505 port = EHCI_PORTSC(index); 2506 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2507 EOWRITE4(sc, port, v | EHCI_PS_PO); 2508 } 2509 2510 /* Abort a root control request. */ 2511 Static void 2512 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2513 { 2514 /* Nothing to do, all transfers are synchronous. */ 2515 } 2516 2517 /* Close the root pipe. */ 2518 Static void 2519 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2520 { 2521 DPRINTF(("ehci_root_ctrl_close\n")); 2522 /* Nothing to do. */ 2523 } 2524 2525 void 2526 ehci_root_intr_done(usbd_xfer_handle xfer) 2527 { 2528 } 2529 2530 Static usbd_status 2531 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2532 { 2533 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2534 usbd_status err; 2535 2536 /* Insert last in queue. */ 2537 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 2538 &EXFER(xfer)->dmabuf); 2539 if (err) 2540 return (err); 2541 2542 /* Pipe isn't running, start first */ 2543 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2544 } 2545 2546 Static usbd_status 2547 ehci_root_intr_start(usbd_xfer_handle xfer) 2548 { 2549 usbd_pipe_handle pipe = xfer->pipe; 2550 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2551 2552 if (sc->sc_dying) 2553 return (USBD_IOERROR); 2554 2555 if (xfer->rqflags & URQ_DEV_MAP_MBUF) 2556 return (USBD_INVAL); /* mbuf transfer is not supported */ 2557 2558 sc->sc_intrxfer = xfer; 2559 2560 return (USBD_IN_PROGRESS); 2561 } 2562 2563 /* Abort a root interrupt request. */ 2564 Static void 2565 ehci_root_intr_abort(usbd_xfer_handle xfer) 2566 { 2567 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2568 int s; 2569 2570 if (xfer->pipe->intrxfer == xfer) { 2571 DPRINTF(("ehci_root_intr_abort: remove\n")); 2572 xfer->pipe->intrxfer = NULL; 2573 } 2574 xfer->status = USBD_CANCELLED; 2575 s = splusb(); 2576 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 2577 splx(s); 2578 } 2579 2580 /* Close the root pipe. */ 2581 Static void 2582 ehci_root_intr_close(usbd_pipe_handle pipe) 2583 { 2584 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2585 2586 DPRINTF(("ehci_root_intr_close\n")); 2587 2588 sc->sc_intrxfer = NULL; 2589 } 2590 2591 void 2592 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2593 { 2594 } 2595 2596 /************************/ 2597 2598 ehci_soft_qh_t * 2599 ehci_alloc_sqh(ehci_softc_t *sc) 2600 { 2601 ehci_soft_qh_t *sqh; 2602 ehci_soft_qtd_t *sqtd; 2603 usbd_status err; 2604 int i, offs; 2605 usb_dma_t dma; 2606 struct ehci_mem_desc *em; 2607 2608 if (sc->sc_freeqhs == NULL) { 2609 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2610 err = usb_allocmem(&sc->sc_dmatag, 2611 EHCI_SQH_SIZE*EHCI_SQH_CHUNK + sizeof(struct ehci_mem_desc), 2612 EHCI_PAGE_SIZE, &dma); 2613 #ifdef EHCI_DEBUG 2614 if (err) 2615 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2616 #endif 2617 if (err) 2618 return (NULL); 2619 em = KERNADDR(&dma, EHCI_SQH_SIZE * EHCI_SQH_CHUNK); 2620 em->em_top = KERNADDR(&dma, 0); 2621 em->em_topdma = DMAADDR(&dma, 0); 2622 em->em_dma = dma; 2623 SIMPLEQ_INSERT_HEAD(&sc->sc_sqh_chunks, em, em_next); 2624 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2625 offs = i * EHCI_SQH_SIZE; 2626 sqh = KERNADDR(&dma, offs); 2627 sqh->eh_mdesc = em; 2628 sqh->next = sc->sc_freeqhs; 2629 sc->sc_freeqhs = sqh; 2630 } 2631 } 2632 /* Allocate the initial inactive sqtd. */ 2633 sqtd = ehci_alloc_sqtd_norsv(sc); 2634 if (sqtd == NULL) 2635 return (NULL); 2636 sqtd->qtd.qtd_status = htole32(0); 2637 sqtd->qtd.qtd_next = EHCI_NULL; 2638 sqtd->qtd.qtd_altnext = EHCI_NULL; 2639 2640 sqh = sc->sc_freeqhs; 2641 sc->sc_freeqhs = sqh->next; 2642 2643 /* The overlay QTD should begin zeroed. */ 2644 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(sqtd)); 2645 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2646 sqh->qh.qh_qtd.qtd_status = 0; 2647 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) { 2648 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2649 sqh->qh.qh_qtd.qtd_buffer_hi[i] = 0; 2650 } 2651 sqh->next = NULL; 2652 sqh->prev = NULL; 2653 sqh->sqtd = sqtd; 2654 sqh->inactivesqtd = sqtd; 2655 return (sqh); 2656 } 2657 2658 void 2659 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2660 { 2661 ehci_free_sqtd_norsv(sc, sqh->inactivesqtd); 2662 sqh->next = sc->sc_freeqhs; 2663 sc->sc_freeqhs = sqh; 2664 } 2665 2666 Static usbd_status 2667 ehci_grow_sqtd(ehci_softc_t *sc) 2668 { 2669 usb_dma_t dma; 2670 struct ehci_mem_desc *em; 2671 ehci_soft_qtd_t *sqtd; 2672 usbd_status err; 2673 int i, s, offs; 2674 2675 DPRINTFN(2, ("ehci_grow_sqtd: allocating chunk\n")); 2676 err = usb_allocmem(&sc->sc_dmatag, 2677 EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK + sizeof(struct ehci_mem_desc), 2678 EHCI_PAGE_SIZE, &dma); 2679 #ifdef EHCI_DEBUG 2680 if (err) 2681 printf("ehci_grow_sqtd: usb_allocmem()=%d\n", err); 2682 #endif 2683 if (err) 2684 return (err); 2685 em = KERNADDR(&dma, EHCI_SQTD_SIZE * EHCI_SQTD_CHUNK); 2686 em->em_top = KERNADDR(&dma, 0); 2687 em->em_topdma = DMAADDR(&dma, 0); 2688 em->em_dma = dma; 2689 s = splusb(); 2690 SIMPLEQ_INSERT_HEAD(&sc->sc_sqtd_chunks, em, em_next); 2691 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2692 offs = i * EHCI_SQTD_SIZE; 2693 sqtd = KERNADDR(&dma, offs); 2694 sqtd->et_mdesc = em; 2695 sqtd->nextqtd = sc->sc_freeqtds; 2696 sc->sc_freeqtds = sqtd; 2697 sc->sc_nfreeqtds++; 2698 } 2699 splx(s); 2700 2701 return (USBD_NORMAL_COMPLETION); 2702 } 2703 2704 ehci_soft_qtd_t * 2705 ehci_alloc_sqtd(ehci_softc_t *sc) 2706 { 2707 ehci_soft_qtd_t *sqtd; 2708 int i; 2709 int s; 2710 2711 s = splusb(); 2712 2713 #ifdef DIAGNOSTIC 2714 if (sc->sc_freeqtds == NULL) 2715 panic("ehci_alloc_sqtd: %p %d", 2716 sc->sc_freeqtds, sc->sc_nfreeqtds); 2717 #endif 2718 sqtd = sc->sc_freeqtds; 2719 sc->sc_freeqtds = sqtd->nextqtd; 2720 splx(s); 2721 sqtd->qtd.qtd_next = EHCI_NULL; 2722 sqtd->qtd.qtd_altnext = EHCI_NULL; 2723 sqtd->qtd.qtd_status = 0; 2724 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) { 2725 sqtd->qtd.qtd_buffer[i] = 0; 2726 sqtd->qtd.qtd_buffer_hi[i] = 0; 2727 } 2728 sqtd->nextqtd = NULL; 2729 sqtd->xfer = NULL; 2730 2731 return (sqtd); 2732 } 2733 2734 Static ehci_soft_qtd_t * 2735 ehci_alloc_sqtd_norsv(ehci_softc_t *sc) 2736 { 2737 int s; 2738 2739 s = splusb(); 2740 if (sc->sc_nfreeqtds < 1) 2741 if (ehci_grow_sqtd(sc)) 2742 return (NULL); 2743 sc->sc_nfreeqtds--; 2744 splx(s); 2745 return (ehci_alloc_sqtd(sc)); 2746 } 2747 2748 void 2749 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2750 { 2751 int s; 2752 2753 s = splusb(); 2754 sqtd->nextqtd = sc->sc_freeqtds; 2755 sc->sc_freeqtds = sqtd; 2756 splx(s); 2757 } 2758 2759 Static void 2760 ehci_free_sqtd_norsv(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2761 { 2762 int s; 2763 2764 ehci_free_sqtd(sc, sqtd); 2765 s = splusb(); 2766 sc->sc_nfreeqtds++; 2767 splx(s); 2768 } 2769 2770 usbd_status 2771 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2772 int alen, int rd, usbd_xfer_handle xfer, ehci_soft_qtd_t *start, 2773 ehci_soft_qtd_t *newinactive, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2774 { 2775 usb_endpoint_descriptor_t *endpt; 2776 ehci_soft_qtd_t *next, *cur; 2777 ehci_physaddr_t dataphys, nextphys; 2778 u_int32_t qtdstatus; 2779 int adj, len, curlen, mps, offset, pagelen, seg, segoff; 2780 int i, iscontrol, forceshort; 2781 struct usb_buffer_dma *ub = &EXFER(xfer)->dmabuf; 2782 bus_dma_segment_t *segs = USB_BUFFER_SEGS(ub); 2783 int nsegs = USB_BUFFER_NSEGS(ub); 2784 int needaux; 2785 int isread; 2786 union usb_bufptr bufptr; 2787 struct aux_desc ad; 2788 bus_addr_t auxdma; 2789 2790 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2791 2792 offset = 0; 2793 len = alen; 2794 iscontrol = (epipe->pipe.endpoint->edesc->bmAttributes & UE_XFERTYPE) == 2795 UE_CONTROL; 2796 qtdstatus = EHCI_QTD_ACTIVE | 2797 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2798 EHCI_QTD_SET_CERR(3) 2799 /* IOC set below */ 2800 /* BYTES set below */ 2801 ; 2802 endpt = epipe->pipe.endpoint->edesc; 2803 mps = UE_MAXPKTSZ(endpt); 2804 forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) && 2805 len % mps == 0; 2806 /* 2807 * The control transfer data stage always starts with a toggle of 1. 2808 * For other transfers we let the hardware track the toggle state. 2809 */ 2810 if (iscontrol) 2811 qtdstatus |= EHCI_QTD_SET_TOGGLE(1); 2812 2813 /* 2814 * aux memory is possibly required if 2815 * buffer has more than one segments, 2816 * the transfer direction is OUT, 2817 * and 2818 * buffer is an mbuf chain, or 2819 * buffer is not mps aligned 2820 */ 2821 isread = UE_GET_DIR(endpt->bEndpointAddress) == UE_DIR_IN; 2822 needaux = 2823 nsegs > 1 && !isread && 2824 ((xfer->rqflags & URQ_DEV_MAP_MBUF) || 2825 (mps & (mps - 1)) != 0 /* mps is not a power of 2 */ || 2826 (segs[0].ds_addr & (mps - 1)) != 0 /* buffer is unaligned */); 2827 2828 if (needaux) { 2829 usb_bufptr_init(&bufptr, xfer); 2830 if (EXFER(xfer)->aux.aux_naux) { 2831 /* sync previous aux (just in case, probably a no-op) */ 2832 ehci_aux_dma_sync(sc, &EXFER(xfer)->aux, 2833 BUS_DMASYNC_POSTWRITE); 2834 2835 ehci_aux_mem_init(&EXFER(xfer)->aux); 2836 } 2837 } 2838 2839 if (start != NULL) { 2840 /* 2841 * If we are given a starting qTD, assume it is linked into 2842 * an active QH so be careful not to mark it active. 2843 */ 2844 cur = start; 2845 *sp = cur; 2846 qtdstatus &= ~EHCI_QTD_ACTIVE; 2847 } else { 2848 cur = ehci_alloc_sqtd(sc); 2849 *sp = cur; 2850 if (cur == NULL) 2851 goto nomem; 2852 } 2853 seg = 0; 2854 segoff = 0; 2855 for (;;) { 2856 curlen = 0; 2857 2858 /* The EHCI hardware can handle at most 5 pages. */ 2859 for (i = 0; i < EHCI_QTD_NBUFFERS && curlen < len; i++) { 2860 USB_KASSERT2(seg < nsegs, 2861 ("ehci_alloc_sqtd_chain: overrun")); 2862 dataphys = segs[seg].ds_addr + segoff; 2863 pagelen = segs[seg].ds_len - segoff; 2864 if (pagelen > len - curlen) 2865 pagelen = len - curlen; 2866 if (pagelen > EHCI_PAGE_SIZE - 2867 EHCI_PAGE_OFFSET(dataphys)) 2868 pagelen = EHCI_PAGE_SIZE - 2869 EHCI_PAGE_OFFSET(dataphys); 2870 segoff += pagelen; 2871 if (segoff >= segs[seg].ds_len) { 2872 USB_KASSERT2(segoff == segs[seg].ds_len, 2873 ("ehci_alloc_sqtd_chain: overlap")); 2874 seg++; 2875 segoff = 0; 2876 } 2877 2878 cur->qtd.qtd_buffer[i] = htole32(dataphys); 2879 cur->qtd.qtd_buffer_hi[i] = 0; 2880 curlen += pagelen; 2881 2882 /* 2883 * Must stop if there is any gap before or after 2884 * the page boundary. 2885 */ 2886 if (EHCI_PAGE_OFFSET(dataphys + pagelen) != 0) 2887 break; 2888 if (seg < nsegs && EHCI_PAGE_OFFSET(segoff + 2889 segs[seg].ds_addr) != 0) 2890 break; 2891 } 2892 /* Adjust down to a multiple of mps if not at the end. */ 2893 if (!isread && curlen < len && (adj = curlen % mps) != 0) { 2894 curlen -= adj; 2895 if (curlen == 0) { 2896 USB_KASSERT(needaux); 2897 /* need aux -- a packet is not contiguous */ 2898 curlen = len < mps ? len : mps; 2899 auxdma = ehci_aux_dma_alloc(&EXFER(xfer)->aux, 2900 curlen, &ad); 2901 2902 /* prepare aux DMA */ 2903 usb_bufptr_wr(&bufptr, ad.aux_kern, curlen, 2904 xfer->rqflags & URQ_DEV_MAP_MBUF); 2905 cur->qtd.qtd_buffer[i] = htole32(auxdma); 2906 cur->qtd.qtd_buffer_hi[i] = 0; 2907 2908 /* skip handled segments */ 2909 segoff += curlen - adj; 2910 do { 2911 segoff -= segs[seg].ds_len; 2912 seg++; 2913 } while (segoff > segs[seg].ds_len); 2914 2915 } else { 2916 segoff -= adj; 2917 if (segoff < 0) { 2918 seg--; 2919 segoff += segs[seg].ds_len; 2920 } 2921 USB_KASSERT2(seg >= 0 && segoff >= 0, 2922 ("ehci_alloc_sqtd_chain: adjust to mps")); 2923 } 2924 } 2925 2926 len -= curlen; 2927 2928 if (len != 0 || forceshort) { 2929 next = ehci_alloc_sqtd(sc); 2930 if (next == NULL) 2931 goto nomem; 2932 nextphys = htole32(EHCI_SQTD_DMAADDR(next)); 2933 } else { 2934 next = NULL; 2935 nextphys = EHCI_NULL; 2936 } 2937 2938 cur->nextqtd = next; 2939 cur->qtd.qtd_next = nextphys; 2940 /* Make sure to stop after a short transfer. */ 2941 cur->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 2942 cur->qtd.qtd_status = 2943 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2944 cur->xfer = xfer; 2945 cur->len = curlen; 2946 DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%d\n", curlen)); 2947 if (iscontrol) { 2948 /* 2949 * adjust the toggle based on the number of packets 2950 * in this qtd 2951 */ 2952 if ((((curlen + mps - 1) / mps) & 1) || curlen == 0) 2953 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2954 } 2955 qtdstatus |= EHCI_QTD_ACTIVE; 2956 if (len == 0) { 2957 if (!forceshort) 2958 break; 2959 forceshort = 0; 2960 } 2961 EHCI_SQTD_SYNC(sc, cur, 2962 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2963 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2964 offset += curlen; 2965 cur = next; 2966 2967 if (needaux) 2968 usb_bufptr_advance(&bufptr, curlen, 2969 xfer->rqflags & URQ_DEV_MAP_MBUF); 2970 } 2971 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2972 EHCI_SQTD_SYNC(sc, cur, 2973 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2974 if (needaux) 2975 ehci_aux_dma_sync(sc, &EXFER(xfer)->aux, BUS_DMASYNC_PREWRITE); 2976 2977 *ep = cur; 2978 2979 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2980 *sp, *ep)); 2981 2982 return (USBD_NORMAL_COMPLETION); 2983 2984 nomem: 2985 /* XXX free chain */ 2986 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2987 return (USBD_NOMEM); 2988 } 2989 2990 /* Free the chain starting at sqtd and end at the qTD before sqtdend */ 2991 Static void 2992 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qh_t *sqh, 2993 ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *sqtdend) 2994 { 2995 ehci_soft_qtd_t *p, **prevp; 2996 int i; 2997 2998 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2999 sqtd, sqtdend)); 3000 3001 /* First unlink the chain from the QH's software qTD list. */ 3002 prevp = &sqh->sqtd; 3003 for (p = sqh->sqtd; p != NULL; p = p->nextqtd) { 3004 if (p == sqtd) { 3005 *prevp = sqtdend; 3006 break; 3007 } 3008 prevp = &p->nextqtd; 3009 } 3010 USB_KASSERT2(p != NULL, ("ehci_free_sqtd_chain: chain not found")); 3011 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 3012 p = sqtd->nextqtd; 3013 ehci_free_sqtd(sc, sqtd); 3014 } 3015 } 3016 3017 /****************/ 3018 3019 /* 3020 * Close a reqular pipe. 3021 * Assumes that there are no pending transactions. 3022 */ 3023 void 3024 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3025 { 3026 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3027 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3028 ehci_soft_qh_t *sqh = epipe->sqh; 3029 int s; 3030 3031 s = splusb(); 3032 ehci_rem_qh(sc, sqh, head); 3033 splx(s); 3034 pipe->endpoint->savedtoggle = 3035 EHCI_QTD_GET_TOGGLE(le32toh(sqh->qh.qh_qtd.qtd_status)); 3036 ehci_free_sqh(sc, epipe->sqh); 3037 } 3038 3039 /* 3040 * Abort a device request. 3041 * If this routine is called at splusb() it guarantees that the request 3042 * will be removed from the hardware scheduling and that the callback 3043 * for it will be called with USBD_CANCELLED status. 3044 * It's impossible to guarantee that the requested transfer will not 3045 * have happened since the hardware runs concurrently. 3046 * If the transaction has already happened we rely on the ordinary 3047 * interrupt processing to process it. 3048 */ 3049 void 3050 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3051 { 3052 #define exfer EXFER(xfer) 3053 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3054 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 3055 ehci_soft_qh_t *sqh = epipe->sqh; 3056 ehci_soft_qtd_t *sqtd, *snext; 3057 ehci_physaddr_t cur, us, next; 3058 int s; 3059 int hit, i; 3060 /* int count = 0; */ 3061 ehci_soft_qh_t *psqh; 3062 3063 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 3064 3065 if (sc->sc_dying) { 3066 /* If we're dying, just do the software part. */ 3067 s = splusb(); 3068 xfer->status = status; /* make software ignore it */ 3069 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3070 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 3071 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, 3072 &EXFER(xfer)->dmabuf); 3073 splx(s); 3074 return; 3075 } 3076 3077 if (xfer->device->bus->intr_context || !curproc) 3078 panic("ehci_abort_xfer: not in process context"); 3079 3080 /* 3081 * If an abort is already in progress then just wait for it to 3082 * complete and return. 3083 */ 3084 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 3085 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3086 /* No need to wait if we're aborting from a timeout. */ 3087 if (status == USBD_TIMEOUT) 3088 return; 3089 /* Override the status which might be USBD_TIMEOUT. */ 3090 xfer->status = status; 3091 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3092 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT; 3093 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 3094 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciaw", 0); 3095 return; 3096 } 3097 3098 /* 3099 * Step 1: Make interrupt routine and timeouts ignore xfer. 3100 */ 3101 s = splusb(); 3102 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 3103 xfer->status = status; /* make software ignore it */ 3104 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3105 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 3106 splx(s); 3107 3108 /* 3109 * Step 2: Wait until we know hardware has finished any possible 3110 * use of the xfer. We do this by removing the entire 3111 * queue from the async schedule and waiting for the doorbell. 3112 * Nothing else should be touching the queue now. 3113 */ 3114 psqh = sqh->prev; 3115 ehci_rem_qh(sc, sqh, psqh); 3116 3117 /* 3118 * Step 3: make sure the soft interrupt routine 3119 * has run. This should remove any completed items off the queue. 3120 * The hardware has no reference to completed items (TDs). 3121 * It's safe to remove them at any time. 3122 */ 3123 s = splusb(); 3124 #ifdef USB_USE_SOFTINTR 3125 sc->sc_softwake = 1; 3126 #endif /* USB_USE_SOFTINTR */ 3127 usb_schedsoftintr(&sc->sc_bus); 3128 #ifdef USB_USE_SOFTINTR 3129 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3130 #endif /* USB_USE_SOFTINTR */ 3131 3132 /* 3133 * Step 4: Remove any vestiges of the xfer from the hardware. 3134 * The complication here is that the hardware may have executed 3135 * into or even beyond the xfer we're trying to abort. 3136 * So as we're scanning the TDs of this xfer we check if 3137 * the hardware points to any of them. 3138 * 3139 * first we need to see if there are any transfers 3140 * on this queue before the xfer we are aborting.. we need 3141 * to update any pointers that point to us to point past 3142 * the aborting xfer. (If there is something past us). 3143 * Hardware and software. 3144 */ 3145 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3146 hit = 0; 3147 3148 /* If they initially point here. */ 3149 us = EHCI_SQTD_DMAADDR(exfer->sqtdstart); 3150 3151 /* We will change them to point here */ 3152 snext = exfer->sqtdend->nextqtd; 3153 next = htole32(EHCI_SQTD_DMAADDR(snext)); 3154 3155 /* 3156 * Now loop through any qTDs before us and keep track of the pointer 3157 * that points to us for the end. 3158 */ 3159 sqtd = sqh->sqtd; 3160 while (sqtd && sqtd != exfer->sqtdstart) { 3161 hit |= (cur == EHCI_SQTD_DMAADDR(sqtd)); 3162 if (EHCI_LINK_ADDR(le32toh(sqtd->qtd.qtd_next)) == us) { 3163 sqtd->qtd.qtd_next = next; 3164 EHCI_SQTD_SYNC(sc, sqtd, 3165 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3166 } 3167 if (EHCI_LINK_ADDR(le32toh(sqtd->qtd.qtd_altnext)) == us) { 3168 sqtd->qtd.qtd_altnext = next; 3169 EHCI_SQTD_SYNC(sc, sqtd, 3170 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3171 } 3172 sqtd = sqtd->nextqtd; 3173 } 3174 3175 /* 3176 * If we already saw the active one then we are pretty much done. 3177 * We've done all the relinking we need to do. 3178 */ 3179 if (!hit) { 3180 3181 /* 3182 * Now reinitialise the QH to point to the next qTD 3183 * (if there is one). We only need to do this if 3184 * it was previously pointing to us. 3185 */ 3186 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3187 if (cur == EHCI_SQTD_DMAADDR(sqtd)) { 3188 hit++; 3189 } 3190 if (sqtd == exfer->sqtdend) 3191 break; 3192 } 3193 sqtd = sqtd->nextqtd; 3194 /* 3195 * Only need to alter the QH if it was pointing at a qTD 3196 * that we are removing. 3197 */ 3198 if (hit) { 3199 sqh->qh.qh_qtd.qtd_next = 3200 htole32(EHCI_SQTD_DMAADDR(snext)); 3201 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 3202 sqh->qh.qh_qtd.qtd_status &= 3203 htole32(EHCI_QTD_TOGGLE_MASK); 3204 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) { 3205 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 3206 sqh->qh.qh_qtd.qtd_buffer_hi[i] = 0; 3207 } 3208 } 3209 } 3210 ehci_add_qh(sc, sqh, psqh); 3211 /* 3212 * Step 5: Execute callback. 3213 */ 3214 #ifdef DIAGNOSTIC 3215 exfer->isdone = 1; 3216 #endif 3217 /* Do the wakeup first to avoid touching the xfer after the callback. */ 3218 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTING; 3219 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) { 3220 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT; 3221 wakeup(&exfer->ehci_xfer_flags); 3222 } 3223 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 3224 3225 /* printf("%s: %d TDs aborted\n", __func__, count); */ 3226 splx(s); 3227 #undef exfer 3228 } 3229 3230 void 3231 ehci_timeout(void *addr) 3232 { 3233 struct ehci_xfer *exfer = addr; 3234 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3235 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 3236 3237 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3238 #ifdef USB_DEBUG 3239 if (ehcidebug > 1) 3240 usbd_dump_pipe(exfer->xfer.pipe); 3241 #endif 3242 3243 if (sc->sc_dying) { 3244 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3245 return; 3246 } 3247 3248 /* Execute the abort in a process context. */ 3249 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3250 USB_TASKQ_HC); 3251 } 3252 3253 void 3254 ehci_timeout_task(void *addr) 3255 { 3256 usbd_xfer_handle xfer = addr; 3257 int s; 3258 3259 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3260 3261 s = splusb(); 3262 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3263 splx(s); 3264 } 3265 3266 /* 3267 * Some EHCI chips from VIA / ATI seem to trigger interrupts before writing 3268 * back the qTD status, or miss signalling occasionally under heavy load. 3269 * If the host machine is too fast, we can miss transaction completion - when 3270 * we scan the active list the transaction still seems to be active. This 3271 * generally exhibits itself as a umass stall that never recovers. 3272 * 3273 * We work around this behaviour by setting up this callback after any softintr 3274 * that completes with transactions still pending, giving us another chance to 3275 * check for completion after the writeback has taken place. 3276 */ 3277 void 3278 ehci_intrlist_timeout(void *arg) 3279 { 3280 ehci_softc_t *sc = arg; 3281 int s = splusb(); 3282 3283 DPRINTFN(3, ("ehci_intrlist_timeout\n")); 3284 usb_schedsoftintr(&sc->sc_bus); 3285 3286 splx(s); 3287 } 3288 3289 /************************/ 3290 3291 Static usbd_status 3292 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3293 { 3294 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3295 usbd_status err; 3296 3297 /* Insert last in queue. */ 3298 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3299 &EXFER(xfer)->dmabuf); 3300 if (err) 3301 return (err); 3302 3303 /* Pipe isn't running, start first */ 3304 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3305 } 3306 3307 Static usbd_status 3308 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3309 { 3310 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3311 usbd_status err; 3312 3313 if (sc->sc_dying) 3314 return (USBD_IOERROR); 3315 3316 #ifdef DIAGNOSTIC 3317 if (!(xfer->rqflags & URQ_REQUEST)) { 3318 /* XXX panic */ 3319 printf("ehci_device_ctrl_transfer: not a request\n"); 3320 return (USBD_INVAL); 3321 } 3322 #endif 3323 3324 err = ehci_device_request(xfer); 3325 if (err) 3326 return (err); 3327 3328 if (sc->sc_bus.use_polling) 3329 ehci_waitintr(sc, xfer); 3330 return (USBD_IN_PROGRESS); 3331 } 3332 3333 void 3334 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3335 { 3336 struct ehci_xfer *ex = EXFER(xfer); 3337 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3338 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3339 3340 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3341 3342 #ifdef DIAGNOSTIC 3343 if (!(xfer->rqflags & URQ_REQUEST)) { 3344 panic("ehci_ctrl_done: not a request"); 3345 } 3346 #endif 3347 3348 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3349 ehci_del_intr_list(ex); /* remove from active list */ 3350 ehci_free_sqtd_chain(sc, epipe->sqh, ex->sqtdstart, 3351 ex->sqtdend->nextqtd); 3352 } 3353 3354 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3355 } 3356 3357 /* Abort a device control request. */ 3358 Static void 3359 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3360 { 3361 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3362 ehci_abort_xfer(xfer, USBD_CANCELLED); 3363 } 3364 3365 /* Close a device control pipe. */ 3366 Static void 3367 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3368 { 3369 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3370 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3371 3372 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3373 ehci_close_pipe(pipe, sc->sc_async_head); 3374 usb_freemem(&sc->sc_dmatag, &epipe->u.ctl.reqdma); 3375 } 3376 3377 usbd_status 3378 ehci_device_request(usbd_xfer_handle xfer) 3379 { 3380 #define exfer EXFER(xfer) 3381 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3382 usb_device_request_t *req = &xfer->request; 3383 usbd_device_handle dev = epipe->pipe.device; 3384 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3385 ehci_soft_qtd_t *newinactive, *setup, *stat, *next; 3386 ehci_soft_qh_t *sqh; 3387 int isread; 3388 int len; 3389 usbd_status err; 3390 int s; 3391 3392 isread = req->bmRequestType & UT_READ; 3393 len = UGETW(req->wLength); 3394 3395 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3396 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3397 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3398 UGETW(req->wIndex), len, dev->address, 3399 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3400 3401 newinactive = ehci_alloc_sqtd(sc); 3402 if (newinactive == NULL) { 3403 err = USBD_NOMEM; 3404 goto bad1; 3405 } 3406 newinactive->qtd.qtd_status = htole32(0); 3407 newinactive->qtd.qtd_next = EHCI_NULL; 3408 newinactive->qtd.qtd_altnext = EHCI_NULL; 3409 EHCI_SQTD_SYNC(sc, newinactive, 3410 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3411 stat = ehci_alloc_sqtd(sc); 3412 if (stat == NULL) { 3413 err = USBD_NOMEM; 3414 goto bad2; 3415 } 3416 3417 sqh = epipe->sqh; 3418 setup = sqh->inactivesqtd; 3419 sqh->inactivesqtd = newinactive; 3420 epipe->u.ctl.length = len; 3421 3422 /* Set up data transaction */ 3423 if (len != 0) { 3424 ehci_soft_qtd_t *end; 3425 3426 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3427 NULL, newinactive, &next, &end); 3428 if (err) 3429 goto bad3; 3430 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3431 end->nextqtd = stat; 3432 end->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(stat)); 3433 end->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3434 } else { 3435 next = stat; 3436 } 3437 3438 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3439 3440 /* Clear toggle, and do not activate until complete */ 3441 setup->qtd.qtd_status = htole32( 3442 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3443 EHCI_QTD_SET_CERR(3) | 3444 EHCI_QTD_SET_TOGGLE(0) | 3445 EHCI_QTD_SET_BYTES(sizeof *req) 3446 ); 3447 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3448 setup->qtd.qtd_buffer_hi[0] = 0; 3449 setup->nextqtd = next; 3450 setup->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(next)); 3451 setup->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3452 setup->xfer = xfer; 3453 setup->len = sizeof *req; 3454 EHCI_SQTD_SYNC(sc, setup, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3455 3456 stat->qtd.qtd_status = htole32( 3457 EHCI_QTD_ACTIVE | 3458 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3459 EHCI_QTD_SET_CERR(3) | 3460 EHCI_QTD_SET_TOGGLE(1) | 3461 EHCI_QTD_IOC 3462 ); 3463 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3464 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3465 stat->nextqtd = newinactive; 3466 stat->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3467 stat->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3468 stat->xfer = xfer; 3469 stat->len = 0; 3470 EHCI_SQTD_SYNC(sc, stat, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3471 3472 #ifdef EHCI_DEBUG 3473 if (ehcidebug > 5) { 3474 DPRINTF(("ehci_device_request:\n")); 3475 ehci_dump_sqh(sqh); 3476 ehci_dump_sqtds(setup); 3477 } 3478 #endif 3479 3480 exfer->sqtdstart = setup; 3481 exfer->sqtdend = stat; 3482 #ifdef DIAGNOSTIC 3483 if (!exfer->isdone) { 3484 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3485 } 3486 exfer->isdone = 0; 3487 #endif 3488 3489 /* Activate the new qTD in the QH list. */ 3490 s = splusb(); 3491 ehci_activate_qh(sc, sqh, setup); 3492 if (xfer->timeout && !sc->sc_bus.use_polling) { 3493 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 3494 ehci_timeout, xfer); 3495 } 3496 ehci_add_intr_list(sc, exfer); 3497 xfer->status = USBD_IN_PROGRESS; 3498 splx(s); 3499 3500 #ifdef EHCI_DEBUG 3501 if (ehcidebug > 10) { 3502 DPRINTF(("ehci_device_request: status=%x\n", 3503 EOREAD4(sc, EHCI_USBSTS))); 3504 delay(10000); 3505 ehci_dump_regs(sc); 3506 ehci_dump_sqh(sc->sc_async_head); 3507 ehci_dump_sqh(sqh); 3508 ehci_dump_sqtds(setup); 3509 } 3510 #endif 3511 3512 return (USBD_NORMAL_COMPLETION); 3513 3514 bad3: 3515 sqh->inactivesqtd = setup; 3516 ehci_free_sqtd(sc, stat); 3517 bad2: 3518 ehci_free_sqtd(sc, newinactive); 3519 bad1: 3520 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3521 xfer->status = err; 3522 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, 3523 &EXFER(xfer)->dmabuf); 3524 return (err); 3525 #undef exfer 3526 } 3527 3528 /************************/ 3529 3530 Static usbd_status 3531 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3532 { 3533 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3534 usbd_status err; 3535 3536 /* Insert last in queue. */ 3537 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3538 &EXFER(xfer)->dmabuf); 3539 if (err) 3540 return (err); 3541 3542 /* Pipe isn't running, start first */ 3543 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3544 } 3545 3546 usbd_status 3547 ehci_device_bulk_start(usbd_xfer_handle xfer) 3548 { 3549 #define exfer EXFER(xfer) 3550 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3551 usbd_device_handle dev = epipe->pipe.device; 3552 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3553 ehci_soft_qtd_t *data, *dataend, *newinactive; 3554 ehci_soft_qh_t *sqh; 3555 usbd_status err; 3556 int len, isread, endpt; 3557 int s; 3558 3559 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3560 xfer, xfer->length, xfer->flags)); 3561 3562 if (sc->sc_dying) 3563 return (USBD_IOERROR); 3564 3565 #ifdef DIAGNOSTIC 3566 if (xfer->rqflags & URQ_REQUEST) 3567 panic("ehci_device_bulk_start: a request"); 3568 #endif 3569 3570 len = xfer->length; 3571 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3572 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3573 sqh = epipe->sqh; 3574 3575 epipe->u.bulk.length = len; 3576 3577 newinactive = ehci_alloc_sqtd(sc); 3578 if (newinactive == NULL) { 3579 DPRINTFN(-1,("ehci_device_bulk_start: no sqtd memory\n")); 3580 err = USBD_NOMEM; 3581 xfer->status = err; 3582 usb_transfer_complete(xfer); 3583 return (err); 3584 } 3585 newinactive->qtd.qtd_status = htole32(0); 3586 newinactive->qtd.qtd_next = EHCI_NULL; 3587 newinactive->qtd.qtd_altnext = EHCI_NULL; 3588 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3589 sqh->inactivesqtd, newinactive, &data, &dataend); 3590 if (err) { 3591 DPRINTFN(-1,("ehci_device_bulk_start: no memory\n")); 3592 ehci_free_sqtd(sc, newinactive); 3593 xfer->status = err; 3594 usb_transfer_complete(xfer); 3595 return (err); 3596 } 3597 dataend->nextqtd = newinactive; 3598 dataend->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3599 dataend->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3600 sqh->inactivesqtd = newinactive; 3601 EHCI_SQTD_SYNC(sc, newinactive, 3602 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3603 EHCI_SQTD_SYNC(sc, dataend, 3604 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3605 3606 #ifdef EHCI_DEBUG 3607 if (ehcidebug > 5) { 3608 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3609 ehci_dump_sqh(sqh); 3610 ehci_dump_sqtds(data); 3611 } 3612 #endif 3613 3614 /* Set up interrupt info. */ 3615 exfer->sqtdstart = data; 3616 exfer->sqtdend = dataend; 3617 #ifdef DIAGNOSTIC 3618 if (!exfer->isdone) { 3619 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3620 } 3621 exfer->isdone = 0; 3622 #endif 3623 3624 s = splusb(); 3625 ehci_activate_qh(sc, sqh, data); 3626 if (xfer->timeout && !sc->sc_bus.use_polling) { 3627 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 3628 ehci_timeout, xfer); 3629 } 3630 ehci_add_intr_list(sc, exfer); 3631 xfer->status = USBD_IN_PROGRESS; 3632 splx(s); 3633 3634 #ifdef EHCI_DEBUG 3635 if (ehcidebug > 10) { 3636 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3637 delay(10000); 3638 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3639 ehci_dump_regs(sc); 3640 #if 0 3641 printf("async_head:\n"); 3642 ehci_dump_sqh(sc->sc_async_head); 3643 #endif 3644 printf("sqh:\n"); 3645 ehci_dump_sqh(sqh); 3646 ehci_dump_sqtds(data); 3647 } 3648 #endif 3649 3650 if (sc->sc_bus.use_polling) 3651 ehci_waitintr(sc, xfer); 3652 3653 return (USBD_IN_PROGRESS); 3654 #undef exfer 3655 } 3656 3657 Static void 3658 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3659 { 3660 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3661 ehci_abort_xfer(xfer, USBD_CANCELLED); 3662 } 3663 3664 /* 3665 * Close a device bulk pipe. 3666 */ 3667 Static void 3668 ehci_device_bulk_close(usbd_pipe_handle pipe) 3669 { 3670 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3671 3672 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3673 ehci_close_pipe(pipe, sc->sc_async_head); 3674 } 3675 3676 void 3677 ehci_device_bulk_done(usbd_xfer_handle xfer) 3678 { 3679 struct ehci_xfer *ex = EXFER(xfer); 3680 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3681 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3682 3683 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3684 xfer, xfer->actlen)); 3685 3686 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3687 ehci_del_intr_list(ex); /* remove from active list */ 3688 ehci_free_sqtd_chain(sc, epipe->sqh, ex->sqtdstart, 3689 ex->sqtdend->nextqtd); 3690 } 3691 3692 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3693 } 3694 3695 /************************/ 3696 3697 Static usbd_status 3698 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3699 { 3700 struct ehci_soft_islot *isp; 3701 int islot, lev; 3702 3703 /* Find a poll rate that is large enough. */ 3704 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3705 if (EHCI_ILEV_IVAL(lev) <= ival) 3706 break; 3707 3708 /* Pick an interrupt slot at the right level. */ 3709 /* XXX could do better than picking at random. */ 3710 islot = EHCI_IQHIDX(lev, arc4random()); 3711 3712 sqh->islot = islot; 3713 isp = &sc->sc_islots[islot]; 3714 ehci_add_qh(sc, sqh, isp->sqh); 3715 3716 return (USBD_NORMAL_COMPLETION); 3717 } 3718 3719 Static usbd_status 3720 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3721 { 3722 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3723 usbd_status err; 3724 3725 /* Insert last in queue. */ 3726 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3727 &EXFER(xfer)->dmabuf); 3728 if (err) 3729 return (err); 3730 3731 /* 3732 * Pipe isn't running (otherwise err would be USBD_INPROG), 3733 * so start it first. 3734 */ 3735 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3736 } 3737 3738 Static usbd_status 3739 ehci_device_intr_start(usbd_xfer_handle xfer) 3740 { 3741 #define exfer EXFER(xfer) 3742 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3743 usbd_device_handle dev = xfer->pipe->device; 3744 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3745 ehci_soft_qtd_t *data, *dataend, *newinactive; 3746 ehci_soft_qh_t *sqh; 3747 usbd_status err; 3748 int len, isread, endpt; 3749 int s; 3750 3751 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3752 xfer, xfer->length, xfer->flags)); 3753 3754 if (sc->sc_dying) 3755 return (USBD_IOERROR); 3756 3757 #ifdef DIAGNOSTIC 3758 if (xfer->rqflags & URQ_REQUEST) 3759 panic("ehci_device_intr_start: a request"); 3760 #endif 3761 3762 len = xfer->length; 3763 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3764 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3765 sqh = epipe->sqh; 3766 3767 epipe->u.intr.length = len; 3768 3769 newinactive = ehci_alloc_sqtd(sc); 3770 if (newinactive == NULL) { 3771 DPRINTFN(-1,("ehci_device_intr_start: no sqtd memory\n")); 3772 err = USBD_NOMEM; 3773 xfer->status = err; 3774 usb_transfer_complete(xfer); 3775 return (err); 3776 } 3777 newinactive->qtd.qtd_status = htole32(0); 3778 newinactive->qtd.qtd_next = EHCI_NULL; 3779 newinactive->qtd.qtd_altnext = EHCI_NULL; 3780 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3781 sqh->inactivesqtd, newinactive, &data, &dataend); 3782 if (err) { 3783 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3784 xfer->status = err; 3785 usb_transfer_complete(xfer); 3786 return (err); 3787 } 3788 dataend->nextqtd = newinactive; 3789 dataend->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3790 dataend->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3791 sqh->inactivesqtd = newinactive; 3792 EHCI_SQTD_SYNC(sc, newinactive, 3793 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3794 EHCI_SQTD_SYNC(sc, dataend, 3795 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3796 3797 #ifdef EHCI_DEBUG 3798 if (ehcidebug > 5) { 3799 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3800 ehci_dump_sqh(sqh); 3801 ehci_dump_sqtds(data); 3802 } 3803 #endif 3804 3805 /* Set up interrupt info. */ 3806 exfer->sqtdstart = data; 3807 exfer->sqtdend = dataend; 3808 #ifdef DIAGNOSTIC 3809 if (!exfer->isdone) { 3810 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3811 } 3812 exfer->isdone = 0; 3813 #endif 3814 3815 s = splusb(); 3816 ehci_activate_qh(sc, sqh, data); 3817 if (xfer->timeout && !sc->sc_bus.use_polling) { 3818 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 3819 ehci_timeout, xfer); 3820 } 3821 ehci_add_intr_list(sc, exfer); 3822 xfer->status = USBD_IN_PROGRESS; 3823 splx(s); 3824 3825 #ifdef EHCI_DEBUG 3826 if (ehcidebug > 10) { 3827 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3828 delay(10000); 3829 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3830 ehci_dump_regs(sc); 3831 printf("sqh:\n"); 3832 ehci_dump_sqh(sqh); 3833 ehci_dump_sqtds(data); 3834 } 3835 #endif 3836 3837 if (sc->sc_bus.use_polling) 3838 ehci_waitintr(sc, xfer); 3839 3840 return (USBD_IN_PROGRESS); 3841 #undef exfer 3842 } 3843 3844 Static void 3845 ehci_device_intr_abort(usbd_xfer_handle xfer) 3846 { 3847 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3848 if (xfer->pipe->intrxfer == xfer) { 3849 DPRINTFN(1, ("ehci_device_intr_abort: remove\n")); 3850 xfer->pipe->intrxfer = NULL; 3851 } 3852 ehci_abort_xfer(xfer, USBD_CANCELLED); 3853 } 3854 3855 Static void 3856 ehci_device_intr_close(usbd_pipe_handle pipe) 3857 { 3858 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3859 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3860 struct ehci_soft_islot *isp; 3861 3862 isp = &sc->sc_islots[epipe->sqh->islot]; 3863 ehci_close_pipe(pipe, isp->sqh); 3864 } 3865 3866 Static void 3867 ehci_device_intr_done(usbd_xfer_handle xfer) 3868 { 3869 #define exfer EXFER(xfer) 3870 struct ehci_xfer *ex = EXFER(xfer); 3871 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3872 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3873 ehci_soft_qtd_t *data, *dataend, *newinactive; 3874 ehci_soft_qh_t *sqh; 3875 usbd_status err; 3876 int len, isread, endpt, s; 3877 3878 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3879 xfer, xfer->actlen)); 3880 3881 sqh = epipe->sqh; 3882 if (xfer->pipe->repeat) { 3883 ehci_free_sqtd_chain(sc, sqh, ex->sqtdstart, 3884 ex->sqtdend->nextqtd); 3885 3886 len = epipe->u.intr.length; 3887 xfer->length = len; 3888 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3889 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3890 3891 newinactive = ehci_alloc_sqtd(sc); 3892 if (newinactive == NULL) { 3893 DPRINTFN(-1, 3894 ("ehci_device_intr_done: no sqtd memory\n")); 3895 err = USBD_NOMEM; 3896 xfer->status = err; 3897 return; 3898 } 3899 newinactive->qtd.qtd_status = htole32(0); 3900 newinactive->qtd.qtd_next = EHCI_NULL; 3901 newinactive->qtd.qtd_altnext = EHCI_NULL; 3902 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3903 sqh->inactivesqtd, newinactive, &data, &dataend); 3904 if (err) { 3905 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3906 xfer->status = err; 3907 return; 3908 } 3909 dataend->nextqtd = newinactive; 3910 dataend->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3911 dataend->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3912 sqh->inactivesqtd = newinactive; 3913 EHCI_SQTD_SYNC(sc, newinactive, 3914 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3915 EHCI_SQTD_SYNC(sc, dataend, 3916 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3917 3918 /* Set up interrupt info. */ 3919 exfer->sqtdstart = data; 3920 exfer->sqtdend = dataend; 3921 #ifdef DIAGNOSTIC 3922 if (!exfer->isdone) { 3923 printf("ehci_device_intr_done: not done, ex=%p\n", 3924 exfer); 3925 } 3926 exfer->isdone = 0; 3927 #endif 3928 3929 s = splusb(); 3930 ehci_activate_qh(sc, sqh, data); 3931 if (xfer->timeout && !sc->sc_bus.use_polling) { 3932 usb_callout(xfer->timeout_handle, 3933 MS_TO_TICKS(xfer->timeout), ehci_timeout, xfer); 3934 } 3935 splx(s); 3936 3937 xfer->status = USBD_IN_PROGRESS; 3938 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3939 ehci_del_intr_list(ex); /* remove from active list */ 3940 ehci_free_sqtd_chain(sc, sqh, ex->sqtdstart, 3941 ex->sqtdend->nextqtd); 3942 } 3943 #undef exfer 3944 } 3945 3946 /************************/ 3947 3948 Static usbd_status 3949 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3950 { 3951 return USBD_IOERROR; 3952 } 3953 Static usbd_status 3954 ehci_device_isoc_start(usbd_xfer_handle xfer) 3955 { 3956 return USBD_IOERROR; 3957 } 3958 Static void 3959 ehci_device_isoc_abort(usbd_xfer_handle xfer) 3960 { 3961 } 3962 Static void 3963 ehci_device_isoc_close(usbd_pipe_handle pipe) 3964 { 3965 } 3966 Static void 3967 ehci_device_isoc_done(usbd_xfer_handle xfer) 3968 { 3969 } 3970
Indexes created Thu Oct 02 01:09:59 GMT 2025