ehci.c revision 1.123.12.6
1 /* $NetBSD: ehci.c,v 1.123.12.6 2009/11/13 02:04:49 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 2004, 2005, 2007 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 41 * 42 * The EHCI 1.0 spec can be found at 43 * http://www.intel.com/technology/usb/spec.htm 44 * and the USB 2.0 spec at 45 * http://www.usb.org/developers/docs/ 46 * 47 */ 48 49 /* 50 * TODO: 51 * 1) The EHCI driver lacks support for isochronous transfers, so 52 * devices using them don't work. 53 * 54 * 2) Interrupt transfer scheduling does not manage the time available 55 * in each frame, so it is possible for the transfers to overrun 56 * the end of the frame. 57 * 58 * 3) Command failures are not recovered correctly. 59 */ 60 61 #include <sys/cdefs.h> 62 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.123.12.6 2009/11/13 02:04:49 uebayasi Exp $"); 63 /* __FBSDID("$FreeBSD: /repoman/r/ncvs/src/sys/dev/usb/ehci.c,v 1.52 2006/10/19 01:15:58 iedowse Exp $"); */ 64 65 #if defined(__NetBSD__) || defined(__OpenBSD__) 66 #include "ohci.h" 67 #include "uhci.h" 68 #endif 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/kernel.h> 73 #include <sys/malloc.h> 74 #if defined(__NetBSD__) || defined(__OpenBSD__) 75 #include <sys/device.h> 76 #include <sys/select.h> 77 #elif defined(__FreeBSD__) 78 #include <sys/endian.h> 79 #include <sys/module.h> 80 #include <sys/bus.h> 81 #include <sys/lockmgr.h> 82 #if defined(DIAGNOSTIC) && defined(__i386__) && defined(__FreeBSD__) 83 #include <machine/cpu.h> 84 #endif 85 #endif 86 #include <sys/proc.h> 87 #include <sys/queue.h> 88 #include <sys/sysctl.h> 89 90 #include <machine/bus.h> 91 #include <machine/endian.h> 92 93 #include <dev/usb/usb.h> 94 #include <dev/usb/usbdi.h> 95 #include <dev/usb/usbdivar.h> 96 #include <dev/usb/usb_mem.h> 97 #include <dev/usb/usb_quirks.h> 98 99 #include <dev/usb/ehcireg.h> 100 #include <dev/usb/ehcivar.h> 101 102 #if defined(__FreeBSD__) 103 104 #define delay(d) DELAY(d) 105 #endif 106 107 #ifdef USB_DEBUG 108 /* #define EHCI_DEBUG USB_DEBUG */ 109 #define DPRINTF(x) do { if (ehcidebug) logprintf x; } while (0) 110 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) logprintf x; } while (0) 111 int ehcidebug = 0; 112 #ifdef __FreeBSD__ 113 SYSCTL_NODE(_hw_usb, OID_AUTO, ehci, CTLFLAG_RW, 0, "USB ehci"); 114 SYSCTL_INT(_hw_usb_ehci, OID_AUTO, debug, CTLFLAG_RW, 115 &ehcidebug, 0, "ehci debug level"); 116 #endif 117 #ifndef __NetBSD__ 118 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 119 #endif 120 #else 121 #define DPRINTF(x) 122 #define DPRINTFN(n,x) 123 #endif 124 125 struct ehci_pipe { 126 struct usbd_pipe pipe; 127 128 ehci_soft_qh_t *sqh; 129 union { 130 ehci_soft_qtd_t *qtd; 131 /* ehci_soft_itd_t *itd; */ 132 } tail; 133 union { 134 /* Control pipe */ 135 struct { 136 usb_dma_t reqdma; 137 u_int length; 138 } ctl; 139 /* Interrupt pipe */ 140 struct { 141 u_int length; 142 } intr; 143 /* Bulk pipe */ 144 struct { 145 u_int length; 146 } bulk; 147 /* Iso pipe */ 148 struct { 149 u_int next_frame; 150 u_int cur_xfers; 151 } isoc; 152 } u; 153 }; 154 155 Static usbd_status ehci_open(usbd_pipe_handle); 156 Static void ehci_poll(struct usbd_bus *); 157 Static void ehci_softintr(void *); 158 Static int ehci_intr1(ehci_softc_t *); 159 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 160 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 161 Static void ehci_idone(struct ehci_xfer *); 162 Static void ehci_timeout(void *); 163 Static void ehci_timeout_task(void *); 164 Static void ehci_intrlist_timeout(void *); 165 166 Static void ehci_aux_mem_init(struct ehci_aux_mem *); 167 Static usbd_status ehci_aux_mem_alloc(ehci_softc_t *, 168 struct ehci_aux_mem *, 169 int /*naux*/, int /*maxp*/); 170 Static void ehci_aux_mem_free(ehci_softc_t *, 171 struct ehci_aux_mem *); 172 struct aux_desc { 173 void *aux_kern; 174 }; 175 Static bus_addr_t ehci_aux_dma_alloc(struct ehci_aux_mem *, int, 176 struct aux_desc *); 177 Static void ehci_aux_dma_sync(ehci_softc_t *, 178 struct ehci_aux_mem *, int /*op*/); 179 180 Static usbd_status ehci_prealloc(struct ehci_softc *, struct ehci_xfer *, 181 size_t, int); 182 Static usbd_status ehci_allocm(struct usbd_bus *, usbd_xfer_handle, 183 void *, size_t); 184 Static void ehci_freem(struct usbd_bus *, usbd_xfer_handle, 185 enum usbd_waitflg); 186 187 Static usbd_status ehci_map_alloc(usbd_xfer_handle); 188 Static void ehci_map_free(usbd_xfer_handle); 189 Static void ehci_mapm(usbd_xfer_handle, void *, size_t); 190 Static usbd_status ehci_mapm_mbuf(usbd_xfer_handle, struct mbuf *); 191 Static void ehci_unmapm(usbd_xfer_handle); 192 193 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *, usbd_pipe_handle, 194 enum usbd_waitflg); 195 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 196 197 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 198 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 199 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 200 Static void ehci_root_ctrl_close(usbd_pipe_handle); 201 Static void ehci_root_ctrl_done(usbd_xfer_handle); 202 203 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 204 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 205 Static void ehci_root_intr_abort(usbd_xfer_handle); 206 Static void ehci_root_intr_close(usbd_pipe_handle); 207 Static void ehci_root_intr_done(usbd_xfer_handle); 208 209 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 210 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 211 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 212 Static void ehci_device_ctrl_close(usbd_pipe_handle); 213 Static void ehci_device_ctrl_done(usbd_xfer_handle); 214 215 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 216 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 217 Static void ehci_device_bulk_abort(usbd_xfer_handle); 218 Static void ehci_device_bulk_close(usbd_pipe_handle); 219 Static void ehci_device_bulk_done(usbd_xfer_handle); 220 221 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 222 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 223 Static void ehci_device_intr_abort(usbd_xfer_handle); 224 Static void ehci_device_intr_close(usbd_pipe_handle); 225 Static void ehci_device_intr_done(usbd_xfer_handle); 226 227 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 228 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 229 Static void ehci_device_isoc_abort(usbd_xfer_handle); 230 Static void ehci_device_isoc_close(usbd_pipe_handle); 231 Static void ehci_device_isoc_done(usbd_xfer_handle); 232 233 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 234 Static void ehci_noop(usbd_pipe_handle pipe); 235 236 Static int ehci_str(usb_string_descriptor_t *, int, const char *); 237 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 238 Static void ehci_disown(ehci_softc_t *, int, int); 239 240 Static usbd_status ehci_grow_sqtd(ehci_softc_t *); 241 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 242 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 243 244 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 245 Static ehci_soft_qtd_t *ehci_alloc_sqtd_norsv(ehci_softc_t *); 246 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 247 Static void ehci_free_sqtd_norsv(ehci_softc_t *, ehci_soft_qtd_t *); 248 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 249 ehci_softc_t *, int, int, usbd_xfer_handle, 250 ehci_soft_qtd_t *, ehci_soft_qtd_t *, 251 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 252 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qh_t *, 253 ehci_soft_qtd_t *, ehci_soft_qtd_t *); 254 Static void ehci_free_desc_chunks(ehci_softc_t *, 255 struct ehci_mdescs *); 256 257 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 258 259 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 260 int ival); 261 262 Static void ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *, 263 ehci_soft_qh_t *); 264 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 265 ehci_soft_qh_t *); 266 Static void ehci_activate_qh(ehci_softc_t *, ehci_soft_qh_t *, 267 ehci_soft_qtd_t *); 268 Static void ehci_sync_hc(ehci_softc_t *); 269 270 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 271 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 272 273 #ifdef EHCI_DEBUG 274 Static void ehci_dump_regs(ehci_softc_t *); 275 void ehci_dump(void); 276 Static ehci_softc_t *theehci; 277 Static void ehci_dump_link(ehci_link_t, int); 278 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 279 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 280 Static void ehci_dump_qtd(ehci_qtd_t *); 281 Static void ehci_dump_sqh(ehci_soft_qh_t *); 282 #ifdef DIAGNOSTIC 283 Static void ehci_dump_exfer(struct ehci_xfer *); 284 #endif 285 #endif 286 287 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 288 289 #define EHCI_INTR_ENDPT 1 290 291 #define ehci_add_intr_list(sc, ex) \ 292 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext); 293 #define ehci_del_intr_list(ex) \ 294 do { \ 295 LIST_REMOVE((ex), inext); \ 296 (ex)->inext.le_prev = NULL; \ 297 } while (0) 298 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL) 299 300 Static const struct usbd_bus_methods ehci_bus_methods = { 301 ehci_open, 302 ehci_softintr, 303 ehci_poll, 304 ehci_allocm, 305 ehci_freem, 306 ehci_allocx, 307 ehci_freex, 308 ehci_map_alloc, 309 ehci_map_free, 310 ehci_mapm, 311 ehci_mapm_mbuf, 312 ehci_unmapm, 313 }; 314 315 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 316 ehci_root_ctrl_transfer, 317 ehci_root_ctrl_start, 318 ehci_root_ctrl_abort, 319 ehci_root_ctrl_close, 320 ehci_noop, 321 ehci_root_ctrl_done, 322 }; 323 324 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 325 ehci_root_intr_transfer, 326 ehci_root_intr_start, 327 ehci_root_intr_abort, 328 ehci_root_intr_close, 329 ehci_noop, 330 ehci_root_intr_done, 331 }; 332 333 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 334 ehci_device_ctrl_transfer, 335 ehci_device_ctrl_start, 336 ehci_device_ctrl_abort, 337 ehci_device_ctrl_close, 338 ehci_noop, 339 ehci_device_ctrl_done, 340 }; 341 342 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 343 ehci_device_intr_transfer, 344 ehci_device_intr_start, 345 ehci_device_intr_abort, 346 ehci_device_intr_close, 347 ehci_device_clear_toggle, 348 ehci_device_intr_done, 349 }; 350 351 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 352 ehci_device_bulk_transfer, 353 ehci_device_bulk_start, 354 ehci_device_bulk_abort, 355 ehci_device_bulk_close, 356 ehci_device_clear_toggle, 357 ehci_device_bulk_done, 358 }; 359 360 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 361 ehci_device_isoc_transfer, 362 ehci_device_isoc_start, 363 ehci_device_isoc_abort, 364 ehci_device_isoc_close, 365 ehci_noop, 366 ehci_device_isoc_done, 367 }; 368 369 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 370 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 371 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 372 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 373 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 374 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 375 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 376 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 377 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 378 }; 379 380 usbd_status 381 ehci_init(ehci_softc_t *sc) 382 { 383 u_int32_t vers, sparams, cparams, hcr; 384 u_int i; 385 usbd_status err; 386 ehci_soft_qh_t *sqh; 387 u_int ncomp; 388 int lev; 389 390 DPRINTF(("ehci_init: start\n")); 391 #ifdef EHCI_DEBUG 392 theehci = sc; 393 #endif 394 395 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 396 397 vers = EREAD2(sc, EHCI_HCIVERSION); 398 aprint_verbose("%s: EHCI version %x.%x\n", USBDEVNAME(sc->sc_bus.bdev), 399 vers >> 8, vers & 0xff); 400 401 sparams = EREAD4(sc, EHCI_HCSPARAMS); 402 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 403 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 404 ncomp = EHCI_HCS_N_CC(sparams); 405 if (ncomp != sc->sc_ncomp) { 406 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 407 USBDEVNAME(sc->sc_bus.bdev), 408 ncomp, sc->sc_ncomp); 409 if (ncomp < sc->sc_ncomp) 410 sc->sc_ncomp = ncomp; 411 } 412 if (sc->sc_ncomp > 0) { 413 printf("%s: companion controller%s, %d port%s each:", 414 USBDEVNAME(sc->sc_bus.bdev), sc->sc_ncomp!=1 ? "s" : "", 415 EHCI_HCS_N_PCC(sparams), 416 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 417 for (i = 0; i < sc->sc_ncomp; i++) 418 printf(" %s", USBDEVNAME(sc->sc_comps[i]->bdev)); 419 printf("\n"); 420 } 421 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 422 cparams = EREAD4(sc, EHCI_HCCPARAMS); 423 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 424 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 425 426 if (EHCI_HCC_64BIT(cparams)) { 427 /* MUST clear segment register if 64 bit capable. */ 428 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 429 } 430 431 sc->sc_bus.usbrev = USBREV_2_0; 432 usb_dma_tag_init(&sc->sc_dmatag); 433 434 /* Reset the controller */ 435 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 436 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 437 usb_delay_ms(&sc->sc_bus, 1); 438 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 439 for (i = 0; i < 100; i++) { 440 usb_delay_ms(&sc->sc_bus, 1); 441 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 442 if (!hcr) 443 break; 444 } 445 if (hcr) { 446 printf("%s: reset timeout\n", 447 USBDEVNAME(sc->sc_bus.bdev)); 448 return (USBD_IOERROR); 449 } 450 451 /* frame list size at default, read back what we got and use that */ 452 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 453 case 0: sc->sc_flsize = 1024; break; 454 case 1: sc->sc_flsize = 512; break; 455 case 2: sc->sc_flsize = 256; break; 456 case 3: return (USBD_IOERROR); 457 } 458 err = usb_allocmem(&sc->sc_dmatag, sc->sc_flsize * sizeof(ehci_link_t), 459 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 460 if (err) 461 return (err); 462 DPRINTF(("%s: flsize=%d\n", USBDEVNAME(sc->sc_bus.bdev),sc->sc_flsize)); 463 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 464 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 465 466 /* Set up the bus struct. */ 467 sc->sc_bus.methods = &ehci_bus_methods; 468 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 469 470 #if defined(__NetBSD__) || defined(__OpenBSD__) 471 sc->sc_powerhook = powerhook_establish(USBDEVNAME(sc->sc_bus.bdev), 472 ehci_power, sc); 473 sc->sc_shutdownhook = shutdownhook_establish(ehci_shutdown, sc); 474 #endif 475 476 sc->sc_eintrs = EHCI_NORMAL_INTRS; 477 478 /* 479 * Allocate the interrupt dummy QHs. These are arranged to give 480 * poll intervals that are powers of 2 times 1ms. 481 */ 482 for (i = 0; i < EHCI_INTRQHS; i++) { 483 sqh = ehci_alloc_sqh(sc); 484 if (sqh == NULL) { 485 err = USBD_NOMEM; 486 goto bad1; 487 } 488 sc->sc_islots[i].sqh = sqh; 489 } 490 lev = 0; 491 for (i = 0; i < EHCI_INTRQHS; i++) { 492 if (i == EHCI_IQHIDX(lev + 1, 0)) 493 lev++; 494 sqh = sc->sc_islots[i].sqh; 495 if (i == 0) { 496 /* The last (1ms) QH terminates. */ 497 sqh->qh.qh_link = EHCI_NULL; 498 sqh->next = NULL; 499 } else { 500 /* Otherwise the next QH has half the poll interval */ 501 sqh->next = 502 sc->sc_islots[EHCI_IQHIDX(lev - 1, i + 1)].sqh; 503 sqh->qh.qh_link = htole32(EHCI_SQH_DMAADDR(sqh->next) | 504 EHCI_LINK_QH); 505 } 506 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 507 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 508 sqh->qh.qh_curqtd = EHCI_NULL; 509 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 510 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 511 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 512 } 513 /* Point the frame list at the last level (128ms). */ 514 for (i = 0; i < sc->sc_flsize; i++) { 515 int j; 516 517 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 518 revbits[i & (EHCI_MAX_POLLRATE-1)]; 519 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 520 EHCI_SQH_DMAADDR(sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES 521 - 1, i)].sqh)); 522 } 523 EHCI_SQH_SYNC(sc, sqh, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 524 525 /* Allocate dummy QH that starts the async list. */ 526 sqh = ehci_alloc_sqh(sc); 527 if (sqh == NULL) { 528 err = USBD_NOMEM; 529 goto bad1; 530 } 531 /* Fill the QH */ 532 sqh->qh.qh_endp = 533 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 534 sqh->qh.qh_link = 535 htole32(EHCI_SQH_DMAADDR(sqh) | EHCI_LINK_QH); 536 sqh->qh.qh_curqtd = EHCI_NULL; 537 sqh->prev = sqh; /*It's a circular list.. */ 538 sqh->next = sqh; 539 /* Fill the overlay qTD */ 540 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 541 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 542 sqh->qh.qh_qtd.qtd_status = htole32(0); 543 #ifdef EHCI_DEBUG 544 if (ehcidebug) { 545 ehci_dump_sqh(sqh); 546 } 547 #endif 548 EHCI_SQH_SYNC(sc, sqh, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 549 550 /* Point to async list */ 551 sc->sc_async_head = sqh; 552 EOWRITE4(sc, EHCI_ASYNCLISTADDR, EHCI_SQH_DMAADDR(sqh) | EHCI_LINK_QH); 553 554 usb_callout_init(sc->sc_tmo_intrlist); 555 556 lockinit(&sc->sc_doorbell_lock, PZERO, "ehcidb", 0, 0); 557 558 /* Enable interrupts */ 559 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 560 561 /* Turn on controller */ 562 EOWRITE4(sc, EHCI_USBCMD, 563 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 564 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 565 EHCI_CMD_ASE | 566 EHCI_CMD_PSE | 567 EHCI_CMD_RS); 568 569 /* Take over port ownership */ 570 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 571 572 for (i = 0; i < 100; i++) { 573 usb_delay_ms(&sc->sc_bus, 1); 574 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 575 if (!hcr) 576 break; 577 } 578 if (hcr) { 579 printf("%s: run timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 580 return (USBD_IOERROR); 581 } 582 583 /* Enable interrupts */ 584 DPRINTFN(1,("ehci_init: enabling\n")); 585 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 586 587 return (USBD_NORMAL_COMPLETION); 588 589 #if 0 590 bad2: 591 ehci_free_sqh(sc, sc->sc_async_head); 592 #endif 593 bad1: 594 usb_freemem(&sc->sc_dmatag, &sc->sc_fldma); 595 usb_dma_tag_finish(&sc->sc_dmatag); 596 return (err); 597 } 598 599 int 600 ehci_intr(void *v) 601 { 602 ehci_softc_t *sc = v; 603 604 if (sc == NULL || sc->sc_dying) 605 return (0); 606 607 /* If we get an interrupt while polling, then just ignore it. */ 608 if (sc->sc_bus.use_polling) { 609 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 610 611 if (intrs) 612 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 613 #ifdef DIAGNOSTIC 614 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 615 #endif 616 return (0); 617 } 618 619 return (ehci_intr1(sc)); 620 } 621 622 Static int 623 ehci_intr1(ehci_softc_t *sc) 624 { 625 u_int32_t intrs, eintrs; 626 627 DPRINTFN(20,("ehci_intr1: enter\n")); 628 629 /* In case the interrupt occurs before initialization has completed. */ 630 if (sc == NULL) { 631 #ifdef DIAGNOSTIC 632 printf("ehci_intr1: sc == NULL\n"); 633 #endif 634 return (0); 635 } 636 637 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 638 if (!intrs) 639 return (0); 640 641 eintrs = intrs & sc->sc_eintrs; 642 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 643 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 644 (u_int)eintrs)); 645 if (!eintrs) 646 return (0); 647 648 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 649 sc->sc_bus.intr_context++; 650 sc->sc_bus.no_intrs++; 651 if (eintrs & EHCI_STS_IAA) { 652 DPRINTF(("ehci_intr1: door bell\n")); 653 wakeup(&sc->sc_async_head); 654 eintrs &= ~EHCI_STS_IAA; 655 } 656 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 657 DPRINTFN(5,("ehci_intr1: %s %s\n", 658 eintrs & EHCI_STS_INT ? "INT" : "", 659 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 660 usb_schedsoftintr(&sc->sc_bus); 661 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 662 } 663 if (eintrs & EHCI_STS_HSE) { 664 printf("%s: unrecoverable error, controller halted\n", 665 USBDEVNAME(sc->sc_bus.bdev)); 666 /* XXX what else */ 667 } 668 if (eintrs & EHCI_STS_PCD) { 669 ehci_pcd(sc, sc->sc_intrxfer); 670 eintrs &= ~EHCI_STS_PCD; 671 } 672 673 sc->sc_bus.intr_context--; 674 675 if (eintrs != 0) { 676 /* Block unprocessed interrupts. */ 677 sc->sc_eintrs &= ~eintrs; 678 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 679 printf("%s: blocking intrs 0x%x\n", 680 USBDEVNAME(sc->sc_bus.bdev), eintrs); 681 } 682 683 return (1); 684 } 685 686 687 void 688 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 689 { 690 usbd_pipe_handle pipe; 691 u_char *p; 692 int i, m; 693 694 if (xfer == NULL) { 695 /* Just ignore the change. */ 696 return; 697 } 698 699 pipe = xfer->pipe; 700 701 p = xfer->hcbuffer; 702 m = min(sc->sc_noport, xfer->length * 8 - 1); 703 memset(p, 0, xfer->length); 704 for (i = 1; i <= m; i++) { 705 /* Pick out CHANGE bits from the status reg. */ 706 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 707 p[i/8] |= 1 << (i%8); 708 } 709 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 710 xfer->actlen = xfer->length; 711 xfer->status = USBD_NORMAL_COMPLETION; 712 713 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 714 } 715 716 void 717 ehci_softintr(void *v) 718 { 719 ehci_softc_t *sc = v; 720 struct ehci_xfer *ex, *nextex; 721 722 DPRINTFN(10,("%s: ehci_softintr (%d)\n", USBDEVNAME(sc->sc_bus.bdev), 723 sc->sc_bus.intr_context)); 724 725 sc->sc_bus.intr_context++; 726 727 /* 728 * The only explanation I can think of for why EHCI is as brain dead 729 * as UHCI interrupt-wise is that Intel was involved in both. 730 * An interrupt just tells us that something is done, we have no 731 * clue what, so we need to scan through all active transfers. :-( 732 */ 733 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 734 nextex = LIST_NEXT(ex, inext); 735 ehci_check_intr(sc, ex); 736 } 737 738 /* Schedule a callout to catch any dropped transactions. */ 739 if ((sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) && 740 !LIST_EMPTY(&sc->sc_intrhead)) 741 usb_callout(sc->sc_tmo_intrlist, hz / 5, ehci_intrlist_timeout, 742 sc); 743 744 /* Schedule a callout to catch any dropped transactions. */ 745 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 746 !LIST_EMPTY(&sc->sc_intrhead)) 747 usb_callout(sc->sc_tmo_intrlist, hz, 748 ehci_intrlist_timeout, sc); 749 750 #ifdef USB_USE_SOFTINTR 751 if (sc->sc_softwake) { 752 sc->sc_softwake = 0; 753 wakeup(&sc->sc_softwake); 754 } 755 #endif /* USB_USE_SOFTINTR */ 756 757 sc->sc_bus.intr_context--; 758 } 759 760 /* Check for an interrupt. */ 761 void 762 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 763 { 764 ehci_soft_qtd_t *sqtd, *lsqtd; 765 u_int32_t status; 766 767 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 768 769 if (ex->sqtdstart == NULL) { 770 printf("ehci_check_intr: sqtdstart=NULL\n"); 771 return; 772 } 773 lsqtd = ex->sqtdend; 774 #ifdef DIAGNOSTIC 775 if (lsqtd == NULL) { 776 printf("ehci_check_intr: lsqtd==0\n"); 777 return; 778 } 779 #endif 780 /* 781 * If the last TD is still active we need to check whether there 782 * is a an error somewhere in the middle, or whether there was a 783 * short packet (SPD and not ACTIVE). 784 */ 785 EHCI_SQTD_SYNC(sc, lsqtd, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 786 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 787 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 788 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 789 EHCI_SQTD_SYNC(sc, sqtd, 790 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 791 status = le32toh(sqtd->qtd.qtd_status); 792 /* If there's an active QTD the xfer isn't done. */ 793 if (status & EHCI_QTD_ACTIVE) 794 break; 795 /* Any kind of error makes the xfer done. */ 796 if (status & EHCI_QTD_HALTED) 797 goto done; 798 /* We want short packets, and it is short: it's done */ 799 if (EHCI_QTD_GET_BYTES(status) != 0) 800 goto done; 801 } 802 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 803 ex, ex->sqtdstart)); 804 return; 805 } 806 done: 807 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 808 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 809 usb_rem_task(ex->xfer.pipe->device, &ex->abort_task); 810 ehci_idone(ex); 811 } 812 813 void 814 ehci_idone(struct ehci_xfer *ex) 815 { 816 usbd_xfer_handle xfer = &ex->xfer; 817 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 818 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 819 ehci_soft_qtd_t *sqtd, *lsqtd; 820 u_int32_t status = 0, nstatus = 0; 821 ehci_physaddr_t nextphys, altnextphys; 822 ehci_physaddr_t stdma; 823 int actlen, cerr; 824 825 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 826 #ifdef DIAGNOSTIC 827 { 828 int s = splhigh(); 829 if (ex->isdone) { 830 splx(s); 831 #ifdef EHCI_DEBUG 832 printf("ehci_idone: ex is done!\n "); 833 ehci_dump_exfer(ex); 834 #else 835 printf("ehci_idone: ex=%p is done!\n", ex); 836 #endif 837 return; 838 } 839 ex->isdone = 1; 840 splx(s); 841 } 842 #endif 843 844 if (xfer->status == USBD_CANCELLED || 845 xfer->status == USBD_TIMEOUT) { 846 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 847 return; 848 } 849 850 #ifdef EHCI_DEBUG 851 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 852 if (ehcidebug > 10) 853 ehci_dump_sqtds(ex->sqtdstart); 854 #endif 855 856 /* 857 * Make sure that the QH overlay qTD does not reference any 858 * of the qTDs we are about to free. This is probably only 859 * necessary if the transfer is marked as HALTED. 860 */ 861 EHCI_SQH_SYNC(sc, epipe->sqh, 862 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 863 nextphys = EHCI_LINK_ADDR(le32toh(epipe->sqh->qh.qh_qtd.qtd_next)); 864 altnextphys = 865 EHCI_LINK_ADDR(le32toh(epipe->sqh->qh.qh_qtd.qtd_altnext)); 866 for (sqtd = ex->sqtdstart; sqtd != ex->sqtdend->nextqtd; 867 sqtd = sqtd->nextqtd) { 868 stdma = EHCI_SQTD_DMAADDR(sqtd); 869 if (stdma == nextphys) { 870 epipe->sqh->qh.qh_qtd.qtd_next = 871 htole32(EHCI_SQTD_DMAADDR(ex->sqtdend->nextqtd)); 872 DPRINTFN(4, ("ehci_idone: updated overlay next ptr\n")); 873 EHCI_SQH_SYNC(sc, epipe->sqh, 874 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 875 876 } 877 if (stdma == altnextphys) { 878 DPRINTFN(4, 879 ("ehci_idone: updated overlay altnext ptr\n")); 880 epipe->sqh->qh.qh_qtd.qtd_altnext = 881 htole32(EHCI_SQTD_DMAADDR(ex->sqtdend->nextqtd)); 882 EHCI_SQH_SYNC(sc, epipe->sqh, 883 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 884 } 885 } 886 887 /* The transfer is done, compute actual length and status. */ 888 lsqtd = ex->sqtdend; 889 actlen = 0; 890 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd=sqtd->nextqtd) { 891 EHCI_SQTD_SYNC(sc, sqtd, 892 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 893 nstatus = le32toh(sqtd->qtd.qtd_status); 894 if (nstatus & EHCI_QTD_ACTIVE) 895 break; 896 897 status = nstatus; 898 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 899 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 900 } 901 902 cerr = EHCI_QTD_GET_CERR(status); 903 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, " 904 "status=0x%x\n", xfer->length, actlen, cerr, status)); 905 xfer->actlen = actlen; 906 if ((status & EHCI_QTD_HALTED) != 0) { 907 #ifdef EHCI_DEBUG 908 char sbuf[128]; 909 910 bitmask_snprintf((u_int32_t)status, 911 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 912 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 913 914 DPRINTFN(2, 915 ("ehci_idone: error, addr=%d, endpt=0x%02x, " 916 "status 0x%s\n", 917 xfer->pipe->device->address, 918 xfer->pipe->endpoint->edesc->bEndpointAddress, 919 sbuf)); 920 if (ehcidebug > 2) { 921 ehci_dump_sqh(epipe->sqh); 922 ehci_dump_sqtds(ex->sqtdstart); 923 } 924 #endif 925 /* low&full speed has an extra error flag */ 926 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 927 EHCI_QH_SPEED_HIGH) 928 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 929 else 930 status &= EHCI_QTD_STATERRS; 931 if (status == 0) /* no other errors means a stall */ 932 xfer->status = USBD_STALLED; 933 else 934 xfer->status = USBD_IOERROR; /* more info XXX */ 935 /* XXX need to reset TT on missed microframe */ 936 if (status & EHCI_QTD_MISSEDMICRO) { 937 printf("%s: missed microframe, TT reset not " 938 "implemented, hub might be inoperational\n", 939 USBDEVNAME(sc->sc_bus.bdev)); 940 } 941 } else { 942 xfer->status = USBD_NORMAL_COMPLETION; 943 } 944 945 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 946 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 947 } 948 949 /* 950 * Wait here until controller claims to have an interrupt. 951 * Then call ehci_intr and return. Use timeout to avoid waiting 952 * too long. 953 */ 954 void 955 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 956 { 957 int timo; 958 u_int32_t intrs; 959 960 xfer->status = USBD_IN_PROGRESS; 961 for (timo = xfer->timeout; timo >= 0; timo--) { 962 usb_delay_ms(&sc->sc_bus, 1); 963 if (sc->sc_dying) 964 break; 965 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 966 sc->sc_eintrs; 967 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 968 #ifdef EHCI_DEBUG 969 if (ehcidebug > 15) 970 ehci_dump_regs(sc); 971 #endif 972 if (intrs) { 973 ehci_intr1(sc); 974 if (xfer->status != USBD_IN_PROGRESS) 975 return; 976 } 977 } 978 979 /* Timeout */ 980 DPRINTF(("ehci_waitintr: timeout\n")); 981 xfer->status = USBD_TIMEOUT; 982 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 983 /* XXX should free TD */ 984 } 985 986 void 987 ehci_poll(struct usbd_bus *bus) 988 { 989 ehci_softc_t *sc = (ehci_softc_t *)bus; 990 #ifdef EHCI_DEBUG 991 static int last; 992 int new; 993 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 994 if (new != last) { 995 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 996 last = new; 997 } 998 #endif 999 1000 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1001 ehci_intr1(sc); 1002 } 1003 1004 int 1005 ehci_detach(struct ehci_softc *sc, int flags) 1006 { 1007 int rv = 0; 1008 usbd_xfer_handle xfer; 1009 1010 #if defined(__NetBSD__) || defined(__OpenBSD__) 1011 if (sc->sc_child != NULL) 1012 rv = config_detach(sc->sc_child, flags); 1013 1014 if (rv != 0) 1015 return (rv); 1016 #else 1017 sc->sc_dying = 1; 1018 #endif 1019 1020 if (sc->sc_bus.methods == NULL) 1021 return (rv); /* attach has been aborted */ 1022 1023 #if defined(__NetBSD__) || defined(__OpenBSD__) 1024 /* Don't touch hardware if it has already been gone. */ 1025 if ((flags & DETACH_FORCE) == 0) 1026 #endif 1027 { 1028 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1029 EOWRITE4(sc, EHCI_USBCMD, 0); 1030 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1031 } 1032 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 1033 1034 #if defined(__NetBSD__) || defined(__OpenBSD__) 1035 if (sc->sc_powerhook != NULL) 1036 powerhook_disestablish(sc->sc_powerhook); 1037 if (sc->sc_shutdownhook != NULL) 1038 shutdownhook_disestablish(sc->sc_shutdownhook); 1039 #endif 1040 1041 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1042 1043 usb_freemem(&sc->sc_dmatag, &sc->sc_fldma); 1044 /* XXX free other data structures XXX */ 1045 1046 while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 1047 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1048 usb_clean_buffer_dma(&sc->sc_dmatag, &EXFER(xfer)->dmabuf); 1049 free(xfer, M_USB); 1050 } 1051 ehci_free_desc_chunks(sc, &sc->sc_sqh_chunks); 1052 ehci_free_desc_chunks(sc, &sc->sc_sqtd_chunks); 1053 usb_dma_tag_finish(&sc->sc_dmatag); 1054 1055 return (rv); 1056 } 1057 1058 Static void 1059 ehci_free_desc_chunks(ehci_softc_t *sc, struct ehci_mdescs *c) 1060 { 1061 struct ehci_mem_desc *em; 1062 1063 while ((em = SIMPLEQ_FIRST(c)) != NULL) { 1064 SIMPLEQ_REMOVE_HEAD(c, em_next); 1065 usb_freemem(&sc->sc_dmatag, &em->em_dma); 1066 } 1067 } 1068 1069 #if defined(__NetBSD__) || defined(__OpenBSD__) 1070 int 1071 ehci_activate(device_t self, enum devact act) 1072 { 1073 struct ehci_softc *sc = (struct ehci_softc *)self; 1074 int rv = 0; 1075 1076 switch (act) { 1077 case DVACT_ACTIVATE: 1078 return (EOPNOTSUPP); 1079 1080 case DVACT_DEACTIVATE: 1081 if (sc->sc_child != NULL) 1082 rv = config_deactivate(sc->sc_child); 1083 sc->sc_dying = 1; 1084 break; 1085 } 1086 return (rv); 1087 } 1088 #endif 1089 1090 /* 1091 * Handle suspend/resume. 1092 * 1093 * We need to switch to polling mode here, because this routine is 1094 * called from an interrupt context. This is all right since we 1095 * are almost suspended anyway. 1096 */ 1097 void 1098 ehci_power(int why, void *v) 1099 { 1100 ehci_softc_t *sc = v; 1101 u_int32_t cmd, hcr; 1102 int s, i; 1103 1104 #ifdef EHCI_DEBUG 1105 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why)); 1106 if (ehcidebug > 0) 1107 ehci_dump_regs(sc); 1108 #endif 1109 1110 s = splhardusb(); 1111 switch (why) { 1112 USB_PWR_CASE_SUSPEND: 1113 sc->sc_bus.use_polling++; 1114 1115 for (i = 1; i <= sc->sc_noport; i++) { 1116 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1117 if ((cmd & EHCI_PS_PO) == 0 && 1118 (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1119 EOWRITE4(sc, EHCI_PORTSC(i), 1120 cmd | EHCI_PS_SUSP); 1121 } 1122 1123 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1124 1125 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1126 EOWRITE4(sc, EHCI_USBCMD, cmd); 1127 1128 for (i = 0; i < 100; i++) { 1129 hcr = EOREAD4(sc, EHCI_USBSTS) & 1130 (EHCI_STS_ASS | EHCI_STS_PSS); 1131 if (hcr == 0) 1132 break; 1133 1134 usb_delay_ms(&sc->sc_bus, 1); 1135 } 1136 if (hcr != 0) { 1137 printf("%s: reset timeout\n", 1138 USBDEVNAME(sc->sc_bus.bdev)); 1139 } 1140 1141 cmd &= ~EHCI_CMD_RS; 1142 EOWRITE4(sc, EHCI_USBCMD, cmd); 1143 1144 for (i = 0; i < 100; i++) { 1145 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1146 if (hcr == EHCI_STS_HCH) 1147 break; 1148 1149 usb_delay_ms(&sc->sc_bus, 1); 1150 } 1151 if (hcr != EHCI_STS_HCH) { 1152 printf("%s: config timeout\n", 1153 USBDEVNAME(sc->sc_bus.bdev)); 1154 } 1155 1156 sc->sc_bus.use_polling--; 1157 break; 1158 1159 USB_PWR_CASE_RESUME: 1160 sc->sc_bus.use_polling++; 1161 1162 /* restore things in case the bios sucks */ 1163 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1164 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1165 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1166 EHCI_SQH_DMAADDR(sc->sc_async_head) | EHCI_LINK_QH); 1167 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1168 1169 hcr = 0; 1170 for (i = 1; i <= sc->sc_noport; i++) { 1171 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1172 if ((cmd & EHCI_PS_PO) == 0 && 1173 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1174 EOWRITE4(sc, EHCI_PORTSC(i), 1175 cmd | EHCI_PS_FPR); 1176 hcr = 1; 1177 } 1178 } 1179 1180 if (hcr) { 1181 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1182 1183 for (i = 1; i <= sc->sc_noport; i++) { 1184 cmd = EOREAD4(sc, EHCI_PORTSC(i)); 1185 if ((cmd & EHCI_PS_PO) == 0 && 1186 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1187 EOWRITE4(sc, EHCI_PORTSC(i), 1188 cmd & ~EHCI_PS_FPR); 1189 } 1190 } 1191 1192 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1193 1194 for (i = 0; i < 100; i++) { 1195 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1196 if (hcr != EHCI_STS_HCH) 1197 break; 1198 1199 usb_delay_ms(&sc->sc_bus, 1); 1200 } 1201 if (hcr == EHCI_STS_HCH) { 1202 printf("%s: config timeout\n", 1203 USBDEVNAME(sc->sc_bus.bdev)); 1204 } 1205 1206 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1207 1208 sc->sc_bus.use_polling--; 1209 break; 1210 1211 default: 1212 break; 1213 } 1214 splx(s); 1215 1216 #ifdef EHCI_DEBUG 1217 DPRINTF(("ehci_power: sc=%p\n", sc)); 1218 if (ehcidebug > 0) 1219 ehci_dump_regs(sc); 1220 #endif 1221 } 1222 1223 /* 1224 * Shut down the controller when the system is going down. 1225 */ 1226 void 1227 ehci_shutdown(void *v) 1228 { 1229 ehci_softc_t *sc = v; 1230 1231 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1232 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1233 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1234 } 1235 1236 /* 1237 * Allocate a physically contiguous buffer to handle cases where EHCI 1238 * cannot handle a packet because it is not physically contiguous. 1239 */ 1240 Static void 1241 ehci_aux_mem_init(struct ehci_aux_mem *aux) 1242 { 1243 1244 aux->aux_curchunk = aux->aux_chunkoff = aux->aux_naux = 0; 1245 } 1246 1247 Static usbd_status 1248 ehci_aux_mem_alloc(ehci_softc_t *sc, struct ehci_aux_mem *aux, 1249 int naux, int maxp) 1250 { 1251 int nchunk, i, j; 1252 usbd_status err; 1253 1254 USB_KASSERT(aux->aux_nchunk == 0); 1255 1256 nchunk = EHCI_NCHUNK(naux, maxp); 1257 for (i = 0; i < nchunk; i++) { 1258 err = usb_allocmem(&sc->sc_dmatag, EHCI_AUX_CHUNK_SIZE, 1259 EHCI_AUX_CHUNK_SIZE, &aux->aux_chunk_dma[i]); 1260 if (err) { 1261 for (j = 0; j < i; j++) 1262 usb_freemem(&sc->sc_dmatag, 1263 &aux->aux_chunk_dma[j]); 1264 return (err); 1265 } 1266 } 1267 1268 aux->aux_nchunk = nchunk; 1269 ehci_aux_mem_init(aux); 1270 1271 return (USBD_NORMAL_COMPLETION); 1272 } 1273 1274 Static void 1275 ehci_aux_mem_free(ehci_softc_t *sc, struct ehci_aux_mem *aux) 1276 { 1277 int i; 1278 1279 /* sync last aux (just in case, probably a no-op) */ 1280 if (aux->aux_naux) 1281 ehci_aux_dma_sync(sc, aux, BUS_DMASYNC_POSTWRITE); 1282 1283 for (i = 0; i < aux->aux_nchunk; i++) 1284 usb_freemem(&sc->sc_dmatag, &aux->aux_chunk_dma[i]); 1285 1286 aux->aux_nchunk = 0; 1287 } 1288 1289 Static bus_addr_t 1290 ehci_aux_dma_alloc(struct ehci_aux_mem *aux, int len, struct aux_desc *ad) 1291 { 1292 bus_addr_t auxdma; 1293 1294 if (aux->aux_chunkoff + len > EHCI_AUX_CHUNK_SIZE) { 1295 aux->aux_curchunk++; 1296 aux->aux_chunkoff = 0; 1297 } 1298 USB_KASSERT(aux->aux_curchunk < aux->aux_nchunk); 1299 1300 auxdma = 1301 DMAADDR(&aux->aux_chunk_dma[aux->aux_curchunk], aux->aux_chunkoff); 1302 ad->aux_kern = 1303 KERNADDR(&aux->aux_chunk_dma[aux->aux_curchunk], aux->aux_chunkoff); 1304 1305 aux->aux_chunkoff += len; 1306 aux->aux_naux++; 1307 1308 return auxdma; 1309 } 1310 1311 Static void 1312 ehci_aux_dma_sync(ehci_softc_t *sc, struct ehci_aux_mem *aux, int op) 1313 { 1314 int i; 1315 1316 for (i = 0; i < aux->aux_curchunk; i++) 1317 USB_MEM_SYNC(&sc->sc_dmatag, &aux->aux_chunk_dma[i], op); 1318 if (aux->aux_chunkoff) 1319 USB_MEM_SYNC2(&sc->sc_dmatag, &aux->aux_chunk_dma[i], 1320 0, aux->aux_chunkoff, op); 1321 } 1322 1323 Static usbd_status 1324 ehci_prealloc(struct ehci_softc *sc, struct ehci_xfer *exfer, 1325 size_t bufsize, int nseg) 1326 { 1327 usb_endpoint_descriptor_t *endpt; 1328 int maxseg, mps, naux; 1329 int seglen, ntd; 1330 int s; 1331 int err; 1332 1333 endpt = exfer->xfer.pipe->endpoint->edesc; 1334 mps = UE_MAXPKTSZ(endpt); 1335 1336 if (mps == 0) 1337 return (USBD_INVAL); 1338 1339 /* (over) estimate needed number of TDs */ 1340 maxseg = EHCI_PAGE_SIZE * EHCI_QTD_NBUFFERS; 1341 seglen = maxseg - (maxseg % mps); 1342 ntd = bufsize / seglen + nseg; 1343 1344 /* allocate aux buffer for non-isoc OUT transfer */ 1345 naux = 0; 1346 if (nseg > 1 && 1347 (endpt->bmAttributes & UE_XFERTYPE) != UE_ISOCHRONOUS && 1348 UE_GET_DIR(endpt->bEndpointAddress) == UE_DIR_OUT) { 1349 /* estimate needed aux segments */ 1350 naux = nseg - 1; 1351 1352 /* pre-allocate aux memory */ 1353 err = ehci_aux_mem_alloc(sc, &exfer->aux, naux, mps); 1354 if (err) 1355 return err; 1356 1357 /* an aux segment will consume a TD */ 1358 ntd += naux; 1359 } 1360 1361 s = splusb(); 1362 /* pre-allocate QDs */ 1363 /* XXX ITDs */ 1364 while (sc->sc_nfreeqtds < ntd) { 1365 DPRINTF(("%s: qhci_prealloc: need %d QTD (%d cur)\n", 1366 USBDEVNAME(sc->sc_bus.bdev), ntd, sc->sc_nfreeqtds)); 1367 if ((err = ehci_grow_sqtd(sc)) != USBD_NORMAL_COMPLETION) { 1368 splx(s); 1369 ehci_aux_mem_free(sc, &exfer->aux); 1370 return err; 1371 } 1372 } 1373 sc->sc_nfreeqtds -= ntd; 1374 splx(s); 1375 1376 exfer->rsvd_tds = ntd; 1377 1378 return USBD_NORMAL_COMPLETION; 1379 } 1380 1381 usbd_status 1382 ehci_allocm(struct usbd_bus *bus, usbd_xfer_handle xfer, void *buf, size_t size) 1383 { 1384 struct ehci_softc *sc = (struct ehci_softc *)bus; 1385 struct ehci_xfer *exfer = EXFER(xfer); 1386 usbd_status err; 1387 1388 if ((err = usb_alloc_buffer_dma(&sc->sc_dmatag, &exfer->dmabuf, 1389 buf, size, &xfer->hcbuffer)) == USBD_NORMAL_COMPLETION) { 1390 if ((xfer->rqflags & URQ_DEV_MAP_PREPARED) == 0 && 1391 (err = ehci_prealloc(sc, exfer, size, 1392 USB_BUFFER_NSEGS(&exfer->dmabuf))) 1393 != USBD_NORMAL_COMPLETION) { 1394 usb_free_buffer_dma(&sc->sc_dmatag, &exfer->dmabuf, 1395 U_WAITOK); 1396 } 1397 } 1398 #ifdef EHCI_DEBUG 1399 if (err) 1400 printf("ehci_allocm: usb_alloc_buffer_dma()=%d\n", err); 1401 #endif 1402 return (err); 1403 } 1404 1405 void 1406 ehci_freem(struct usbd_bus *bus, usbd_xfer_handle xfer, 1407 enum usbd_waitflg waitflg) 1408 { 1409 struct ehci_softc *sc = (struct ehci_softc *)bus; 1410 struct ehci_xfer *exfer = EXFER(xfer); 1411 int s; 1412 1413 usb_free_buffer_dma(&sc->sc_dmatag, &exfer->dmabuf, waitflg); 1414 1415 if ((xfer->rqflags & URQ_DEV_MAP_PREPARED) == 0) { 1416 /* XXX ITDs */ 1417 1418 s = splusb(); 1419 sc->sc_nfreeqtds += exfer->rsvd_tds; 1420 splx(s); 1421 exfer->rsvd_tds = 0; 1422 ehci_aux_mem_free(sc, &exfer->aux); 1423 } 1424 } 1425 1426 Static usbd_status 1427 ehci_map_alloc(usbd_xfer_handle xfer) 1428 { 1429 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1430 struct ehci_xfer *exfer = EXFER(xfer); 1431 usbd_status st; 1432 1433 st = usb_alloc_dma_resources(&sc->sc_dmatag, &exfer->dmabuf); 1434 if (st) 1435 return st; 1436 1437 if ((st = ehci_prealloc(sc, exfer, MAXPHYS, USB_DMA_NSEG))) { 1438 usb_free_dma_resources(&sc->sc_dmatag, &exfer->dmabuf); 1439 } 1440 1441 return st; 1442 } 1443 1444 Static void 1445 ehci_map_free(usbd_xfer_handle xfer) 1446 { 1447 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1448 struct ehci_xfer *exfer = EXFER(xfer); 1449 int s; 1450 1451 USB_KASSERT(xfer->rqflags & URQ_DEV_MAP_PREPARED); 1452 1453 usb_free_dma_resources(&sc->sc_dmatag, &exfer->dmabuf); 1454 1455 /* XXX ITDs */ 1456 1457 s = splusb(); 1458 sc->sc_nfreeqtds += exfer->rsvd_tds; 1459 splx(s); 1460 exfer->rsvd_tds = 0; 1461 ehci_aux_mem_free(sc, &exfer->aux); 1462 } 1463 1464 Static void 1465 ehci_mapm(usbd_xfer_handle xfer, void *buf, size_t size) 1466 { 1467 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1468 struct ehci_xfer *exfer = EXFER(xfer); 1469 1470 usb_map_dma(&sc->sc_dmatag, &exfer->dmabuf, buf, size); 1471 } 1472 1473 Static usbd_status 1474 ehci_mapm_mbuf(usbd_xfer_handle xfer, struct mbuf *chain) 1475 { 1476 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1477 struct ehci_xfer *exfer = EXFER(xfer); 1478 1479 return (usb_map_mbuf_dma(&sc->sc_dmatag, &exfer->dmabuf, chain)); 1480 } 1481 1482 Static void 1483 ehci_unmapm(usbd_xfer_handle xfer) 1484 { 1485 struct ehci_softc *sc = (struct ehci_softc *)xfer->device->bus; 1486 struct ehci_xfer *exfer = EXFER(xfer); 1487 1488 usb_unmap_dma(&sc->sc_dmatag, &exfer->dmabuf); 1489 } 1490 1491 usbd_xfer_handle 1492 ehci_allocx(struct usbd_bus *bus, usbd_pipe_handle pipe, 1493 enum usbd_waitflg waitflg) 1494 { 1495 struct ehci_softc *sc = (struct ehci_softc *)bus; 1496 usbd_xfer_handle xfer; 1497 1498 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1499 if (xfer != NULL) { 1500 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1501 #ifdef DIAGNOSTIC 1502 if (xfer->busy_free != XFER_FREE) { 1503 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1504 xfer->busy_free); 1505 } 1506 #endif 1507 } else { 1508 xfer = malloc(sizeof(struct ehci_xfer), M_USB, 1509 waitflg == U_WAITOK ? M_WAITOK : M_NOWAIT); 1510 } 1511 if (xfer != NULL) { 1512 memset(xfer, 0, sizeof(struct ehci_xfer)); 1513 usb_init_task(&EXFER(xfer)->abort_task, ehci_timeout_task, 1514 xfer); 1515 EXFER(xfer)->ehci_xfer_flags = 0; 1516 EXFER(xfer)->rsvd_tds = 0; 1517 #ifdef DIAGNOSTIC 1518 EXFER(xfer)->isdone = 1; 1519 xfer->busy_free = XFER_BUSY; 1520 #endif 1521 } 1522 return (xfer); 1523 } 1524 1525 void 1526 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1527 { 1528 struct ehci_softc *sc = (struct ehci_softc *)bus; 1529 1530 #ifdef DIAGNOSTIC 1531 if (xfer->busy_free != XFER_BUSY) { 1532 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1533 xfer->busy_free); 1534 } 1535 xfer->busy_free = XFER_FREE; 1536 if (!EXFER(xfer)->isdone) { 1537 printf("ehci_freex: !isdone\n"); 1538 } 1539 #endif 1540 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1541 } 1542 1543 Static void 1544 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1545 { 1546 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1547 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 1548 1549 EHCI_SQH_SYNC(sc, epipe->sqh, 1550 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1551 1552 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1553 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1554 #ifdef USB_DEBUG 1555 if (ehcidebug) 1556 usbd_dump_pipe(pipe); 1557 #endif 1558 USB_KASSERT2((epipe->sqh->qh.qh_qtd.qtd_status & 1559 htole32(EHCI_QTD_ACTIVE)) == 0, 1560 ("ehci_device_clear_toggle: queue active")); 1561 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE_MASK); 1562 EHCI_SQH_SYNC(sc, epipe->sqh, 1563 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1564 } 1565 1566 Static void 1567 ehci_noop(usbd_pipe_handle pipe) 1568 { 1569 } 1570 1571 #ifdef EHCI_DEBUG 1572 void 1573 ehci_dump_regs(ehci_softc_t *sc) 1574 { 1575 int i; 1576 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1577 EOREAD4(sc, EHCI_USBCMD), 1578 EOREAD4(sc, EHCI_USBSTS), 1579 EOREAD4(sc, EHCI_USBINTR)); 1580 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1581 EOREAD4(sc, EHCI_FRINDEX), 1582 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1583 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1584 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1585 for (i = 1; i <= sc->sc_noport; i++) 1586 printf("port %d status=0x%08x\n", i, 1587 EOREAD4(sc, EHCI_PORTSC(i))); 1588 } 1589 1590 /* 1591 * Unused function - this is meant to be called from a kernel 1592 * debugger. 1593 */ 1594 void 1595 ehci_dump() 1596 { 1597 ehci_dump_regs(theehci); 1598 } 1599 1600 void 1601 ehci_dump_link(ehci_link_t link, int type) 1602 { 1603 link = le32toh(link); 1604 printf("0x%08x", link); 1605 if (link & EHCI_LINK_TERMINATE) 1606 printf("<T>"); 1607 else { 1608 printf("<"); 1609 if (type) { 1610 switch (EHCI_LINK_TYPE(link)) { 1611 case EHCI_LINK_ITD: printf("ITD"); break; 1612 case EHCI_LINK_QH: printf("QH"); break; 1613 case EHCI_LINK_SITD: printf("SITD"); break; 1614 case EHCI_LINK_FSTN: printf("FSTN"); break; 1615 } 1616 } 1617 printf(">"); 1618 } 1619 } 1620 1621 void 1622 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1623 { 1624 int i; 1625 u_int32_t stop; 1626 1627 stop = 0; 1628 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1629 ehci_dump_sqtd(sqtd); 1630 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1631 } 1632 if (sqtd) 1633 printf("dump aborted, too many TDs\n"); 1634 } 1635 1636 void 1637 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1638 { 1639 printf("QTD(%p) at 0x%08x:\n", sqtd, EHCI_SQTD_DMAADDR(sqtd)); 1640 ehci_dump_qtd(&sqtd->qtd); 1641 } 1642 1643 void 1644 ehci_dump_qtd(ehci_qtd_t *qtd) 1645 { 1646 u_int32_t s; 1647 char sbuf[128]; 1648 1649 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1650 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1651 printf("\n"); 1652 s = le32toh(qtd->qtd_status); 1653 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1654 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1655 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1656 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1657 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1658 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1659 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1660 EHCI_QTD_GET_PID(s), sbuf); 1661 for (s = 0; s < 5; s++) 1662 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1663 } 1664 1665 void 1666 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1667 { 1668 ehci_qh_t *qh = &sqh->qh; 1669 u_int32_t endp, endphub; 1670 1671 printf("QH(%p) at 0x%08x:\n", sqh, EHCI_SQH_DMAADDR(sqh)); 1672 printf(" sqtd=%p inactivesqtd=%p\n", sqh->sqtd, sqh->inactivesqtd); 1673 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1674 endp = le32toh(qh->qh_endp); 1675 printf(" endp=0x%08x\n", endp); 1676 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1677 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1678 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1679 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1680 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1681 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1682 EHCI_QH_GET_NRL(endp)); 1683 endphub = le32toh(qh->qh_endphub); 1684 printf(" endphub=0x%08x\n", endphub); 1685 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1686 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1687 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1688 EHCI_QH_GET_MULT(endphub)); 1689 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1690 printf("Overlay qTD:\n"); 1691 ehci_dump_qtd(&qh->qh_qtd); 1692 } 1693 1694 #ifdef DIAGNOSTIC 1695 Static void 1696 ehci_dump_exfer(struct ehci_xfer *ex) 1697 { 1698 printf("ehci_dump_exfer: ex=%p\n", ex); 1699 } 1700 #endif 1701 #endif 1702 1703 usbd_status 1704 ehci_open(usbd_pipe_handle pipe) 1705 { 1706 usbd_device_handle dev = pipe->device; 1707 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 1708 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1709 u_int8_t addr = dev->address; 1710 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1711 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1712 ehci_soft_qh_t *sqh; 1713 usbd_status err; 1714 int s; 1715 int ival, speed, naks; 1716 int hshubaddr, hshubport; 1717 1718 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1719 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1720 1721 if (dev->myhsport) { 1722 hshubaddr = dev->myhsport->parent->address; 1723 hshubport = dev->myhsport->portno; 1724 } else { 1725 hshubaddr = 0; 1726 hshubport = 0; 1727 } 1728 1729 if (sc->sc_dying) 1730 return (USBD_IOERROR); 1731 1732 if (addr == sc->sc_addr) { 1733 switch (ed->bEndpointAddress) { 1734 case USB_CONTROL_ENDPOINT: 1735 pipe->methods = &ehci_root_ctrl_methods; 1736 break; 1737 case UE_DIR_IN | EHCI_INTR_ENDPT: 1738 pipe->methods = &ehci_root_intr_methods; 1739 break; 1740 default: 1741 return (USBD_INVAL); 1742 } 1743 return (USBD_NORMAL_COMPLETION); 1744 } 1745 1746 /* XXX All this stuff is only valid for async. */ 1747 switch (dev->speed) { 1748 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1749 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1750 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1751 default: panic("ehci_open: bad device speed %d", dev->speed); 1752 } 1753 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1754 printf("%s: *** WARNING: opening low/full speed isoc device, " 1755 "this does not work yet.\n", 1756 USBDEVNAME(sc->sc_bus.bdev)); 1757 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1758 hshubaddr, hshubport)); 1759 return USBD_INVAL; 1760 } 1761 1762 naks = 8; /* XXX */ 1763 sqh = ehci_alloc_sqh(sc); 1764 if (sqh == NULL) 1765 return (USBD_NOMEM); 1766 /* qh_link filled when the QH is added */ 1767 sqh->qh.qh_endp = htole32( 1768 EHCI_QH_SET_ADDR(addr) | 1769 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1770 EHCI_QH_SET_EPS(speed) | 1771 (xfertype == UE_CONTROL ? EHCI_QH_DTC : 0) | 1772 EHCI_QH_SET_MPL(UE_MAXPKTSZ(ed)) | 1773 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1774 EHCI_QH_CTL : 0) | 1775 EHCI_QH_SET_NRL(naks) 1776 ); 1777 sqh->qh.qh_endphub = htole32( 1778 EHCI_QH_SET_MULT(1) | 1779 EHCI_QH_SET_HUBA(hshubaddr) | 1780 EHCI_QH_SET_PORT(hshubport) | 1781 EHCI_QH_SET_CMASK(0x1c) | 1782 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0) 1783 ); 1784 sqh->qh.qh_curqtd = EHCI_NULL; 1785 /* The overlay qTD was already set up by ehci_alloc_sqh(). */ 1786 sqh->qh.qh_qtd.qtd_status = 1787 htole32(EHCI_QTD_SET_TOGGLE(pipe->endpoint->savedtoggle)); 1788 1789 epipe->sqh = sqh; 1790 1791 switch (xfertype) { 1792 case UE_CONTROL: 1793 err = usb_allocmem(&sc->sc_dmatag, sizeof(usb_device_request_t), 1794 0, &epipe->u.ctl.reqdma); 1795 #ifdef EHCI_DEBUG 1796 if (err) 1797 printf("ehci_open: usb_allocmem()=%d\n", err); 1798 #endif 1799 if (err) 1800 goto bad; 1801 pipe->methods = &ehci_device_ctrl_methods; 1802 s = splusb(); 1803 ehci_add_qh(sc, sqh, sc->sc_async_head); 1804 splx(s); 1805 break; 1806 case UE_BULK: 1807 pipe->methods = &ehci_device_bulk_methods; 1808 s = splusb(); 1809 ehci_add_qh(sc, sqh, sc->sc_async_head); 1810 splx(s); 1811 break; 1812 case UE_INTERRUPT: 1813 pipe->methods = &ehci_device_intr_methods; 1814 ival = pipe->interval; 1815 if (ival == USBD_DEFAULT_INTERVAL) { 1816 if (speed == EHCI_QH_SPEED_HIGH) { 1817 if (ed->bInterval > 16) { 1818 /* 1819 * illegal with high-speed, but there 1820 * were documentation bugs in the spec, 1821 * so be generous 1822 */ 1823 ival = 256; 1824 } else 1825 ival = (1 << (ed->bInterval - 1)) / 8; 1826 } else 1827 ival = ed->bInterval; 1828 } 1829 err = ehci_device_setintr(sc, sqh, ival); 1830 if (err) 1831 goto bad; 1832 break; 1833 case UE_ISOCHRONOUS: 1834 pipe->methods = &ehci_device_isoc_methods; 1835 /* FALLTHROUGH */ 1836 default: 1837 err = USBD_INVAL; 1838 goto bad; 1839 } 1840 return (USBD_NORMAL_COMPLETION); 1841 1842 bad: 1843 ehci_free_sqh(sc, sqh); 1844 return (err); 1845 } 1846 1847 /* 1848 * Add an ED to the schedule. Called at splusb(). 1849 * If in the async schedule, it will always have a next. 1850 * If in the intr schedule it may not. 1851 */ 1852 void 1853 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1854 { 1855 SPLUSBCHECK; 1856 1857 sqh->next = head->next; 1858 sqh->prev = head; 1859 sqh->qh.qh_link = head->qh.qh_link; 1860 EHCI_SQH_SYNC(sc, sqh, 1861 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1862 head->next = sqh; 1863 if (sqh->next) 1864 sqh->next->prev = sqh; 1865 head->qh.qh_link = htole32(EHCI_SQH_DMAADDR(sqh) | EHCI_LINK_QH); 1866 EHCI_SQH_SYNC(sc, head, 1867 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1868 1869 #ifdef EHCI_DEBUG 1870 if (ehcidebug > 5) { 1871 printf("ehci_add_qh:\n"); 1872 ehci_dump_sqh(sqh); 1873 } 1874 #endif 1875 } 1876 1877 /* 1878 * Remove an ED from the schedule. Called at splusb(). 1879 * Will always have a 'next' if it's in the async list as it's circular. 1880 */ 1881 void 1882 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1883 { 1884 SPLUSBCHECK; 1885 /* XXX */ 1886 sqh->prev->qh.qh_link = sqh->qh.qh_link; 1887 EHCI_SQH_SYNC(sc, sqh->prev, 1888 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1889 sqh->prev->next = sqh->next; 1890 if (sqh->next) 1891 sqh->next->prev = sqh->prev; 1892 ehci_sync_hc(sc); 1893 } 1894 1895 /* Restart a QH following the addition of a qTD. */ 1896 void 1897 ehci_activate_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1898 { 1899 ehci_physaddr_t qtddma; 1900 1901 EHCI_SQTD_SYNC(sc, sqtd, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1902 1903 USB_KASSERT2((sqtd->qtd.qtd_status & htole32(EHCI_QTD_ACTIVE)) == 0, 1904 ("ehci_activate_qh: already active")); 1905 1906 /* 1907 * When a QH is idle, the overlay qTD should be marked as not 1908 * halted and not active. This causes the host controller to 1909 * retrieve the real qTD on each pass (rather than just examinig 1910 * the overlay), so it will notice when we activate the qTD. 1911 */ 1912 if (sqtd == sqh->sqtd) { 1913 /* Check that the hardware is in the state we expect. */ 1914 qtddma = EHCI_SQTD_DMAADDR(sqtd); 1915 if (EHCI_LINK_ADDR(le32toh(sqh->qh.qh_qtd.qtd_next)) != 1916 qtddma) { 1917 #ifdef EHCI_DEBUG 1918 printf("ehci_activate_qh: unexpected next ptr\n"); 1919 ehci_dump_sqh(sqh); 1920 ehci_dump_sqtds(sqh->sqtd); 1921 #endif 1922 sqh->qh.qh_qtd.qtd_next = htole32(qtddma); 1923 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1924 } 1925 /* Ensure the flags are correct. */ 1926 sqh->qh.qh_qtd.qtd_status &= htole32(EHCI_QTD_PINGSTATE | 1927 EHCI_QTD_TOGGLE_MASK); 1928 EHCI_SQH_SYNC(sc, sqh, 1929 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1930 } 1931 1932 /* Now activate the qTD. */ 1933 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_ACTIVE); 1934 EHCI_SQTD_SYNC(sc, sqtd, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1935 } 1936 1937 /* 1938 * Ensure that the HC has released all references to the QH. We do this 1939 * by asking for a Async Advance Doorbell interrupt and then we wait for 1940 * the interrupt. 1941 * To make this easier we first obtain exclusive use of the doorbell. 1942 */ 1943 void 1944 ehci_sync_hc(ehci_softc_t *sc) 1945 { 1946 int s, error; 1947 1948 if (sc->sc_dying) { 1949 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1950 return; 1951 } 1952 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1953 /* get doorbell */ 1954 usb_lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE, NULL); 1955 s = splhardusb(); 1956 /* ask for doorbell */ 1957 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1958 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1959 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1960 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1961 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1962 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1963 splx(s); 1964 /* release doorbell */ 1965 usb_lockmgr(&sc->sc_doorbell_lock, LK_RELEASE, NULL); 1966 #ifdef DIAGNOSTIC 1967 if (error) 1968 printf("ehci_sync_hc: tsleep() = %d\n", error); 1969 #endif 1970 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1971 } 1972 1973 /***********/ 1974 1975 /* 1976 * Data structures and routines to emulate the root hub. 1977 */ 1978 Static usb_device_descriptor_t ehci_devd = { 1979 USB_DEVICE_DESCRIPTOR_SIZE, 1980 UDESC_DEVICE, /* type */ 1981 {0x00, 0x02}, /* USB version */ 1982 UDCLASS_HUB, /* class */ 1983 UDSUBCLASS_HUB, /* subclass */ 1984 UDPROTO_HSHUBSTT, /* protocol */ 1985 64, /* max packet */ 1986 {0},{0},{0x00,0x01}, /* device id */ 1987 1,2,0, /* string indicies */ 1988 1 /* # of configurations */ 1989 }; 1990 1991 Static const usb_device_qualifier_t ehci_odevd = { 1992 USB_DEVICE_DESCRIPTOR_SIZE, 1993 UDESC_DEVICE_QUALIFIER, /* type */ 1994 {0x00, 0x02}, /* USB version */ 1995 UDCLASS_HUB, /* class */ 1996 UDSUBCLASS_HUB, /* subclass */ 1997 UDPROTO_FSHUB, /* protocol */ 1998 64, /* max packet */ 1999 1, /* # of configurations */ 2000 0 2001 }; 2002 2003 Static const usb_config_descriptor_t ehci_confd = { 2004 USB_CONFIG_DESCRIPTOR_SIZE, 2005 UDESC_CONFIG, 2006 {USB_CONFIG_DESCRIPTOR_SIZE + 2007 USB_INTERFACE_DESCRIPTOR_SIZE + 2008 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2009 1, 2010 1, 2011 0, 2012 UC_ATTR_MBO | UC_SELF_POWERED, 2013 0 /* max power */ 2014 }; 2015 2016 Static const usb_interface_descriptor_t ehci_ifcd = { 2017 USB_INTERFACE_DESCRIPTOR_SIZE, 2018 UDESC_INTERFACE, 2019 0, 2020 0, 2021 1, 2022 UICLASS_HUB, 2023 UISUBCLASS_HUB, 2024 UIPROTO_HSHUBSTT, 2025 0 2026 }; 2027 2028 Static const usb_endpoint_descriptor_t ehci_endpd = { 2029 USB_ENDPOINT_DESCRIPTOR_SIZE, 2030 UDESC_ENDPOINT, 2031 UE_DIR_IN | EHCI_INTR_ENDPT, 2032 UE_INTERRUPT, 2033 {8, 0}, /* max packet */ 2034 12 2035 }; 2036 2037 Static const usb_hub_descriptor_t ehci_hubd = { 2038 USB_HUB_DESCRIPTOR_SIZE, 2039 UDESC_HUB, 2040 0, 2041 {0,0}, 2042 0, 2043 0, 2044 {""}, 2045 {""}, 2046 }; 2047 2048 Static int 2049 ehci_str(usb_string_descriptor_t *p, int l, const char *s) 2050 { 2051 int i; 2052 2053 if (l == 0) 2054 return (0); 2055 p->bLength = 2 * strlen(s) + 2; 2056 if (l == 1) 2057 return (1); 2058 p->bDescriptorType = UDESC_STRING; 2059 l -= 2; 2060 for (i = 0; s[i] && l > 1; i++, l -= 2) 2061 USETW2(p->bString[i], 0, s[i]); 2062 return (2*i+2); 2063 } 2064 2065 /* 2066 * Simulate a hardware hub by handling all the necessary requests. 2067 */ 2068 Static usbd_status 2069 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2070 { 2071 usbd_status err; 2072 2073 /* Insert last in queue. */ 2074 err = usb_insert_transfer(xfer); 2075 if (err) 2076 return (err); 2077 2078 /* Pipe isn't running, start first */ 2079 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2080 } 2081 2082 Static usbd_status 2083 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2084 { 2085 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2086 usb_device_request_t *req; 2087 void *buf = NULL; 2088 int port, i; 2089 int s, len, value, index, l, totlen = 0; 2090 usb_port_status_t ps; 2091 usb_hub_descriptor_t hubd; 2092 usbd_status err; 2093 u_int32_t v; 2094 2095 if (sc->sc_dying) 2096 return (USBD_IOERROR); 2097 2098 #ifdef DIAGNOSTIC 2099 if (!(xfer->rqflags & URQ_REQUEST)) 2100 /* XXX panic */ 2101 return (USBD_INVAL); 2102 #endif 2103 req = &xfer->request; 2104 2105 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2106 req->bmRequestType, req->bRequest)); 2107 2108 len = UGETW(req->wLength); 2109 value = UGETW(req->wValue); 2110 index = UGETW(req->wIndex); 2111 2112 if (len != 0) { 2113 /* mbuf transfer is not supported */ 2114 if (xfer->rqflags & URQ_DEV_MAP_MBUF) 2115 return (USBD_INVAL); 2116 buf = xfer->hcbuffer; 2117 } 2118 2119 #define C(x,y) ((x) | ((y) << 8)) 2120 switch(C(req->bRequest, req->bmRequestType)) { 2121 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2122 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2123 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2124 /* 2125 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2126 * for the integrated root hub. 2127 */ 2128 break; 2129 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2130 if (len > 0) { 2131 *(u_int8_t *)buf = sc->sc_conf; 2132 totlen = 1; 2133 } 2134 break; 2135 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2136 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2137 if (len == 0) 2138 break; 2139 switch(value >> 8) { 2140 case UDESC_DEVICE: 2141 if ((value & 0xff) != 0) { 2142 err = USBD_IOERROR; 2143 goto ret; 2144 } 2145 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2146 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2147 memcpy(buf, &ehci_devd, l); 2148 break; 2149 /* 2150 * We can't really operate at another speed, but the spec says 2151 * we need this descriptor. 2152 */ 2153 case UDESC_DEVICE_QUALIFIER: 2154 if ((value & 0xff) != 0) { 2155 err = USBD_IOERROR; 2156 goto ret; 2157 } 2158 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2159 memcpy(buf, &ehci_odevd, l); 2160 break; 2161 /* 2162 * We can't really operate at another speed, but the spec says 2163 * we need this descriptor. 2164 */ 2165 case UDESC_OTHER_SPEED_CONFIGURATION: 2166 case UDESC_CONFIG: 2167 if ((value & 0xff) != 0) { 2168 err = USBD_IOERROR; 2169 goto ret; 2170 } 2171 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2172 memcpy(buf, &ehci_confd, l); 2173 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2174 value >> 8; 2175 buf = (char *)buf + l; 2176 len -= l; 2177 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2178 totlen += l; 2179 memcpy(buf, &ehci_ifcd, l); 2180 buf = (char *)buf + l; 2181 len -= l; 2182 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2183 totlen += l; 2184 memcpy(buf, &ehci_endpd, l); 2185 break; 2186 case UDESC_STRING: 2187 *(u_int8_t *)buf = 0; 2188 totlen = 1; 2189 switch (value & 0xff) { 2190 case 0: /* Language table */ 2191 if (len > 0) 2192 *(u_int8_t *)buf = 4; 2193 if (len >= 4) { 2194 USETW(((usb_string_descriptor_t *)buf)->bString[0], 0x0409); 2195 totlen = 4; 2196 } 2197 break; 2198 case 1: /* Vendor */ 2199 totlen = ehci_str(buf, len, sc->sc_vendor); 2200 break; 2201 case 2: /* Product */ 2202 totlen = ehci_str(buf, len, "EHCI root hub"); 2203 break; 2204 } 2205 break; 2206 default: 2207 err = USBD_IOERROR; 2208 goto ret; 2209 } 2210 break; 2211 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2212 if (len > 0) { 2213 *(u_int8_t *)buf = 0; 2214 totlen = 1; 2215 } 2216 break; 2217 case C(UR_GET_STATUS, UT_READ_DEVICE): 2218 if (len > 1) { 2219 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2220 totlen = 2; 2221 } 2222 break; 2223 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2224 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2225 if (len > 1) { 2226 USETW(((usb_status_t *)buf)->wStatus, 0); 2227 totlen = 2; 2228 } 2229 break; 2230 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2231 if (value >= USB_MAX_DEVICES) { 2232 err = USBD_IOERROR; 2233 goto ret; 2234 } 2235 sc->sc_addr = value; 2236 break; 2237 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2238 if (value != 0 && value != 1) { 2239 err = USBD_IOERROR; 2240 goto ret; 2241 } 2242 sc->sc_conf = value; 2243 break; 2244 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2245 break; 2246 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2247 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2248 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2249 err = USBD_IOERROR; 2250 goto ret; 2251 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2252 break; 2253 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2254 break; 2255 /* Hub requests */ 2256 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2257 break; 2258 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2259 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2260 "port=%d feature=%d\n", 2261 index, value)); 2262 if (index < 1 || index > sc->sc_noport) { 2263 err = USBD_IOERROR; 2264 goto ret; 2265 } 2266 port = EHCI_PORTSC(index); 2267 v = EOREAD4(sc, port); 2268 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2269 v &= ~EHCI_PS_CLEAR; 2270 switch(value) { 2271 case UHF_PORT_ENABLE: 2272 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2273 break; 2274 case UHF_PORT_SUSPEND: 2275 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 2276 break; 2277 case UHF_PORT_POWER: 2278 if (sc->sc_hasppc) 2279 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2280 break; 2281 case UHF_PORT_TEST: 2282 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2283 "%d\n", index)); 2284 break; 2285 case UHF_PORT_INDICATOR: 2286 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2287 "%d\n", index)); 2288 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2289 break; 2290 case UHF_C_PORT_CONNECTION: 2291 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2292 break; 2293 case UHF_C_PORT_ENABLE: 2294 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2295 break; 2296 case UHF_C_PORT_SUSPEND: 2297 /* how? */ 2298 break; 2299 case UHF_C_PORT_OVER_CURRENT: 2300 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2301 break; 2302 case UHF_C_PORT_RESET: 2303 sc->sc_isreset[index] = 0; 2304 break; 2305 default: 2306 err = USBD_IOERROR; 2307 goto ret; 2308 } 2309 #if 0 2310 switch(value) { 2311 case UHF_C_PORT_CONNECTION: 2312 case UHF_C_PORT_ENABLE: 2313 case UHF_C_PORT_SUSPEND: 2314 case UHF_C_PORT_OVER_CURRENT: 2315 case UHF_C_PORT_RESET: 2316 default: 2317 break; 2318 } 2319 #endif 2320 break; 2321 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2322 if (len == 0) 2323 break; 2324 if ((value & 0xff) != 0) { 2325 err = USBD_IOERROR; 2326 goto ret; 2327 } 2328 hubd = ehci_hubd; 2329 hubd.bNbrPorts = sc->sc_noport; 2330 v = EOREAD4(sc, EHCI_HCSPARAMS); 2331 USETW(hubd.wHubCharacteristics, 2332 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2333 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2334 ? UHD_PORT_IND : 0); 2335 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2336 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2337 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2338 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2339 l = min(len, hubd.bDescLength); 2340 totlen = l; 2341 memcpy(buf, &hubd, l); 2342 break; 2343 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2344 if (len != 4) { 2345 err = USBD_IOERROR; 2346 goto ret; 2347 } 2348 memset(buf, 0, len); /* ? XXX */ 2349 totlen = len; 2350 break; 2351 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2352 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2353 index)); 2354 if (index < 1 || index > sc->sc_noport) { 2355 err = USBD_IOERROR; 2356 goto ret; 2357 } 2358 if (len != 4) { 2359 err = USBD_IOERROR; 2360 goto ret; 2361 } 2362 v = EOREAD4(sc, EHCI_PORTSC(index)); 2363 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2364 v)); 2365 i = UPS_HIGH_SPEED; 2366 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2367 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2368 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2369 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2370 if (v & EHCI_PS_PR) i |= UPS_RESET; 2371 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2372 USETW(ps.wPortStatus, i); 2373 i = 0; 2374 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2375 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2376 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2377 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2378 USETW(ps.wPortChange, i); 2379 l = min(len, sizeof ps); 2380 memcpy(buf, &ps, l); 2381 totlen = l; 2382 break; 2383 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2384 err = USBD_IOERROR; 2385 goto ret; 2386 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2387 break; 2388 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2389 if (index < 1 || index > sc->sc_noport) { 2390 err = USBD_IOERROR; 2391 goto ret; 2392 } 2393 port = EHCI_PORTSC(index); 2394 v = EOREAD4(sc, port); 2395 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2396 v &= ~EHCI_PS_CLEAR; 2397 switch(value) { 2398 case UHF_PORT_ENABLE: 2399 EOWRITE4(sc, port, v | EHCI_PS_PE); 2400 break; 2401 case UHF_PORT_SUSPEND: 2402 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2403 break; 2404 case UHF_PORT_RESET: 2405 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2406 index)); 2407 if (EHCI_PS_IS_LOWSPEED(v)) { 2408 /* Low speed device, give up ownership. */ 2409 ehci_disown(sc, index, 1); 2410 break; 2411 } 2412 /* Start reset sequence. */ 2413 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2414 EOWRITE4(sc, port, v | EHCI_PS_PR); 2415 /* Wait for reset to complete. */ 2416 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2417 if (sc->sc_dying) { 2418 err = USBD_IOERROR; 2419 goto ret; 2420 } 2421 /* Terminate reset sequence. */ 2422 EOWRITE4(sc, port, v); 2423 /* Wait for HC to complete reset. */ 2424 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2425 if (sc->sc_dying) { 2426 err = USBD_IOERROR; 2427 goto ret; 2428 } 2429 v = EOREAD4(sc, port); 2430 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2431 if (v & EHCI_PS_PR) { 2432 printf("%s: port reset timeout\n", 2433 USBDEVNAME(sc->sc_bus.bdev)); 2434 return (USBD_TIMEOUT); 2435 } 2436 if (!(v & EHCI_PS_PE)) { 2437 /* Not a high speed device, give up ownership.*/ 2438 ehci_disown(sc, index, 0); 2439 break; 2440 } 2441 sc->sc_isreset[index] = 1; 2442 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2443 index, v)); 2444 break; 2445 case UHF_PORT_POWER: 2446 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2447 "%d (has PPC = %d)\n", index, 2448 sc->sc_hasppc)); 2449 if (sc->sc_hasppc) 2450 EOWRITE4(sc, port, v | EHCI_PS_PP); 2451 break; 2452 case UHF_PORT_TEST: 2453 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2454 "%d\n", index)); 2455 break; 2456 case UHF_PORT_INDICATOR: 2457 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2458 "%d\n", index)); 2459 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2460 break; 2461 default: 2462 err = USBD_IOERROR; 2463 goto ret; 2464 } 2465 break; 2466 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2467 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2468 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2469 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2470 break; 2471 default: 2472 err = USBD_IOERROR; 2473 goto ret; 2474 } 2475 xfer->actlen = totlen; 2476 err = USBD_NORMAL_COMPLETION; 2477 ret: 2478 xfer->status = err; 2479 s = splusb(); 2480 usb_transfer_complete(xfer); 2481 splx(s); 2482 return (USBD_IN_PROGRESS); 2483 } 2484 2485 void 2486 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2487 { 2488 int port; 2489 u_int32_t v; 2490 2491 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2492 #ifdef DIAGNOSTIC 2493 if (sc->sc_npcomp != 0) { 2494 int i = (index-1) / sc->sc_npcomp; 2495 if (i >= sc->sc_ncomp) 2496 printf("%s: strange port\n", 2497 USBDEVNAME(sc->sc_bus.bdev)); 2498 else 2499 printf("%s: handing over %s speed device on " 2500 "port %d to %s\n", 2501 USBDEVNAME(sc->sc_bus.bdev), 2502 lowspeed ? "low" : "full", 2503 index, USBDEVNAME(sc->sc_comps[i]->bdev)); 2504 } else { 2505 printf("%s: npcomp == 0\n", USBDEVNAME(sc->sc_bus.bdev)); 2506 } 2507 #endif 2508 port = EHCI_PORTSC(index); 2509 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2510 EOWRITE4(sc, port, v | EHCI_PS_PO); 2511 } 2512 2513 /* Abort a root control request. */ 2514 Static void 2515 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2516 { 2517 /* Nothing to do, all transfers are synchronous. */ 2518 } 2519 2520 /* Close the root pipe. */ 2521 Static void 2522 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2523 { 2524 DPRINTF(("ehci_root_ctrl_close\n")); 2525 /* Nothing to do. */ 2526 } 2527 2528 void 2529 ehci_root_intr_done(usbd_xfer_handle xfer) 2530 { 2531 } 2532 2533 Static usbd_status 2534 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2535 { 2536 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2537 usbd_status err; 2538 2539 /* Insert last in queue. */ 2540 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 2541 &EXFER(xfer)->dmabuf); 2542 if (err) 2543 return (err); 2544 2545 /* Pipe isn't running, start first */ 2546 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2547 } 2548 2549 Static usbd_status 2550 ehci_root_intr_start(usbd_xfer_handle xfer) 2551 { 2552 usbd_pipe_handle pipe = xfer->pipe; 2553 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2554 2555 if (sc->sc_dying) 2556 return (USBD_IOERROR); 2557 2558 if (xfer->rqflags & URQ_DEV_MAP_MBUF) 2559 return (USBD_INVAL); /* mbuf transfer is not supported */ 2560 2561 sc->sc_intrxfer = xfer; 2562 2563 return (USBD_IN_PROGRESS); 2564 } 2565 2566 /* Abort a root interrupt request. */ 2567 Static void 2568 ehci_root_intr_abort(usbd_xfer_handle xfer) 2569 { 2570 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2571 int s; 2572 2573 if (xfer->pipe->intrxfer == xfer) { 2574 DPRINTF(("ehci_root_intr_abort: remove\n")); 2575 xfer->pipe->intrxfer = NULL; 2576 } 2577 xfer->status = USBD_CANCELLED; 2578 s = splusb(); 2579 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 2580 splx(s); 2581 } 2582 2583 /* Close the root pipe. */ 2584 Static void 2585 ehci_root_intr_close(usbd_pipe_handle pipe) 2586 { 2587 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2588 2589 DPRINTF(("ehci_root_intr_close\n")); 2590 2591 sc->sc_intrxfer = NULL; 2592 } 2593 2594 void 2595 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2596 { 2597 } 2598 2599 /************************/ 2600 2601 ehci_soft_qh_t * 2602 ehci_alloc_sqh(ehci_softc_t *sc) 2603 { 2604 ehci_soft_qh_t *sqh; 2605 ehci_soft_qtd_t *sqtd; 2606 usbd_status err; 2607 int i, offs; 2608 usb_dma_t dma; 2609 struct ehci_mem_desc *em; 2610 2611 if (sc->sc_freeqhs == NULL) { 2612 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2613 err = usb_allocmem(&sc->sc_dmatag, 2614 EHCI_SQH_SIZE*EHCI_SQH_CHUNK + sizeof(struct ehci_mem_desc), 2615 EHCI_PAGE_SIZE, &dma); 2616 #ifdef EHCI_DEBUG 2617 if (err) 2618 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2619 #endif 2620 if (err) 2621 return (NULL); 2622 em = KERNADDR(&dma, EHCI_SQH_SIZE * EHCI_SQH_CHUNK); 2623 em->em_top = KERNADDR(&dma, 0); 2624 em->em_topdma = DMAADDR(&dma, 0); 2625 em->em_dma = dma; 2626 SIMPLEQ_INSERT_HEAD(&sc->sc_sqh_chunks, em, em_next); 2627 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2628 offs = i * EHCI_SQH_SIZE; 2629 sqh = KERNADDR(&dma, offs); 2630 sqh->eh_mdesc = em; 2631 sqh->next = sc->sc_freeqhs; 2632 sc->sc_freeqhs = sqh; 2633 } 2634 } 2635 /* Allocate the initial inactive sqtd. */ 2636 sqtd = ehci_alloc_sqtd_norsv(sc); 2637 if (sqtd == NULL) 2638 return (NULL); 2639 sqtd->qtd.qtd_status = htole32(0); 2640 sqtd->qtd.qtd_next = EHCI_NULL; 2641 sqtd->qtd.qtd_altnext = EHCI_NULL; 2642 2643 sqh = sc->sc_freeqhs; 2644 sc->sc_freeqhs = sqh->next; 2645 2646 /* The overlay QTD should begin zeroed. */ 2647 sqh->qh.qh_qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(sqtd)); 2648 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2649 sqh->qh.qh_qtd.qtd_status = 0; 2650 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) { 2651 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2652 sqh->qh.qh_qtd.qtd_buffer_hi[i] = 0; 2653 } 2654 sqh->next = NULL; 2655 sqh->prev = NULL; 2656 sqh->sqtd = sqtd; 2657 sqh->inactivesqtd = sqtd; 2658 return (sqh); 2659 } 2660 2661 void 2662 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2663 { 2664 ehci_free_sqtd_norsv(sc, sqh->inactivesqtd); 2665 sqh->next = sc->sc_freeqhs; 2666 sc->sc_freeqhs = sqh; 2667 } 2668 2669 Static usbd_status 2670 ehci_grow_sqtd(ehci_softc_t *sc) 2671 { 2672 usb_dma_t dma; 2673 struct ehci_mem_desc *em; 2674 ehci_soft_qtd_t *sqtd; 2675 usbd_status err; 2676 int i, s, offs; 2677 2678 DPRINTFN(2, ("ehci_grow_sqtd: allocating chunk\n")); 2679 err = usb_allocmem(&sc->sc_dmatag, 2680 EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK + sizeof(struct ehci_mem_desc), 2681 EHCI_PAGE_SIZE, &dma); 2682 #ifdef EHCI_DEBUG 2683 if (err) 2684 printf("ehci_grow_sqtd: usb_allocmem()=%d\n", err); 2685 #endif 2686 if (err) 2687 return (err); 2688 em = KERNADDR(&dma, EHCI_SQTD_SIZE * EHCI_SQTD_CHUNK); 2689 em->em_top = KERNADDR(&dma, 0); 2690 em->em_topdma = DMAADDR(&dma, 0); 2691 em->em_dma = dma; 2692 s = splusb(); 2693 SIMPLEQ_INSERT_HEAD(&sc->sc_sqtd_chunks, em, em_next); 2694 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2695 offs = i * EHCI_SQTD_SIZE; 2696 sqtd = KERNADDR(&dma, offs); 2697 sqtd->et_mdesc = em; 2698 sqtd->nextqtd = sc->sc_freeqtds; 2699 sc->sc_freeqtds = sqtd; 2700 sc->sc_nfreeqtds++; 2701 } 2702 splx(s); 2703 2704 return (USBD_NORMAL_COMPLETION); 2705 } 2706 2707 ehci_soft_qtd_t * 2708 ehci_alloc_sqtd(ehci_softc_t *sc) 2709 { 2710 ehci_soft_qtd_t *sqtd; 2711 int i; 2712 int s; 2713 2714 s = splusb(); 2715 2716 #ifdef DIAGNOSTIC 2717 if (sc->sc_freeqtds == NULL) 2718 panic("ehci_alloc_sqtd: %p %d", 2719 sc->sc_freeqtds, sc->sc_nfreeqtds); 2720 #endif 2721 sqtd = sc->sc_freeqtds; 2722 sc->sc_freeqtds = sqtd->nextqtd; 2723 splx(s); 2724 sqtd->qtd.qtd_next = EHCI_NULL; 2725 sqtd->qtd.qtd_altnext = EHCI_NULL; 2726 sqtd->qtd.qtd_status = 0; 2727 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) { 2728 sqtd->qtd.qtd_buffer[i] = 0; 2729 sqtd->qtd.qtd_buffer_hi[i] = 0; 2730 } 2731 sqtd->nextqtd = NULL; 2732 sqtd->xfer = NULL; 2733 2734 return (sqtd); 2735 } 2736 2737 Static ehci_soft_qtd_t * 2738 ehci_alloc_sqtd_norsv(ehci_softc_t *sc) 2739 { 2740 int s; 2741 2742 s = splusb(); 2743 if (sc->sc_nfreeqtds < 1) 2744 if (ehci_grow_sqtd(sc)) 2745 return (NULL); 2746 sc->sc_nfreeqtds--; 2747 splx(s); 2748 return (ehci_alloc_sqtd(sc)); 2749 } 2750 2751 void 2752 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2753 { 2754 int s; 2755 2756 s = splusb(); 2757 sqtd->nextqtd = sc->sc_freeqtds; 2758 sc->sc_freeqtds = sqtd; 2759 splx(s); 2760 } 2761 2762 Static void 2763 ehci_free_sqtd_norsv(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2764 { 2765 int s; 2766 2767 ehci_free_sqtd(sc, sqtd); 2768 s = splusb(); 2769 sc->sc_nfreeqtds++; 2770 splx(s); 2771 } 2772 2773 usbd_status 2774 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2775 int alen, int rd, usbd_xfer_handle xfer, ehci_soft_qtd_t *start, 2776 ehci_soft_qtd_t *newinactive, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2777 { 2778 usb_endpoint_descriptor_t *endpt; 2779 ehci_soft_qtd_t *next, *cur; 2780 ehci_physaddr_t dataphys, nextphys; 2781 u_int32_t qtdstatus; 2782 int adj, len, curlen, mps, offset, pagelen, seg, segoff; 2783 int i, iscontrol, forceshort; 2784 struct usb_buffer_dma *ub = &EXFER(xfer)->dmabuf; 2785 bus_dma_segment_t *segs = USB_BUFFER_SEGS(ub); 2786 int nsegs = USB_BUFFER_NSEGS(ub); 2787 int needaux; 2788 int isread; 2789 union usb_bufptr bufptr; 2790 struct aux_desc ad; 2791 bus_addr_t auxdma; 2792 2793 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2794 2795 offset = 0; 2796 len = alen; 2797 iscontrol = (epipe->pipe.endpoint->edesc->bmAttributes & UE_XFERTYPE) == 2798 UE_CONTROL; 2799 qtdstatus = EHCI_QTD_ACTIVE | 2800 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2801 EHCI_QTD_SET_CERR(3) 2802 /* IOC set below */ 2803 /* BYTES set below */ 2804 ; 2805 endpt = epipe->pipe.endpoint->edesc; 2806 mps = UE_MAXPKTSZ(endpt); 2807 forceshort = ((xfer->flags & USBD_FORCE_SHORT_XFER) || len == 0) && 2808 len % mps == 0; 2809 /* 2810 * The control transfer data stage always starts with a toggle of 1. 2811 * For other transfers we let the hardware track the toggle state. 2812 */ 2813 if (iscontrol) 2814 qtdstatus |= EHCI_QTD_SET_TOGGLE(1); 2815 2816 /* 2817 * aux memory is possibly required if 2818 * buffer has more than one segments, 2819 * the transfer direction is OUT, 2820 * and 2821 * buffer is an mbuf chain, or 2822 * buffer is not mps aligned 2823 */ 2824 isread = UE_GET_DIR(endpt->bEndpointAddress) == UE_DIR_IN; 2825 needaux = 2826 nsegs > 1 && !isread && 2827 ((xfer->rqflags & URQ_DEV_MAP_MBUF) || 2828 (mps & (mps - 1)) != 0 /* mps is not a power of 2 */ || 2829 (segs[0].ds_addr & (mps - 1)) != 0 /* buffer is unaligned */); 2830 2831 if (needaux) { 2832 usb_bufptr_init(&bufptr, xfer); 2833 if (EXFER(xfer)->aux.aux_naux) { 2834 /* sync previous aux (just in case, probably a no-op) */ 2835 ehci_aux_dma_sync(sc, &EXFER(xfer)->aux, 2836 BUS_DMASYNC_POSTWRITE); 2837 2838 ehci_aux_mem_init(&EXFER(xfer)->aux); 2839 } 2840 } 2841 2842 if (start != NULL) { 2843 /* 2844 * If we are given a starting qTD, assume it is linked into 2845 * an active QH so be careful not to mark it active. 2846 */ 2847 cur = start; 2848 *sp = cur; 2849 qtdstatus &= ~EHCI_QTD_ACTIVE; 2850 } else { 2851 cur = ehci_alloc_sqtd(sc); 2852 *sp = cur; 2853 if (cur == NULL) 2854 goto nomem; 2855 } 2856 seg = 0; 2857 segoff = 0; 2858 for (;;) { 2859 curlen = 0; 2860 2861 /* The EHCI hardware can handle at most 5 pages. */ 2862 for (i = 0; i < EHCI_QTD_NBUFFERS && curlen < len; i++) { 2863 USB_KASSERT2(seg < nsegs, 2864 ("ehci_alloc_sqtd_chain: overrun")); 2865 dataphys = segs[seg].ds_addr + segoff; 2866 pagelen = segs[seg].ds_len - segoff; 2867 if (pagelen > len - curlen) 2868 pagelen = len - curlen; 2869 if (pagelen > EHCI_PAGE_SIZE - 2870 EHCI_PAGE_OFFSET(dataphys)) 2871 pagelen = EHCI_PAGE_SIZE - 2872 EHCI_PAGE_OFFSET(dataphys); 2873 segoff += pagelen; 2874 if (segoff >= segs[seg].ds_len) { 2875 USB_KASSERT2(segoff == segs[seg].ds_len, 2876 ("ehci_alloc_sqtd_chain: overlap")); 2877 seg++; 2878 segoff = 0; 2879 } 2880 2881 cur->qtd.qtd_buffer[i] = htole32(dataphys); 2882 cur->qtd.qtd_buffer_hi[i] = 0; 2883 curlen += pagelen; 2884 2885 /* 2886 * Must stop if there is any gap before or after 2887 * the page boundary. 2888 */ 2889 if (EHCI_PAGE_OFFSET(dataphys + pagelen) != 0) 2890 break; 2891 if (seg < nsegs && EHCI_PAGE_OFFSET(segoff + 2892 segs[seg].ds_addr) != 0) 2893 break; 2894 } 2895 /* Adjust down to a multiple of mps if not at the end. */ 2896 if (!isread && curlen < len && (adj = curlen % mps) != 0) { 2897 curlen -= adj; 2898 if (curlen == 0) { 2899 USB_KASSERT(needaux); 2900 /* need aux -- a packet is not contiguous */ 2901 curlen = len < mps ? len : mps; 2902 auxdma = ehci_aux_dma_alloc(&EXFER(xfer)->aux, 2903 curlen, &ad); 2904 2905 /* prepare aux DMA */ 2906 usb_bufptr_wr(&bufptr, ad.aux_kern, curlen, 2907 xfer->rqflags & URQ_DEV_MAP_MBUF); 2908 cur->qtd.qtd_buffer[i] = htole32(auxdma); 2909 cur->qtd.qtd_buffer_hi[i] = 0; 2910 2911 /* skip handled segments */ 2912 segoff += curlen - adj; 2913 do { 2914 segoff -= segs[seg].ds_len; 2915 seg++; 2916 } while (segoff > segs[seg].ds_len); 2917 2918 } else { 2919 segoff -= adj; 2920 if (segoff < 0) { 2921 seg--; 2922 segoff += segs[seg].ds_len; 2923 } 2924 USB_KASSERT2(seg >= 0 && segoff >= 0, 2925 ("ehci_alloc_sqtd_chain: adjust to mps")); 2926 } 2927 } 2928 2929 len -= curlen; 2930 2931 if (len != 0 || forceshort) { 2932 next = ehci_alloc_sqtd(sc); 2933 if (next == NULL) 2934 goto nomem; 2935 nextphys = htole32(EHCI_SQTD_DMAADDR(next)); 2936 } else { 2937 next = NULL; 2938 nextphys = EHCI_NULL; 2939 } 2940 2941 cur->nextqtd = next; 2942 cur->qtd.qtd_next = nextphys; 2943 /* Make sure to stop after a short transfer. */ 2944 cur->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 2945 cur->qtd.qtd_status = 2946 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2947 cur->xfer = xfer; 2948 cur->len = curlen; 2949 DPRINTFN(10,("ehci_alloc_sqtd_chain: curlen=%d\n", curlen)); 2950 if (iscontrol) { 2951 /* 2952 * adjust the toggle based on the number of packets 2953 * in this qtd 2954 */ 2955 if ((((curlen + mps - 1) / mps) & 1) || curlen == 0) 2956 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2957 } 2958 qtdstatus |= EHCI_QTD_ACTIVE; 2959 if (len == 0) { 2960 if (!forceshort) 2961 break; 2962 forceshort = 0; 2963 } 2964 EHCI_SQTD_SYNC(sc, cur, 2965 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2966 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2967 offset += curlen; 2968 cur = next; 2969 2970 if (needaux) 2971 usb_bufptr_advance(&bufptr, curlen, 2972 xfer->rqflags & URQ_DEV_MAP_MBUF); 2973 } 2974 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2975 EHCI_SQTD_SYNC(sc, cur, 2976 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2977 if (needaux) 2978 ehci_aux_dma_sync(sc, &EXFER(xfer)->aux, BUS_DMASYNC_PREWRITE); 2979 2980 *ep = cur; 2981 2982 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2983 *sp, *ep)); 2984 2985 return (USBD_NORMAL_COMPLETION); 2986 2987 nomem: 2988 /* XXX free chain */ 2989 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2990 return (USBD_NOMEM); 2991 } 2992 2993 /* Free the chain starting at sqtd and end at the qTD before sqtdend */ 2994 Static void 2995 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qh_t *sqh, 2996 ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *sqtdend) 2997 { 2998 ehci_soft_qtd_t *p, **prevp; 2999 int i; 3000 3001 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 3002 sqtd, sqtdend)); 3003 3004 /* First unlink the chain from the QH's software qTD list. */ 3005 prevp = &sqh->sqtd; 3006 for (p = sqh->sqtd; p != NULL; p = p->nextqtd) { 3007 if (p == sqtd) { 3008 *prevp = sqtdend; 3009 break; 3010 } 3011 prevp = &p->nextqtd; 3012 } 3013 USB_KASSERT2(p != NULL, ("ehci_free_sqtd_chain: chain not found")); 3014 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 3015 p = sqtd->nextqtd; 3016 ehci_free_sqtd(sc, sqtd); 3017 } 3018 } 3019 3020 /****************/ 3021 3022 /* 3023 * Close a reqular pipe. 3024 * Assumes that there are no pending transactions. 3025 */ 3026 void 3027 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3028 { 3029 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3030 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3031 ehci_soft_qh_t *sqh = epipe->sqh; 3032 int s; 3033 3034 s = splusb(); 3035 ehci_rem_qh(sc, sqh, head); 3036 splx(s); 3037 pipe->endpoint->savedtoggle = 3038 EHCI_QTD_GET_TOGGLE(le32toh(sqh->qh.qh_qtd.qtd_status)); 3039 ehci_free_sqh(sc, epipe->sqh); 3040 } 3041 3042 /* 3043 * Abort a device request. 3044 * If this routine is called at splusb() it guarantees that the request 3045 * will be removed from the hardware scheduling and that the callback 3046 * for it will be called with USBD_CANCELLED status. 3047 * It's impossible to guarantee that the requested transfer will not 3048 * have happened since the hardware runs concurrently. 3049 * If the transaction has already happened we rely on the ordinary 3050 * interrupt processing to process it. 3051 */ 3052 void 3053 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3054 { 3055 #define exfer EXFER(xfer) 3056 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3057 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 3058 ehci_soft_qh_t *sqh = epipe->sqh; 3059 ehci_soft_qtd_t *sqtd, *snext; 3060 ehci_physaddr_t cur, us, next; 3061 int s; 3062 int hit, i; 3063 /* int count = 0; */ 3064 ehci_soft_qh_t *psqh; 3065 3066 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 3067 3068 if (sc->sc_dying) { 3069 /* If we're dying, just do the software part. */ 3070 s = splusb(); 3071 xfer->status = status; /* make software ignore it */ 3072 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3073 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 3074 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, 3075 &EXFER(xfer)->dmabuf); 3076 splx(s); 3077 return; 3078 } 3079 3080 if (xfer->device->bus->intr_context || !curproc) 3081 panic("ehci_abort_xfer: not in process context"); 3082 3083 /* 3084 * If an abort is already in progress then just wait for it to 3085 * complete and return. 3086 */ 3087 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) { 3088 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3089 /* No need to wait if we're aborting from a timeout. */ 3090 if (status == USBD_TIMEOUT) 3091 return; 3092 /* Override the status which might be USBD_TIMEOUT. */ 3093 xfer->status = status; 3094 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3095 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTWAIT; 3096 while (exfer->ehci_xfer_flags & EHCI_XFER_ABORTING) 3097 tsleep(&exfer->ehci_xfer_flags, PZERO, "ehciaw", 0); 3098 return; 3099 } 3100 3101 /* 3102 * Step 1: Make interrupt routine and timeouts ignore xfer. 3103 */ 3104 s = splusb(); 3105 exfer->ehci_xfer_flags |= EHCI_XFER_ABORTING; 3106 xfer->status = status; /* make software ignore it */ 3107 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3108 usb_rem_task(epipe->pipe.device, &exfer->abort_task); 3109 splx(s); 3110 3111 /* 3112 * Step 2: Wait until we know hardware has finished any possible 3113 * use of the xfer. We do this by removing the entire 3114 * queue from the async schedule and waiting for the doorbell. 3115 * Nothing else should be touching the queue now. 3116 */ 3117 psqh = sqh->prev; 3118 ehci_rem_qh(sc, sqh, psqh); 3119 3120 /* 3121 * Step 3: make sure the soft interrupt routine 3122 * has run. This should remove any completed items off the queue. 3123 * The hardware has no reference to completed items (TDs). 3124 * It's safe to remove them at any time. 3125 */ 3126 s = splusb(); 3127 #ifdef USB_USE_SOFTINTR 3128 sc->sc_softwake = 1; 3129 #endif /* USB_USE_SOFTINTR */ 3130 usb_schedsoftintr(&sc->sc_bus); 3131 #ifdef USB_USE_SOFTINTR 3132 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3133 #endif /* USB_USE_SOFTINTR */ 3134 3135 /* 3136 * Step 4: Remove any vestiges of the xfer from the hardware. 3137 * The complication here is that the hardware may have executed 3138 * into or even beyond the xfer we're trying to abort. 3139 * So as we're scanning the TDs of this xfer we check if 3140 * the hardware points to any of them. 3141 * 3142 * first we need to see if there are any transfers 3143 * on this queue before the xfer we are aborting.. we need 3144 * to update any pointers that point to us to point past 3145 * the aborting xfer. (If there is something past us). 3146 * Hardware and software. 3147 */ 3148 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3149 hit = 0; 3150 3151 /* If they initially point here. */ 3152 us = EHCI_SQTD_DMAADDR(exfer->sqtdstart); 3153 3154 /* We will change them to point here */ 3155 snext = exfer->sqtdend->nextqtd; 3156 next = htole32(EHCI_SQTD_DMAADDR(snext)); 3157 3158 /* 3159 * Now loop through any qTDs before us and keep track of the pointer 3160 * that points to us for the end. 3161 */ 3162 sqtd = sqh->sqtd; 3163 while (sqtd && sqtd != exfer->sqtdstart) { 3164 hit |= (cur == EHCI_SQTD_DMAADDR(sqtd)); 3165 if (EHCI_LINK_ADDR(le32toh(sqtd->qtd.qtd_next)) == us) { 3166 sqtd->qtd.qtd_next = next; 3167 EHCI_SQTD_SYNC(sc, sqtd, 3168 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3169 } 3170 if (EHCI_LINK_ADDR(le32toh(sqtd->qtd.qtd_altnext)) == us) { 3171 sqtd->qtd.qtd_altnext = next; 3172 EHCI_SQTD_SYNC(sc, sqtd, 3173 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3174 } 3175 sqtd = sqtd->nextqtd; 3176 } 3177 3178 /* 3179 * If we already saw the active one then we are pretty much done. 3180 * We've done all the relinking we need to do. 3181 */ 3182 if (!hit) { 3183 3184 /* 3185 * Now reinitialise the QH to point to the next qTD 3186 * (if there is one). We only need to do this if 3187 * it was previously pointing to us. 3188 */ 3189 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3190 if (cur == EHCI_SQTD_DMAADDR(sqtd)) { 3191 hit++; 3192 } 3193 if (sqtd == exfer->sqtdend) 3194 break; 3195 } 3196 sqtd = sqtd->nextqtd; 3197 /* 3198 * Only need to alter the QH if it was pointing at a qTD 3199 * that we are removing. 3200 */ 3201 if (hit) { 3202 sqh->qh.qh_qtd.qtd_next = 3203 htole32(EHCI_SQTD_DMAADDR(snext)); 3204 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 3205 sqh->qh.qh_qtd.qtd_status &= 3206 htole32(EHCI_QTD_TOGGLE_MASK); 3207 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) { 3208 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 3209 sqh->qh.qh_qtd.qtd_buffer_hi[i] = 0; 3210 } 3211 } 3212 } 3213 ehci_add_qh(sc, sqh, psqh); 3214 /* 3215 * Step 5: Execute callback. 3216 */ 3217 #ifdef DIAGNOSTIC 3218 exfer->isdone = 1; 3219 #endif 3220 /* Do the wakeup first to avoid touching the xfer after the callback. */ 3221 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTING; 3222 if (exfer->ehci_xfer_flags & EHCI_XFER_ABORTWAIT) { 3223 exfer->ehci_xfer_flags &= ~EHCI_XFER_ABORTWAIT; 3224 wakeup(&exfer->ehci_xfer_flags); 3225 } 3226 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, &EXFER(xfer)->dmabuf); 3227 3228 /* printf("%s: %d TDs aborted\n", __func__, count); */ 3229 splx(s); 3230 #undef exfer 3231 } 3232 3233 void 3234 ehci_timeout(void *addr) 3235 { 3236 struct ehci_xfer *exfer = addr; 3237 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3238 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 3239 3240 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3241 #ifdef USB_DEBUG 3242 if (ehcidebug > 1) 3243 usbd_dump_pipe(exfer->xfer.pipe); 3244 #endif 3245 3246 if (sc->sc_dying) { 3247 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3248 return; 3249 } 3250 3251 /* Execute the abort in a process context. */ 3252 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3253 USB_TASKQ_HC); 3254 } 3255 3256 void 3257 ehci_timeout_task(void *addr) 3258 { 3259 usbd_xfer_handle xfer = addr; 3260 int s; 3261 3262 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3263 3264 s = splusb(); 3265 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3266 splx(s); 3267 } 3268 3269 /* 3270 * Some EHCI chips from VIA / ATI seem to trigger interrupts before writing 3271 * back the qTD status, or miss signalling occasionally under heavy load. 3272 * If the host machine is too fast, we can miss transaction completion - when 3273 * we scan the active list the transaction still seems to be active. This 3274 * generally exhibits itself as a umass stall that never recovers. 3275 * 3276 * We work around this behaviour by setting up this callback after any softintr 3277 * that completes with transactions still pending, giving us another chance to 3278 * check for completion after the writeback has taken place. 3279 */ 3280 void 3281 ehci_intrlist_timeout(void *arg) 3282 { 3283 ehci_softc_t *sc = arg; 3284 int s = splusb(); 3285 3286 DPRINTFN(3, ("ehci_intrlist_timeout\n")); 3287 usb_schedsoftintr(&sc->sc_bus); 3288 3289 splx(s); 3290 } 3291 3292 /************************/ 3293 3294 Static usbd_status 3295 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3296 { 3297 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3298 usbd_status err; 3299 3300 /* Insert last in queue. */ 3301 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3302 &EXFER(xfer)->dmabuf); 3303 if (err) 3304 return (err); 3305 3306 /* Pipe isn't running, start first */ 3307 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3308 } 3309 3310 Static usbd_status 3311 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3312 { 3313 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3314 usbd_status err; 3315 3316 if (sc->sc_dying) 3317 return (USBD_IOERROR); 3318 3319 #ifdef DIAGNOSTIC 3320 if (!(xfer->rqflags & URQ_REQUEST)) { 3321 /* XXX panic */ 3322 printf("ehci_device_ctrl_transfer: not a request\n"); 3323 return (USBD_INVAL); 3324 } 3325 #endif 3326 3327 err = ehci_device_request(xfer); 3328 if (err) 3329 return (err); 3330 3331 if (sc->sc_bus.use_polling) 3332 ehci_waitintr(sc, xfer); 3333 return (USBD_IN_PROGRESS); 3334 } 3335 3336 void 3337 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3338 { 3339 struct ehci_xfer *ex = EXFER(xfer); 3340 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3341 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3342 3343 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3344 3345 #ifdef DIAGNOSTIC 3346 if (!(xfer->rqflags & URQ_REQUEST)) { 3347 panic("ehci_ctrl_done: not a request"); 3348 } 3349 #endif 3350 3351 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3352 ehci_del_intr_list(ex); /* remove from active list */ 3353 ehci_free_sqtd_chain(sc, epipe->sqh, ex->sqtdstart, 3354 ex->sqtdend->nextqtd); 3355 } 3356 3357 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3358 } 3359 3360 /* Abort a device control request. */ 3361 Static void 3362 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3363 { 3364 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3365 ehci_abort_xfer(xfer, USBD_CANCELLED); 3366 } 3367 3368 /* Close a device control pipe. */ 3369 Static void 3370 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3371 { 3372 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3373 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3374 3375 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3376 ehci_close_pipe(pipe, sc->sc_async_head); 3377 usb_freemem(&sc->sc_dmatag, &epipe->u.ctl.reqdma); 3378 } 3379 3380 usbd_status 3381 ehci_device_request(usbd_xfer_handle xfer) 3382 { 3383 #define exfer EXFER(xfer) 3384 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3385 usb_device_request_t *req = &xfer->request; 3386 usbd_device_handle dev = epipe->pipe.device; 3387 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3388 ehci_soft_qtd_t *newinactive, *setup, *stat, *next; 3389 ehci_soft_qh_t *sqh; 3390 int isread; 3391 int len; 3392 usbd_status err; 3393 int s; 3394 3395 isread = req->bmRequestType & UT_READ; 3396 len = UGETW(req->wLength); 3397 3398 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3399 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3400 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3401 UGETW(req->wIndex), len, dev->address, 3402 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3403 3404 newinactive = ehci_alloc_sqtd(sc); 3405 if (newinactive == NULL) { 3406 err = USBD_NOMEM; 3407 goto bad1; 3408 } 3409 newinactive->qtd.qtd_status = htole32(0); 3410 newinactive->qtd.qtd_next = EHCI_NULL; 3411 newinactive->qtd.qtd_altnext = EHCI_NULL; 3412 EHCI_SQTD_SYNC(sc, newinactive, 3413 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3414 stat = ehci_alloc_sqtd(sc); 3415 if (stat == NULL) { 3416 err = USBD_NOMEM; 3417 goto bad2; 3418 } 3419 3420 sqh = epipe->sqh; 3421 setup = sqh->inactivesqtd; 3422 sqh->inactivesqtd = newinactive; 3423 epipe->u.ctl.length = len; 3424 3425 /* Set up data transaction */ 3426 if (len != 0) { 3427 ehci_soft_qtd_t *end; 3428 3429 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3430 NULL, newinactive, &next, &end); 3431 if (err) 3432 goto bad3; 3433 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3434 end->nextqtd = stat; 3435 end->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(stat)); 3436 end->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3437 } else { 3438 next = stat; 3439 } 3440 3441 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3442 3443 /* Clear toggle, and do not activate until complete */ 3444 setup->qtd.qtd_status = htole32( 3445 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3446 EHCI_QTD_SET_CERR(3) | 3447 EHCI_QTD_SET_TOGGLE(0) | 3448 EHCI_QTD_SET_BYTES(sizeof *req) 3449 ); 3450 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3451 setup->qtd.qtd_buffer_hi[0] = 0; 3452 setup->nextqtd = next; 3453 setup->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(next)); 3454 setup->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3455 setup->xfer = xfer; 3456 setup->len = sizeof *req; 3457 EHCI_SQTD_SYNC(sc, setup, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3458 3459 stat->qtd.qtd_status = htole32( 3460 EHCI_QTD_ACTIVE | 3461 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3462 EHCI_QTD_SET_CERR(3) | 3463 EHCI_QTD_SET_TOGGLE(1) | 3464 EHCI_QTD_IOC 3465 ); 3466 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3467 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3468 stat->nextqtd = newinactive; 3469 stat->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3470 stat->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3471 stat->xfer = xfer; 3472 stat->len = 0; 3473 EHCI_SQTD_SYNC(sc, stat, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3474 3475 #ifdef EHCI_DEBUG 3476 if (ehcidebug > 5) { 3477 DPRINTF(("ehci_device_request:\n")); 3478 ehci_dump_sqh(sqh); 3479 ehci_dump_sqtds(setup); 3480 } 3481 #endif 3482 3483 exfer->sqtdstart = setup; 3484 exfer->sqtdend = stat; 3485 #ifdef DIAGNOSTIC 3486 if (!exfer->isdone) { 3487 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3488 } 3489 exfer->isdone = 0; 3490 #endif 3491 3492 /* Activate the new qTD in the QH list. */ 3493 s = splusb(); 3494 ehci_activate_qh(sc, sqh, setup); 3495 if (xfer->timeout && !sc->sc_bus.use_polling) { 3496 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 3497 ehci_timeout, xfer); 3498 } 3499 ehci_add_intr_list(sc, exfer); 3500 xfer->status = USBD_IN_PROGRESS; 3501 splx(s); 3502 3503 #ifdef EHCI_DEBUG 3504 if (ehcidebug > 10) { 3505 DPRINTF(("ehci_device_request: status=%x\n", 3506 EOREAD4(sc, EHCI_USBSTS))); 3507 delay(10000); 3508 ehci_dump_regs(sc); 3509 ehci_dump_sqh(sc->sc_async_head); 3510 ehci_dump_sqh(sqh); 3511 ehci_dump_sqtds(setup); 3512 } 3513 #endif 3514 3515 return (USBD_NORMAL_COMPLETION); 3516 3517 bad3: 3518 sqh->inactivesqtd = setup; 3519 ehci_free_sqtd(sc, stat); 3520 bad2: 3521 ehci_free_sqtd(sc, newinactive); 3522 bad1: 3523 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3524 xfer->status = err; 3525 usb_transfer_complete_dma(xfer, &sc->sc_dmatag, 3526 &EXFER(xfer)->dmabuf); 3527 return (err); 3528 #undef exfer 3529 } 3530 3531 /************************/ 3532 3533 Static usbd_status 3534 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3535 { 3536 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3537 usbd_status err; 3538 3539 /* Insert last in queue. */ 3540 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3541 &EXFER(xfer)->dmabuf); 3542 if (err) 3543 return (err); 3544 3545 /* Pipe isn't running, start first */ 3546 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3547 } 3548 3549 usbd_status 3550 ehci_device_bulk_start(usbd_xfer_handle xfer) 3551 { 3552 #define exfer EXFER(xfer) 3553 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3554 usbd_device_handle dev = epipe->pipe.device; 3555 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3556 ehci_soft_qtd_t *data, *dataend, *newinactive; 3557 ehci_soft_qh_t *sqh; 3558 usbd_status err; 3559 int len, isread, endpt; 3560 int s; 3561 3562 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3563 xfer, xfer->length, xfer->flags)); 3564 3565 if (sc->sc_dying) 3566 return (USBD_IOERROR); 3567 3568 #ifdef DIAGNOSTIC 3569 if (xfer->rqflags & URQ_REQUEST) 3570 panic("ehci_device_bulk_start: a request"); 3571 #endif 3572 3573 len = xfer->length; 3574 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3575 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3576 sqh = epipe->sqh; 3577 3578 epipe->u.bulk.length = len; 3579 3580 newinactive = ehci_alloc_sqtd(sc); 3581 if (newinactive == NULL) { 3582 DPRINTFN(-1,("ehci_device_bulk_start: no sqtd memory\n")); 3583 err = USBD_NOMEM; 3584 xfer->status = err; 3585 usb_transfer_complete(xfer); 3586 return (err); 3587 } 3588 newinactive->qtd.qtd_status = htole32(0); 3589 newinactive->qtd.qtd_next = EHCI_NULL; 3590 newinactive->qtd.qtd_altnext = EHCI_NULL; 3591 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3592 sqh->inactivesqtd, newinactive, &data, &dataend); 3593 if (err) { 3594 DPRINTFN(-1,("ehci_device_bulk_start: no memory\n")); 3595 ehci_free_sqtd(sc, newinactive); 3596 xfer->status = err; 3597 usb_transfer_complete(xfer); 3598 return (err); 3599 } 3600 dataend->nextqtd = newinactive; 3601 dataend->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3602 dataend->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3603 sqh->inactivesqtd = newinactive; 3604 EHCI_SQTD_SYNC(sc, newinactive, 3605 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3606 EHCI_SQTD_SYNC(sc, dataend, 3607 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3608 3609 #ifdef EHCI_DEBUG 3610 if (ehcidebug > 5) { 3611 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3612 ehci_dump_sqh(sqh); 3613 ehci_dump_sqtds(data); 3614 } 3615 #endif 3616 3617 /* Set up interrupt info. */ 3618 exfer->sqtdstart = data; 3619 exfer->sqtdend = dataend; 3620 #ifdef DIAGNOSTIC 3621 if (!exfer->isdone) { 3622 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3623 } 3624 exfer->isdone = 0; 3625 #endif 3626 3627 s = splusb(); 3628 ehci_activate_qh(sc, sqh, data); 3629 if (xfer->timeout && !sc->sc_bus.use_polling) { 3630 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 3631 ehci_timeout, xfer); 3632 } 3633 ehci_add_intr_list(sc, exfer); 3634 xfer->status = USBD_IN_PROGRESS; 3635 splx(s); 3636 3637 #ifdef EHCI_DEBUG 3638 if (ehcidebug > 10) { 3639 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3640 delay(10000); 3641 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3642 ehci_dump_regs(sc); 3643 #if 0 3644 printf("async_head:\n"); 3645 ehci_dump_sqh(sc->sc_async_head); 3646 #endif 3647 printf("sqh:\n"); 3648 ehci_dump_sqh(sqh); 3649 ehci_dump_sqtds(data); 3650 } 3651 #endif 3652 3653 if (sc->sc_bus.use_polling) 3654 ehci_waitintr(sc, xfer); 3655 3656 return (USBD_IN_PROGRESS); 3657 #undef exfer 3658 } 3659 3660 Static void 3661 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3662 { 3663 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3664 ehci_abort_xfer(xfer, USBD_CANCELLED); 3665 } 3666 3667 /* 3668 * Close a device bulk pipe. 3669 */ 3670 Static void 3671 ehci_device_bulk_close(usbd_pipe_handle pipe) 3672 { 3673 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3674 3675 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3676 ehci_close_pipe(pipe, sc->sc_async_head); 3677 } 3678 3679 void 3680 ehci_device_bulk_done(usbd_xfer_handle xfer) 3681 { 3682 struct ehci_xfer *ex = EXFER(xfer); 3683 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3684 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3685 3686 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3687 xfer, xfer->actlen)); 3688 3689 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3690 ehci_del_intr_list(ex); /* remove from active list */ 3691 ehci_free_sqtd_chain(sc, epipe->sqh, ex->sqtdstart, 3692 ex->sqtdend->nextqtd); 3693 } 3694 3695 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3696 } 3697 3698 /************************/ 3699 3700 Static usbd_status 3701 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3702 { 3703 struct ehci_soft_islot *isp; 3704 int islot, lev; 3705 3706 /* Find a poll rate that is large enough. */ 3707 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3708 if (EHCI_ILEV_IVAL(lev) <= ival) 3709 break; 3710 3711 /* Pick an interrupt slot at the right level. */ 3712 /* XXX could do better than picking at random. */ 3713 islot = EHCI_IQHIDX(lev, arc4random()); 3714 3715 sqh->islot = islot; 3716 isp = &sc->sc_islots[islot]; 3717 ehci_add_qh(sc, sqh, isp->sqh); 3718 3719 return (USBD_NORMAL_COMPLETION); 3720 } 3721 3722 Static usbd_status 3723 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3724 { 3725 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3726 usbd_status err; 3727 3728 /* Insert last in queue. */ 3729 err = usb_insert_transfer_dma(xfer, &sc->sc_dmatag, 3730 &EXFER(xfer)->dmabuf); 3731 if (err) 3732 return (err); 3733 3734 /* 3735 * Pipe isn't running (otherwise err would be USBD_INPROG), 3736 * so start it first. 3737 */ 3738 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3739 } 3740 3741 Static usbd_status 3742 ehci_device_intr_start(usbd_xfer_handle xfer) 3743 { 3744 #define exfer EXFER(xfer) 3745 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3746 usbd_device_handle dev = xfer->pipe->device; 3747 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 3748 ehci_soft_qtd_t *data, *dataend, *newinactive; 3749 ehci_soft_qh_t *sqh; 3750 usbd_status err; 3751 int len, isread, endpt; 3752 int s; 3753 3754 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3755 xfer, xfer->length, xfer->flags)); 3756 3757 if (sc->sc_dying) 3758 return (USBD_IOERROR); 3759 3760 #ifdef DIAGNOSTIC 3761 if (xfer->rqflags & URQ_REQUEST) 3762 panic("ehci_device_intr_start: a request"); 3763 #endif 3764 3765 len = xfer->length; 3766 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3767 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3768 sqh = epipe->sqh; 3769 3770 epipe->u.intr.length = len; 3771 3772 newinactive = ehci_alloc_sqtd(sc); 3773 if (newinactive == NULL) { 3774 DPRINTFN(-1,("ehci_device_intr_start: no sqtd memory\n")); 3775 err = USBD_NOMEM; 3776 xfer->status = err; 3777 usb_transfer_complete(xfer); 3778 return (err); 3779 } 3780 newinactive->qtd.qtd_status = htole32(0); 3781 newinactive->qtd.qtd_next = EHCI_NULL; 3782 newinactive->qtd.qtd_altnext = EHCI_NULL; 3783 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3784 sqh->inactivesqtd, newinactive, &data, &dataend); 3785 if (err) { 3786 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3787 xfer->status = err; 3788 usb_transfer_complete(xfer); 3789 return (err); 3790 } 3791 dataend->nextqtd = newinactive; 3792 dataend->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3793 dataend->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3794 sqh->inactivesqtd = newinactive; 3795 EHCI_SQTD_SYNC(sc, newinactive, 3796 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3797 EHCI_SQTD_SYNC(sc, dataend, 3798 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3799 3800 #ifdef EHCI_DEBUG 3801 if (ehcidebug > 5) { 3802 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3803 ehci_dump_sqh(sqh); 3804 ehci_dump_sqtds(data); 3805 } 3806 #endif 3807 3808 /* Set up interrupt info. */ 3809 exfer->sqtdstart = data; 3810 exfer->sqtdend = dataend; 3811 #ifdef DIAGNOSTIC 3812 if (!exfer->isdone) { 3813 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3814 } 3815 exfer->isdone = 0; 3816 #endif 3817 3818 s = splusb(); 3819 ehci_activate_qh(sc, sqh, data); 3820 if (xfer->timeout && !sc->sc_bus.use_polling) { 3821 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 3822 ehci_timeout, xfer); 3823 } 3824 ehci_add_intr_list(sc, exfer); 3825 xfer->status = USBD_IN_PROGRESS; 3826 splx(s); 3827 3828 #ifdef EHCI_DEBUG 3829 if (ehcidebug > 10) { 3830 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3831 delay(10000); 3832 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3833 ehci_dump_regs(sc); 3834 printf("sqh:\n"); 3835 ehci_dump_sqh(sqh); 3836 ehci_dump_sqtds(data); 3837 } 3838 #endif 3839 3840 if (sc->sc_bus.use_polling) 3841 ehci_waitintr(sc, xfer); 3842 3843 return (USBD_IN_PROGRESS); 3844 #undef exfer 3845 } 3846 3847 Static void 3848 ehci_device_intr_abort(usbd_xfer_handle xfer) 3849 { 3850 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3851 if (xfer->pipe->intrxfer == xfer) { 3852 DPRINTFN(1, ("ehci_device_intr_abort: remove\n")); 3853 xfer->pipe->intrxfer = NULL; 3854 } 3855 ehci_abort_xfer(xfer, USBD_CANCELLED); 3856 } 3857 3858 Static void 3859 ehci_device_intr_close(usbd_pipe_handle pipe) 3860 { 3861 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 3862 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3863 struct ehci_soft_islot *isp; 3864 3865 isp = &sc->sc_islots[epipe->sqh->islot]; 3866 ehci_close_pipe(pipe, isp->sqh); 3867 } 3868 3869 Static void 3870 ehci_device_intr_done(usbd_xfer_handle xfer) 3871 { 3872 #define exfer EXFER(xfer) 3873 struct ehci_xfer *ex = EXFER(xfer); 3874 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 3875 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3876 ehci_soft_qtd_t *data, *dataend, *newinactive; 3877 ehci_soft_qh_t *sqh; 3878 usbd_status err; 3879 int len, isread, endpt, s; 3880 3881 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3882 xfer, xfer->actlen)); 3883 3884 sqh = epipe->sqh; 3885 if (xfer->pipe->repeat) { 3886 ehci_free_sqtd_chain(sc, sqh, ex->sqtdstart, 3887 ex->sqtdend->nextqtd); 3888 3889 len = epipe->u.intr.length; 3890 xfer->length = len; 3891 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3892 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3893 3894 newinactive = ehci_alloc_sqtd(sc); 3895 if (newinactive == NULL) { 3896 DPRINTFN(-1, 3897 ("ehci_device_intr_done: no sqtd memory\n")); 3898 err = USBD_NOMEM; 3899 xfer->status = err; 3900 return; 3901 } 3902 newinactive->qtd.qtd_status = htole32(0); 3903 newinactive->qtd.qtd_next = EHCI_NULL; 3904 newinactive->qtd.qtd_altnext = EHCI_NULL; 3905 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3906 sqh->inactivesqtd, newinactive, &data, &dataend); 3907 if (err) { 3908 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3909 xfer->status = err; 3910 return; 3911 } 3912 dataend->nextqtd = newinactive; 3913 dataend->qtd.qtd_next = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3914 dataend->qtd.qtd_altnext = htole32(EHCI_SQTD_DMAADDR(newinactive)); 3915 sqh->inactivesqtd = newinactive; 3916 EHCI_SQTD_SYNC(sc, newinactive, 3917 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3918 EHCI_SQTD_SYNC(sc, dataend, 3919 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3920 3921 /* Set up interrupt info. */ 3922 exfer->sqtdstart = data; 3923 exfer->sqtdend = dataend; 3924 #ifdef DIAGNOSTIC 3925 if (!exfer->isdone) { 3926 printf("ehci_device_intr_done: not done, ex=%p\n", 3927 exfer); 3928 } 3929 exfer->isdone = 0; 3930 #endif 3931 3932 s = splusb(); 3933 ehci_activate_qh(sc, sqh, data); 3934 if (xfer->timeout && !sc->sc_bus.use_polling) { 3935 usb_callout(xfer->timeout_handle, 3936 MS_TO_TICKS(xfer->timeout), ehci_timeout, xfer); 3937 } 3938 splx(s); 3939 3940 xfer->status = USBD_IN_PROGRESS; 3941 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3942 ehci_del_intr_list(ex); /* remove from active list */ 3943 ehci_free_sqtd_chain(sc, sqh, ex->sqtdstart, 3944 ex->sqtdend->nextqtd); 3945 } 3946 #undef exfer 3947 } 3948 3949 /************************/ 3950 3951 Static usbd_status 3952 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3953 { 3954 return USBD_IOERROR; 3955 } 3956 Static usbd_status 3957 ehci_device_isoc_start(usbd_xfer_handle xfer) 3958 { 3959 return USBD_IOERROR; 3960 } 3961 Static void 3962 ehci_device_isoc_abort(usbd_xfer_handle xfer) 3963 { 3964 } 3965 Static void 3966 ehci_device_isoc_close(usbd_pipe_handle pipe) 3967 { 3968 } 3969 Static void 3970 ehci_device_isoc_done(usbd_xfer_handle xfer) 3971 { 3972 } 3973
Indexes created Thu Oct 02 01:09:59 GMT 2025