ehci.c revision 1.138.2.1
1 /* $NetBSD: ehci.c,v 1.138.2.1 2008/10/19 22:17:09 haad Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum and 9 * Jeremy Morse (jeremy.morse (at) gmail.com). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 35 * 36 * The EHCI 1.0 spec can be found at 37 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/usb_20.zip 40 * 41 */ 42 43 /* 44 * TODO: 45 * 1) hold off explorations by companion controllers until ehci has started. 46 * 47 * 2) The hub driver needs to handle and schedule the transaction translator, 48 * to assign place in frame where different devices get to go. See chapter 49 * on hubs in USB 2.0 for details. 50 * 51 * 3) command failures are not recovered correctly 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.138.2.1 2008/10/19 22:17:09 haad Exp $"); 56 57 #include "ohci.h" 58 #include "uhci.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/kernel.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/select.h> 66 #include <sys/proc.h> 67 #include <sys/queue.h> 68 #include <sys/mutex.h> 69 #include <sys/bus.h> 70 71 #include <machine/endian.h> 72 73 #include <dev/usb/usb.h> 74 #include <dev/usb/usbdi.h> 75 #include <dev/usb/usbdivar.h> 76 #include <dev/usb/usb_mem.h> 77 #include <dev/usb/usb_quirks.h> 78 79 #include <dev/usb/ehcireg.h> 80 #include <dev/usb/ehcivar.h> 81 #include <dev/usb/usbroothub_subr.h> 82 83 #ifdef EHCI_DEBUG 84 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 85 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 86 int ehcidebug = 0; 87 #ifndef __NetBSD__ 88 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 89 #endif 90 #else 91 #define DPRINTF(x) 92 #define DPRINTFN(n,x) 93 #endif 94 95 struct ehci_pipe { 96 struct usbd_pipe pipe; 97 int nexttoggle; 98 99 ehci_soft_qh_t *sqh; 100 union { 101 ehci_soft_qtd_t *qtd; 102 /* ehci_soft_itd_t *itd; */ 103 } tail; 104 union { 105 /* Control pipe */ 106 struct { 107 usb_dma_t reqdma; 108 u_int length; 109 } ctl; 110 /* Interrupt pipe */ 111 struct { 112 u_int length; 113 } intr; 114 /* Bulk pipe */ 115 struct { 116 u_int length; 117 } bulk; 118 /* Iso pipe */ 119 struct { 120 u_int next_frame; 121 u_int cur_xfers; 122 } isoc; 123 } u; 124 }; 125 126 Static usbd_status ehci_open(usbd_pipe_handle); 127 Static void ehci_poll(struct usbd_bus *); 128 Static void ehci_softintr(void *); 129 Static int ehci_intr1(ehci_softc_t *); 130 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 131 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 132 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 133 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 134 Static void ehci_idone(struct ehci_xfer *); 135 Static void ehci_timeout(void *); 136 Static void ehci_timeout_task(void *); 137 Static void ehci_intrlist_timeout(void *); 138 139 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 140 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 141 142 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 143 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 144 145 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 146 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 147 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 148 Static void ehci_root_ctrl_close(usbd_pipe_handle); 149 Static void ehci_root_ctrl_done(usbd_xfer_handle); 150 151 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 152 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 153 Static void ehci_root_intr_abort(usbd_xfer_handle); 154 Static void ehci_root_intr_close(usbd_pipe_handle); 155 Static void ehci_root_intr_done(usbd_xfer_handle); 156 157 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 158 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 159 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 160 Static void ehci_device_ctrl_close(usbd_pipe_handle); 161 Static void ehci_device_ctrl_done(usbd_xfer_handle); 162 163 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 164 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 165 Static void ehci_device_bulk_abort(usbd_xfer_handle); 166 Static void ehci_device_bulk_close(usbd_pipe_handle); 167 Static void ehci_device_bulk_done(usbd_xfer_handle); 168 169 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 170 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 171 Static void ehci_device_intr_abort(usbd_xfer_handle); 172 Static void ehci_device_intr_close(usbd_pipe_handle); 173 Static void ehci_device_intr_done(usbd_xfer_handle); 174 175 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 176 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 177 Static void ehci_device_isoc_abort(usbd_xfer_handle); 178 Static void ehci_device_isoc_close(usbd_pipe_handle); 179 Static void ehci_device_isoc_done(usbd_xfer_handle); 180 181 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 182 Static void ehci_noop(usbd_pipe_handle pipe); 183 184 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 185 Static void ehci_disown(ehci_softc_t *, int, int); 186 187 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 188 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 189 190 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 191 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 192 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 193 ehci_softc_t *, int, int, usbd_xfer_handle, 194 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 195 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 196 ehci_soft_qtd_t *); 197 198 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 199 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 200 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 201 struct ehci_xfer *exfer); 202 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 203 usbd_status status); 204 205 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 206 207 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 208 int ival); 209 210 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 211 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 212 ehci_soft_qh_t *); 213 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 214 Static void ehci_sync_hc(ehci_softc_t *); 215 216 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 217 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 218 219 #ifdef EHCI_DEBUG 220 Static void ehci_dump_regs(ehci_softc_t *); 221 void ehci_dump(void); 222 Static ehci_softc_t *theehci; 223 Static void ehci_dump_link(ehci_link_t, int); 224 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 225 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 226 Static void ehci_dump_qtd(ehci_qtd_t *); 227 Static void ehci_dump_sqh(ehci_soft_qh_t *); 228 #if notyet 229 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 230 Static void ehci_dump_itd(struct ehci_soft_itd *); 231 #endif 232 #ifdef DIAGNOSTIC 233 Static void ehci_dump_exfer(struct ehci_xfer *); 234 #endif 235 #endif 236 237 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 238 239 #define EHCI_INTR_ENDPT 1 240 241 #define ehci_add_intr_list(sc, ex) \ 242 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 243 #define ehci_del_intr_list(sc, ex) \ 244 do { \ 245 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 246 (ex)->inext.tqe_prev = NULL; \ 247 } while (0) 248 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 249 250 Static const struct usbd_bus_methods ehci_bus_methods = { 251 ehci_open, 252 ehci_softintr, 253 ehci_poll, 254 ehci_allocm, 255 ehci_freem, 256 ehci_allocx, 257 ehci_freex, 258 }; 259 260 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 261 ehci_root_ctrl_transfer, 262 ehci_root_ctrl_start, 263 ehci_root_ctrl_abort, 264 ehci_root_ctrl_close, 265 ehci_noop, 266 ehci_root_ctrl_done, 267 }; 268 269 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 270 ehci_root_intr_transfer, 271 ehci_root_intr_start, 272 ehci_root_intr_abort, 273 ehci_root_intr_close, 274 ehci_noop, 275 ehci_root_intr_done, 276 }; 277 278 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 279 ehci_device_ctrl_transfer, 280 ehci_device_ctrl_start, 281 ehci_device_ctrl_abort, 282 ehci_device_ctrl_close, 283 ehci_noop, 284 ehci_device_ctrl_done, 285 }; 286 287 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 288 ehci_device_intr_transfer, 289 ehci_device_intr_start, 290 ehci_device_intr_abort, 291 ehci_device_intr_close, 292 ehci_device_clear_toggle, 293 ehci_device_intr_done, 294 }; 295 296 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 297 ehci_device_bulk_transfer, 298 ehci_device_bulk_start, 299 ehci_device_bulk_abort, 300 ehci_device_bulk_close, 301 ehci_device_clear_toggle, 302 ehci_device_bulk_done, 303 }; 304 305 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 306 ehci_device_isoc_transfer, 307 ehci_device_isoc_start, 308 ehci_device_isoc_abort, 309 ehci_device_isoc_close, 310 ehci_noop, 311 ehci_device_isoc_done, 312 }; 313 314 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 315 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 316 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 317 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 318 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 319 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 320 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 321 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 322 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 323 }; 324 325 usbd_status 326 ehci_init(ehci_softc_t *sc) 327 { 328 u_int32_t vers, sparams, cparams, hcr; 329 u_int i; 330 usbd_status err; 331 ehci_soft_qh_t *sqh; 332 u_int ncomp; 333 334 DPRINTF(("ehci_init: start\n")); 335 #ifdef EHCI_DEBUG 336 theehci = sc; 337 #endif 338 339 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 340 341 vers = EREAD2(sc, EHCI_HCIVERSION); 342 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 343 vers >> 8, vers & 0xff); 344 345 sparams = EREAD4(sc, EHCI_HCSPARAMS); 346 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 347 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 348 ncomp = EHCI_HCS_N_CC(sparams); 349 if (ncomp != sc->sc_ncomp) { 350 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 351 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 352 #if NOHCI == 0 || NUHCI == 0 353 aprint_error("%s: ohci or uhci probably not configured\n", 354 device_xname(sc->sc_dev)); 355 #endif 356 if (ncomp < sc->sc_ncomp) 357 sc->sc_ncomp = ncomp; 358 } 359 if (sc->sc_ncomp > 0) { 360 aprint_normal("%s: companion controller%s, %d port%s each:", 361 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 362 EHCI_HCS_N_PCC(sparams), 363 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 364 for (i = 0; i < sc->sc_ncomp; i++) 365 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 366 aprint_normal("\n"); 367 } 368 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 369 cparams = EREAD4(sc, EHCI_HCCPARAMS); 370 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 371 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 372 373 if (EHCI_HCC_64BIT(cparams)) { 374 /* MUST clear segment register if 64 bit capable. */ 375 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 376 } 377 378 sc->sc_bus.usbrev = USBREV_2_0; 379 380 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 381 USB_MEM_RESERVE); 382 383 /* Reset the controller */ 384 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 385 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 386 usb_delay_ms(&sc->sc_bus, 1); 387 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 388 for (i = 0; i < 100; i++) { 389 usb_delay_ms(&sc->sc_bus, 1); 390 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 391 if (!hcr) 392 break; 393 } 394 if (hcr) { 395 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 396 return (USBD_IOERROR); 397 } 398 399 /* XXX need proper intr scheduling */ 400 sc->sc_rand = 96; 401 402 /* frame list size at default, read back what we got and use that */ 403 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 404 case 0: sc->sc_flsize = 1024; break; 405 case 1: sc->sc_flsize = 512; break; 406 case 2: sc->sc_flsize = 256; break; 407 case 3: return (USBD_IOERROR); 408 } 409 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 410 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 411 if (err) 412 return (err); 413 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 414 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 415 416 for (i = 0; i < sc->sc_flsize; i++) { 417 sc->sc_flist[i] = EHCI_NULL; 418 } 419 420 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 421 422 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 423 M_USB, M_NOWAIT | M_ZERO); 424 if (sc->sc_softitds == NULL) 425 return ENOMEM; 426 LIST_INIT(&sc->sc_freeitds); 427 TAILQ_INIT(&sc->sc_intrhead); 428 mutex_init(&sc->sc_intrhead_lock, MUTEX_DEFAULT, IPL_USB); 429 430 /* Set up the bus struct. */ 431 sc->sc_bus.methods = &ehci_bus_methods; 432 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 433 434 sc->sc_eintrs = EHCI_NORMAL_INTRS; 435 436 /* 437 * Allocate the interrupt dummy QHs. These are arranged to give poll 438 * intervals that are powers of 2 times 1ms. 439 */ 440 for (i = 0; i < EHCI_INTRQHS; i++) { 441 sqh = ehci_alloc_sqh(sc); 442 if (sqh == NULL) { 443 err = USBD_NOMEM; 444 goto bad1; 445 } 446 sc->sc_islots[i].sqh = sqh; 447 } 448 for (i = 0; i < EHCI_INTRQHS; i++) { 449 sqh = sc->sc_islots[i].sqh; 450 if (i == 0) { 451 /* The last (1ms) QH terminates. */ 452 sqh->qh.qh_link = EHCI_NULL; 453 sqh->next = NULL; 454 } else { 455 /* Otherwise the next QH has half the poll interval */ 456 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 457 sqh->qh.qh_link = htole32(sqh->next->physaddr | 458 EHCI_LINK_QH); 459 } 460 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 461 sqh->qh.qh_curqtd = EHCI_NULL; 462 sqh->next = NULL; 463 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 464 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 465 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 466 sqh->sqtd = NULL; 467 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 468 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 469 } 470 /* Point the frame list at the last level (128ms). */ 471 for (i = 0; i < sc->sc_flsize; i++) { 472 int j; 473 474 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 475 revbits[i & (EHCI_MAX_POLLRATE-1)]; 476 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 477 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 478 i)].sqh->physaddr); 479 } 480 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 481 BUS_DMASYNC_PREWRITE); 482 483 /* Allocate dummy QH that starts the async list. */ 484 sqh = ehci_alloc_sqh(sc); 485 if (sqh == NULL) { 486 err = USBD_NOMEM; 487 goto bad1; 488 } 489 /* Fill the QH */ 490 sqh->qh.qh_endp = 491 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 492 sqh->qh.qh_link = 493 htole32(sqh->physaddr | EHCI_LINK_QH); 494 sqh->qh.qh_curqtd = EHCI_NULL; 495 sqh->next = NULL; 496 /* Fill the overlay qTD */ 497 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 498 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 499 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 500 sqh->sqtd = NULL; 501 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 502 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 503 #ifdef EHCI_DEBUG 504 if (ehcidebug) { 505 ehci_dump_sqh(sqh); 506 } 507 #endif 508 509 /* Point to async list */ 510 sc->sc_async_head = sqh; 511 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 512 513 usb_callout_init(sc->sc_tmo_intrlist); 514 515 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE); 516 517 /* Turn on controller */ 518 EOWRITE4(sc, EHCI_USBCMD, 519 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 520 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 521 EHCI_CMD_ASE | 522 EHCI_CMD_PSE | 523 EHCI_CMD_RS); 524 525 /* Take over port ownership */ 526 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 527 528 for (i = 0; i < 100; i++) { 529 usb_delay_ms(&sc->sc_bus, 1); 530 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 531 if (!hcr) 532 break; 533 } 534 if (hcr) { 535 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 536 return (USBD_IOERROR); 537 } 538 539 /* Enable interrupts */ 540 DPRINTFN(1,("ehci_init: enabling\n")); 541 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 542 543 return (USBD_NORMAL_COMPLETION); 544 545 #if 0 546 bad2: 547 ehci_free_sqh(sc, sc->sc_async_head); 548 #endif 549 bad1: 550 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 551 return (err); 552 } 553 554 int 555 ehci_intr(void *v) 556 { 557 ehci_softc_t *sc = v; 558 559 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 560 return (0); 561 562 /* If we get an interrupt while polling, then just ignore it. */ 563 if (sc->sc_bus.use_polling) { 564 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 565 566 if (intrs) 567 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 568 #ifdef DIAGNOSTIC 569 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 570 #endif 571 return (0); 572 } 573 574 return (ehci_intr1(sc)); 575 } 576 577 Static int 578 ehci_intr1(ehci_softc_t *sc) 579 { 580 u_int32_t intrs, eintrs; 581 582 DPRINTFN(20,("ehci_intr1: enter\n")); 583 584 /* In case the interrupt occurs before initialization has completed. */ 585 if (sc == NULL) { 586 #ifdef DIAGNOSTIC 587 printf("ehci_intr1: sc == NULL\n"); 588 #endif 589 return (0); 590 } 591 592 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 593 if (!intrs) 594 return (0); 595 596 eintrs = intrs & sc->sc_eintrs; 597 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 598 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 599 (u_int)eintrs)); 600 if (!eintrs) 601 return (0); 602 603 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 604 sc->sc_bus.intr_context++; 605 sc->sc_bus.no_intrs++; 606 if (eintrs & EHCI_STS_IAA) { 607 DPRINTF(("ehci_intr1: door bell\n")); 608 wakeup(&sc->sc_async_head); 609 eintrs &= ~EHCI_STS_IAA; 610 } 611 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 612 DPRINTFN(5,("ehci_intr1: %s %s\n", 613 eintrs & EHCI_STS_INT ? "INT" : "", 614 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 615 usb_schedsoftintr(&sc->sc_bus); 616 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 617 } 618 if (eintrs & EHCI_STS_HSE) { 619 printf("%s: unrecoverable error, controller halted\n", 620 device_xname(sc->sc_dev)); 621 /* XXX what else */ 622 } 623 if (eintrs & EHCI_STS_PCD) { 624 ehci_pcd(sc, sc->sc_intrxfer); 625 eintrs &= ~EHCI_STS_PCD; 626 } 627 628 sc->sc_bus.intr_context--; 629 630 if (eintrs != 0) { 631 /* Block unprocessed interrupts. */ 632 sc->sc_eintrs &= ~eintrs; 633 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 634 printf("%s: blocking intrs 0x%x\n", 635 device_xname(sc->sc_dev), eintrs); 636 } 637 638 return (1); 639 } 640 641 642 void 643 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 644 { 645 usbd_pipe_handle pipe; 646 u_char *p; 647 int i, m; 648 649 if (xfer == NULL) { 650 /* Just ignore the change. */ 651 return; 652 } 653 654 pipe = xfer->pipe; 655 656 p = KERNADDR(&xfer->dmabuf, 0); 657 m = min(sc->sc_noport, xfer->length * 8 - 1); 658 memset(p, 0, xfer->length); 659 for (i = 1; i <= m; i++) { 660 /* Pick out CHANGE bits from the status reg. */ 661 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 662 p[i/8] |= 1 << (i%8); 663 } 664 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 665 xfer->actlen = xfer->length; 666 xfer->status = USBD_NORMAL_COMPLETION; 667 668 usb_transfer_complete(xfer); 669 } 670 671 void 672 ehci_softintr(void *v) 673 { 674 struct usbd_bus *bus = v; 675 ehci_softc_t *sc = bus->hci_private; 676 struct ehci_xfer *ex, *nextex; 677 678 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 679 sc->sc_bus.intr_context)); 680 681 sc->sc_bus.intr_context++; 682 683 /* 684 * The only explanation I can think of for why EHCI is as brain dead 685 * as UHCI interrupt-wise is that Intel was involved in both. 686 * An interrupt just tells us that something is done, we have no 687 * clue what, so we need to scan through all active transfers. :-( 688 */ 689 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 690 nextex = TAILQ_NEXT(ex, inext); 691 ehci_check_intr(sc, ex); 692 } 693 694 /* Schedule a callout to catch any dropped transactions. */ 695 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 696 !TAILQ_EMPTY(&sc->sc_intrhead)) 697 usb_callout(sc->sc_tmo_intrlist, hz, 698 ehci_intrlist_timeout, sc); 699 700 #ifdef USB_USE_SOFTINTR 701 if (sc->sc_softwake) { 702 sc->sc_softwake = 0; 703 wakeup(&sc->sc_softwake); 704 } 705 #endif /* USB_USE_SOFTINTR */ 706 707 sc->sc_bus.intr_context--; 708 } 709 710 /* Check for an interrupt. */ 711 void 712 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 713 { 714 int attr; 715 716 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 717 718 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 719 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 720 ehci_check_itd_intr(sc, ex); 721 else 722 ehci_check_qh_intr(sc, ex); 723 724 return; 725 } 726 727 void 728 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 729 { 730 ehci_soft_qtd_t *sqtd, *lsqtd; 731 __uint32_t status; 732 733 if (ex->sqtdstart == NULL) { 734 printf("ehci_check_qh_intr: not valid sqtd\n"); 735 return; 736 } 737 738 lsqtd = ex->sqtdend; 739 #ifdef DIAGNOSTIC 740 if (lsqtd == NULL) { 741 printf("ehci_check_qh_intr: lsqtd==0\n"); 742 return; 743 } 744 #endif 745 /* 746 * If the last TD is still active we need to check whether there 747 * is a an error somewhere in the middle, or whether there was a 748 * short packet (SPD and not ACTIVE). 749 */ 750 usb_syncmem(&lsqtd->dma, 751 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 752 sizeof(lsqtd->qtd.qtd_status), 753 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 754 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 755 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 756 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 757 usb_syncmem(&sqtd->dma, 758 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 759 sizeof(sqtd->qtd.qtd_status), 760 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 761 status = le32toh(sqtd->qtd.qtd_status); 762 usb_syncmem(&sqtd->dma, 763 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 764 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 765 /* If there's an active QTD the xfer isn't done. */ 766 if (status & EHCI_QTD_ACTIVE) 767 break; 768 /* Any kind of error makes the xfer done. */ 769 if (status & EHCI_QTD_HALTED) 770 goto done; 771 /* We want short packets, and it is short: it's done */ 772 if (EHCI_QTD_GET_BYTES(status) != 0) 773 goto done; 774 } 775 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 776 ex, ex->sqtdstart)); 777 usb_syncmem(&lsqtd->dma, 778 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 779 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 780 return; 781 } 782 done: 783 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 784 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 785 ehci_idone(ex); 786 } 787 788 void 789 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 790 ehci_soft_itd_t *itd; 791 int i; 792 793 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 794 return; 795 796 if (ex->itdstart == NULL) { 797 printf("ehci_check_itd_intr: not valid itd\n"); 798 return; 799 } 800 801 itd = ex->itdend; 802 #ifdef DIAGNOSTIC 803 if (itd == NULL) { 804 printf("ehci_check_itd_intr: itdend == 0\n"); 805 return; 806 } 807 #endif 808 809 /* 810 * check no active transfers in last itd, meaning we're finished 811 */ 812 813 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 814 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 815 BUS_DMASYNC_POSTREAD); 816 817 for (i = 0; i < 8; i++) { 818 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 819 break; 820 } 821 822 if (i == 8) { 823 goto done; /* All 8 descriptors inactive, it's done */ 824 } 825 826 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 827 ex->itdstart)); 828 return; 829 done: 830 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 831 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 832 ehci_idone(ex); 833 } 834 835 void 836 ehci_idone(struct ehci_xfer *ex) 837 { 838 usbd_xfer_handle xfer = &ex->xfer; 839 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 840 ehci_soft_qtd_t *sqtd, *lsqtd; 841 u_int32_t status = 0, nstatus = 0; 842 int actlen; 843 844 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 845 #ifdef DIAGNOSTIC 846 { 847 int s = splhigh(); 848 if (ex->isdone) { 849 splx(s); 850 #ifdef EHCI_DEBUG 851 printf("ehci_idone: ex is done!\n "); 852 ehci_dump_exfer(ex); 853 #else 854 printf("ehci_idone: ex=%p is done!\n", ex); 855 #endif 856 return; 857 } 858 ex->isdone = 1; 859 splx(s); 860 } 861 #endif 862 if (xfer->status == USBD_CANCELLED || 863 xfer->status == USBD_TIMEOUT) { 864 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 865 return; 866 } 867 868 #ifdef EHCI_DEBUG 869 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 870 if (ehcidebug > 10) 871 ehci_dump_sqtds(ex->sqtdstart); 872 #endif 873 874 /* The transfer is done, compute actual length and status. */ 875 876 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 877 == UE_ISOCHRONOUS) { 878 /* Isoc transfer */ 879 struct ehci_soft_itd *itd; 880 int i, nframes, len, uframes; 881 882 nframes = 0; 883 actlen = 0; 884 885 switch (xfer->pipe->endpoint->edesc->bInterval) { 886 case 0: 887 panic("ehci: isoc xfer suddenly has 0 bInterval, invalid\n"); 888 case 1: uframes = 1; break; 889 case 2: uframes = 2; break; 890 case 3: uframes = 4; break; 891 default: uframes = 8; break; 892 } 893 894 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 895 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 896 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 897 BUS_DMASYNC_POSTREAD); 898 899 for (i = 0; i < 8; i += uframes) { 900 /* XXX - driver didn't fill in the frame full 901 * of uframes. This leads to scheduling 902 * inefficiencies, but working around 903 * this doubles complexity of tracking 904 * an xfer. 905 */ 906 if (nframes >= xfer->nframes) 907 break; 908 909 status = le32toh(itd->itd.itd_ctl[i]); 910 len = EHCI_ITD_GET_LEN(status); 911 xfer->frlengths[nframes++] = len; 912 actlen += len; 913 } 914 915 if (nframes >= xfer->nframes) 916 break; 917 } 918 919 xfer->actlen = actlen; 920 xfer->status = USBD_NORMAL_COMPLETION; 921 if (xfer->rqflags & URQ_DEV_DMABUF) { 922 usb_syncmem(&xfer->dmabuf, 0, ex->isoc_len, 923 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 924 } 925 926 goto end; 927 } 928 929 /* Continue processing xfers using queue heads */ 930 931 lsqtd = ex->sqtdend; 932 actlen = 0; 933 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 934 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 935 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 936 nstatus = le32toh(sqtd->qtd.qtd_status); 937 if (nstatus & EHCI_QTD_ACTIVE) 938 break; 939 940 status = nstatus; 941 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 942 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 943 } 944 945 946 /* 947 * If there are left over TDs we need to update the toggle. 948 * The default pipe doesn't need it since control transfers 949 * start the toggle at 0 every time. 950 * For a short transfer we need to update the toggle for the missing 951 * packets within the qTD. 952 */ 953 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 954 xfer->pipe->device->default_pipe != xfer->pipe) { 955 DPRINTFN(2, ("ehci_idone: need toggle update " 956 "status=%08x nstatus=%08x\n", status, nstatus)); 957 #if 0 958 ehci_dump_sqh(epipe->sqh); 959 ehci_dump_sqtds(ex->sqtdstart); 960 #endif 961 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 962 } 963 964 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 965 xfer->length, actlen, status)); 966 xfer->actlen = actlen; 967 if (status & EHCI_QTD_HALTED) { 968 #ifdef EHCI_DEBUG 969 char sbuf[128]; 970 971 bitmask_snprintf((u_int32_t)status, 972 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 973 "\3MISSED\1PINGSTATE", sbuf, sizeof(sbuf)); 974 975 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 976 "status 0x%s\n", 977 xfer->pipe->device->address, 978 xfer->pipe->endpoint->edesc->bEndpointAddress, 979 sbuf)); 980 if (ehcidebug > 2) { 981 ehci_dump_sqh(epipe->sqh); 982 ehci_dump_sqtds(ex->sqtdstart); 983 } 984 #endif 985 /* low&full speed has an extra error flag */ 986 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 987 EHCI_QH_SPEED_HIGH) 988 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 989 else 990 status &= EHCI_QTD_STATERRS; 991 if (status == 0) /* no other errors means a stall */ { 992 xfer->status = USBD_STALLED; 993 } else { 994 xfer->status = USBD_IOERROR; /* more info XXX */ 995 } 996 /* XXX need to reset TT on missed microframe */ 997 if (status & EHCI_QTD_MISSEDMICRO) { 998 ehci_softc_t *sc = 999 xfer->pipe->device->bus->hci_private; 1000 1001 printf("%s: missed microframe, TT reset not " 1002 "implemented, hub might be inoperational\n", 1003 device_xname(sc->sc_dev)); 1004 } 1005 } else { 1006 xfer->status = USBD_NORMAL_COMPLETION; 1007 } 1008 1009 end: 1010 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1011 * during this call, before methods->done is called: dma sync required 1012 * beforehand? */ 1013 usb_transfer_complete(xfer); 1014 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1015 } 1016 1017 /* 1018 * Wait here until controller claims to have an interrupt. 1019 * Then call ehci_intr and return. Use timeout to avoid waiting 1020 * too long. 1021 */ 1022 void 1023 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1024 { 1025 int timo; 1026 u_int32_t intrs; 1027 1028 xfer->status = USBD_IN_PROGRESS; 1029 for (timo = xfer->timeout; timo >= 0; timo--) { 1030 usb_delay_ms(&sc->sc_bus, 1); 1031 if (sc->sc_dying) 1032 break; 1033 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1034 sc->sc_eintrs; 1035 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1036 #ifdef EHCI_DEBUG 1037 if (ehcidebug > 15) 1038 ehci_dump_regs(sc); 1039 #endif 1040 if (intrs) { 1041 ehci_intr1(sc); 1042 if (xfer->status != USBD_IN_PROGRESS) 1043 return; 1044 } 1045 } 1046 1047 /* Timeout */ 1048 DPRINTF(("ehci_waitintr: timeout\n")); 1049 xfer->status = USBD_TIMEOUT; 1050 usb_transfer_complete(xfer); 1051 /* XXX should free TD */ 1052 } 1053 1054 void 1055 ehci_poll(struct usbd_bus *bus) 1056 { 1057 ehci_softc_t *sc = bus->hci_private; 1058 #ifdef EHCI_DEBUG 1059 static int last; 1060 int new; 1061 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1062 if (new != last) { 1063 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1064 last = new; 1065 } 1066 #endif 1067 1068 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1069 ehci_intr1(sc); 1070 } 1071 1072 void 1073 ehci_childdet(device_t self, device_t child) 1074 { 1075 struct ehci_softc *sc = device_private(self); 1076 1077 KASSERT(sc->sc_child == child); 1078 sc->sc_child = NULL; 1079 } 1080 1081 int 1082 ehci_detach(struct ehci_softc *sc, int flags) 1083 { 1084 int rv = 0; 1085 1086 if (sc->sc_child != NULL) 1087 rv = config_detach(sc->sc_child, flags); 1088 1089 if (rv != 0) 1090 return (rv); 1091 1092 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 1093 1094 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1095 1096 /* XXX free other data structures XXX */ 1097 mutex_destroy(&sc->sc_doorbell_lock); 1098 mutex_destroy(&sc->sc_intrhead_lock); 1099 1100 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1101 1102 return (rv); 1103 } 1104 1105 1106 int 1107 ehci_activate(device_t self, enum devact act) 1108 { 1109 struct ehci_softc *sc = device_private(self); 1110 int rv = 0; 1111 1112 switch (act) { 1113 case DVACT_ACTIVATE: 1114 return (EOPNOTSUPP); 1115 1116 case DVACT_DEACTIVATE: 1117 sc->sc_dying = 1; 1118 if (sc->sc_child != NULL) 1119 rv = config_deactivate(sc->sc_child); 1120 break; 1121 } 1122 return (rv); 1123 } 1124 1125 /* 1126 * Handle suspend/resume. 1127 * 1128 * We need to switch to polling mode here, because this routine is 1129 * called from an interrupt context. This is all right since we 1130 * are almost suspended anyway. 1131 * 1132 * Note that this power handler isn't to be registered directly; the 1133 * bus glue needs to call out to it. 1134 */ 1135 bool 1136 ehci_suspend(device_t dv PMF_FN_ARGS) 1137 { 1138 ehci_softc_t *sc = device_private(dv); 1139 int i, s; 1140 uint32_t cmd, hcr; 1141 1142 s = splhardusb(); 1143 1144 sc->sc_bus.use_polling++; 1145 1146 for (i = 1; i <= sc->sc_noport; i++) { 1147 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1148 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1149 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1150 } 1151 1152 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1153 1154 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1155 EOWRITE4(sc, EHCI_USBCMD, cmd); 1156 1157 for (i = 0; i < 100; i++) { 1158 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1159 if (hcr == 0) 1160 break; 1161 1162 usb_delay_ms(&sc->sc_bus, 1); 1163 } 1164 if (hcr != 0) 1165 printf("%s: reset timeout\n", device_xname(dv)); 1166 1167 cmd &= ~EHCI_CMD_RS; 1168 EOWRITE4(sc, EHCI_USBCMD, cmd); 1169 1170 for (i = 0; i < 100; i++) { 1171 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1172 if (hcr == EHCI_STS_HCH) 1173 break; 1174 1175 usb_delay_ms(&sc->sc_bus, 1); 1176 } 1177 if (hcr != EHCI_STS_HCH) 1178 printf("%s: config timeout\n", device_xname(dv)); 1179 1180 sc->sc_bus.use_polling--; 1181 splx(s); 1182 1183 return true; 1184 } 1185 1186 bool 1187 ehci_resume(device_t dv PMF_FN_ARGS) 1188 { 1189 ehci_softc_t *sc = device_private(dv); 1190 int i; 1191 uint32_t cmd, hcr; 1192 1193 /* restore things in case the bios sucks */ 1194 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1195 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1196 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1197 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1198 1199 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1200 1201 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1202 1203 hcr = 0; 1204 for (i = 1; i <= sc->sc_noport; i++) { 1205 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1206 if ((cmd & EHCI_PS_PO) == 0 && 1207 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1208 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1209 hcr = 1; 1210 } 1211 } 1212 1213 if (hcr) { 1214 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1215 1216 for (i = 1; i <= sc->sc_noport; i++) { 1217 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1218 if ((cmd & EHCI_PS_PO) == 0 && 1219 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1220 EOWRITE4(sc, EHCI_PORTSC(i), 1221 cmd & ~EHCI_PS_FPR); 1222 } 1223 } 1224 1225 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1226 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1227 1228 for (i = 0; i < 100; i++) { 1229 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1230 if (hcr != EHCI_STS_HCH) 1231 break; 1232 1233 usb_delay_ms(&sc->sc_bus, 1); 1234 } 1235 if (hcr == EHCI_STS_HCH) 1236 printf("%s: config timeout\n", device_xname(dv)); 1237 1238 return true; 1239 } 1240 1241 /* 1242 * Shut down the controller when the system is going down. 1243 */ 1244 bool 1245 ehci_shutdown(device_t self, int flags) 1246 { 1247 ehci_softc_t *sc = device_private(self); 1248 1249 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1250 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1251 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1252 return true; 1253 } 1254 1255 usbd_status 1256 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1257 { 1258 struct ehci_softc *sc = bus->hci_private; 1259 usbd_status err; 1260 1261 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1262 if (err == USBD_NOMEM) 1263 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1264 #ifdef EHCI_DEBUG 1265 if (err) 1266 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1267 #endif 1268 return (err); 1269 } 1270 1271 void 1272 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1273 { 1274 struct ehci_softc *sc = bus->hci_private; 1275 1276 if (dma->block->flags & USB_DMA_RESERVE) { 1277 usb_reserve_freem(&sc->sc_dma_reserve, 1278 dma); 1279 return; 1280 } 1281 usb_freemem(&sc->sc_bus, dma); 1282 } 1283 1284 usbd_xfer_handle 1285 ehci_allocx(struct usbd_bus *bus) 1286 { 1287 struct ehci_softc *sc = bus->hci_private; 1288 usbd_xfer_handle xfer; 1289 1290 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1291 if (xfer != NULL) { 1292 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1293 #ifdef DIAGNOSTIC 1294 if (xfer->busy_free != XFER_FREE) { 1295 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1296 xfer->busy_free); 1297 } 1298 #endif 1299 } else { 1300 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1301 } 1302 if (xfer != NULL) { 1303 memset(xfer, 0, sizeof(struct ehci_xfer)); 1304 #ifdef DIAGNOSTIC 1305 EXFER(xfer)->isdone = 1; 1306 xfer->busy_free = XFER_BUSY; 1307 #endif 1308 } 1309 return (xfer); 1310 } 1311 1312 void 1313 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1314 { 1315 struct ehci_softc *sc = bus->hci_private; 1316 1317 #ifdef DIAGNOSTIC 1318 if (xfer->busy_free != XFER_BUSY) { 1319 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1320 xfer->busy_free); 1321 } 1322 xfer->busy_free = XFER_FREE; 1323 if (!EXFER(xfer)->isdone) { 1324 printf("ehci_freex: !isdone\n"); 1325 } 1326 #endif 1327 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1328 } 1329 1330 Static void 1331 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1332 { 1333 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1334 1335 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1336 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1337 #ifdef USB_DEBUG 1338 if (ehcidebug) 1339 usbd_dump_pipe(pipe); 1340 #endif 1341 epipe->nexttoggle = 0; 1342 } 1343 1344 Static void 1345 ehci_noop(usbd_pipe_handle pipe) 1346 { 1347 } 1348 1349 #ifdef EHCI_DEBUG 1350 void 1351 ehci_dump_regs(ehci_softc_t *sc) 1352 { 1353 int i; 1354 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1355 EOREAD4(sc, EHCI_USBCMD), 1356 EOREAD4(sc, EHCI_USBSTS), 1357 EOREAD4(sc, EHCI_USBINTR)); 1358 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1359 EOREAD4(sc, EHCI_FRINDEX), 1360 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1361 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1362 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1363 for (i = 1; i <= sc->sc_noport; i++) 1364 printf("port %d status=0x%08x\n", i, 1365 EOREAD4(sc, EHCI_PORTSC(i))); 1366 } 1367 1368 /* 1369 * Unused function - this is meant to be called from a kernel 1370 * debugger. 1371 */ 1372 void 1373 ehci_dump() 1374 { 1375 ehci_dump_regs(theehci); 1376 } 1377 1378 void 1379 ehci_dump_link(ehci_link_t link, int type) 1380 { 1381 link = le32toh(link); 1382 printf("0x%08x", link); 1383 if (link & EHCI_LINK_TERMINATE) 1384 printf("<T>"); 1385 else { 1386 printf("<"); 1387 if (type) { 1388 switch (EHCI_LINK_TYPE(link)) { 1389 case EHCI_LINK_ITD: printf("ITD"); break; 1390 case EHCI_LINK_QH: printf("QH"); break; 1391 case EHCI_LINK_SITD: printf("SITD"); break; 1392 case EHCI_LINK_FSTN: printf("FSTN"); break; 1393 } 1394 } 1395 printf(">"); 1396 } 1397 } 1398 1399 void 1400 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1401 { 1402 int i; 1403 u_int32_t stop; 1404 1405 stop = 0; 1406 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1407 ehci_dump_sqtd(sqtd); 1408 usb_syncmem(&sqtd->dma, 1409 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1410 sizeof(sqtd->qtd), 1411 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1412 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1413 usb_syncmem(&sqtd->dma, 1414 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1415 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1416 } 1417 if (sqtd) 1418 printf("dump aborted, too many TDs\n"); 1419 } 1420 1421 void 1422 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1423 { 1424 usb_syncmem(&sqtd->dma, sqtd->offs, 1425 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1426 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1427 ehci_dump_qtd(&sqtd->qtd); 1428 usb_syncmem(&sqtd->dma, sqtd->offs, 1429 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1430 } 1431 1432 void 1433 ehci_dump_qtd(ehci_qtd_t *qtd) 1434 { 1435 u_int32_t s; 1436 char sbuf[128]; 1437 1438 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1439 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1440 printf("\n"); 1441 s = le32toh(qtd->qtd_status); 1442 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1443 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1444 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1445 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1446 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1447 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1448 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1449 EHCI_QTD_GET_PID(s), sbuf); 1450 for (s = 0; s < 5; s++) 1451 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1452 } 1453 1454 void 1455 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1456 { 1457 ehci_qh_t *qh = &sqh->qh; 1458 u_int32_t endp, endphub; 1459 1460 usb_syncmem(&sqh->dma, sqh->offs, 1461 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1462 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1463 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1464 endp = le32toh(qh->qh_endp); 1465 printf(" endp=0x%08x\n", endp); 1466 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1467 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1468 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1469 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1470 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1471 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1472 EHCI_QH_GET_NRL(endp)); 1473 endphub = le32toh(qh->qh_endphub); 1474 printf(" endphub=0x%08x\n", endphub); 1475 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1476 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1477 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1478 EHCI_QH_GET_MULT(endphub)); 1479 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1480 printf("Overlay qTD:\n"); 1481 ehci_dump_qtd(&qh->qh_qtd); 1482 usb_syncmem(&sqh->dma, sqh->offs, 1483 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1484 } 1485 1486 #if notyet 1487 void 1488 ehci_dump_itd(struct ehci_soft_itd *itd) 1489 { 1490 ehci_isoc_trans_t t; 1491 ehci_isoc_bufr_ptr_t b, b2, b3; 1492 int i; 1493 1494 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1495 1496 for (i = 0; i < 8;i++) { 1497 t = le32toh(itd->itd.itd_ctl[i]); 1498 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1499 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1500 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1501 EHCI_ITD_GET_OFFS(t)); 1502 } 1503 printf("ITDbufr: "); 1504 for (i = 0; i < 7; i++) 1505 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1506 1507 b = le32toh(itd->itd.itd_bufr[0]); 1508 b2 = le32toh(itd->itd.itd_bufr[1]); 1509 b3 = le32toh(itd->itd.itd_bufr[2]); 1510 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1511 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1512 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1513 } 1514 1515 void 1516 ehci_dump_sitd(struct ehci_soft_itd *itd) 1517 { 1518 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1519 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1520 itd->xfer_next, itd->physaddr, itd->slot); 1521 } 1522 #endif 1523 1524 #ifdef DIAGNOSTIC 1525 void 1526 ehci_dump_exfer(struct ehci_xfer *ex) 1527 { 1528 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1529 } 1530 #endif 1531 #endif 1532 1533 usbd_status 1534 ehci_open(usbd_pipe_handle pipe) 1535 { 1536 usbd_device_handle dev = pipe->device; 1537 ehci_softc_t *sc = dev->bus->hci_private; 1538 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1539 u_int8_t addr = dev->address; 1540 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1541 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1542 ehci_soft_qh_t *sqh; 1543 usbd_status err; 1544 int s; 1545 int ival, speed, naks; 1546 int hshubaddr, hshubport; 1547 1548 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1549 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1550 1551 if (dev->myhsport) { 1552 hshubaddr = dev->myhsport->parent->address; 1553 hshubport = dev->myhsport->portno; 1554 } else { 1555 hshubaddr = 0; 1556 hshubport = 0; 1557 } 1558 1559 if (sc->sc_dying) 1560 return (USBD_IOERROR); 1561 1562 epipe->nexttoggle = 0; 1563 1564 if (addr == sc->sc_addr) { 1565 switch (ed->bEndpointAddress) { 1566 case USB_CONTROL_ENDPOINT: 1567 pipe->methods = &ehci_root_ctrl_methods; 1568 break; 1569 case UE_DIR_IN | EHCI_INTR_ENDPT: 1570 pipe->methods = &ehci_root_intr_methods; 1571 break; 1572 default: 1573 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1574 ed->bEndpointAddress)); 1575 return (USBD_INVAL); 1576 } 1577 return (USBD_NORMAL_COMPLETION); 1578 } 1579 1580 /* XXX All this stuff is only valid for async. */ 1581 switch (dev->speed) { 1582 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1583 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1584 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1585 default: panic("ehci_open: bad device speed %d", dev->speed); 1586 } 1587 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1588 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1589 "isoc endpoint.\n"); 1590 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1591 "attached to a USB2 hub, and transaction translations are " 1592 "not yet supported.\n"); 1593 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1594 "root hub instead.\n"); 1595 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1596 hshubaddr, hshubport)); 1597 return USBD_INVAL; 1598 } 1599 1600 naks = 8; /* XXX */ 1601 1602 /* Allocate sqh for everything, save isoc xfers */ 1603 if (xfertype != UE_ISOCHRONOUS) { 1604 sqh = ehci_alloc_sqh(sc); 1605 if (sqh == NULL) 1606 return (USBD_NOMEM); 1607 /* qh_link filled when the QH is added */ 1608 sqh->qh.qh_endp = htole32( 1609 EHCI_QH_SET_ADDR(addr) | 1610 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1611 EHCI_QH_SET_EPS(speed) | 1612 EHCI_QH_DTC | 1613 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1614 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1615 EHCI_QH_CTL : 0) | 1616 EHCI_QH_SET_NRL(naks) 1617 ); 1618 sqh->qh.qh_endphub = htole32( 1619 EHCI_QH_SET_MULT(1) | 1620 EHCI_QH_SET_HUBA(hshubaddr) | 1621 EHCI_QH_SET_PORT(hshubport) | 1622 EHCI_QH_SET_CMASK(0x08) | /* XXX */ 1623 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1624 ); 1625 sqh->qh.qh_curqtd = EHCI_NULL; 1626 /* Fill the overlay qTD */ 1627 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1628 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1629 sqh->qh.qh_qtd.qtd_status = htole32(0); 1630 1631 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1632 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1633 epipe->sqh = sqh; 1634 } else { 1635 sqh = NULL; 1636 } /*xfertype == UE_ISOC*/ 1637 1638 switch (xfertype) { 1639 case UE_CONTROL: 1640 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1641 0, &epipe->u.ctl.reqdma); 1642 #ifdef EHCI_DEBUG 1643 if (err) 1644 printf("ehci_open: usb_allocmem()=%d\n", err); 1645 #endif 1646 if (err) 1647 goto bad; 1648 pipe->methods = &ehci_device_ctrl_methods; 1649 s = splusb(); 1650 ehci_add_qh(sqh, sc->sc_async_head); 1651 splx(s); 1652 break; 1653 case UE_BULK: 1654 pipe->methods = &ehci_device_bulk_methods; 1655 s = splusb(); 1656 ehci_add_qh(sqh, sc->sc_async_head); 1657 splx(s); 1658 break; 1659 case UE_INTERRUPT: 1660 pipe->methods = &ehci_device_intr_methods; 1661 ival = pipe->interval; 1662 if (ival == USBD_DEFAULT_INTERVAL) { 1663 if (speed == EHCI_QH_SPEED_HIGH) { 1664 if (ed->bInterval > 16) { 1665 /* 1666 * illegal with high-speed, but there 1667 * were documentation bugs in the spec, 1668 * so be generous 1669 */ 1670 ival = 256; 1671 } else 1672 ival = (1 << (ed->bInterval - 1)) / 8; 1673 } else 1674 ival = ed->bInterval; 1675 } 1676 err = ehci_device_setintr(sc, sqh, ival); 1677 if (err) 1678 goto bad; 1679 break; 1680 case UE_ISOCHRONOUS: 1681 pipe->methods = &ehci_device_isoc_methods; 1682 if (ed->bInterval == 0 || ed->bInterval > 16) { 1683 printf("ehci: opening pipe with invalid bInterval\n"); 1684 err = USBD_INVAL; 1685 goto bad; 1686 } 1687 if (UGETW(ed->wMaxPacketSize) == 0) { 1688 printf("ehci: zero length endpoint open request\n"); 1689 err = USBD_INVAL; 1690 goto bad; 1691 } 1692 epipe->u.isoc.next_frame = 0; 1693 epipe->u.isoc.cur_xfers = 0; 1694 break; 1695 default: 1696 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1697 err = USBD_INVAL; 1698 goto bad; 1699 } 1700 return (USBD_NORMAL_COMPLETION); 1701 1702 bad: 1703 if (sqh != NULL) 1704 ehci_free_sqh(sc, sqh); 1705 return (err); 1706 } 1707 1708 /* 1709 * Add an ED to the schedule. Called at splusb(). 1710 */ 1711 void 1712 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1713 { 1714 SPLUSBCHECK; 1715 1716 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1717 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1718 sqh->next = head->next; 1719 sqh->qh.qh_link = head->qh.qh_link; 1720 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1721 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1722 head->next = sqh; 1723 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1724 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1725 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1726 1727 #ifdef EHCI_DEBUG 1728 if (ehcidebug > 5) { 1729 printf("ehci_add_qh:\n"); 1730 ehci_dump_sqh(sqh); 1731 } 1732 #endif 1733 } 1734 1735 /* 1736 * Remove an ED from the schedule. Called at splusb(). 1737 */ 1738 void 1739 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1740 { 1741 ehci_soft_qh_t *p; 1742 1743 SPLUSBCHECK; 1744 /* XXX */ 1745 for (p = head; p != NULL && p->next != sqh; p = p->next) 1746 ; 1747 if (p == NULL) 1748 panic("ehci_rem_qh: ED not found"); 1749 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1750 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1751 p->next = sqh->next; 1752 p->qh.qh_link = sqh->qh.qh_link; 1753 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1754 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1755 1756 ehci_sync_hc(sc); 1757 } 1758 1759 void 1760 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1761 { 1762 int i; 1763 u_int32_t status; 1764 1765 /* Save toggle bit and ping status. */ 1766 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1767 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1768 status = sqh->qh.qh_qtd.qtd_status & 1769 htole32(EHCI_QTD_TOGGLE_MASK | 1770 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1771 /* Set HALTED to make hw leave it alone. */ 1772 sqh->qh.qh_qtd.qtd_status = 1773 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1774 usb_syncmem(&sqh->dma, 1775 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1776 sizeof(sqh->qh.qh_qtd.qtd_status), 1777 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1778 sqh->qh.qh_curqtd = 0; 1779 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1780 sqh->qh.qh_qtd.qtd_altnext = 0; 1781 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1782 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1783 sqh->sqtd = sqtd; 1784 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1785 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1786 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1787 sqh->qh.qh_qtd.qtd_status = status; 1788 usb_syncmem(&sqh->dma, 1789 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1790 sizeof(sqh->qh.qh_qtd.qtd_status), 1791 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1792 } 1793 1794 /* 1795 * Ensure that the HC has released all references to the QH. We do this 1796 * by asking for a Async Advance Doorbell interrupt and then we wait for 1797 * the interrupt. 1798 * To make this easier we first obtain exclusive use of the doorbell. 1799 */ 1800 void 1801 ehci_sync_hc(ehci_softc_t *sc) 1802 { 1803 int s, error; 1804 1805 if (sc->sc_dying) { 1806 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1807 return; 1808 } 1809 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1810 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */ 1811 s = splhardusb(); 1812 /* ask for doorbell */ 1813 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1814 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1815 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1816 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1817 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1818 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1819 splx(s); 1820 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */ 1821 #ifdef DIAGNOSTIC 1822 if (error) 1823 printf("ehci_sync_hc: tsleep() = %d\n", error); 1824 #endif 1825 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1826 } 1827 1828 /*Call at splusb*/ 1829 void 1830 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1831 { 1832 struct ehci_soft_itd *itd, *prev; 1833 1834 prev = NULL; 1835 1836 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1837 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1838 1839 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1840 prev = itd->u.frame_list.prev; 1841 /* Unlink itd from hardware chain, or frame array */ 1842 if (prev == NULL) { /* We're at the table head */ 1843 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1844 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1845 usb_syncmem(&sc->sc_fldma, 1846 sizeof(ehci_link_t) * itd->slot, 1847 sizeof(ehci_link_t), 1848 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1849 1850 if (itd->u.frame_list.next != NULL) 1851 itd->u.frame_list.next->u.frame_list.prev = NULL; 1852 } else { 1853 /* XXX this part is untested... */ 1854 prev->itd.itd_next = itd->itd.itd_next; 1855 usb_syncmem(&itd->dma, 1856 itd->offs + offsetof(ehci_itd_t, itd_next), 1857 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1858 1859 prev->u.frame_list.next = itd->u.frame_list.next; 1860 if (itd->u.frame_list.next != NULL) 1861 itd->u.frame_list.next->u.frame_list.prev = prev; 1862 } 1863 } 1864 1865 prev = NULL; 1866 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1867 if (prev != NULL) 1868 ehci_free_itd(sc, prev); 1869 prev = itd; 1870 } 1871 if (prev) 1872 ehci_free_itd(sc, prev); 1873 exfer->itdstart = NULL; 1874 exfer->itdend = NULL; 1875 } 1876 1877 /***********/ 1878 1879 /* 1880 * Data structures and routines to emulate the root hub. 1881 */ 1882 Static usb_device_descriptor_t ehci_devd = { 1883 USB_DEVICE_DESCRIPTOR_SIZE, 1884 UDESC_DEVICE, /* type */ 1885 {0x00, 0x02}, /* USB version */ 1886 UDCLASS_HUB, /* class */ 1887 UDSUBCLASS_HUB, /* subclass */ 1888 UDPROTO_HSHUBSTT, /* protocol */ 1889 64, /* max packet */ 1890 {0},{0},{0x00,0x01}, /* device id */ 1891 1,2,0, /* string indicies */ 1892 1 /* # of configurations */ 1893 }; 1894 1895 Static const usb_device_qualifier_t ehci_odevd = { 1896 USB_DEVICE_DESCRIPTOR_SIZE, 1897 UDESC_DEVICE_QUALIFIER, /* type */ 1898 {0x00, 0x02}, /* USB version */ 1899 UDCLASS_HUB, /* class */ 1900 UDSUBCLASS_HUB, /* subclass */ 1901 UDPROTO_FSHUB, /* protocol */ 1902 64, /* max packet */ 1903 1, /* # of configurations */ 1904 0 1905 }; 1906 1907 Static const usb_config_descriptor_t ehci_confd = { 1908 USB_CONFIG_DESCRIPTOR_SIZE, 1909 UDESC_CONFIG, 1910 {USB_CONFIG_DESCRIPTOR_SIZE + 1911 USB_INTERFACE_DESCRIPTOR_SIZE + 1912 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1913 1, 1914 1, 1915 0, 1916 UC_ATTR_MBO | UC_SELF_POWERED, 1917 0 /* max power */ 1918 }; 1919 1920 Static const usb_interface_descriptor_t ehci_ifcd = { 1921 USB_INTERFACE_DESCRIPTOR_SIZE, 1922 UDESC_INTERFACE, 1923 0, 1924 0, 1925 1, 1926 UICLASS_HUB, 1927 UISUBCLASS_HUB, 1928 UIPROTO_HSHUBSTT, 1929 0 1930 }; 1931 1932 Static const usb_endpoint_descriptor_t ehci_endpd = { 1933 USB_ENDPOINT_DESCRIPTOR_SIZE, 1934 UDESC_ENDPOINT, 1935 UE_DIR_IN | EHCI_INTR_ENDPT, 1936 UE_INTERRUPT, 1937 {8, 0}, /* max packet */ 1938 12 1939 }; 1940 1941 Static const usb_hub_descriptor_t ehci_hubd = { 1942 USB_HUB_DESCRIPTOR_SIZE, 1943 UDESC_HUB, 1944 0, 1945 {0,0}, 1946 0, 1947 0, 1948 {""}, 1949 {""}, 1950 }; 1951 1952 /* 1953 * Simulate a hardware hub by handling all the necessary requests. 1954 */ 1955 Static usbd_status 1956 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1957 { 1958 usbd_status err; 1959 1960 /* Insert last in queue. */ 1961 err = usb_insert_transfer(xfer); 1962 if (err) 1963 return (err); 1964 1965 /* Pipe isn't running, start first */ 1966 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1967 } 1968 1969 Static usbd_status 1970 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1971 { 1972 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1973 usb_device_request_t *req; 1974 void *buf = NULL; 1975 int port, i; 1976 int s, len, value, index, l, totlen = 0; 1977 usb_port_status_t ps; 1978 usb_hub_descriptor_t hubd; 1979 usbd_status err; 1980 u_int32_t v; 1981 1982 if (sc->sc_dying) 1983 return (USBD_IOERROR); 1984 1985 #ifdef DIAGNOSTIC 1986 if (!(xfer->rqflags & URQ_REQUEST)) 1987 /* XXX panic */ 1988 return (USBD_INVAL); 1989 #endif 1990 req = &xfer->request; 1991 1992 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1993 req->bmRequestType, req->bRequest)); 1994 1995 len = UGETW(req->wLength); 1996 value = UGETW(req->wValue); 1997 index = UGETW(req->wIndex); 1998 1999 if (len != 0) 2000 buf = KERNADDR(&xfer->dmabuf, 0); 2001 2002 #define C(x,y) ((x) | ((y) << 8)) 2003 switch(C(req->bRequest, req->bmRequestType)) { 2004 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2005 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2006 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2007 /* 2008 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2009 * for the integrated root hub. 2010 */ 2011 break; 2012 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2013 if (len > 0) { 2014 *(u_int8_t *)buf = sc->sc_conf; 2015 totlen = 1; 2016 } 2017 break; 2018 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2019 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2020 if (len == 0) 2021 break; 2022 switch(value >> 8) { 2023 case UDESC_DEVICE: 2024 if ((value & 0xff) != 0) { 2025 err = USBD_IOERROR; 2026 goto ret; 2027 } 2028 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2029 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2030 memcpy(buf, &ehci_devd, l); 2031 break; 2032 /* 2033 * We can't really operate at another speed, but the spec says 2034 * we need this descriptor. 2035 */ 2036 case UDESC_DEVICE_QUALIFIER: 2037 if ((value & 0xff) != 0) { 2038 err = USBD_IOERROR; 2039 goto ret; 2040 } 2041 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2042 memcpy(buf, &ehci_odevd, l); 2043 break; 2044 /* 2045 * We can't really operate at another speed, but the spec says 2046 * we need this descriptor. 2047 */ 2048 case UDESC_OTHER_SPEED_CONFIGURATION: 2049 case UDESC_CONFIG: 2050 if ((value & 0xff) != 0) { 2051 err = USBD_IOERROR; 2052 goto ret; 2053 } 2054 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2055 memcpy(buf, &ehci_confd, l); 2056 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2057 value >> 8; 2058 buf = (char *)buf + l; 2059 len -= l; 2060 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2061 totlen += l; 2062 memcpy(buf, &ehci_ifcd, l); 2063 buf = (char *)buf + l; 2064 len -= l; 2065 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2066 totlen += l; 2067 memcpy(buf, &ehci_endpd, l); 2068 break; 2069 case UDESC_STRING: 2070 #define sd ((usb_string_descriptor_t *)buf) 2071 switch (value & 0xff) { 2072 case 0: /* Language table */ 2073 totlen = usb_makelangtbl(sd, len); 2074 break; 2075 case 1: /* Vendor */ 2076 totlen = usb_makestrdesc(sd, len, 2077 sc->sc_vendor); 2078 break; 2079 case 2: /* Product */ 2080 totlen = usb_makestrdesc(sd, len, 2081 "EHCI root hub"); 2082 break; 2083 } 2084 #undef sd 2085 break; 2086 default: 2087 err = USBD_IOERROR; 2088 goto ret; 2089 } 2090 break; 2091 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2092 if (len > 0) { 2093 *(u_int8_t *)buf = 0; 2094 totlen = 1; 2095 } 2096 break; 2097 case C(UR_GET_STATUS, UT_READ_DEVICE): 2098 if (len > 1) { 2099 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2100 totlen = 2; 2101 } 2102 break; 2103 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2104 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2105 if (len > 1) { 2106 USETW(((usb_status_t *)buf)->wStatus, 0); 2107 totlen = 2; 2108 } 2109 break; 2110 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2111 if (value >= USB_MAX_DEVICES) { 2112 err = USBD_IOERROR; 2113 goto ret; 2114 } 2115 sc->sc_addr = value; 2116 break; 2117 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2118 if (value != 0 && value != 1) { 2119 err = USBD_IOERROR; 2120 goto ret; 2121 } 2122 sc->sc_conf = value; 2123 break; 2124 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2125 break; 2126 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2127 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2128 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2129 err = USBD_IOERROR; 2130 goto ret; 2131 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2132 break; 2133 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2134 break; 2135 /* Hub requests */ 2136 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2137 break; 2138 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2139 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2140 "port=%d feature=%d\n", 2141 index, value)); 2142 if (index < 1 || index > sc->sc_noport) { 2143 err = USBD_IOERROR; 2144 goto ret; 2145 } 2146 port = EHCI_PORTSC(index); 2147 v = EOREAD4(sc, port); 2148 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2149 v &= ~EHCI_PS_CLEAR; 2150 switch(value) { 2151 case UHF_PORT_ENABLE: 2152 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2153 break; 2154 case UHF_PORT_SUSPEND: 2155 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2156 break; 2157 v &= ~EHCI_PS_SUSP; 2158 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2159 /* see USB2 spec ch. 7.1.7.7 */ 2160 usb_delay_ms(&sc->sc_bus, 20); 2161 EOWRITE4(sc, port, v); 2162 usb_delay_ms(&sc->sc_bus, 2); 2163 #ifdef DEBUG 2164 v = EOREAD4(sc, port); 2165 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2166 printf("ehci: resume failed: %x\n", v); 2167 #endif 2168 break; 2169 case UHF_PORT_POWER: 2170 if (sc->sc_hasppc) 2171 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2172 break; 2173 case UHF_PORT_TEST: 2174 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2175 "%d\n", index)); 2176 break; 2177 case UHF_PORT_INDICATOR: 2178 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2179 "%d\n", index)); 2180 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2181 break; 2182 case UHF_C_PORT_CONNECTION: 2183 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2184 break; 2185 case UHF_C_PORT_ENABLE: 2186 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2187 break; 2188 case UHF_C_PORT_SUSPEND: 2189 /* how? */ 2190 break; 2191 case UHF_C_PORT_OVER_CURRENT: 2192 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2193 break; 2194 case UHF_C_PORT_RESET: 2195 sc->sc_isreset[index] = 0; 2196 break; 2197 default: 2198 err = USBD_IOERROR; 2199 goto ret; 2200 } 2201 #if 0 2202 switch(value) { 2203 case UHF_C_PORT_CONNECTION: 2204 case UHF_C_PORT_ENABLE: 2205 case UHF_C_PORT_SUSPEND: 2206 case UHF_C_PORT_OVER_CURRENT: 2207 case UHF_C_PORT_RESET: 2208 default: 2209 break; 2210 } 2211 #endif 2212 break; 2213 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2214 if (len == 0) 2215 break; 2216 if ((value & 0xff) != 0) { 2217 err = USBD_IOERROR; 2218 goto ret; 2219 } 2220 hubd = ehci_hubd; 2221 hubd.bNbrPorts = sc->sc_noport; 2222 v = EOREAD4(sc, EHCI_HCSPARAMS); 2223 USETW(hubd.wHubCharacteristics, 2224 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2225 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2226 ? UHD_PORT_IND : 0); 2227 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2228 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2229 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2230 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2231 l = min(len, hubd.bDescLength); 2232 totlen = l; 2233 memcpy(buf, &hubd, l); 2234 break; 2235 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2236 if (len != 4) { 2237 err = USBD_IOERROR; 2238 goto ret; 2239 } 2240 memset(buf, 0, len); /* ? XXX */ 2241 totlen = len; 2242 break; 2243 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2244 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2245 index)); 2246 if (index < 1 || index > sc->sc_noport) { 2247 err = USBD_IOERROR; 2248 goto ret; 2249 } 2250 if (len != 4) { 2251 err = USBD_IOERROR; 2252 goto ret; 2253 } 2254 v = EOREAD4(sc, EHCI_PORTSC(index)); 2255 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2256 v)); 2257 i = UPS_HIGH_SPEED; 2258 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2259 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2260 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2261 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2262 if (v & EHCI_PS_PR) i |= UPS_RESET; 2263 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2264 USETW(ps.wPortStatus, i); 2265 i = 0; 2266 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2267 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2268 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2269 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2270 USETW(ps.wPortChange, i); 2271 l = min(len, sizeof ps); 2272 memcpy(buf, &ps, l); 2273 totlen = l; 2274 break; 2275 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2276 err = USBD_IOERROR; 2277 goto ret; 2278 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2279 break; 2280 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2281 if (index < 1 || index > sc->sc_noport) { 2282 err = USBD_IOERROR; 2283 goto ret; 2284 } 2285 port = EHCI_PORTSC(index); 2286 v = EOREAD4(sc, port); 2287 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2288 v &= ~EHCI_PS_CLEAR; 2289 switch(value) { 2290 case UHF_PORT_ENABLE: 2291 EOWRITE4(sc, port, v | EHCI_PS_PE); 2292 break; 2293 case UHF_PORT_SUSPEND: 2294 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2295 break; 2296 case UHF_PORT_RESET: 2297 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2298 index)); 2299 if (EHCI_PS_IS_LOWSPEED(v)) { 2300 /* Low speed device, give up ownership. */ 2301 ehci_disown(sc, index, 1); 2302 break; 2303 } 2304 /* Start reset sequence. */ 2305 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2306 EOWRITE4(sc, port, v | EHCI_PS_PR); 2307 /* Wait for reset to complete. */ 2308 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2309 if (sc->sc_dying) { 2310 err = USBD_IOERROR; 2311 goto ret; 2312 } 2313 /* Terminate reset sequence. */ 2314 EOWRITE4(sc, port, v); 2315 /* Wait for HC to complete reset. */ 2316 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2317 if (sc->sc_dying) { 2318 err = USBD_IOERROR; 2319 goto ret; 2320 } 2321 v = EOREAD4(sc, port); 2322 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2323 if (v & EHCI_PS_PR) { 2324 printf("%s: port reset timeout\n", 2325 device_xname(sc->sc_dev)); 2326 return (USBD_TIMEOUT); 2327 } 2328 if (!(v & EHCI_PS_PE)) { 2329 /* Not a high speed device, give up ownership.*/ 2330 ehci_disown(sc, index, 0); 2331 break; 2332 } 2333 sc->sc_isreset[index] = 1; 2334 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2335 index, v)); 2336 break; 2337 case UHF_PORT_POWER: 2338 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2339 "%d (has PPC = %d)\n", index, 2340 sc->sc_hasppc)); 2341 if (sc->sc_hasppc) 2342 EOWRITE4(sc, port, v | EHCI_PS_PP); 2343 break; 2344 case UHF_PORT_TEST: 2345 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2346 "%d\n", index)); 2347 break; 2348 case UHF_PORT_INDICATOR: 2349 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2350 "%d\n", index)); 2351 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2352 break; 2353 default: 2354 err = USBD_IOERROR; 2355 goto ret; 2356 } 2357 break; 2358 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2359 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2360 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2361 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2362 break; 2363 default: 2364 err = USBD_IOERROR; 2365 goto ret; 2366 } 2367 xfer->actlen = totlen; 2368 err = USBD_NORMAL_COMPLETION; 2369 ret: 2370 xfer->status = err; 2371 s = splusb(); 2372 usb_transfer_complete(xfer); 2373 splx(s); 2374 return (USBD_IN_PROGRESS); 2375 } 2376 2377 void 2378 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2379 { 2380 int port; 2381 u_int32_t v; 2382 2383 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2384 #ifdef DIAGNOSTIC 2385 if (sc->sc_npcomp != 0) { 2386 int i = (index-1) / sc->sc_npcomp; 2387 if (i >= sc->sc_ncomp) 2388 printf("%s: strange port\n", 2389 device_xname(sc->sc_dev)); 2390 else 2391 printf("%s: handing over %s speed device on " 2392 "port %d to %s\n", 2393 device_xname(sc->sc_dev), 2394 lowspeed ? "low" : "full", 2395 index, device_xname(sc->sc_comps[i])); 2396 } else { 2397 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2398 } 2399 #endif 2400 port = EHCI_PORTSC(index); 2401 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2402 EOWRITE4(sc, port, v | EHCI_PS_PO); 2403 } 2404 2405 /* Abort a root control request. */ 2406 Static void 2407 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2408 { 2409 /* Nothing to do, all transfers are synchronous. */ 2410 } 2411 2412 /* Close the root pipe. */ 2413 Static void 2414 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2415 { 2416 DPRINTF(("ehci_root_ctrl_close\n")); 2417 /* Nothing to do. */ 2418 } 2419 2420 void 2421 ehci_root_intr_done(usbd_xfer_handle xfer) 2422 { 2423 xfer->hcpriv = NULL; 2424 } 2425 2426 Static usbd_status 2427 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2428 { 2429 usbd_status err; 2430 2431 /* Insert last in queue. */ 2432 err = usb_insert_transfer(xfer); 2433 if (err) 2434 return (err); 2435 2436 /* Pipe isn't running, start first */ 2437 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2438 } 2439 2440 Static usbd_status 2441 ehci_root_intr_start(usbd_xfer_handle xfer) 2442 { 2443 usbd_pipe_handle pipe = xfer->pipe; 2444 ehci_softc_t *sc = pipe->device->bus->hci_private; 2445 2446 if (sc->sc_dying) 2447 return (USBD_IOERROR); 2448 2449 sc->sc_intrxfer = xfer; 2450 2451 return (USBD_IN_PROGRESS); 2452 } 2453 2454 /* Abort a root interrupt request. */ 2455 Static void 2456 ehci_root_intr_abort(usbd_xfer_handle xfer) 2457 { 2458 int s; 2459 2460 if (xfer->pipe->intrxfer == xfer) { 2461 DPRINTF(("ehci_root_intr_abort: remove\n")); 2462 xfer->pipe->intrxfer = NULL; 2463 } 2464 xfer->status = USBD_CANCELLED; 2465 s = splusb(); 2466 usb_transfer_complete(xfer); 2467 splx(s); 2468 } 2469 2470 /* Close the root pipe. */ 2471 Static void 2472 ehci_root_intr_close(usbd_pipe_handle pipe) 2473 { 2474 ehci_softc_t *sc = pipe->device->bus->hci_private; 2475 2476 DPRINTF(("ehci_root_intr_close\n")); 2477 2478 sc->sc_intrxfer = NULL; 2479 } 2480 2481 void 2482 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2483 { 2484 xfer->hcpriv = NULL; 2485 } 2486 2487 /************************/ 2488 2489 ehci_soft_qh_t * 2490 ehci_alloc_sqh(ehci_softc_t *sc) 2491 { 2492 ehci_soft_qh_t *sqh; 2493 usbd_status err; 2494 int i, offs; 2495 usb_dma_t dma; 2496 2497 if (sc->sc_freeqhs == NULL) { 2498 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2499 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2500 EHCI_PAGE_SIZE, &dma); 2501 #ifdef EHCI_DEBUG 2502 if (err) 2503 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2504 #endif 2505 if (err) 2506 return (NULL); 2507 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2508 offs = i * EHCI_SQH_SIZE; 2509 sqh = KERNADDR(&dma, offs); 2510 sqh->physaddr = DMAADDR(&dma, offs); 2511 sqh->dma = dma; 2512 sqh->offs = offs; 2513 sqh->next = sc->sc_freeqhs; 2514 sc->sc_freeqhs = sqh; 2515 } 2516 } 2517 sqh = sc->sc_freeqhs; 2518 sc->sc_freeqhs = sqh->next; 2519 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2520 sqh->next = NULL; 2521 return (sqh); 2522 } 2523 2524 void 2525 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2526 { 2527 sqh->next = sc->sc_freeqhs; 2528 sc->sc_freeqhs = sqh; 2529 } 2530 2531 ehci_soft_qtd_t * 2532 ehci_alloc_sqtd(ehci_softc_t *sc) 2533 { 2534 ehci_soft_qtd_t *sqtd; 2535 usbd_status err; 2536 int i, offs; 2537 usb_dma_t dma; 2538 int s; 2539 2540 if (sc->sc_freeqtds == NULL) { 2541 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2542 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2543 EHCI_PAGE_SIZE, &dma); 2544 #ifdef EHCI_DEBUG 2545 if (err) 2546 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2547 #endif 2548 if (err) 2549 return (NULL); 2550 s = splusb(); 2551 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2552 offs = i * EHCI_SQTD_SIZE; 2553 sqtd = KERNADDR(&dma, offs); 2554 sqtd->physaddr = DMAADDR(&dma, offs); 2555 sqtd->dma = dma; 2556 sqtd->offs = offs; 2557 sqtd->nextqtd = sc->sc_freeqtds; 2558 sc->sc_freeqtds = sqtd; 2559 } 2560 splx(s); 2561 } 2562 2563 s = splusb(); 2564 sqtd = sc->sc_freeqtds; 2565 sc->sc_freeqtds = sqtd->nextqtd; 2566 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2567 sqtd->nextqtd = NULL; 2568 sqtd->xfer = NULL; 2569 splx(s); 2570 2571 return (sqtd); 2572 } 2573 2574 void 2575 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2576 { 2577 int s; 2578 2579 s = splusb(); 2580 sqtd->nextqtd = sc->sc_freeqtds; 2581 sc->sc_freeqtds = sqtd; 2582 splx(s); 2583 } 2584 2585 usbd_status 2586 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2587 int alen, int rd, usbd_xfer_handle xfer, 2588 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2589 { 2590 ehci_soft_qtd_t *next, *cur; 2591 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2592 u_int32_t qtdstatus; 2593 int len, curlen, mps; 2594 int i, tog; 2595 usb_dma_t *dma = &xfer->dmabuf; 2596 u_int16_t flags = xfer->flags; 2597 2598 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2599 2600 len = alen; 2601 dataphys = DMAADDR(dma, 0); 2602 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2603 qtdstatus = EHCI_QTD_ACTIVE | 2604 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2605 EHCI_QTD_SET_CERR(3) 2606 /* IOC set below */ 2607 /* BYTES set below */ 2608 ; 2609 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2610 tog = epipe->nexttoggle; 2611 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2612 2613 cur = ehci_alloc_sqtd(sc); 2614 *sp = cur; 2615 if (cur == NULL) 2616 goto nomem; 2617 2618 usb_syncmem(dma, 0, alen, 2619 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2620 for (;;) { 2621 dataphyspage = EHCI_PAGE(dataphys); 2622 /* The EHCI hardware can handle at most 5 pages. */ 2623 if (dataphyslastpage - dataphyspage < 2624 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2625 /* we can handle it in this QTD */ 2626 curlen = len; 2627 } else { 2628 /* must use multiple TDs, fill as much as possible. */ 2629 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2630 EHCI_PAGE_OFFSET(dataphys); 2631 #ifdef DIAGNOSTIC 2632 if (curlen > len) { 2633 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2634 "len=0x%x offs=0x%x\n", curlen, len, 2635 EHCI_PAGE_OFFSET(dataphys)); 2636 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2637 dataphyslastpage, dataphyspage, 2638 dataphys); 2639 curlen = len; 2640 } 2641 #endif 2642 /* the length must be a multiple of the max size */ 2643 curlen -= curlen % mps; 2644 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2645 "curlen=%d\n", curlen)); 2646 #ifdef DIAGNOSTIC 2647 if (curlen == 0) 2648 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2649 #endif 2650 } 2651 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2652 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2653 dataphys, dataphyslastpage, 2654 len, curlen)); 2655 len -= curlen; 2656 2657 /* 2658 * Allocate another transfer if there's more data left, 2659 * or if force last short transfer flag is set and we're 2660 * allocating a multiple of the max packet size. 2661 */ 2662 if (len != 0 || 2663 ((curlen % mps) == 0 && !rd && curlen != 0 && 2664 (flags & USBD_FORCE_SHORT_XFER))) { 2665 next = ehci_alloc_sqtd(sc); 2666 if (next == NULL) 2667 goto nomem; 2668 nextphys = htole32(next->physaddr); 2669 } else { 2670 next = NULL; 2671 nextphys = EHCI_NULL; 2672 } 2673 2674 for (i = 0; i * EHCI_PAGE_SIZE < 2675 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2676 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2677 if (i != 0) /* use offset only in first buffer */ 2678 a = EHCI_PAGE(a); 2679 cur->qtd.qtd_buffer[i] = htole32(a); 2680 cur->qtd.qtd_buffer_hi[i] = 0; 2681 #ifdef DIAGNOSTIC 2682 if (i >= EHCI_QTD_NBUFFERS) { 2683 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2684 goto nomem; 2685 } 2686 #endif 2687 } 2688 cur->nextqtd = next; 2689 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2690 cur->qtd.qtd_status = 2691 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2692 cur->xfer = xfer; 2693 cur->len = curlen; 2694 2695 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2696 dataphys, dataphys + curlen)); 2697 /* adjust the toggle based on the number of packets in this 2698 qtd */ 2699 if (((curlen + mps - 1) / mps) & 1) { 2700 tog ^= 1; 2701 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2702 } 2703 if (next == NULL) 2704 break; 2705 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2706 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2707 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2708 dataphys += curlen; 2709 cur = next; 2710 } 2711 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2712 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2713 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2714 *ep = cur; 2715 epipe->nexttoggle = tog; 2716 2717 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2718 *sp, *ep)); 2719 2720 return (USBD_NORMAL_COMPLETION); 2721 2722 nomem: 2723 /* XXX free chain */ 2724 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2725 return (USBD_NOMEM); 2726 } 2727 2728 Static void 2729 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2730 ehci_soft_qtd_t *sqtdend) 2731 { 2732 ehci_soft_qtd_t *p; 2733 int i; 2734 2735 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2736 sqtd, sqtdend)); 2737 2738 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2739 p = sqtd->nextqtd; 2740 ehci_free_sqtd(sc, sqtd); 2741 } 2742 } 2743 2744 ehci_soft_itd_t * 2745 ehci_alloc_itd(ehci_softc_t *sc) 2746 { 2747 struct ehci_soft_itd *itd, *freeitd; 2748 usbd_status err; 2749 int i, s, offs, frindex, previndex; 2750 usb_dma_t dma; 2751 2752 s = splusb(); 2753 2754 /* Find an itd that wasn't freed this frame or last frame. This can 2755 * discard itds that were freed before frindex wrapped around 2756 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2757 * interrupt and fiddling with list when that happens */ 2758 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2759 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2760 2761 freeitd = NULL; 2762 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2763 if (itd == NULL) 2764 break; 2765 if (itd->slot != frindex && itd->slot != previndex) { 2766 freeitd = itd; 2767 break; 2768 } 2769 } 2770 2771 if (freeitd == NULL) { 2772 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2773 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2774 EHCI_PAGE_SIZE, &dma); 2775 2776 if (err) { 2777 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2778 return NULL; 2779 } 2780 2781 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2782 offs = i * EHCI_ITD_SIZE; 2783 itd = KERNADDR(&dma, offs); 2784 itd->physaddr = DMAADDR(&dma, offs); 2785 itd->dma = dma; 2786 itd->offs = offs; 2787 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2788 } 2789 freeitd = LIST_FIRST(&sc->sc_freeitds); 2790 } 2791 2792 itd = freeitd; 2793 LIST_REMOVE(itd, u.free_list); 2794 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2795 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2796 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2797 BUS_DMASYNC_PREREAD); 2798 2799 itd->u.frame_list.next = NULL; 2800 itd->u.frame_list.prev = NULL; 2801 itd->xfer_next = NULL; 2802 itd->slot = 0; 2803 splx(s); 2804 2805 return itd; 2806 } 2807 2808 void 2809 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2810 { 2811 int s; 2812 2813 s = splusb(); 2814 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2815 splx(s); 2816 } 2817 2818 2819 2820 /****************/ 2821 2822 /* 2823 * Close a reqular pipe. 2824 * Assumes that there are no pending transactions. 2825 */ 2826 void 2827 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2828 { 2829 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2830 ehci_softc_t *sc = pipe->device->bus->hci_private; 2831 ehci_soft_qh_t *sqh = epipe->sqh; 2832 int s; 2833 2834 s = splusb(); 2835 ehci_rem_qh(sc, sqh, head); 2836 splx(s); 2837 ehci_free_sqh(sc, epipe->sqh); 2838 } 2839 2840 /* 2841 * Abort a device request. 2842 * If this routine is called at splusb() it guarantees that the request 2843 * will be removed from the hardware scheduling and that the callback 2844 * for it will be called with USBD_CANCELLED status. 2845 * It's impossible to guarantee that the requested transfer will not 2846 * have happened since the hardware runs concurrently. 2847 * If the transaction has already happened we rely on the ordinary 2848 * interrupt processing to process it. 2849 * XXX This is most probably wrong. 2850 */ 2851 void 2852 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2853 { 2854 #define exfer EXFER(xfer) 2855 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2856 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2857 ehci_soft_qh_t *sqh = epipe->sqh; 2858 ehci_soft_qtd_t *sqtd; 2859 ehci_physaddr_t cur; 2860 u_int32_t qhstatus; 2861 int s; 2862 int hit; 2863 int wake; 2864 2865 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2866 2867 if (sc->sc_dying) { 2868 /* If we're dying, just do the software part. */ 2869 s = splusb(); 2870 xfer->status = status; /* make software ignore it */ 2871 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2872 usb_transfer_complete(xfer); 2873 splx(s); 2874 return; 2875 } 2876 2877 if (xfer->device->bus->intr_context) 2878 panic("ehci_abort_xfer: not in process context"); 2879 2880 /* 2881 * If an abort is already in progress then just wait for it to 2882 * complete and return. 2883 */ 2884 if (xfer->hcflags & UXFER_ABORTING) { 2885 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2886 #ifdef DIAGNOSTIC 2887 if (status == USBD_TIMEOUT) 2888 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2889 #endif 2890 /* Override the status which might be USBD_TIMEOUT. */ 2891 xfer->status = status; 2892 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2893 xfer->hcflags |= UXFER_ABORTWAIT; 2894 while (xfer->hcflags & UXFER_ABORTING) 2895 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2896 return; 2897 } 2898 xfer->hcflags |= UXFER_ABORTING; 2899 2900 /* 2901 * Step 1: Make interrupt routine and hardware ignore xfer. 2902 */ 2903 s = splusb(); 2904 xfer->status = status; /* make software ignore it */ 2905 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2906 2907 usb_syncmem(&sqh->dma, 2908 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2909 sizeof(sqh->qh.qh_qtd.qtd_status), 2910 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2911 qhstatus = sqh->qh.qh_qtd.qtd_status; 2912 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2913 usb_syncmem(&sqh->dma, 2914 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2915 sizeof(sqh->qh.qh_qtd.qtd_status), 2916 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2917 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2918 usb_syncmem(&sqtd->dma, 2919 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2920 sizeof(sqtd->qtd.qtd_status), 2921 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2922 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2923 usb_syncmem(&sqtd->dma, 2924 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2925 sizeof(sqtd->qtd.qtd_status), 2926 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2927 if (sqtd == exfer->sqtdend) 2928 break; 2929 } 2930 splx(s); 2931 2932 /* 2933 * Step 2: Wait until we know hardware has finished any possible 2934 * use of the xfer. Also make sure the soft interrupt routine 2935 * has run. 2936 */ 2937 ehci_sync_hc(sc); 2938 s = splusb(); 2939 #ifdef USB_USE_SOFTINTR 2940 sc->sc_softwake = 1; 2941 #endif /* USB_USE_SOFTINTR */ 2942 usb_schedsoftintr(&sc->sc_bus); 2943 #ifdef USB_USE_SOFTINTR 2944 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2945 #endif /* USB_USE_SOFTINTR */ 2946 splx(s); 2947 2948 /* 2949 * Step 3: Remove any vestiges of the xfer from the hardware. 2950 * The complication here is that the hardware may have executed 2951 * beyond the xfer we're trying to abort. So as we're scanning 2952 * the TDs of this xfer we check if the hardware points to 2953 * any of them. 2954 */ 2955 s = splusb(); /* XXX why? */ 2956 2957 usb_syncmem(&sqh->dma, 2958 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2959 sizeof(sqh->qh.qh_curqtd), 2960 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2961 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2962 hit = 0; 2963 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2964 hit |= cur == sqtd->physaddr; 2965 if (sqtd == exfer->sqtdend) 2966 break; 2967 } 2968 sqtd = sqtd->nextqtd; 2969 /* Zap curqtd register if hardware pointed inside the xfer. */ 2970 if (hit && sqtd != NULL) { 2971 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 2972 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 2973 usb_syncmem(&sqh->dma, 2974 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2975 sizeof(sqh->qh.qh_curqtd), 2976 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2977 sqh->qh.qh_qtd.qtd_status = qhstatus; 2978 usb_syncmem(&sqh->dma, 2979 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2980 sizeof(sqh->qh.qh_qtd.qtd_status), 2981 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2982 } else { 2983 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2984 } 2985 2986 /* 2987 * Step 4: Execute callback. 2988 */ 2989 #ifdef DIAGNOSTIC 2990 exfer->isdone = 1; 2991 #endif 2992 wake = xfer->hcflags & UXFER_ABORTWAIT; 2993 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2994 usb_transfer_complete(xfer); 2995 if (wake) 2996 wakeup(&xfer->hcflags); 2997 2998 splx(s); 2999 #undef exfer 3000 } 3001 3002 void 3003 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3004 { 3005 ehci_isoc_trans_t trans_status; 3006 struct ehci_pipe *epipe; 3007 struct ehci_xfer *exfer; 3008 ehci_softc_t *sc; 3009 struct ehci_soft_itd *itd; 3010 int s, i, wake; 3011 3012 epipe = (struct ehci_pipe *) xfer->pipe; 3013 exfer = EXFER(xfer); 3014 sc = epipe->pipe.device->bus->hci_private; 3015 3016 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3017 3018 if (sc->sc_dying) { 3019 s = splusb(); 3020 xfer->status = status; 3021 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3022 usb_transfer_complete(xfer); 3023 splx(s); 3024 return; 3025 } 3026 3027 if (xfer->hcflags & UXFER_ABORTING) { 3028 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3029 3030 #ifdef DIAGNOSTIC 3031 if (status == USBD_TIMEOUT) 3032 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3033 #endif 3034 3035 xfer->status = status; 3036 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3037 xfer->hcflags |= UXFER_ABORTWAIT; 3038 while (xfer->hcflags & UXFER_ABORTING) 3039 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0); 3040 return; 3041 } 3042 xfer->hcflags |= UXFER_ABORTING; 3043 3044 xfer->status = status; 3045 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3046 3047 s = splusb(); 3048 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3049 usb_syncmem(&itd->dma, 3050 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3051 sizeof(itd->itd.itd_ctl), 3052 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3053 3054 for (i = 0; i < 8; i++) { 3055 trans_status = le32toh(itd->itd.itd_ctl[i]); 3056 trans_status &= ~EHCI_ITD_ACTIVE; 3057 itd->itd.itd_ctl[i] = htole32(trans_status); 3058 } 3059 3060 usb_syncmem(&itd->dma, 3061 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3062 sizeof(itd->itd.itd_ctl), 3063 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3064 } 3065 splx(s); 3066 3067 s = splusb(); 3068 #ifdef USB_USE_SOFTINTR 3069 sc->sc_softwake = 1; 3070 #endif /* USB_USE_SOFTINTR */ 3071 usb_schedsoftintr(&sc->sc_bus); 3072 #ifdef USB_USE_SOFTINTR 3073 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3074 #endif /* USB_USE_SOFTINTR */ 3075 splx(s); 3076 3077 #ifdef DIAGNOSTIC 3078 exfer->isdone = 1; 3079 #endif 3080 wake = xfer->hcflags & UXFER_ABORTWAIT; 3081 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3082 usb_transfer_complete(xfer); 3083 if (wake) 3084 wakeup(&xfer->hcflags); 3085 3086 return; 3087 } 3088 3089 void 3090 ehci_timeout(void *addr) 3091 { 3092 struct ehci_xfer *exfer = addr; 3093 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3094 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3095 3096 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3097 #ifdef USB_DEBUG 3098 if (ehcidebug > 1) 3099 usbd_dump_pipe(exfer->xfer.pipe); 3100 #endif 3101 3102 if (sc->sc_dying) { 3103 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3104 return; 3105 } 3106 3107 /* Execute the abort in a process context. */ 3108 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3109 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3110 USB_TASKQ_HC); 3111 } 3112 3113 void 3114 ehci_timeout_task(void *addr) 3115 { 3116 usbd_xfer_handle xfer = addr; 3117 int s; 3118 3119 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3120 3121 s = splusb(); 3122 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3123 splx(s); 3124 } 3125 3126 /************************/ 3127 3128 Static usbd_status 3129 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3130 { 3131 usbd_status err; 3132 3133 /* Insert last in queue. */ 3134 err = usb_insert_transfer(xfer); 3135 if (err) 3136 return (err); 3137 3138 /* Pipe isn't running, start first */ 3139 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3140 } 3141 3142 Static usbd_status 3143 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3144 { 3145 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3146 usbd_status err; 3147 3148 if (sc->sc_dying) 3149 return (USBD_IOERROR); 3150 3151 #ifdef DIAGNOSTIC 3152 if (!(xfer->rqflags & URQ_REQUEST)) { 3153 /* XXX panic */ 3154 printf("ehci_device_ctrl_transfer: not a request\n"); 3155 return (USBD_INVAL); 3156 } 3157 #endif 3158 3159 err = ehci_device_request(xfer); 3160 if (err) 3161 return (err); 3162 3163 if (sc->sc_bus.use_polling) 3164 ehci_waitintr(sc, xfer); 3165 return (USBD_IN_PROGRESS); 3166 } 3167 3168 void 3169 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3170 { 3171 struct ehci_xfer *ex = EXFER(xfer); 3172 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3173 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3174 usb_device_request_t *req = &xfer->request; 3175 int len = UGETW(req->wLength); 3176 int rd = req->bmRequestType & UT_READ; 3177 3178 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3179 3180 #ifdef DIAGNOSTIC 3181 if (!(xfer->rqflags & URQ_REQUEST)) { 3182 panic("ehci_ctrl_done: not a request"); 3183 } 3184 #endif 3185 3186 mutex_enter(&sc->sc_intrhead_lock); 3187 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3188 ehci_del_intr_list(sc, ex); /* remove from active list */ 3189 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3190 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3191 BUS_DMASYNC_POSTWRITE); 3192 if (len) 3193 usb_syncmem(&xfer->dmabuf, 0, len, 3194 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3195 } 3196 mutex_exit(&sc->sc_intrhead_lock); 3197 3198 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3199 } 3200 3201 /* Abort a device control request. */ 3202 Static void 3203 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3204 { 3205 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3206 ehci_abort_xfer(xfer, USBD_CANCELLED); 3207 } 3208 3209 /* Close a device control pipe. */ 3210 Static void 3211 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3212 { 3213 ehci_softc_t *sc = pipe->device->bus->hci_private; 3214 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3215 3216 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3217 ehci_close_pipe(pipe, sc->sc_async_head); 3218 } 3219 3220 usbd_status 3221 ehci_device_request(usbd_xfer_handle xfer) 3222 { 3223 #define exfer EXFER(xfer) 3224 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3225 usb_device_request_t *req = &xfer->request; 3226 usbd_device_handle dev = epipe->pipe.device; 3227 ehci_softc_t *sc = dev->bus->hci_private; 3228 int addr = dev->address; 3229 ehci_soft_qtd_t *setup, *stat, *next; 3230 ehci_soft_qh_t *sqh; 3231 int isread; 3232 int len; 3233 usbd_status err; 3234 int s; 3235 3236 isread = req->bmRequestType & UT_READ; 3237 len = UGETW(req->wLength); 3238 3239 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3240 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3241 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3242 UGETW(req->wIndex), len, addr, 3243 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3244 3245 setup = ehci_alloc_sqtd(sc); 3246 if (setup == NULL) { 3247 err = USBD_NOMEM; 3248 goto bad1; 3249 } 3250 stat = ehci_alloc_sqtd(sc); 3251 if (stat == NULL) { 3252 err = USBD_NOMEM; 3253 goto bad2; 3254 } 3255 3256 sqh = epipe->sqh; 3257 epipe->u.ctl.length = len; 3258 3259 /* Update device address and length since they may have changed 3260 during the setup of the control pipe in usbd_new_device(). */ 3261 /* XXX This only needs to be done once, but it's too early in open. */ 3262 /* XXXX Should not touch ED here! */ 3263 sqh->qh.qh_endp = 3264 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3265 htole32( 3266 EHCI_QH_SET_ADDR(addr) | 3267 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3268 ); 3269 3270 /* Set up data transaction */ 3271 if (len != 0) { 3272 ehci_soft_qtd_t *end; 3273 3274 /* Start toggle at 1. */ 3275 epipe->nexttoggle = 1; 3276 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3277 &next, &end); 3278 if (err) 3279 goto bad3; 3280 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3281 end->nextqtd = stat; 3282 end->qtd.qtd_next = 3283 end->qtd.qtd_altnext = htole32(stat->physaddr); 3284 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3285 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3286 } else { 3287 next = stat; 3288 } 3289 3290 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3291 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3292 3293 /* Clear toggle */ 3294 setup->qtd.qtd_status = htole32( 3295 EHCI_QTD_ACTIVE | 3296 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3297 EHCI_QTD_SET_CERR(3) | 3298 EHCI_QTD_SET_TOGGLE(0) | 3299 EHCI_QTD_SET_BYTES(sizeof *req) 3300 ); 3301 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3302 setup->qtd.qtd_buffer_hi[0] = 0; 3303 setup->nextqtd = next; 3304 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3305 setup->xfer = xfer; 3306 setup->len = sizeof *req; 3307 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3308 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3309 3310 stat->qtd.qtd_status = htole32( 3311 EHCI_QTD_ACTIVE | 3312 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3313 EHCI_QTD_SET_CERR(3) | 3314 EHCI_QTD_SET_TOGGLE(1) | 3315 EHCI_QTD_IOC 3316 ); 3317 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3318 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3319 stat->nextqtd = NULL; 3320 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3321 stat->xfer = xfer; 3322 stat->len = 0; 3323 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3324 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3325 3326 #ifdef EHCI_DEBUG 3327 if (ehcidebug > 5) { 3328 DPRINTF(("ehci_device_request:\n")); 3329 ehci_dump_sqh(sqh); 3330 ehci_dump_sqtds(setup); 3331 } 3332 #endif 3333 3334 exfer->sqtdstart = setup; 3335 exfer->sqtdend = stat; 3336 #ifdef DIAGNOSTIC 3337 if (!exfer->isdone) { 3338 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3339 } 3340 exfer->isdone = 0; 3341 #endif 3342 3343 /* Insert qTD in QH list. */ 3344 s = splusb(); 3345 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3346 if (xfer->timeout && !sc->sc_bus.use_polling) { 3347 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3348 ehci_timeout, xfer); 3349 } 3350 mutex_enter(&sc->sc_intrhead_lock); 3351 ehci_add_intr_list(sc, exfer); 3352 mutex_exit(&sc->sc_intrhead_lock); 3353 xfer->status = USBD_IN_PROGRESS; 3354 splx(s); 3355 3356 #ifdef EHCI_DEBUG 3357 if (ehcidebug > 10) { 3358 DPRINTF(("ehci_device_request: status=%x\n", 3359 EOREAD4(sc, EHCI_USBSTS))); 3360 delay(10000); 3361 ehci_dump_regs(sc); 3362 ehci_dump_sqh(sc->sc_async_head); 3363 ehci_dump_sqh(sqh); 3364 ehci_dump_sqtds(setup); 3365 } 3366 #endif 3367 3368 return (USBD_NORMAL_COMPLETION); 3369 3370 bad3: 3371 ehci_free_sqtd(sc, stat); 3372 bad2: 3373 ehci_free_sqtd(sc, setup); 3374 bad1: 3375 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3376 xfer->status = err; 3377 usb_transfer_complete(xfer); 3378 return (err); 3379 #undef exfer 3380 } 3381 3382 /* 3383 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3384 * qTD status, or miss signalling occasionally under heavy load. If the host 3385 * machine is too fast, we we can miss transaction completion - when we scan 3386 * the active list the transaction still seems to be active. This generally 3387 * exhibits itself as a umass stall that never recovers. 3388 * 3389 * We work around this behaviour by setting up this callback after any softintr 3390 * that completes with transactions still pending, giving us another chance to 3391 * check for completion after the writeback has taken place. 3392 */ 3393 void 3394 ehci_intrlist_timeout(void *arg) 3395 { 3396 ehci_softc_t *sc = arg; 3397 int s = splusb(); 3398 3399 DPRINTF(("ehci_intrlist_timeout\n")); 3400 usb_schedsoftintr(&sc->sc_bus); 3401 3402 splx(s); 3403 } 3404 3405 /************************/ 3406 3407 Static usbd_status 3408 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3409 { 3410 usbd_status err; 3411 3412 /* Insert last in queue. */ 3413 err = usb_insert_transfer(xfer); 3414 if (err) 3415 return (err); 3416 3417 /* Pipe isn't running, start first */ 3418 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3419 } 3420 3421 usbd_status 3422 ehci_device_bulk_start(usbd_xfer_handle xfer) 3423 { 3424 #define exfer EXFER(xfer) 3425 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3426 usbd_device_handle dev = epipe->pipe.device; 3427 ehci_softc_t *sc = dev->bus->hci_private; 3428 ehci_soft_qtd_t *data, *dataend; 3429 ehci_soft_qh_t *sqh; 3430 usbd_status err; 3431 int len, isread, endpt; 3432 int s; 3433 3434 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3435 xfer, xfer->length, xfer->flags)); 3436 3437 if (sc->sc_dying) 3438 return (USBD_IOERROR); 3439 3440 #ifdef DIAGNOSTIC 3441 if (xfer->rqflags & URQ_REQUEST) 3442 panic("ehci_device_bulk_start: a request"); 3443 #endif 3444 3445 len = xfer->length; 3446 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3447 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3448 sqh = epipe->sqh; 3449 3450 epipe->u.bulk.length = len; 3451 3452 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3453 &dataend); 3454 if (err) { 3455 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3456 xfer->status = err; 3457 usb_transfer_complete(xfer); 3458 return (err); 3459 } 3460 3461 #ifdef EHCI_DEBUG 3462 if (ehcidebug > 5) { 3463 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3464 ehci_dump_sqh(sqh); 3465 ehci_dump_sqtds(data); 3466 } 3467 #endif 3468 3469 /* Set up interrupt info. */ 3470 exfer->sqtdstart = data; 3471 exfer->sqtdend = dataend; 3472 #ifdef DIAGNOSTIC 3473 if (!exfer->isdone) { 3474 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3475 } 3476 exfer->isdone = 0; 3477 #endif 3478 3479 s = splusb(); 3480 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3481 if (xfer->timeout && !sc->sc_bus.use_polling) { 3482 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3483 ehci_timeout, xfer); 3484 } 3485 mutex_enter(&sc->sc_intrhead_lock); 3486 ehci_add_intr_list(sc, exfer); 3487 mutex_exit(&sc->sc_intrhead_lock); 3488 xfer->status = USBD_IN_PROGRESS; 3489 splx(s); 3490 3491 #ifdef EHCI_DEBUG 3492 if (ehcidebug > 10) { 3493 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3494 delay(10000); 3495 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3496 ehci_dump_regs(sc); 3497 #if 0 3498 printf("async_head:\n"); 3499 ehci_dump_sqh(sc->sc_async_head); 3500 #endif 3501 printf("sqh:\n"); 3502 ehci_dump_sqh(sqh); 3503 ehci_dump_sqtds(data); 3504 } 3505 #endif 3506 3507 if (sc->sc_bus.use_polling) 3508 ehci_waitintr(sc, xfer); 3509 3510 return (USBD_IN_PROGRESS); 3511 #undef exfer 3512 } 3513 3514 Static void 3515 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3516 { 3517 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3518 ehci_abort_xfer(xfer, USBD_CANCELLED); 3519 } 3520 3521 /* 3522 * Close a device bulk pipe. 3523 */ 3524 Static void 3525 ehci_device_bulk_close(usbd_pipe_handle pipe) 3526 { 3527 ehci_softc_t *sc = pipe->device->bus->hci_private; 3528 3529 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3530 ehci_close_pipe(pipe, sc->sc_async_head); 3531 } 3532 3533 void 3534 ehci_device_bulk_done(usbd_xfer_handle xfer) 3535 { 3536 struct ehci_xfer *ex = EXFER(xfer); 3537 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3538 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3539 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3540 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3541 3542 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3543 xfer, xfer->actlen)); 3544 3545 mutex_enter(&sc->sc_intrhead_lock); 3546 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3547 ehci_del_intr_list(sc, ex); /* remove from active list */ 3548 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3549 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3550 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3551 } 3552 mutex_exit(&sc->sc_intrhead_lock); 3553 3554 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3555 } 3556 3557 /************************/ 3558 3559 Static usbd_status 3560 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3561 { 3562 struct ehci_soft_islot *isp; 3563 int islot, lev; 3564 3565 /* Find a poll rate that is large enough. */ 3566 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3567 if (EHCI_ILEV_IVAL(lev) <= ival) 3568 break; 3569 3570 /* Pick an interrupt slot at the right level. */ 3571 /* XXX could do better than picking at random */ 3572 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3573 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3574 3575 sqh->islot = islot; 3576 isp = &sc->sc_islots[islot]; 3577 ehci_add_qh(sqh, isp->sqh); 3578 3579 return (USBD_NORMAL_COMPLETION); 3580 } 3581 3582 Static usbd_status 3583 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3584 { 3585 usbd_status err; 3586 3587 /* Insert last in queue. */ 3588 err = usb_insert_transfer(xfer); 3589 if (err) 3590 return (err); 3591 3592 /* 3593 * Pipe isn't running (otherwise err would be USBD_INPROG), 3594 * so start it first. 3595 */ 3596 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3597 } 3598 3599 Static usbd_status 3600 ehci_device_intr_start(usbd_xfer_handle xfer) 3601 { 3602 #define exfer EXFER(xfer) 3603 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3604 usbd_device_handle dev = xfer->pipe->device; 3605 ehci_softc_t *sc = dev->bus->hci_private; 3606 ehci_soft_qtd_t *data, *dataend; 3607 ehci_soft_qh_t *sqh; 3608 usbd_status err; 3609 int len, isread, endpt; 3610 int s; 3611 3612 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3613 xfer, xfer->length, xfer->flags)); 3614 3615 if (sc->sc_dying) 3616 return (USBD_IOERROR); 3617 3618 #ifdef DIAGNOSTIC 3619 if (xfer->rqflags & URQ_REQUEST) 3620 panic("ehci_device_intr_start: a request"); 3621 #endif 3622 3623 len = xfer->length; 3624 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3625 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3626 sqh = epipe->sqh; 3627 3628 epipe->u.intr.length = len; 3629 3630 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3631 &dataend); 3632 if (err) { 3633 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3634 xfer->status = err; 3635 usb_transfer_complete(xfer); 3636 return (err); 3637 } 3638 3639 #ifdef EHCI_DEBUG 3640 if (ehcidebug > 5) { 3641 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3642 ehci_dump_sqh(sqh); 3643 ehci_dump_sqtds(data); 3644 } 3645 #endif 3646 3647 /* Set up interrupt info. */ 3648 exfer->sqtdstart = data; 3649 exfer->sqtdend = dataend; 3650 #ifdef DIAGNOSTIC 3651 if (!exfer->isdone) { 3652 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3653 } 3654 exfer->isdone = 0; 3655 #endif 3656 3657 s = splusb(); 3658 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3659 if (xfer->timeout && !sc->sc_bus.use_polling) { 3660 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3661 ehci_timeout, xfer); 3662 } 3663 mutex_enter(&sc->sc_intrhead_lock); 3664 ehci_add_intr_list(sc, exfer); 3665 mutex_exit(&sc->sc_intrhead_lock); 3666 xfer->status = USBD_IN_PROGRESS; 3667 splx(s); 3668 3669 #ifdef EHCI_DEBUG 3670 if (ehcidebug > 10) { 3671 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3672 delay(10000); 3673 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3674 ehci_dump_regs(sc); 3675 printf("sqh:\n"); 3676 ehci_dump_sqh(sqh); 3677 ehci_dump_sqtds(data); 3678 } 3679 #endif 3680 3681 if (sc->sc_bus.use_polling) 3682 ehci_waitintr(sc, xfer); 3683 3684 return (USBD_IN_PROGRESS); 3685 #undef exfer 3686 } 3687 3688 Static void 3689 ehci_device_intr_abort(usbd_xfer_handle xfer) 3690 { 3691 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3692 if (xfer->pipe->intrxfer == xfer) { 3693 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3694 xfer->pipe->intrxfer = NULL; 3695 } 3696 /* 3697 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3698 * async doorbell. That's dependant on the async list, wheras 3699 * intr xfers are periodic, should not use this? 3700 */ 3701 ehci_abort_xfer(xfer, USBD_CANCELLED); 3702 } 3703 3704 Static void 3705 ehci_device_intr_close(usbd_pipe_handle pipe) 3706 { 3707 ehci_softc_t *sc = pipe->device->bus->hci_private; 3708 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3709 struct ehci_soft_islot *isp; 3710 3711 isp = &sc->sc_islots[epipe->sqh->islot]; 3712 ehci_close_pipe(pipe, isp->sqh); 3713 } 3714 3715 Static void 3716 ehci_device_intr_done(usbd_xfer_handle xfer) 3717 { 3718 #define exfer EXFER(xfer) 3719 struct ehci_xfer *ex = EXFER(xfer); 3720 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3721 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3722 ehci_soft_qtd_t *data, *dataend; 3723 ehci_soft_qh_t *sqh; 3724 usbd_status err; 3725 int len, isread, endpt, s; 3726 3727 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3728 xfer, xfer->actlen)); 3729 3730 mutex_enter(&sc->sc_intrhead_lock); 3731 if (xfer->pipe->repeat) { 3732 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3733 3734 len = epipe->u.intr.length; 3735 xfer->length = len; 3736 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3737 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3738 usb_syncmem(&xfer->dmabuf, 0, len, 3739 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3740 sqh = epipe->sqh; 3741 3742 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3743 &data, &dataend); 3744 if (err) { 3745 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3746 xfer->status = err; 3747 mutex_exit(&sc->sc_intrhead_lock); 3748 return; 3749 } 3750 3751 /* Set up interrupt info. */ 3752 exfer->sqtdstart = data; 3753 exfer->sqtdend = dataend; 3754 #ifdef DIAGNOSTIC 3755 if (!exfer->isdone) { 3756 printf("ehci_device_intr_done: not done, ex=%p\n", 3757 exfer); 3758 } 3759 exfer->isdone = 0; 3760 #endif 3761 3762 s = splusb(); 3763 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3764 if (xfer->timeout && !sc->sc_bus.use_polling) { 3765 usb_callout(xfer->timeout_handle, 3766 mstohz(xfer->timeout), ehci_timeout, xfer); 3767 } 3768 splx(s); 3769 3770 xfer->status = USBD_IN_PROGRESS; 3771 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3772 ehci_del_intr_list(sc, ex); /* remove from active list */ 3773 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3774 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3775 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3776 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3777 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3778 } 3779 mutex_exit(&sc->sc_intrhead_lock); 3780 #undef exfer 3781 } 3782 3783 /************************/ 3784 3785 Static usbd_status 3786 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3787 { 3788 usbd_status err; 3789 3790 err = usb_insert_transfer(xfer); 3791 if (err && err != USBD_IN_PROGRESS) 3792 return err; 3793 3794 return ehci_device_isoc_start(xfer); 3795 } 3796 3797 Static usbd_status 3798 ehci_device_isoc_start(usbd_xfer_handle xfer) 3799 { 3800 struct ehci_pipe *epipe; 3801 usbd_device_handle dev; 3802 ehci_softc_t *sc; 3803 struct ehci_xfer *exfer; 3804 ehci_soft_itd_t *itd, *prev, *start, *stop; 3805 usb_dma_t *dma_buf; 3806 int i, j, k, frames, uframes, ufrperframe; 3807 int s, trans_count, offs, total_length; 3808 int frindex; 3809 3810 start = NULL; 3811 prev = NULL; 3812 itd = NULL; 3813 trans_count = 0; 3814 total_length = 0; 3815 exfer = (struct ehci_xfer *) xfer; 3816 sc = xfer->pipe->device->bus->hci_private; 3817 dev = xfer->pipe->device; 3818 epipe = (struct ehci_pipe *)xfer->pipe; 3819 3820 /* 3821 * To allow continuous transfers, above we start all transfers 3822 * immediately. However, we're still going to get usbd_start_next call 3823 * this when another xfer completes. So, check if this is already 3824 * in progress or not 3825 */ 3826 3827 if (exfer->itdstart != NULL) 3828 return USBD_IN_PROGRESS; 3829 3830 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3831 xfer, xfer->length, xfer->flags)); 3832 3833 if (sc->sc_dying) 3834 return USBD_IOERROR; 3835 3836 /* 3837 * To avoid complication, don't allow a request right now that'll span 3838 * the entire frame table. To within 4 frames, to allow some leeway 3839 * on either side of where the hc currently is. 3840 */ 3841 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3842 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3843 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3844 return USBD_INVAL; 3845 } 3846 3847 #ifdef DIAGNOSTIC 3848 if (xfer->rqflags & URQ_REQUEST) 3849 panic("ehci_device_isoc_start: request\n"); 3850 3851 if (!exfer->isdone) 3852 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3853 exfer->isdone = 0; 3854 #endif 3855 3856 /* 3857 * Step 1: Allocate and initialize itds, how many do we need? 3858 * One per transfer if interval >= 8 microframes, fewer if we use 3859 * multiple microframes per frame. 3860 */ 3861 3862 i = epipe->pipe.endpoint->edesc->bInterval; 3863 if (i > 16 || i == 0) { 3864 /* Spec page 271 says intervals > 16 are invalid */ 3865 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3866 return USBD_INVAL; 3867 } 3868 3869 switch (i) { 3870 case 1: 3871 ufrperframe = 8; 3872 break; 3873 case 2: 3874 ufrperframe = 4; 3875 break; 3876 case 3: 3877 ufrperframe = 2; 3878 break; 3879 default: 3880 ufrperframe = 1; 3881 break; 3882 } 3883 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3884 uframes = 8 / ufrperframe; 3885 3886 if (frames == 0) { 3887 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3888 return USBD_INVAL; 3889 } 3890 3891 dma_buf = &xfer->dmabuf; 3892 offs = 0; 3893 3894 for (i = 0; i < frames; i++) { 3895 int froffs = offs; 3896 itd = ehci_alloc_itd(sc); 3897 3898 if (prev != NULL) { 3899 prev->itd.itd_next = 3900 htole32(itd->physaddr | EHCI_LINK_ITD); 3901 usb_syncmem(&itd->dma, 3902 itd->offs + offsetof(ehci_itd_t, itd_next), 3903 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 3904 3905 prev->xfer_next = itd; 3906 } else { 3907 start = itd; 3908 } 3909 3910 /* 3911 * Step 1.5, initialize uframes 3912 */ 3913 for (j = 0; j < 8; j += uframes) { 3914 /* Calculate which page in the list this starts in */ 3915 int addr = DMAADDR(dma_buf, froffs); 3916 addr = EHCI_PAGE_OFFSET(addr); 3917 addr += (offs - froffs); 3918 addr = EHCI_PAGE(addr); 3919 addr /= EHCI_PAGE_SIZE; 3920 3921 /* This gets the initial offset into the first page, 3922 * looks how far further along the current uframe 3923 * offset is. Works out how many pages that is. 3924 */ 3925 3926 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3927 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3928 EHCI_ITD_SET_PG(addr) | 3929 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 3930 3931 total_length += xfer->frlengths[trans_count]; 3932 offs += xfer->frlengths[trans_count]; 3933 trans_count++; 3934 3935 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3936 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3937 break; 3938 } 3939 } 3940 3941 /* Step 1.75, set buffer pointers. To simplify matters, all 3942 * pointers are filled out for the next 7 hardware pages in 3943 * the dma block, so no need to worry what pages to cover 3944 * and what to not. 3945 */ 3946 3947 for (j=0; j < 7; j++) { 3948 /* 3949 * Don't try to lookup a page that's past the end 3950 * of buffer 3951 */ 3952 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 3953 if (page_offs >= dma_buf->block->size) 3954 break; 3955 3956 int page = DMAADDR(dma_buf, page_offs); 3957 page = EHCI_PAGE(page); 3958 itd->itd.itd_bufr[j] = 3959 htole32(EHCI_ITD_SET_BPTR(page) | 3960 EHCI_LINK_ITD); 3961 } 3962 3963 /* 3964 * Other special values 3965 */ 3966 3967 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3968 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3969 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3970 3971 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3972 ? 1 : 0; 3973 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3974 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3975 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3976 3977 /* FIXME: handle invalid trans */ 3978 itd->itd.itd_bufr[2] |= 3979 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3980 3981 usb_syncmem(&itd->dma, 3982 itd->offs + offsetof(ehci_itd_t, itd_next), 3983 sizeof(ehci_itd_t), 3984 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3985 3986 prev = itd; 3987 } /* End of frame */ 3988 3989 stop = itd; 3990 stop->xfer_next = NULL; 3991 exfer->isoc_len = total_length; 3992 3993 /* 3994 * Part 2: Transfer descriptors have now been set up, now they must 3995 * be scheduled into the period frame list. Erk. Not wanting to 3996 * complicate matters, transfer is denied if the transfer spans 3997 * more than the period frame list. 3998 */ 3999 4000 s = splusb(); 4001 4002 /* Start inserting frames */ 4003 if (epipe->u.isoc.cur_xfers > 0) { 4004 frindex = epipe->u.isoc.next_frame; 4005 } else { 4006 frindex = EOREAD4(sc, EHCI_FRINDEX); 4007 frindex = frindex >> 3; /* Erase microframe index */ 4008 frindex += 2; 4009 } 4010 4011 if (frindex >= sc->sc_flsize) 4012 frindex &= (sc->sc_flsize - 1); 4013 4014 /* Whats the frame interval? */ 4015 i = (1 << epipe->pipe.endpoint->edesc->bInterval); 4016 if (i / 8 == 0) 4017 i = 1; 4018 else 4019 i /= 8; 4020 4021 itd = start; 4022 for (j = 0; j < frames; j++) { 4023 if (itd == NULL) 4024 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4025 4026 itd->itd.itd_next = sc->sc_flist[frindex]; 4027 if (itd->itd.itd_next == 0) 4028 /* FIXME: frindex table gets initialized to NULL 4029 * or EHCI_NULL? */ 4030 itd->itd.itd_next = htole32(EHCI_NULL); 4031 4032 usb_syncmem(&itd->dma, 4033 itd->offs + offsetof(ehci_itd_t, itd_next), 4034 sizeof(itd->itd.itd_next), 4035 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4036 4037 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4038 4039 usb_syncmem(&sc->sc_fldma, 4040 sizeof(ehci_link_t) * frindex, 4041 sizeof(ehci_link_t), 4042 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4043 4044 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4045 sc->sc_softitds[frindex] = itd; 4046 if (itd->u.frame_list.next != NULL) 4047 itd->u.frame_list.next->u.frame_list.prev = itd; 4048 itd->slot = frindex; 4049 itd->u.frame_list.prev = NULL; 4050 4051 frindex += i; 4052 if (frindex >= sc->sc_flsize) 4053 frindex -= sc->sc_flsize; 4054 4055 itd = itd->xfer_next; 4056 } 4057 4058 epipe->u.isoc.cur_xfers++; 4059 epipe->u.isoc.next_frame = frindex; 4060 4061 exfer->itdstart = start; 4062 exfer->itdend = stop; 4063 exfer->sqtdstart = NULL; 4064 exfer->sqtdstart = NULL; 4065 4066 mutex_enter(&sc->sc_intrhead_lock); 4067 ehci_add_intr_list(sc, exfer); 4068 mutex_exit(&sc->sc_intrhead_lock); 4069 xfer->status = USBD_IN_PROGRESS; 4070 xfer->done = 0; 4071 splx(s); 4072 4073 if (sc->sc_bus.use_polling) { 4074 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4075 ehci_waitintr(sc, xfer); 4076 } 4077 4078 return USBD_IN_PROGRESS; 4079 } 4080 4081 Static void 4082 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4083 { 4084 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4085 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4086 } 4087 4088 Static void 4089 ehci_device_isoc_close(usbd_pipe_handle pipe) 4090 { 4091 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4092 } 4093 4094 Static void 4095 ehci_device_isoc_done(usbd_xfer_handle xfer) 4096 { 4097 struct ehci_xfer *exfer; 4098 ehci_softc_t *sc; 4099 struct ehci_pipe *epipe; 4100 int s; 4101 4102 exfer = EXFER(xfer); 4103 sc = xfer->pipe->device->bus->hci_private; 4104 epipe = (struct ehci_pipe *) xfer->pipe; 4105 4106 s = splusb(); 4107 epipe->u.isoc.cur_xfers--; 4108 mutex_enter(&sc->sc_intrhead_lock); 4109 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4110 ehci_del_intr_list(sc, exfer); 4111 ehci_rem_free_itd_chain(sc, exfer); 4112 } 4113 mutex_exit(&sc->sc_intrhead_lock); 4114 splx(s); 4115 4116 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4117 BUS_DMASYNC_POSTREAD); 4118 4119 } 4120
Indexes created Wed Oct 01 19:09:53 GMT 2025