ehci.c revision 1.139
1 /* $NetBSD: ehci.c,v 1.139 2008/08/02 22:23:18 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2004,2005 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net) and by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 34 * 35 * The EHCI 1.0 spec can be found at 36 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 37 * and the USB 2.0 spec at 38 * http://www.usb.org/developers/docs/usb_20.zip 39 * 40 */ 41 42 /* 43 * TODO: 44 * 1) hold off explorations by companion controllers until ehci has started. 45 * 46 * 2) The EHCI driver lacks support for isochronous transfers, so 47 * devices using them don't work. 48 * 49 * 3) The hub driver needs to handle and schedule the transaction translator, 50 * to assign place in frame where different devices get to go. See chapter 51 * on hubs in USB 2.0 for details. 52 * 53 * 4) command failures are not recovered correctly 54 */ 55 56 #include <sys/cdefs.h> 57 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.139 2008/08/02 22:23:18 jmcneill Exp $"); 58 59 #include "ohci.h" 60 #include "uhci.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/malloc.h> 66 #include <sys/device.h> 67 #include <sys/select.h> 68 #include <sys/proc.h> 69 #include <sys/queue.h> 70 #include <sys/mutex.h> 71 #include <sys/bus.h> 72 73 #include <machine/endian.h> 74 75 #include <dev/usb/usb.h> 76 #include <dev/usb/usbdi.h> 77 #include <dev/usb/usbdivar.h> 78 #include <dev/usb/usb_mem.h> 79 #include <dev/usb/usb_quirks.h> 80 81 #include <dev/usb/ehcireg.h> 82 #include <dev/usb/ehcivar.h> 83 #include <dev/usb/usbroothub_subr.h> 84 85 #ifdef EHCI_DEBUG 86 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 87 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 88 int ehcidebug = 0; 89 #ifndef __NetBSD__ 90 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 91 #endif 92 #else 93 #define DPRINTF(x) 94 #define DPRINTFN(n,x) 95 #endif 96 97 struct ehci_pipe { 98 struct usbd_pipe pipe; 99 int nexttoggle; 100 101 ehci_soft_qh_t *sqh; 102 union { 103 ehci_soft_qtd_t *qtd; 104 /* ehci_soft_itd_t *itd; */ 105 } tail; 106 union { 107 /* Control pipe */ 108 struct { 109 usb_dma_t reqdma; 110 u_int length; 111 } ctl; 112 /* Interrupt pipe */ 113 struct { 114 u_int length; 115 } intr; 116 /* Bulk pipe */ 117 struct { 118 u_int length; 119 } bulk; 120 /* Iso pipe */ 121 struct { 122 u_int next_frame; 123 u_int cur_xfers; 124 } isoc; 125 } u; 126 }; 127 128 Static usbd_status ehci_open(usbd_pipe_handle); 129 Static void ehci_poll(struct usbd_bus *); 130 Static void ehci_softintr(void *); 131 Static int ehci_intr1(ehci_softc_t *); 132 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 133 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 134 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 135 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 136 Static void ehci_idone(struct ehci_xfer *); 137 Static void ehci_timeout(void *); 138 Static void ehci_timeout_task(void *); 139 Static void ehci_intrlist_timeout(void *); 140 141 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 142 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 143 144 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 145 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 146 147 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 148 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 149 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 150 Static void ehci_root_ctrl_close(usbd_pipe_handle); 151 Static void ehci_root_ctrl_done(usbd_xfer_handle); 152 153 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 154 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 155 Static void ehci_root_intr_abort(usbd_xfer_handle); 156 Static void ehci_root_intr_close(usbd_pipe_handle); 157 Static void ehci_root_intr_done(usbd_xfer_handle); 158 159 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 160 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 161 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 162 Static void ehci_device_ctrl_close(usbd_pipe_handle); 163 Static void ehci_device_ctrl_done(usbd_xfer_handle); 164 165 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 166 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 167 Static void ehci_device_bulk_abort(usbd_xfer_handle); 168 Static void ehci_device_bulk_close(usbd_pipe_handle); 169 Static void ehci_device_bulk_done(usbd_xfer_handle); 170 171 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 172 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 173 Static void ehci_device_intr_abort(usbd_xfer_handle); 174 Static void ehci_device_intr_close(usbd_pipe_handle); 175 Static void ehci_device_intr_done(usbd_xfer_handle); 176 177 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 178 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 179 Static void ehci_device_isoc_abort(usbd_xfer_handle); 180 Static void ehci_device_isoc_close(usbd_pipe_handle); 181 Static void ehci_device_isoc_done(usbd_xfer_handle); 182 183 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 184 Static void ehci_noop(usbd_pipe_handle pipe); 185 186 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 187 Static void ehci_disown(ehci_softc_t *, int, int); 188 189 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 190 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 191 192 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 193 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 194 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 195 ehci_softc_t *, int, int, usbd_xfer_handle, 196 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 197 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 198 ehci_soft_qtd_t *); 199 200 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 201 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 202 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 203 struct ehci_xfer *exfer); 204 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 205 usbd_status status); 206 207 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 208 209 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 210 int ival); 211 212 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 213 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 214 ehci_soft_qh_t *); 215 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 216 Static void ehci_sync_hc(ehci_softc_t *); 217 218 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 219 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 220 221 #ifdef EHCI_DEBUG 222 Static void ehci_dump_regs(ehci_softc_t *); 223 void ehci_dump(void); 224 Static ehci_softc_t *theehci; 225 Static void ehci_dump_link(ehci_link_t, int); 226 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 227 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 228 Static void ehci_dump_qtd(ehci_qtd_t *); 229 Static void ehci_dump_sqh(ehci_soft_qh_t *); 230 #if notyet 231 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 232 Static void ehci_dump_itd(struct ehci_soft_itd *); 233 Static void ehci_dump_exfer(struct ehci_xfer *); 234 #endif 235 #ifdef DIAGNOSTIC 236 #endif 237 #endif 238 239 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 240 241 #define EHCI_INTR_ENDPT 1 242 243 #define ehci_add_intr_list(sc, ex) \ 244 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext); 245 #define ehci_del_intr_list(ex) \ 246 do { \ 247 LIST_REMOVE((ex), inext); \ 248 (ex)->inext.le_prev = NULL; \ 249 } while (0) 250 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL) 251 252 Static const struct usbd_bus_methods ehci_bus_methods = { 253 ehci_open, 254 ehci_softintr, 255 ehci_poll, 256 ehci_allocm, 257 ehci_freem, 258 ehci_allocx, 259 ehci_freex, 260 }; 261 262 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 263 ehci_root_ctrl_transfer, 264 ehci_root_ctrl_start, 265 ehci_root_ctrl_abort, 266 ehci_root_ctrl_close, 267 ehci_noop, 268 ehci_root_ctrl_done, 269 }; 270 271 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 272 ehci_root_intr_transfer, 273 ehci_root_intr_start, 274 ehci_root_intr_abort, 275 ehci_root_intr_close, 276 ehci_noop, 277 ehci_root_intr_done, 278 }; 279 280 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 281 ehci_device_ctrl_transfer, 282 ehci_device_ctrl_start, 283 ehci_device_ctrl_abort, 284 ehci_device_ctrl_close, 285 ehci_noop, 286 ehci_device_ctrl_done, 287 }; 288 289 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 290 ehci_device_intr_transfer, 291 ehci_device_intr_start, 292 ehci_device_intr_abort, 293 ehci_device_intr_close, 294 ehci_device_clear_toggle, 295 ehci_device_intr_done, 296 }; 297 298 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 299 ehci_device_bulk_transfer, 300 ehci_device_bulk_start, 301 ehci_device_bulk_abort, 302 ehci_device_bulk_close, 303 ehci_device_clear_toggle, 304 ehci_device_bulk_done, 305 }; 306 307 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 308 ehci_device_isoc_transfer, 309 ehci_device_isoc_start, 310 ehci_device_isoc_abort, 311 ehci_device_isoc_close, 312 ehci_noop, 313 ehci_device_isoc_done, 314 }; 315 316 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 317 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 318 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 319 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 320 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 321 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 322 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 323 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 324 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 325 }; 326 327 usbd_status 328 ehci_init(ehci_softc_t *sc) 329 { 330 u_int32_t vers, sparams, cparams, hcr; 331 u_int i; 332 usbd_status err; 333 ehci_soft_qh_t *sqh; 334 u_int ncomp; 335 336 DPRINTF(("ehci_init: start\n")); 337 #ifdef EHCI_DEBUG 338 theehci = sc; 339 #endif 340 341 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 342 343 vers = EREAD2(sc, EHCI_HCIVERSION); 344 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 345 vers >> 8, vers & 0xff); 346 347 sparams = EREAD4(sc, EHCI_HCSPARAMS); 348 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 349 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 350 ncomp = EHCI_HCS_N_CC(sparams); 351 if (ncomp != sc->sc_ncomp) { 352 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 353 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 354 #if NOHCI == 0 || NUHCI == 0 355 aprint_error("%s: ohci or uhci probably not configured\n", 356 device_xname(sc->sc_dev)); 357 #endif 358 if (ncomp < sc->sc_ncomp) 359 sc->sc_ncomp = ncomp; 360 } 361 if (sc->sc_ncomp > 0) { 362 aprint_normal("%s: companion controller%s, %d port%s each:", 363 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 364 EHCI_HCS_N_PCC(sparams), 365 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 366 for (i = 0; i < sc->sc_ncomp; i++) 367 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 368 aprint_normal("\n"); 369 } 370 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 371 cparams = EREAD4(sc, EHCI_HCCPARAMS); 372 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 373 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 374 375 if (EHCI_HCC_64BIT(cparams)) { 376 /* MUST clear segment register if 64 bit capable. */ 377 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 378 } 379 380 sc->sc_bus.usbrev = USBREV_2_0; 381 382 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 383 USB_MEM_RESERVE); 384 385 /* Reset the controller */ 386 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 387 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 388 usb_delay_ms(&sc->sc_bus, 1); 389 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 390 for (i = 0; i < 100; i++) { 391 usb_delay_ms(&sc->sc_bus, 1); 392 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 393 if (!hcr) 394 break; 395 } 396 if (hcr) { 397 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 398 return (USBD_IOERROR); 399 } 400 401 /* XXX need proper intr scheduling */ 402 sc->sc_rand = 96; 403 404 /* frame list size at default, read back what we got and use that */ 405 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 406 case 0: sc->sc_flsize = 1024; break; 407 case 1: sc->sc_flsize = 512; break; 408 case 2: sc->sc_flsize = 256; break; 409 case 3: return (USBD_IOERROR); 410 } 411 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 412 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 413 if (err) 414 return (err); 415 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 416 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 417 418 for (i = 0; i < sc->sc_flsize; i++) { 419 sc->sc_flist[i] = EHCI_NULL; 420 } 421 422 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 423 424 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 425 M_USB, M_WAITOK | M_ZERO); 426 if (sc->sc_softitds == NULL) 427 return ENOMEM; 428 LIST_INIT(&sc->sc_freeitds); 429 430 /* Set up the bus struct. */ 431 sc->sc_bus.methods = &ehci_bus_methods; 432 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 433 434 sc->sc_eintrs = EHCI_NORMAL_INTRS; 435 436 /* 437 * Allocate the interrupt dummy QHs. These are arranged to give poll 438 * intervals that are powers of 2 times 1ms. 439 */ 440 for (i = 0; i < EHCI_INTRQHS; i++) { 441 sqh = ehci_alloc_sqh(sc); 442 if (sqh == NULL) { 443 err = USBD_NOMEM; 444 goto bad1; 445 } 446 sc->sc_islots[i].sqh = sqh; 447 } 448 for (i = 0; i < EHCI_INTRQHS; i++) { 449 sqh = sc->sc_islots[i].sqh; 450 if (i == 0) { 451 /* The last (1ms) QH terminates. */ 452 sqh->qh.qh_link = EHCI_NULL; 453 sqh->next = NULL; 454 } else { 455 /* Otherwise the next QH has half the poll interval */ 456 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 457 sqh->qh.qh_link = htole32(sqh->next->physaddr | 458 EHCI_LINK_QH); 459 } 460 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 461 sqh->qh.qh_curqtd = EHCI_NULL; 462 sqh->next = NULL; 463 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 464 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 465 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 466 sqh->sqtd = NULL; 467 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 468 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 469 } 470 /* Point the frame list at the last level (128ms). */ 471 for (i = 0; i < sc->sc_flsize; i++) { 472 int j; 473 474 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 475 revbits[i & (EHCI_MAX_POLLRATE-1)]; 476 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 477 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 478 i)].sqh->physaddr); 479 } 480 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 481 BUS_DMASYNC_PREWRITE); 482 483 /* Allocate dummy QH that starts the async list. */ 484 sqh = ehci_alloc_sqh(sc); 485 if (sqh == NULL) { 486 err = USBD_NOMEM; 487 goto bad1; 488 } 489 /* Fill the QH */ 490 sqh->qh.qh_endp = 491 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 492 sqh->qh.qh_link = 493 htole32(sqh->physaddr | EHCI_LINK_QH); 494 sqh->qh.qh_curqtd = EHCI_NULL; 495 sqh->next = NULL; 496 /* Fill the overlay qTD */ 497 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 498 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 499 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 500 sqh->sqtd = NULL; 501 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 502 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 503 #ifdef EHCI_DEBUG 504 if (ehcidebug) { 505 ehci_dump_sqh(sqh); 506 } 507 #endif 508 509 /* Point to async list */ 510 sc->sc_async_head = sqh; 511 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 512 513 usb_callout_init(sc->sc_tmo_intrlist); 514 515 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE); 516 517 /* Turn on controller */ 518 EOWRITE4(sc, EHCI_USBCMD, 519 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 520 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 521 EHCI_CMD_ASE | 522 EHCI_CMD_PSE | 523 EHCI_CMD_RS); 524 525 /* Take over port ownership */ 526 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 527 528 for (i = 0; i < 100; i++) { 529 usb_delay_ms(&sc->sc_bus, 1); 530 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 531 if (!hcr) 532 break; 533 } 534 if (hcr) { 535 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 536 return (USBD_IOERROR); 537 } 538 539 /* Enable interrupts */ 540 DPRINTFN(1,("ehci_init: enabling\n")); 541 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 542 543 return (USBD_NORMAL_COMPLETION); 544 545 #if 0 546 bad2: 547 ehci_free_sqh(sc, sc->sc_async_head); 548 #endif 549 bad1: 550 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 551 return (err); 552 } 553 554 int 555 ehci_intr(void *v) 556 { 557 ehci_softc_t *sc = v; 558 559 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 560 return (0); 561 562 /* If we get an interrupt while polling, then just ignore it. */ 563 if (sc->sc_bus.use_polling) { 564 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 565 566 if (intrs) 567 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 568 #ifdef DIAGNOSTIC 569 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 570 #endif 571 return (0); 572 } 573 574 return (ehci_intr1(sc)); 575 } 576 577 Static int 578 ehci_intr1(ehci_softc_t *sc) 579 { 580 u_int32_t intrs, eintrs; 581 582 DPRINTFN(20,("ehci_intr1: enter\n")); 583 584 /* In case the interrupt occurs before initialization has completed. */ 585 if (sc == NULL) { 586 #ifdef DIAGNOSTIC 587 printf("ehci_intr1: sc == NULL\n"); 588 #endif 589 return (0); 590 } 591 592 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 593 if (!intrs) 594 return (0); 595 596 eintrs = intrs & sc->sc_eintrs; 597 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 598 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 599 (u_int)eintrs)); 600 if (!eintrs) 601 return (0); 602 603 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 604 sc->sc_bus.intr_context++; 605 sc->sc_bus.no_intrs++; 606 if (eintrs & EHCI_STS_IAA) { 607 DPRINTF(("ehci_intr1: door bell\n")); 608 wakeup(&sc->sc_async_head); 609 eintrs &= ~EHCI_STS_IAA; 610 } 611 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 612 DPRINTFN(5,("ehci_intr1: %s %s\n", 613 eintrs & EHCI_STS_INT ? "INT" : "", 614 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 615 usb_schedsoftintr(&sc->sc_bus); 616 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 617 } 618 if (eintrs & EHCI_STS_HSE) { 619 printf("%s: unrecoverable error, controller halted\n", 620 device_xname(sc->sc_dev)); 621 /* XXX what else */ 622 } 623 if (eintrs & EHCI_STS_PCD) { 624 ehci_pcd(sc, sc->sc_intrxfer); 625 eintrs &= ~EHCI_STS_PCD; 626 } 627 628 sc->sc_bus.intr_context--; 629 630 if (eintrs != 0) { 631 /* Block unprocessed interrupts. */ 632 sc->sc_eintrs &= ~eintrs; 633 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 634 printf("%s: blocking intrs 0x%x\n", 635 device_xname(sc->sc_dev), eintrs); 636 } 637 638 return (1); 639 } 640 641 642 void 643 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 644 { 645 usbd_pipe_handle pipe; 646 u_char *p; 647 int i, m; 648 649 if (xfer == NULL) { 650 /* Just ignore the change. */ 651 return; 652 } 653 654 pipe = xfer->pipe; 655 656 p = KERNADDR(&xfer->dmabuf, 0); 657 m = min(sc->sc_noport, xfer->length * 8 - 1); 658 memset(p, 0, xfer->length); 659 for (i = 1; i <= m; i++) { 660 /* Pick out CHANGE bits from the status reg. */ 661 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 662 p[i/8] |= 1 << (i%8); 663 } 664 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 665 xfer->actlen = xfer->length; 666 xfer->status = USBD_NORMAL_COMPLETION; 667 668 usb_transfer_complete(xfer); 669 } 670 671 void 672 ehci_softintr(void *v) 673 { 674 struct usbd_bus *bus = v; 675 ehci_softc_t *sc = bus->hci_private; 676 struct ehci_xfer *ex, *nextex; 677 678 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 679 sc->sc_bus.intr_context)); 680 681 sc->sc_bus.intr_context++; 682 683 /* 684 * The only explanation I can think of for why EHCI is as brain dead 685 * as UHCI interrupt-wise is that Intel was involved in both. 686 * An interrupt just tells us that something is done, we have no 687 * clue what, so we need to scan through all active transfers. :-( 688 */ 689 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 690 nextex = LIST_NEXT(ex, inext); 691 ehci_check_intr(sc, ex); 692 } 693 694 /* Schedule a callout to catch any dropped transactions. */ 695 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 696 !LIST_EMPTY(&sc->sc_intrhead)) 697 usb_callout(sc->sc_tmo_intrlist, hz, 698 ehci_intrlist_timeout, sc); 699 700 #ifdef USB_USE_SOFTINTR 701 if (sc->sc_softwake) { 702 sc->sc_softwake = 0; 703 wakeup(&sc->sc_softwake); 704 } 705 #endif /* USB_USE_SOFTINTR */ 706 707 sc->sc_bus.intr_context--; 708 } 709 710 /* Check for an interrupt. */ 711 void 712 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 713 { 714 int attr; 715 716 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 717 718 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 719 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 720 ehci_check_itd_intr(sc, ex); 721 else 722 ehci_check_qh_intr(sc, ex); 723 724 return; 725 } 726 727 void 728 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 729 { 730 ehci_soft_qtd_t *sqtd, *lsqtd; 731 __uint32_t status; 732 733 if (ex->sqtdstart == NULL) { 734 printf("ehci_check_qh_intr: not valid sqtd\n"); 735 return; 736 } 737 738 lsqtd = ex->sqtdend; 739 #ifdef DIAGNOSTIC 740 if (lsqtd == NULL) { 741 printf("ehci_check_qh_intr: lsqtd==0\n"); 742 return; 743 } 744 #endif 745 /* 746 * If the last TD is still active we need to check whether there 747 * is a an error somewhere in the middle, or whether there was a 748 * short packet (SPD and not ACTIVE). 749 */ 750 usb_syncmem(&lsqtd->dma, 751 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 752 sizeof(lsqtd->qtd.qtd_status), 753 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 754 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 755 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 756 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 757 usb_syncmem(&sqtd->dma, 758 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 759 sizeof(sqtd->qtd.qtd_status), 760 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 761 status = le32toh(sqtd->qtd.qtd_status); 762 usb_syncmem(&sqtd->dma, 763 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 764 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 765 /* If there's an active QTD the xfer isn't done. */ 766 if (status & EHCI_QTD_ACTIVE) 767 break; 768 /* Any kind of error makes the xfer done. */ 769 if (status & EHCI_QTD_HALTED) 770 goto done; 771 /* We want short packets, and it is short: it's done */ 772 if (EHCI_QTD_GET_BYTES(status) != 0) 773 goto done; 774 } 775 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 776 ex, ex->sqtdstart)); 777 usb_syncmem(&lsqtd->dma, 778 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 779 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 780 return; 781 } 782 done: 783 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 784 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 785 ehci_idone(ex); 786 } 787 788 void 789 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 790 ehci_soft_itd_t *itd; 791 int i; 792 793 if (ex->itdstart == NULL) { 794 printf("ehci_check_itd_intr: not valid itd\n"); 795 return; 796 } 797 798 itd = ex->itdend; 799 #ifdef DIAGNOSTIC 800 if (itd == NULL) { 801 printf("ehci_check_itd_intr: itdend == 0\n"); 802 return; 803 } 804 #endif 805 806 /* 807 * Step 1, check no active transfers in last itd, meaning we're finished 808 */ 809 810 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 811 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 812 BUS_DMASYNC_POSTREAD); 813 814 for (i = 0; i < 8; i++) { 815 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 816 break; 817 } 818 819 if (i == 8) { 820 goto done; /* All 8 descriptors inactive, it's done */ 821 } 822 823 /* 824 * Step 2, check for errors in status bits, throughout chain... 825 */ 826 827 DPRINTFN(12, ("ehci_check_itd_intr: active ex=%p\n", ex)); 828 829 for (itd = ex->itdstart; itd != ex->itdend; itd = itd->xfer_next) { 830 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 831 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 832 BUS_DMASYNC_POSTREAD); 833 834 for (i = 0; i < 8; i++) { 835 if (le32toh(itd->itd.itd_ctl[i]) & (EHCI_ITD_BUF_ERR | 836 EHCI_ITD_BABBLE | EHCI_ITD_ERROR)) 837 break; 838 } 839 if (i != 8) { /* Error in one of the itds */ 840 goto done; 841 } 842 } /* itd search loop */ 843 844 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 845 ex->itdstart)); 846 return; 847 848 done: 849 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 850 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 851 ehci_idone(ex); 852 } 853 854 void 855 ehci_idone(struct ehci_xfer *ex) 856 { 857 usbd_xfer_handle xfer = &ex->xfer; 858 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 859 ehci_soft_qtd_t *sqtd, *lsqtd; 860 u_int32_t status = 0, nstatus = 0; 861 int actlen; 862 863 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 864 #ifdef DIAGNOSTIC 865 { 866 int s = splhigh(); 867 if (ex->isdone) { 868 splx(s); 869 #ifdef EHCI_DEBUG 870 printf("ehci_idone: ex is done!\n "); 871 ehci_dump_exfer(ex); 872 #else 873 printf("ehci_idone: ex=%p is done!\n", ex); 874 #endif 875 return; 876 } 877 ex->isdone = 1; 878 splx(s); 879 } 880 #endif 881 if (xfer->status == USBD_CANCELLED || 882 xfer->status == USBD_TIMEOUT) { 883 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 884 return; 885 } 886 887 #ifdef EHCI_DEBUG 888 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 889 if (ehcidebug > 10) 890 ehci_dump_sqtds(ex->sqtdstart); 891 #endif 892 893 /* The transfer is done, compute actual length and status. */ 894 895 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 896 == UE_ISOCHRONOUS) { 897 /* Isoc transfer */ 898 struct ehci_soft_itd *itd; 899 int i, nframes, len, uframes; 900 901 nframes = 0; 902 actlen = 0; 903 904 switch (xfer->pipe->endpoint->edesc->bInterval) { 905 case 0: 906 panic("ehci: isoc xfer suddenly has 0 bInterval, invalid\n"); 907 case 1: uframes = 1; break; 908 case 2: uframes = 2; break; 909 case 3: uframes = 4; break; 910 default: uframes = 8; break; 911 } 912 913 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 914 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 915 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 916 BUS_DMASYNC_POSTREAD); 917 918 for (i = 0; i < 8; i += uframes) { 919 /* XXX - driver didn't fill in the frame full 920 * of uframes. This leads to scheduling 921 * inefficiencies, but working around 922 * this doubles complexity of tracking 923 * an xfer. 924 */ 925 if (nframes >= xfer->nframes) 926 break; 927 928 status = le32toh(itd->itd.itd_ctl[i]); 929 len = EHCI_ITD_GET_LEN(status); 930 xfer->frlengths[nframes++] = len; 931 actlen += len; 932 } 933 934 if (nframes >= xfer->nframes) 935 break; 936 } 937 938 xfer->actlen = actlen; 939 xfer->status = USBD_NORMAL_COMPLETION; 940 if (xfer->rqflags & URQ_DEV_DMABUF) { 941 usb_syncmem(&xfer->dmabuf, 0, ex->isoc_len, 942 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 943 } 944 945 goto end; 946 } 947 948 /* Continue processing xfers using queue heads */ 949 950 lsqtd = ex->sqtdend; 951 actlen = 0; 952 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 953 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 954 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 955 nstatus = le32toh(sqtd->qtd.qtd_status); 956 if (nstatus & EHCI_QTD_ACTIVE) 957 break; 958 959 status = nstatus; 960 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 961 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 962 } 963 964 965 /* 966 * If there are left over TDs we need to update the toggle. 967 * The default pipe doesn't need it since control transfers 968 * start the toggle at 0 every time. 969 * For a short transfer we need to update the toggle for the missing 970 * packets within the qTD. 971 */ 972 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 973 xfer->pipe->device->default_pipe != xfer->pipe) { 974 DPRINTFN(2, ("ehci_idone: need toggle update " 975 "status=%08x nstatus=%08x\n", status, nstatus)); 976 #if 0 977 ehci_dump_sqh(epipe->sqh); 978 ehci_dump_sqtds(ex->sqtdstart); 979 #endif 980 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 981 } 982 983 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 984 xfer->length, actlen, status)); 985 xfer->actlen = actlen; 986 if (status & EHCI_QTD_HALTED) { 987 #ifdef EHCI_DEBUG 988 char sbuf[128]; 989 990 bitmask_snprintf((u_int32_t)status, 991 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 992 "\3MISSED\1PINGSTATE", sbuf, sizeof(sbuf)); 993 994 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 995 "status 0x%s\n", 996 xfer->pipe->device->address, 997 xfer->pipe->endpoint->edesc->bEndpointAddress, 998 sbuf)); 999 if (ehcidebug > 2) { 1000 ehci_dump_sqh(epipe->sqh); 1001 ehci_dump_sqtds(ex->sqtdstart); 1002 } 1003 #endif 1004 /* low&full speed has an extra error flag */ 1005 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1006 EHCI_QH_SPEED_HIGH) 1007 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1008 else 1009 status &= EHCI_QTD_STATERRS; 1010 if (status == 0) /* no other errors means a stall */ { 1011 xfer->status = USBD_STALLED; 1012 } else { 1013 xfer->status = USBD_IOERROR; /* more info XXX */ 1014 } 1015 /* XXX need to reset TT on missed microframe */ 1016 if (status & EHCI_QTD_MISSEDMICRO) { 1017 ehci_softc_t *sc = 1018 xfer->pipe->device->bus->hci_private; 1019 1020 printf("%s: missed microframe, TT reset not " 1021 "implemented, hub might be inoperational\n", 1022 device_xname(sc->sc_dev)); 1023 } 1024 } else { 1025 xfer->status = USBD_NORMAL_COMPLETION; 1026 } 1027 1028 end: 1029 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1030 * during this call, before methods->done is called: dma sync required 1031 * beforehand? */ 1032 usb_transfer_complete(xfer); 1033 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1034 } 1035 1036 /* 1037 * Wait here until controller claims to have an interrupt. 1038 * Then call ehci_intr and return. Use timeout to avoid waiting 1039 * too long. 1040 */ 1041 void 1042 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1043 { 1044 int timo; 1045 u_int32_t intrs; 1046 1047 xfer->status = USBD_IN_PROGRESS; 1048 for (timo = xfer->timeout; timo >= 0; timo--) { 1049 usb_delay_ms(&sc->sc_bus, 1); 1050 if (sc->sc_dying) 1051 break; 1052 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1053 sc->sc_eintrs; 1054 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1055 #ifdef EHCI_DEBUG 1056 if (ehcidebug > 15) 1057 ehci_dump_regs(sc); 1058 #endif 1059 if (intrs) { 1060 ehci_intr1(sc); 1061 if (xfer->status != USBD_IN_PROGRESS) 1062 return; 1063 } 1064 } 1065 1066 /* Timeout */ 1067 DPRINTF(("ehci_waitintr: timeout\n")); 1068 xfer->status = USBD_TIMEOUT; 1069 usb_transfer_complete(xfer); 1070 /* XXX should free TD */ 1071 } 1072 1073 void 1074 ehci_poll(struct usbd_bus *bus) 1075 { 1076 ehci_softc_t *sc = bus->hci_private; 1077 #ifdef EHCI_DEBUG 1078 static int last; 1079 int new; 1080 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1081 if (new != last) { 1082 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1083 last = new; 1084 } 1085 #endif 1086 1087 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1088 ehci_intr1(sc); 1089 } 1090 1091 void 1092 ehci_childdet(device_t self, device_t child) 1093 { 1094 struct ehci_softc *sc = device_private(self); 1095 1096 KASSERT(sc->sc_child == child); 1097 sc->sc_child = NULL; 1098 } 1099 1100 int 1101 ehci_detach(struct ehci_softc *sc, int flags) 1102 { 1103 int rv = 0; 1104 1105 if (sc->sc_child != NULL) 1106 rv = config_detach(sc->sc_child, flags); 1107 1108 if (rv != 0) 1109 return (rv); 1110 1111 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 1112 1113 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1114 1115 /* XXX free other data structures XXX */ 1116 mutex_destroy(&sc->sc_doorbell_lock); 1117 1118 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1119 1120 return (rv); 1121 } 1122 1123 1124 int 1125 ehci_activate(device_t self, enum devact act) 1126 { 1127 struct ehci_softc *sc = device_private(self); 1128 int rv = 0; 1129 1130 switch (act) { 1131 case DVACT_ACTIVATE: 1132 return (EOPNOTSUPP); 1133 1134 case DVACT_DEACTIVATE: 1135 sc->sc_dying = 1; 1136 if (sc->sc_child != NULL) 1137 rv = config_deactivate(sc->sc_child); 1138 break; 1139 } 1140 return (rv); 1141 } 1142 1143 /* 1144 * Handle suspend/resume. 1145 * 1146 * We need to switch to polling mode here, because this routine is 1147 * called from an interrupt context. This is all right since we 1148 * are almost suspended anyway. 1149 * 1150 * Note that this power handler isn't to be registered directly; the 1151 * bus glue needs to call out to it. 1152 */ 1153 bool 1154 ehci_suspend(device_t dv PMF_FN_ARGS) 1155 { 1156 ehci_softc_t *sc = device_private(dv); 1157 int i, s; 1158 uint32_t cmd, hcr; 1159 1160 s = splhardusb(); 1161 1162 sc->sc_bus.use_polling++; 1163 1164 for (i = 1; i <= sc->sc_noport; i++) { 1165 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1166 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1167 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1168 } 1169 1170 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1171 1172 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1173 EOWRITE4(sc, EHCI_USBCMD, cmd); 1174 1175 for (i = 0; i < 100; i++) { 1176 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1177 if (hcr == 0) 1178 break; 1179 1180 usb_delay_ms(&sc->sc_bus, 1); 1181 } 1182 if (hcr != 0) 1183 printf("%s: reset timeout\n", device_xname(dv)); 1184 1185 cmd &= ~EHCI_CMD_RS; 1186 EOWRITE4(sc, EHCI_USBCMD, cmd); 1187 1188 for (i = 0; i < 100; i++) { 1189 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1190 if (hcr == EHCI_STS_HCH) 1191 break; 1192 1193 usb_delay_ms(&sc->sc_bus, 1); 1194 } 1195 if (hcr != EHCI_STS_HCH) 1196 printf("%s: config timeout\n", device_xname(dv)); 1197 1198 sc->sc_bus.use_polling--; 1199 splx(s); 1200 1201 return true; 1202 } 1203 1204 bool 1205 ehci_resume(device_t dv PMF_FN_ARGS) 1206 { 1207 ehci_softc_t *sc = device_private(dv); 1208 int i; 1209 uint32_t cmd, hcr; 1210 1211 /* restore things in case the bios sucks */ 1212 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1213 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1214 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1215 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1216 1217 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1218 1219 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1220 1221 hcr = 0; 1222 for (i = 1; i <= sc->sc_noport; i++) { 1223 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1224 if ((cmd & EHCI_PS_PO) == 0 && 1225 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1226 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1227 hcr = 1; 1228 } 1229 } 1230 1231 if (hcr) { 1232 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1233 1234 for (i = 1; i <= sc->sc_noport; i++) { 1235 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1236 if ((cmd & EHCI_PS_PO) == 0 && 1237 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1238 EOWRITE4(sc, EHCI_PORTSC(i), 1239 cmd & ~EHCI_PS_FPR); 1240 } 1241 } 1242 1243 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1244 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1245 1246 for (i = 0; i < 100; i++) { 1247 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1248 if (hcr != EHCI_STS_HCH) 1249 break; 1250 1251 usb_delay_ms(&sc->sc_bus, 1); 1252 } 1253 if (hcr == EHCI_STS_HCH) 1254 printf("%s: config timeout\n", device_xname(dv)); 1255 1256 return true; 1257 } 1258 1259 /* 1260 * Shut down the controller when the system is going down. 1261 */ 1262 bool 1263 ehci_shutdown(device_t self, int flags) 1264 { 1265 ehci_softc_t *sc = device_private(self); 1266 1267 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1268 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1269 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1270 return true; 1271 } 1272 1273 usbd_status 1274 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1275 { 1276 struct ehci_softc *sc = bus->hci_private; 1277 usbd_status err; 1278 1279 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1280 if (err == USBD_NOMEM) 1281 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1282 #ifdef EHCI_DEBUG 1283 if (err) 1284 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1285 #endif 1286 return (err); 1287 } 1288 1289 void 1290 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1291 { 1292 struct ehci_softc *sc = bus->hci_private; 1293 1294 if (dma->block->flags & USB_DMA_RESERVE) { 1295 usb_reserve_freem(&sc->sc_dma_reserve, 1296 dma); 1297 return; 1298 } 1299 usb_freemem(&sc->sc_bus, dma); 1300 } 1301 1302 usbd_xfer_handle 1303 ehci_allocx(struct usbd_bus *bus) 1304 { 1305 struct ehci_softc *sc = bus->hci_private; 1306 usbd_xfer_handle xfer; 1307 1308 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1309 if (xfer != NULL) { 1310 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1311 #ifdef DIAGNOSTIC 1312 if (xfer->busy_free != XFER_FREE) { 1313 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1314 xfer->busy_free); 1315 } 1316 #endif 1317 } else { 1318 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1319 } 1320 if (xfer != NULL) { 1321 memset(xfer, 0, sizeof(struct ehci_xfer)); 1322 #ifdef DIAGNOSTIC 1323 EXFER(xfer)->isdone = 1; 1324 xfer->busy_free = XFER_BUSY; 1325 #endif 1326 } 1327 return (xfer); 1328 } 1329 1330 void 1331 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1332 { 1333 struct ehci_softc *sc = bus->hci_private; 1334 1335 #ifdef DIAGNOSTIC 1336 if (xfer->busy_free != XFER_BUSY) { 1337 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1338 xfer->busy_free); 1339 } 1340 xfer->busy_free = XFER_FREE; 1341 if (!EXFER(xfer)->isdone) { 1342 printf("ehci_freex: !isdone\n"); 1343 } 1344 #endif 1345 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1346 } 1347 1348 Static void 1349 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1350 { 1351 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1352 1353 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1354 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1355 #ifdef USB_DEBUG 1356 if (ehcidebug) 1357 usbd_dump_pipe(pipe); 1358 #endif 1359 epipe->nexttoggle = 0; 1360 } 1361 1362 Static void 1363 ehci_noop(usbd_pipe_handle pipe) 1364 { 1365 } 1366 1367 #ifdef EHCI_DEBUG 1368 void 1369 ehci_dump_regs(ehci_softc_t *sc) 1370 { 1371 int i; 1372 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1373 EOREAD4(sc, EHCI_USBCMD), 1374 EOREAD4(sc, EHCI_USBSTS), 1375 EOREAD4(sc, EHCI_USBINTR)); 1376 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1377 EOREAD4(sc, EHCI_FRINDEX), 1378 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1379 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1380 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1381 for (i = 1; i <= sc->sc_noport; i++) 1382 printf("port %d status=0x%08x\n", i, 1383 EOREAD4(sc, EHCI_PORTSC(i))); 1384 } 1385 1386 /* 1387 * Unused function - this is meant to be called from a kernel 1388 * debugger. 1389 */ 1390 void 1391 ehci_dump() 1392 { 1393 ehci_dump_regs(theehci); 1394 } 1395 1396 void 1397 ehci_dump_link(ehci_link_t link, int type) 1398 { 1399 link = le32toh(link); 1400 printf("0x%08x", link); 1401 if (link & EHCI_LINK_TERMINATE) 1402 printf("<T>"); 1403 else { 1404 printf("<"); 1405 if (type) { 1406 switch (EHCI_LINK_TYPE(link)) { 1407 case EHCI_LINK_ITD: printf("ITD"); break; 1408 case EHCI_LINK_QH: printf("QH"); break; 1409 case EHCI_LINK_SITD: printf("SITD"); break; 1410 case EHCI_LINK_FSTN: printf("FSTN"); break; 1411 } 1412 } 1413 printf(">"); 1414 } 1415 } 1416 1417 void 1418 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1419 { 1420 int i; 1421 u_int32_t stop; 1422 1423 stop = 0; 1424 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1425 ehci_dump_sqtd(sqtd); 1426 usb_syncmem(&sqtd->dma, 1427 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1428 sizeof(sqtd->qtd), 1429 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1430 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1431 usb_syncmem(&sqtd->dma, 1432 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1433 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1434 } 1435 if (sqtd) 1436 printf("dump aborted, too many TDs\n"); 1437 } 1438 1439 void 1440 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1441 { 1442 usb_syncmem(&sqtd->dma, sqtd->offs, 1443 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1444 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1445 ehci_dump_qtd(&sqtd->qtd); 1446 usb_syncmem(&sqtd->dma, sqtd->offs, 1447 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1448 } 1449 1450 void 1451 ehci_dump_qtd(ehci_qtd_t *qtd) 1452 { 1453 u_int32_t s; 1454 char sbuf[128]; 1455 1456 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1457 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1458 printf("\n"); 1459 s = le32toh(qtd->qtd_status); 1460 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1461 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1462 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1463 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1464 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1465 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1466 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1467 EHCI_QTD_GET_PID(s), sbuf); 1468 for (s = 0; s < 5; s++) 1469 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1470 } 1471 1472 void 1473 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1474 { 1475 ehci_qh_t *qh = &sqh->qh; 1476 u_int32_t endp, endphub; 1477 1478 usb_syncmem(&sqh->dma, sqh->offs, 1479 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1480 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1481 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1482 endp = le32toh(qh->qh_endp); 1483 printf(" endp=0x%08x\n", endp); 1484 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1485 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1486 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1487 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1488 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1489 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1490 EHCI_QH_GET_NRL(endp)); 1491 endphub = le32toh(qh->qh_endphub); 1492 printf(" endphub=0x%08x\n", endphub); 1493 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1494 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1495 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1496 EHCI_QH_GET_MULT(endphub)); 1497 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1498 printf("Overlay qTD:\n"); 1499 ehci_dump_qtd(&qh->qh_qtd); 1500 usb_syncmem(&sqh->dma, sqh->offs, 1501 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1502 } 1503 1504 #if notyet 1505 void 1506 ehci_dump_itd(struct ehci_soft_itd *itd) 1507 { 1508 ehci_isoc_trans_t t; 1509 ehci_isoc_bufr_ptr_t b, b2, b3; 1510 int i; 1511 1512 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1513 1514 for (i = 0; i < 8;i++) { 1515 t = le32toh(itd->itd.itd_ctl[i]); 1516 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1517 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1518 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1519 EHCI_ITD_GET_OFFS(t)); 1520 } 1521 printf("ITDbufr: "); 1522 for (i = 0; i < 7; i++) 1523 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1524 1525 b = le32toh(itd->itd.itd_bufr[0]); 1526 b2 = le32toh(itd->itd.itd_bufr[1]); 1527 b3 = le32toh(itd->itd.itd_bufr[2]); 1528 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1529 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1530 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1531 } 1532 1533 void 1534 ehci_dump_sitd(struct ehci_soft_itd *itd) 1535 { 1536 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1537 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1538 itd->xfer_next, itd->physaddr, itd->slot); 1539 } 1540 #endif 1541 1542 #ifdef DIAGNOSTIC 1543 void 1544 ehci_dump_exfer(struct ehci_xfer *ex) 1545 { 1546 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1547 } 1548 #endif 1549 1550 #endif 1551 1552 usbd_status 1553 ehci_open(usbd_pipe_handle pipe) 1554 { 1555 usbd_device_handle dev = pipe->device; 1556 ehci_softc_t *sc = dev->bus->hci_private; 1557 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1558 u_int8_t addr = dev->address; 1559 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1560 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1561 ehci_soft_qh_t *sqh; 1562 usbd_status err; 1563 int s; 1564 int ival, speed, naks; 1565 int hshubaddr, hshubport; 1566 1567 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1568 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1569 1570 if (dev->myhsport) { 1571 hshubaddr = dev->myhsport->parent->address; 1572 hshubport = dev->myhsport->portno; 1573 } else { 1574 hshubaddr = 0; 1575 hshubport = 0; 1576 } 1577 1578 if (sc->sc_dying) 1579 return (USBD_IOERROR); 1580 1581 epipe->nexttoggle = 0; 1582 1583 if (addr == sc->sc_addr) { 1584 switch (ed->bEndpointAddress) { 1585 case USB_CONTROL_ENDPOINT: 1586 pipe->methods = &ehci_root_ctrl_methods; 1587 break; 1588 case UE_DIR_IN | EHCI_INTR_ENDPT: 1589 pipe->methods = &ehci_root_intr_methods; 1590 break; 1591 default: 1592 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1593 ed->bEndpointAddress)); 1594 return (USBD_INVAL); 1595 } 1596 return (USBD_NORMAL_COMPLETION); 1597 } 1598 1599 /* XXX All this stuff is only valid for async. */ 1600 switch (dev->speed) { 1601 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1602 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1603 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1604 default: panic("ehci_open: bad device speed %d", dev->speed); 1605 } 1606 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1607 printf("%s: *** Error: opening low/full speed isoc device on" 1608 "ehci, this does not work yet. Feel free to implement\n", 1609 device_xname(sc->sc_dev)); 1610 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1611 hshubaddr, hshubport)); 1612 return USBD_INVAL; 1613 } 1614 1615 naks = 8; /* XXX */ 1616 1617 /* Allocate sqh for everything, save isoc xfers */ 1618 if (xfertype != UE_ISOCHRONOUS) { 1619 sqh = ehci_alloc_sqh(sc); 1620 if (sqh == NULL) 1621 return (USBD_NOMEM); 1622 /* qh_link filled when the QH is added */ 1623 sqh->qh.qh_endp = htole32( 1624 EHCI_QH_SET_ADDR(addr) | 1625 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1626 EHCI_QH_SET_EPS(speed) | 1627 EHCI_QH_DTC | 1628 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1629 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1630 EHCI_QH_CTL : 0) | 1631 EHCI_QH_SET_NRL(naks) 1632 ); 1633 sqh->qh.qh_endphub = htole32( 1634 EHCI_QH_SET_MULT(1) | 1635 EHCI_QH_SET_HUBA(hshubaddr) | 1636 EHCI_QH_SET_PORT(hshubport) | 1637 EHCI_QH_SET_CMASK(0x08) | /* XXX */ 1638 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1639 ); 1640 sqh->qh.qh_curqtd = EHCI_NULL; 1641 /* Fill the overlay qTD */ 1642 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1643 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1644 sqh->qh.qh_qtd.qtd_status = htole32(0); 1645 1646 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1647 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1648 epipe->sqh = sqh; 1649 } else { 1650 sqh = NULL; 1651 } /*xfertype == UE_ISOC*/ 1652 1653 switch (xfertype) { 1654 case UE_CONTROL: 1655 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1656 0, &epipe->u.ctl.reqdma); 1657 #ifdef EHCI_DEBUG 1658 if (err) 1659 printf("ehci_open: usb_allocmem()=%d\n", err); 1660 #endif 1661 if (err) 1662 goto bad; 1663 pipe->methods = &ehci_device_ctrl_methods; 1664 s = splusb(); 1665 ehci_add_qh(sqh, sc->sc_async_head); 1666 splx(s); 1667 break; 1668 case UE_BULK: 1669 pipe->methods = &ehci_device_bulk_methods; 1670 s = splusb(); 1671 ehci_add_qh(sqh, sc->sc_async_head); 1672 splx(s); 1673 break; 1674 case UE_INTERRUPT: 1675 pipe->methods = &ehci_device_intr_methods; 1676 ival = pipe->interval; 1677 if (ival == USBD_DEFAULT_INTERVAL) { 1678 if (speed == EHCI_QH_SPEED_HIGH) { 1679 if (ed->bInterval > 16) { 1680 /* 1681 * illegal with high-speed, but there 1682 * were documentation bugs in the spec, 1683 * so be generous 1684 */ 1685 ival = 256; 1686 } else 1687 ival = (1 << (ed->bInterval - 1)) / 8; 1688 } else 1689 ival = ed->bInterval; 1690 } 1691 err = ehci_device_setintr(sc, sqh, ival); 1692 if (err) 1693 goto bad; 1694 break; 1695 case UE_ISOCHRONOUS: 1696 pipe->methods = &ehci_device_isoc_methods; 1697 if (ed->bInterval == 0 || ed->bInterval >= 16) { 1698 printf("ehci: opening pipe with invalid bInterval\n"); 1699 err = USBD_INVAL; 1700 goto bad; 1701 } 1702 if (UGETW(ed->wMaxPacketSize) == 0) { 1703 printf("ehci: zero length endpoint open request\n"); 1704 err = USBD_INVAL; 1705 goto bad; 1706 } 1707 epipe->u.isoc.next_frame = 0; 1708 epipe->u.isoc.cur_xfers = 0; 1709 break; 1710 default: 1711 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1712 err = USBD_INVAL; 1713 goto bad; 1714 } 1715 return (USBD_NORMAL_COMPLETION); 1716 1717 bad: 1718 if (sqh != NULL) 1719 ehci_free_sqh(sc, sqh); 1720 return (err); 1721 } 1722 1723 /* 1724 * Add an ED to the schedule. Called at splusb(). 1725 */ 1726 void 1727 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1728 { 1729 SPLUSBCHECK; 1730 1731 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1732 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1733 sqh->next = head->next; 1734 sqh->qh.qh_link = head->qh.qh_link; 1735 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1736 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1737 head->next = sqh; 1738 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1739 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1740 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1741 1742 #ifdef EHCI_DEBUG 1743 if (ehcidebug > 5) { 1744 printf("ehci_add_qh:\n"); 1745 ehci_dump_sqh(sqh); 1746 } 1747 #endif 1748 } 1749 1750 /* 1751 * Remove an ED from the schedule. Called at splusb(). 1752 */ 1753 void 1754 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1755 { 1756 ehci_soft_qh_t *p; 1757 1758 SPLUSBCHECK; 1759 /* XXX */ 1760 for (p = head; p != NULL && p->next != sqh; p = p->next) 1761 ; 1762 if (p == NULL) 1763 panic("ehci_rem_qh: ED not found"); 1764 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1765 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1766 p->next = sqh->next; 1767 p->qh.qh_link = sqh->qh.qh_link; 1768 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1769 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1770 1771 ehci_sync_hc(sc); 1772 } 1773 1774 void 1775 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1776 { 1777 int i; 1778 u_int32_t status; 1779 1780 /* Save toggle bit and ping status. */ 1781 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1782 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1783 status = sqh->qh.qh_qtd.qtd_status & 1784 htole32(EHCI_QTD_TOGGLE_MASK | 1785 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1786 /* Set HALTED to make hw leave it alone. */ 1787 sqh->qh.qh_qtd.qtd_status = 1788 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1789 usb_syncmem(&sqh->dma, 1790 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1791 sizeof(sqh->qh.qh_qtd.qtd_status), 1792 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1793 sqh->qh.qh_curqtd = 0; 1794 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1795 sqh->qh.qh_qtd.qtd_altnext = 0; 1796 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1797 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1798 sqh->sqtd = sqtd; 1799 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1800 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1801 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1802 sqh->qh.qh_qtd.qtd_status = status; 1803 usb_syncmem(&sqh->dma, 1804 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1805 sizeof(sqh->qh.qh_qtd.qtd_status), 1806 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1807 } 1808 1809 /* 1810 * Ensure that the HC has released all references to the QH. We do this 1811 * by asking for a Async Advance Doorbell interrupt and then we wait for 1812 * the interrupt. 1813 * To make this easier we first obtain exclusive use of the doorbell. 1814 */ 1815 void 1816 ehci_sync_hc(ehci_softc_t *sc) 1817 { 1818 int s, error; 1819 1820 if (sc->sc_dying) { 1821 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1822 return; 1823 } 1824 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1825 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */ 1826 s = splhardusb(); 1827 /* ask for doorbell */ 1828 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1829 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1830 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1831 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1832 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1833 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1834 splx(s); 1835 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */ 1836 #ifdef DIAGNOSTIC 1837 if (error) 1838 printf("ehci_sync_hc: tsleep() = %d\n", error); 1839 #endif 1840 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1841 } 1842 1843 /*Call at splusb*/ 1844 void 1845 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1846 { 1847 struct ehci_soft_itd *itd, *prev; 1848 1849 prev = NULL; 1850 1851 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1852 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1853 1854 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1855 prev = itd->u.frame_list.prev; 1856 /* Unlink itd from hardware chain, or frame array */ 1857 if (prev == NULL) { /* We're at the table head */ 1858 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1859 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1860 usb_syncmem(&sc->sc_fldma, 1861 sizeof(ehci_link_t) * itd->slot, 1862 sizeof(ehci_link_t), 1863 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1864 1865 if (itd->u.frame_list.next != NULL) 1866 itd->u.frame_list.next->u.frame_list.prev = NULL; 1867 } else { 1868 /* XXX this part is untested... */ 1869 prev->itd.itd_next = itd->itd.itd_next; 1870 usb_syncmem(&itd->dma, 1871 itd->offs + offsetof(ehci_itd_t, itd_next), 1872 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1873 1874 prev->u.frame_list.next = itd->u.frame_list.next; 1875 if (itd->u.frame_list.next != NULL) 1876 itd->u.frame_list.next->u.frame_list.prev = prev; 1877 } 1878 } 1879 1880 prev = NULL; 1881 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1882 if (prev != NULL) 1883 ehci_free_itd(sc, prev); 1884 prev = itd; 1885 } 1886 if (prev) 1887 ehci_free_itd(sc, prev); 1888 exfer->itdstart = NULL; 1889 exfer->itdend = NULL; 1890 } 1891 1892 /***********/ 1893 1894 /* 1895 * Data structures and routines to emulate the root hub. 1896 */ 1897 Static usb_device_descriptor_t ehci_devd = { 1898 USB_DEVICE_DESCRIPTOR_SIZE, 1899 UDESC_DEVICE, /* type */ 1900 {0x00, 0x02}, /* USB version */ 1901 UDCLASS_HUB, /* class */ 1902 UDSUBCLASS_HUB, /* subclass */ 1903 UDPROTO_HSHUBSTT, /* protocol */ 1904 64, /* max packet */ 1905 {0},{0},{0x00,0x01}, /* device id */ 1906 1,2,0, /* string indicies */ 1907 1 /* # of configurations */ 1908 }; 1909 1910 Static const usb_device_qualifier_t ehci_odevd = { 1911 USB_DEVICE_DESCRIPTOR_SIZE, 1912 UDESC_DEVICE_QUALIFIER, /* type */ 1913 {0x00, 0x02}, /* USB version */ 1914 UDCLASS_HUB, /* class */ 1915 UDSUBCLASS_HUB, /* subclass */ 1916 UDPROTO_FSHUB, /* protocol */ 1917 64, /* max packet */ 1918 1, /* # of configurations */ 1919 0 1920 }; 1921 1922 Static const usb_config_descriptor_t ehci_confd = { 1923 USB_CONFIG_DESCRIPTOR_SIZE, 1924 UDESC_CONFIG, 1925 {USB_CONFIG_DESCRIPTOR_SIZE + 1926 USB_INTERFACE_DESCRIPTOR_SIZE + 1927 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1928 1, 1929 1, 1930 0, 1931 UC_ATTR_MBO | UC_SELF_POWERED, 1932 0 /* max power */ 1933 }; 1934 1935 Static const usb_interface_descriptor_t ehci_ifcd = { 1936 USB_INTERFACE_DESCRIPTOR_SIZE, 1937 UDESC_INTERFACE, 1938 0, 1939 0, 1940 1, 1941 UICLASS_HUB, 1942 UISUBCLASS_HUB, 1943 UIPROTO_HSHUBSTT, 1944 0 1945 }; 1946 1947 Static const usb_endpoint_descriptor_t ehci_endpd = { 1948 USB_ENDPOINT_DESCRIPTOR_SIZE, 1949 UDESC_ENDPOINT, 1950 UE_DIR_IN | EHCI_INTR_ENDPT, 1951 UE_INTERRUPT, 1952 {8, 0}, /* max packet */ 1953 12 1954 }; 1955 1956 Static const usb_hub_descriptor_t ehci_hubd = { 1957 USB_HUB_DESCRIPTOR_SIZE, 1958 UDESC_HUB, 1959 0, 1960 {0,0}, 1961 0, 1962 0, 1963 {""}, 1964 {""}, 1965 }; 1966 1967 /* 1968 * Simulate a hardware hub by handling all the necessary requests. 1969 */ 1970 Static usbd_status 1971 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1972 { 1973 usbd_status err; 1974 1975 /* Insert last in queue. */ 1976 err = usb_insert_transfer(xfer); 1977 if (err) 1978 return (err); 1979 1980 /* Pipe isn't running, start first */ 1981 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1982 } 1983 1984 Static usbd_status 1985 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1986 { 1987 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1988 usb_device_request_t *req; 1989 void *buf = NULL; 1990 int port, i; 1991 int s, len, value, index, l, totlen = 0; 1992 usb_port_status_t ps; 1993 usb_hub_descriptor_t hubd; 1994 usbd_status err; 1995 u_int32_t v; 1996 1997 if (sc->sc_dying) 1998 return (USBD_IOERROR); 1999 2000 #ifdef DIAGNOSTIC 2001 if (!(xfer->rqflags & URQ_REQUEST)) 2002 /* XXX panic */ 2003 return (USBD_INVAL); 2004 #endif 2005 req = &xfer->request; 2006 2007 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2008 req->bmRequestType, req->bRequest)); 2009 2010 len = UGETW(req->wLength); 2011 value = UGETW(req->wValue); 2012 index = UGETW(req->wIndex); 2013 2014 if (len != 0) 2015 buf = KERNADDR(&xfer->dmabuf, 0); 2016 2017 #define C(x,y) ((x) | ((y) << 8)) 2018 switch(C(req->bRequest, req->bmRequestType)) { 2019 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2020 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2021 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2022 /* 2023 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2024 * for the integrated root hub. 2025 */ 2026 break; 2027 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2028 if (len > 0) { 2029 *(u_int8_t *)buf = sc->sc_conf; 2030 totlen = 1; 2031 } 2032 break; 2033 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2034 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2035 if (len == 0) 2036 break; 2037 switch(value >> 8) { 2038 case UDESC_DEVICE: 2039 if ((value & 0xff) != 0) { 2040 err = USBD_IOERROR; 2041 goto ret; 2042 } 2043 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2044 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2045 memcpy(buf, &ehci_devd, l); 2046 break; 2047 /* 2048 * We can't really operate at another speed, but the spec says 2049 * we need this descriptor. 2050 */ 2051 case UDESC_DEVICE_QUALIFIER: 2052 if ((value & 0xff) != 0) { 2053 err = USBD_IOERROR; 2054 goto ret; 2055 } 2056 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2057 memcpy(buf, &ehci_odevd, l); 2058 break; 2059 /* 2060 * We can't really operate at another speed, but the spec says 2061 * we need this descriptor. 2062 */ 2063 case UDESC_OTHER_SPEED_CONFIGURATION: 2064 case UDESC_CONFIG: 2065 if ((value & 0xff) != 0) { 2066 err = USBD_IOERROR; 2067 goto ret; 2068 } 2069 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2070 memcpy(buf, &ehci_confd, l); 2071 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2072 value >> 8; 2073 buf = (char *)buf + l; 2074 len -= l; 2075 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2076 totlen += l; 2077 memcpy(buf, &ehci_ifcd, l); 2078 buf = (char *)buf + l; 2079 len -= l; 2080 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2081 totlen += l; 2082 memcpy(buf, &ehci_endpd, l); 2083 break; 2084 case UDESC_STRING: 2085 #define sd ((usb_string_descriptor_t *)buf) 2086 switch (value & 0xff) { 2087 case 0: /* Language table */ 2088 totlen = usb_makelangtbl(sd, len); 2089 break; 2090 case 1: /* Vendor */ 2091 totlen = usb_makestrdesc(sd, len, 2092 sc->sc_vendor); 2093 break; 2094 case 2: /* Product */ 2095 totlen = usb_makestrdesc(sd, len, 2096 "EHCI root hub"); 2097 break; 2098 } 2099 #undef sd 2100 break; 2101 default: 2102 err = USBD_IOERROR; 2103 goto ret; 2104 } 2105 break; 2106 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2107 if (len > 0) { 2108 *(u_int8_t *)buf = 0; 2109 totlen = 1; 2110 } 2111 break; 2112 case C(UR_GET_STATUS, UT_READ_DEVICE): 2113 if (len > 1) { 2114 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2115 totlen = 2; 2116 } 2117 break; 2118 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2119 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2120 if (len > 1) { 2121 USETW(((usb_status_t *)buf)->wStatus, 0); 2122 totlen = 2; 2123 } 2124 break; 2125 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2126 if (value >= USB_MAX_DEVICES) { 2127 err = USBD_IOERROR; 2128 goto ret; 2129 } 2130 sc->sc_addr = value; 2131 break; 2132 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2133 if (value != 0 && value != 1) { 2134 err = USBD_IOERROR; 2135 goto ret; 2136 } 2137 sc->sc_conf = value; 2138 break; 2139 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2140 break; 2141 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2142 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2143 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2144 err = USBD_IOERROR; 2145 goto ret; 2146 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2147 break; 2148 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2149 break; 2150 /* Hub requests */ 2151 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2152 break; 2153 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2154 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2155 "port=%d feature=%d\n", 2156 index, value)); 2157 if (index < 1 || index > sc->sc_noport) { 2158 err = USBD_IOERROR; 2159 goto ret; 2160 } 2161 port = EHCI_PORTSC(index); 2162 v = EOREAD4(sc, port); 2163 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2164 v &= ~EHCI_PS_CLEAR; 2165 switch(value) { 2166 case UHF_PORT_ENABLE: 2167 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2168 break; 2169 case UHF_PORT_SUSPEND: 2170 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2171 break; 2172 v &= ~EHCI_PS_SUSP; 2173 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2174 /* see USB2 spec ch. 7.1.7.7 */ 2175 usb_delay_ms(&sc->sc_bus, 20); 2176 EOWRITE4(sc, port, v); 2177 usb_delay_ms(&sc->sc_bus, 2); 2178 #ifdef DEBUG 2179 v = EOREAD4(sc, port); 2180 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2181 printf("ehci: resume failed: %x\n", v); 2182 #endif 2183 break; 2184 case UHF_PORT_POWER: 2185 if (sc->sc_hasppc) 2186 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2187 break; 2188 case UHF_PORT_TEST: 2189 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2190 "%d\n", index)); 2191 break; 2192 case UHF_PORT_INDICATOR: 2193 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2194 "%d\n", index)); 2195 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2196 break; 2197 case UHF_C_PORT_CONNECTION: 2198 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2199 break; 2200 case UHF_C_PORT_ENABLE: 2201 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2202 break; 2203 case UHF_C_PORT_SUSPEND: 2204 /* how? */ 2205 break; 2206 case UHF_C_PORT_OVER_CURRENT: 2207 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2208 break; 2209 case UHF_C_PORT_RESET: 2210 sc->sc_isreset[index] = 0; 2211 break; 2212 default: 2213 err = USBD_IOERROR; 2214 goto ret; 2215 } 2216 #if 0 2217 switch(value) { 2218 case UHF_C_PORT_CONNECTION: 2219 case UHF_C_PORT_ENABLE: 2220 case UHF_C_PORT_SUSPEND: 2221 case UHF_C_PORT_OVER_CURRENT: 2222 case UHF_C_PORT_RESET: 2223 default: 2224 break; 2225 } 2226 #endif 2227 break; 2228 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2229 if (len == 0) 2230 break; 2231 if ((value & 0xff) != 0) { 2232 err = USBD_IOERROR; 2233 goto ret; 2234 } 2235 hubd = ehci_hubd; 2236 hubd.bNbrPorts = sc->sc_noport; 2237 v = EOREAD4(sc, EHCI_HCSPARAMS); 2238 USETW(hubd.wHubCharacteristics, 2239 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2240 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2241 ? UHD_PORT_IND : 0); 2242 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2243 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2244 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2245 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2246 l = min(len, hubd.bDescLength); 2247 totlen = l; 2248 memcpy(buf, &hubd, l); 2249 break; 2250 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2251 if (len != 4) { 2252 err = USBD_IOERROR; 2253 goto ret; 2254 } 2255 memset(buf, 0, len); /* ? XXX */ 2256 totlen = len; 2257 break; 2258 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2259 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2260 index)); 2261 if (index < 1 || index > sc->sc_noport) { 2262 err = USBD_IOERROR; 2263 goto ret; 2264 } 2265 if (len != 4) { 2266 err = USBD_IOERROR; 2267 goto ret; 2268 } 2269 v = EOREAD4(sc, EHCI_PORTSC(index)); 2270 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2271 v)); 2272 i = UPS_HIGH_SPEED; 2273 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2274 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2275 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2276 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2277 if (v & EHCI_PS_PR) i |= UPS_RESET; 2278 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2279 USETW(ps.wPortStatus, i); 2280 i = 0; 2281 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2282 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2283 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2284 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2285 USETW(ps.wPortChange, i); 2286 l = min(len, sizeof ps); 2287 memcpy(buf, &ps, l); 2288 totlen = l; 2289 break; 2290 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2291 err = USBD_IOERROR; 2292 goto ret; 2293 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2294 break; 2295 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2296 if (index < 1 || index > sc->sc_noport) { 2297 err = USBD_IOERROR; 2298 goto ret; 2299 } 2300 port = EHCI_PORTSC(index); 2301 v = EOREAD4(sc, port); 2302 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2303 v &= ~EHCI_PS_CLEAR; 2304 switch(value) { 2305 case UHF_PORT_ENABLE: 2306 EOWRITE4(sc, port, v | EHCI_PS_PE); 2307 break; 2308 case UHF_PORT_SUSPEND: 2309 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2310 break; 2311 case UHF_PORT_RESET: 2312 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2313 index)); 2314 if (EHCI_PS_IS_LOWSPEED(v)) { 2315 /* Low speed device, give up ownership. */ 2316 ehci_disown(sc, index, 1); 2317 break; 2318 } 2319 /* Start reset sequence. */ 2320 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2321 EOWRITE4(sc, port, v | EHCI_PS_PR); 2322 /* Wait for reset to complete. */ 2323 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2324 if (sc->sc_dying) { 2325 err = USBD_IOERROR; 2326 goto ret; 2327 } 2328 /* Terminate reset sequence. */ 2329 EOWRITE4(sc, port, v); 2330 /* Wait for HC to complete reset. */ 2331 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2332 if (sc->sc_dying) { 2333 err = USBD_IOERROR; 2334 goto ret; 2335 } 2336 v = EOREAD4(sc, port); 2337 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2338 if (v & EHCI_PS_PR) { 2339 printf("%s: port reset timeout\n", 2340 device_xname(sc->sc_dev)); 2341 return (USBD_TIMEOUT); 2342 } 2343 if (!(v & EHCI_PS_PE)) { 2344 /* Not a high speed device, give up ownership.*/ 2345 ehci_disown(sc, index, 0); 2346 break; 2347 } 2348 sc->sc_isreset[index] = 1; 2349 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2350 index, v)); 2351 break; 2352 case UHF_PORT_POWER: 2353 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2354 "%d (has PPC = %d)\n", index, 2355 sc->sc_hasppc)); 2356 if (sc->sc_hasppc) 2357 EOWRITE4(sc, port, v | EHCI_PS_PP); 2358 break; 2359 case UHF_PORT_TEST: 2360 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2361 "%d\n", index)); 2362 break; 2363 case UHF_PORT_INDICATOR: 2364 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2365 "%d\n", index)); 2366 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2367 break; 2368 default: 2369 err = USBD_IOERROR; 2370 goto ret; 2371 } 2372 break; 2373 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2374 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2375 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2376 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2377 break; 2378 default: 2379 err = USBD_IOERROR; 2380 goto ret; 2381 } 2382 xfer->actlen = totlen; 2383 err = USBD_NORMAL_COMPLETION; 2384 ret: 2385 xfer->status = err; 2386 s = splusb(); 2387 usb_transfer_complete(xfer); 2388 splx(s); 2389 return (USBD_IN_PROGRESS); 2390 } 2391 2392 void 2393 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2394 { 2395 int port; 2396 u_int32_t v; 2397 2398 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2399 #ifdef DIAGNOSTIC 2400 if (sc->sc_npcomp != 0) { 2401 int i = (index-1) / sc->sc_npcomp; 2402 if (i >= sc->sc_ncomp) 2403 printf("%s: strange port\n", 2404 device_xname(sc->sc_dev)); 2405 else 2406 printf("%s: handing over %s speed device on " 2407 "port %d to %s\n", 2408 device_xname(sc->sc_dev), 2409 lowspeed ? "low" : "full", 2410 index, device_xname(sc->sc_comps[i])); 2411 } else { 2412 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2413 } 2414 #endif 2415 port = EHCI_PORTSC(index); 2416 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2417 EOWRITE4(sc, port, v | EHCI_PS_PO); 2418 } 2419 2420 /* Abort a root control request. */ 2421 Static void 2422 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2423 { 2424 /* Nothing to do, all transfers are synchronous. */ 2425 } 2426 2427 /* Close the root pipe. */ 2428 Static void 2429 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2430 { 2431 DPRINTF(("ehci_root_ctrl_close\n")); 2432 /* Nothing to do. */ 2433 } 2434 2435 void 2436 ehci_root_intr_done(usbd_xfer_handle xfer) 2437 { 2438 xfer->hcpriv = NULL; 2439 } 2440 2441 Static usbd_status 2442 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2443 { 2444 usbd_status err; 2445 2446 /* Insert last in queue. */ 2447 err = usb_insert_transfer(xfer); 2448 if (err) 2449 return (err); 2450 2451 /* Pipe isn't running, start first */ 2452 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2453 } 2454 2455 Static usbd_status 2456 ehci_root_intr_start(usbd_xfer_handle xfer) 2457 { 2458 usbd_pipe_handle pipe = xfer->pipe; 2459 ehci_softc_t *sc = pipe->device->bus->hci_private; 2460 2461 if (sc->sc_dying) 2462 return (USBD_IOERROR); 2463 2464 sc->sc_intrxfer = xfer; 2465 2466 return (USBD_IN_PROGRESS); 2467 } 2468 2469 /* Abort a root interrupt request. */ 2470 Static void 2471 ehci_root_intr_abort(usbd_xfer_handle xfer) 2472 { 2473 int s; 2474 2475 if (xfer->pipe->intrxfer == xfer) { 2476 DPRINTF(("ehci_root_intr_abort: remove\n")); 2477 xfer->pipe->intrxfer = NULL; 2478 } 2479 xfer->status = USBD_CANCELLED; 2480 s = splusb(); 2481 usb_transfer_complete(xfer); 2482 splx(s); 2483 } 2484 2485 /* Close the root pipe. */ 2486 Static void 2487 ehci_root_intr_close(usbd_pipe_handle pipe) 2488 { 2489 ehci_softc_t *sc = pipe->device->bus->hci_private; 2490 2491 DPRINTF(("ehci_root_intr_close\n")); 2492 2493 sc->sc_intrxfer = NULL; 2494 } 2495 2496 void 2497 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2498 { 2499 xfer->hcpriv = NULL; 2500 } 2501 2502 /************************/ 2503 2504 ehci_soft_qh_t * 2505 ehci_alloc_sqh(ehci_softc_t *sc) 2506 { 2507 ehci_soft_qh_t *sqh; 2508 usbd_status err; 2509 int i, offs; 2510 usb_dma_t dma; 2511 2512 if (sc->sc_freeqhs == NULL) { 2513 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2514 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2515 EHCI_PAGE_SIZE, &dma); 2516 #ifdef EHCI_DEBUG 2517 if (err) 2518 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2519 #endif 2520 if (err) 2521 return (NULL); 2522 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2523 offs = i * EHCI_SQH_SIZE; 2524 sqh = KERNADDR(&dma, offs); 2525 sqh->physaddr = DMAADDR(&dma, offs); 2526 sqh->dma = dma; 2527 sqh->offs = offs; 2528 sqh->next = sc->sc_freeqhs; 2529 sc->sc_freeqhs = sqh; 2530 } 2531 } 2532 sqh = sc->sc_freeqhs; 2533 sc->sc_freeqhs = sqh->next; 2534 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2535 sqh->next = NULL; 2536 return (sqh); 2537 } 2538 2539 void 2540 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2541 { 2542 sqh->next = sc->sc_freeqhs; 2543 sc->sc_freeqhs = sqh; 2544 } 2545 2546 ehci_soft_qtd_t * 2547 ehci_alloc_sqtd(ehci_softc_t *sc) 2548 { 2549 ehci_soft_qtd_t *sqtd; 2550 usbd_status err; 2551 int i, offs; 2552 usb_dma_t dma; 2553 int s; 2554 2555 if (sc->sc_freeqtds == NULL) { 2556 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2557 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2558 EHCI_PAGE_SIZE, &dma); 2559 #ifdef EHCI_DEBUG 2560 if (err) 2561 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2562 #endif 2563 if (err) 2564 return (NULL); 2565 s = splusb(); 2566 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2567 offs = i * EHCI_SQTD_SIZE; 2568 sqtd = KERNADDR(&dma, offs); 2569 sqtd->physaddr = DMAADDR(&dma, offs); 2570 sqtd->dma = dma; 2571 sqtd->offs = offs; 2572 sqtd->nextqtd = sc->sc_freeqtds; 2573 sc->sc_freeqtds = sqtd; 2574 } 2575 splx(s); 2576 } 2577 2578 s = splusb(); 2579 sqtd = sc->sc_freeqtds; 2580 sc->sc_freeqtds = sqtd->nextqtd; 2581 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2582 sqtd->nextqtd = NULL; 2583 sqtd->xfer = NULL; 2584 splx(s); 2585 2586 return (sqtd); 2587 } 2588 2589 void 2590 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2591 { 2592 int s; 2593 2594 s = splusb(); 2595 sqtd->nextqtd = sc->sc_freeqtds; 2596 sc->sc_freeqtds = sqtd; 2597 splx(s); 2598 } 2599 2600 usbd_status 2601 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2602 int alen, int rd, usbd_xfer_handle xfer, 2603 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2604 { 2605 ehci_soft_qtd_t *next, *cur; 2606 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2607 u_int32_t qtdstatus; 2608 int len, curlen, mps; 2609 int i, tog; 2610 usb_dma_t *dma = &xfer->dmabuf; 2611 u_int16_t flags = xfer->flags; 2612 2613 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2614 2615 len = alen; 2616 dataphys = DMAADDR(dma, 0); 2617 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2618 qtdstatus = EHCI_QTD_ACTIVE | 2619 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2620 EHCI_QTD_SET_CERR(3) 2621 /* IOC set below */ 2622 /* BYTES set below */ 2623 ; 2624 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2625 tog = epipe->nexttoggle; 2626 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2627 2628 cur = ehci_alloc_sqtd(sc); 2629 *sp = cur; 2630 if (cur == NULL) 2631 goto nomem; 2632 2633 usb_syncmem(dma, 0, alen, 2634 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2635 for (;;) { 2636 dataphyspage = EHCI_PAGE(dataphys); 2637 /* The EHCI hardware can handle at most 5 pages. */ 2638 if (dataphyslastpage - dataphyspage < 2639 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2640 /* we can handle it in this QTD */ 2641 curlen = len; 2642 } else { 2643 /* must use multiple TDs, fill as much as possible. */ 2644 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2645 EHCI_PAGE_OFFSET(dataphys); 2646 #ifdef DIAGNOSTIC 2647 if (curlen > len) { 2648 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2649 "len=0x%x offs=0x%x\n", curlen, len, 2650 EHCI_PAGE_OFFSET(dataphys)); 2651 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2652 dataphyslastpage, dataphyspage, 2653 dataphys); 2654 curlen = len; 2655 } 2656 #endif 2657 /* the length must be a multiple of the max size */ 2658 curlen -= curlen % mps; 2659 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2660 "curlen=%d\n", curlen)); 2661 #ifdef DIAGNOSTIC 2662 if (curlen == 0) 2663 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2664 #endif 2665 } 2666 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2667 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2668 dataphys, dataphyslastpage, 2669 len, curlen)); 2670 len -= curlen; 2671 2672 /* 2673 * Allocate another transfer if there's more data left, 2674 * or if force last short transfer flag is set and we're 2675 * allocating a multiple of the max packet size. 2676 */ 2677 if (len != 0 || 2678 ((curlen % mps) == 0 && !rd && curlen != 0 && 2679 (flags & USBD_FORCE_SHORT_XFER))) { 2680 next = ehci_alloc_sqtd(sc); 2681 if (next == NULL) 2682 goto nomem; 2683 nextphys = htole32(next->physaddr); 2684 } else { 2685 next = NULL; 2686 nextphys = EHCI_NULL; 2687 } 2688 2689 for (i = 0; i * EHCI_PAGE_SIZE < 2690 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2691 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2692 if (i != 0) /* use offset only in first buffer */ 2693 a = EHCI_PAGE(a); 2694 cur->qtd.qtd_buffer[i] = htole32(a); 2695 cur->qtd.qtd_buffer_hi[i] = 0; 2696 #ifdef DIAGNOSTIC 2697 if (i >= EHCI_QTD_NBUFFERS) { 2698 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2699 goto nomem; 2700 } 2701 #endif 2702 } 2703 cur->nextqtd = next; 2704 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2705 cur->qtd.qtd_status = 2706 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2707 cur->xfer = xfer; 2708 cur->len = curlen; 2709 2710 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2711 dataphys, dataphys + curlen)); 2712 /* adjust the toggle based on the number of packets in this 2713 qtd */ 2714 if (((curlen + mps - 1) / mps) & 1) { 2715 tog ^= 1; 2716 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2717 } 2718 if (next == NULL) 2719 break; 2720 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2721 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2722 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2723 dataphys += curlen; 2724 cur = next; 2725 } 2726 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2727 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2728 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2729 *ep = cur; 2730 epipe->nexttoggle = tog; 2731 2732 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2733 *sp, *ep)); 2734 2735 return (USBD_NORMAL_COMPLETION); 2736 2737 nomem: 2738 /* XXX free chain */ 2739 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2740 return (USBD_NOMEM); 2741 } 2742 2743 Static void 2744 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2745 ehci_soft_qtd_t *sqtdend) 2746 { 2747 ehci_soft_qtd_t *p; 2748 int i; 2749 2750 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2751 sqtd, sqtdend)); 2752 2753 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2754 p = sqtd->nextqtd; 2755 ehci_free_sqtd(sc, sqtd); 2756 } 2757 } 2758 2759 ehci_soft_itd_t * 2760 ehci_alloc_itd(ehci_softc_t *sc) 2761 { 2762 struct ehci_soft_itd *itd, *freeitd; 2763 usbd_status err; 2764 int i, s, offs, frindex, previndex; 2765 usb_dma_t dma; 2766 2767 s = splusb(); 2768 2769 /* Find an itd that wasn't freed this frame or last frame. This can 2770 * discard itds that were freed before frindex wrapped around 2771 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2772 * interrupt and fiddling with list when that happens */ 2773 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2774 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2775 2776 freeitd = NULL; 2777 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2778 if (itd == NULL) 2779 break; 2780 if (itd->slot != frindex && itd->slot != previndex) { 2781 freeitd = itd; 2782 break; 2783 } 2784 } 2785 2786 if (freeitd == NULL) { 2787 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2788 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2789 EHCI_PAGE_SIZE, &dma); 2790 2791 if (err) { 2792 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2793 return NULL; 2794 } 2795 2796 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2797 offs = i * EHCI_ITD_SIZE; 2798 itd = KERNADDR(&dma, offs); 2799 itd->physaddr = DMAADDR(&dma, offs); 2800 itd->dma = dma; 2801 itd->offs = offs; 2802 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2803 } 2804 freeitd = LIST_FIRST(&sc->sc_freeitds); 2805 } 2806 2807 itd = freeitd; 2808 LIST_REMOVE(itd, u.free_list); 2809 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2810 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2811 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2812 BUS_DMASYNC_PREREAD); 2813 2814 itd->u.frame_list.next = NULL; 2815 itd->u.frame_list.prev = NULL; 2816 itd->xfer_next = NULL; 2817 itd->slot = 0; 2818 splx(s); 2819 2820 return itd; 2821 } 2822 2823 void 2824 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2825 { 2826 int s; 2827 2828 s = splusb(); 2829 LIST_INSERT_AFTER(LIST_FIRST(&sc->sc_freeitds), itd, u.free_list); 2830 splx(s); 2831 } 2832 2833 2834 2835 /****************/ 2836 2837 /* 2838 * Close a reqular pipe. 2839 * Assumes that there are no pending transactions. 2840 */ 2841 void 2842 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2843 { 2844 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2845 ehci_softc_t *sc = pipe->device->bus->hci_private; 2846 ehci_soft_qh_t *sqh = epipe->sqh; 2847 int s; 2848 2849 s = splusb(); 2850 ehci_rem_qh(sc, sqh, head); 2851 splx(s); 2852 ehci_free_sqh(sc, epipe->sqh); 2853 } 2854 2855 /* 2856 * Abort a device request. 2857 * If this routine is called at splusb() it guarantees that the request 2858 * will be removed from the hardware scheduling and that the callback 2859 * for it will be called with USBD_CANCELLED status. 2860 * It's impossible to guarantee that the requested transfer will not 2861 * have happened since the hardware runs concurrently. 2862 * If the transaction has already happened we rely on the ordinary 2863 * interrupt processing to process it. 2864 * XXX This is most probably wrong. 2865 */ 2866 void 2867 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2868 { 2869 #define exfer EXFER(xfer) 2870 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2871 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2872 ehci_soft_qh_t *sqh = epipe->sqh; 2873 ehci_soft_qtd_t *sqtd; 2874 ehci_physaddr_t cur; 2875 u_int32_t qhstatus; 2876 int s; 2877 int hit; 2878 int wake; 2879 2880 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2881 2882 if (sc->sc_dying) { 2883 /* If we're dying, just do the software part. */ 2884 s = splusb(); 2885 xfer->status = status; /* make software ignore it */ 2886 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2887 usb_transfer_complete(xfer); 2888 splx(s); 2889 return; 2890 } 2891 2892 if (xfer->device->bus->intr_context) 2893 panic("ehci_abort_xfer: not in process context"); 2894 2895 /* 2896 * If an abort is already in progress then just wait for it to 2897 * complete and return. 2898 */ 2899 if (xfer->hcflags & UXFER_ABORTING) { 2900 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2901 #ifdef DIAGNOSTIC 2902 if (status == USBD_TIMEOUT) 2903 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2904 #endif 2905 /* Override the status which might be USBD_TIMEOUT. */ 2906 xfer->status = status; 2907 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2908 xfer->hcflags |= UXFER_ABORTWAIT; 2909 while (xfer->hcflags & UXFER_ABORTING) 2910 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2911 return; 2912 } 2913 xfer->hcflags |= UXFER_ABORTING; 2914 2915 /* 2916 * Step 1: Make interrupt routine and hardware ignore xfer. 2917 */ 2918 s = splusb(); 2919 xfer->status = status; /* make software ignore it */ 2920 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2921 2922 usb_syncmem(&sqh->dma, 2923 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2924 sizeof(sqh->qh.qh_qtd.qtd_status), 2925 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2926 qhstatus = sqh->qh.qh_qtd.qtd_status; 2927 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2928 usb_syncmem(&sqh->dma, 2929 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2930 sizeof(sqh->qh.qh_qtd.qtd_status), 2931 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2932 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2933 usb_syncmem(&sqtd->dma, 2934 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2935 sizeof(sqtd->qtd.qtd_status), 2936 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2937 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2938 usb_syncmem(&sqtd->dma, 2939 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2940 sizeof(sqtd->qtd.qtd_status), 2941 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2942 if (sqtd == exfer->sqtdend) 2943 break; 2944 } 2945 splx(s); 2946 2947 /* 2948 * Step 2: Wait until we know hardware has finished any possible 2949 * use of the xfer. Also make sure the soft interrupt routine 2950 * has run. 2951 */ 2952 ehci_sync_hc(sc); 2953 s = splusb(); 2954 #ifdef USB_USE_SOFTINTR 2955 sc->sc_softwake = 1; 2956 #endif /* USB_USE_SOFTINTR */ 2957 usb_schedsoftintr(&sc->sc_bus); 2958 #ifdef USB_USE_SOFTINTR 2959 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2960 #endif /* USB_USE_SOFTINTR */ 2961 splx(s); 2962 2963 /* 2964 * Step 3: Remove any vestiges of the xfer from the hardware. 2965 * The complication here is that the hardware may have executed 2966 * beyond the xfer we're trying to abort. So as we're scanning 2967 * the TDs of this xfer we check if the hardware points to 2968 * any of them. 2969 */ 2970 s = splusb(); /* XXX why? */ 2971 2972 usb_syncmem(&sqh->dma, 2973 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2974 sizeof(sqh->qh.qh_curqtd), 2975 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2976 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2977 hit = 0; 2978 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2979 hit |= cur == sqtd->physaddr; 2980 if (sqtd == exfer->sqtdend) 2981 break; 2982 } 2983 sqtd = sqtd->nextqtd; 2984 /* Zap curqtd register if hardware pointed inside the xfer. */ 2985 if (hit && sqtd != NULL) { 2986 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 2987 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 2988 usb_syncmem(&sqh->dma, 2989 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2990 sizeof(sqh->qh.qh_curqtd), 2991 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2992 sqh->qh.qh_qtd.qtd_status = qhstatus; 2993 usb_syncmem(&sqh->dma, 2994 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2995 sizeof(sqh->qh.qh_qtd.qtd_status), 2996 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2997 } else { 2998 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2999 } 3000 3001 /* 3002 * Step 4: Execute callback. 3003 */ 3004 #ifdef DIAGNOSTIC 3005 exfer->isdone = 1; 3006 #endif 3007 wake = xfer->hcflags & UXFER_ABORTWAIT; 3008 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3009 usb_transfer_complete(xfer); 3010 if (wake) 3011 wakeup(&xfer->hcflags); 3012 3013 splx(s); 3014 #undef exfer 3015 } 3016 3017 void 3018 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3019 { 3020 ehci_isoc_trans_t trans_status; 3021 struct ehci_pipe *epipe; 3022 struct ehci_xfer *exfer; 3023 ehci_softc_t *sc; 3024 struct ehci_soft_itd *itd; 3025 int s, i, wake; 3026 3027 epipe = (struct ehci_pipe *) xfer->pipe; 3028 exfer = EXFER(xfer); 3029 sc = epipe->pipe.device->bus->hci_private; 3030 3031 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3032 3033 if (sc->sc_dying) { 3034 s = splusb(); 3035 xfer->status = status; 3036 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3037 usb_transfer_complete(xfer); 3038 splx(s); 3039 return; 3040 } 3041 3042 if (xfer->hcflags & UXFER_ABORTING) { 3043 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3044 3045 #ifdef DIAGNOSTIC 3046 if (status == USBD_TIMEOUT) 3047 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3048 #endif 3049 3050 xfer->status = status; 3051 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3052 xfer->hcflags |= UXFER_ABORTWAIT; 3053 while (xfer->hcflags & UXFER_ABORTING) 3054 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0); 3055 return; 3056 } 3057 xfer->hcflags |= UXFER_ABORTING; 3058 3059 xfer->status = status; 3060 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3061 3062 s = splusb(); 3063 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3064 usb_syncmem(&itd->dma, 3065 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3066 sizeof(itd->itd.itd_ctl), 3067 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3068 3069 for (i = 0; i < 8; i++) { 3070 trans_status = le32toh(itd->itd.itd_ctl[i]); 3071 trans_status &= ~EHCI_ITD_ACTIVE; 3072 itd->itd.itd_ctl[i] = htole32(trans_status); 3073 } 3074 3075 usb_syncmem(&itd->dma, 3076 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3077 sizeof(itd->itd.itd_ctl), 3078 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3079 } 3080 splx(s); 3081 3082 s = splusb(); 3083 #ifdef USB_USE_SOFTINTR 3084 sc->sc_softwake = 1; 3085 #endif /* USB_USE_SOFTINTR */ 3086 usb_schedsoftintr(&sc->sc_bus); 3087 #ifdef USB_USE_SOFTINTR 3088 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3089 #endif /* USB_USE_SOFTINTR */ 3090 splx(s); 3091 3092 #ifdef DIAGNOSTIC 3093 exfer->isdone = 1; 3094 #endif 3095 wake = xfer->hcflags & UXFER_ABORTWAIT; 3096 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3097 usb_transfer_complete(xfer); 3098 if (wake) 3099 wakeup(&xfer->hcflags); 3100 3101 return; 3102 } 3103 3104 void 3105 ehci_timeout(void *addr) 3106 { 3107 struct ehci_xfer *exfer = addr; 3108 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3109 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3110 3111 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3112 #ifdef USB_DEBUG 3113 if (ehcidebug > 1) 3114 usbd_dump_pipe(exfer->xfer.pipe); 3115 #endif 3116 3117 if (sc->sc_dying) { 3118 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3119 return; 3120 } 3121 3122 /* Execute the abort in a process context. */ 3123 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3124 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3125 USB_TASKQ_HC); 3126 } 3127 3128 void 3129 ehci_timeout_task(void *addr) 3130 { 3131 usbd_xfer_handle xfer = addr; 3132 int s; 3133 3134 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3135 3136 s = splusb(); 3137 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3138 splx(s); 3139 } 3140 3141 /************************/ 3142 3143 Static usbd_status 3144 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3145 { 3146 usbd_status err; 3147 3148 /* Insert last in queue. */ 3149 err = usb_insert_transfer(xfer); 3150 if (err) 3151 return (err); 3152 3153 /* Pipe isn't running, start first */ 3154 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3155 } 3156 3157 Static usbd_status 3158 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3159 { 3160 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3161 usbd_status err; 3162 3163 if (sc->sc_dying) 3164 return (USBD_IOERROR); 3165 3166 #ifdef DIAGNOSTIC 3167 if (!(xfer->rqflags & URQ_REQUEST)) { 3168 /* XXX panic */ 3169 printf("ehci_device_ctrl_transfer: not a request\n"); 3170 return (USBD_INVAL); 3171 } 3172 #endif 3173 3174 err = ehci_device_request(xfer); 3175 if (err) 3176 return (err); 3177 3178 if (sc->sc_bus.use_polling) 3179 ehci_waitintr(sc, xfer); 3180 return (USBD_IN_PROGRESS); 3181 } 3182 3183 void 3184 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3185 { 3186 struct ehci_xfer *ex = EXFER(xfer); 3187 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3188 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3189 usb_device_request_t *req = &xfer->request; 3190 int len = UGETW(req->wLength); 3191 int rd = req->bmRequestType & UT_READ; 3192 3193 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3194 3195 #ifdef DIAGNOSTIC 3196 if (!(xfer->rqflags & URQ_REQUEST)) { 3197 panic("ehci_ctrl_done: not a request"); 3198 } 3199 #endif 3200 3201 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3202 ehci_del_intr_list(ex); /* remove from active list */ 3203 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3204 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3205 BUS_DMASYNC_POSTWRITE); 3206 if (len) 3207 usb_syncmem(&xfer->dmabuf, 0, len, 3208 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3209 } 3210 3211 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3212 } 3213 3214 /* Abort a device control request. */ 3215 Static void 3216 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3217 { 3218 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3219 ehci_abort_xfer(xfer, USBD_CANCELLED); 3220 } 3221 3222 /* Close a device control pipe. */ 3223 Static void 3224 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3225 { 3226 ehci_softc_t *sc = pipe->device->bus->hci_private; 3227 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3228 3229 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3230 ehci_close_pipe(pipe, sc->sc_async_head); 3231 } 3232 3233 usbd_status 3234 ehci_device_request(usbd_xfer_handle xfer) 3235 { 3236 #define exfer EXFER(xfer) 3237 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3238 usb_device_request_t *req = &xfer->request; 3239 usbd_device_handle dev = epipe->pipe.device; 3240 ehci_softc_t *sc = dev->bus->hci_private; 3241 int addr = dev->address; 3242 ehci_soft_qtd_t *setup, *stat, *next; 3243 ehci_soft_qh_t *sqh; 3244 int isread; 3245 int len; 3246 usbd_status err; 3247 int s; 3248 3249 isread = req->bmRequestType & UT_READ; 3250 len = UGETW(req->wLength); 3251 3252 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3253 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3254 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3255 UGETW(req->wIndex), len, addr, 3256 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3257 3258 setup = ehci_alloc_sqtd(sc); 3259 if (setup == NULL) { 3260 err = USBD_NOMEM; 3261 goto bad1; 3262 } 3263 stat = ehci_alloc_sqtd(sc); 3264 if (stat == NULL) { 3265 err = USBD_NOMEM; 3266 goto bad2; 3267 } 3268 3269 sqh = epipe->sqh; 3270 epipe->u.ctl.length = len; 3271 3272 /* Update device address and length since they may have changed 3273 during the setup of the control pipe in usbd_new_device(). */ 3274 /* XXX This only needs to be done once, but it's too early in open. */ 3275 /* XXXX Should not touch ED here! */ 3276 sqh->qh.qh_endp = 3277 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3278 htole32( 3279 EHCI_QH_SET_ADDR(addr) | 3280 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3281 ); 3282 3283 /* Set up data transaction */ 3284 if (len != 0) { 3285 ehci_soft_qtd_t *end; 3286 3287 /* Start toggle at 1. */ 3288 epipe->nexttoggle = 1; 3289 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3290 &next, &end); 3291 if (err) 3292 goto bad3; 3293 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3294 end->nextqtd = stat; 3295 end->qtd.qtd_next = 3296 end->qtd.qtd_altnext = htole32(stat->physaddr); 3297 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3298 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3299 } else { 3300 next = stat; 3301 } 3302 3303 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3304 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3305 3306 /* Clear toggle */ 3307 setup->qtd.qtd_status = htole32( 3308 EHCI_QTD_ACTIVE | 3309 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3310 EHCI_QTD_SET_CERR(3) | 3311 EHCI_QTD_SET_TOGGLE(0) | 3312 EHCI_QTD_SET_BYTES(sizeof *req) 3313 ); 3314 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3315 setup->qtd.qtd_buffer_hi[0] = 0; 3316 setup->nextqtd = next; 3317 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3318 setup->xfer = xfer; 3319 setup->len = sizeof *req; 3320 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3321 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3322 3323 stat->qtd.qtd_status = htole32( 3324 EHCI_QTD_ACTIVE | 3325 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3326 EHCI_QTD_SET_CERR(3) | 3327 EHCI_QTD_SET_TOGGLE(1) | 3328 EHCI_QTD_IOC 3329 ); 3330 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3331 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3332 stat->nextqtd = NULL; 3333 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3334 stat->xfer = xfer; 3335 stat->len = 0; 3336 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3337 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3338 3339 #ifdef EHCI_DEBUG 3340 if (ehcidebug > 5) { 3341 DPRINTF(("ehci_device_request:\n")); 3342 ehci_dump_sqh(sqh); 3343 ehci_dump_sqtds(setup); 3344 } 3345 #endif 3346 3347 exfer->sqtdstart = setup; 3348 exfer->sqtdend = stat; 3349 #ifdef DIAGNOSTIC 3350 if (!exfer->isdone) { 3351 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3352 } 3353 exfer->isdone = 0; 3354 #endif 3355 3356 /* Insert qTD in QH list. */ 3357 s = splusb(); 3358 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3359 if (xfer->timeout && !sc->sc_bus.use_polling) { 3360 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3361 ehci_timeout, xfer); 3362 } 3363 ehci_add_intr_list(sc, exfer); 3364 xfer->status = USBD_IN_PROGRESS; 3365 splx(s); 3366 3367 #ifdef EHCI_DEBUG 3368 if (ehcidebug > 10) { 3369 DPRINTF(("ehci_device_request: status=%x\n", 3370 EOREAD4(sc, EHCI_USBSTS))); 3371 delay(10000); 3372 ehci_dump_regs(sc); 3373 ehci_dump_sqh(sc->sc_async_head); 3374 ehci_dump_sqh(sqh); 3375 ehci_dump_sqtds(setup); 3376 } 3377 #endif 3378 3379 return (USBD_NORMAL_COMPLETION); 3380 3381 bad3: 3382 ehci_free_sqtd(sc, stat); 3383 bad2: 3384 ehci_free_sqtd(sc, setup); 3385 bad1: 3386 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3387 xfer->status = err; 3388 usb_transfer_complete(xfer); 3389 return (err); 3390 #undef exfer 3391 } 3392 3393 /* 3394 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3395 * qTD status, or miss signalling occasionally under heavy load. If the host 3396 * machine is too fast, we we can miss transaction completion - when we scan 3397 * the active list the transaction still seems to be active. This generally 3398 * exhibits itself as a umass stall that never recovers. 3399 * 3400 * We work around this behaviour by setting up this callback after any softintr 3401 * that completes with transactions still pending, giving us another chance to 3402 * check for completion after the writeback has taken place. 3403 */ 3404 void 3405 ehci_intrlist_timeout(void *arg) 3406 { 3407 ehci_softc_t *sc = arg; 3408 int s = splusb(); 3409 3410 DPRINTF(("ehci_intrlist_timeout\n")); 3411 usb_schedsoftintr(&sc->sc_bus); 3412 3413 splx(s); 3414 } 3415 3416 /************************/ 3417 3418 Static usbd_status 3419 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3420 { 3421 usbd_status err; 3422 3423 /* Insert last in queue. */ 3424 err = usb_insert_transfer(xfer); 3425 if (err) 3426 return (err); 3427 3428 /* Pipe isn't running, start first */ 3429 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3430 } 3431 3432 usbd_status 3433 ehci_device_bulk_start(usbd_xfer_handle xfer) 3434 { 3435 #define exfer EXFER(xfer) 3436 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3437 usbd_device_handle dev = epipe->pipe.device; 3438 ehci_softc_t *sc = dev->bus->hci_private; 3439 ehci_soft_qtd_t *data, *dataend; 3440 ehci_soft_qh_t *sqh; 3441 usbd_status err; 3442 int len, isread, endpt; 3443 int s; 3444 3445 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3446 xfer, xfer->length, xfer->flags)); 3447 3448 if (sc->sc_dying) 3449 return (USBD_IOERROR); 3450 3451 #ifdef DIAGNOSTIC 3452 if (xfer->rqflags & URQ_REQUEST) 3453 panic("ehci_device_bulk_start: a request"); 3454 #endif 3455 3456 len = xfer->length; 3457 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3458 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3459 sqh = epipe->sqh; 3460 3461 epipe->u.bulk.length = len; 3462 3463 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3464 &dataend); 3465 if (err) { 3466 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3467 xfer->status = err; 3468 usb_transfer_complete(xfer); 3469 return (err); 3470 } 3471 3472 #ifdef EHCI_DEBUG 3473 if (ehcidebug > 5) { 3474 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3475 ehci_dump_sqh(sqh); 3476 ehci_dump_sqtds(data); 3477 } 3478 #endif 3479 3480 /* Set up interrupt info. */ 3481 exfer->sqtdstart = data; 3482 exfer->sqtdend = dataend; 3483 #ifdef DIAGNOSTIC 3484 if (!exfer->isdone) { 3485 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3486 } 3487 exfer->isdone = 0; 3488 #endif 3489 3490 s = splusb(); 3491 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3492 if (xfer->timeout && !sc->sc_bus.use_polling) { 3493 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3494 ehci_timeout, xfer); 3495 } 3496 ehci_add_intr_list(sc, exfer); 3497 xfer->status = USBD_IN_PROGRESS; 3498 splx(s); 3499 3500 #ifdef EHCI_DEBUG 3501 if (ehcidebug > 10) { 3502 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3503 delay(10000); 3504 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3505 ehci_dump_regs(sc); 3506 #if 0 3507 printf("async_head:\n"); 3508 ehci_dump_sqh(sc->sc_async_head); 3509 #endif 3510 printf("sqh:\n"); 3511 ehci_dump_sqh(sqh); 3512 ehci_dump_sqtds(data); 3513 } 3514 #endif 3515 3516 if (sc->sc_bus.use_polling) 3517 ehci_waitintr(sc, xfer); 3518 3519 return (USBD_IN_PROGRESS); 3520 #undef exfer 3521 } 3522 3523 Static void 3524 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3525 { 3526 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3527 ehci_abort_xfer(xfer, USBD_CANCELLED); 3528 } 3529 3530 /* 3531 * Close a device bulk pipe. 3532 */ 3533 Static void 3534 ehci_device_bulk_close(usbd_pipe_handle pipe) 3535 { 3536 ehci_softc_t *sc = pipe->device->bus->hci_private; 3537 3538 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3539 ehci_close_pipe(pipe, sc->sc_async_head); 3540 } 3541 3542 void 3543 ehci_device_bulk_done(usbd_xfer_handle xfer) 3544 { 3545 struct ehci_xfer *ex = EXFER(xfer); 3546 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3547 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3548 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3549 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3550 3551 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3552 xfer, xfer->actlen)); 3553 3554 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3555 ehci_del_intr_list(ex); /* remove from active list */ 3556 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3557 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3558 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3559 } 3560 3561 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3562 } 3563 3564 /************************/ 3565 3566 Static usbd_status 3567 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3568 { 3569 struct ehci_soft_islot *isp; 3570 int islot, lev; 3571 3572 /* Find a poll rate that is large enough. */ 3573 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3574 if (EHCI_ILEV_IVAL(lev) <= ival) 3575 break; 3576 3577 /* Pick an interrupt slot at the right level. */ 3578 /* XXX could do better than picking at random */ 3579 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3580 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3581 3582 sqh->islot = islot; 3583 isp = &sc->sc_islots[islot]; 3584 ehci_add_qh(sqh, isp->sqh); 3585 3586 return (USBD_NORMAL_COMPLETION); 3587 } 3588 3589 Static usbd_status 3590 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3591 { 3592 usbd_status err; 3593 3594 /* Insert last in queue. */ 3595 err = usb_insert_transfer(xfer); 3596 if (err) 3597 return (err); 3598 3599 /* 3600 * Pipe isn't running (otherwise err would be USBD_INPROG), 3601 * so start it first. 3602 */ 3603 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3604 } 3605 3606 Static usbd_status 3607 ehci_device_intr_start(usbd_xfer_handle xfer) 3608 { 3609 #define exfer EXFER(xfer) 3610 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3611 usbd_device_handle dev = xfer->pipe->device; 3612 ehci_softc_t *sc = dev->bus->hci_private; 3613 ehci_soft_qtd_t *data, *dataend; 3614 ehci_soft_qh_t *sqh; 3615 usbd_status err; 3616 int len, isread, endpt; 3617 int s; 3618 3619 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3620 xfer, xfer->length, xfer->flags)); 3621 3622 if (sc->sc_dying) 3623 return (USBD_IOERROR); 3624 3625 #ifdef DIAGNOSTIC 3626 if (xfer->rqflags & URQ_REQUEST) 3627 panic("ehci_device_intr_start: a request"); 3628 #endif 3629 3630 len = xfer->length; 3631 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3632 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3633 sqh = epipe->sqh; 3634 3635 epipe->u.intr.length = len; 3636 3637 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3638 &dataend); 3639 if (err) { 3640 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3641 xfer->status = err; 3642 usb_transfer_complete(xfer); 3643 return (err); 3644 } 3645 3646 #ifdef EHCI_DEBUG 3647 if (ehcidebug > 5) { 3648 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3649 ehci_dump_sqh(sqh); 3650 ehci_dump_sqtds(data); 3651 } 3652 #endif 3653 3654 /* Set up interrupt info. */ 3655 exfer->sqtdstart = data; 3656 exfer->sqtdend = dataend; 3657 #ifdef DIAGNOSTIC 3658 if (!exfer->isdone) { 3659 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3660 } 3661 exfer->isdone = 0; 3662 #endif 3663 3664 s = splusb(); 3665 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3666 if (xfer->timeout && !sc->sc_bus.use_polling) { 3667 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3668 ehci_timeout, xfer); 3669 } 3670 ehci_add_intr_list(sc, exfer); 3671 xfer->status = USBD_IN_PROGRESS; 3672 splx(s); 3673 3674 #ifdef EHCI_DEBUG 3675 if (ehcidebug > 10) { 3676 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3677 delay(10000); 3678 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3679 ehci_dump_regs(sc); 3680 printf("sqh:\n"); 3681 ehci_dump_sqh(sqh); 3682 ehci_dump_sqtds(data); 3683 } 3684 #endif 3685 3686 if (sc->sc_bus.use_polling) 3687 ehci_waitintr(sc, xfer); 3688 3689 return (USBD_IN_PROGRESS); 3690 #undef exfer 3691 } 3692 3693 Static void 3694 ehci_device_intr_abort(usbd_xfer_handle xfer) 3695 { 3696 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3697 if (xfer->pipe->intrxfer == xfer) { 3698 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3699 xfer->pipe->intrxfer = NULL; 3700 } 3701 /* 3702 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3703 * async doorbell. That's dependant on the async list, wheras 3704 * intr xfers are periodic, should not use this? 3705 */ 3706 ehci_abort_xfer(xfer, USBD_CANCELLED); 3707 } 3708 3709 Static void 3710 ehci_device_intr_close(usbd_pipe_handle pipe) 3711 { 3712 ehci_softc_t *sc = pipe->device->bus->hci_private; 3713 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3714 struct ehci_soft_islot *isp; 3715 3716 isp = &sc->sc_islots[epipe->sqh->islot]; 3717 ehci_close_pipe(pipe, isp->sqh); 3718 } 3719 3720 Static void 3721 ehci_device_intr_done(usbd_xfer_handle xfer) 3722 { 3723 #define exfer EXFER(xfer) 3724 struct ehci_xfer *ex = EXFER(xfer); 3725 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3726 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3727 ehci_soft_qtd_t *data, *dataend; 3728 ehci_soft_qh_t *sqh; 3729 usbd_status err; 3730 int len, isread, endpt, s; 3731 3732 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3733 xfer, xfer->actlen)); 3734 3735 if (xfer->pipe->repeat) { 3736 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3737 3738 len = epipe->u.intr.length; 3739 xfer->length = len; 3740 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3741 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3742 usb_syncmem(&xfer->dmabuf, 0, len, 3743 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3744 sqh = epipe->sqh; 3745 3746 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3747 &data, &dataend); 3748 if (err) { 3749 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3750 xfer->status = err; 3751 return; 3752 } 3753 3754 /* Set up interrupt info. */ 3755 exfer->sqtdstart = data; 3756 exfer->sqtdend = dataend; 3757 #ifdef DIAGNOSTIC 3758 if (!exfer->isdone) { 3759 printf("ehci_device_intr_done: not done, ex=%p\n", 3760 exfer); 3761 } 3762 exfer->isdone = 0; 3763 #endif 3764 3765 s = splusb(); 3766 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3767 if (xfer->timeout && !sc->sc_bus.use_polling) { 3768 usb_callout(xfer->timeout_handle, 3769 mstohz(xfer->timeout), ehci_timeout, xfer); 3770 } 3771 splx(s); 3772 3773 xfer->status = USBD_IN_PROGRESS; 3774 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3775 ehci_del_intr_list(ex); /* remove from active list */ 3776 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3777 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3778 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3779 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3780 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3781 } 3782 #undef exfer 3783 } 3784 3785 /************************/ 3786 3787 Static usbd_status 3788 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3789 { 3790 usbd_status err; 3791 3792 err = usb_insert_transfer(xfer); 3793 if (err && err != USBD_IN_PROGRESS) 3794 return err; 3795 3796 return ehci_device_isoc_start(xfer); 3797 } 3798 3799 Static usbd_status 3800 ehci_device_isoc_start(usbd_xfer_handle xfer) 3801 { 3802 struct ehci_pipe *epipe; 3803 usbd_device_handle dev; 3804 ehci_softc_t *sc; 3805 struct ehci_xfer *exfer; 3806 ehci_soft_itd_t *itd, *prev, *start, *stop; 3807 usb_dma_t *dma_buf; 3808 int i, j, k, frames, uframes; 3809 int s, trans_count, offs, total_length; 3810 int frindex; 3811 3812 start = NULL; 3813 prev = NULL; 3814 itd = NULL; 3815 trans_count = 0; 3816 total_length = 0; 3817 exfer = (struct ehci_xfer *) xfer; 3818 sc = xfer->pipe->device->bus->hci_private; 3819 dev = xfer->pipe->device; 3820 epipe = (struct ehci_pipe *)xfer->pipe; 3821 3822 /* 3823 * To allow continuous transfers, above we start all transfers 3824 * immediately. However, we're still going to get usbd_start_next call 3825 * this when another xfer completes. So, check if this is already 3826 * in progress or not 3827 */ 3828 3829 if (exfer->itdstart != NULL) 3830 return USBD_IN_PROGRESS; 3831 3832 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3833 xfer, xfer->length, xfer->flags)); 3834 3835 if (sc->sc_dying) 3836 return USBD_IOERROR; 3837 3838 /* 3839 * To avoid complication, don't allow a request right now that'll span 3840 * the entire frame table. To within 4 frames, to allow some leeway 3841 * on either side of where the hc currently is. 3842 */ 3843 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3844 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3845 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3846 return USBD_INVAL; 3847 } 3848 3849 #ifdef DIAGNOSTIC 3850 if (xfer->rqflags & URQ_REQUEST) 3851 panic("ehci_device_isoc_start: request\n"); 3852 3853 if (!exfer->isdone) 3854 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3855 exfer->isdone = 0; 3856 #endif 3857 3858 /* 3859 * Step 1: Allocate and initialize itds, how many do we need? 3860 * One per transfer if interval >= 8 microframes, fewer if we use 3861 * multiple microframes per frame. 3862 */ 3863 3864 i = epipe->pipe.endpoint->edesc->bInterval; 3865 if (i > 16 || i == 0) { 3866 /* Spec page 271 says intervals > 16 are invalid */ 3867 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3868 return USBD_INVAL; 3869 } else if (i >= 4) { 3870 frames = xfer->nframes; 3871 uframes = 8; 3872 } else { 3873 frames = xfer->nframes + 0x7; /* 7 added for rounding up */ 3874 uframes = 0; 3875 switch (i) { 3876 case 1: frames /= 8; uframes = 1; break; 3877 case 2: frames /= 4; uframes = 2; break; 3878 case 3: frames /= 2; uframes = 4; break; 3879 } 3880 } 3881 3882 if (frames == 0) { 3883 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3884 return USBD_INVAL; 3885 } 3886 3887 dma_buf = &xfer->dmabuf; 3888 offs = 0; 3889 3890 for (i = 0; i < frames; i++) { 3891 int froffs = offs; 3892 itd = ehci_alloc_itd(sc); 3893 3894 if (prev != NULL) { 3895 prev->itd.itd_next = 3896 htole32(itd->physaddr | EHCI_LINK_ITD); 3897 usb_syncmem(&itd->dma, 3898 itd->offs + offsetof(ehci_itd_t, itd_next), 3899 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 3900 3901 prev->xfer_next = itd; 3902 } else { 3903 start = itd; 3904 } 3905 3906 /* 3907 * Step 1.5, initialize uframes 3908 */ 3909 for (j = 0; j < 8; j += uframes) { 3910 /* Calculate which page in the list this starts in */ 3911 int addr = DMAADDR(dma_buf, froffs); 3912 addr = EHCI_PAGE_OFFSET(addr); 3913 addr += (offs - froffs); 3914 addr = EHCI_PAGE(addr); 3915 addr /= EHCI_PAGE_SIZE; 3916 3917 /* This gets the initial offset into the first page, 3918 * looks how far further along the current uframe 3919 * offset is. Works out how many pages that is. 3920 */ 3921 3922 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3923 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3924 EHCI_ITD_SET_PG(addr) | 3925 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 3926 3927 total_length += xfer->frlengths[trans_count]; 3928 offs += xfer->frlengths[trans_count]; 3929 trans_count++; 3930 3931 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3932 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3933 } 3934 } 3935 3936 /* Step 1.75, set buffer pointers. To simplify matters, all 3937 * pointers are filled out for the next 7 hardware pages in 3938 * the dma block, so no need to worry what pages to cover 3939 * and what to not. 3940 */ 3941 3942 for (j=0; j < 7; j++) { 3943 /* 3944 * Don't try to lookup a page that's past the end 3945 * of buffer 3946 */ 3947 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 3948 if (page_offs >= dma_buf->block->size) 3949 break; 3950 3951 int page = DMAADDR(dma_buf, page_offs); 3952 page = EHCI_PAGE(page); 3953 itd->itd.itd_bufr[j] = 3954 htole32(EHCI_ITD_SET_BPTR(page) | 3955 EHCI_LINK_ITD); 3956 } 3957 3958 /* 3959 * Other special values 3960 */ 3961 3962 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3963 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3964 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3965 3966 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3967 ? 1 : 0; 3968 j = UE_GET_SIZE(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)); 3969 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3970 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3971 3972 /* FIXME: handle invalid trans */ 3973 itd->itd.itd_bufr[2] |= 3974 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3975 3976 usb_syncmem(&itd->dma, 3977 itd->offs + offsetof(ehci_itd_t, itd_next), 3978 sizeof(ehci_itd_t), 3979 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3980 3981 prev = itd; 3982 } /* End of frame */ 3983 3984 stop = itd; 3985 stop->xfer_next = NULL; 3986 exfer->isoc_len = total_length; 3987 3988 /* 3989 * Part 2: Transfer descriptors have now been set up, now they must 3990 * be scheduled into the period frame list. Erk. Not wanting to 3991 * complicate matters, transfer is denied if the transfer spans 3992 * more than the period frame list. 3993 */ 3994 3995 s = splusb(); 3996 3997 /* Start inserting frames */ 3998 if (epipe->u.isoc.cur_xfers > 0) { 3999 frindex = epipe->u.isoc.next_frame; 4000 } else { 4001 frindex = EOREAD4(sc, EHCI_FRINDEX); 4002 frindex = frindex >> 3; /* Erase microframe index */ 4003 frindex += 2; 4004 } 4005 4006 if (frindex >= sc->sc_flsize) 4007 frindex &= (sc->sc_flsize - 1); 4008 4009 /* Whats the frame interval? */ 4010 i = (1 << epipe->pipe.endpoint->edesc->bInterval); 4011 if (i / 8 == 0) 4012 i = 1; 4013 else 4014 i /= 8; 4015 4016 itd = start; 4017 for (j = 0; j < frames; j++) { 4018 if (itd == NULL) 4019 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4020 4021 itd->itd.itd_next = sc->sc_flist[frindex]; 4022 if (itd->itd.itd_next == 0) 4023 /* FIXME: frindex table gets initialized to NULL 4024 * or EHCI_NULL? */ 4025 itd->itd.itd_next = htole32(EHCI_NULL); 4026 4027 usb_syncmem(&itd->dma, 4028 itd->offs + offsetof(ehci_itd_t, itd_next), 4029 sizeof(itd->itd.itd_next), 4030 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4031 4032 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4033 4034 usb_syncmem(&sc->sc_fldma, 4035 sizeof(ehci_link_t) * frindex, 4036 sizeof(ehci_link_t), 4037 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4038 4039 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4040 sc->sc_softitds[frindex] = itd; 4041 if (itd->u.frame_list.next != NULL) 4042 itd->u.frame_list.next->u.frame_list.prev = itd; 4043 itd->slot = frindex; 4044 itd->u.frame_list.prev = NULL; 4045 4046 frindex += i; 4047 if (frindex >= sc->sc_flsize) 4048 frindex -= sc->sc_flsize; 4049 4050 itd = itd->xfer_next; 4051 } 4052 4053 epipe->u.isoc.cur_xfers++; 4054 epipe->u.isoc.next_frame = frindex; 4055 4056 exfer->itdstart = start; 4057 exfer->itdend = stop; 4058 exfer->sqtdstart = NULL; 4059 exfer->sqtdstart = NULL; 4060 4061 ehci_add_intr_list(sc, exfer); 4062 xfer->status = USBD_IN_PROGRESS; 4063 xfer->done = 0; 4064 splx(s); 4065 4066 if (sc->sc_bus.use_polling) { 4067 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4068 ehci_waitintr(sc, xfer); 4069 } 4070 4071 return USBD_IN_PROGRESS; 4072 } 4073 4074 Static void 4075 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4076 { 4077 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4078 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4079 } 4080 4081 Static void 4082 ehci_device_isoc_close(usbd_pipe_handle pipe) 4083 { 4084 printf("ehci_device_isoc_close: nothing in the pipe to free?\n"); 4085 } 4086 4087 Static void 4088 ehci_device_isoc_done(usbd_xfer_handle xfer) 4089 { 4090 struct ehci_xfer *exfer; 4091 ehci_softc_t *sc; 4092 struct ehci_pipe *epipe; 4093 int s; 4094 4095 exfer = EXFER(xfer); 4096 sc = xfer->pipe->device->bus->hci_private; 4097 epipe = (struct ehci_pipe *) xfer->pipe; 4098 4099 s = splusb(); 4100 epipe->u.isoc.cur_xfers--; 4101 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4102 ehci_del_intr_list(exfer); 4103 ehci_rem_free_itd_chain(sc, exfer); 4104 } 4105 splx(s); 4106 4107 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4108 BUS_DMASYNC_POSTREAD); 4109 4110 } 4111
Indexes created Mon Sep 22 13:09:51 GMT 2025