ehci.c revision 1.141
1 /* $NetBSD: ehci.c,v 1.141 2008/08/03 07:05:22 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2004,2005 The NetBSD Foundation, Inc. 5 * Copyright (c) 2008 Jeremy Morse <jeremy.morse (at) gmail.com> 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Lennart Augustsson (lennart (at) augustsson.net) and by Charles M. Hannum. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 35 * 36 * The EHCI 1.0 spec can be found at 37 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/usb_20.zip 40 * 41 */ 42 43 /* 44 * TODO: 45 * 1) hold off explorations by companion controllers until ehci has started. 46 * 47 * 2) The EHCI driver lacks support for isochronous transfers, so 48 * devices using them don't work. 49 * 50 * 3) The hub driver needs to handle and schedule the transaction translator, 51 * to assign place in frame where different devices get to go. See chapter 52 * on hubs in USB 2.0 for details. 53 * 54 * 4) command failures are not recovered correctly 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.141 2008/08/03 07:05:22 cegger Exp $"); 59 60 #include "ohci.h" 61 #include "uhci.h" 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/kernel.h> 66 #include <sys/malloc.h> 67 #include <sys/device.h> 68 #include <sys/select.h> 69 #include <sys/proc.h> 70 #include <sys/queue.h> 71 #include <sys/mutex.h> 72 #include <sys/bus.h> 73 74 #include <machine/endian.h> 75 76 #include <dev/usb/usb.h> 77 #include <dev/usb/usbdi.h> 78 #include <dev/usb/usbdivar.h> 79 #include <dev/usb/usb_mem.h> 80 #include <dev/usb/usb_quirks.h> 81 82 #include <dev/usb/ehcireg.h> 83 #include <dev/usb/ehcivar.h> 84 #include <dev/usb/usbroothub_subr.h> 85 86 #ifdef EHCI_DEBUG 87 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 88 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 89 int ehcidebug = 0; 90 #ifndef __NetBSD__ 91 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 92 #endif 93 #else 94 #define DPRINTF(x) 95 #define DPRINTFN(n,x) 96 #endif 97 98 struct ehci_pipe { 99 struct usbd_pipe pipe; 100 int nexttoggle; 101 102 ehci_soft_qh_t *sqh; 103 union { 104 ehci_soft_qtd_t *qtd; 105 /* ehci_soft_itd_t *itd; */ 106 } tail; 107 union { 108 /* Control pipe */ 109 struct { 110 usb_dma_t reqdma; 111 u_int length; 112 } ctl; 113 /* Interrupt pipe */ 114 struct { 115 u_int length; 116 } intr; 117 /* Bulk pipe */ 118 struct { 119 u_int length; 120 } bulk; 121 /* Iso pipe */ 122 struct { 123 u_int next_frame; 124 u_int cur_xfers; 125 } isoc; 126 } u; 127 }; 128 129 Static usbd_status ehci_open(usbd_pipe_handle); 130 Static void ehci_poll(struct usbd_bus *); 131 Static void ehci_softintr(void *); 132 Static int ehci_intr1(ehci_softc_t *); 133 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 134 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 135 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 136 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 137 Static void ehci_idone(struct ehci_xfer *); 138 Static void ehci_timeout(void *); 139 Static void ehci_timeout_task(void *); 140 Static void ehci_intrlist_timeout(void *); 141 142 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 143 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 144 145 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 146 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 147 148 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 149 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 150 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 151 Static void ehci_root_ctrl_close(usbd_pipe_handle); 152 Static void ehci_root_ctrl_done(usbd_xfer_handle); 153 154 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 155 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 156 Static void ehci_root_intr_abort(usbd_xfer_handle); 157 Static void ehci_root_intr_close(usbd_pipe_handle); 158 Static void ehci_root_intr_done(usbd_xfer_handle); 159 160 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 161 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 162 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 163 Static void ehci_device_ctrl_close(usbd_pipe_handle); 164 Static void ehci_device_ctrl_done(usbd_xfer_handle); 165 166 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 167 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 168 Static void ehci_device_bulk_abort(usbd_xfer_handle); 169 Static void ehci_device_bulk_close(usbd_pipe_handle); 170 Static void ehci_device_bulk_done(usbd_xfer_handle); 171 172 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 173 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 174 Static void ehci_device_intr_abort(usbd_xfer_handle); 175 Static void ehci_device_intr_close(usbd_pipe_handle); 176 Static void ehci_device_intr_done(usbd_xfer_handle); 177 178 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 179 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 180 Static void ehci_device_isoc_abort(usbd_xfer_handle); 181 Static void ehci_device_isoc_close(usbd_pipe_handle); 182 Static void ehci_device_isoc_done(usbd_xfer_handle); 183 184 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 185 Static void ehci_noop(usbd_pipe_handle pipe); 186 187 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 188 Static void ehci_disown(ehci_softc_t *, int, int); 189 190 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 191 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 192 193 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 194 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 195 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 196 ehci_softc_t *, int, int, usbd_xfer_handle, 197 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 198 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 199 ehci_soft_qtd_t *); 200 201 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 202 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 203 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 204 struct ehci_xfer *exfer); 205 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 206 usbd_status status); 207 208 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 209 210 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 211 int ival); 212 213 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 214 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 215 ehci_soft_qh_t *); 216 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 217 Static void ehci_sync_hc(ehci_softc_t *); 218 219 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 220 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 221 222 #ifdef EHCI_DEBUG 223 Static void ehci_dump_regs(ehci_softc_t *); 224 void ehci_dump(void); 225 Static ehci_softc_t *theehci; 226 Static void ehci_dump_link(ehci_link_t, int); 227 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 228 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 229 Static void ehci_dump_qtd(ehci_qtd_t *); 230 Static void ehci_dump_sqh(ehci_soft_qh_t *); 231 #if notyet 232 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 233 Static void ehci_dump_itd(struct ehci_soft_itd *); 234 #endif 235 #ifdef DIAGNOSTIC 236 Static void ehci_dump_exfer(struct ehci_xfer *); 237 #endif 238 #endif 239 240 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 241 242 #define EHCI_INTR_ENDPT 1 243 244 #define ehci_add_intr_list(sc, ex) \ 245 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext); 246 #define ehci_del_intr_list(ex) \ 247 do { \ 248 LIST_REMOVE((ex), inext); \ 249 (ex)->inext.le_prev = NULL; \ 250 } while (0) 251 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL) 252 253 Static const struct usbd_bus_methods ehci_bus_methods = { 254 ehci_open, 255 ehci_softintr, 256 ehci_poll, 257 ehci_allocm, 258 ehci_freem, 259 ehci_allocx, 260 ehci_freex, 261 }; 262 263 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 264 ehci_root_ctrl_transfer, 265 ehci_root_ctrl_start, 266 ehci_root_ctrl_abort, 267 ehci_root_ctrl_close, 268 ehci_noop, 269 ehci_root_ctrl_done, 270 }; 271 272 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 273 ehci_root_intr_transfer, 274 ehci_root_intr_start, 275 ehci_root_intr_abort, 276 ehci_root_intr_close, 277 ehci_noop, 278 ehci_root_intr_done, 279 }; 280 281 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 282 ehci_device_ctrl_transfer, 283 ehci_device_ctrl_start, 284 ehci_device_ctrl_abort, 285 ehci_device_ctrl_close, 286 ehci_noop, 287 ehci_device_ctrl_done, 288 }; 289 290 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 291 ehci_device_intr_transfer, 292 ehci_device_intr_start, 293 ehci_device_intr_abort, 294 ehci_device_intr_close, 295 ehci_device_clear_toggle, 296 ehci_device_intr_done, 297 }; 298 299 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 300 ehci_device_bulk_transfer, 301 ehci_device_bulk_start, 302 ehci_device_bulk_abort, 303 ehci_device_bulk_close, 304 ehci_device_clear_toggle, 305 ehci_device_bulk_done, 306 }; 307 308 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 309 ehci_device_isoc_transfer, 310 ehci_device_isoc_start, 311 ehci_device_isoc_abort, 312 ehci_device_isoc_close, 313 ehci_noop, 314 ehci_device_isoc_done, 315 }; 316 317 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 318 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 319 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 320 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 321 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 322 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 323 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 324 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 325 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 326 }; 327 328 usbd_status 329 ehci_init(ehci_softc_t *sc) 330 { 331 u_int32_t vers, sparams, cparams, hcr; 332 u_int i; 333 usbd_status err; 334 ehci_soft_qh_t *sqh; 335 u_int ncomp; 336 337 DPRINTF(("ehci_init: start\n")); 338 #ifdef EHCI_DEBUG 339 theehci = sc; 340 #endif 341 342 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 343 344 vers = EREAD2(sc, EHCI_HCIVERSION); 345 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 346 vers >> 8, vers & 0xff); 347 348 sparams = EREAD4(sc, EHCI_HCSPARAMS); 349 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 350 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 351 ncomp = EHCI_HCS_N_CC(sparams); 352 if (ncomp != sc->sc_ncomp) { 353 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 354 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 355 #if NOHCI == 0 || NUHCI == 0 356 aprint_error("%s: ohci or uhci probably not configured\n", 357 device_xname(sc->sc_dev)); 358 #endif 359 if (ncomp < sc->sc_ncomp) 360 sc->sc_ncomp = ncomp; 361 } 362 if (sc->sc_ncomp > 0) { 363 aprint_normal("%s: companion controller%s, %d port%s each:", 364 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 365 EHCI_HCS_N_PCC(sparams), 366 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 367 for (i = 0; i < sc->sc_ncomp; i++) 368 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 369 aprint_normal("\n"); 370 } 371 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 372 cparams = EREAD4(sc, EHCI_HCCPARAMS); 373 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 374 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 375 376 if (EHCI_HCC_64BIT(cparams)) { 377 /* MUST clear segment register if 64 bit capable. */ 378 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 379 } 380 381 sc->sc_bus.usbrev = USBREV_2_0; 382 383 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 384 USB_MEM_RESERVE); 385 386 /* Reset the controller */ 387 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 388 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 389 usb_delay_ms(&sc->sc_bus, 1); 390 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 391 for (i = 0; i < 100; i++) { 392 usb_delay_ms(&sc->sc_bus, 1); 393 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 394 if (!hcr) 395 break; 396 } 397 if (hcr) { 398 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 399 return (USBD_IOERROR); 400 } 401 402 /* XXX need proper intr scheduling */ 403 sc->sc_rand = 96; 404 405 /* frame list size at default, read back what we got and use that */ 406 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 407 case 0: sc->sc_flsize = 1024; break; 408 case 1: sc->sc_flsize = 512; break; 409 case 2: sc->sc_flsize = 256; break; 410 case 3: return (USBD_IOERROR); 411 } 412 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 413 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 414 if (err) 415 return (err); 416 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 417 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 418 419 for (i = 0; i < sc->sc_flsize; i++) { 420 sc->sc_flist[i] = EHCI_NULL; 421 } 422 423 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 424 425 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 426 M_USB, M_WAITOK | M_ZERO); 427 if (sc->sc_softitds == NULL) 428 return ENOMEM; 429 LIST_INIT(&sc->sc_freeitds); 430 431 /* Set up the bus struct. */ 432 sc->sc_bus.methods = &ehci_bus_methods; 433 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 434 435 sc->sc_eintrs = EHCI_NORMAL_INTRS; 436 437 /* 438 * Allocate the interrupt dummy QHs. These are arranged to give poll 439 * intervals that are powers of 2 times 1ms. 440 */ 441 for (i = 0; i < EHCI_INTRQHS; i++) { 442 sqh = ehci_alloc_sqh(sc); 443 if (sqh == NULL) { 444 err = USBD_NOMEM; 445 goto bad1; 446 } 447 sc->sc_islots[i].sqh = sqh; 448 } 449 for (i = 0; i < EHCI_INTRQHS; i++) { 450 sqh = sc->sc_islots[i].sqh; 451 if (i == 0) { 452 /* The last (1ms) QH terminates. */ 453 sqh->qh.qh_link = EHCI_NULL; 454 sqh->next = NULL; 455 } else { 456 /* Otherwise the next QH has half the poll interval */ 457 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 458 sqh->qh.qh_link = htole32(sqh->next->physaddr | 459 EHCI_LINK_QH); 460 } 461 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 462 sqh->qh.qh_curqtd = EHCI_NULL; 463 sqh->next = NULL; 464 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 465 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 466 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 467 sqh->sqtd = NULL; 468 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 469 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 470 } 471 /* Point the frame list at the last level (128ms). */ 472 for (i = 0; i < sc->sc_flsize; i++) { 473 int j; 474 475 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 476 revbits[i & (EHCI_MAX_POLLRATE-1)]; 477 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 478 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 479 i)].sqh->physaddr); 480 } 481 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 482 BUS_DMASYNC_PREWRITE); 483 484 /* Allocate dummy QH that starts the async list. */ 485 sqh = ehci_alloc_sqh(sc); 486 if (sqh == NULL) { 487 err = USBD_NOMEM; 488 goto bad1; 489 } 490 /* Fill the QH */ 491 sqh->qh.qh_endp = 492 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 493 sqh->qh.qh_link = 494 htole32(sqh->physaddr | EHCI_LINK_QH); 495 sqh->qh.qh_curqtd = EHCI_NULL; 496 sqh->next = NULL; 497 /* Fill the overlay qTD */ 498 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 499 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 500 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 501 sqh->sqtd = NULL; 502 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 503 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 504 #ifdef EHCI_DEBUG 505 if (ehcidebug) { 506 ehci_dump_sqh(sqh); 507 } 508 #endif 509 510 /* Point to async list */ 511 sc->sc_async_head = sqh; 512 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 513 514 usb_callout_init(sc->sc_tmo_intrlist); 515 516 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE); 517 518 /* Turn on controller */ 519 EOWRITE4(sc, EHCI_USBCMD, 520 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 521 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 522 EHCI_CMD_ASE | 523 EHCI_CMD_PSE | 524 EHCI_CMD_RS); 525 526 /* Take over port ownership */ 527 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 528 529 for (i = 0; i < 100; i++) { 530 usb_delay_ms(&sc->sc_bus, 1); 531 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 532 if (!hcr) 533 break; 534 } 535 if (hcr) { 536 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 537 return (USBD_IOERROR); 538 } 539 540 /* Enable interrupts */ 541 DPRINTFN(1,("ehci_init: enabling\n")); 542 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 543 544 return (USBD_NORMAL_COMPLETION); 545 546 #if 0 547 bad2: 548 ehci_free_sqh(sc, sc->sc_async_head); 549 #endif 550 bad1: 551 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 552 return (err); 553 } 554 555 int 556 ehci_intr(void *v) 557 { 558 ehci_softc_t *sc = v; 559 560 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 561 return (0); 562 563 /* If we get an interrupt while polling, then just ignore it. */ 564 if (sc->sc_bus.use_polling) { 565 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 566 567 if (intrs) 568 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 569 #ifdef DIAGNOSTIC 570 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 571 #endif 572 return (0); 573 } 574 575 return (ehci_intr1(sc)); 576 } 577 578 Static int 579 ehci_intr1(ehci_softc_t *sc) 580 { 581 u_int32_t intrs, eintrs; 582 583 DPRINTFN(20,("ehci_intr1: enter\n")); 584 585 /* In case the interrupt occurs before initialization has completed. */ 586 if (sc == NULL) { 587 #ifdef DIAGNOSTIC 588 printf("ehci_intr1: sc == NULL\n"); 589 #endif 590 return (0); 591 } 592 593 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 594 if (!intrs) 595 return (0); 596 597 eintrs = intrs & sc->sc_eintrs; 598 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 599 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 600 (u_int)eintrs)); 601 if (!eintrs) 602 return (0); 603 604 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 605 sc->sc_bus.intr_context++; 606 sc->sc_bus.no_intrs++; 607 if (eintrs & EHCI_STS_IAA) { 608 DPRINTF(("ehci_intr1: door bell\n")); 609 wakeup(&sc->sc_async_head); 610 eintrs &= ~EHCI_STS_IAA; 611 } 612 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 613 DPRINTFN(5,("ehci_intr1: %s %s\n", 614 eintrs & EHCI_STS_INT ? "INT" : "", 615 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 616 usb_schedsoftintr(&sc->sc_bus); 617 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 618 } 619 if (eintrs & EHCI_STS_HSE) { 620 printf("%s: unrecoverable error, controller halted\n", 621 device_xname(sc->sc_dev)); 622 /* XXX what else */ 623 } 624 if (eintrs & EHCI_STS_PCD) { 625 ehci_pcd(sc, sc->sc_intrxfer); 626 eintrs &= ~EHCI_STS_PCD; 627 } 628 629 sc->sc_bus.intr_context--; 630 631 if (eintrs != 0) { 632 /* Block unprocessed interrupts. */ 633 sc->sc_eintrs &= ~eintrs; 634 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 635 printf("%s: blocking intrs 0x%x\n", 636 device_xname(sc->sc_dev), eintrs); 637 } 638 639 return (1); 640 } 641 642 643 void 644 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 645 { 646 usbd_pipe_handle pipe; 647 u_char *p; 648 int i, m; 649 650 if (xfer == NULL) { 651 /* Just ignore the change. */ 652 return; 653 } 654 655 pipe = xfer->pipe; 656 657 p = KERNADDR(&xfer->dmabuf, 0); 658 m = min(sc->sc_noport, xfer->length * 8 - 1); 659 memset(p, 0, xfer->length); 660 for (i = 1; i <= m; i++) { 661 /* Pick out CHANGE bits from the status reg. */ 662 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 663 p[i/8] |= 1 << (i%8); 664 } 665 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 666 xfer->actlen = xfer->length; 667 xfer->status = USBD_NORMAL_COMPLETION; 668 669 usb_transfer_complete(xfer); 670 } 671 672 void 673 ehci_softintr(void *v) 674 { 675 struct usbd_bus *bus = v; 676 ehci_softc_t *sc = bus->hci_private; 677 struct ehci_xfer *ex, *nextex; 678 679 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 680 sc->sc_bus.intr_context)); 681 682 sc->sc_bus.intr_context++; 683 684 /* 685 * The only explanation I can think of for why EHCI is as brain dead 686 * as UHCI interrupt-wise is that Intel was involved in both. 687 * An interrupt just tells us that something is done, we have no 688 * clue what, so we need to scan through all active transfers. :-( 689 */ 690 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 691 nextex = LIST_NEXT(ex, inext); 692 ehci_check_intr(sc, ex); 693 } 694 695 /* Schedule a callout to catch any dropped transactions. */ 696 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 697 !LIST_EMPTY(&sc->sc_intrhead)) 698 usb_callout(sc->sc_tmo_intrlist, hz, 699 ehci_intrlist_timeout, sc); 700 701 #ifdef USB_USE_SOFTINTR 702 if (sc->sc_softwake) { 703 sc->sc_softwake = 0; 704 wakeup(&sc->sc_softwake); 705 } 706 #endif /* USB_USE_SOFTINTR */ 707 708 sc->sc_bus.intr_context--; 709 } 710 711 /* Check for an interrupt. */ 712 void 713 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 714 { 715 int attr; 716 717 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 718 719 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 720 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 721 ehci_check_itd_intr(sc, ex); 722 else 723 ehci_check_qh_intr(sc, ex); 724 725 return; 726 } 727 728 void 729 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 730 { 731 ehci_soft_qtd_t *sqtd, *lsqtd; 732 __uint32_t status; 733 734 if (ex->sqtdstart == NULL) { 735 printf("ehci_check_qh_intr: not valid sqtd\n"); 736 return; 737 } 738 739 lsqtd = ex->sqtdend; 740 #ifdef DIAGNOSTIC 741 if (lsqtd == NULL) { 742 printf("ehci_check_qh_intr: lsqtd==0\n"); 743 return; 744 } 745 #endif 746 /* 747 * If the last TD is still active we need to check whether there 748 * is a an error somewhere in the middle, or whether there was a 749 * short packet (SPD and not ACTIVE). 750 */ 751 usb_syncmem(&lsqtd->dma, 752 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 753 sizeof(lsqtd->qtd.qtd_status), 754 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 755 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 756 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 757 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 758 usb_syncmem(&sqtd->dma, 759 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 760 sizeof(sqtd->qtd.qtd_status), 761 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 762 status = le32toh(sqtd->qtd.qtd_status); 763 usb_syncmem(&sqtd->dma, 764 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 765 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 766 /* If there's an active QTD the xfer isn't done. */ 767 if (status & EHCI_QTD_ACTIVE) 768 break; 769 /* Any kind of error makes the xfer done. */ 770 if (status & EHCI_QTD_HALTED) 771 goto done; 772 /* We want short packets, and it is short: it's done */ 773 if (EHCI_QTD_GET_BYTES(status) != 0) 774 goto done; 775 } 776 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 777 ex, ex->sqtdstart)); 778 usb_syncmem(&lsqtd->dma, 779 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 780 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 781 return; 782 } 783 done: 784 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 785 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 786 ehci_idone(ex); 787 } 788 789 void 790 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 791 ehci_soft_itd_t *itd; 792 int i; 793 794 if (ex->itdstart == NULL) { 795 printf("ehci_check_itd_intr: not valid itd\n"); 796 return; 797 } 798 799 itd = ex->itdend; 800 #ifdef DIAGNOSTIC 801 if (itd == NULL) { 802 printf("ehci_check_itd_intr: itdend == 0\n"); 803 return; 804 } 805 #endif 806 807 /* 808 * Step 1, check no active transfers in last itd, meaning we're finished 809 */ 810 811 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 812 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 813 BUS_DMASYNC_POSTREAD); 814 815 for (i = 0; i < 8; i++) { 816 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 817 break; 818 } 819 820 if (i == 8) { 821 goto done; /* All 8 descriptors inactive, it's done */ 822 } 823 824 /* 825 * Step 2, check for errors in status bits, throughout chain... 826 */ 827 828 DPRINTFN(12, ("ehci_check_itd_intr: active ex=%p\n", ex)); 829 830 for (itd = ex->itdstart; itd != ex->itdend; itd = itd->xfer_next) { 831 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 832 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 833 BUS_DMASYNC_POSTREAD); 834 835 for (i = 0; i < 8; i++) { 836 if (le32toh(itd->itd.itd_ctl[i]) & (EHCI_ITD_BUF_ERR | 837 EHCI_ITD_BABBLE | EHCI_ITD_ERROR)) 838 break; 839 } 840 if (i != 8) { /* Error in one of the itds */ 841 goto done; 842 } 843 } /* itd search loop */ 844 845 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 846 ex->itdstart)); 847 return; 848 849 done: 850 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 851 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 852 ehci_idone(ex); 853 } 854 855 void 856 ehci_idone(struct ehci_xfer *ex) 857 { 858 usbd_xfer_handle xfer = &ex->xfer; 859 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 860 ehci_soft_qtd_t *sqtd, *lsqtd; 861 u_int32_t status = 0, nstatus = 0; 862 int actlen; 863 864 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 865 #ifdef DIAGNOSTIC 866 { 867 int s = splhigh(); 868 if (ex->isdone) { 869 splx(s); 870 #ifdef EHCI_DEBUG 871 printf("ehci_idone: ex is done!\n "); 872 ehci_dump_exfer(ex); 873 #else 874 printf("ehci_idone: ex=%p is done!\n", ex); 875 #endif 876 return; 877 } 878 ex->isdone = 1; 879 splx(s); 880 } 881 #endif 882 if (xfer->status == USBD_CANCELLED || 883 xfer->status == USBD_TIMEOUT) { 884 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 885 return; 886 } 887 888 #ifdef EHCI_DEBUG 889 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 890 if (ehcidebug > 10) 891 ehci_dump_sqtds(ex->sqtdstart); 892 #endif 893 894 /* The transfer is done, compute actual length and status. */ 895 896 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 897 == UE_ISOCHRONOUS) { 898 /* Isoc transfer */ 899 struct ehci_soft_itd *itd; 900 int i, nframes, len, uframes; 901 902 nframes = 0; 903 actlen = 0; 904 905 switch (xfer->pipe->endpoint->edesc->bInterval) { 906 case 0: 907 panic("ehci: isoc xfer suddenly has 0 bInterval, invalid\n"); 908 case 1: uframes = 1; break; 909 case 2: uframes = 2; break; 910 case 3: uframes = 4; break; 911 default: uframes = 8; break; 912 } 913 914 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 915 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 916 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 917 BUS_DMASYNC_POSTREAD); 918 919 for (i = 0; i < 8; i += uframes) { 920 /* XXX - driver didn't fill in the frame full 921 * of uframes. This leads to scheduling 922 * inefficiencies, but working around 923 * this doubles complexity of tracking 924 * an xfer. 925 */ 926 if (nframes >= xfer->nframes) 927 break; 928 929 status = le32toh(itd->itd.itd_ctl[i]); 930 len = EHCI_ITD_GET_LEN(status); 931 xfer->frlengths[nframes++] = len; 932 actlen += len; 933 } 934 935 if (nframes >= xfer->nframes) 936 break; 937 } 938 939 xfer->actlen = actlen; 940 xfer->status = USBD_NORMAL_COMPLETION; 941 if (xfer->rqflags & URQ_DEV_DMABUF) { 942 usb_syncmem(&xfer->dmabuf, 0, ex->isoc_len, 943 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 944 } 945 946 goto end; 947 } 948 949 /* Continue processing xfers using queue heads */ 950 951 lsqtd = ex->sqtdend; 952 actlen = 0; 953 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 954 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 955 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 956 nstatus = le32toh(sqtd->qtd.qtd_status); 957 if (nstatus & EHCI_QTD_ACTIVE) 958 break; 959 960 status = nstatus; 961 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 962 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 963 } 964 965 966 /* 967 * If there are left over TDs we need to update the toggle. 968 * The default pipe doesn't need it since control transfers 969 * start the toggle at 0 every time. 970 * For a short transfer we need to update the toggle for the missing 971 * packets within the qTD. 972 */ 973 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 974 xfer->pipe->device->default_pipe != xfer->pipe) { 975 DPRINTFN(2, ("ehci_idone: need toggle update " 976 "status=%08x nstatus=%08x\n", status, nstatus)); 977 #if 0 978 ehci_dump_sqh(epipe->sqh); 979 ehci_dump_sqtds(ex->sqtdstart); 980 #endif 981 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 982 } 983 984 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 985 xfer->length, actlen, status)); 986 xfer->actlen = actlen; 987 if (status & EHCI_QTD_HALTED) { 988 #ifdef EHCI_DEBUG 989 char sbuf[128]; 990 991 bitmask_snprintf((u_int32_t)status, 992 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 993 "\3MISSED\1PINGSTATE", sbuf, sizeof(sbuf)); 994 995 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 996 "status 0x%s\n", 997 xfer->pipe->device->address, 998 xfer->pipe->endpoint->edesc->bEndpointAddress, 999 sbuf)); 1000 if (ehcidebug > 2) { 1001 ehci_dump_sqh(epipe->sqh); 1002 ehci_dump_sqtds(ex->sqtdstart); 1003 } 1004 #endif 1005 /* low&full speed has an extra error flag */ 1006 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1007 EHCI_QH_SPEED_HIGH) 1008 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1009 else 1010 status &= EHCI_QTD_STATERRS; 1011 if (status == 0) /* no other errors means a stall */ { 1012 xfer->status = USBD_STALLED; 1013 } else { 1014 xfer->status = USBD_IOERROR; /* more info XXX */ 1015 } 1016 /* XXX need to reset TT on missed microframe */ 1017 if (status & EHCI_QTD_MISSEDMICRO) { 1018 ehci_softc_t *sc = 1019 xfer->pipe->device->bus->hci_private; 1020 1021 printf("%s: missed microframe, TT reset not " 1022 "implemented, hub might be inoperational\n", 1023 device_xname(sc->sc_dev)); 1024 } 1025 } else { 1026 xfer->status = USBD_NORMAL_COMPLETION; 1027 } 1028 1029 end: 1030 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1031 * during this call, before methods->done is called: dma sync required 1032 * beforehand? */ 1033 usb_transfer_complete(xfer); 1034 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1035 } 1036 1037 /* 1038 * Wait here until controller claims to have an interrupt. 1039 * Then call ehci_intr and return. Use timeout to avoid waiting 1040 * too long. 1041 */ 1042 void 1043 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1044 { 1045 int timo; 1046 u_int32_t intrs; 1047 1048 xfer->status = USBD_IN_PROGRESS; 1049 for (timo = xfer->timeout; timo >= 0; timo--) { 1050 usb_delay_ms(&sc->sc_bus, 1); 1051 if (sc->sc_dying) 1052 break; 1053 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1054 sc->sc_eintrs; 1055 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1056 #ifdef EHCI_DEBUG 1057 if (ehcidebug > 15) 1058 ehci_dump_regs(sc); 1059 #endif 1060 if (intrs) { 1061 ehci_intr1(sc); 1062 if (xfer->status != USBD_IN_PROGRESS) 1063 return; 1064 } 1065 } 1066 1067 /* Timeout */ 1068 DPRINTF(("ehci_waitintr: timeout\n")); 1069 xfer->status = USBD_TIMEOUT; 1070 usb_transfer_complete(xfer); 1071 /* XXX should free TD */ 1072 } 1073 1074 void 1075 ehci_poll(struct usbd_bus *bus) 1076 { 1077 ehci_softc_t *sc = bus->hci_private; 1078 #ifdef EHCI_DEBUG 1079 static int last; 1080 int new; 1081 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1082 if (new != last) { 1083 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1084 last = new; 1085 } 1086 #endif 1087 1088 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1089 ehci_intr1(sc); 1090 } 1091 1092 void 1093 ehci_childdet(device_t self, device_t child) 1094 { 1095 struct ehci_softc *sc = device_private(self); 1096 1097 KASSERT(sc->sc_child == child); 1098 sc->sc_child = NULL; 1099 } 1100 1101 int 1102 ehci_detach(struct ehci_softc *sc, int flags) 1103 { 1104 int rv = 0; 1105 1106 if (sc->sc_child != NULL) 1107 rv = config_detach(sc->sc_child, flags); 1108 1109 if (rv != 0) 1110 return (rv); 1111 1112 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 1113 1114 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1115 1116 /* XXX free other data structures XXX */ 1117 mutex_destroy(&sc->sc_doorbell_lock); 1118 1119 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1120 1121 return (rv); 1122 } 1123 1124 1125 int 1126 ehci_activate(device_t self, enum devact act) 1127 { 1128 struct ehci_softc *sc = device_private(self); 1129 int rv = 0; 1130 1131 switch (act) { 1132 case DVACT_ACTIVATE: 1133 return (EOPNOTSUPP); 1134 1135 case DVACT_DEACTIVATE: 1136 sc->sc_dying = 1; 1137 if (sc->sc_child != NULL) 1138 rv = config_deactivate(sc->sc_child); 1139 break; 1140 } 1141 return (rv); 1142 } 1143 1144 /* 1145 * Handle suspend/resume. 1146 * 1147 * We need to switch to polling mode here, because this routine is 1148 * called from an interrupt context. This is all right since we 1149 * are almost suspended anyway. 1150 * 1151 * Note that this power handler isn't to be registered directly; the 1152 * bus glue needs to call out to it. 1153 */ 1154 bool 1155 ehci_suspend(device_t dv PMF_FN_ARGS) 1156 { 1157 ehci_softc_t *sc = device_private(dv); 1158 int i, s; 1159 uint32_t cmd, hcr; 1160 1161 s = splhardusb(); 1162 1163 sc->sc_bus.use_polling++; 1164 1165 for (i = 1; i <= sc->sc_noport; i++) { 1166 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1167 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1168 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1169 } 1170 1171 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1172 1173 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1174 EOWRITE4(sc, EHCI_USBCMD, cmd); 1175 1176 for (i = 0; i < 100; i++) { 1177 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1178 if (hcr == 0) 1179 break; 1180 1181 usb_delay_ms(&sc->sc_bus, 1); 1182 } 1183 if (hcr != 0) 1184 printf("%s: reset timeout\n", device_xname(dv)); 1185 1186 cmd &= ~EHCI_CMD_RS; 1187 EOWRITE4(sc, EHCI_USBCMD, cmd); 1188 1189 for (i = 0; i < 100; i++) { 1190 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1191 if (hcr == EHCI_STS_HCH) 1192 break; 1193 1194 usb_delay_ms(&sc->sc_bus, 1); 1195 } 1196 if (hcr != EHCI_STS_HCH) 1197 printf("%s: config timeout\n", device_xname(dv)); 1198 1199 sc->sc_bus.use_polling--; 1200 splx(s); 1201 1202 return true; 1203 } 1204 1205 bool 1206 ehci_resume(device_t dv PMF_FN_ARGS) 1207 { 1208 ehci_softc_t *sc = device_private(dv); 1209 int i; 1210 uint32_t cmd, hcr; 1211 1212 /* restore things in case the bios sucks */ 1213 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1214 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1215 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1216 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1217 1218 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1219 1220 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1221 1222 hcr = 0; 1223 for (i = 1; i <= sc->sc_noport; i++) { 1224 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1225 if ((cmd & EHCI_PS_PO) == 0 && 1226 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1227 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1228 hcr = 1; 1229 } 1230 } 1231 1232 if (hcr) { 1233 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1234 1235 for (i = 1; i <= sc->sc_noport; i++) { 1236 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1237 if ((cmd & EHCI_PS_PO) == 0 && 1238 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1239 EOWRITE4(sc, EHCI_PORTSC(i), 1240 cmd & ~EHCI_PS_FPR); 1241 } 1242 } 1243 1244 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1245 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1246 1247 for (i = 0; i < 100; i++) { 1248 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1249 if (hcr != EHCI_STS_HCH) 1250 break; 1251 1252 usb_delay_ms(&sc->sc_bus, 1); 1253 } 1254 if (hcr == EHCI_STS_HCH) 1255 printf("%s: config timeout\n", device_xname(dv)); 1256 1257 return true; 1258 } 1259 1260 /* 1261 * Shut down the controller when the system is going down. 1262 */ 1263 bool 1264 ehci_shutdown(device_t self, int flags) 1265 { 1266 ehci_softc_t *sc = device_private(self); 1267 1268 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1269 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1270 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1271 return true; 1272 } 1273 1274 usbd_status 1275 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1276 { 1277 struct ehci_softc *sc = bus->hci_private; 1278 usbd_status err; 1279 1280 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1281 if (err == USBD_NOMEM) 1282 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1283 #ifdef EHCI_DEBUG 1284 if (err) 1285 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1286 #endif 1287 return (err); 1288 } 1289 1290 void 1291 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1292 { 1293 struct ehci_softc *sc = bus->hci_private; 1294 1295 if (dma->block->flags & USB_DMA_RESERVE) { 1296 usb_reserve_freem(&sc->sc_dma_reserve, 1297 dma); 1298 return; 1299 } 1300 usb_freemem(&sc->sc_bus, dma); 1301 } 1302 1303 usbd_xfer_handle 1304 ehci_allocx(struct usbd_bus *bus) 1305 { 1306 struct ehci_softc *sc = bus->hci_private; 1307 usbd_xfer_handle xfer; 1308 1309 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1310 if (xfer != NULL) { 1311 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1312 #ifdef DIAGNOSTIC 1313 if (xfer->busy_free != XFER_FREE) { 1314 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1315 xfer->busy_free); 1316 } 1317 #endif 1318 } else { 1319 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1320 } 1321 if (xfer != NULL) { 1322 memset(xfer, 0, sizeof(struct ehci_xfer)); 1323 #ifdef DIAGNOSTIC 1324 EXFER(xfer)->isdone = 1; 1325 xfer->busy_free = XFER_BUSY; 1326 #endif 1327 } 1328 return (xfer); 1329 } 1330 1331 void 1332 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1333 { 1334 struct ehci_softc *sc = bus->hci_private; 1335 1336 #ifdef DIAGNOSTIC 1337 if (xfer->busy_free != XFER_BUSY) { 1338 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1339 xfer->busy_free); 1340 } 1341 xfer->busy_free = XFER_FREE; 1342 if (!EXFER(xfer)->isdone) { 1343 printf("ehci_freex: !isdone\n"); 1344 } 1345 #endif 1346 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1347 } 1348 1349 Static void 1350 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1351 { 1352 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1353 1354 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1355 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1356 #ifdef USB_DEBUG 1357 if (ehcidebug) 1358 usbd_dump_pipe(pipe); 1359 #endif 1360 epipe->nexttoggle = 0; 1361 } 1362 1363 Static void 1364 ehci_noop(usbd_pipe_handle pipe) 1365 { 1366 } 1367 1368 #ifdef EHCI_DEBUG 1369 void 1370 ehci_dump_regs(ehci_softc_t *sc) 1371 { 1372 int i; 1373 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1374 EOREAD4(sc, EHCI_USBCMD), 1375 EOREAD4(sc, EHCI_USBSTS), 1376 EOREAD4(sc, EHCI_USBINTR)); 1377 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1378 EOREAD4(sc, EHCI_FRINDEX), 1379 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1380 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1381 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1382 for (i = 1; i <= sc->sc_noport; i++) 1383 printf("port %d status=0x%08x\n", i, 1384 EOREAD4(sc, EHCI_PORTSC(i))); 1385 } 1386 1387 /* 1388 * Unused function - this is meant to be called from a kernel 1389 * debugger. 1390 */ 1391 void 1392 ehci_dump() 1393 { 1394 ehci_dump_regs(theehci); 1395 } 1396 1397 void 1398 ehci_dump_link(ehci_link_t link, int type) 1399 { 1400 link = le32toh(link); 1401 printf("0x%08x", link); 1402 if (link & EHCI_LINK_TERMINATE) 1403 printf("<T>"); 1404 else { 1405 printf("<"); 1406 if (type) { 1407 switch (EHCI_LINK_TYPE(link)) { 1408 case EHCI_LINK_ITD: printf("ITD"); break; 1409 case EHCI_LINK_QH: printf("QH"); break; 1410 case EHCI_LINK_SITD: printf("SITD"); break; 1411 case EHCI_LINK_FSTN: printf("FSTN"); break; 1412 } 1413 } 1414 printf(">"); 1415 } 1416 } 1417 1418 void 1419 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1420 { 1421 int i; 1422 u_int32_t stop; 1423 1424 stop = 0; 1425 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1426 ehci_dump_sqtd(sqtd); 1427 usb_syncmem(&sqtd->dma, 1428 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1429 sizeof(sqtd->qtd), 1430 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1431 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1432 usb_syncmem(&sqtd->dma, 1433 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1434 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1435 } 1436 if (sqtd) 1437 printf("dump aborted, too many TDs\n"); 1438 } 1439 1440 void 1441 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1442 { 1443 usb_syncmem(&sqtd->dma, sqtd->offs, 1444 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1445 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1446 ehci_dump_qtd(&sqtd->qtd); 1447 usb_syncmem(&sqtd->dma, sqtd->offs, 1448 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1449 } 1450 1451 void 1452 ehci_dump_qtd(ehci_qtd_t *qtd) 1453 { 1454 u_int32_t s; 1455 char sbuf[128]; 1456 1457 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1458 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1459 printf("\n"); 1460 s = le32toh(qtd->qtd_status); 1461 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1462 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1463 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1464 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1465 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1466 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1467 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1468 EHCI_QTD_GET_PID(s), sbuf); 1469 for (s = 0; s < 5; s++) 1470 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1471 } 1472 1473 void 1474 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1475 { 1476 ehci_qh_t *qh = &sqh->qh; 1477 u_int32_t endp, endphub; 1478 1479 usb_syncmem(&sqh->dma, sqh->offs, 1480 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1481 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1482 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1483 endp = le32toh(qh->qh_endp); 1484 printf(" endp=0x%08x\n", endp); 1485 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1486 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1487 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1488 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1489 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1490 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1491 EHCI_QH_GET_NRL(endp)); 1492 endphub = le32toh(qh->qh_endphub); 1493 printf(" endphub=0x%08x\n", endphub); 1494 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1495 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1496 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1497 EHCI_QH_GET_MULT(endphub)); 1498 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1499 printf("Overlay qTD:\n"); 1500 ehci_dump_qtd(&qh->qh_qtd); 1501 usb_syncmem(&sqh->dma, sqh->offs, 1502 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1503 } 1504 1505 #if notyet 1506 void 1507 ehci_dump_itd(struct ehci_soft_itd *itd) 1508 { 1509 ehci_isoc_trans_t t; 1510 ehci_isoc_bufr_ptr_t b, b2, b3; 1511 int i; 1512 1513 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1514 1515 for (i = 0; i < 8;i++) { 1516 t = le32toh(itd->itd.itd_ctl[i]); 1517 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1518 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1519 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1520 EHCI_ITD_GET_OFFS(t)); 1521 } 1522 printf("ITDbufr: "); 1523 for (i = 0; i < 7; i++) 1524 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1525 1526 b = le32toh(itd->itd.itd_bufr[0]); 1527 b2 = le32toh(itd->itd.itd_bufr[1]); 1528 b3 = le32toh(itd->itd.itd_bufr[2]); 1529 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1530 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1531 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1532 } 1533 1534 void 1535 ehci_dump_sitd(struct ehci_soft_itd *itd) 1536 { 1537 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1538 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1539 itd->xfer_next, itd->physaddr, itd->slot); 1540 } 1541 #endif 1542 1543 #ifdef DIAGNOSTIC 1544 void 1545 ehci_dump_exfer(struct ehci_xfer *ex) 1546 { 1547 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1548 } 1549 #endif 1550 1551 #endif 1552 1553 usbd_status 1554 ehci_open(usbd_pipe_handle pipe) 1555 { 1556 usbd_device_handle dev = pipe->device; 1557 ehci_softc_t *sc = dev->bus->hci_private; 1558 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1559 u_int8_t addr = dev->address; 1560 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1561 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1562 ehci_soft_qh_t *sqh; 1563 usbd_status err; 1564 int s; 1565 int ival, speed, naks; 1566 int hshubaddr, hshubport; 1567 1568 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1569 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1570 1571 if (dev->myhsport) { 1572 hshubaddr = dev->myhsport->parent->address; 1573 hshubport = dev->myhsport->portno; 1574 } else { 1575 hshubaddr = 0; 1576 hshubport = 0; 1577 } 1578 1579 if (sc->sc_dying) 1580 return (USBD_IOERROR); 1581 1582 epipe->nexttoggle = 0; 1583 1584 if (addr == sc->sc_addr) { 1585 switch (ed->bEndpointAddress) { 1586 case USB_CONTROL_ENDPOINT: 1587 pipe->methods = &ehci_root_ctrl_methods; 1588 break; 1589 case UE_DIR_IN | EHCI_INTR_ENDPT: 1590 pipe->methods = &ehci_root_intr_methods; 1591 break; 1592 default: 1593 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1594 ed->bEndpointAddress)); 1595 return (USBD_INVAL); 1596 } 1597 return (USBD_NORMAL_COMPLETION); 1598 } 1599 1600 /* XXX All this stuff is only valid for async. */ 1601 switch (dev->speed) { 1602 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1603 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1604 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1605 default: panic("ehci_open: bad device speed %d", dev->speed); 1606 } 1607 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1608 printf("%s: *** Error: opening low/full speed isoc device on" 1609 "ehci, this does not work yet. Feel free to implement\n", 1610 device_xname(sc->sc_dev)); 1611 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1612 hshubaddr, hshubport)); 1613 return USBD_INVAL; 1614 } 1615 1616 naks = 8; /* XXX */ 1617 1618 /* Allocate sqh for everything, save isoc xfers */ 1619 if (xfertype != UE_ISOCHRONOUS) { 1620 sqh = ehci_alloc_sqh(sc); 1621 if (sqh == NULL) 1622 return (USBD_NOMEM); 1623 /* qh_link filled when the QH is added */ 1624 sqh->qh.qh_endp = htole32( 1625 EHCI_QH_SET_ADDR(addr) | 1626 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1627 EHCI_QH_SET_EPS(speed) | 1628 EHCI_QH_DTC | 1629 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1630 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1631 EHCI_QH_CTL : 0) | 1632 EHCI_QH_SET_NRL(naks) 1633 ); 1634 sqh->qh.qh_endphub = htole32( 1635 EHCI_QH_SET_MULT(1) | 1636 EHCI_QH_SET_HUBA(hshubaddr) | 1637 EHCI_QH_SET_PORT(hshubport) | 1638 EHCI_QH_SET_CMASK(0x08) | /* XXX */ 1639 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1640 ); 1641 sqh->qh.qh_curqtd = EHCI_NULL; 1642 /* Fill the overlay qTD */ 1643 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1644 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1645 sqh->qh.qh_qtd.qtd_status = htole32(0); 1646 1647 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1648 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1649 epipe->sqh = sqh; 1650 } else { 1651 sqh = NULL; 1652 } /*xfertype == UE_ISOC*/ 1653 1654 switch (xfertype) { 1655 case UE_CONTROL: 1656 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1657 0, &epipe->u.ctl.reqdma); 1658 #ifdef EHCI_DEBUG 1659 if (err) 1660 printf("ehci_open: usb_allocmem()=%d\n", err); 1661 #endif 1662 if (err) 1663 goto bad; 1664 pipe->methods = &ehci_device_ctrl_methods; 1665 s = splusb(); 1666 ehci_add_qh(sqh, sc->sc_async_head); 1667 splx(s); 1668 break; 1669 case UE_BULK: 1670 pipe->methods = &ehci_device_bulk_methods; 1671 s = splusb(); 1672 ehci_add_qh(sqh, sc->sc_async_head); 1673 splx(s); 1674 break; 1675 case UE_INTERRUPT: 1676 pipe->methods = &ehci_device_intr_methods; 1677 ival = pipe->interval; 1678 if (ival == USBD_DEFAULT_INTERVAL) { 1679 if (speed == EHCI_QH_SPEED_HIGH) { 1680 if (ed->bInterval > 16) { 1681 /* 1682 * illegal with high-speed, but there 1683 * were documentation bugs in the spec, 1684 * so be generous 1685 */ 1686 ival = 256; 1687 } else 1688 ival = (1 << (ed->bInterval - 1)) / 8; 1689 } else 1690 ival = ed->bInterval; 1691 } 1692 err = ehci_device_setintr(sc, sqh, ival); 1693 if (err) 1694 goto bad; 1695 break; 1696 case UE_ISOCHRONOUS: 1697 pipe->methods = &ehci_device_isoc_methods; 1698 if (ed->bInterval == 0 || ed->bInterval >= 16) { 1699 printf("ehci: opening pipe with invalid bInterval\n"); 1700 err = USBD_INVAL; 1701 goto bad; 1702 } 1703 if (UGETW(ed->wMaxPacketSize) == 0) { 1704 printf("ehci: zero length endpoint open request\n"); 1705 err = USBD_INVAL; 1706 goto bad; 1707 } 1708 epipe->u.isoc.next_frame = 0; 1709 epipe->u.isoc.cur_xfers = 0; 1710 break; 1711 default: 1712 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1713 err = USBD_INVAL; 1714 goto bad; 1715 } 1716 return (USBD_NORMAL_COMPLETION); 1717 1718 bad: 1719 if (sqh != NULL) 1720 ehci_free_sqh(sc, sqh); 1721 return (err); 1722 } 1723 1724 /* 1725 * Add an ED to the schedule. Called at splusb(). 1726 */ 1727 void 1728 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1729 { 1730 SPLUSBCHECK; 1731 1732 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1733 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1734 sqh->next = head->next; 1735 sqh->qh.qh_link = head->qh.qh_link; 1736 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1737 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1738 head->next = sqh; 1739 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1740 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1741 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1742 1743 #ifdef EHCI_DEBUG 1744 if (ehcidebug > 5) { 1745 printf("ehci_add_qh:\n"); 1746 ehci_dump_sqh(sqh); 1747 } 1748 #endif 1749 } 1750 1751 /* 1752 * Remove an ED from the schedule. Called at splusb(). 1753 */ 1754 void 1755 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1756 { 1757 ehci_soft_qh_t *p; 1758 1759 SPLUSBCHECK; 1760 /* XXX */ 1761 for (p = head; p != NULL && p->next != sqh; p = p->next) 1762 ; 1763 if (p == NULL) 1764 panic("ehci_rem_qh: ED not found"); 1765 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1766 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1767 p->next = sqh->next; 1768 p->qh.qh_link = sqh->qh.qh_link; 1769 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1770 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1771 1772 ehci_sync_hc(sc); 1773 } 1774 1775 void 1776 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1777 { 1778 int i; 1779 u_int32_t status; 1780 1781 /* Save toggle bit and ping status. */ 1782 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1783 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1784 status = sqh->qh.qh_qtd.qtd_status & 1785 htole32(EHCI_QTD_TOGGLE_MASK | 1786 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1787 /* Set HALTED to make hw leave it alone. */ 1788 sqh->qh.qh_qtd.qtd_status = 1789 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1790 usb_syncmem(&sqh->dma, 1791 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1792 sizeof(sqh->qh.qh_qtd.qtd_status), 1793 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1794 sqh->qh.qh_curqtd = 0; 1795 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1796 sqh->qh.qh_qtd.qtd_altnext = 0; 1797 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1798 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1799 sqh->sqtd = sqtd; 1800 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1801 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1802 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1803 sqh->qh.qh_qtd.qtd_status = status; 1804 usb_syncmem(&sqh->dma, 1805 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1806 sizeof(sqh->qh.qh_qtd.qtd_status), 1807 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1808 } 1809 1810 /* 1811 * Ensure that the HC has released all references to the QH. We do this 1812 * by asking for a Async Advance Doorbell interrupt and then we wait for 1813 * the interrupt. 1814 * To make this easier we first obtain exclusive use of the doorbell. 1815 */ 1816 void 1817 ehci_sync_hc(ehci_softc_t *sc) 1818 { 1819 int s, error; 1820 1821 if (sc->sc_dying) { 1822 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1823 return; 1824 } 1825 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1826 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */ 1827 s = splhardusb(); 1828 /* ask for doorbell */ 1829 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1830 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1831 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1832 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1833 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1834 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1835 splx(s); 1836 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */ 1837 #ifdef DIAGNOSTIC 1838 if (error) 1839 printf("ehci_sync_hc: tsleep() = %d\n", error); 1840 #endif 1841 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1842 } 1843 1844 /*Call at splusb*/ 1845 void 1846 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1847 { 1848 struct ehci_soft_itd *itd, *prev; 1849 1850 prev = NULL; 1851 1852 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1853 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1854 1855 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1856 prev = itd->u.frame_list.prev; 1857 /* Unlink itd from hardware chain, or frame array */ 1858 if (prev == NULL) { /* We're at the table head */ 1859 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1860 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1861 usb_syncmem(&sc->sc_fldma, 1862 sizeof(ehci_link_t) * itd->slot, 1863 sizeof(ehci_link_t), 1864 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1865 1866 if (itd->u.frame_list.next != NULL) 1867 itd->u.frame_list.next->u.frame_list.prev = NULL; 1868 } else { 1869 /* XXX this part is untested... */ 1870 prev->itd.itd_next = itd->itd.itd_next; 1871 usb_syncmem(&itd->dma, 1872 itd->offs + offsetof(ehci_itd_t, itd_next), 1873 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1874 1875 prev->u.frame_list.next = itd->u.frame_list.next; 1876 if (itd->u.frame_list.next != NULL) 1877 itd->u.frame_list.next->u.frame_list.prev = prev; 1878 } 1879 } 1880 1881 prev = NULL; 1882 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1883 if (prev != NULL) 1884 ehci_free_itd(sc, prev); 1885 prev = itd; 1886 } 1887 if (prev) 1888 ehci_free_itd(sc, prev); 1889 exfer->itdstart = NULL; 1890 exfer->itdend = NULL; 1891 } 1892 1893 /***********/ 1894 1895 /* 1896 * Data structures and routines to emulate the root hub. 1897 */ 1898 Static usb_device_descriptor_t ehci_devd = { 1899 USB_DEVICE_DESCRIPTOR_SIZE, 1900 UDESC_DEVICE, /* type */ 1901 {0x00, 0x02}, /* USB version */ 1902 UDCLASS_HUB, /* class */ 1903 UDSUBCLASS_HUB, /* subclass */ 1904 UDPROTO_HSHUBSTT, /* protocol */ 1905 64, /* max packet */ 1906 {0},{0},{0x00,0x01}, /* device id */ 1907 1,2,0, /* string indicies */ 1908 1 /* # of configurations */ 1909 }; 1910 1911 Static const usb_device_qualifier_t ehci_odevd = { 1912 USB_DEVICE_DESCRIPTOR_SIZE, 1913 UDESC_DEVICE_QUALIFIER, /* type */ 1914 {0x00, 0x02}, /* USB version */ 1915 UDCLASS_HUB, /* class */ 1916 UDSUBCLASS_HUB, /* subclass */ 1917 UDPROTO_FSHUB, /* protocol */ 1918 64, /* max packet */ 1919 1, /* # of configurations */ 1920 0 1921 }; 1922 1923 Static const usb_config_descriptor_t ehci_confd = { 1924 USB_CONFIG_DESCRIPTOR_SIZE, 1925 UDESC_CONFIG, 1926 {USB_CONFIG_DESCRIPTOR_SIZE + 1927 USB_INTERFACE_DESCRIPTOR_SIZE + 1928 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1929 1, 1930 1, 1931 0, 1932 UC_ATTR_MBO | UC_SELF_POWERED, 1933 0 /* max power */ 1934 }; 1935 1936 Static const usb_interface_descriptor_t ehci_ifcd = { 1937 USB_INTERFACE_DESCRIPTOR_SIZE, 1938 UDESC_INTERFACE, 1939 0, 1940 0, 1941 1, 1942 UICLASS_HUB, 1943 UISUBCLASS_HUB, 1944 UIPROTO_HSHUBSTT, 1945 0 1946 }; 1947 1948 Static const usb_endpoint_descriptor_t ehci_endpd = { 1949 USB_ENDPOINT_DESCRIPTOR_SIZE, 1950 UDESC_ENDPOINT, 1951 UE_DIR_IN | EHCI_INTR_ENDPT, 1952 UE_INTERRUPT, 1953 {8, 0}, /* max packet */ 1954 12 1955 }; 1956 1957 Static const usb_hub_descriptor_t ehci_hubd = { 1958 USB_HUB_DESCRIPTOR_SIZE, 1959 UDESC_HUB, 1960 0, 1961 {0,0}, 1962 0, 1963 0, 1964 {""}, 1965 {""}, 1966 }; 1967 1968 /* 1969 * Simulate a hardware hub by handling all the necessary requests. 1970 */ 1971 Static usbd_status 1972 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1973 { 1974 usbd_status err; 1975 1976 /* Insert last in queue. */ 1977 err = usb_insert_transfer(xfer); 1978 if (err) 1979 return (err); 1980 1981 /* Pipe isn't running, start first */ 1982 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1983 } 1984 1985 Static usbd_status 1986 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1987 { 1988 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1989 usb_device_request_t *req; 1990 void *buf = NULL; 1991 int port, i; 1992 int s, len, value, index, l, totlen = 0; 1993 usb_port_status_t ps; 1994 usb_hub_descriptor_t hubd; 1995 usbd_status err; 1996 u_int32_t v; 1997 1998 if (sc->sc_dying) 1999 return (USBD_IOERROR); 2000 2001 #ifdef DIAGNOSTIC 2002 if (!(xfer->rqflags & URQ_REQUEST)) 2003 /* XXX panic */ 2004 return (USBD_INVAL); 2005 #endif 2006 req = &xfer->request; 2007 2008 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2009 req->bmRequestType, req->bRequest)); 2010 2011 len = UGETW(req->wLength); 2012 value = UGETW(req->wValue); 2013 index = UGETW(req->wIndex); 2014 2015 if (len != 0) 2016 buf = KERNADDR(&xfer->dmabuf, 0); 2017 2018 #define C(x,y) ((x) | ((y) << 8)) 2019 switch(C(req->bRequest, req->bmRequestType)) { 2020 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2021 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2022 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2023 /* 2024 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2025 * for the integrated root hub. 2026 */ 2027 break; 2028 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2029 if (len > 0) { 2030 *(u_int8_t *)buf = sc->sc_conf; 2031 totlen = 1; 2032 } 2033 break; 2034 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2035 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2036 if (len == 0) 2037 break; 2038 switch(value >> 8) { 2039 case UDESC_DEVICE: 2040 if ((value & 0xff) != 0) { 2041 err = USBD_IOERROR; 2042 goto ret; 2043 } 2044 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2045 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2046 memcpy(buf, &ehci_devd, l); 2047 break; 2048 /* 2049 * We can't really operate at another speed, but the spec says 2050 * we need this descriptor. 2051 */ 2052 case UDESC_DEVICE_QUALIFIER: 2053 if ((value & 0xff) != 0) { 2054 err = USBD_IOERROR; 2055 goto ret; 2056 } 2057 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2058 memcpy(buf, &ehci_odevd, l); 2059 break; 2060 /* 2061 * We can't really operate at another speed, but the spec says 2062 * we need this descriptor. 2063 */ 2064 case UDESC_OTHER_SPEED_CONFIGURATION: 2065 case UDESC_CONFIG: 2066 if ((value & 0xff) != 0) { 2067 err = USBD_IOERROR; 2068 goto ret; 2069 } 2070 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2071 memcpy(buf, &ehci_confd, l); 2072 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2073 value >> 8; 2074 buf = (char *)buf + l; 2075 len -= l; 2076 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2077 totlen += l; 2078 memcpy(buf, &ehci_ifcd, l); 2079 buf = (char *)buf + l; 2080 len -= l; 2081 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2082 totlen += l; 2083 memcpy(buf, &ehci_endpd, l); 2084 break; 2085 case UDESC_STRING: 2086 #define sd ((usb_string_descriptor_t *)buf) 2087 switch (value & 0xff) { 2088 case 0: /* Language table */ 2089 totlen = usb_makelangtbl(sd, len); 2090 break; 2091 case 1: /* Vendor */ 2092 totlen = usb_makestrdesc(sd, len, 2093 sc->sc_vendor); 2094 break; 2095 case 2: /* Product */ 2096 totlen = usb_makestrdesc(sd, len, 2097 "EHCI root hub"); 2098 break; 2099 } 2100 #undef sd 2101 break; 2102 default: 2103 err = USBD_IOERROR; 2104 goto ret; 2105 } 2106 break; 2107 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2108 if (len > 0) { 2109 *(u_int8_t *)buf = 0; 2110 totlen = 1; 2111 } 2112 break; 2113 case C(UR_GET_STATUS, UT_READ_DEVICE): 2114 if (len > 1) { 2115 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2116 totlen = 2; 2117 } 2118 break; 2119 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2120 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2121 if (len > 1) { 2122 USETW(((usb_status_t *)buf)->wStatus, 0); 2123 totlen = 2; 2124 } 2125 break; 2126 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2127 if (value >= USB_MAX_DEVICES) { 2128 err = USBD_IOERROR; 2129 goto ret; 2130 } 2131 sc->sc_addr = value; 2132 break; 2133 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2134 if (value != 0 && value != 1) { 2135 err = USBD_IOERROR; 2136 goto ret; 2137 } 2138 sc->sc_conf = value; 2139 break; 2140 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2141 break; 2142 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2143 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2144 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2145 err = USBD_IOERROR; 2146 goto ret; 2147 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2148 break; 2149 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2150 break; 2151 /* Hub requests */ 2152 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2153 break; 2154 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2155 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2156 "port=%d feature=%d\n", 2157 index, value)); 2158 if (index < 1 || index > sc->sc_noport) { 2159 err = USBD_IOERROR; 2160 goto ret; 2161 } 2162 port = EHCI_PORTSC(index); 2163 v = EOREAD4(sc, port); 2164 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2165 v &= ~EHCI_PS_CLEAR; 2166 switch(value) { 2167 case UHF_PORT_ENABLE: 2168 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2169 break; 2170 case UHF_PORT_SUSPEND: 2171 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2172 break; 2173 v &= ~EHCI_PS_SUSP; 2174 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2175 /* see USB2 spec ch. 7.1.7.7 */ 2176 usb_delay_ms(&sc->sc_bus, 20); 2177 EOWRITE4(sc, port, v); 2178 usb_delay_ms(&sc->sc_bus, 2); 2179 #ifdef DEBUG 2180 v = EOREAD4(sc, port); 2181 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2182 printf("ehci: resume failed: %x\n", v); 2183 #endif 2184 break; 2185 case UHF_PORT_POWER: 2186 if (sc->sc_hasppc) 2187 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2188 break; 2189 case UHF_PORT_TEST: 2190 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2191 "%d\n", index)); 2192 break; 2193 case UHF_PORT_INDICATOR: 2194 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2195 "%d\n", index)); 2196 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2197 break; 2198 case UHF_C_PORT_CONNECTION: 2199 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2200 break; 2201 case UHF_C_PORT_ENABLE: 2202 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2203 break; 2204 case UHF_C_PORT_SUSPEND: 2205 /* how? */ 2206 break; 2207 case UHF_C_PORT_OVER_CURRENT: 2208 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2209 break; 2210 case UHF_C_PORT_RESET: 2211 sc->sc_isreset[index] = 0; 2212 break; 2213 default: 2214 err = USBD_IOERROR; 2215 goto ret; 2216 } 2217 #if 0 2218 switch(value) { 2219 case UHF_C_PORT_CONNECTION: 2220 case UHF_C_PORT_ENABLE: 2221 case UHF_C_PORT_SUSPEND: 2222 case UHF_C_PORT_OVER_CURRENT: 2223 case UHF_C_PORT_RESET: 2224 default: 2225 break; 2226 } 2227 #endif 2228 break; 2229 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2230 if (len == 0) 2231 break; 2232 if ((value & 0xff) != 0) { 2233 err = USBD_IOERROR; 2234 goto ret; 2235 } 2236 hubd = ehci_hubd; 2237 hubd.bNbrPorts = sc->sc_noport; 2238 v = EOREAD4(sc, EHCI_HCSPARAMS); 2239 USETW(hubd.wHubCharacteristics, 2240 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2241 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2242 ? UHD_PORT_IND : 0); 2243 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2244 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2245 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2246 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2247 l = min(len, hubd.bDescLength); 2248 totlen = l; 2249 memcpy(buf, &hubd, l); 2250 break; 2251 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2252 if (len != 4) { 2253 err = USBD_IOERROR; 2254 goto ret; 2255 } 2256 memset(buf, 0, len); /* ? XXX */ 2257 totlen = len; 2258 break; 2259 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2260 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2261 index)); 2262 if (index < 1 || index > sc->sc_noport) { 2263 err = USBD_IOERROR; 2264 goto ret; 2265 } 2266 if (len != 4) { 2267 err = USBD_IOERROR; 2268 goto ret; 2269 } 2270 v = EOREAD4(sc, EHCI_PORTSC(index)); 2271 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2272 v)); 2273 i = UPS_HIGH_SPEED; 2274 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2275 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2276 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2277 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2278 if (v & EHCI_PS_PR) i |= UPS_RESET; 2279 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2280 USETW(ps.wPortStatus, i); 2281 i = 0; 2282 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2283 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2284 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2285 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2286 USETW(ps.wPortChange, i); 2287 l = min(len, sizeof ps); 2288 memcpy(buf, &ps, l); 2289 totlen = l; 2290 break; 2291 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2292 err = USBD_IOERROR; 2293 goto ret; 2294 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2295 break; 2296 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2297 if (index < 1 || index > sc->sc_noport) { 2298 err = USBD_IOERROR; 2299 goto ret; 2300 } 2301 port = EHCI_PORTSC(index); 2302 v = EOREAD4(sc, port); 2303 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2304 v &= ~EHCI_PS_CLEAR; 2305 switch(value) { 2306 case UHF_PORT_ENABLE: 2307 EOWRITE4(sc, port, v | EHCI_PS_PE); 2308 break; 2309 case UHF_PORT_SUSPEND: 2310 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2311 break; 2312 case UHF_PORT_RESET: 2313 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2314 index)); 2315 if (EHCI_PS_IS_LOWSPEED(v)) { 2316 /* Low speed device, give up ownership. */ 2317 ehci_disown(sc, index, 1); 2318 break; 2319 } 2320 /* Start reset sequence. */ 2321 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2322 EOWRITE4(sc, port, v | EHCI_PS_PR); 2323 /* Wait for reset to complete. */ 2324 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2325 if (sc->sc_dying) { 2326 err = USBD_IOERROR; 2327 goto ret; 2328 } 2329 /* Terminate reset sequence. */ 2330 EOWRITE4(sc, port, v); 2331 /* Wait for HC to complete reset. */ 2332 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2333 if (sc->sc_dying) { 2334 err = USBD_IOERROR; 2335 goto ret; 2336 } 2337 v = EOREAD4(sc, port); 2338 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2339 if (v & EHCI_PS_PR) { 2340 printf("%s: port reset timeout\n", 2341 device_xname(sc->sc_dev)); 2342 return (USBD_TIMEOUT); 2343 } 2344 if (!(v & EHCI_PS_PE)) { 2345 /* Not a high speed device, give up ownership.*/ 2346 ehci_disown(sc, index, 0); 2347 break; 2348 } 2349 sc->sc_isreset[index] = 1; 2350 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2351 index, v)); 2352 break; 2353 case UHF_PORT_POWER: 2354 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2355 "%d (has PPC = %d)\n", index, 2356 sc->sc_hasppc)); 2357 if (sc->sc_hasppc) 2358 EOWRITE4(sc, port, v | EHCI_PS_PP); 2359 break; 2360 case UHF_PORT_TEST: 2361 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2362 "%d\n", index)); 2363 break; 2364 case UHF_PORT_INDICATOR: 2365 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2366 "%d\n", index)); 2367 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2368 break; 2369 default: 2370 err = USBD_IOERROR; 2371 goto ret; 2372 } 2373 break; 2374 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2375 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2376 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2377 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2378 break; 2379 default: 2380 err = USBD_IOERROR; 2381 goto ret; 2382 } 2383 xfer->actlen = totlen; 2384 err = USBD_NORMAL_COMPLETION; 2385 ret: 2386 xfer->status = err; 2387 s = splusb(); 2388 usb_transfer_complete(xfer); 2389 splx(s); 2390 return (USBD_IN_PROGRESS); 2391 } 2392 2393 void 2394 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2395 { 2396 int port; 2397 u_int32_t v; 2398 2399 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2400 #ifdef DIAGNOSTIC 2401 if (sc->sc_npcomp != 0) { 2402 int i = (index-1) / sc->sc_npcomp; 2403 if (i >= sc->sc_ncomp) 2404 printf("%s: strange port\n", 2405 device_xname(sc->sc_dev)); 2406 else 2407 printf("%s: handing over %s speed device on " 2408 "port %d to %s\n", 2409 device_xname(sc->sc_dev), 2410 lowspeed ? "low" : "full", 2411 index, device_xname(sc->sc_comps[i])); 2412 } else { 2413 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2414 } 2415 #endif 2416 port = EHCI_PORTSC(index); 2417 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2418 EOWRITE4(sc, port, v | EHCI_PS_PO); 2419 } 2420 2421 /* Abort a root control request. */ 2422 Static void 2423 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2424 { 2425 /* Nothing to do, all transfers are synchronous. */ 2426 } 2427 2428 /* Close the root pipe. */ 2429 Static void 2430 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2431 { 2432 DPRINTF(("ehci_root_ctrl_close\n")); 2433 /* Nothing to do. */ 2434 } 2435 2436 void 2437 ehci_root_intr_done(usbd_xfer_handle xfer) 2438 { 2439 xfer->hcpriv = NULL; 2440 } 2441 2442 Static usbd_status 2443 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2444 { 2445 usbd_status err; 2446 2447 /* Insert last in queue. */ 2448 err = usb_insert_transfer(xfer); 2449 if (err) 2450 return (err); 2451 2452 /* Pipe isn't running, start first */ 2453 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2454 } 2455 2456 Static usbd_status 2457 ehci_root_intr_start(usbd_xfer_handle xfer) 2458 { 2459 usbd_pipe_handle pipe = xfer->pipe; 2460 ehci_softc_t *sc = pipe->device->bus->hci_private; 2461 2462 if (sc->sc_dying) 2463 return (USBD_IOERROR); 2464 2465 sc->sc_intrxfer = xfer; 2466 2467 return (USBD_IN_PROGRESS); 2468 } 2469 2470 /* Abort a root interrupt request. */ 2471 Static void 2472 ehci_root_intr_abort(usbd_xfer_handle xfer) 2473 { 2474 int s; 2475 2476 if (xfer->pipe->intrxfer == xfer) { 2477 DPRINTF(("ehci_root_intr_abort: remove\n")); 2478 xfer->pipe->intrxfer = NULL; 2479 } 2480 xfer->status = USBD_CANCELLED; 2481 s = splusb(); 2482 usb_transfer_complete(xfer); 2483 splx(s); 2484 } 2485 2486 /* Close the root pipe. */ 2487 Static void 2488 ehci_root_intr_close(usbd_pipe_handle pipe) 2489 { 2490 ehci_softc_t *sc = pipe->device->bus->hci_private; 2491 2492 DPRINTF(("ehci_root_intr_close\n")); 2493 2494 sc->sc_intrxfer = NULL; 2495 } 2496 2497 void 2498 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2499 { 2500 xfer->hcpriv = NULL; 2501 } 2502 2503 /************************/ 2504 2505 ehci_soft_qh_t * 2506 ehci_alloc_sqh(ehci_softc_t *sc) 2507 { 2508 ehci_soft_qh_t *sqh; 2509 usbd_status err; 2510 int i, offs; 2511 usb_dma_t dma; 2512 2513 if (sc->sc_freeqhs == NULL) { 2514 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2515 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2516 EHCI_PAGE_SIZE, &dma); 2517 #ifdef EHCI_DEBUG 2518 if (err) 2519 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2520 #endif 2521 if (err) 2522 return (NULL); 2523 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2524 offs = i * EHCI_SQH_SIZE; 2525 sqh = KERNADDR(&dma, offs); 2526 sqh->physaddr = DMAADDR(&dma, offs); 2527 sqh->dma = dma; 2528 sqh->offs = offs; 2529 sqh->next = sc->sc_freeqhs; 2530 sc->sc_freeqhs = sqh; 2531 } 2532 } 2533 sqh = sc->sc_freeqhs; 2534 sc->sc_freeqhs = sqh->next; 2535 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2536 sqh->next = NULL; 2537 return (sqh); 2538 } 2539 2540 void 2541 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2542 { 2543 sqh->next = sc->sc_freeqhs; 2544 sc->sc_freeqhs = sqh; 2545 } 2546 2547 ehci_soft_qtd_t * 2548 ehci_alloc_sqtd(ehci_softc_t *sc) 2549 { 2550 ehci_soft_qtd_t *sqtd; 2551 usbd_status err; 2552 int i, offs; 2553 usb_dma_t dma; 2554 int s; 2555 2556 if (sc->sc_freeqtds == NULL) { 2557 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2558 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2559 EHCI_PAGE_SIZE, &dma); 2560 #ifdef EHCI_DEBUG 2561 if (err) 2562 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2563 #endif 2564 if (err) 2565 return (NULL); 2566 s = splusb(); 2567 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2568 offs = i * EHCI_SQTD_SIZE; 2569 sqtd = KERNADDR(&dma, offs); 2570 sqtd->physaddr = DMAADDR(&dma, offs); 2571 sqtd->dma = dma; 2572 sqtd->offs = offs; 2573 sqtd->nextqtd = sc->sc_freeqtds; 2574 sc->sc_freeqtds = sqtd; 2575 } 2576 splx(s); 2577 } 2578 2579 s = splusb(); 2580 sqtd = sc->sc_freeqtds; 2581 sc->sc_freeqtds = sqtd->nextqtd; 2582 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2583 sqtd->nextqtd = NULL; 2584 sqtd->xfer = NULL; 2585 splx(s); 2586 2587 return (sqtd); 2588 } 2589 2590 void 2591 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2592 { 2593 int s; 2594 2595 s = splusb(); 2596 sqtd->nextqtd = sc->sc_freeqtds; 2597 sc->sc_freeqtds = sqtd; 2598 splx(s); 2599 } 2600 2601 usbd_status 2602 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2603 int alen, int rd, usbd_xfer_handle xfer, 2604 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2605 { 2606 ehci_soft_qtd_t *next, *cur; 2607 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2608 u_int32_t qtdstatus; 2609 int len, curlen, mps; 2610 int i, tog; 2611 usb_dma_t *dma = &xfer->dmabuf; 2612 u_int16_t flags = xfer->flags; 2613 2614 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2615 2616 len = alen; 2617 dataphys = DMAADDR(dma, 0); 2618 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2619 qtdstatus = EHCI_QTD_ACTIVE | 2620 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2621 EHCI_QTD_SET_CERR(3) 2622 /* IOC set below */ 2623 /* BYTES set below */ 2624 ; 2625 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2626 tog = epipe->nexttoggle; 2627 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2628 2629 cur = ehci_alloc_sqtd(sc); 2630 *sp = cur; 2631 if (cur == NULL) 2632 goto nomem; 2633 2634 usb_syncmem(dma, 0, alen, 2635 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2636 for (;;) { 2637 dataphyspage = EHCI_PAGE(dataphys); 2638 /* The EHCI hardware can handle at most 5 pages. */ 2639 if (dataphyslastpage - dataphyspage < 2640 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2641 /* we can handle it in this QTD */ 2642 curlen = len; 2643 } else { 2644 /* must use multiple TDs, fill as much as possible. */ 2645 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2646 EHCI_PAGE_OFFSET(dataphys); 2647 #ifdef DIAGNOSTIC 2648 if (curlen > len) { 2649 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2650 "len=0x%x offs=0x%x\n", curlen, len, 2651 EHCI_PAGE_OFFSET(dataphys)); 2652 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2653 dataphyslastpage, dataphyspage, 2654 dataphys); 2655 curlen = len; 2656 } 2657 #endif 2658 /* the length must be a multiple of the max size */ 2659 curlen -= curlen % mps; 2660 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2661 "curlen=%d\n", curlen)); 2662 #ifdef DIAGNOSTIC 2663 if (curlen == 0) 2664 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2665 #endif 2666 } 2667 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2668 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2669 dataphys, dataphyslastpage, 2670 len, curlen)); 2671 len -= curlen; 2672 2673 /* 2674 * Allocate another transfer if there's more data left, 2675 * or if force last short transfer flag is set and we're 2676 * allocating a multiple of the max packet size. 2677 */ 2678 if (len != 0 || 2679 ((curlen % mps) == 0 && !rd && curlen != 0 && 2680 (flags & USBD_FORCE_SHORT_XFER))) { 2681 next = ehci_alloc_sqtd(sc); 2682 if (next == NULL) 2683 goto nomem; 2684 nextphys = htole32(next->physaddr); 2685 } else { 2686 next = NULL; 2687 nextphys = EHCI_NULL; 2688 } 2689 2690 for (i = 0; i * EHCI_PAGE_SIZE < 2691 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2692 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2693 if (i != 0) /* use offset only in first buffer */ 2694 a = EHCI_PAGE(a); 2695 cur->qtd.qtd_buffer[i] = htole32(a); 2696 cur->qtd.qtd_buffer_hi[i] = 0; 2697 #ifdef DIAGNOSTIC 2698 if (i >= EHCI_QTD_NBUFFERS) { 2699 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2700 goto nomem; 2701 } 2702 #endif 2703 } 2704 cur->nextqtd = next; 2705 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2706 cur->qtd.qtd_status = 2707 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2708 cur->xfer = xfer; 2709 cur->len = curlen; 2710 2711 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2712 dataphys, dataphys + curlen)); 2713 /* adjust the toggle based on the number of packets in this 2714 qtd */ 2715 if (((curlen + mps - 1) / mps) & 1) { 2716 tog ^= 1; 2717 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2718 } 2719 if (next == NULL) 2720 break; 2721 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2722 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2723 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2724 dataphys += curlen; 2725 cur = next; 2726 } 2727 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2728 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2729 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2730 *ep = cur; 2731 epipe->nexttoggle = tog; 2732 2733 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2734 *sp, *ep)); 2735 2736 return (USBD_NORMAL_COMPLETION); 2737 2738 nomem: 2739 /* XXX free chain */ 2740 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2741 return (USBD_NOMEM); 2742 } 2743 2744 Static void 2745 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2746 ehci_soft_qtd_t *sqtdend) 2747 { 2748 ehci_soft_qtd_t *p; 2749 int i; 2750 2751 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2752 sqtd, sqtdend)); 2753 2754 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2755 p = sqtd->nextqtd; 2756 ehci_free_sqtd(sc, sqtd); 2757 } 2758 } 2759 2760 ehci_soft_itd_t * 2761 ehci_alloc_itd(ehci_softc_t *sc) 2762 { 2763 struct ehci_soft_itd *itd, *freeitd; 2764 usbd_status err; 2765 int i, s, offs, frindex, previndex; 2766 usb_dma_t dma; 2767 2768 s = splusb(); 2769 2770 /* Find an itd that wasn't freed this frame or last frame. This can 2771 * discard itds that were freed before frindex wrapped around 2772 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2773 * interrupt and fiddling with list when that happens */ 2774 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2775 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2776 2777 freeitd = NULL; 2778 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2779 if (itd == NULL) 2780 break; 2781 if (itd->slot != frindex && itd->slot != previndex) { 2782 freeitd = itd; 2783 break; 2784 } 2785 } 2786 2787 if (freeitd == NULL) { 2788 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2789 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2790 EHCI_PAGE_SIZE, &dma); 2791 2792 if (err) { 2793 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2794 return NULL; 2795 } 2796 2797 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2798 offs = i * EHCI_ITD_SIZE; 2799 itd = KERNADDR(&dma, offs); 2800 itd->physaddr = DMAADDR(&dma, offs); 2801 itd->dma = dma; 2802 itd->offs = offs; 2803 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2804 } 2805 freeitd = LIST_FIRST(&sc->sc_freeitds); 2806 } 2807 2808 itd = freeitd; 2809 LIST_REMOVE(itd, u.free_list); 2810 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2811 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2812 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2813 BUS_DMASYNC_PREREAD); 2814 2815 itd->u.frame_list.next = NULL; 2816 itd->u.frame_list.prev = NULL; 2817 itd->xfer_next = NULL; 2818 itd->slot = 0; 2819 splx(s); 2820 2821 return itd; 2822 } 2823 2824 void 2825 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2826 { 2827 int s; 2828 2829 s = splusb(); 2830 LIST_INSERT_AFTER(LIST_FIRST(&sc->sc_freeitds), itd, u.free_list); 2831 splx(s); 2832 } 2833 2834 2835 2836 /****************/ 2837 2838 /* 2839 * Close a reqular pipe. 2840 * Assumes that there are no pending transactions. 2841 */ 2842 void 2843 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2844 { 2845 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2846 ehci_softc_t *sc = pipe->device->bus->hci_private; 2847 ehci_soft_qh_t *sqh = epipe->sqh; 2848 int s; 2849 2850 s = splusb(); 2851 ehci_rem_qh(sc, sqh, head); 2852 splx(s); 2853 ehci_free_sqh(sc, epipe->sqh); 2854 } 2855 2856 /* 2857 * Abort a device request. 2858 * If this routine is called at splusb() it guarantees that the request 2859 * will be removed from the hardware scheduling and that the callback 2860 * for it will be called with USBD_CANCELLED status. 2861 * It's impossible to guarantee that the requested transfer will not 2862 * have happened since the hardware runs concurrently. 2863 * If the transaction has already happened we rely on the ordinary 2864 * interrupt processing to process it. 2865 * XXX This is most probably wrong. 2866 */ 2867 void 2868 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2869 { 2870 #define exfer EXFER(xfer) 2871 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2872 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2873 ehci_soft_qh_t *sqh = epipe->sqh; 2874 ehci_soft_qtd_t *sqtd; 2875 ehci_physaddr_t cur; 2876 u_int32_t qhstatus; 2877 int s; 2878 int hit; 2879 int wake; 2880 2881 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2882 2883 if (sc->sc_dying) { 2884 /* If we're dying, just do the software part. */ 2885 s = splusb(); 2886 xfer->status = status; /* make software ignore it */ 2887 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2888 usb_transfer_complete(xfer); 2889 splx(s); 2890 return; 2891 } 2892 2893 if (xfer->device->bus->intr_context) 2894 panic("ehci_abort_xfer: not in process context"); 2895 2896 /* 2897 * If an abort is already in progress then just wait for it to 2898 * complete and return. 2899 */ 2900 if (xfer->hcflags & UXFER_ABORTING) { 2901 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2902 #ifdef DIAGNOSTIC 2903 if (status == USBD_TIMEOUT) 2904 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2905 #endif 2906 /* Override the status which might be USBD_TIMEOUT. */ 2907 xfer->status = status; 2908 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2909 xfer->hcflags |= UXFER_ABORTWAIT; 2910 while (xfer->hcflags & UXFER_ABORTING) 2911 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2912 return; 2913 } 2914 xfer->hcflags |= UXFER_ABORTING; 2915 2916 /* 2917 * Step 1: Make interrupt routine and hardware ignore xfer. 2918 */ 2919 s = splusb(); 2920 xfer->status = status; /* make software ignore it */ 2921 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2922 2923 usb_syncmem(&sqh->dma, 2924 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2925 sizeof(sqh->qh.qh_qtd.qtd_status), 2926 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2927 qhstatus = sqh->qh.qh_qtd.qtd_status; 2928 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2929 usb_syncmem(&sqh->dma, 2930 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2931 sizeof(sqh->qh.qh_qtd.qtd_status), 2932 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2933 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2934 usb_syncmem(&sqtd->dma, 2935 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2936 sizeof(sqtd->qtd.qtd_status), 2937 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2938 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2939 usb_syncmem(&sqtd->dma, 2940 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2941 sizeof(sqtd->qtd.qtd_status), 2942 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2943 if (sqtd == exfer->sqtdend) 2944 break; 2945 } 2946 splx(s); 2947 2948 /* 2949 * Step 2: Wait until we know hardware has finished any possible 2950 * use of the xfer. Also make sure the soft interrupt routine 2951 * has run. 2952 */ 2953 ehci_sync_hc(sc); 2954 s = splusb(); 2955 #ifdef USB_USE_SOFTINTR 2956 sc->sc_softwake = 1; 2957 #endif /* USB_USE_SOFTINTR */ 2958 usb_schedsoftintr(&sc->sc_bus); 2959 #ifdef USB_USE_SOFTINTR 2960 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2961 #endif /* USB_USE_SOFTINTR */ 2962 splx(s); 2963 2964 /* 2965 * Step 3: Remove any vestiges of the xfer from the hardware. 2966 * The complication here is that the hardware may have executed 2967 * beyond the xfer we're trying to abort. So as we're scanning 2968 * the TDs of this xfer we check if the hardware points to 2969 * any of them. 2970 */ 2971 s = splusb(); /* XXX why? */ 2972 2973 usb_syncmem(&sqh->dma, 2974 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2975 sizeof(sqh->qh.qh_curqtd), 2976 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2977 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2978 hit = 0; 2979 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2980 hit |= cur == sqtd->physaddr; 2981 if (sqtd == exfer->sqtdend) 2982 break; 2983 } 2984 sqtd = sqtd->nextqtd; 2985 /* Zap curqtd register if hardware pointed inside the xfer. */ 2986 if (hit && sqtd != NULL) { 2987 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 2988 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 2989 usb_syncmem(&sqh->dma, 2990 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2991 sizeof(sqh->qh.qh_curqtd), 2992 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2993 sqh->qh.qh_qtd.qtd_status = qhstatus; 2994 usb_syncmem(&sqh->dma, 2995 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2996 sizeof(sqh->qh.qh_qtd.qtd_status), 2997 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2998 } else { 2999 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3000 } 3001 3002 /* 3003 * Step 4: Execute callback. 3004 */ 3005 #ifdef DIAGNOSTIC 3006 exfer->isdone = 1; 3007 #endif 3008 wake = xfer->hcflags & UXFER_ABORTWAIT; 3009 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3010 usb_transfer_complete(xfer); 3011 if (wake) 3012 wakeup(&xfer->hcflags); 3013 3014 splx(s); 3015 #undef exfer 3016 } 3017 3018 void 3019 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3020 { 3021 ehci_isoc_trans_t trans_status; 3022 struct ehci_pipe *epipe; 3023 struct ehci_xfer *exfer; 3024 ehci_softc_t *sc; 3025 struct ehci_soft_itd *itd; 3026 int s, i, wake; 3027 3028 epipe = (struct ehci_pipe *) xfer->pipe; 3029 exfer = EXFER(xfer); 3030 sc = epipe->pipe.device->bus->hci_private; 3031 3032 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3033 3034 if (sc->sc_dying) { 3035 s = splusb(); 3036 xfer->status = status; 3037 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3038 usb_transfer_complete(xfer); 3039 splx(s); 3040 return; 3041 } 3042 3043 if (xfer->hcflags & UXFER_ABORTING) { 3044 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3045 3046 #ifdef DIAGNOSTIC 3047 if (status == USBD_TIMEOUT) 3048 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3049 #endif 3050 3051 xfer->status = status; 3052 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3053 xfer->hcflags |= UXFER_ABORTWAIT; 3054 while (xfer->hcflags & UXFER_ABORTING) 3055 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0); 3056 return; 3057 } 3058 xfer->hcflags |= UXFER_ABORTING; 3059 3060 xfer->status = status; 3061 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3062 3063 s = splusb(); 3064 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3065 usb_syncmem(&itd->dma, 3066 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3067 sizeof(itd->itd.itd_ctl), 3068 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3069 3070 for (i = 0; i < 8; i++) { 3071 trans_status = le32toh(itd->itd.itd_ctl[i]); 3072 trans_status &= ~EHCI_ITD_ACTIVE; 3073 itd->itd.itd_ctl[i] = htole32(trans_status); 3074 } 3075 3076 usb_syncmem(&itd->dma, 3077 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3078 sizeof(itd->itd.itd_ctl), 3079 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3080 } 3081 splx(s); 3082 3083 s = splusb(); 3084 #ifdef USB_USE_SOFTINTR 3085 sc->sc_softwake = 1; 3086 #endif /* USB_USE_SOFTINTR */ 3087 usb_schedsoftintr(&sc->sc_bus); 3088 #ifdef USB_USE_SOFTINTR 3089 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3090 #endif /* USB_USE_SOFTINTR */ 3091 splx(s); 3092 3093 #ifdef DIAGNOSTIC 3094 exfer->isdone = 1; 3095 #endif 3096 wake = xfer->hcflags & UXFER_ABORTWAIT; 3097 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3098 usb_transfer_complete(xfer); 3099 if (wake) 3100 wakeup(&xfer->hcflags); 3101 3102 return; 3103 } 3104 3105 void 3106 ehci_timeout(void *addr) 3107 { 3108 struct ehci_xfer *exfer = addr; 3109 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3110 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3111 3112 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3113 #ifdef USB_DEBUG 3114 if (ehcidebug > 1) 3115 usbd_dump_pipe(exfer->xfer.pipe); 3116 #endif 3117 3118 if (sc->sc_dying) { 3119 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3120 return; 3121 } 3122 3123 /* Execute the abort in a process context. */ 3124 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3125 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3126 USB_TASKQ_HC); 3127 } 3128 3129 void 3130 ehci_timeout_task(void *addr) 3131 { 3132 usbd_xfer_handle xfer = addr; 3133 int s; 3134 3135 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3136 3137 s = splusb(); 3138 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3139 splx(s); 3140 } 3141 3142 /************************/ 3143 3144 Static usbd_status 3145 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3146 { 3147 usbd_status err; 3148 3149 /* Insert last in queue. */ 3150 err = usb_insert_transfer(xfer); 3151 if (err) 3152 return (err); 3153 3154 /* Pipe isn't running, start first */ 3155 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3156 } 3157 3158 Static usbd_status 3159 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3160 { 3161 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3162 usbd_status err; 3163 3164 if (sc->sc_dying) 3165 return (USBD_IOERROR); 3166 3167 #ifdef DIAGNOSTIC 3168 if (!(xfer->rqflags & URQ_REQUEST)) { 3169 /* XXX panic */ 3170 printf("ehci_device_ctrl_transfer: not a request\n"); 3171 return (USBD_INVAL); 3172 } 3173 #endif 3174 3175 err = ehci_device_request(xfer); 3176 if (err) 3177 return (err); 3178 3179 if (sc->sc_bus.use_polling) 3180 ehci_waitintr(sc, xfer); 3181 return (USBD_IN_PROGRESS); 3182 } 3183 3184 void 3185 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3186 { 3187 struct ehci_xfer *ex = EXFER(xfer); 3188 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3189 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3190 usb_device_request_t *req = &xfer->request; 3191 int len = UGETW(req->wLength); 3192 int rd = req->bmRequestType & UT_READ; 3193 3194 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3195 3196 #ifdef DIAGNOSTIC 3197 if (!(xfer->rqflags & URQ_REQUEST)) { 3198 panic("ehci_ctrl_done: not a request"); 3199 } 3200 #endif 3201 3202 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3203 ehci_del_intr_list(ex); /* remove from active list */ 3204 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3205 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3206 BUS_DMASYNC_POSTWRITE); 3207 if (len) 3208 usb_syncmem(&xfer->dmabuf, 0, len, 3209 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3210 } 3211 3212 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3213 } 3214 3215 /* Abort a device control request. */ 3216 Static void 3217 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3218 { 3219 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3220 ehci_abort_xfer(xfer, USBD_CANCELLED); 3221 } 3222 3223 /* Close a device control pipe. */ 3224 Static void 3225 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3226 { 3227 ehci_softc_t *sc = pipe->device->bus->hci_private; 3228 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3229 3230 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3231 ehci_close_pipe(pipe, sc->sc_async_head); 3232 } 3233 3234 usbd_status 3235 ehci_device_request(usbd_xfer_handle xfer) 3236 { 3237 #define exfer EXFER(xfer) 3238 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3239 usb_device_request_t *req = &xfer->request; 3240 usbd_device_handle dev = epipe->pipe.device; 3241 ehci_softc_t *sc = dev->bus->hci_private; 3242 int addr = dev->address; 3243 ehci_soft_qtd_t *setup, *stat, *next; 3244 ehci_soft_qh_t *sqh; 3245 int isread; 3246 int len; 3247 usbd_status err; 3248 int s; 3249 3250 isread = req->bmRequestType & UT_READ; 3251 len = UGETW(req->wLength); 3252 3253 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3254 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3255 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3256 UGETW(req->wIndex), len, addr, 3257 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3258 3259 setup = ehci_alloc_sqtd(sc); 3260 if (setup == NULL) { 3261 err = USBD_NOMEM; 3262 goto bad1; 3263 } 3264 stat = ehci_alloc_sqtd(sc); 3265 if (stat == NULL) { 3266 err = USBD_NOMEM; 3267 goto bad2; 3268 } 3269 3270 sqh = epipe->sqh; 3271 epipe->u.ctl.length = len; 3272 3273 /* Update device address and length since they may have changed 3274 during the setup of the control pipe in usbd_new_device(). */ 3275 /* XXX This only needs to be done once, but it's too early in open. */ 3276 /* XXXX Should not touch ED here! */ 3277 sqh->qh.qh_endp = 3278 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3279 htole32( 3280 EHCI_QH_SET_ADDR(addr) | 3281 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3282 ); 3283 3284 /* Set up data transaction */ 3285 if (len != 0) { 3286 ehci_soft_qtd_t *end; 3287 3288 /* Start toggle at 1. */ 3289 epipe->nexttoggle = 1; 3290 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3291 &next, &end); 3292 if (err) 3293 goto bad3; 3294 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3295 end->nextqtd = stat; 3296 end->qtd.qtd_next = 3297 end->qtd.qtd_altnext = htole32(stat->physaddr); 3298 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3299 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3300 } else { 3301 next = stat; 3302 } 3303 3304 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3305 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3306 3307 /* Clear toggle */ 3308 setup->qtd.qtd_status = htole32( 3309 EHCI_QTD_ACTIVE | 3310 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3311 EHCI_QTD_SET_CERR(3) | 3312 EHCI_QTD_SET_TOGGLE(0) | 3313 EHCI_QTD_SET_BYTES(sizeof *req) 3314 ); 3315 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3316 setup->qtd.qtd_buffer_hi[0] = 0; 3317 setup->nextqtd = next; 3318 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3319 setup->xfer = xfer; 3320 setup->len = sizeof *req; 3321 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3322 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3323 3324 stat->qtd.qtd_status = htole32( 3325 EHCI_QTD_ACTIVE | 3326 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3327 EHCI_QTD_SET_CERR(3) | 3328 EHCI_QTD_SET_TOGGLE(1) | 3329 EHCI_QTD_IOC 3330 ); 3331 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3332 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3333 stat->nextqtd = NULL; 3334 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3335 stat->xfer = xfer; 3336 stat->len = 0; 3337 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3338 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3339 3340 #ifdef EHCI_DEBUG 3341 if (ehcidebug > 5) { 3342 DPRINTF(("ehci_device_request:\n")); 3343 ehci_dump_sqh(sqh); 3344 ehci_dump_sqtds(setup); 3345 } 3346 #endif 3347 3348 exfer->sqtdstart = setup; 3349 exfer->sqtdend = stat; 3350 #ifdef DIAGNOSTIC 3351 if (!exfer->isdone) { 3352 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3353 } 3354 exfer->isdone = 0; 3355 #endif 3356 3357 /* Insert qTD in QH list. */ 3358 s = splusb(); 3359 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3360 if (xfer->timeout && !sc->sc_bus.use_polling) { 3361 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3362 ehci_timeout, xfer); 3363 } 3364 ehci_add_intr_list(sc, exfer); 3365 xfer->status = USBD_IN_PROGRESS; 3366 splx(s); 3367 3368 #ifdef EHCI_DEBUG 3369 if (ehcidebug > 10) { 3370 DPRINTF(("ehci_device_request: status=%x\n", 3371 EOREAD4(sc, EHCI_USBSTS))); 3372 delay(10000); 3373 ehci_dump_regs(sc); 3374 ehci_dump_sqh(sc->sc_async_head); 3375 ehci_dump_sqh(sqh); 3376 ehci_dump_sqtds(setup); 3377 } 3378 #endif 3379 3380 return (USBD_NORMAL_COMPLETION); 3381 3382 bad3: 3383 ehci_free_sqtd(sc, stat); 3384 bad2: 3385 ehci_free_sqtd(sc, setup); 3386 bad1: 3387 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3388 xfer->status = err; 3389 usb_transfer_complete(xfer); 3390 return (err); 3391 #undef exfer 3392 } 3393 3394 /* 3395 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3396 * qTD status, or miss signalling occasionally under heavy load. If the host 3397 * machine is too fast, we we can miss transaction completion - when we scan 3398 * the active list the transaction still seems to be active. This generally 3399 * exhibits itself as a umass stall that never recovers. 3400 * 3401 * We work around this behaviour by setting up this callback after any softintr 3402 * that completes with transactions still pending, giving us another chance to 3403 * check for completion after the writeback has taken place. 3404 */ 3405 void 3406 ehci_intrlist_timeout(void *arg) 3407 { 3408 ehci_softc_t *sc = arg; 3409 int s = splusb(); 3410 3411 DPRINTF(("ehci_intrlist_timeout\n")); 3412 usb_schedsoftintr(&sc->sc_bus); 3413 3414 splx(s); 3415 } 3416 3417 /************************/ 3418 3419 Static usbd_status 3420 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3421 { 3422 usbd_status err; 3423 3424 /* Insert last in queue. */ 3425 err = usb_insert_transfer(xfer); 3426 if (err) 3427 return (err); 3428 3429 /* Pipe isn't running, start first */ 3430 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3431 } 3432 3433 usbd_status 3434 ehci_device_bulk_start(usbd_xfer_handle xfer) 3435 { 3436 #define exfer EXFER(xfer) 3437 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3438 usbd_device_handle dev = epipe->pipe.device; 3439 ehci_softc_t *sc = dev->bus->hci_private; 3440 ehci_soft_qtd_t *data, *dataend; 3441 ehci_soft_qh_t *sqh; 3442 usbd_status err; 3443 int len, isread, endpt; 3444 int s; 3445 3446 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3447 xfer, xfer->length, xfer->flags)); 3448 3449 if (sc->sc_dying) 3450 return (USBD_IOERROR); 3451 3452 #ifdef DIAGNOSTIC 3453 if (xfer->rqflags & URQ_REQUEST) 3454 panic("ehci_device_bulk_start: a request"); 3455 #endif 3456 3457 len = xfer->length; 3458 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3459 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3460 sqh = epipe->sqh; 3461 3462 epipe->u.bulk.length = len; 3463 3464 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3465 &dataend); 3466 if (err) { 3467 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3468 xfer->status = err; 3469 usb_transfer_complete(xfer); 3470 return (err); 3471 } 3472 3473 #ifdef EHCI_DEBUG 3474 if (ehcidebug > 5) { 3475 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3476 ehci_dump_sqh(sqh); 3477 ehci_dump_sqtds(data); 3478 } 3479 #endif 3480 3481 /* Set up interrupt info. */ 3482 exfer->sqtdstart = data; 3483 exfer->sqtdend = dataend; 3484 #ifdef DIAGNOSTIC 3485 if (!exfer->isdone) { 3486 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3487 } 3488 exfer->isdone = 0; 3489 #endif 3490 3491 s = splusb(); 3492 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3493 if (xfer->timeout && !sc->sc_bus.use_polling) { 3494 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3495 ehci_timeout, xfer); 3496 } 3497 ehci_add_intr_list(sc, exfer); 3498 xfer->status = USBD_IN_PROGRESS; 3499 splx(s); 3500 3501 #ifdef EHCI_DEBUG 3502 if (ehcidebug > 10) { 3503 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3504 delay(10000); 3505 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3506 ehci_dump_regs(sc); 3507 #if 0 3508 printf("async_head:\n"); 3509 ehci_dump_sqh(sc->sc_async_head); 3510 #endif 3511 printf("sqh:\n"); 3512 ehci_dump_sqh(sqh); 3513 ehci_dump_sqtds(data); 3514 } 3515 #endif 3516 3517 if (sc->sc_bus.use_polling) 3518 ehci_waitintr(sc, xfer); 3519 3520 return (USBD_IN_PROGRESS); 3521 #undef exfer 3522 } 3523 3524 Static void 3525 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3526 { 3527 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3528 ehci_abort_xfer(xfer, USBD_CANCELLED); 3529 } 3530 3531 /* 3532 * Close a device bulk pipe. 3533 */ 3534 Static void 3535 ehci_device_bulk_close(usbd_pipe_handle pipe) 3536 { 3537 ehci_softc_t *sc = pipe->device->bus->hci_private; 3538 3539 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3540 ehci_close_pipe(pipe, sc->sc_async_head); 3541 } 3542 3543 void 3544 ehci_device_bulk_done(usbd_xfer_handle xfer) 3545 { 3546 struct ehci_xfer *ex = EXFER(xfer); 3547 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3548 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3549 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3550 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3551 3552 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3553 xfer, xfer->actlen)); 3554 3555 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3556 ehci_del_intr_list(ex); /* remove from active list */ 3557 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3558 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3559 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3560 } 3561 3562 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3563 } 3564 3565 /************************/ 3566 3567 Static usbd_status 3568 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3569 { 3570 struct ehci_soft_islot *isp; 3571 int islot, lev; 3572 3573 /* Find a poll rate that is large enough. */ 3574 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3575 if (EHCI_ILEV_IVAL(lev) <= ival) 3576 break; 3577 3578 /* Pick an interrupt slot at the right level. */ 3579 /* XXX could do better than picking at random */ 3580 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3581 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3582 3583 sqh->islot = islot; 3584 isp = &sc->sc_islots[islot]; 3585 ehci_add_qh(sqh, isp->sqh); 3586 3587 return (USBD_NORMAL_COMPLETION); 3588 } 3589 3590 Static usbd_status 3591 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3592 { 3593 usbd_status err; 3594 3595 /* Insert last in queue. */ 3596 err = usb_insert_transfer(xfer); 3597 if (err) 3598 return (err); 3599 3600 /* 3601 * Pipe isn't running (otherwise err would be USBD_INPROG), 3602 * so start it first. 3603 */ 3604 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3605 } 3606 3607 Static usbd_status 3608 ehci_device_intr_start(usbd_xfer_handle xfer) 3609 { 3610 #define exfer EXFER(xfer) 3611 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3612 usbd_device_handle dev = xfer->pipe->device; 3613 ehci_softc_t *sc = dev->bus->hci_private; 3614 ehci_soft_qtd_t *data, *dataend; 3615 ehci_soft_qh_t *sqh; 3616 usbd_status err; 3617 int len, isread, endpt; 3618 int s; 3619 3620 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3621 xfer, xfer->length, xfer->flags)); 3622 3623 if (sc->sc_dying) 3624 return (USBD_IOERROR); 3625 3626 #ifdef DIAGNOSTIC 3627 if (xfer->rqflags & URQ_REQUEST) 3628 panic("ehci_device_intr_start: a request"); 3629 #endif 3630 3631 len = xfer->length; 3632 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3633 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3634 sqh = epipe->sqh; 3635 3636 epipe->u.intr.length = len; 3637 3638 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3639 &dataend); 3640 if (err) { 3641 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3642 xfer->status = err; 3643 usb_transfer_complete(xfer); 3644 return (err); 3645 } 3646 3647 #ifdef EHCI_DEBUG 3648 if (ehcidebug > 5) { 3649 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3650 ehci_dump_sqh(sqh); 3651 ehci_dump_sqtds(data); 3652 } 3653 #endif 3654 3655 /* Set up interrupt info. */ 3656 exfer->sqtdstart = data; 3657 exfer->sqtdend = dataend; 3658 #ifdef DIAGNOSTIC 3659 if (!exfer->isdone) { 3660 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3661 } 3662 exfer->isdone = 0; 3663 #endif 3664 3665 s = splusb(); 3666 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3667 if (xfer->timeout && !sc->sc_bus.use_polling) { 3668 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3669 ehci_timeout, xfer); 3670 } 3671 ehci_add_intr_list(sc, exfer); 3672 xfer->status = USBD_IN_PROGRESS; 3673 splx(s); 3674 3675 #ifdef EHCI_DEBUG 3676 if (ehcidebug > 10) { 3677 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3678 delay(10000); 3679 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3680 ehci_dump_regs(sc); 3681 printf("sqh:\n"); 3682 ehci_dump_sqh(sqh); 3683 ehci_dump_sqtds(data); 3684 } 3685 #endif 3686 3687 if (sc->sc_bus.use_polling) 3688 ehci_waitintr(sc, xfer); 3689 3690 return (USBD_IN_PROGRESS); 3691 #undef exfer 3692 } 3693 3694 Static void 3695 ehci_device_intr_abort(usbd_xfer_handle xfer) 3696 { 3697 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3698 if (xfer->pipe->intrxfer == xfer) { 3699 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3700 xfer->pipe->intrxfer = NULL; 3701 } 3702 /* 3703 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3704 * async doorbell. That's dependant on the async list, wheras 3705 * intr xfers are periodic, should not use this? 3706 */ 3707 ehci_abort_xfer(xfer, USBD_CANCELLED); 3708 } 3709 3710 Static void 3711 ehci_device_intr_close(usbd_pipe_handle pipe) 3712 { 3713 ehci_softc_t *sc = pipe->device->bus->hci_private; 3714 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3715 struct ehci_soft_islot *isp; 3716 3717 isp = &sc->sc_islots[epipe->sqh->islot]; 3718 ehci_close_pipe(pipe, isp->sqh); 3719 } 3720 3721 Static void 3722 ehci_device_intr_done(usbd_xfer_handle xfer) 3723 { 3724 #define exfer EXFER(xfer) 3725 struct ehci_xfer *ex = EXFER(xfer); 3726 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3727 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3728 ehci_soft_qtd_t *data, *dataend; 3729 ehci_soft_qh_t *sqh; 3730 usbd_status err; 3731 int len, isread, endpt, s; 3732 3733 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3734 xfer, xfer->actlen)); 3735 3736 if (xfer->pipe->repeat) { 3737 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3738 3739 len = epipe->u.intr.length; 3740 xfer->length = len; 3741 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3742 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3743 usb_syncmem(&xfer->dmabuf, 0, len, 3744 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3745 sqh = epipe->sqh; 3746 3747 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3748 &data, &dataend); 3749 if (err) { 3750 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3751 xfer->status = err; 3752 return; 3753 } 3754 3755 /* Set up interrupt info. */ 3756 exfer->sqtdstart = data; 3757 exfer->sqtdend = dataend; 3758 #ifdef DIAGNOSTIC 3759 if (!exfer->isdone) { 3760 printf("ehci_device_intr_done: not done, ex=%p\n", 3761 exfer); 3762 } 3763 exfer->isdone = 0; 3764 #endif 3765 3766 s = splusb(); 3767 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3768 if (xfer->timeout && !sc->sc_bus.use_polling) { 3769 usb_callout(xfer->timeout_handle, 3770 mstohz(xfer->timeout), ehci_timeout, xfer); 3771 } 3772 splx(s); 3773 3774 xfer->status = USBD_IN_PROGRESS; 3775 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3776 ehci_del_intr_list(ex); /* remove from active list */ 3777 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3778 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3779 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3780 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3781 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3782 } 3783 #undef exfer 3784 } 3785 3786 /************************/ 3787 3788 Static usbd_status 3789 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3790 { 3791 usbd_status err; 3792 3793 err = usb_insert_transfer(xfer); 3794 if (err && err != USBD_IN_PROGRESS) 3795 return err; 3796 3797 return ehci_device_isoc_start(xfer); 3798 } 3799 3800 Static usbd_status 3801 ehci_device_isoc_start(usbd_xfer_handle xfer) 3802 { 3803 struct ehci_pipe *epipe; 3804 usbd_device_handle dev; 3805 ehci_softc_t *sc; 3806 struct ehci_xfer *exfer; 3807 ehci_soft_itd_t *itd, *prev, *start, *stop; 3808 usb_dma_t *dma_buf; 3809 int i, j, k, frames, uframes; 3810 int s, trans_count, offs, total_length; 3811 int frindex; 3812 3813 start = NULL; 3814 prev = NULL; 3815 itd = NULL; 3816 trans_count = 0; 3817 total_length = 0; 3818 exfer = (struct ehci_xfer *) xfer; 3819 sc = xfer->pipe->device->bus->hci_private; 3820 dev = xfer->pipe->device; 3821 epipe = (struct ehci_pipe *)xfer->pipe; 3822 3823 /* 3824 * To allow continuous transfers, above we start all transfers 3825 * immediately. However, we're still going to get usbd_start_next call 3826 * this when another xfer completes. So, check if this is already 3827 * in progress or not 3828 */ 3829 3830 if (exfer->itdstart != NULL) 3831 return USBD_IN_PROGRESS; 3832 3833 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3834 xfer, xfer->length, xfer->flags)); 3835 3836 if (sc->sc_dying) 3837 return USBD_IOERROR; 3838 3839 /* 3840 * To avoid complication, don't allow a request right now that'll span 3841 * the entire frame table. To within 4 frames, to allow some leeway 3842 * on either side of where the hc currently is. 3843 */ 3844 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3845 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3846 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3847 return USBD_INVAL; 3848 } 3849 3850 #ifdef DIAGNOSTIC 3851 if (xfer->rqflags & URQ_REQUEST) 3852 panic("ehci_device_isoc_start: request\n"); 3853 3854 if (!exfer->isdone) 3855 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3856 exfer->isdone = 0; 3857 #endif 3858 3859 /* 3860 * Step 1: Allocate and initialize itds, how many do we need? 3861 * One per transfer if interval >= 8 microframes, fewer if we use 3862 * multiple microframes per frame. 3863 */ 3864 3865 i = epipe->pipe.endpoint->edesc->bInterval; 3866 if (i > 16 || i == 0) { 3867 /* Spec page 271 says intervals > 16 are invalid */ 3868 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3869 return USBD_INVAL; 3870 } else if (i >= 4) { 3871 frames = xfer->nframes; 3872 uframes = 8; 3873 } else { 3874 frames = xfer->nframes + 0x7; /* 7 added for rounding up */ 3875 uframes = 0; 3876 switch (i) { 3877 case 1: frames /= 8; uframes = 1; break; 3878 case 2: frames /= 4; uframes = 2; break; 3879 case 3: frames /= 2; uframes = 4; break; 3880 } 3881 } 3882 3883 if (frames == 0) { 3884 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3885 return USBD_INVAL; 3886 } 3887 3888 dma_buf = &xfer->dmabuf; 3889 offs = 0; 3890 3891 for (i = 0; i < frames; i++) { 3892 int froffs = offs; 3893 itd = ehci_alloc_itd(sc); 3894 3895 if (prev != NULL) { 3896 prev->itd.itd_next = 3897 htole32(itd->physaddr | EHCI_LINK_ITD); 3898 usb_syncmem(&itd->dma, 3899 itd->offs + offsetof(ehci_itd_t, itd_next), 3900 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 3901 3902 prev->xfer_next = itd; 3903 } else { 3904 start = itd; 3905 } 3906 3907 /* 3908 * Step 1.5, initialize uframes 3909 */ 3910 for (j = 0; j < 8; j += uframes) { 3911 /* Calculate which page in the list this starts in */ 3912 int addr = DMAADDR(dma_buf, froffs); 3913 addr = EHCI_PAGE_OFFSET(addr); 3914 addr += (offs - froffs); 3915 addr = EHCI_PAGE(addr); 3916 addr /= EHCI_PAGE_SIZE; 3917 3918 /* This gets the initial offset into the first page, 3919 * looks how far further along the current uframe 3920 * offset is. Works out how many pages that is. 3921 */ 3922 3923 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3924 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3925 EHCI_ITD_SET_PG(addr) | 3926 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 3927 3928 total_length += xfer->frlengths[trans_count]; 3929 offs += xfer->frlengths[trans_count]; 3930 trans_count++; 3931 3932 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3933 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3934 } 3935 } 3936 3937 /* Step 1.75, set buffer pointers. To simplify matters, all 3938 * pointers are filled out for the next 7 hardware pages in 3939 * the dma block, so no need to worry what pages to cover 3940 * and what to not. 3941 */ 3942 3943 for (j=0; j < 7; j++) { 3944 /* 3945 * Don't try to lookup a page that's past the end 3946 * of buffer 3947 */ 3948 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 3949 if (page_offs >= dma_buf->block->size) 3950 break; 3951 3952 int page = DMAADDR(dma_buf, page_offs); 3953 page = EHCI_PAGE(page); 3954 itd->itd.itd_bufr[j] = 3955 htole32(EHCI_ITD_SET_BPTR(page) | 3956 EHCI_LINK_ITD); 3957 } 3958 3959 /* 3960 * Other special values 3961 */ 3962 3963 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3964 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3965 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3966 3967 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3968 ? 1 : 0; 3969 j = UE_GET_SIZE(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)); 3970 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3971 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3972 3973 /* FIXME: handle invalid trans */ 3974 itd->itd.itd_bufr[2] |= 3975 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3976 3977 usb_syncmem(&itd->dma, 3978 itd->offs + offsetof(ehci_itd_t, itd_next), 3979 sizeof(ehci_itd_t), 3980 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3981 3982 prev = itd; 3983 } /* End of frame */ 3984 3985 stop = itd; 3986 stop->xfer_next = NULL; 3987 exfer->isoc_len = total_length; 3988 3989 /* 3990 * Part 2: Transfer descriptors have now been set up, now they must 3991 * be scheduled into the period frame list. Erk. Not wanting to 3992 * complicate matters, transfer is denied if the transfer spans 3993 * more than the period frame list. 3994 */ 3995 3996 s = splusb(); 3997 3998 /* Start inserting frames */ 3999 if (epipe->u.isoc.cur_xfers > 0) { 4000 frindex = epipe->u.isoc.next_frame; 4001 } else { 4002 frindex = EOREAD4(sc, EHCI_FRINDEX); 4003 frindex = frindex >> 3; /* Erase microframe index */ 4004 frindex += 2; 4005 } 4006 4007 if (frindex >= sc->sc_flsize) 4008 frindex &= (sc->sc_flsize - 1); 4009 4010 /* Whats the frame interval? */ 4011 i = (1 << epipe->pipe.endpoint->edesc->bInterval); 4012 if (i / 8 == 0) 4013 i = 1; 4014 else 4015 i /= 8; 4016 4017 itd = start; 4018 for (j = 0; j < frames; j++) { 4019 if (itd == NULL) 4020 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4021 4022 itd->itd.itd_next = sc->sc_flist[frindex]; 4023 if (itd->itd.itd_next == 0) 4024 /* FIXME: frindex table gets initialized to NULL 4025 * or EHCI_NULL? */ 4026 itd->itd.itd_next = htole32(EHCI_NULL); 4027 4028 usb_syncmem(&itd->dma, 4029 itd->offs + offsetof(ehci_itd_t, itd_next), 4030 sizeof(itd->itd.itd_next), 4031 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4032 4033 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4034 4035 usb_syncmem(&sc->sc_fldma, 4036 sizeof(ehci_link_t) * frindex, 4037 sizeof(ehci_link_t), 4038 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4039 4040 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4041 sc->sc_softitds[frindex] = itd; 4042 if (itd->u.frame_list.next != NULL) 4043 itd->u.frame_list.next->u.frame_list.prev = itd; 4044 itd->slot = frindex; 4045 itd->u.frame_list.prev = NULL; 4046 4047 frindex += i; 4048 if (frindex >= sc->sc_flsize) 4049 frindex -= sc->sc_flsize; 4050 4051 itd = itd->xfer_next; 4052 } 4053 4054 epipe->u.isoc.cur_xfers++; 4055 epipe->u.isoc.next_frame = frindex; 4056 4057 exfer->itdstart = start; 4058 exfer->itdend = stop; 4059 exfer->sqtdstart = NULL; 4060 exfer->sqtdstart = NULL; 4061 4062 ehci_add_intr_list(sc, exfer); 4063 xfer->status = USBD_IN_PROGRESS; 4064 xfer->done = 0; 4065 splx(s); 4066 4067 if (sc->sc_bus.use_polling) { 4068 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4069 ehci_waitintr(sc, xfer); 4070 } 4071 4072 return USBD_IN_PROGRESS; 4073 } 4074 4075 Static void 4076 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4077 { 4078 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4079 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4080 } 4081 4082 Static void 4083 ehci_device_isoc_close(usbd_pipe_handle pipe) 4084 { 4085 printf("ehci_device_isoc_close: nothing in the pipe to free?\n"); 4086 } 4087 4088 Static void 4089 ehci_device_isoc_done(usbd_xfer_handle xfer) 4090 { 4091 struct ehci_xfer *exfer; 4092 ehci_softc_t *sc; 4093 struct ehci_pipe *epipe; 4094 int s; 4095 4096 exfer = EXFER(xfer); 4097 sc = xfer->pipe->device->bus->hci_private; 4098 epipe = (struct ehci_pipe *) xfer->pipe; 4099 4100 s = splusb(); 4101 epipe->u.isoc.cur_xfers--; 4102 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4103 ehci_del_intr_list(exfer); 4104 ehci_rem_free_itd_chain(sc, exfer); 4105 } 4106 splx(s); 4107 4108 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4109 BUS_DMASYNC_POSTREAD); 4110 4111 } 4112
Indexes created Tue Sep 23 07:09:52 GMT 2025