ehci.c revision 1.151
1 /* $NetBSD: ehci.c,v 1.151 2008/10/11 05:17:12 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum and 9 * Jeremy Morse (jeremy.morse (at) gmail.com). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 35 * 36 * The EHCI 1.0 spec can be found at 37 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/usb_20.zip 40 * 41 */ 42 43 /* 44 * TODO: 45 * 1) hold off explorations by companion controllers until ehci has started. 46 * 47 * 2) The hub driver needs to handle and schedule the transaction translator, 48 * to assign place in frame where different devices get to go. See chapter 49 * on hubs in USB 2.0 for details. 50 * 51 * 3) command failures are not recovered correctly 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.151 2008/10/11 05:17:12 jmcneill Exp $"); 56 57 #include "ohci.h" 58 #include "uhci.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/kernel.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/select.h> 66 #include <sys/proc.h> 67 #include <sys/queue.h> 68 #include <sys/mutex.h> 69 #include <sys/bus.h> 70 71 #include <machine/endian.h> 72 73 #include <dev/usb/usb.h> 74 #include <dev/usb/usbdi.h> 75 #include <dev/usb/usbdivar.h> 76 #include <dev/usb/usb_mem.h> 77 #include <dev/usb/usb_quirks.h> 78 79 #include <dev/usb/ehcireg.h> 80 #include <dev/usb/ehcivar.h> 81 #include <dev/usb/usbroothub_subr.h> 82 83 #ifdef EHCI_DEBUG 84 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 85 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 86 int ehcidebug = 0; 87 #ifndef __NetBSD__ 88 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 89 #endif 90 #else 91 #define DPRINTF(x) 92 #define DPRINTFN(n,x) 93 #endif 94 95 struct ehci_pipe { 96 struct usbd_pipe pipe; 97 int nexttoggle; 98 99 ehci_soft_qh_t *sqh; 100 union { 101 ehci_soft_qtd_t *qtd; 102 /* ehci_soft_itd_t *itd; */ 103 } tail; 104 union { 105 /* Control pipe */ 106 struct { 107 usb_dma_t reqdma; 108 u_int length; 109 } ctl; 110 /* Interrupt pipe */ 111 struct { 112 u_int length; 113 } intr; 114 /* Bulk pipe */ 115 struct { 116 u_int length; 117 } bulk; 118 /* Iso pipe */ 119 struct { 120 u_int next_frame; 121 u_int cur_xfers; 122 } isoc; 123 } u; 124 }; 125 126 Static usbd_status ehci_open(usbd_pipe_handle); 127 Static void ehci_poll(struct usbd_bus *); 128 Static void ehci_softintr(void *); 129 Static int ehci_intr1(ehci_softc_t *); 130 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 131 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 132 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 133 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 134 Static void ehci_idone(struct ehci_xfer *); 135 Static void ehci_timeout(void *); 136 Static void ehci_timeout_task(void *); 137 Static void ehci_intrlist_timeout(void *); 138 139 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 140 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 141 142 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 143 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 144 145 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 146 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 147 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 148 Static void ehci_root_ctrl_close(usbd_pipe_handle); 149 Static void ehci_root_ctrl_done(usbd_xfer_handle); 150 151 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 152 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 153 Static void ehci_root_intr_abort(usbd_xfer_handle); 154 Static void ehci_root_intr_close(usbd_pipe_handle); 155 Static void ehci_root_intr_done(usbd_xfer_handle); 156 157 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 158 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 159 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 160 Static void ehci_device_ctrl_close(usbd_pipe_handle); 161 Static void ehci_device_ctrl_done(usbd_xfer_handle); 162 163 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 164 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 165 Static void ehci_device_bulk_abort(usbd_xfer_handle); 166 Static void ehci_device_bulk_close(usbd_pipe_handle); 167 Static void ehci_device_bulk_done(usbd_xfer_handle); 168 169 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 170 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 171 Static void ehci_device_intr_abort(usbd_xfer_handle); 172 Static void ehci_device_intr_close(usbd_pipe_handle); 173 Static void ehci_device_intr_done(usbd_xfer_handle); 174 175 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 176 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 177 Static void ehci_device_isoc_abort(usbd_xfer_handle); 178 Static void ehci_device_isoc_close(usbd_pipe_handle); 179 Static void ehci_device_isoc_done(usbd_xfer_handle); 180 181 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 182 Static void ehci_noop(usbd_pipe_handle pipe); 183 184 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 185 Static void ehci_disown(ehci_softc_t *, int, int); 186 187 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 188 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 189 190 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 191 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 192 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 193 ehci_softc_t *, int, int, usbd_xfer_handle, 194 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 195 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 196 ehci_soft_qtd_t *); 197 198 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 199 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 200 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 201 struct ehci_xfer *exfer); 202 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 203 usbd_status status); 204 205 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 206 207 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 208 int ival); 209 210 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 211 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 212 ehci_soft_qh_t *); 213 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 214 Static void ehci_sync_hc(ehci_softc_t *); 215 216 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 217 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 218 219 #ifdef EHCI_DEBUG 220 Static void ehci_dump_regs(ehci_softc_t *); 221 void ehci_dump(void); 222 Static ehci_softc_t *theehci; 223 Static void ehci_dump_link(ehci_link_t, int); 224 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 225 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 226 Static void ehci_dump_qtd(ehci_qtd_t *); 227 Static void ehci_dump_sqh(ehci_soft_qh_t *); 228 #if notyet 229 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 230 Static void ehci_dump_itd(struct ehci_soft_itd *); 231 #endif 232 #ifdef DIAGNOSTIC 233 Static void ehci_dump_exfer(struct ehci_xfer *); 234 #endif 235 #endif 236 237 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 238 239 #define EHCI_INTR_ENDPT 1 240 241 #define ehci_add_intr_list(sc, ex) \ 242 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext); 243 #define ehci_del_intr_list(ex) \ 244 do { \ 245 LIST_REMOVE((ex), inext); \ 246 (ex)->inext.le_prev = NULL; \ 247 } while (0) 248 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL) 249 250 Static const struct usbd_bus_methods ehci_bus_methods = { 251 ehci_open, 252 ehci_softintr, 253 ehci_poll, 254 ehci_allocm, 255 ehci_freem, 256 ehci_allocx, 257 ehci_freex, 258 }; 259 260 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 261 ehci_root_ctrl_transfer, 262 ehci_root_ctrl_start, 263 ehci_root_ctrl_abort, 264 ehci_root_ctrl_close, 265 ehci_noop, 266 ehci_root_ctrl_done, 267 }; 268 269 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 270 ehci_root_intr_transfer, 271 ehci_root_intr_start, 272 ehci_root_intr_abort, 273 ehci_root_intr_close, 274 ehci_noop, 275 ehci_root_intr_done, 276 }; 277 278 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 279 ehci_device_ctrl_transfer, 280 ehci_device_ctrl_start, 281 ehci_device_ctrl_abort, 282 ehci_device_ctrl_close, 283 ehci_noop, 284 ehci_device_ctrl_done, 285 }; 286 287 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 288 ehci_device_intr_transfer, 289 ehci_device_intr_start, 290 ehci_device_intr_abort, 291 ehci_device_intr_close, 292 ehci_device_clear_toggle, 293 ehci_device_intr_done, 294 }; 295 296 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 297 ehci_device_bulk_transfer, 298 ehci_device_bulk_start, 299 ehci_device_bulk_abort, 300 ehci_device_bulk_close, 301 ehci_device_clear_toggle, 302 ehci_device_bulk_done, 303 }; 304 305 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 306 ehci_device_isoc_transfer, 307 ehci_device_isoc_start, 308 ehci_device_isoc_abort, 309 ehci_device_isoc_close, 310 ehci_noop, 311 ehci_device_isoc_done, 312 }; 313 314 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 315 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 316 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 317 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 318 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 319 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 320 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 321 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 322 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 323 }; 324 325 usbd_status 326 ehci_init(ehci_softc_t *sc) 327 { 328 u_int32_t vers, sparams, cparams, hcr; 329 u_int i; 330 usbd_status err; 331 ehci_soft_qh_t *sqh; 332 u_int ncomp; 333 334 DPRINTF(("ehci_init: start\n")); 335 #ifdef EHCI_DEBUG 336 theehci = sc; 337 #endif 338 339 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 340 341 vers = EREAD2(sc, EHCI_HCIVERSION); 342 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 343 vers >> 8, vers & 0xff); 344 345 sparams = EREAD4(sc, EHCI_HCSPARAMS); 346 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 347 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 348 ncomp = EHCI_HCS_N_CC(sparams); 349 if (ncomp != sc->sc_ncomp) { 350 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 351 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 352 #if NOHCI == 0 || NUHCI == 0 353 aprint_error("%s: ohci or uhci probably not configured\n", 354 device_xname(sc->sc_dev)); 355 #endif 356 if (ncomp < sc->sc_ncomp) 357 sc->sc_ncomp = ncomp; 358 } 359 if (sc->sc_ncomp > 0) { 360 aprint_normal("%s: companion controller%s, %d port%s each:", 361 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 362 EHCI_HCS_N_PCC(sparams), 363 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 364 for (i = 0; i < sc->sc_ncomp; i++) 365 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 366 aprint_normal("\n"); 367 } 368 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 369 cparams = EREAD4(sc, EHCI_HCCPARAMS); 370 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 371 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 372 373 if (EHCI_HCC_64BIT(cparams)) { 374 /* MUST clear segment register if 64 bit capable. */ 375 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 376 } 377 378 sc->sc_bus.usbrev = USBREV_2_0; 379 380 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 381 USB_MEM_RESERVE); 382 383 /* Reset the controller */ 384 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 385 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 386 usb_delay_ms(&sc->sc_bus, 1); 387 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 388 for (i = 0; i < 100; i++) { 389 usb_delay_ms(&sc->sc_bus, 1); 390 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 391 if (!hcr) 392 break; 393 } 394 if (hcr) { 395 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 396 return (USBD_IOERROR); 397 } 398 399 /* XXX need proper intr scheduling */ 400 sc->sc_rand = 96; 401 402 /* frame list size at default, read back what we got and use that */ 403 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 404 case 0: sc->sc_flsize = 1024; break; 405 case 1: sc->sc_flsize = 512; break; 406 case 2: sc->sc_flsize = 256; break; 407 case 3: return (USBD_IOERROR); 408 } 409 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 410 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 411 if (err) 412 return (err); 413 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 414 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 415 416 for (i = 0; i < sc->sc_flsize; i++) { 417 sc->sc_flist[i] = EHCI_NULL; 418 } 419 420 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 421 422 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 423 M_USB, M_NOWAIT | M_ZERO); 424 if (sc->sc_softitds == NULL) 425 return ENOMEM; 426 LIST_INIT(&sc->sc_freeitds); 427 428 /* Set up the bus struct. */ 429 sc->sc_bus.methods = &ehci_bus_methods; 430 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 431 432 sc->sc_eintrs = EHCI_NORMAL_INTRS; 433 434 /* 435 * Allocate the interrupt dummy QHs. These are arranged to give poll 436 * intervals that are powers of 2 times 1ms. 437 */ 438 for (i = 0; i < EHCI_INTRQHS; i++) { 439 sqh = ehci_alloc_sqh(sc); 440 if (sqh == NULL) { 441 err = USBD_NOMEM; 442 goto bad1; 443 } 444 sc->sc_islots[i].sqh = sqh; 445 } 446 for (i = 0; i < EHCI_INTRQHS; i++) { 447 sqh = sc->sc_islots[i].sqh; 448 if (i == 0) { 449 /* The last (1ms) QH terminates. */ 450 sqh->qh.qh_link = EHCI_NULL; 451 sqh->next = NULL; 452 } else { 453 /* Otherwise the next QH has half the poll interval */ 454 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 455 sqh->qh.qh_link = htole32(sqh->next->physaddr | 456 EHCI_LINK_QH); 457 } 458 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 459 sqh->qh.qh_curqtd = EHCI_NULL; 460 sqh->next = NULL; 461 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 462 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 463 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 464 sqh->sqtd = NULL; 465 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 466 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 467 } 468 /* Point the frame list at the last level (128ms). */ 469 for (i = 0; i < sc->sc_flsize; i++) { 470 int j; 471 472 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 473 revbits[i & (EHCI_MAX_POLLRATE-1)]; 474 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 475 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 476 i)].sqh->physaddr); 477 } 478 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 479 BUS_DMASYNC_PREWRITE); 480 481 /* Allocate dummy QH that starts the async list. */ 482 sqh = ehci_alloc_sqh(sc); 483 if (sqh == NULL) { 484 err = USBD_NOMEM; 485 goto bad1; 486 } 487 /* Fill the QH */ 488 sqh->qh.qh_endp = 489 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 490 sqh->qh.qh_link = 491 htole32(sqh->physaddr | EHCI_LINK_QH); 492 sqh->qh.qh_curqtd = EHCI_NULL; 493 sqh->next = NULL; 494 /* Fill the overlay qTD */ 495 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 496 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 497 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 498 sqh->sqtd = NULL; 499 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 500 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 501 #ifdef EHCI_DEBUG 502 if (ehcidebug) { 503 ehci_dump_sqh(sqh); 504 } 505 #endif 506 507 /* Point to async list */ 508 sc->sc_async_head = sqh; 509 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 510 511 usb_callout_init(sc->sc_tmo_intrlist); 512 513 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE); 514 515 /* Turn on controller */ 516 EOWRITE4(sc, EHCI_USBCMD, 517 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 518 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 519 EHCI_CMD_ASE | 520 EHCI_CMD_PSE | 521 EHCI_CMD_RS); 522 523 /* Take over port ownership */ 524 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 525 526 for (i = 0; i < 100; i++) { 527 usb_delay_ms(&sc->sc_bus, 1); 528 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 529 if (!hcr) 530 break; 531 } 532 if (hcr) { 533 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 534 return (USBD_IOERROR); 535 } 536 537 /* Enable interrupts */ 538 DPRINTFN(1,("ehci_init: enabling\n")); 539 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 540 541 return (USBD_NORMAL_COMPLETION); 542 543 #if 0 544 bad2: 545 ehci_free_sqh(sc, sc->sc_async_head); 546 #endif 547 bad1: 548 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 549 return (err); 550 } 551 552 int 553 ehci_intr(void *v) 554 { 555 ehci_softc_t *sc = v; 556 557 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 558 return (0); 559 560 /* If we get an interrupt while polling, then just ignore it. */ 561 if (sc->sc_bus.use_polling) { 562 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 563 564 if (intrs) 565 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 566 #ifdef DIAGNOSTIC 567 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 568 #endif 569 return (0); 570 } 571 572 return (ehci_intr1(sc)); 573 } 574 575 Static int 576 ehci_intr1(ehci_softc_t *sc) 577 { 578 u_int32_t intrs, eintrs; 579 580 DPRINTFN(20,("ehci_intr1: enter\n")); 581 582 /* In case the interrupt occurs before initialization has completed. */ 583 if (sc == NULL) { 584 #ifdef DIAGNOSTIC 585 printf("ehci_intr1: sc == NULL\n"); 586 #endif 587 return (0); 588 } 589 590 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 591 if (!intrs) 592 return (0); 593 594 eintrs = intrs & sc->sc_eintrs; 595 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 596 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 597 (u_int)eintrs)); 598 if (!eintrs) 599 return (0); 600 601 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 602 sc->sc_bus.intr_context++; 603 sc->sc_bus.no_intrs++; 604 if (eintrs & EHCI_STS_IAA) { 605 DPRINTF(("ehci_intr1: door bell\n")); 606 wakeup(&sc->sc_async_head); 607 eintrs &= ~EHCI_STS_IAA; 608 } 609 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 610 DPRINTFN(5,("ehci_intr1: %s %s\n", 611 eintrs & EHCI_STS_INT ? "INT" : "", 612 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 613 usb_schedsoftintr(&sc->sc_bus); 614 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 615 } 616 if (eintrs & EHCI_STS_HSE) { 617 printf("%s: unrecoverable error, controller halted\n", 618 device_xname(sc->sc_dev)); 619 /* XXX what else */ 620 } 621 if (eintrs & EHCI_STS_PCD) { 622 ehci_pcd(sc, sc->sc_intrxfer); 623 eintrs &= ~EHCI_STS_PCD; 624 } 625 626 sc->sc_bus.intr_context--; 627 628 if (eintrs != 0) { 629 /* Block unprocessed interrupts. */ 630 sc->sc_eintrs &= ~eintrs; 631 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 632 printf("%s: blocking intrs 0x%x\n", 633 device_xname(sc->sc_dev), eintrs); 634 } 635 636 return (1); 637 } 638 639 640 void 641 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 642 { 643 usbd_pipe_handle pipe; 644 u_char *p; 645 int i, m; 646 647 if (xfer == NULL) { 648 /* Just ignore the change. */ 649 return; 650 } 651 652 pipe = xfer->pipe; 653 654 p = KERNADDR(&xfer->dmabuf, 0); 655 m = min(sc->sc_noport, xfer->length * 8 - 1); 656 memset(p, 0, xfer->length); 657 for (i = 1; i <= m; i++) { 658 /* Pick out CHANGE bits from the status reg. */ 659 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 660 p[i/8] |= 1 << (i%8); 661 } 662 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 663 xfer->actlen = xfer->length; 664 xfer->status = USBD_NORMAL_COMPLETION; 665 666 usb_transfer_complete(xfer); 667 } 668 669 void 670 ehci_softintr(void *v) 671 { 672 struct usbd_bus *bus = v; 673 ehci_softc_t *sc = bus->hci_private; 674 struct ehci_xfer *ex, *nextex; 675 676 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 677 sc->sc_bus.intr_context)); 678 679 sc->sc_bus.intr_context++; 680 681 /* 682 * The only explanation I can think of for why EHCI is as brain dead 683 * as UHCI interrupt-wise is that Intel was involved in both. 684 * An interrupt just tells us that something is done, we have no 685 * clue what, so we need to scan through all active transfers. :-( 686 */ 687 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 688 nextex = LIST_NEXT(ex, inext); 689 ehci_check_intr(sc, ex); 690 } 691 692 /* Schedule a callout to catch any dropped transactions. */ 693 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 694 !LIST_EMPTY(&sc->sc_intrhead)) 695 usb_callout(sc->sc_tmo_intrlist, hz, 696 ehci_intrlist_timeout, sc); 697 698 #ifdef USB_USE_SOFTINTR 699 if (sc->sc_softwake) { 700 sc->sc_softwake = 0; 701 wakeup(&sc->sc_softwake); 702 } 703 #endif /* USB_USE_SOFTINTR */ 704 705 sc->sc_bus.intr_context--; 706 } 707 708 /* Check for an interrupt. */ 709 void 710 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 711 { 712 int attr; 713 714 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 715 716 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 717 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 718 ehci_check_itd_intr(sc, ex); 719 else 720 ehci_check_qh_intr(sc, ex); 721 722 return; 723 } 724 725 void 726 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 727 { 728 ehci_soft_qtd_t *sqtd, *lsqtd; 729 __uint32_t status; 730 731 if (ex->sqtdstart == NULL) { 732 printf("ehci_check_qh_intr: not valid sqtd\n"); 733 return; 734 } 735 736 lsqtd = ex->sqtdend; 737 #ifdef DIAGNOSTIC 738 if (lsqtd == NULL) { 739 printf("ehci_check_qh_intr: lsqtd==0\n"); 740 return; 741 } 742 #endif 743 /* 744 * If the last TD is still active we need to check whether there 745 * is a an error somewhere in the middle, or whether there was a 746 * short packet (SPD and not ACTIVE). 747 */ 748 usb_syncmem(&lsqtd->dma, 749 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 750 sizeof(lsqtd->qtd.qtd_status), 751 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 752 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 753 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 754 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 755 usb_syncmem(&sqtd->dma, 756 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 757 sizeof(sqtd->qtd.qtd_status), 758 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 759 status = le32toh(sqtd->qtd.qtd_status); 760 usb_syncmem(&sqtd->dma, 761 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 762 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 763 /* If there's an active QTD the xfer isn't done. */ 764 if (status & EHCI_QTD_ACTIVE) 765 break; 766 /* Any kind of error makes the xfer done. */ 767 if (status & EHCI_QTD_HALTED) 768 goto done; 769 /* We want short packets, and it is short: it's done */ 770 if (EHCI_QTD_GET_BYTES(status) != 0) 771 goto done; 772 } 773 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 774 ex, ex->sqtdstart)); 775 usb_syncmem(&lsqtd->dma, 776 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 777 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 778 return; 779 } 780 done: 781 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 782 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 783 ehci_idone(ex); 784 } 785 786 void 787 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 788 ehci_soft_itd_t *itd; 789 int i; 790 791 if (ex->itdstart == NULL) { 792 printf("ehci_check_itd_intr: not valid itd\n"); 793 return; 794 } 795 796 itd = ex->itdend; 797 #ifdef DIAGNOSTIC 798 if (itd == NULL) { 799 printf("ehci_check_itd_intr: itdend == 0\n"); 800 return; 801 } 802 #endif 803 804 /* 805 * Step 1, check no active transfers in last itd, meaning we're finished 806 */ 807 808 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 809 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 810 BUS_DMASYNC_POSTREAD); 811 812 for (i = 0; i < 8; i++) { 813 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 814 continue; 815 break; 816 } 817 818 if (i == 8) { 819 goto done; /* All 8 descriptors inactive, it's done */ 820 } 821 822 /* 823 * Step 2, check for errors in status bits, throughout chain... 824 */ 825 826 DPRINTFN(12, ("ehci_check_itd_intr: active ex=%p\n", ex)); 827 828 for (itd = ex->itdstart; itd != ex->itdend; itd = itd->xfer_next) { 829 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 830 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 831 BUS_DMASYNC_POSTREAD); 832 833 for (i = 0; i < 8; i++) { 834 if (le32toh(itd->itd.itd_ctl[i]) & (EHCI_ITD_BUF_ERR | 835 EHCI_ITD_BABBLE | EHCI_ITD_ERROR)) 836 break; 837 } 838 if (i != 8) { /* Error in one of the itds */ 839 goto done; 840 } 841 } /* itd search loop */ 842 843 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 844 ex->itdstart)); 845 return; 846 847 done: 848 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 849 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 850 ehci_idone(ex); 851 } 852 853 void 854 ehci_idone(struct ehci_xfer *ex) 855 { 856 usbd_xfer_handle xfer = &ex->xfer; 857 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 858 ehci_soft_qtd_t *sqtd, *lsqtd; 859 u_int32_t status = 0, nstatus = 0; 860 int actlen; 861 862 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 863 #ifdef DIAGNOSTIC 864 { 865 int s = splhigh(); 866 if (ex->isdone) { 867 splx(s); 868 #ifdef EHCI_DEBUG 869 printf("ehci_idone: ex is done!\n "); 870 ehci_dump_exfer(ex); 871 #else 872 printf("ehci_idone: ex=%p is done!\n", ex); 873 #endif 874 return; 875 } 876 ex->isdone = 1; 877 splx(s); 878 } 879 #endif 880 if (xfer->status == USBD_CANCELLED || 881 xfer->status == USBD_TIMEOUT) { 882 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 883 return; 884 } 885 886 #ifdef EHCI_DEBUG 887 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 888 if (ehcidebug > 10) 889 ehci_dump_sqtds(ex->sqtdstart); 890 #endif 891 892 /* The transfer is done, compute actual length and status. */ 893 894 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 895 == UE_ISOCHRONOUS) { 896 /* Isoc transfer */ 897 struct ehci_soft_itd *itd; 898 int i, nframes, len, uframes; 899 900 nframes = 0; 901 actlen = 0; 902 903 switch (xfer->pipe->endpoint->edesc->bInterval) { 904 case 0: 905 panic("ehci: isoc xfer suddenly has 0 bInterval, invalid\n"); 906 case 1: uframes = 1; break; 907 case 2: uframes = 2; break; 908 case 3: uframes = 4; break; 909 default: uframes = 8; break; 910 } 911 912 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 913 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 914 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 915 BUS_DMASYNC_POSTREAD); 916 917 for (i = 0; i < 8; i += uframes) { 918 /* XXX - driver didn't fill in the frame full 919 * of uframes. This leads to scheduling 920 * inefficiencies, but working around 921 * this doubles complexity of tracking 922 * an xfer. 923 */ 924 if (nframes >= xfer->nframes) 925 break; 926 927 status = le32toh(itd->itd.itd_ctl[i]); 928 len = EHCI_ITD_GET_LEN(status); 929 xfer->frlengths[nframes++] = len; 930 actlen += len; 931 } 932 933 if (nframes >= xfer->nframes) 934 break; 935 } 936 937 xfer->actlen = actlen; 938 xfer->status = USBD_NORMAL_COMPLETION; 939 if (xfer->rqflags & URQ_DEV_DMABUF) { 940 usb_syncmem(&xfer->dmabuf, 0, ex->isoc_len, 941 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 942 } 943 944 goto end; 945 } 946 947 /* Continue processing xfers using queue heads */ 948 949 lsqtd = ex->sqtdend; 950 actlen = 0; 951 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 952 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 953 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 954 nstatus = le32toh(sqtd->qtd.qtd_status); 955 if (nstatus & EHCI_QTD_ACTIVE) 956 break; 957 958 status = nstatus; 959 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 960 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 961 } 962 963 964 /* 965 * If there are left over TDs we need to update the toggle. 966 * The default pipe doesn't need it since control transfers 967 * start the toggle at 0 every time. 968 * For a short transfer we need to update the toggle for the missing 969 * packets within the qTD. 970 */ 971 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 972 xfer->pipe->device->default_pipe != xfer->pipe) { 973 DPRINTFN(2, ("ehci_idone: need toggle update " 974 "status=%08x nstatus=%08x\n", status, nstatus)); 975 #if 0 976 ehci_dump_sqh(epipe->sqh); 977 ehci_dump_sqtds(ex->sqtdstart); 978 #endif 979 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 980 } 981 982 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 983 xfer->length, actlen, status)); 984 xfer->actlen = actlen; 985 if (status & EHCI_QTD_HALTED) { 986 #ifdef EHCI_DEBUG 987 char sbuf[128]; 988 989 bitmask_snprintf((u_int32_t)status, 990 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 991 "\3MISSED\1PINGSTATE", sbuf, sizeof(sbuf)); 992 993 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 994 "status 0x%s\n", 995 xfer->pipe->device->address, 996 xfer->pipe->endpoint->edesc->bEndpointAddress, 997 sbuf)); 998 if (ehcidebug > 2) { 999 ehci_dump_sqh(epipe->sqh); 1000 ehci_dump_sqtds(ex->sqtdstart); 1001 } 1002 #endif 1003 /* low&full speed has an extra error flag */ 1004 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1005 EHCI_QH_SPEED_HIGH) 1006 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1007 else 1008 status &= EHCI_QTD_STATERRS; 1009 if (status == 0) /* no other errors means a stall */ { 1010 xfer->status = USBD_STALLED; 1011 } else { 1012 xfer->status = USBD_IOERROR; /* more info XXX */ 1013 } 1014 /* XXX need to reset TT on missed microframe */ 1015 if (status & EHCI_QTD_MISSEDMICRO) { 1016 ehci_softc_t *sc = 1017 xfer->pipe->device->bus->hci_private; 1018 1019 printf("%s: missed microframe, TT reset not " 1020 "implemented, hub might be inoperational\n", 1021 device_xname(sc->sc_dev)); 1022 } 1023 } else { 1024 xfer->status = USBD_NORMAL_COMPLETION; 1025 } 1026 1027 end: 1028 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1029 * during this call, before methods->done is called: dma sync required 1030 * beforehand? */ 1031 usb_transfer_complete(xfer); 1032 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1033 } 1034 1035 /* 1036 * Wait here until controller claims to have an interrupt. 1037 * Then call ehci_intr and return. Use timeout to avoid waiting 1038 * too long. 1039 */ 1040 void 1041 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1042 { 1043 int timo; 1044 u_int32_t intrs; 1045 1046 xfer->status = USBD_IN_PROGRESS; 1047 for (timo = xfer->timeout; timo >= 0; timo--) { 1048 usb_delay_ms(&sc->sc_bus, 1); 1049 if (sc->sc_dying) 1050 break; 1051 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1052 sc->sc_eintrs; 1053 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1054 #ifdef EHCI_DEBUG 1055 if (ehcidebug > 15) 1056 ehci_dump_regs(sc); 1057 #endif 1058 if (intrs) { 1059 ehci_intr1(sc); 1060 if (xfer->status != USBD_IN_PROGRESS) 1061 return; 1062 } 1063 } 1064 1065 /* Timeout */ 1066 DPRINTF(("ehci_waitintr: timeout\n")); 1067 xfer->status = USBD_TIMEOUT; 1068 usb_transfer_complete(xfer); 1069 /* XXX should free TD */ 1070 } 1071 1072 void 1073 ehci_poll(struct usbd_bus *bus) 1074 { 1075 ehci_softc_t *sc = bus->hci_private; 1076 #ifdef EHCI_DEBUG 1077 static int last; 1078 int new; 1079 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1080 if (new != last) { 1081 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1082 last = new; 1083 } 1084 #endif 1085 1086 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1087 ehci_intr1(sc); 1088 } 1089 1090 void 1091 ehci_childdet(device_t self, device_t child) 1092 { 1093 struct ehci_softc *sc = device_private(self); 1094 1095 KASSERT(sc->sc_child == child); 1096 sc->sc_child = NULL; 1097 } 1098 1099 int 1100 ehci_detach(struct ehci_softc *sc, int flags) 1101 { 1102 int rv = 0; 1103 1104 if (sc->sc_child != NULL) 1105 rv = config_detach(sc->sc_child, flags); 1106 1107 if (rv != 0) 1108 return (rv); 1109 1110 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 1111 1112 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1113 1114 /* XXX free other data structures XXX */ 1115 mutex_destroy(&sc->sc_doorbell_lock); 1116 1117 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1118 1119 return (rv); 1120 } 1121 1122 1123 int 1124 ehci_activate(device_t self, enum devact act) 1125 { 1126 struct ehci_softc *sc = device_private(self); 1127 int rv = 0; 1128 1129 switch (act) { 1130 case DVACT_ACTIVATE: 1131 return (EOPNOTSUPP); 1132 1133 case DVACT_DEACTIVATE: 1134 sc->sc_dying = 1; 1135 if (sc->sc_child != NULL) 1136 rv = config_deactivate(sc->sc_child); 1137 break; 1138 } 1139 return (rv); 1140 } 1141 1142 /* 1143 * Handle suspend/resume. 1144 * 1145 * We need to switch to polling mode here, because this routine is 1146 * called from an interrupt context. This is all right since we 1147 * are almost suspended anyway. 1148 * 1149 * Note that this power handler isn't to be registered directly; the 1150 * bus glue needs to call out to it. 1151 */ 1152 bool 1153 ehci_suspend(device_t dv PMF_FN_ARGS) 1154 { 1155 ehci_softc_t *sc = device_private(dv); 1156 int i, s; 1157 uint32_t cmd, hcr; 1158 1159 s = splhardusb(); 1160 1161 sc->sc_bus.use_polling++; 1162 1163 for (i = 1; i <= sc->sc_noport; i++) { 1164 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1165 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1166 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1167 } 1168 1169 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1170 1171 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1172 EOWRITE4(sc, EHCI_USBCMD, cmd); 1173 1174 for (i = 0; i < 100; i++) { 1175 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1176 if (hcr == 0) 1177 break; 1178 1179 usb_delay_ms(&sc->sc_bus, 1); 1180 } 1181 if (hcr != 0) 1182 printf("%s: reset timeout\n", device_xname(dv)); 1183 1184 cmd &= ~EHCI_CMD_RS; 1185 EOWRITE4(sc, EHCI_USBCMD, cmd); 1186 1187 for (i = 0; i < 100; i++) { 1188 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1189 if (hcr == EHCI_STS_HCH) 1190 break; 1191 1192 usb_delay_ms(&sc->sc_bus, 1); 1193 } 1194 if (hcr != EHCI_STS_HCH) 1195 printf("%s: config timeout\n", device_xname(dv)); 1196 1197 sc->sc_bus.use_polling--; 1198 splx(s); 1199 1200 return true; 1201 } 1202 1203 bool 1204 ehci_resume(device_t dv PMF_FN_ARGS) 1205 { 1206 ehci_softc_t *sc = device_private(dv); 1207 int i; 1208 uint32_t cmd, hcr; 1209 1210 /* restore things in case the bios sucks */ 1211 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1212 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1213 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1214 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1215 1216 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1217 1218 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1219 1220 hcr = 0; 1221 for (i = 1; i <= sc->sc_noport; i++) { 1222 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1223 if ((cmd & EHCI_PS_PO) == 0 && 1224 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1225 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1226 hcr = 1; 1227 } 1228 } 1229 1230 if (hcr) { 1231 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1232 1233 for (i = 1; i <= sc->sc_noport; i++) { 1234 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1235 if ((cmd & EHCI_PS_PO) == 0 && 1236 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1237 EOWRITE4(sc, EHCI_PORTSC(i), 1238 cmd & ~EHCI_PS_FPR); 1239 } 1240 } 1241 1242 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1243 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1244 1245 for (i = 0; i < 100; i++) { 1246 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1247 if (hcr != EHCI_STS_HCH) 1248 break; 1249 1250 usb_delay_ms(&sc->sc_bus, 1); 1251 } 1252 if (hcr == EHCI_STS_HCH) 1253 printf("%s: config timeout\n", device_xname(dv)); 1254 1255 return true; 1256 } 1257 1258 /* 1259 * Shut down the controller when the system is going down. 1260 */ 1261 bool 1262 ehci_shutdown(device_t self, int flags) 1263 { 1264 ehci_softc_t *sc = device_private(self); 1265 1266 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1267 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1268 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1269 return true; 1270 } 1271 1272 usbd_status 1273 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1274 { 1275 struct ehci_softc *sc = bus->hci_private; 1276 usbd_status err; 1277 1278 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1279 if (err == USBD_NOMEM) 1280 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1281 #ifdef EHCI_DEBUG 1282 if (err) 1283 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1284 #endif 1285 return (err); 1286 } 1287 1288 void 1289 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1290 { 1291 struct ehci_softc *sc = bus->hci_private; 1292 1293 if (dma->block->flags & USB_DMA_RESERVE) { 1294 usb_reserve_freem(&sc->sc_dma_reserve, 1295 dma); 1296 return; 1297 } 1298 usb_freemem(&sc->sc_bus, dma); 1299 } 1300 1301 usbd_xfer_handle 1302 ehci_allocx(struct usbd_bus *bus) 1303 { 1304 struct ehci_softc *sc = bus->hci_private; 1305 usbd_xfer_handle xfer; 1306 1307 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1308 if (xfer != NULL) { 1309 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1310 #ifdef DIAGNOSTIC 1311 if (xfer->busy_free != XFER_FREE) { 1312 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1313 xfer->busy_free); 1314 } 1315 #endif 1316 } else { 1317 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1318 } 1319 if (xfer != NULL) { 1320 memset(xfer, 0, sizeof(struct ehci_xfer)); 1321 #ifdef DIAGNOSTIC 1322 EXFER(xfer)->isdone = 1; 1323 xfer->busy_free = XFER_BUSY; 1324 #endif 1325 } 1326 return (xfer); 1327 } 1328 1329 void 1330 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1331 { 1332 struct ehci_softc *sc = bus->hci_private; 1333 1334 #ifdef DIAGNOSTIC 1335 if (xfer->busy_free != XFER_BUSY) { 1336 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1337 xfer->busy_free); 1338 } 1339 xfer->busy_free = XFER_FREE; 1340 if (!EXFER(xfer)->isdone) { 1341 printf("ehci_freex: !isdone\n"); 1342 } 1343 #endif 1344 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1345 } 1346 1347 Static void 1348 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1349 { 1350 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1351 1352 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1353 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1354 #ifdef USB_DEBUG 1355 if (ehcidebug) 1356 usbd_dump_pipe(pipe); 1357 #endif 1358 epipe->nexttoggle = 0; 1359 } 1360 1361 Static void 1362 ehci_noop(usbd_pipe_handle pipe) 1363 { 1364 } 1365 1366 #ifdef EHCI_DEBUG 1367 void 1368 ehci_dump_regs(ehci_softc_t *sc) 1369 { 1370 int i; 1371 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1372 EOREAD4(sc, EHCI_USBCMD), 1373 EOREAD4(sc, EHCI_USBSTS), 1374 EOREAD4(sc, EHCI_USBINTR)); 1375 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1376 EOREAD4(sc, EHCI_FRINDEX), 1377 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1378 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1379 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1380 for (i = 1; i <= sc->sc_noport; i++) 1381 printf("port %d status=0x%08x\n", i, 1382 EOREAD4(sc, EHCI_PORTSC(i))); 1383 } 1384 1385 /* 1386 * Unused function - this is meant to be called from a kernel 1387 * debugger. 1388 */ 1389 void 1390 ehci_dump() 1391 { 1392 ehci_dump_regs(theehci); 1393 } 1394 1395 void 1396 ehci_dump_link(ehci_link_t link, int type) 1397 { 1398 link = le32toh(link); 1399 printf("0x%08x", link); 1400 if (link & EHCI_LINK_TERMINATE) 1401 printf("<T>"); 1402 else { 1403 printf("<"); 1404 if (type) { 1405 switch (EHCI_LINK_TYPE(link)) { 1406 case EHCI_LINK_ITD: printf("ITD"); break; 1407 case EHCI_LINK_QH: printf("QH"); break; 1408 case EHCI_LINK_SITD: printf("SITD"); break; 1409 case EHCI_LINK_FSTN: printf("FSTN"); break; 1410 } 1411 } 1412 printf(">"); 1413 } 1414 } 1415 1416 void 1417 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1418 { 1419 int i; 1420 u_int32_t stop; 1421 1422 stop = 0; 1423 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1424 ehci_dump_sqtd(sqtd); 1425 usb_syncmem(&sqtd->dma, 1426 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1427 sizeof(sqtd->qtd), 1428 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1429 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1430 usb_syncmem(&sqtd->dma, 1431 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1432 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1433 } 1434 if (sqtd) 1435 printf("dump aborted, too many TDs\n"); 1436 } 1437 1438 void 1439 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1440 { 1441 usb_syncmem(&sqtd->dma, sqtd->offs, 1442 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1443 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1444 ehci_dump_qtd(&sqtd->qtd); 1445 usb_syncmem(&sqtd->dma, sqtd->offs, 1446 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1447 } 1448 1449 void 1450 ehci_dump_qtd(ehci_qtd_t *qtd) 1451 { 1452 u_int32_t s; 1453 char sbuf[128]; 1454 1455 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1456 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1457 printf("\n"); 1458 s = le32toh(qtd->qtd_status); 1459 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1460 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1461 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1462 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1463 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1464 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1465 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1466 EHCI_QTD_GET_PID(s), sbuf); 1467 for (s = 0; s < 5; s++) 1468 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1469 } 1470 1471 void 1472 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1473 { 1474 ehci_qh_t *qh = &sqh->qh; 1475 u_int32_t endp, endphub; 1476 1477 usb_syncmem(&sqh->dma, sqh->offs, 1478 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1479 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1480 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1481 endp = le32toh(qh->qh_endp); 1482 printf(" endp=0x%08x\n", endp); 1483 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1484 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1485 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1486 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1487 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1488 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1489 EHCI_QH_GET_NRL(endp)); 1490 endphub = le32toh(qh->qh_endphub); 1491 printf(" endphub=0x%08x\n", endphub); 1492 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1493 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1494 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1495 EHCI_QH_GET_MULT(endphub)); 1496 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1497 printf("Overlay qTD:\n"); 1498 ehci_dump_qtd(&qh->qh_qtd); 1499 usb_syncmem(&sqh->dma, sqh->offs, 1500 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1501 } 1502 1503 #if notyet 1504 void 1505 ehci_dump_itd(struct ehci_soft_itd *itd) 1506 { 1507 ehci_isoc_trans_t t; 1508 ehci_isoc_bufr_ptr_t b, b2, b3; 1509 int i; 1510 1511 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1512 1513 for (i = 0; i < 8;i++) { 1514 t = le32toh(itd->itd.itd_ctl[i]); 1515 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1516 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1517 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1518 EHCI_ITD_GET_OFFS(t)); 1519 } 1520 printf("ITDbufr: "); 1521 for (i = 0; i < 7; i++) 1522 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1523 1524 b = le32toh(itd->itd.itd_bufr[0]); 1525 b2 = le32toh(itd->itd.itd_bufr[1]); 1526 b3 = le32toh(itd->itd.itd_bufr[2]); 1527 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1528 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1529 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1530 } 1531 1532 void 1533 ehci_dump_sitd(struct ehci_soft_itd *itd) 1534 { 1535 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1536 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1537 itd->xfer_next, itd->physaddr, itd->slot); 1538 } 1539 #endif 1540 1541 #ifdef DIAGNOSTIC 1542 void 1543 ehci_dump_exfer(struct ehci_xfer *ex) 1544 { 1545 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1546 } 1547 #endif 1548 1549 #endif 1550 1551 usbd_status 1552 ehci_open(usbd_pipe_handle pipe) 1553 { 1554 usbd_device_handle dev = pipe->device; 1555 ehci_softc_t *sc = dev->bus->hci_private; 1556 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1557 u_int8_t addr = dev->address; 1558 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1559 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1560 ehci_soft_qh_t *sqh; 1561 usbd_status err; 1562 int s; 1563 int ival, speed, naks; 1564 int hshubaddr, hshubport; 1565 1566 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1567 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1568 1569 if (dev->myhsport) { 1570 hshubaddr = dev->myhsport->parent->address; 1571 hshubport = dev->myhsport->portno; 1572 } else { 1573 hshubaddr = 0; 1574 hshubport = 0; 1575 } 1576 1577 if (sc->sc_dying) 1578 return (USBD_IOERROR); 1579 1580 epipe->nexttoggle = 0; 1581 1582 if (addr == sc->sc_addr) { 1583 switch (ed->bEndpointAddress) { 1584 case USB_CONTROL_ENDPOINT: 1585 pipe->methods = &ehci_root_ctrl_methods; 1586 break; 1587 case UE_DIR_IN | EHCI_INTR_ENDPT: 1588 pipe->methods = &ehci_root_intr_methods; 1589 break; 1590 default: 1591 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1592 ed->bEndpointAddress)); 1593 return (USBD_INVAL); 1594 } 1595 return (USBD_NORMAL_COMPLETION); 1596 } 1597 1598 /* XXX All this stuff is only valid for async. */ 1599 switch (dev->speed) { 1600 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1601 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1602 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1603 default: panic("ehci_open: bad device speed %d", dev->speed); 1604 } 1605 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1606 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1607 "isoc endpoint.\n"); 1608 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1609 "attached to a USB2 hub, and transaction translations are " 1610 "not yet supported.\n"); 1611 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1612 "root hub instead.\n"); 1613 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1614 hshubaddr, hshubport)); 1615 return USBD_INVAL; 1616 } 1617 1618 naks = 8; /* XXX */ 1619 1620 /* Allocate sqh for everything, save isoc xfers */ 1621 if (xfertype != UE_ISOCHRONOUS) { 1622 sqh = ehci_alloc_sqh(sc); 1623 if (sqh == NULL) 1624 return (USBD_NOMEM); 1625 /* qh_link filled when the QH is added */ 1626 sqh->qh.qh_endp = htole32( 1627 EHCI_QH_SET_ADDR(addr) | 1628 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1629 EHCI_QH_SET_EPS(speed) | 1630 EHCI_QH_DTC | 1631 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1632 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1633 EHCI_QH_CTL : 0) | 1634 EHCI_QH_SET_NRL(naks) 1635 ); 1636 sqh->qh.qh_endphub = htole32( 1637 EHCI_QH_SET_MULT(1) | 1638 EHCI_QH_SET_HUBA(hshubaddr) | 1639 EHCI_QH_SET_PORT(hshubport) | 1640 EHCI_QH_SET_CMASK(0x08) | /* XXX */ 1641 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1642 ); 1643 sqh->qh.qh_curqtd = EHCI_NULL; 1644 /* Fill the overlay qTD */ 1645 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1646 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1647 sqh->qh.qh_qtd.qtd_status = htole32(0); 1648 1649 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1650 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1651 epipe->sqh = sqh; 1652 } else { 1653 sqh = NULL; 1654 } /*xfertype == UE_ISOC*/ 1655 1656 switch (xfertype) { 1657 case UE_CONTROL: 1658 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1659 0, &epipe->u.ctl.reqdma); 1660 #ifdef EHCI_DEBUG 1661 if (err) 1662 printf("ehci_open: usb_allocmem()=%d\n", err); 1663 #endif 1664 if (err) 1665 goto bad; 1666 pipe->methods = &ehci_device_ctrl_methods; 1667 s = splusb(); 1668 ehci_add_qh(sqh, sc->sc_async_head); 1669 splx(s); 1670 break; 1671 case UE_BULK: 1672 pipe->methods = &ehci_device_bulk_methods; 1673 s = splusb(); 1674 ehci_add_qh(sqh, sc->sc_async_head); 1675 splx(s); 1676 break; 1677 case UE_INTERRUPT: 1678 pipe->methods = &ehci_device_intr_methods; 1679 ival = pipe->interval; 1680 if (ival == USBD_DEFAULT_INTERVAL) { 1681 if (speed == EHCI_QH_SPEED_HIGH) { 1682 if (ed->bInterval > 16) { 1683 /* 1684 * illegal with high-speed, but there 1685 * were documentation bugs in the spec, 1686 * so be generous 1687 */ 1688 ival = 256; 1689 } else 1690 ival = (1 << (ed->bInterval - 1)) / 8; 1691 } else 1692 ival = ed->bInterval; 1693 } 1694 err = ehci_device_setintr(sc, sqh, ival); 1695 if (err) 1696 goto bad; 1697 break; 1698 case UE_ISOCHRONOUS: 1699 pipe->methods = &ehci_device_isoc_methods; 1700 if (ed->bInterval == 0 || ed->bInterval > 16) { 1701 printf("ehci: opening pipe with invalid bInterval\n"); 1702 err = USBD_INVAL; 1703 goto bad; 1704 } 1705 if (UGETW(ed->wMaxPacketSize) == 0) { 1706 printf("ehci: zero length endpoint open request\n"); 1707 err = USBD_INVAL; 1708 goto bad; 1709 } 1710 epipe->u.isoc.next_frame = 0; 1711 epipe->u.isoc.cur_xfers = 0; 1712 break; 1713 default: 1714 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1715 err = USBD_INVAL; 1716 goto bad; 1717 } 1718 return (USBD_NORMAL_COMPLETION); 1719 1720 bad: 1721 if (sqh != NULL) 1722 ehci_free_sqh(sc, sqh); 1723 return (err); 1724 } 1725 1726 /* 1727 * Add an ED to the schedule. Called at splusb(). 1728 */ 1729 void 1730 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1731 { 1732 SPLUSBCHECK; 1733 1734 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1735 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1736 sqh->next = head->next; 1737 sqh->qh.qh_link = head->qh.qh_link; 1738 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1739 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1740 head->next = sqh; 1741 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1742 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1743 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1744 1745 #ifdef EHCI_DEBUG 1746 if (ehcidebug > 5) { 1747 printf("ehci_add_qh:\n"); 1748 ehci_dump_sqh(sqh); 1749 } 1750 #endif 1751 } 1752 1753 /* 1754 * Remove an ED from the schedule. Called at splusb(). 1755 */ 1756 void 1757 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1758 { 1759 ehci_soft_qh_t *p; 1760 1761 SPLUSBCHECK; 1762 /* XXX */ 1763 for (p = head; p != NULL && p->next != sqh; p = p->next) 1764 ; 1765 if (p == NULL) 1766 panic("ehci_rem_qh: ED not found"); 1767 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1768 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1769 p->next = sqh->next; 1770 p->qh.qh_link = sqh->qh.qh_link; 1771 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1772 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1773 1774 ehci_sync_hc(sc); 1775 } 1776 1777 void 1778 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1779 { 1780 int i; 1781 u_int32_t status; 1782 1783 /* Save toggle bit and ping status. */ 1784 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1785 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1786 status = sqh->qh.qh_qtd.qtd_status & 1787 htole32(EHCI_QTD_TOGGLE_MASK | 1788 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1789 /* Set HALTED to make hw leave it alone. */ 1790 sqh->qh.qh_qtd.qtd_status = 1791 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1792 usb_syncmem(&sqh->dma, 1793 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1794 sizeof(sqh->qh.qh_qtd.qtd_status), 1795 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1796 sqh->qh.qh_curqtd = 0; 1797 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1798 sqh->qh.qh_qtd.qtd_altnext = 0; 1799 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1800 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1801 sqh->sqtd = sqtd; 1802 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1803 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1804 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1805 sqh->qh.qh_qtd.qtd_status = status; 1806 usb_syncmem(&sqh->dma, 1807 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1808 sizeof(sqh->qh.qh_qtd.qtd_status), 1809 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1810 } 1811 1812 /* 1813 * Ensure that the HC has released all references to the QH. We do this 1814 * by asking for a Async Advance Doorbell interrupt and then we wait for 1815 * the interrupt. 1816 * To make this easier we first obtain exclusive use of the doorbell. 1817 */ 1818 void 1819 ehci_sync_hc(ehci_softc_t *sc) 1820 { 1821 int s, error; 1822 1823 if (sc->sc_dying) { 1824 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1825 return; 1826 } 1827 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1828 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */ 1829 s = splhardusb(); 1830 /* ask for doorbell */ 1831 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1832 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1833 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1834 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1835 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1836 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1837 splx(s); 1838 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */ 1839 #ifdef DIAGNOSTIC 1840 if (error) 1841 printf("ehci_sync_hc: tsleep() = %d\n", error); 1842 #endif 1843 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1844 } 1845 1846 /*Call at splusb*/ 1847 void 1848 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1849 { 1850 struct ehci_soft_itd *itd, *prev; 1851 1852 prev = NULL; 1853 1854 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1855 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1856 1857 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1858 prev = itd->u.frame_list.prev; 1859 /* Unlink itd from hardware chain, or frame array */ 1860 if (prev == NULL) { /* We're at the table head */ 1861 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1862 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1863 usb_syncmem(&sc->sc_fldma, 1864 sizeof(ehci_link_t) * itd->slot, 1865 sizeof(ehci_link_t), 1866 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1867 1868 if (itd->u.frame_list.next != NULL) 1869 itd->u.frame_list.next->u.frame_list.prev = NULL; 1870 } else { 1871 /* XXX this part is untested... */ 1872 prev->itd.itd_next = itd->itd.itd_next; 1873 usb_syncmem(&itd->dma, 1874 itd->offs + offsetof(ehci_itd_t, itd_next), 1875 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1876 1877 prev->u.frame_list.next = itd->u.frame_list.next; 1878 if (itd->u.frame_list.next != NULL) 1879 itd->u.frame_list.next->u.frame_list.prev = prev; 1880 } 1881 } 1882 1883 prev = NULL; 1884 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1885 if (prev != NULL) 1886 ehci_free_itd(sc, prev); 1887 prev = itd; 1888 } 1889 if (prev) 1890 ehci_free_itd(sc, prev); 1891 exfer->itdstart = NULL; 1892 exfer->itdend = NULL; 1893 } 1894 1895 /***********/ 1896 1897 /* 1898 * Data structures and routines to emulate the root hub. 1899 */ 1900 Static usb_device_descriptor_t ehci_devd = { 1901 USB_DEVICE_DESCRIPTOR_SIZE, 1902 UDESC_DEVICE, /* type */ 1903 {0x00, 0x02}, /* USB version */ 1904 UDCLASS_HUB, /* class */ 1905 UDSUBCLASS_HUB, /* subclass */ 1906 UDPROTO_HSHUBSTT, /* protocol */ 1907 64, /* max packet */ 1908 {0},{0},{0x00,0x01}, /* device id */ 1909 1,2,0, /* string indicies */ 1910 1 /* # of configurations */ 1911 }; 1912 1913 Static const usb_device_qualifier_t ehci_odevd = { 1914 USB_DEVICE_DESCRIPTOR_SIZE, 1915 UDESC_DEVICE_QUALIFIER, /* type */ 1916 {0x00, 0x02}, /* USB version */ 1917 UDCLASS_HUB, /* class */ 1918 UDSUBCLASS_HUB, /* subclass */ 1919 UDPROTO_FSHUB, /* protocol */ 1920 64, /* max packet */ 1921 1, /* # of configurations */ 1922 0 1923 }; 1924 1925 Static const usb_config_descriptor_t ehci_confd = { 1926 USB_CONFIG_DESCRIPTOR_SIZE, 1927 UDESC_CONFIG, 1928 {USB_CONFIG_DESCRIPTOR_SIZE + 1929 USB_INTERFACE_DESCRIPTOR_SIZE + 1930 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1931 1, 1932 1, 1933 0, 1934 UC_ATTR_MBO | UC_SELF_POWERED, 1935 0 /* max power */ 1936 }; 1937 1938 Static const usb_interface_descriptor_t ehci_ifcd = { 1939 USB_INTERFACE_DESCRIPTOR_SIZE, 1940 UDESC_INTERFACE, 1941 0, 1942 0, 1943 1, 1944 UICLASS_HUB, 1945 UISUBCLASS_HUB, 1946 UIPROTO_HSHUBSTT, 1947 0 1948 }; 1949 1950 Static const usb_endpoint_descriptor_t ehci_endpd = { 1951 USB_ENDPOINT_DESCRIPTOR_SIZE, 1952 UDESC_ENDPOINT, 1953 UE_DIR_IN | EHCI_INTR_ENDPT, 1954 UE_INTERRUPT, 1955 {8, 0}, /* max packet */ 1956 12 1957 }; 1958 1959 Static const usb_hub_descriptor_t ehci_hubd = { 1960 USB_HUB_DESCRIPTOR_SIZE, 1961 UDESC_HUB, 1962 0, 1963 {0,0}, 1964 0, 1965 0, 1966 {""}, 1967 {""}, 1968 }; 1969 1970 /* 1971 * Simulate a hardware hub by handling all the necessary requests. 1972 */ 1973 Static usbd_status 1974 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1975 { 1976 usbd_status err; 1977 1978 /* Insert last in queue. */ 1979 err = usb_insert_transfer(xfer); 1980 if (err) 1981 return (err); 1982 1983 /* Pipe isn't running, start first */ 1984 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1985 } 1986 1987 Static usbd_status 1988 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1989 { 1990 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1991 usb_device_request_t *req; 1992 void *buf = NULL; 1993 int port, i; 1994 int s, len, value, index, l, totlen = 0; 1995 usb_port_status_t ps; 1996 usb_hub_descriptor_t hubd; 1997 usbd_status err; 1998 u_int32_t v; 1999 2000 if (sc->sc_dying) 2001 return (USBD_IOERROR); 2002 2003 #ifdef DIAGNOSTIC 2004 if (!(xfer->rqflags & URQ_REQUEST)) 2005 /* XXX panic */ 2006 return (USBD_INVAL); 2007 #endif 2008 req = &xfer->request; 2009 2010 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2011 req->bmRequestType, req->bRequest)); 2012 2013 len = UGETW(req->wLength); 2014 value = UGETW(req->wValue); 2015 index = UGETW(req->wIndex); 2016 2017 if (len != 0) 2018 buf = KERNADDR(&xfer->dmabuf, 0); 2019 2020 #define C(x,y) ((x) | ((y) << 8)) 2021 switch(C(req->bRequest, req->bmRequestType)) { 2022 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2023 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2024 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2025 /* 2026 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2027 * for the integrated root hub. 2028 */ 2029 break; 2030 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2031 if (len > 0) { 2032 *(u_int8_t *)buf = sc->sc_conf; 2033 totlen = 1; 2034 } 2035 break; 2036 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2037 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2038 if (len == 0) 2039 break; 2040 switch(value >> 8) { 2041 case UDESC_DEVICE: 2042 if ((value & 0xff) != 0) { 2043 err = USBD_IOERROR; 2044 goto ret; 2045 } 2046 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2047 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2048 memcpy(buf, &ehci_devd, l); 2049 break; 2050 /* 2051 * We can't really operate at another speed, but the spec says 2052 * we need this descriptor. 2053 */ 2054 case UDESC_DEVICE_QUALIFIER: 2055 if ((value & 0xff) != 0) { 2056 err = USBD_IOERROR; 2057 goto ret; 2058 } 2059 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2060 memcpy(buf, &ehci_odevd, l); 2061 break; 2062 /* 2063 * We can't really operate at another speed, but the spec says 2064 * we need this descriptor. 2065 */ 2066 case UDESC_OTHER_SPEED_CONFIGURATION: 2067 case UDESC_CONFIG: 2068 if ((value & 0xff) != 0) { 2069 err = USBD_IOERROR; 2070 goto ret; 2071 } 2072 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2073 memcpy(buf, &ehci_confd, l); 2074 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2075 value >> 8; 2076 buf = (char *)buf + l; 2077 len -= l; 2078 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2079 totlen += l; 2080 memcpy(buf, &ehci_ifcd, l); 2081 buf = (char *)buf + l; 2082 len -= l; 2083 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2084 totlen += l; 2085 memcpy(buf, &ehci_endpd, l); 2086 break; 2087 case UDESC_STRING: 2088 #define sd ((usb_string_descriptor_t *)buf) 2089 switch (value & 0xff) { 2090 case 0: /* Language table */ 2091 totlen = usb_makelangtbl(sd, len); 2092 break; 2093 case 1: /* Vendor */ 2094 totlen = usb_makestrdesc(sd, len, 2095 sc->sc_vendor); 2096 break; 2097 case 2: /* Product */ 2098 totlen = usb_makestrdesc(sd, len, 2099 "EHCI root hub"); 2100 break; 2101 } 2102 #undef sd 2103 break; 2104 default: 2105 err = USBD_IOERROR; 2106 goto ret; 2107 } 2108 break; 2109 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2110 if (len > 0) { 2111 *(u_int8_t *)buf = 0; 2112 totlen = 1; 2113 } 2114 break; 2115 case C(UR_GET_STATUS, UT_READ_DEVICE): 2116 if (len > 1) { 2117 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2118 totlen = 2; 2119 } 2120 break; 2121 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2122 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2123 if (len > 1) { 2124 USETW(((usb_status_t *)buf)->wStatus, 0); 2125 totlen = 2; 2126 } 2127 break; 2128 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2129 if (value >= USB_MAX_DEVICES) { 2130 err = USBD_IOERROR; 2131 goto ret; 2132 } 2133 sc->sc_addr = value; 2134 break; 2135 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2136 if (value != 0 && value != 1) { 2137 err = USBD_IOERROR; 2138 goto ret; 2139 } 2140 sc->sc_conf = value; 2141 break; 2142 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2143 break; 2144 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2145 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2146 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2147 err = USBD_IOERROR; 2148 goto ret; 2149 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2150 break; 2151 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2152 break; 2153 /* Hub requests */ 2154 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2155 break; 2156 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2157 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2158 "port=%d feature=%d\n", 2159 index, value)); 2160 if (index < 1 || index > sc->sc_noport) { 2161 err = USBD_IOERROR; 2162 goto ret; 2163 } 2164 port = EHCI_PORTSC(index); 2165 v = EOREAD4(sc, port); 2166 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2167 v &= ~EHCI_PS_CLEAR; 2168 switch(value) { 2169 case UHF_PORT_ENABLE: 2170 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2171 break; 2172 case UHF_PORT_SUSPEND: 2173 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2174 break; 2175 v &= ~EHCI_PS_SUSP; 2176 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2177 /* see USB2 spec ch. 7.1.7.7 */ 2178 usb_delay_ms(&sc->sc_bus, 20); 2179 EOWRITE4(sc, port, v); 2180 usb_delay_ms(&sc->sc_bus, 2); 2181 #ifdef DEBUG 2182 v = EOREAD4(sc, port); 2183 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2184 printf("ehci: resume failed: %x\n", v); 2185 #endif 2186 break; 2187 case UHF_PORT_POWER: 2188 if (sc->sc_hasppc) 2189 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2190 break; 2191 case UHF_PORT_TEST: 2192 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2193 "%d\n", index)); 2194 break; 2195 case UHF_PORT_INDICATOR: 2196 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2197 "%d\n", index)); 2198 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2199 break; 2200 case UHF_C_PORT_CONNECTION: 2201 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2202 break; 2203 case UHF_C_PORT_ENABLE: 2204 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2205 break; 2206 case UHF_C_PORT_SUSPEND: 2207 /* how? */ 2208 break; 2209 case UHF_C_PORT_OVER_CURRENT: 2210 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2211 break; 2212 case UHF_C_PORT_RESET: 2213 sc->sc_isreset[index] = 0; 2214 break; 2215 default: 2216 err = USBD_IOERROR; 2217 goto ret; 2218 } 2219 #if 0 2220 switch(value) { 2221 case UHF_C_PORT_CONNECTION: 2222 case UHF_C_PORT_ENABLE: 2223 case UHF_C_PORT_SUSPEND: 2224 case UHF_C_PORT_OVER_CURRENT: 2225 case UHF_C_PORT_RESET: 2226 default: 2227 break; 2228 } 2229 #endif 2230 break; 2231 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2232 if (len == 0) 2233 break; 2234 if ((value & 0xff) != 0) { 2235 err = USBD_IOERROR; 2236 goto ret; 2237 } 2238 hubd = ehci_hubd; 2239 hubd.bNbrPorts = sc->sc_noport; 2240 v = EOREAD4(sc, EHCI_HCSPARAMS); 2241 USETW(hubd.wHubCharacteristics, 2242 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2243 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2244 ? UHD_PORT_IND : 0); 2245 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2246 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2247 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2248 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2249 l = min(len, hubd.bDescLength); 2250 totlen = l; 2251 memcpy(buf, &hubd, l); 2252 break; 2253 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2254 if (len != 4) { 2255 err = USBD_IOERROR; 2256 goto ret; 2257 } 2258 memset(buf, 0, len); /* ? XXX */ 2259 totlen = len; 2260 break; 2261 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2262 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2263 index)); 2264 if (index < 1 || index > sc->sc_noport) { 2265 err = USBD_IOERROR; 2266 goto ret; 2267 } 2268 if (len != 4) { 2269 err = USBD_IOERROR; 2270 goto ret; 2271 } 2272 v = EOREAD4(sc, EHCI_PORTSC(index)); 2273 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2274 v)); 2275 i = UPS_HIGH_SPEED; 2276 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2277 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2278 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2279 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2280 if (v & EHCI_PS_PR) i |= UPS_RESET; 2281 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2282 USETW(ps.wPortStatus, i); 2283 i = 0; 2284 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2285 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2286 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2287 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2288 USETW(ps.wPortChange, i); 2289 l = min(len, sizeof ps); 2290 memcpy(buf, &ps, l); 2291 totlen = l; 2292 break; 2293 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2294 err = USBD_IOERROR; 2295 goto ret; 2296 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2297 break; 2298 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2299 if (index < 1 || index > sc->sc_noport) { 2300 err = USBD_IOERROR; 2301 goto ret; 2302 } 2303 port = EHCI_PORTSC(index); 2304 v = EOREAD4(sc, port); 2305 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2306 v &= ~EHCI_PS_CLEAR; 2307 switch(value) { 2308 case UHF_PORT_ENABLE: 2309 EOWRITE4(sc, port, v | EHCI_PS_PE); 2310 break; 2311 case UHF_PORT_SUSPEND: 2312 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2313 break; 2314 case UHF_PORT_RESET: 2315 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2316 index)); 2317 if (EHCI_PS_IS_LOWSPEED(v)) { 2318 /* Low speed device, give up ownership. */ 2319 ehci_disown(sc, index, 1); 2320 break; 2321 } 2322 /* Start reset sequence. */ 2323 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2324 EOWRITE4(sc, port, v | EHCI_PS_PR); 2325 /* Wait for reset to complete. */ 2326 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2327 if (sc->sc_dying) { 2328 err = USBD_IOERROR; 2329 goto ret; 2330 } 2331 /* Terminate reset sequence. */ 2332 EOWRITE4(sc, port, v); 2333 /* Wait for HC to complete reset. */ 2334 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2335 if (sc->sc_dying) { 2336 err = USBD_IOERROR; 2337 goto ret; 2338 } 2339 v = EOREAD4(sc, port); 2340 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2341 if (v & EHCI_PS_PR) { 2342 printf("%s: port reset timeout\n", 2343 device_xname(sc->sc_dev)); 2344 return (USBD_TIMEOUT); 2345 } 2346 if (!(v & EHCI_PS_PE)) { 2347 /* Not a high speed device, give up ownership.*/ 2348 ehci_disown(sc, index, 0); 2349 break; 2350 } 2351 sc->sc_isreset[index] = 1; 2352 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2353 index, v)); 2354 break; 2355 case UHF_PORT_POWER: 2356 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2357 "%d (has PPC = %d)\n", index, 2358 sc->sc_hasppc)); 2359 if (sc->sc_hasppc) 2360 EOWRITE4(sc, port, v | EHCI_PS_PP); 2361 break; 2362 case UHF_PORT_TEST: 2363 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2364 "%d\n", index)); 2365 break; 2366 case UHF_PORT_INDICATOR: 2367 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2368 "%d\n", index)); 2369 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2370 break; 2371 default: 2372 err = USBD_IOERROR; 2373 goto ret; 2374 } 2375 break; 2376 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2377 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2378 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2379 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2380 break; 2381 default: 2382 err = USBD_IOERROR; 2383 goto ret; 2384 } 2385 xfer->actlen = totlen; 2386 err = USBD_NORMAL_COMPLETION; 2387 ret: 2388 xfer->status = err; 2389 s = splusb(); 2390 usb_transfer_complete(xfer); 2391 splx(s); 2392 return (USBD_IN_PROGRESS); 2393 } 2394 2395 void 2396 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2397 { 2398 int port; 2399 u_int32_t v; 2400 2401 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2402 #ifdef DIAGNOSTIC 2403 if (sc->sc_npcomp != 0) { 2404 int i = (index-1) / sc->sc_npcomp; 2405 if (i >= sc->sc_ncomp) 2406 printf("%s: strange port\n", 2407 device_xname(sc->sc_dev)); 2408 else 2409 printf("%s: handing over %s speed device on " 2410 "port %d to %s\n", 2411 device_xname(sc->sc_dev), 2412 lowspeed ? "low" : "full", 2413 index, device_xname(sc->sc_comps[i])); 2414 } else { 2415 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2416 } 2417 #endif 2418 port = EHCI_PORTSC(index); 2419 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2420 EOWRITE4(sc, port, v | EHCI_PS_PO); 2421 } 2422 2423 /* Abort a root control request. */ 2424 Static void 2425 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2426 { 2427 /* Nothing to do, all transfers are synchronous. */ 2428 } 2429 2430 /* Close the root pipe. */ 2431 Static void 2432 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2433 { 2434 DPRINTF(("ehci_root_ctrl_close\n")); 2435 /* Nothing to do. */ 2436 } 2437 2438 void 2439 ehci_root_intr_done(usbd_xfer_handle xfer) 2440 { 2441 xfer->hcpriv = NULL; 2442 } 2443 2444 Static usbd_status 2445 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2446 { 2447 usbd_status err; 2448 2449 /* Insert last in queue. */ 2450 err = usb_insert_transfer(xfer); 2451 if (err) 2452 return (err); 2453 2454 /* Pipe isn't running, start first */ 2455 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2456 } 2457 2458 Static usbd_status 2459 ehci_root_intr_start(usbd_xfer_handle xfer) 2460 { 2461 usbd_pipe_handle pipe = xfer->pipe; 2462 ehci_softc_t *sc = pipe->device->bus->hci_private; 2463 2464 if (sc->sc_dying) 2465 return (USBD_IOERROR); 2466 2467 sc->sc_intrxfer = xfer; 2468 2469 return (USBD_IN_PROGRESS); 2470 } 2471 2472 /* Abort a root interrupt request. */ 2473 Static void 2474 ehci_root_intr_abort(usbd_xfer_handle xfer) 2475 { 2476 int s; 2477 2478 if (xfer->pipe->intrxfer == xfer) { 2479 DPRINTF(("ehci_root_intr_abort: remove\n")); 2480 xfer->pipe->intrxfer = NULL; 2481 } 2482 xfer->status = USBD_CANCELLED; 2483 s = splusb(); 2484 usb_transfer_complete(xfer); 2485 splx(s); 2486 } 2487 2488 /* Close the root pipe. */ 2489 Static void 2490 ehci_root_intr_close(usbd_pipe_handle pipe) 2491 { 2492 ehci_softc_t *sc = pipe->device->bus->hci_private; 2493 2494 DPRINTF(("ehci_root_intr_close\n")); 2495 2496 sc->sc_intrxfer = NULL; 2497 } 2498 2499 void 2500 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2501 { 2502 xfer->hcpriv = NULL; 2503 } 2504 2505 /************************/ 2506 2507 ehci_soft_qh_t * 2508 ehci_alloc_sqh(ehci_softc_t *sc) 2509 { 2510 ehci_soft_qh_t *sqh; 2511 usbd_status err; 2512 int i, offs; 2513 usb_dma_t dma; 2514 2515 if (sc->sc_freeqhs == NULL) { 2516 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2517 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2518 EHCI_PAGE_SIZE, &dma); 2519 #ifdef EHCI_DEBUG 2520 if (err) 2521 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2522 #endif 2523 if (err) 2524 return (NULL); 2525 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2526 offs = i * EHCI_SQH_SIZE; 2527 sqh = KERNADDR(&dma, offs); 2528 sqh->physaddr = DMAADDR(&dma, offs); 2529 sqh->dma = dma; 2530 sqh->offs = offs; 2531 sqh->next = sc->sc_freeqhs; 2532 sc->sc_freeqhs = sqh; 2533 } 2534 } 2535 sqh = sc->sc_freeqhs; 2536 sc->sc_freeqhs = sqh->next; 2537 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2538 sqh->next = NULL; 2539 return (sqh); 2540 } 2541 2542 void 2543 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2544 { 2545 sqh->next = sc->sc_freeqhs; 2546 sc->sc_freeqhs = sqh; 2547 } 2548 2549 ehci_soft_qtd_t * 2550 ehci_alloc_sqtd(ehci_softc_t *sc) 2551 { 2552 ehci_soft_qtd_t *sqtd; 2553 usbd_status err; 2554 int i, offs; 2555 usb_dma_t dma; 2556 int s; 2557 2558 if (sc->sc_freeqtds == NULL) { 2559 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2560 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2561 EHCI_PAGE_SIZE, &dma); 2562 #ifdef EHCI_DEBUG 2563 if (err) 2564 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2565 #endif 2566 if (err) 2567 return (NULL); 2568 s = splusb(); 2569 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2570 offs = i * EHCI_SQTD_SIZE; 2571 sqtd = KERNADDR(&dma, offs); 2572 sqtd->physaddr = DMAADDR(&dma, offs); 2573 sqtd->dma = dma; 2574 sqtd->offs = offs; 2575 sqtd->nextqtd = sc->sc_freeqtds; 2576 sc->sc_freeqtds = sqtd; 2577 } 2578 splx(s); 2579 } 2580 2581 s = splusb(); 2582 sqtd = sc->sc_freeqtds; 2583 sc->sc_freeqtds = sqtd->nextqtd; 2584 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2585 sqtd->nextqtd = NULL; 2586 sqtd->xfer = NULL; 2587 splx(s); 2588 2589 return (sqtd); 2590 } 2591 2592 void 2593 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2594 { 2595 int s; 2596 2597 s = splusb(); 2598 sqtd->nextqtd = sc->sc_freeqtds; 2599 sc->sc_freeqtds = sqtd; 2600 splx(s); 2601 } 2602 2603 usbd_status 2604 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2605 int alen, int rd, usbd_xfer_handle xfer, 2606 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2607 { 2608 ehci_soft_qtd_t *next, *cur; 2609 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2610 u_int32_t qtdstatus; 2611 int len, curlen, mps; 2612 int i, tog; 2613 usb_dma_t *dma = &xfer->dmabuf; 2614 u_int16_t flags = xfer->flags; 2615 2616 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2617 2618 len = alen; 2619 dataphys = DMAADDR(dma, 0); 2620 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2621 qtdstatus = EHCI_QTD_ACTIVE | 2622 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2623 EHCI_QTD_SET_CERR(3) 2624 /* IOC set below */ 2625 /* BYTES set below */ 2626 ; 2627 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2628 tog = epipe->nexttoggle; 2629 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2630 2631 cur = ehci_alloc_sqtd(sc); 2632 *sp = cur; 2633 if (cur == NULL) 2634 goto nomem; 2635 2636 usb_syncmem(dma, 0, alen, 2637 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2638 for (;;) { 2639 dataphyspage = EHCI_PAGE(dataphys); 2640 /* The EHCI hardware can handle at most 5 pages. */ 2641 if (dataphyslastpage - dataphyspage < 2642 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2643 /* we can handle it in this QTD */ 2644 curlen = len; 2645 } else { 2646 /* must use multiple TDs, fill as much as possible. */ 2647 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2648 EHCI_PAGE_OFFSET(dataphys); 2649 #ifdef DIAGNOSTIC 2650 if (curlen > len) { 2651 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2652 "len=0x%x offs=0x%x\n", curlen, len, 2653 EHCI_PAGE_OFFSET(dataphys)); 2654 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2655 dataphyslastpage, dataphyspage, 2656 dataphys); 2657 curlen = len; 2658 } 2659 #endif 2660 /* the length must be a multiple of the max size */ 2661 curlen -= curlen % mps; 2662 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2663 "curlen=%d\n", curlen)); 2664 #ifdef DIAGNOSTIC 2665 if (curlen == 0) 2666 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2667 #endif 2668 } 2669 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2670 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2671 dataphys, dataphyslastpage, 2672 len, curlen)); 2673 len -= curlen; 2674 2675 /* 2676 * Allocate another transfer if there's more data left, 2677 * or if force last short transfer flag is set and we're 2678 * allocating a multiple of the max packet size. 2679 */ 2680 if (len != 0 || 2681 ((curlen % mps) == 0 && !rd && curlen != 0 && 2682 (flags & USBD_FORCE_SHORT_XFER))) { 2683 next = ehci_alloc_sqtd(sc); 2684 if (next == NULL) 2685 goto nomem; 2686 nextphys = htole32(next->physaddr); 2687 } else { 2688 next = NULL; 2689 nextphys = EHCI_NULL; 2690 } 2691 2692 for (i = 0; i * EHCI_PAGE_SIZE < 2693 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2694 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2695 if (i != 0) /* use offset only in first buffer */ 2696 a = EHCI_PAGE(a); 2697 cur->qtd.qtd_buffer[i] = htole32(a); 2698 cur->qtd.qtd_buffer_hi[i] = 0; 2699 #ifdef DIAGNOSTIC 2700 if (i >= EHCI_QTD_NBUFFERS) { 2701 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2702 goto nomem; 2703 } 2704 #endif 2705 } 2706 cur->nextqtd = next; 2707 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2708 cur->qtd.qtd_status = 2709 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2710 cur->xfer = xfer; 2711 cur->len = curlen; 2712 2713 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2714 dataphys, dataphys + curlen)); 2715 /* adjust the toggle based on the number of packets in this 2716 qtd */ 2717 if (((curlen + mps - 1) / mps) & 1) { 2718 tog ^= 1; 2719 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2720 } 2721 if (next == NULL) 2722 break; 2723 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2724 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2725 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2726 dataphys += curlen; 2727 cur = next; 2728 } 2729 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2730 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2731 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2732 *ep = cur; 2733 epipe->nexttoggle = tog; 2734 2735 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2736 *sp, *ep)); 2737 2738 return (USBD_NORMAL_COMPLETION); 2739 2740 nomem: 2741 /* XXX free chain */ 2742 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2743 return (USBD_NOMEM); 2744 } 2745 2746 Static void 2747 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2748 ehci_soft_qtd_t *sqtdend) 2749 { 2750 ehci_soft_qtd_t *p; 2751 int i; 2752 2753 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2754 sqtd, sqtdend)); 2755 2756 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2757 p = sqtd->nextqtd; 2758 ehci_free_sqtd(sc, sqtd); 2759 } 2760 } 2761 2762 ehci_soft_itd_t * 2763 ehci_alloc_itd(ehci_softc_t *sc) 2764 { 2765 struct ehci_soft_itd *itd, *freeitd; 2766 usbd_status err; 2767 int i, s, offs, frindex, previndex; 2768 usb_dma_t dma; 2769 2770 s = splusb(); 2771 2772 /* Find an itd that wasn't freed this frame or last frame. This can 2773 * discard itds that were freed before frindex wrapped around 2774 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2775 * interrupt and fiddling with list when that happens */ 2776 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2777 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2778 2779 freeitd = NULL; 2780 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2781 if (itd == NULL) 2782 break; 2783 if (itd->slot != frindex && itd->slot != previndex) { 2784 freeitd = itd; 2785 break; 2786 } 2787 } 2788 2789 if (freeitd == NULL) { 2790 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2791 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2792 EHCI_PAGE_SIZE, &dma); 2793 2794 if (err) { 2795 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2796 return NULL; 2797 } 2798 2799 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2800 offs = i * EHCI_ITD_SIZE; 2801 itd = KERNADDR(&dma, offs); 2802 itd->physaddr = DMAADDR(&dma, offs); 2803 itd->dma = dma; 2804 itd->offs = offs; 2805 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2806 } 2807 freeitd = LIST_FIRST(&sc->sc_freeitds); 2808 } 2809 2810 itd = freeitd; 2811 LIST_REMOVE(itd, u.free_list); 2812 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2813 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2814 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2815 BUS_DMASYNC_PREREAD); 2816 2817 itd->u.frame_list.next = NULL; 2818 itd->u.frame_list.prev = NULL; 2819 itd->xfer_next = NULL; 2820 itd->slot = 0; 2821 splx(s); 2822 2823 return itd; 2824 } 2825 2826 void 2827 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2828 { 2829 int s; 2830 2831 s = splusb(); 2832 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2833 splx(s); 2834 } 2835 2836 2837 2838 /****************/ 2839 2840 /* 2841 * Close a reqular pipe. 2842 * Assumes that there are no pending transactions. 2843 */ 2844 void 2845 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2846 { 2847 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2848 ehci_softc_t *sc = pipe->device->bus->hci_private; 2849 ehci_soft_qh_t *sqh = epipe->sqh; 2850 int s; 2851 2852 s = splusb(); 2853 ehci_rem_qh(sc, sqh, head); 2854 splx(s); 2855 ehci_free_sqh(sc, epipe->sqh); 2856 } 2857 2858 /* 2859 * Abort a device request. 2860 * If this routine is called at splusb() it guarantees that the request 2861 * will be removed from the hardware scheduling and that the callback 2862 * for it will be called with USBD_CANCELLED status. 2863 * It's impossible to guarantee that the requested transfer will not 2864 * have happened since the hardware runs concurrently. 2865 * If the transaction has already happened we rely on the ordinary 2866 * interrupt processing to process it. 2867 * XXX This is most probably wrong. 2868 */ 2869 void 2870 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2871 { 2872 #define exfer EXFER(xfer) 2873 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2874 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2875 ehci_soft_qh_t *sqh = epipe->sqh; 2876 ehci_soft_qtd_t *sqtd; 2877 ehci_physaddr_t cur; 2878 u_int32_t qhstatus; 2879 int s; 2880 int hit; 2881 int wake; 2882 2883 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2884 2885 if (sc->sc_dying) { 2886 /* If we're dying, just do the software part. */ 2887 s = splusb(); 2888 xfer->status = status; /* make software ignore it */ 2889 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2890 usb_transfer_complete(xfer); 2891 splx(s); 2892 return; 2893 } 2894 2895 if (xfer->device->bus->intr_context) 2896 panic("ehci_abort_xfer: not in process context"); 2897 2898 /* 2899 * If an abort is already in progress then just wait for it to 2900 * complete and return. 2901 */ 2902 if (xfer->hcflags & UXFER_ABORTING) { 2903 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2904 #ifdef DIAGNOSTIC 2905 if (status == USBD_TIMEOUT) 2906 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2907 #endif 2908 /* Override the status which might be USBD_TIMEOUT. */ 2909 xfer->status = status; 2910 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2911 xfer->hcflags |= UXFER_ABORTWAIT; 2912 while (xfer->hcflags & UXFER_ABORTING) 2913 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2914 return; 2915 } 2916 xfer->hcflags |= UXFER_ABORTING; 2917 2918 /* 2919 * Step 1: Make interrupt routine and hardware ignore xfer. 2920 */ 2921 s = splusb(); 2922 xfer->status = status; /* make software ignore it */ 2923 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2924 2925 usb_syncmem(&sqh->dma, 2926 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2927 sizeof(sqh->qh.qh_qtd.qtd_status), 2928 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2929 qhstatus = sqh->qh.qh_qtd.qtd_status; 2930 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2931 usb_syncmem(&sqh->dma, 2932 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2933 sizeof(sqh->qh.qh_qtd.qtd_status), 2934 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2935 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2936 usb_syncmem(&sqtd->dma, 2937 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2938 sizeof(sqtd->qtd.qtd_status), 2939 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2940 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2941 usb_syncmem(&sqtd->dma, 2942 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2943 sizeof(sqtd->qtd.qtd_status), 2944 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2945 if (sqtd == exfer->sqtdend) 2946 break; 2947 } 2948 splx(s); 2949 2950 /* 2951 * Step 2: Wait until we know hardware has finished any possible 2952 * use of the xfer. Also make sure the soft interrupt routine 2953 * has run. 2954 */ 2955 ehci_sync_hc(sc); 2956 s = splusb(); 2957 #ifdef USB_USE_SOFTINTR 2958 sc->sc_softwake = 1; 2959 #endif /* USB_USE_SOFTINTR */ 2960 usb_schedsoftintr(&sc->sc_bus); 2961 #ifdef USB_USE_SOFTINTR 2962 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2963 #endif /* USB_USE_SOFTINTR */ 2964 splx(s); 2965 2966 /* 2967 * Step 3: Remove any vestiges of the xfer from the hardware. 2968 * The complication here is that the hardware may have executed 2969 * beyond the xfer we're trying to abort. So as we're scanning 2970 * the TDs of this xfer we check if the hardware points to 2971 * any of them. 2972 */ 2973 s = splusb(); /* XXX why? */ 2974 2975 usb_syncmem(&sqh->dma, 2976 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2977 sizeof(sqh->qh.qh_curqtd), 2978 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2979 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2980 hit = 0; 2981 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2982 hit |= cur == sqtd->physaddr; 2983 if (sqtd == exfer->sqtdend) 2984 break; 2985 } 2986 sqtd = sqtd->nextqtd; 2987 /* Zap curqtd register if hardware pointed inside the xfer. */ 2988 if (hit && sqtd != NULL) { 2989 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 2990 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 2991 usb_syncmem(&sqh->dma, 2992 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2993 sizeof(sqh->qh.qh_curqtd), 2994 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2995 sqh->qh.qh_qtd.qtd_status = qhstatus; 2996 usb_syncmem(&sqh->dma, 2997 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2998 sizeof(sqh->qh.qh_qtd.qtd_status), 2999 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3000 } else { 3001 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3002 } 3003 3004 /* 3005 * Step 4: Execute callback. 3006 */ 3007 #ifdef DIAGNOSTIC 3008 exfer->isdone = 1; 3009 #endif 3010 wake = xfer->hcflags & UXFER_ABORTWAIT; 3011 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3012 usb_transfer_complete(xfer); 3013 if (wake) 3014 wakeup(&xfer->hcflags); 3015 3016 splx(s); 3017 #undef exfer 3018 } 3019 3020 void 3021 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3022 { 3023 ehci_isoc_trans_t trans_status; 3024 struct ehci_pipe *epipe; 3025 struct ehci_xfer *exfer; 3026 ehci_softc_t *sc; 3027 struct ehci_soft_itd *itd; 3028 int s, i, wake; 3029 3030 epipe = (struct ehci_pipe *) xfer->pipe; 3031 exfer = EXFER(xfer); 3032 sc = epipe->pipe.device->bus->hci_private; 3033 3034 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3035 3036 if (sc->sc_dying) { 3037 s = splusb(); 3038 xfer->status = status; 3039 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3040 usb_transfer_complete(xfer); 3041 splx(s); 3042 return; 3043 } 3044 3045 if (xfer->hcflags & UXFER_ABORTING) { 3046 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3047 3048 #ifdef DIAGNOSTIC 3049 if (status == USBD_TIMEOUT) 3050 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3051 #endif 3052 3053 xfer->status = status; 3054 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3055 xfer->hcflags |= UXFER_ABORTWAIT; 3056 while (xfer->hcflags & UXFER_ABORTING) 3057 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0); 3058 return; 3059 } 3060 xfer->hcflags |= UXFER_ABORTING; 3061 3062 xfer->status = status; 3063 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3064 3065 s = splusb(); 3066 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3067 usb_syncmem(&itd->dma, 3068 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3069 sizeof(itd->itd.itd_ctl), 3070 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3071 3072 for (i = 0; i < 8; i++) { 3073 trans_status = le32toh(itd->itd.itd_ctl[i]); 3074 trans_status &= ~EHCI_ITD_ACTIVE; 3075 itd->itd.itd_ctl[i] = htole32(trans_status); 3076 } 3077 3078 usb_syncmem(&itd->dma, 3079 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3080 sizeof(itd->itd.itd_ctl), 3081 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3082 } 3083 splx(s); 3084 3085 s = splusb(); 3086 #ifdef USB_USE_SOFTINTR 3087 sc->sc_softwake = 1; 3088 #endif /* USB_USE_SOFTINTR */ 3089 usb_schedsoftintr(&sc->sc_bus); 3090 #ifdef USB_USE_SOFTINTR 3091 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3092 #endif /* USB_USE_SOFTINTR */ 3093 splx(s); 3094 3095 #ifdef DIAGNOSTIC 3096 exfer->isdone = 1; 3097 #endif 3098 wake = xfer->hcflags & UXFER_ABORTWAIT; 3099 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3100 usb_transfer_complete(xfer); 3101 if (wake) 3102 wakeup(&xfer->hcflags); 3103 3104 return; 3105 } 3106 3107 void 3108 ehci_timeout(void *addr) 3109 { 3110 struct ehci_xfer *exfer = addr; 3111 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3112 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3113 3114 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3115 #ifdef USB_DEBUG 3116 if (ehcidebug > 1) 3117 usbd_dump_pipe(exfer->xfer.pipe); 3118 #endif 3119 3120 if (sc->sc_dying) { 3121 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3122 return; 3123 } 3124 3125 /* Execute the abort in a process context. */ 3126 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3127 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3128 USB_TASKQ_HC); 3129 } 3130 3131 void 3132 ehci_timeout_task(void *addr) 3133 { 3134 usbd_xfer_handle xfer = addr; 3135 int s; 3136 3137 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3138 3139 s = splusb(); 3140 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3141 splx(s); 3142 } 3143 3144 /************************/ 3145 3146 Static usbd_status 3147 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3148 { 3149 usbd_status err; 3150 3151 /* Insert last in queue. */ 3152 err = usb_insert_transfer(xfer); 3153 if (err) 3154 return (err); 3155 3156 /* Pipe isn't running, start first */ 3157 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3158 } 3159 3160 Static usbd_status 3161 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3162 { 3163 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3164 usbd_status err; 3165 3166 if (sc->sc_dying) 3167 return (USBD_IOERROR); 3168 3169 #ifdef DIAGNOSTIC 3170 if (!(xfer->rqflags & URQ_REQUEST)) { 3171 /* XXX panic */ 3172 printf("ehci_device_ctrl_transfer: not a request\n"); 3173 return (USBD_INVAL); 3174 } 3175 #endif 3176 3177 err = ehci_device_request(xfer); 3178 if (err) 3179 return (err); 3180 3181 if (sc->sc_bus.use_polling) 3182 ehci_waitintr(sc, xfer); 3183 return (USBD_IN_PROGRESS); 3184 } 3185 3186 void 3187 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3188 { 3189 struct ehci_xfer *ex = EXFER(xfer); 3190 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3191 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3192 usb_device_request_t *req = &xfer->request; 3193 int len = UGETW(req->wLength); 3194 int rd = req->bmRequestType & UT_READ; 3195 3196 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3197 3198 #ifdef DIAGNOSTIC 3199 if (!(xfer->rqflags & URQ_REQUEST)) { 3200 panic("ehci_ctrl_done: not a request"); 3201 } 3202 #endif 3203 3204 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3205 ehci_del_intr_list(ex); /* remove from active list */ 3206 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3207 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3208 BUS_DMASYNC_POSTWRITE); 3209 if (len) 3210 usb_syncmem(&xfer->dmabuf, 0, len, 3211 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3212 } 3213 3214 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3215 } 3216 3217 /* Abort a device control request. */ 3218 Static void 3219 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3220 { 3221 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3222 ehci_abort_xfer(xfer, USBD_CANCELLED); 3223 } 3224 3225 /* Close a device control pipe. */ 3226 Static void 3227 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3228 { 3229 ehci_softc_t *sc = pipe->device->bus->hci_private; 3230 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3231 3232 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3233 ehci_close_pipe(pipe, sc->sc_async_head); 3234 } 3235 3236 usbd_status 3237 ehci_device_request(usbd_xfer_handle xfer) 3238 { 3239 #define exfer EXFER(xfer) 3240 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3241 usb_device_request_t *req = &xfer->request; 3242 usbd_device_handle dev = epipe->pipe.device; 3243 ehci_softc_t *sc = dev->bus->hci_private; 3244 int addr = dev->address; 3245 ehci_soft_qtd_t *setup, *stat, *next; 3246 ehci_soft_qh_t *sqh; 3247 int isread; 3248 int len; 3249 usbd_status err; 3250 int s; 3251 3252 isread = req->bmRequestType & UT_READ; 3253 len = UGETW(req->wLength); 3254 3255 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3256 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3257 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3258 UGETW(req->wIndex), len, addr, 3259 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3260 3261 setup = ehci_alloc_sqtd(sc); 3262 if (setup == NULL) { 3263 err = USBD_NOMEM; 3264 goto bad1; 3265 } 3266 stat = ehci_alloc_sqtd(sc); 3267 if (stat == NULL) { 3268 err = USBD_NOMEM; 3269 goto bad2; 3270 } 3271 3272 sqh = epipe->sqh; 3273 epipe->u.ctl.length = len; 3274 3275 /* Update device address and length since they may have changed 3276 during the setup of the control pipe in usbd_new_device(). */ 3277 /* XXX This only needs to be done once, but it's too early in open. */ 3278 /* XXXX Should not touch ED here! */ 3279 sqh->qh.qh_endp = 3280 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3281 htole32( 3282 EHCI_QH_SET_ADDR(addr) | 3283 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3284 ); 3285 3286 /* Set up data transaction */ 3287 if (len != 0) { 3288 ehci_soft_qtd_t *end; 3289 3290 /* Start toggle at 1. */ 3291 epipe->nexttoggle = 1; 3292 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3293 &next, &end); 3294 if (err) 3295 goto bad3; 3296 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3297 end->nextqtd = stat; 3298 end->qtd.qtd_next = 3299 end->qtd.qtd_altnext = htole32(stat->physaddr); 3300 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3301 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3302 } else { 3303 next = stat; 3304 } 3305 3306 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3307 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3308 3309 /* Clear toggle */ 3310 setup->qtd.qtd_status = htole32( 3311 EHCI_QTD_ACTIVE | 3312 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3313 EHCI_QTD_SET_CERR(3) | 3314 EHCI_QTD_SET_TOGGLE(0) | 3315 EHCI_QTD_SET_BYTES(sizeof *req) 3316 ); 3317 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3318 setup->qtd.qtd_buffer_hi[0] = 0; 3319 setup->nextqtd = next; 3320 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3321 setup->xfer = xfer; 3322 setup->len = sizeof *req; 3323 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3324 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3325 3326 stat->qtd.qtd_status = htole32( 3327 EHCI_QTD_ACTIVE | 3328 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3329 EHCI_QTD_SET_CERR(3) | 3330 EHCI_QTD_SET_TOGGLE(1) | 3331 EHCI_QTD_IOC 3332 ); 3333 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3334 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3335 stat->nextqtd = NULL; 3336 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3337 stat->xfer = xfer; 3338 stat->len = 0; 3339 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3340 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3341 3342 #ifdef EHCI_DEBUG 3343 if (ehcidebug > 5) { 3344 DPRINTF(("ehci_device_request:\n")); 3345 ehci_dump_sqh(sqh); 3346 ehci_dump_sqtds(setup); 3347 } 3348 #endif 3349 3350 exfer->sqtdstart = setup; 3351 exfer->sqtdend = stat; 3352 #ifdef DIAGNOSTIC 3353 if (!exfer->isdone) { 3354 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3355 } 3356 exfer->isdone = 0; 3357 #endif 3358 3359 /* Insert qTD in QH list. */ 3360 s = splusb(); 3361 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3362 if (xfer->timeout && !sc->sc_bus.use_polling) { 3363 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3364 ehci_timeout, xfer); 3365 } 3366 ehci_add_intr_list(sc, exfer); 3367 xfer->status = USBD_IN_PROGRESS; 3368 splx(s); 3369 3370 #ifdef EHCI_DEBUG 3371 if (ehcidebug > 10) { 3372 DPRINTF(("ehci_device_request: status=%x\n", 3373 EOREAD4(sc, EHCI_USBSTS))); 3374 delay(10000); 3375 ehci_dump_regs(sc); 3376 ehci_dump_sqh(sc->sc_async_head); 3377 ehci_dump_sqh(sqh); 3378 ehci_dump_sqtds(setup); 3379 } 3380 #endif 3381 3382 return (USBD_NORMAL_COMPLETION); 3383 3384 bad3: 3385 ehci_free_sqtd(sc, stat); 3386 bad2: 3387 ehci_free_sqtd(sc, setup); 3388 bad1: 3389 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3390 xfer->status = err; 3391 usb_transfer_complete(xfer); 3392 return (err); 3393 #undef exfer 3394 } 3395 3396 /* 3397 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3398 * qTD status, or miss signalling occasionally under heavy load. If the host 3399 * machine is too fast, we we can miss transaction completion - when we scan 3400 * the active list the transaction still seems to be active. This generally 3401 * exhibits itself as a umass stall that never recovers. 3402 * 3403 * We work around this behaviour by setting up this callback after any softintr 3404 * that completes with transactions still pending, giving us another chance to 3405 * check for completion after the writeback has taken place. 3406 */ 3407 void 3408 ehci_intrlist_timeout(void *arg) 3409 { 3410 ehci_softc_t *sc = arg; 3411 int s = splusb(); 3412 3413 DPRINTF(("ehci_intrlist_timeout\n")); 3414 usb_schedsoftintr(&sc->sc_bus); 3415 3416 splx(s); 3417 } 3418 3419 /************************/ 3420 3421 Static usbd_status 3422 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3423 { 3424 usbd_status err; 3425 3426 /* Insert last in queue. */ 3427 err = usb_insert_transfer(xfer); 3428 if (err) 3429 return (err); 3430 3431 /* Pipe isn't running, start first */ 3432 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3433 } 3434 3435 usbd_status 3436 ehci_device_bulk_start(usbd_xfer_handle xfer) 3437 { 3438 #define exfer EXFER(xfer) 3439 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3440 usbd_device_handle dev = epipe->pipe.device; 3441 ehci_softc_t *sc = dev->bus->hci_private; 3442 ehci_soft_qtd_t *data, *dataend; 3443 ehci_soft_qh_t *sqh; 3444 usbd_status err; 3445 int len, isread, endpt; 3446 int s; 3447 3448 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3449 xfer, xfer->length, xfer->flags)); 3450 3451 if (sc->sc_dying) 3452 return (USBD_IOERROR); 3453 3454 #ifdef DIAGNOSTIC 3455 if (xfer->rqflags & URQ_REQUEST) 3456 panic("ehci_device_bulk_start: a request"); 3457 #endif 3458 3459 len = xfer->length; 3460 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3461 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3462 sqh = epipe->sqh; 3463 3464 epipe->u.bulk.length = len; 3465 3466 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3467 &dataend); 3468 if (err) { 3469 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3470 xfer->status = err; 3471 usb_transfer_complete(xfer); 3472 return (err); 3473 } 3474 3475 #ifdef EHCI_DEBUG 3476 if (ehcidebug > 5) { 3477 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3478 ehci_dump_sqh(sqh); 3479 ehci_dump_sqtds(data); 3480 } 3481 #endif 3482 3483 /* Set up interrupt info. */ 3484 exfer->sqtdstart = data; 3485 exfer->sqtdend = dataend; 3486 #ifdef DIAGNOSTIC 3487 if (!exfer->isdone) { 3488 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3489 } 3490 exfer->isdone = 0; 3491 #endif 3492 3493 s = splusb(); 3494 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3495 if (xfer->timeout && !sc->sc_bus.use_polling) { 3496 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3497 ehci_timeout, xfer); 3498 } 3499 ehci_add_intr_list(sc, exfer); 3500 xfer->status = USBD_IN_PROGRESS; 3501 splx(s); 3502 3503 #ifdef EHCI_DEBUG 3504 if (ehcidebug > 10) { 3505 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3506 delay(10000); 3507 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3508 ehci_dump_regs(sc); 3509 #if 0 3510 printf("async_head:\n"); 3511 ehci_dump_sqh(sc->sc_async_head); 3512 #endif 3513 printf("sqh:\n"); 3514 ehci_dump_sqh(sqh); 3515 ehci_dump_sqtds(data); 3516 } 3517 #endif 3518 3519 if (sc->sc_bus.use_polling) 3520 ehci_waitintr(sc, xfer); 3521 3522 return (USBD_IN_PROGRESS); 3523 #undef exfer 3524 } 3525 3526 Static void 3527 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3528 { 3529 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3530 ehci_abort_xfer(xfer, USBD_CANCELLED); 3531 } 3532 3533 /* 3534 * Close a device bulk pipe. 3535 */ 3536 Static void 3537 ehci_device_bulk_close(usbd_pipe_handle pipe) 3538 { 3539 ehci_softc_t *sc = pipe->device->bus->hci_private; 3540 3541 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3542 ehci_close_pipe(pipe, sc->sc_async_head); 3543 } 3544 3545 void 3546 ehci_device_bulk_done(usbd_xfer_handle xfer) 3547 { 3548 struct ehci_xfer *ex = EXFER(xfer); 3549 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3550 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3551 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3552 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3553 3554 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3555 xfer, xfer->actlen)); 3556 3557 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3558 ehci_del_intr_list(ex); /* remove from active list */ 3559 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3560 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3561 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3562 } 3563 3564 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3565 } 3566 3567 /************************/ 3568 3569 Static usbd_status 3570 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3571 { 3572 struct ehci_soft_islot *isp; 3573 int islot, lev; 3574 3575 /* Find a poll rate that is large enough. */ 3576 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3577 if (EHCI_ILEV_IVAL(lev) <= ival) 3578 break; 3579 3580 /* Pick an interrupt slot at the right level. */ 3581 /* XXX could do better than picking at random */ 3582 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3583 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3584 3585 sqh->islot = islot; 3586 isp = &sc->sc_islots[islot]; 3587 ehci_add_qh(sqh, isp->sqh); 3588 3589 return (USBD_NORMAL_COMPLETION); 3590 } 3591 3592 Static usbd_status 3593 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3594 { 3595 usbd_status err; 3596 3597 /* Insert last in queue. */ 3598 err = usb_insert_transfer(xfer); 3599 if (err) 3600 return (err); 3601 3602 /* 3603 * Pipe isn't running (otherwise err would be USBD_INPROG), 3604 * so start it first. 3605 */ 3606 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3607 } 3608 3609 Static usbd_status 3610 ehci_device_intr_start(usbd_xfer_handle xfer) 3611 { 3612 #define exfer EXFER(xfer) 3613 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3614 usbd_device_handle dev = xfer->pipe->device; 3615 ehci_softc_t *sc = dev->bus->hci_private; 3616 ehci_soft_qtd_t *data, *dataend; 3617 ehci_soft_qh_t *sqh; 3618 usbd_status err; 3619 int len, isread, endpt; 3620 int s; 3621 3622 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3623 xfer, xfer->length, xfer->flags)); 3624 3625 if (sc->sc_dying) 3626 return (USBD_IOERROR); 3627 3628 #ifdef DIAGNOSTIC 3629 if (xfer->rqflags & URQ_REQUEST) 3630 panic("ehci_device_intr_start: a request"); 3631 #endif 3632 3633 len = xfer->length; 3634 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3635 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3636 sqh = epipe->sqh; 3637 3638 epipe->u.intr.length = len; 3639 3640 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3641 &dataend); 3642 if (err) { 3643 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3644 xfer->status = err; 3645 usb_transfer_complete(xfer); 3646 return (err); 3647 } 3648 3649 #ifdef EHCI_DEBUG 3650 if (ehcidebug > 5) { 3651 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3652 ehci_dump_sqh(sqh); 3653 ehci_dump_sqtds(data); 3654 } 3655 #endif 3656 3657 /* Set up interrupt info. */ 3658 exfer->sqtdstart = data; 3659 exfer->sqtdend = dataend; 3660 #ifdef DIAGNOSTIC 3661 if (!exfer->isdone) { 3662 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3663 } 3664 exfer->isdone = 0; 3665 #endif 3666 3667 s = splusb(); 3668 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3669 if (xfer->timeout && !sc->sc_bus.use_polling) { 3670 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3671 ehci_timeout, xfer); 3672 } 3673 ehci_add_intr_list(sc, exfer); 3674 xfer->status = USBD_IN_PROGRESS; 3675 splx(s); 3676 3677 #ifdef EHCI_DEBUG 3678 if (ehcidebug > 10) { 3679 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3680 delay(10000); 3681 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3682 ehci_dump_regs(sc); 3683 printf("sqh:\n"); 3684 ehci_dump_sqh(sqh); 3685 ehci_dump_sqtds(data); 3686 } 3687 #endif 3688 3689 if (sc->sc_bus.use_polling) 3690 ehci_waitintr(sc, xfer); 3691 3692 return (USBD_IN_PROGRESS); 3693 #undef exfer 3694 } 3695 3696 Static void 3697 ehci_device_intr_abort(usbd_xfer_handle xfer) 3698 { 3699 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3700 if (xfer->pipe->intrxfer == xfer) { 3701 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3702 xfer->pipe->intrxfer = NULL; 3703 } 3704 /* 3705 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3706 * async doorbell. That's dependant on the async list, wheras 3707 * intr xfers are periodic, should not use this? 3708 */ 3709 ehci_abort_xfer(xfer, USBD_CANCELLED); 3710 } 3711 3712 Static void 3713 ehci_device_intr_close(usbd_pipe_handle pipe) 3714 { 3715 ehci_softc_t *sc = pipe->device->bus->hci_private; 3716 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3717 struct ehci_soft_islot *isp; 3718 3719 isp = &sc->sc_islots[epipe->sqh->islot]; 3720 ehci_close_pipe(pipe, isp->sqh); 3721 } 3722 3723 Static void 3724 ehci_device_intr_done(usbd_xfer_handle xfer) 3725 { 3726 #define exfer EXFER(xfer) 3727 struct ehci_xfer *ex = EXFER(xfer); 3728 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3729 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3730 ehci_soft_qtd_t *data, *dataend; 3731 ehci_soft_qh_t *sqh; 3732 usbd_status err; 3733 int len, isread, endpt, s; 3734 3735 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3736 xfer, xfer->actlen)); 3737 3738 if (xfer->pipe->repeat) { 3739 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3740 3741 len = epipe->u.intr.length; 3742 xfer->length = len; 3743 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3744 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3745 usb_syncmem(&xfer->dmabuf, 0, len, 3746 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3747 sqh = epipe->sqh; 3748 3749 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3750 &data, &dataend); 3751 if (err) { 3752 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3753 xfer->status = err; 3754 return; 3755 } 3756 3757 /* Set up interrupt info. */ 3758 exfer->sqtdstart = data; 3759 exfer->sqtdend = dataend; 3760 #ifdef DIAGNOSTIC 3761 if (!exfer->isdone) { 3762 printf("ehci_device_intr_done: not done, ex=%p\n", 3763 exfer); 3764 } 3765 exfer->isdone = 0; 3766 #endif 3767 3768 s = splusb(); 3769 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3770 if (xfer->timeout && !sc->sc_bus.use_polling) { 3771 usb_callout(xfer->timeout_handle, 3772 mstohz(xfer->timeout), ehci_timeout, xfer); 3773 } 3774 splx(s); 3775 3776 xfer->status = USBD_IN_PROGRESS; 3777 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3778 ehci_del_intr_list(ex); /* remove from active list */ 3779 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3780 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3781 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3782 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3783 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3784 } 3785 #undef exfer 3786 } 3787 3788 /************************/ 3789 3790 Static usbd_status 3791 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3792 { 3793 usbd_status err; 3794 3795 err = usb_insert_transfer(xfer); 3796 if (err && err != USBD_IN_PROGRESS) 3797 return err; 3798 3799 return ehci_device_isoc_start(xfer); 3800 } 3801 3802 Static usbd_status 3803 ehci_device_isoc_start(usbd_xfer_handle xfer) 3804 { 3805 struct ehci_pipe *epipe; 3806 usbd_device_handle dev; 3807 ehci_softc_t *sc; 3808 struct ehci_xfer *exfer; 3809 ehci_soft_itd_t *itd, *prev, *start, *stop; 3810 usb_dma_t *dma_buf; 3811 int i, j, k, frames, uframes, ufrperframe; 3812 int s, trans_count, offs, total_length; 3813 int frindex; 3814 3815 start = NULL; 3816 prev = NULL; 3817 itd = NULL; 3818 trans_count = 0; 3819 total_length = 0; 3820 exfer = (struct ehci_xfer *) xfer; 3821 sc = xfer->pipe->device->bus->hci_private; 3822 dev = xfer->pipe->device; 3823 epipe = (struct ehci_pipe *)xfer->pipe; 3824 3825 /* 3826 * To allow continuous transfers, above we start all transfers 3827 * immediately. However, we're still going to get usbd_start_next call 3828 * this when another xfer completes. So, check if this is already 3829 * in progress or not 3830 */ 3831 3832 if (exfer->itdstart != NULL) 3833 return USBD_IN_PROGRESS; 3834 3835 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3836 xfer, xfer->length, xfer->flags)); 3837 3838 if (sc->sc_dying) 3839 return USBD_IOERROR; 3840 3841 /* 3842 * To avoid complication, don't allow a request right now that'll span 3843 * the entire frame table. To within 4 frames, to allow some leeway 3844 * on either side of where the hc currently is. 3845 */ 3846 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3847 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3848 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3849 return USBD_INVAL; 3850 } 3851 3852 #ifdef DIAGNOSTIC 3853 if (xfer->rqflags & URQ_REQUEST) 3854 panic("ehci_device_isoc_start: request\n"); 3855 3856 if (!exfer->isdone) 3857 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3858 exfer->isdone = 0; 3859 #endif 3860 3861 /* 3862 * Step 1: Allocate and initialize itds, how many do we need? 3863 * One per transfer if interval >= 8 microframes, fewer if we use 3864 * multiple microframes per frame. 3865 */ 3866 3867 i = epipe->pipe.endpoint->edesc->bInterval; 3868 if (i > 16 || i == 0) { 3869 /* Spec page 271 says intervals > 16 are invalid */ 3870 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3871 return USBD_INVAL; 3872 } 3873 3874 switch (i) { 3875 case 1: 3876 ufrperframe = 8; 3877 break; 3878 case 2: 3879 ufrperframe = 4; 3880 break; 3881 case 3: 3882 ufrperframe = 2; 3883 break; 3884 default: 3885 ufrperframe = 1; 3886 break; 3887 } 3888 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3889 uframes = 8 / ufrperframe; 3890 3891 if (frames == 0) { 3892 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3893 return USBD_INVAL; 3894 } 3895 3896 dma_buf = &xfer->dmabuf; 3897 offs = 0; 3898 3899 for (i = 0; i < frames; i++) { 3900 int froffs = offs; 3901 itd = ehci_alloc_itd(sc); 3902 3903 if (prev != NULL) { 3904 prev->itd.itd_next = 3905 htole32(itd->physaddr | EHCI_LINK_ITD); 3906 usb_syncmem(&itd->dma, 3907 itd->offs + offsetof(ehci_itd_t, itd_next), 3908 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 3909 3910 prev->xfer_next = itd; 3911 } else { 3912 start = itd; 3913 } 3914 3915 /* 3916 * Step 1.5, initialize uframes 3917 */ 3918 for (j = 0; j < 8; j += uframes) { 3919 /* Calculate which page in the list this starts in */ 3920 int addr = DMAADDR(dma_buf, froffs); 3921 addr = EHCI_PAGE_OFFSET(addr); 3922 addr += (offs - froffs); 3923 addr = EHCI_PAGE(addr); 3924 addr /= EHCI_PAGE_SIZE; 3925 3926 /* This gets the initial offset into the first page, 3927 * looks how far further along the current uframe 3928 * offset is. Works out how many pages that is. 3929 */ 3930 3931 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3932 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3933 EHCI_ITD_SET_PG(addr) | 3934 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 3935 3936 total_length += xfer->frlengths[trans_count]; 3937 offs += xfer->frlengths[trans_count]; 3938 trans_count++; 3939 3940 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3941 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3942 break; 3943 } 3944 } 3945 3946 /* Step 1.75, set buffer pointers. To simplify matters, all 3947 * pointers are filled out for the next 7 hardware pages in 3948 * the dma block, so no need to worry what pages to cover 3949 * and what to not. 3950 */ 3951 3952 for (j=0; j < 7; j++) { 3953 /* 3954 * Don't try to lookup a page that's past the end 3955 * of buffer 3956 */ 3957 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 3958 if (page_offs >= dma_buf->block->size) 3959 break; 3960 3961 int page = DMAADDR(dma_buf, page_offs); 3962 page = EHCI_PAGE(page); 3963 itd->itd.itd_bufr[j] = 3964 htole32(EHCI_ITD_SET_BPTR(page) | 3965 EHCI_LINK_ITD); 3966 } 3967 3968 /* 3969 * Other special values 3970 */ 3971 3972 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3973 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3974 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3975 3976 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3977 ? 1 : 0; 3978 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3979 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3980 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3981 3982 /* FIXME: handle invalid trans */ 3983 itd->itd.itd_bufr[2] |= 3984 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3985 3986 usb_syncmem(&itd->dma, 3987 itd->offs + offsetof(ehci_itd_t, itd_next), 3988 sizeof(ehci_itd_t), 3989 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3990 3991 prev = itd; 3992 } /* End of frame */ 3993 3994 stop = itd; 3995 stop->xfer_next = NULL; 3996 exfer->isoc_len = total_length; 3997 3998 /* 3999 * Part 2: Transfer descriptors have now been set up, now they must 4000 * be scheduled into the period frame list. Erk. Not wanting to 4001 * complicate matters, transfer is denied if the transfer spans 4002 * more than the period frame list. 4003 */ 4004 4005 s = splusb(); 4006 4007 /* Start inserting frames */ 4008 if (epipe->u.isoc.cur_xfers > 0) { 4009 frindex = epipe->u.isoc.next_frame; 4010 } else { 4011 frindex = EOREAD4(sc, EHCI_FRINDEX); 4012 frindex = frindex >> 3; /* Erase microframe index */ 4013 frindex += 2; 4014 } 4015 4016 if (frindex >= sc->sc_flsize) 4017 frindex &= (sc->sc_flsize - 1); 4018 4019 /* Whats the frame interval? */ 4020 i = (1 << epipe->pipe.endpoint->edesc->bInterval); 4021 if (i / 8 == 0) 4022 i = 1; 4023 else 4024 i /= 8; 4025 4026 itd = start; 4027 for (j = 0; j < frames; j++) { 4028 if (itd == NULL) 4029 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4030 4031 itd->itd.itd_next = sc->sc_flist[frindex]; 4032 if (itd->itd.itd_next == 0) 4033 /* FIXME: frindex table gets initialized to NULL 4034 * or EHCI_NULL? */ 4035 itd->itd.itd_next = htole32(EHCI_NULL); 4036 4037 usb_syncmem(&itd->dma, 4038 itd->offs + offsetof(ehci_itd_t, itd_next), 4039 sizeof(itd->itd.itd_next), 4040 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4041 4042 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4043 4044 usb_syncmem(&sc->sc_fldma, 4045 sizeof(ehci_link_t) * frindex, 4046 sizeof(ehci_link_t), 4047 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4048 4049 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4050 sc->sc_softitds[frindex] = itd; 4051 if (itd->u.frame_list.next != NULL) 4052 itd->u.frame_list.next->u.frame_list.prev = itd; 4053 itd->slot = frindex; 4054 itd->u.frame_list.prev = NULL; 4055 4056 frindex += i; 4057 if (frindex >= sc->sc_flsize) 4058 frindex -= sc->sc_flsize; 4059 4060 itd = itd->xfer_next; 4061 } 4062 4063 epipe->u.isoc.cur_xfers++; 4064 epipe->u.isoc.next_frame = frindex; 4065 4066 exfer->itdstart = start; 4067 exfer->itdend = stop; 4068 exfer->sqtdstart = NULL; 4069 exfer->sqtdstart = NULL; 4070 4071 ehci_add_intr_list(sc, exfer); 4072 xfer->status = USBD_IN_PROGRESS; 4073 xfer->done = 0; 4074 splx(s); 4075 4076 if (sc->sc_bus.use_polling) { 4077 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4078 ehci_waitintr(sc, xfer); 4079 } 4080 4081 return USBD_IN_PROGRESS; 4082 } 4083 4084 Static void 4085 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4086 { 4087 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4088 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4089 } 4090 4091 Static void 4092 ehci_device_isoc_close(usbd_pipe_handle pipe) 4093 { 4094 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4095 } 4096 4097 Static void 4098 ehci_device_isoc_done(usbd_xfer_handle xfer) 4099 { 4100 struct ehci_xfer *exfer; 4101 ehci_softc_t *sc; 4102 struct ehci_pipe *epipe; 4103 int s; 4104 4105 exfer = EXFER(xfer); 4106 sc = xfer->pipe->device->bus->hci_private; 4107 epipe = (struct ehci_pipe *) xfer->pipe; 4108 4109 s = splusb(); 4110 epipe->u.isoc.cur_xfers--; 4111 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4112 ehci_del_intr_list(exfer); 4113 ehci_rem_free_itd_chain(sc, exfer); 4114 } 4115 splx(s); 4116 4117 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4118 BUS_DMASYNC_POSTREAD); 4119 4120 } 4121
Indexes created Thu Oct 02 01:09:59 GMT 2025