ehci.c revision 1.152
1 /* $NetBSD: ehci.c,v 1.152 2008/10/11 13:56:51 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum and 9 * Jeremy Morse (jeremy.morse (at) gmail.com). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 35 * 36 * The EHCI 1.0 spec can be found at 37 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/usb_20.zip 40 * 41 */ 42 43 /* 44 * TODO: 45 * 1) hold off explorations by companion controllers until ehci has started. 46 * 47 * 2) The hub driver needs to handle and schedule the transaction translator, 48 * to assign place in frame where different devices get to go. See chapter 49 * on hubs in USB 2.0 for details. 50 * 51 * 3) command failures are not recovered correctly 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.152 2008/10/11 13:56:51 jmcneill Exp $"); 56 57 #include "ohci.h" 58 #include "uhci.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/kernel.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/select.h> 66 #include <sys/proc.h> 67 #include <sys/queue.h> 68 #include <sys/mutex.h> 69 #include <sys/bus.h> 70 71 #include <machine/endian.h> 72 73 #include <dev/usb/usb.h> 74 #include <dev/usb/usbdi.h> 75 #include <dev/usb/usbdivar.h> 76 #include <dev/usb/usb_mem.h> 77 #include <dev/usb/usb_quirks.h> 78 79 #include <dev/usb/ehcireg.h> 80 #include <dev/usb/ehcivar.h> 81 #include <dev/usb/usbroothub_subr.h> 82 83 #ifdef EHCI_DEBUG 84 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 85 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 86 int ehcidebug = 0; 87 #ifndef __NetBSD__ 88 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 89 #endif 90 #else 91 #define DPRINTF(x) 92 #define DPRINTFN(n,x) 93 #endif 94 95 struct ehci_pipe { 96 struct usbd_pipe pipe; 97 int nexttoggle; 98 99 ehci_soft_qh_t *sqh; 100 union { 101 ehci_soft_qtd_t *qtd; 102 /* ehci_soft_itd_t *itd; */ 103 } tail; 104 union { 105 /* Control pipe */ 106 struct { 107 usb_dma_t reqdma; 108 u_int length; 109 } ctl; 110 /* Interrupt pipe */ 111 struct { 112 u_int length; 113 } intr; 114 /* Bulk pipe */ 115 struct { 116 u_int length; 117 } bulk; 118 /* Iso pipe */ 119 struct { 120 u_int next_frame; 121 u_int cur_xfers; 122 } isoc; 123 } u; 124 }; 125 126 Static usbd_status ehci_open(usbd_pipe_handle); 127 Static void ehci_poll(struct usbd_bus *); 128 Static void ehci_softintr(void *); 129 Static int ehci_intr1(ehci_softc_t *); 130 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 131 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 132 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 133 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 134 Static void ehci_idone(struct ehci_xfer *); 135 Static void ehci_timeout(void *); 136 Static void ehci_timeout_task(void *); 137 Static void ehci_intrlist_timeout(void *); 138 139 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 140 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 141 142 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 143 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 144 145 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 146 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 147 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 148 Static void ehci_root_ctrl_close(usbd_pipe_handle); 149 Static void ehci_root_ctrl_done(usbd_xfer_handle); 150 151 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 152 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 153 Static void ehci_root_intr_abort(usbd_xfer_handle); 154 Static void ehci_root_intr_close(usbd_pipe_handle); 155 Static void ehci_root_intr_done(usbd_xfer_handle); 156 157 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 158 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 159 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 160 Static void ehci_device_ctrl_close(usbd_pipe_handle); 161 Static void ehci_device_ctrl_done(usbd_xfer_handle); 162 163 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 164 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 165 Static void ehci_device_bulk_abort(usbd_xfer_handle); 166 Static void ehci_device_bulk_close(usbd_pipe_handle); 167 Static void ehci_device_bulk_done(usbd_xfer_handle); 168 169 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 170 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 171 Static void ehci_device_intr_abort(usbd_xfer_handle); 172 Static void ehci_device_intr_close(usbd_pipe_handle); 173 Static void ehci_device_intr_done(usbd_xfer_handle); 174 175 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 176 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 177 Static void ehci_device_isoc_abort(usbd_xfer_handle); 178 Static void ehci_device_isoc_close(usbd_pipe_handle); 179 Static void ehci_device_isoc_done(usbd_xfer_handle); 180 181 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 182 Static void ehci_noop(usbd_pipe_handle pipe); 183 184 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 185 Static void ehci_disown(ehci_softc_t *, int, int); 186 187 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 188 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 189 190 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 191 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 192 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 193 ehci_softc_t *, int, int, usbd_xfer_handle, 194 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 195 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 196 ehci_soft_qtd_t *); 197 198 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 199 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 200 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 201 struct ehci_xfer *exfer); 202 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 203 usbd_status status); 204 205 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 206 207 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 208 int ival); 209 210 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 211 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 212 ehci_soft_qh_t *); 213 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 214 Static void ehci_sync_hc(ehci_softc_t *); 215 216 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 217 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 218 219 #ifdef EHCI_DEBUG 220 Static void ehci_dump_regs(ehci_softc_t *); 221 void ehci_dump(void); 222 Static ehci_softc_t *theehci; 223 Static void ehci_dump_link(ehci_link_t, int); 224 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 225 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 226 Static void ehci_dump_qtd(ehci_qtd_t *); 227 Static void ehci_dump_sqh(ehci_soft_qh_t *); 228 #if notyet 229 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 230 Static void ehci_dump_itd(struct ehci_soft_itd *); 231 #endif 232 #ifdef DIAGNOSTIC 233 Static void ehci_dump_exfer(struct ehci_xfer *); 234 #endif 235 #endif 236 237 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 238 239 #define EHCI_INTR_ENDPT 1 240 241 #define ehci_add_intr_list(sc, ex) \ 242 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext); 243 #define ehci_del_intr_list(ex) \ 244 do { \ 245 LIST_REMOVE((ex), inext); \ 246 (ex)->inext.le_prev = NULL; \ 247 } while (0) 248 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL) 249 250 Static const struct usbd_bus_methods ehci_bus_methods = { 251 ehci_open, 252 ehci_softintr, 253 ehci_poll, 254 ehci_allocm, 255 ehci_freem, 256 ehci_allocx, 257 ehci_freex, 258 }; 259 260 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 261 ehci_root_ctrl_transfer, 262 ehci_root_ctrl_start, 263 ehci_root_ctrl_abort, 264 ehci_root_ctrl_close, 265 ehci_noop, 266 ehci_root_ctrl_done, 267 }; 268 269 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 270 ehci_root_intr_transfer, 271 ehci_root_intr_start, 272 ehci_root_intr_abort, 273 ehci_root_intr_close, 274 ehci_noop, 275 ehci_root_intr_done, 276 }; 277 278 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 279 ehci_device_ctrl_transfer, 280 ehci_device_ctrl_start, 281 ehci_device_ctrl_abort, 282 ehci_device_ctrl_close, 283 ehci_noop, 284 ehci_device_ctrl_done, 285 }; 286 287 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 288 ehci_device_intr_transfer, 289 ehci_device_intr_start, 290 ehci_device_intr_abort, 291 ehci_device_intr_close, 292 ehci_device_clear_toggle, 293 ehci_device_intr_done, 294 }; 295 296 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 297 ehci_device_bulk_transfer, 298 ehci_device_bulk_start, 299 ehci_device_bulk_abort, 300 ehci_device_bulk_close, 301 ehci_device_clear_toggle, 302 ehci_device_bulk_done, 303 }; 304 305 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 306 ehci_device_isoc_transfer, 307 ehci_device_isoc_start, 308 ehci_device_isoc_abort, 309 ehci_device_isoc_close, 310 ehci_noop, 311 ehci_device_isoc_done, 312 }; 313 314 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 315 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 316 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 317 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 318 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 319 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 320 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 321 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 322 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 323 }; 324 325 usbd_status 326 ehci_init(ehci_softc_t *sc) 327 { 328 u_int32_t vers, sparams, cparams, hcr; 329 u_int i; 330 usbd_status err; 331 ehci_soft_qh_t *sqh; 332 u_int ncomp; 333 334 DPRINTF(("ehci_init: start\n")); 335 #ifdef EHCI_DEBUG 336 theehci = sc; 337 #endif 338 339 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 340 341 vers = EREAD2(sc, EHCI_HCIVERSION); 342 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 343 vers >> 8, vers & 0xff); 344 345 sparams = EREAD4(sc, EHCI_HCSPARAMS); 346 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 347 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 348 ncomp = EHCI_HCS_N_CC(sparams); 349 if (ncomp != sc->sc_ncomp) { 350 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 351 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 352 #if NOHCI == 0 || NUHCI == 0 353 aprint_error("%s: ohci or uhci probably not configured\n", 354 device_xname(sc->sc_dev)); 355 #endif 356 if (ncomp < sc->sc_ncomp) 357 sc->sc_ncomp = ncomp; 358 } 359 if (sc->sc_ncomp > 0) { 360 aprint_normal("%s: companion controller%s, %d port%s each:", 361 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 362 EHCI_HCS_N_PCC(sparams), 363 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 364 for (i = 0; i < sc->sc_ncomp; i++) 365 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 366 aprint_normal("\n"); 367 } 368 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 369 cparams = EREAD4(sc, EHCI_HCCPARAMS); 370 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 371 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 372 373 if (EHCI_HCC_64BIT(cparams)) { 374 /* MUST clear segment register if 64 bit capable. */ 375 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 376 } 377 378 sc->sc_bus.usbrev = USBREV_2_0; 379 380 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 381 USB_MEM_RESERVE); 382 383 /* Reset the controller */ 384 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 385 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 386 usb_delay_ms(&sc->sc_bus, 1); 387 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 388 for (i = 0; i < 100; i++) { 389 usb_delay_ms(&sc->sc_bus, 1); 390 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 391 if (!hcr) 392 break; 393 } 394 if (hcr) { 395 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 396 return (USBD_IOERROR); 397 } 398 399 /* XXX need proper intr scheduling */ 400 sc->sc_rand = 96; 401 402 /* frame list size at default, read back what we got and use that */ 403 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 404 case 0: sc->sc_flsize = 1024; break; 405 case 1: sc->sc_flsize = 512; break; 406 case 2: sc->sc_flsize = 256; break; 407 case 3: return (USBD_IOERROR); 408 } 409 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 410 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 411 if (err) 412 return (err); 413 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 414 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 415 416 for (i = 0; i < sc->sc_flsize; i++) { 417 sc->sc_flist[i] = EHCI_NULL; 418 } 419 420 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 421 422 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 423 M_USB, M_NOWAIT | M_ZERO); 424 if (sc->sc_softitds == NULL) 425 return ENOMEM; 426 LIST_INIT(&sc->sc_freeitds); 427 428 /* Set up the bus struct. */ 429 sc->sc_bus.methods = &ehci_bus_methods; 430 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 431 432 sc->sc_eintrs = EHCI_NORMAL_INTRS; 433 434 /* 435 * Allocate the interrupt dummy QHs. These are arranged to give poll 436 * intervals that are powers of 2 times 1ms. 437 */ 438 for (i = 0; i < EHCI_INTRQHS; i++) { 439 sqh = ehci_alloc_sqh(sc); 440 if (sqh == NULL) { 441 err = USBD_NOMEM; 442 goto bad1; 443 } 444 sc->sc_islots[i].sqh = sqh; 445 } 446 for (i = 0; i < EHCI_INTRQHS; i++) { 447 sqh = sc->sc_islots[i].sqh; 448 if (i == 0) { 449 /* The last (1ms) QH terminates. */ 450 sqh->qh.qh_link = EHCI_NULL; 451 sqh->next = NULL; 452 } else { 453 /* Otherwise the next QH has half the poll interval */ 454 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 455 sqh->qh.qh_link = htole32(sqh->next->physaddr | 456 EHCI_LINK_QH); 457 } 458 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 459 sqh->qh.qh_curqtd = EHCI_NULL; 460 sqh->next = NULL; 461 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 462 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 463 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 464 sqh->sqtd = NULL; 465 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 466 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 467 } 468 /* Point the frame list at the last level (128ms). */ 469 for (i = 0; i < sc->sc_flsize; i++) { 470 int j; 471 472 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 473 revbits[i & (EHCI_MAX_POLLRATE-1)]; 474 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 475 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 476 i)].sqh->physaddr); 477 } 478 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 479 BUS_DMASYNC_PREWRITE); 480 481 /* Allocate dummy QH that starts the async list. */ 482 sqh = ehci_alloc_sqh(sc); 483 if (sqh == NULL) { 484 err = USBD_NOMEM; 485 goto bad1; 486 } 487 /* Fill the QH */ 488 sqh->qh.qh_endp = 489 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 490 sqh->qh.qh_link = 491 htole32(sqh->physaddr | EHCI_LINK_QH); 492 sqh->qh.qh_curqtd = EHCI_NULL; 493 sqh->next = NULL; 494 /* Fill the overlay qTD */ 495 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 496 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 497 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 498 sqh->sqtd = NULL; 499 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 500 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 501 #ifdef EHCI_DEBUG 502 if (ehcidebug) { 503 ehci_dump_sqh(sqh); 504 } 505 #endif 506 507 /* Point to async list */ 508 sc->sc_async_head = sqh; 509 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 510 511 usb_callout_init(sc->sc_tmo_intrlist); 512 513 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE); 514 515 /* Turn on controller */ 516 EOWRITE4(sc, EHCI_USBCMD, 517 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 518 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 519 EHCI_CMD_ASE | 520 EHCI_CMD_PSE | 521 EHCI_CMD_RS); 522 523 /* Take over port ownership */ 524 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 525 526 for (i = 0; i < 100; i++) { 527 usb_delay_ms(&sc->sc_bus, 1); 528 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 529 if (!hcr) 530 break; 531 } 532 if (hcr) { 533 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 534 return (USBD_IOERROR); 535 } 536 537 /* Enable interrupts */ 538 DPRINTFN(1,("ehci_init: enabling\n")); 539 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 540 541 return (USBD_NORMAL_COMPLETION); 542 543 #if 0 544 bad2: 545 ehci_free_sqh(sc, sc->sc_async_head); 546 #endif 547 bad1: 548 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 549 return (err); 550 } 551 552 int 553 ehci_intr(void *v) 554 { 555 ehci_softc_t *sc = v; 556 557 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 558 return (0); 559 560 /* If we get an interrupt while polling, then just ignore it. */ 561 if (sc->sc_bus.use_polling) { 562 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 563 564 if (intrs) 565 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 566 #ifdef DIAGNOSTIC 567 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 568 #endif 569 return (0); 570 } 571 572 return (ehci_intr1(sc)); 573 } 574 575 Static int 576 ehci_intr1(ehci_softc_t *sc) 577 { 578 u_int32_t intrs, eintrs; 579 580 DPRINTFN(20,("ehci_intr1: enter\n")); 581 582 /* In case the interrupt occurs before initialization has completed. */ 583 if (sc == NULL) { 584 #ifdef DIAGNOSTIC 585 printf("ehci_intr1: sc == NULL\n"); 586 #endif 587 return (0); 588 } 589 590 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 591 if (!intrs) 592 return (0); 593 594 eintrs = intrs & sc->sc_eintrs; 595 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 596 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 597 (u_int)eintrs)); 598 if (!eintrs) 599 return (0); 600 601 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 602 sc->sc_bus.intr_context++; 603 sc->sc_bus.no_intrs++; 604 if (eintrs & EHCI_STS_IAA) { 605 DPRINTF(("ehci_intr1: door bell\n")); 606 wakeup(&sc->sc_async_head); 607 eintrs &= ~EHCI_STS_IAA; 608 } 609 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 610 DPRINTFN(5,("ehci_intr1: %s %s\n", 611 eintrs & EHCI_STS_INT ? "INT" : "", 612 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 613 usb_schedsoftintr(&sc->sc_bus); 614 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 615 } 616 if (eintrs & EHCI_STS_HSE) { 617 printf("%s: unrecoverable error, controller halted\n", 618 device_xname(sc->sc_dev)); 619 /* XXX what else */ 620 } 621 if (eintrs & EHCI_STS_PCD) { 622 ehci_pcd(sc, sc->sc_intrxfer); 623 eintrs &= ~EHCI_STS_PCD; 624 } 625 626 sc->sc_bus.intr_context--; 627 628 if (eintrs != 0) { 629 /* Block unprocessed interrupts. */ 630 sc->sc_eintrs &= ~eintrs; 631 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 632 printf("%s: blocking intrs 0x%x\n", 633 device_xname(sc->sc_dev), eintrs); 634 } 635 636 return (1); 637 } 638 639 640 void 641 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 642 { 643 usbd_pipe_handle pipe; 644 u_char *p; 645 int i, m; 646 647 if (xfer == NULL) { 648 /* Just ignore the change. */ 649 return; 650 } 651 652 pipe = xfer->pipe; 653 654 p = KERNADDR(&xfer->dmabuf, 0); 655 m = min(sc->sc_noport, xfer->length * 8 - 1); 656 memset(p, 0, xfer->length); 657 for (i = 1; i <= m; i++) { 658 /* Pick out CHANGE bits from the status reg. */ 659 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 660 p[i/8] |= 1 << (i%8); 661 } 662 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 663 xfer->actlen = xfer->length; 664 xfer->status = USBD_NORMAL_COMPLETION; 665 666 usb_transfer_complete(xfer); 667 } 668 669 void 670 ehci_softintr(void *v) 671 { 672 struct usbd_bus *bus = v; 673 ehci_softc_t *sc = bus->hci_private; 674 struct ehci_xfer *ex, *nextex; 675 676 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 677 sc->sc_bus.intr_context)); 678 679 sc->sc_bus.intr_context++; 680 681 /* 682 * The only explanation I can think of for why EHCI is as brain dead 683 * as UHCI interrupt-wise is that Intel was involved in both. 684 * An interrupt just tells us that something is done, we have no 685 * clue what, so we need to scan through all active transfers. :-( 686 */ 687 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 688 nextex = LIST_NEXT(ex, inext); 689 ehci_check_intr(sc, ex); 690 } 691 692 /* Schedule a callout to catch any dropped transactions. */ 693 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 694 !LIST_EMPTY(&sc->sc_intrhead)) 695 usb_callout(sc->sc_tmo_intrlist, hz, 696 ehci_intrlist_timeout, sc); 697 698 #ifdef USB_USE_SOFTINTR 699 if (sc->sc_softwake) { 700 sc->sc_softwake = 0; 701 wakeup(&sc->sc_softwake); 702 } 703 #endif /* USB_USE_SOFTINTR */ 704 705 sc->sc_bus.intr_context--; 706 } 707 708 /* Check for an interrupt. */ 709 void 710 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 711 { 712 int attr; 713 714 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 715 716 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 717 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 718 ehci_check_itd_intr(sc, ex); 719 else 720 ehci_check_qh_intr(sc, ex); 721 722 return; 723 } 724 725 void 726 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 727 { 728 ehci_soft_qtd_t *sqtd, *lsqtd; 729 __uint32_t status; 730 731 if (ex->sqtdstart == NULL) { 732 printf("ehci_check_qh_intr: not valid sqtd\n"); 733 return; 734 } 735 736 lsqtd = ex->sqtdend; 737 #ifdef DIAGNOSTIC 738 if (lsqtd == NULL) { 739 printf("ehci_check_qh_intr: lsqtd==0\n"); 740 return; 741 } 742 #endif 743 /* 744 * If the last TD is still active we need to check whether there 745 * is a an error somewhere in the middle, or whether there was a 746 * short packet (SPD and not ACTIVE). 747 */ 748 usb_syncmem(&lsqtd->dma, 749 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 750 sizeof(lsqtd->qtd.qtd_status), 751 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 752 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 753 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 754 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 755 usb_syncmem(&sqtd->dma, 756 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 757 sizeof(sqtd->qtd.qtd_status), 758 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 759 status = le32toh(sqtd->qtd.qtd_status); 760 usb_syncmem(&sqtd->dma, 761 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 762 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 763 /* If there's an active QTD the xfer isn't done. */ 764 if (status & EHCI_QTD_ACTIVE) 765 break; 766 /* Any kind of error makes the xfer done. */ 767 if (status & EHCI_QTD_HALTED) 768 goto done; 769 /* We want short packets, and it is short: it's done */ 770 if (EHCI_QTD_GET_BYTES(status) != 0) 771 goto done; 772 } 773 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 774 ex, ex->sqtdstart)); 775 usb_syncmem(&lsqtd->dma, 776 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 777 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 778 return; 779 } 780 done: 781 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 782 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 783 ehci_idone(ex); 784 } 785 786 void 787 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 788 ehci_soft_itd_t *itd; 789 int i; 790 791 if (ex->itdstart == NULL) { 792 printf("ehci_check_itd_intr: not valid itd\n"); 793 return; 794 } 795 796 itd = ex->itdend; 797 #ifdef DIAGNOSTIC 798 if (itd == NULL) { 799 printf("ehci_check_itd_intr: itdend == 0\n"); 800 return; 801 } 802 #endif 803 804 /* 805 * Step 1, check no active transfers in last itd, meaning we're finished 806 */ 807 808 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 809 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 810 BUS_DMASYNC_POSTREAD); 811 812 for (i = 0; i < 8; i++) { 813 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 814 break; 815 } 816 817 if (i == 8) { 818 goto done; /* All 8 descriptors inactive, it's done */ 819 } 820 821 /* 822 * Step 2, check for errors in status bits, throughout chain... 823 */ 824 825 DPRINTFN(12, ("ehci_check_itd_intr: active ex=%p\n", ex)); 826 827 for (itd = ex->itdstart; itd != ex->itdend; itd = itd->xfer_next) { 828 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 829 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 830 BUS_DMASYNC_POSTREAD); 831 832 for (i = 0; i < 8; i++) { 833 if (le32toh(itd->itd.itd_ctl[i]) & (EHCI_ITD_BUF_ERR | 834 EHCI_ITD_BABBLE | EHCI_ITD_ERROR)) 835 break; 836 } 837 if (i != 8) { /* Error in one of the itds */ 838 goto done; 839 } 840 } /* itd search loop */ 841 842 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 843 ex->itdstart)); 844 return; 845 846 done: 847 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 848 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 849 ehci_idone(ex); 850 } 851 852 void 853 ehci_idone(struct ehci_xfer *ex) 854 { 855 usbd_xfer_handle xfer = &ex->xfer; 856 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 857 ehci_soft_qtd_t *sqtd, *lsqtd; 858 u_int32_t status = 0, nstatus = 0; 859 int actlen; 860 861 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 862 #ifdef DIAGNOSTIC 863 { 864 int s = splhigh(); 865 if (ex->isdone) { 866 splx(s); 867 #ifdef EHCI_DEBUG 868 printf("ehci_idone: ex is done!\n "); 869 ehci_dump_exfer(ex); 870 #else 871 printf("ehci_idone: ex=%p is done!\n", ex); 872 #endif 873 return; 874 } 875 ex->isdone = 1; 876 splx(s); 877 } 878 #endif 879 if (xfer->status == USBD_CANCELLED || 880 xfer->status == USBD_TIMEOUT) { 881 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 882 return; 883 } 884 885 #ifdef EHCI_DEBUG 886 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 887 if (ehcidebug > 10) 888 ehci_dump_sqtds(ex->sqtdstart); 889 #endif 890 891 /* The transfer is done, compute actual length and status. */ 892 893 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 894 == UE_ISOCHRONOUS) { 895 /* Isoc transfer */ 896 struct ehci_soft_itd *itd; 897 int i, nframes, len, uframes; 898 899 nframes = 0; 900 actlen = 0; 901 902 switch (xfer->pipe->endpoint->edesc->bInterval) { 903 case 0: 904 panic("ehci: isoc xfer suddenly has 0 bInterval, invalid\n"); 905 case 1: uframes = 1; break; 906 case 2: uframes = 2; break; 907 case 3: uframes = 4; break; 908 default: uframes = 8; break; 909 } 910 911 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 912 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 913 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 914 BUS_DMASYNC_POSTREAD); 915 916 for (i = 0; i < 8; i += uframes) { 917 /* XXX - driver didn't fill in the frame full 918 * of uframes. This leads to scheduling 919 * inefficiencies, but working around 920 * this doubles complexity of tracking 921 * an xfer. 922 */ 923 if (nframes >= xfer->nframes) 924 break; 925 926 status = le32toh(itd->itd.itd_ctl[i]); 927 len = EHCI_ITD_GET_LEN(status); 928 xfer->frlengths[nframes++] = len; 929 actlen += len; 930 } 931 932 if (nframes >= xfer->nframes) 933 break; 934 } 935 936 xfer->actlen = actlen; 937 xfer->status = USBD_NORMAL_COMPLETION; 938 if (xfer->rqflags & URQ_DEV_DMABUF) { 939 usb_syncmem(&xfer->dmabuf, 0, ex->isoc_len, 940 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 941 } 942 943 goto end; 944 } 945 946 /* Continue processing xfers using queue heads */ 947 948 lsqtd = ex->sqtdend; 949 actlen = 0; 950 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 951 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 952 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 953 nstatus = le32toh(sqtd->qtd.qtd_status); 954 if (nstatus & EHCI_QTD_ACTIVE) 955 break; 956 957 status = nstatus; 958 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 959 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 960 } 961 962 963 /* 964 * If there are left over TDs we need to update the toggle. 965 * The default pipe doesn't need it since control transfers 966 * start the toggle at 0 every time. 967 * For a short transfer we need to update the toggle for the missing 968 * packets within the qTD. 969 */ 970 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 971 xfer->pipe->device->default_pipe != xfer->pipe) { 972 DPRINTFN(2, ("ehci_idone: need toggle update " 973 "status=%08x nstatus=%08x\n", status, nstatus)); 974 #if 0 975 ehci_dump_sqh(epipe->sqh); 976 ehci_dump_sqtds(ex->sqtdstart); 977 #endif 978 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 979 } 980 981 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 982 xfer->length, actlen, status)); 983 xfer->actlen = actlen; 984 if (status & EHCI_QTD_HALTED) { 985 #ifdef EHCI_DEBUG 986 char sbuf[128]; 987 988 bitmask_snprintf((u_int32_t)status, 989 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 990 "\3MISSED\1PINGSTATE", sbuf, sizeof(sbuf)); 991 992 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 993 "status 0x%s\n", 994 xfer->pipe->device->address, 995 xfer->pipe->endpoint->edesc->bEndpointAddress, 996 sbuf)); 997 if (ehcidebug > 2) { 998 ehci_dump_sqh(epipe->sqh); 999 ehci_dump_sqtds(ex->sqtdstart); 1000 } 1001 #endif 1002 /* low&full speed has an extra error flag */ 1003 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1004 EHCI_QH_SPEED_HIGH) 1005 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1006 else 1007 status &= EHCI_QTD_STATERRS; 1008 if (status == 0) /* no other errors means a stall */ { 1009 xfer->status = USBD_STALLED; 1010 } else { 1011 xfer->status = USBD_IOERROR; /* more info XXX */ 1012 } 1013 /* XXX need to reset TT on missed microframe */ 1014 if (status & EHCI_QTD_MISSEDMICRO) { 1015 ehci_softc_t *sc = 1016 xfer->pipe->device->bus->hci_private; 1017 1018 printf("%s: missed microframe, TT reset not " 1019 "implemented, hub might be inoperational\n", 1020 device_xname(sc->sc_dev)); 1021 } 1022 } else { 1023 xfer->status = USBD_NORMAL_COMPLETION; 1024 } 1025 1026 end: 1027 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1028 * during this call, before methods->done is called: dma sync required 1029 * beforehand? */ 1030 usb_transfer_complete(xfer); 1031 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1032 } 1033 1034 /* 1035 * Wait here until controller claims to have an interrupt. 1036 * Then call ehci_intr and return. Use timeout to avoid waiting 1037 * too long. 1038 */ 1039 void 1040 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1041 { 1042 int timo; 1043 u_int32_t intrs; 1044 1045 xfer->status = USBD_IN_PROGRESS; 1046 for (timo = xfer->timeout; timo >= 0; timo--) { 1047 usb_delay_ms(&sc->sc_bus, 1); 1048 if (sc->sc_dying) 1049 break; 1050 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1051 sc->sc_eintrs; 1052 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1053 #ifdef EHCI_DEBUG 1054 if (ehcidebug > 15) 1055 ehci_dump_regs(sc); 1056 #endif 1057 if (intrs) { 1058 ehci_intr1(sc); 1059 if (xfer->status != USBD_IN_PROGRESS) 1060 return; 1061 } 1062 } 1063 1064 /* Timeout */ 1065 DPRINTF(("ehci_waitintr: timeout\n")); 1066 xfer->status = USBD_TIMEOUT; 1067 usb_transfer_complete(xfer); 1068 /* XXX should free TD */ 1069 } 1070 1071 void 1072 ehci_poll(struct usbd_bus *bus) 1073 { 1074 ehci_softc_t *sc = bus->hci_private; 1075 #ifdef EHCI_DEBUG 1076 static int last; 1077 int new; 1078 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1079 if (new != last) { 1080 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1081 last = new; 1082 } 1083 #endif 1084 1085 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1086 ehci_intr1(sc); 1087 } 1088 1089 void 1090 ehci_childdet(device_t self, device_t child) 1091 { 1092 struct ehci_softc *sc = device_private(self); 1093 1094 KASSERT(sc->sc_child == child); 1095 sc->sc_child = NULL; 1096 } 1097 1098 int 1099 ehci_detach(struct ehci_softc *sc, int flags) 1100 { 1101 int rv = 0; 1102 1103 if (sc->sc_child != NULL) 1104 rv = config_detach(sc->sc_child, flags); 1105 1106 if (rv != 0) 1107 return (rv); 1108 1109 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 1110 1111 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1112 1113 /* XXX free other data structures XXX */ 1114 mutex_destroy(&sc->sc_doorbell_lock); 1115 1116 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1117 1118 return (rv); 1119 } 1120 1121 1122 int 1123 ehci_activate(device_t self, enum devact act) 1124 { 1125 struct ehci_softc *sc = device_private(self); 1126 int rv = 0; 1127 1128 switch (act) { 1129 case DVACT_ACTIVATE: 1130 return (EOPNOTSUPP); 1131 1132 case DVACT_DEACTIVATE: 1133 sc->sc_dying = 1; 1134 if (sc->sc_child != NULL) 1135 rv = config_deactivate(sc->sc_child); 1136 break; 1137 } 1138 return (rv); 1139 } 1140 1141 /* 1142 * Handle suspend/resume. 1143 * 1144 * We need to switch to polling mode here, because this routine is 1145 * called from an interrupt context. This is all right since we 1146 * are almost suspended anyway. 1147 * 1148 * Note that this power handler isn't to be registered directly; the 1149 * bus glue needs to call out to it. 1150 */ 1151 bool 1152 ehci_suspend(device_t dv PMF_FN_ARGS) 1153 { 1154 ehci_softc_t *sc = device_private(dv); 1155 int i, s; 1156 uint32_t cmd, hcr; 1157 1158 s = splhardusb(); 1159 1160 sc->sc_bus.use_polling++; 1161 1162 for (i = 1; i <= sc->sc_noport; i++) { 1163 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1164 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1165 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1166 } 1167 1168 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1169 1170 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1171 EOWRITE4(sc, EHCI_USBCMD, cmd); 1172 1173 for (i = 0; i < 100; i++) { 1174 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1175 if (hcr == 0) 1176 break; 1177 1178 usb_delay_ms(&sc->sc_bus, 1); 1179 } 1180 if (hcr != 0) 1181 printf("%s: reset timeout\n", device_xname(dv)); 1182 1183 cmd &= ~EHCI_CMD_RS; 1184 EOWRITE4(sc, EHCI_USBCMD, cmd); 1185 1186 for (i = 0; i < 100; i++) { 1187 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1188 if (hcr == EHCI_STS_HCH) 1189 break; 1190 1191 usb_delay_ms(&sc->sc_bus, 1); 1192 } 1193 if (hcr != EHCI_STS_HCH) 1194 printf("%s: config timeout\n", device_xname(dv)); 1195 1196 sc->sc_bus.use_polling--; 1197 splx(s); 1198 1199 return true; 1200 } 1201 1202 bool 1203 ehci_resume(device_t dv PMF_FN_ARGS) 1204 { 1205 ehci_softc_t *sc = device_private(dv); 1206 int i; 1207 uint32_t cmd, hcr; 1208 1209 /* restore things in case the bios sucks */ 1210 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1211 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1212 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1213 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1214 1215 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1216 1217 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1218 1219 hcr = 0; 1220 for (i = 1; i <= sc->sc_noport; i++) { 1221 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1222 if ((cmd & EHCI_PS_PO) == 0 && 1223 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1224 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1225 hcr = 1; 1226 } 1227 } 1228 1229 if (hcr) { 1230 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1231 1232 for (i = 1; i <= sc->sc_noport; i++) { 1233 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1234 if ((cmd & EHCI_PS_PO) == 0 && 1235 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1236 EOWRITE4(sc, EHCI_PORTSC(i), 1237 cmd & ~EHCI_PS_FPR); 1238 } 1239 } 1240 1241 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1242 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1243 1244 for (i = 0; i < 100; i++) { 1245 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1246 if (hcr != EHCI_STS_HCH) 1247 break; 1248 1249 usb_delay_ms(&sc->sc_bus, 1); 1250 } 1251 if (hcr == EHCI_STS_HCH) 1252 printf("%s: config timeout\n", device_xname(dv)); 1253 1254 return true; 1255 } 1256 1257 /* 1258 * Shut down the controller when the system is going down. 1259 */ 1260 bool 1261 ehci_shutdown(device_t self, int flags) 1262 { 1263 ehci_softc_t *sc = device_private(self); 1264 1265 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1266 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1267 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1268 return true; 1269 } 1270 1271 usbd_status 1272 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1273 { 1274 struct ehci_softc *sc = bus->hci_private; 1275 usbd_status err; 1276 1277 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1278 if (err == USBD_NOMEM) 1279 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1280 #ifdef EHCI_DEBUG 1281 if (err) 1282 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1283 #endif 1284 return (err); 1285 } 1286 1287 void 1288 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1289 { 1290 struct ehci_softc *sc = bus->hci_private; 1291 1292 if (dma->block->flags & USB_DMA_RESERVE) { 1293 usb_reserve_freem(&sc->sc_dma_reserve, 1294 dma); 1295 return; 1296 } 1297 usb_freemem(&sc->sc_bus, dma); 1298 } 1299 1300 usbd_xfer_handle 1301 ehci_allocx(struct usbd_bus *bus) 1302 { 1303 struct ehci_softc *sc = bus->hci_private; 1304 usbd_xfer_handle xfer; 1305 1306 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1307 if (xfer != NULL) { 1308 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1309 #ifdef DIAGNOSTIC 1310 if (xfer->busy_free != XFER_FREE) { 1311 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1312 xfer->busy_free); 1313 } 1314 #endif 1315 } else { 1316 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1317 } 1318 if (xfer != NULL) { 1319 memset(xfer, 0, sizeof(struct ehci_xfer)); 1320 #ifdef DIAGNOSTIC 1321 EXFER(xfer)->isdone = 1; 1322 xfer->busy_free = XFER_BUSY; 1323 #endif 1324 } 1325 return (xfer); 1326 } 1327 1328 void 1329 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1330 { 1331 struct ehci_softc *sc = bus->hci_private; 1332 1333 #ifdef DIAGNOSTIC 1334 if (xfer->busy_free != XFER_BUSY) { 1335 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1336 xfer->busy_free); 1337 } 1338 xfer->busy_free = XFER_FREE; 1339 if (!EXFER(xfer)->isdone) { 1340 printf("ehci_freex: !isdone\n"); 1341 } 1342 #endif 1343 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1344 } 1345 1346 Static void 1347 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1348 { 1349 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1350 1351 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1352 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1353 #ifdef USB_DEBUG 1354 if (ehcidebug) 1355 usbd_dump_pipe(pipe); 1356 #endif 1357 epipe->nexttoggle = 0; 1358 } 1359 1360 Static void 1361 ehci_noop(usbd_pipe_handle pipe) 1362 { 1363 } 1364 1365 #ifdef EHCI_DEBUG 1366 void 1367 ehci_dump_regs(ehci_softc_t *sc) 1368 { 1369 int i; 1370 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1371 EOREAD4(sc, EHCI_USBCMD), 1372 EOREAD4(sc, EHCI_USBSTS), 1373 EOREAD4(sc, EHCI_USBINTR)); 1374 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1375 EOREAD4(sc, EHCI_FRINDEX), 1376 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1377 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1378 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1379 for (i = 1; i <= sc->sc_noport; i++) 1380 printf("port %d status=0x%08x\n", i, 1381 EOREAD4(sc, EHCI_PORTSC(i))); 1382 } 1383 1384 /* 1385 * Unused function - this is meant to be called from a kernel 1386 * debugger. 1387 */ 1388 void 1389 ehci_dump() 1390 { 1391 ehci_dump_regs(theehci); 1392 } 1393 1394 void 1395 ehci_dump_link(ehci_link_t link, int type) 1396 { 1397 link = le32toh(link); 1398 printf("0x%08x", link); 1399 if (link & EHCI_LINK_TERMINATE) 1400 printf("<T>"); 1401 else { 1402 printf("<"); 1403 if (type) { 1404 switch (EHCI_LINK_TYPE(link)) { 1405 case EHCI_LINK_ITD: printf("ITD"); break; 1406 case EHCI_LINK_QH: printf("QH"); break; 1407 case EHCI_LINK_SITD: printf("SITD"); break; 1408 case EHCI_LINK_FSTN: printf("FSTN"); break; 1409 } 1410 } 1411 printf(">"); 1412 } 1413 } 1414 1415 void 1416 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1417 { 1418 int i; 1419 u_int32_t stop; 1420 1421 stop = 0; 1422 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1423 ehci_dump_sqtd(sqtd); 1424 usb_syncmem(&sqtd->dma, 1425 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1426 sizeof(sqtd->qtd), 1427 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1428 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1429 usb_syncmem(&sqtd->dma, 1430 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1431 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1432 } 1433 if (sqtd) 1434 printf("dump aborted, too many TDs\n"); 1435 } 1436 1437 void 1438 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1439 { 1440 usb_syncmem(&sqtd->dma, sqtd->offs, 1441 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1442 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1443 ehci_dump_qtd(&sqtd->qtd); 1444 usb_syncmem(&sqtd->dma, sqtd->offs, 1445 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1446 } 1447 1448 void 1449 ehci_dump_qtd(ehci_qtd_t *qtd) 1450 { 1451 u_int32_t s; 1452 char sbuf[128]; 1453 1454 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1455 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1456 printf("\n"); 1457 s = le32toh(qtd->qtd_status); 1458 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1459 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1460 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1461 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1462 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1463 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1464 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1465 EHCI_QTD_GET_PID(s), sbuf); 1466 for (s = 0; s < 5; s++) 1467 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1468 } 1469 1470 void 1471 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1472 { 1473 ehci_qh_t *qh = &sqh->qh; 1474 u_int32_t endp, endphub; 1475 1476 usb_syncmem(&sqh->dma, sqh->offs, 1477 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1478 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1479 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1480 endp = le32toh(qh->qh_endp); 1481 printf(" endp=0x%08x\n", endp); 1482 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1483 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1484 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1485 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1486 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1487 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1488 EHCI_QH_GET_NRL(endp)); 1489 endphub = le32toh(qh->qh_endphub); 1490 printf(" endphub=0x%08x\n", endphub); 1491 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1492 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1493 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1494 EHCI_QH_GET_MULT(endphub)); 1495 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1496 printf("Overlay qTD:\n"); 1497 ehci_dump_qtd(&qh->qh_qtd); 1498 usb_syncmem(&sqh->dma, sqh->offs, 1499 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1500 } 1501 1502 #if notyet 1503 void 1504 ehci_dump_itd(struct ehci_soft_itd *itd) 1505 { 1506 ehci_isoc_trans_t t; 1507 ehci_isoc_bufr_ptr_t b, b2, b3; 1508 int i; 1509 1510 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1511 1512 for (i = 0; i < 8;i++) { 1513 t = le32toh(itd->itd.itd_ctl[i]); 1514 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1515 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1516 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1517 EHCI_ITD_GET_OFFS(t)); 1518 } 1519 printf("ITDbufr: "); 1520 for (i = 0; i < 7; i++) 1521 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1522 1523 b = le32toh(itd->itd.itd_bufr[0]); 1524 b2 = le32toh(itd->itd.itd_bufr[1]); 1525 b3 = le32toh(itd->itd.itd_bufr[2]); 1526 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1527 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1528 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1529 } 1530 1531 void 1532 ehci_dump_sitd(struct ehci_soft_itd *itd) 1533 { 1534 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1535 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1536 itd->xfer_next, itd->physaddr, itd->slot); 1537 } 1538 #endif 1539 1540 #ifdef DIAGNOSTIC 1541 void 1542 ehci_dump_exfer(struct ehci_xfer *ex) 1543 { 1544 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1545 } 1546 #endif 1547 1548 #endif 1549 1550 usbd_status 1551 ehci_open(usbd_pipe_handle pipe) 1552 { 1553 usbd_device_handle dev = pipe->device; 1554 ehci_softc_t *sc = dev->bus->hci_private; 1555 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1556 u_int8_t addr = dev->address; 1557 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1558 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1559 ehci_soft_qh_t *sqh; 1560 usbd_status err; 1561 int s; 1562 int ival, speed, naks; 1563 int hshubaddr, hshubport; 1564 1565 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1566 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1567 1568 if (dev->myhsport) { 1569 hshubaddr = dev->myhsport->parent->address; 1570 hshubport = dev->myhsport->portno; 1571 } else { 1572 hshubaddr = 0; 1573 hshubport = 0; 1574 } 1575 1576 if (sc->sc_dying) 1577 return (USBD_IOERROR); 1578 1579 epipe->nexttoggle = 0; 1580 1581 if (addr == sc->sc_addr) { 1582 switch (ed->bEndpointAddress) { 1583 case USB_CONTROL_ENDPOINT: 1584 pipe->methods = &ehci_root_ctrl_methods; 1585 break; 1586 case UE_DIR_IN | EHCI_INTR_ENDPT: 1587 pipe->methods = &ehci_root_intr_methods; 1588 break; 1589 default: 1590 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1591 ed->bEndpointAddress)); 1592 return (USBD_INVAL); 1593 } 1594 return (USBD_NORMAL_COMPLETION); 1595 } 1596 1597 /* XXX All this stuff is only valid for async. */ 1598 switch (dev->speed) { 1599 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1600 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1601 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1602 default: panic("ehci_open: bad device speed %d", dev->speed); 1603 } 1604 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1605 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1606 "isoc endpoint.\n"); 1607 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1608 "attached to a USB2 hub, and transaction translations are " 1609 "not yet supported.\n"); 1610 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1611 "root hub instead.\n"); 1612 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1613 hshubaddr, hshubport)); 1614 return USBD_INVAL; 1615 } 1616 1617 naks = 8; /* XXX */ 1618 1619 /* Allocate sqh for everything, save isoc xfers */ 1620 if (xfertype != UE_ISOCHRONOUS) { 1621 sqh = ehci_alloc_sqh(sc); 1622 if (sqh == NULL) 1623 return (USBD_NOMEM); 1624 /* qh_link filled when the QH is added */ 1625 sqh->qh.qh_endp = htole32( 1626 EHCI_QH_SET_ADDR(addr) | 1627 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1628 EHCI_QH_SET_EPS(speed) | 1629 EHCI_QH_DTC | 1630 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1631 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1632 EHCI_QH_CTL : 0) | 1633 EHCI_QH_SET_NRL(naks) 1634 ); 1635 sqh->qh.qh_endphub = htole32( 1636 EHCI_QH_SET_MULT(1) | 1637 EHCI_QH_SET_HUBA(hshubaddr) | 1638 EHCI_QH_SET_PORT(hshubport) | 1639 EHCI_QH_SET_CMASK(0x08) | /* XXX */ 1640 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1641 ); 1642 sqh->qh.qh_curqtd = EHCI_NULL; 1643 /* Fill the overlay qTD */ 1644 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1645 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1646 sqh->qh.qh_qtd.qtd_status = htole32(0); 1647 1648 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1649 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1650 epipe->sqh = sqh; 1651 } else { 1652 sqh = NULL; 1653 } /*xfertype == UE_ISOC*/ 1654 1655 switch (xfertype) { 1656 case UE_CONTROL: 1657 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1658 0, &epipe->u.ctl.reqdma); 1659 #ifdef EHCI_DEBUG 1660 if (err) 1661 printf("ehci_open: usb_allocmem()=%d\n", err); 1662 #endif 1663 if (err) 1664 goto bad; 1665 pipe->methods = &ehci_device_ctrl_methods; 1666 s = splusb(); 1667 ehci_add_qh(sqh, sc->sc_async_head); 1668 splx(s); 1669 break; 1670 case UE_BULK: 1671 pipe->methods = &ehci_device_bulk_methods; 1672 s = splusb(); 1673 ehci_add_qh(sqh, sc->sc_async_head); 1674 splx(s); 1675 break; 1676 case UE_INTERRUPT: 1677 pipe->methods = &ehci_device_intr_methods; 1678 ival = pipe->interval; 1679 if (ival == USBD_DEFAULT_INTERVAL) { 1680 if (speed == EHCI_QH_SPEED_HIGH) { 1681 if (ed->bInterval > 16) { 1682 /* 1683 * illegal with high-speed, but there 1684 * were documentation bugs in the spec, 1685 * so be generous 1686 */ 1687 ival = 256; 1688 } else 1689 ival = (1 << (ed->bInterval - 1)) / 8; 1690 } else 1691 ival = ed->bInterval; 1692 } 1693 err = ehci_device_setintr(sc, sqh, ival); 1694 if (err) 1695 goto bad; 1696 break; 1697 case UE_ISOCHRONOUS: 1698 pipe->methods = &ehci_device_isoc_methods; 1699 if (ed->bInterval == 0 || ed->bInterval > 16) { 1700 printf("ehci: opening pipe with invalid bInterval\n"); 1701 err = USBD_INVAL; 1702 goto bad; 1703 } 1704 if (UGETW(ed->wMaxPacketSize) == 0) { 1705 printf("ehci: zero length endpoint open request\n"); 1706 err = USBD_INVAL; 1707 goto bad; 1708 } 1709 epipe->u.isoc.next_frame = 0; 1710 epipe->u.isoc.cur_xfers = 0; 1711 break; 1712 default: 1713 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1714 err = USBD_INVAL; 1715 goto bad; 1716 } 1717 return (USBD_NORMAL_COMPLETION); 1718 1719 bad: 1720 if (sqh != NULL) 1721 ehci_free_sqh(sc, sqh); 1722 return (err); 1723 } 1724 1725 /* 1726 * Add an ED to the schedule. Called at splusb(). 1727 */ 1728 void 1729 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1730 { 1731 SPLUSBCHECK; 1732 1733 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1734 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1735 sqh->next = head->next; 1736 sqh->qh.qh_link = head->qh.qh_link; 1737 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1738 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1739 head->next = sqh; 1740 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1741 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1742 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1743 1744 #ifdef EHCI_DEBUG 1745 if (ehcidebug > 5) { 1746 printf("ehci_add_qh:\n"); 1747 ehci_dump_sqh(sqh); 1748 } 1749 #endif 1750 } 1751 1752 /* 1753 * Remove an ED from the schedule. Called at splusb(). 1754 */ 1755 void 1756 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1757 { 1758 ehci_soft_qh_t *p; 1759 1760 SPLUSBCHECK; 1761 /* XXX */ 1762 for (p = head; p != NULL && p->next != sqh; p = p->next) 1763 ; 1764 if (p == NULL) 1765 panic("ehci_rem_qh: ED not found"); 1766 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1767 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1768 p->next = sqh->next; 1769 p->qh.qh_link = sqh->qh.qh_link; 1770 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1771 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1772 1773 ehci_sync_hc(sc); 1774 } 1775 1776 void 1777 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1778 { 1779 int i; 1780 u_int32_t status; 1781 1782 /* Save toggle bit and ping status. */ 1783 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1784 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1785 status = sqh->qh.qh_qtd.qtd_status & 1786 htole32(EHCI_QTD_TOGGLE_MASK | 1787 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1788 /* Set HALTED to make hw leave it alone. */ 1789 sqh->qh.qh_qtd.qtd_status = 1790 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1791 usb_syncmem(&sqh->dma, 1792 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1793 sizeof(sqh->qh.qh_qtd.qtd_status), 1794 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1795 sqh->qh.qh_curqtd = 0; 1796 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1797 sqh->qh.qh_qtd.qtd_altnext = 0; 1798 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1799 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1800 sqh->sqtd = sqtd; 1801 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1802 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1803 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1804 sqh->qh.qh_qtd.qtd_status = status; 1805 usb_syncmem(&sqh->dma, 1806 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1807 sizeof(sqh->qh.qh_qtd.qtd_status), 1808 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1809 } 1810 1811 /* 1812 * Ensure that the HC has released all references to the QH. We do this 1813 * by asking for a Async Advance Doorbell interrupt and then we wait for 1814 * the interrupt. 1815 * To make this easier we first obtain exclusive use of the doorbell. 1816 */ 1817 void 1818 ehci_sync_hc(ehci_softc_t *sc) 1819 { 1820 int s, error; 1821 1822 if (sc->sc_dying) { 1823 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1824 return; 1825 } 1826 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1827 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */ 1828 s = splhardusb(); 1829 /* ask for doorbell */ 1830 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1831 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1832 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1833 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1834 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1835 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1836 splx(s); 1837 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */ 1838 #ifdef DIAGNOSTIC 1839 if (error) 1840 printf("ehci_sync_hc: tsleep() = %d\n", error); 1841 #endif 1842 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1843 } 1844 1845 /*Call at splusb*/ 1846 void 1847 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1848 { 1849 struct ehci_soft_itd *itd, *prev; 1850 1851 prev = NULL; 1852 1853 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1854 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1855 1856 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1857 prev = itd->u.frame_list.prev; 1858 /* Unlink itd from hardware chain, or frame array */ 1859 if (prev == NULL) { /* We're at the table head */ 1860 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1861 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1862 usb_syncmem(&sc->sc_fldma, 1863 sizeof(ehci_link_t) * itd->slot, 1864 sizeof(ehci_link_t), 1865 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1866 1867 if (itd->u.frame_list.next != NULL) 1868 itd->u.frame_list.next->u.frame_list.prev = NULL; 1869 } else { 1870 /* XXX this part is untested... */ 1871 prev->itd.itd_next = itd->itd.itd_next; 1872 usb_syncmem(&itd->dma, 1873 itd->offs + offsetof(ehci_itd_t, itd_next), 1874 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1875 1876 prev->u.frame_list.next = itd->u.frame_list.next; 1877 if (itd->u.frame_list.next != NULL) 1878 itd->u.frame_list.next->u.frame_list.prev = prev; 1879 } 1880 } 1881 1882 prev = NULL; 1883 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1884 if (prev != NULL) 1885 ehci_free_itd(sc, prev); 1886 prev = itd; 1887 } 1888 if (prev) 1889 ehci_free_itd(sc, prev); 1890 exfer->itdstart = NULL; 1891 exfer->itdend = NULL; 1892 } 1893 1894 /***********/ 1895 1896 /* 1897 * Data structures and routines to emulate the root hub. 1898 */ 1899 Static usb_device_descriptor_t ehci_devd = { 1900 USB_DEVICE_DESCRIPTOR_SIZE, 1901 UDESC_DEVICE, /* type */ 1902 {0x00, 0x02}, /* USB version */ 1903 UDCLASS_HUB, /* class */ 1904 UDSUBCLASS_HUB, /* subclass */ 1905 UDPROTO_HSHUBSTT, /* protocol */ 1906 64, /* max packet */ 1907 {0},{0},{0x00,0x01}, /* device id */ 1908 1,2,0, /* string indicies */ 1909 1 /* # of configurations */ 1910 }; 1911 1912 Static const usb_device_qualifier_t ehci_odevd = { 1913 USB_DEVICE_DESCRIPTOR_SIZE, 1914 UDESC_DEVICE_QUALIFIER, /* type */ 1915 {0x00, 0x02}, /* USB version */ 1916 UDCLASS_HUB, /* class */ 1917 UDSUBCLASS_HUB, /* subclass */ 1918 UDPROTO_FSHUB, /* protocol */ 1919 64, /* max packet */ 1920 1, /* # of configurations */ 1921 0 1922 }; 1923 1924 Static const usb_config_descriptor_t ehci_confd = { 1925 USB_CONFIG_DESCRIPTOR_SIZE, 1926 UDESC_CONFIG, 1927 {USB_CONFIG_DESCRIPTOR_SIZE + 1928 USB_INTERFACE_DESCRIPTOR_SIZE + 1929 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1930 1, 1931 1, 1932 0, 1933 UC_ATTR_MBO | UC_SELF_POWERED, 1934 0 /* max power */ 1935 }; 1936 1937 Static const usb_interface_descriptor_t ehci_ifcd = { 1938 USB_INTERFACE_DESCRIPTOR_SIZE, 1939 UDESC_INTERFACE, 1940 0, 1941 0, 1942 1, 1943 UICLASS_HUB, 1944 UISUBCLASS_HUB, 1945 UIPROTO_HSHUBSTT, 1946 0 1947 }; 1948 1949 Static const usb_endpoint_descriptor_t ehci_endpd = { 1950 USB_ENDPOINT_DESCRIPTOR_SIZE, 1951 UDESC_ENDPOINT, 1952 UE_DIR_IN | EHCI_INTR_ENDPT, 1953 UE_INTERRUPT, 1954 {8, 0}, /* max packet */ 1955 12 1956 }; 1957 1958 Static const usb_hub_descriptor_t ehci_hubd = { 1959 USB_HUB_DESCRIPTOR_SIZE, 1960 UDESC_HUB, 1961 0, 1962 {0,0}, 1963 0, 1964 0, 1965 {""}, 1966 {""}, 1967 }; 1968 1969 /* 1970 * Simulate a hardware hub by handling all the necessary requests. 1971 */ 1972 Static usbd_status 1973 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1974 { 1975 usbd_status err; 1976 1977 /* Insert last in queue. */ 1978 err = usb_insert_transfer(xfer); 1979 if (err) 1980 return (err); 1981 1982 /* Pipe isn't running, start first */ 1983 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1984 } 1985 1986 Static usbd_status 1987 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1988 { 1989 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1990 usb_device_request_t *req; 1991 void *buf = NULL; 1992 int port, i; 1993 int s, len, value, index, l, totlen = 0; 1994 usb_port_status_t ps; 1995 usb_hub_descriptor_t hubd; 1996 usbd_status err; 1997 u_int32_t v; 1998 1999 if (sc->sc_dying) 2000 return (USBD_IOERROR); 2001 2002 #ifdef DIAGNOSTIC 2003 if (!(xfer->rqflags & URQ_REQUEST)) 2004 /* XXX panic */ 2005 return (USBD_INVAL); 2006 #endif 2007 req = &xfer->request; 2008 2009 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2010 req->bmRequestType, req->bRequest)); 2011 2012 len = UGETW(req->wLength); 2013 value = UGETW(req->wValue); 2014 index = UGETW(req->wIndex); 2015 2016 if (len != 0) 2017 buf = KERNADDR(&xfer->dmabuf, 0); 2018 2019 #define C(x,y) ((x) | ((y) << 8)) 2020 switch(C(req->bRequest, req->bmRequestType)) { 2021 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2022 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2023 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2024 /* 2025 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2026 * for the integrated root hub. 2027 */ 2028 break; 2029 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2030 if (len > 0) { 2031 *(u_int8_t *)buf = sc->sc_conf; 2032 totlen = 1; 2033 } 2034 break; 2035 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2036 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2037 if (len == 0) 2038 break; 2039 switch(value >> 8) { 2040 case UDESC_DEVICE: 2041 if ((value & 0xff) != 0) { 2042 err = USBD_IOERROR; 2043 goto ret; 2044 } 2045 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2046 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2047 memcpy(buf, &ehci_devd, l); 2048 break; 2049 /* 2050 * We can't really operate at another speed, but the spec says 2051 * we need this descriptor. 2052 */ 2053 case UDESC_DEVICE_QUALIFIER: 2054 if ((value & 0xff) != 0) { 2055 err = USBD_IOERROR; 2056 goto ret; 2057 } 2058 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2059 memcpy(buf, &ehci_odevd, l); 2060 break; 2061 /* 2062 * We can't really operate at another speed, but the spec says 2063 * we need this descriptor. 2064 */ 2065 case UDESC_OTHER_SPEED_CONFIGURATION: 2066 case UDESC_CONFIG: 2067 if ((value & 0xff) != 0) { 2068 err = USBD_IOERROR; 2069 goto ret; 2070 } 2071 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2072 memcpy(buf, &ehci_confd, l); 2073 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2074 value >> 8; 2075 buf = (char *)buf + l; 2076 len -= l; 2077 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2078 totlen += l; 2079 memcpy(buf, &ehci_ifcd, l); 2080 buf = (char *)buf + l; 2081 len -= l; 2082 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2083 totlen += l; 2084 memcpy(buf, &ehci_endpd, l); 2085 break; 2086 case UDESC_STRING: 2087 #define sd ((usb_string_descriptor_t *)buf) 2088 switch (value & 0xff) { 2089 case 0: /* Language table */ 2090 totlen = usb_makelangtbl(sd, len); 2091 break; 2092 case 1: /* Vendor */ 2093 totlen = usb_makestrdesc(sd, len, 2094 sc->sc_vendor); 2095 break; 2096 case 2: /* Product */ 2097 totlen = usb_makestrdesc(sd, len, 2098 "EHCI root hub"); 2099 break; 2100 } 2101 #undef sd 2102 break; 2103 default: 2104 err = USBD_IOERROR; 2105 goto ret; 2106 } 2107 break; 2108 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2109 if (len > 0) { 2110 *(u_int8_t *)buf = 0; 2111 totlen = 1; 2112 } 2113 break; 2114 case C(UR_GET_STATUS, UT_READ_DEVICE): 2115 if (len > 1) { 2116 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2117 totlen = 2; 2118 } 2119 break; 2120 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2121 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2122 if (len > 1) { 2123 USETW(((usb_status_t *)buf)->wStatus, 0); 2124 totlen = 2; 2125 } 2126 break; 2127 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2128 if (value >= USB_MAX_DEVICES) { 2129 err = USBD_IOERROR; 2130 goto ret; 2131 } 2132 sc->sc_addr = value; 2133 break; 2134 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2135 if (value != 0 && value != 1) { 2136 err = USBD_IOERROR; 2137 goto ret; 2138 } 2139 sc->sc_conf = value; 2140 break; 2141 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2142 break; 2143 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2144 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2145 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2146 err = USBD_IOERROR; 2147 goto ret; 2148 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2149 break; 2150 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2151 break; 2152 /* Hub requests */ 2153 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2154 break; 2155 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2156 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2157 "port=%d feature=%d\n", 2158 index, value)); 2159 if (index < 1 || index > sc->sc_noport) { 2160 err = USBD_IOERROR; 2161 goto ret; 2162 } 2163 port = EHCI_PORTSC(index); 2164 v = EOREAD4(sc, port); 2165 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2166 v &= ~EHCI_PS_CLEAR; 2167 switch(value) { 2168 case UHF_PORT_ENABLE: 2169 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2170 break; 2171 case UHF_PORT_SUSPEND: 2172 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2173 break; 2174 v &= ~EHCI_PS_SUSP; 2175 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2176 /* see USB2 spec ch. 7.1.7.7 */ 2177 usb_delay_ms(&sc->sc_bus, 20); 2178 EOWRITE4(sc, port, v); 2179 usb_delay_ms(&sc->sc_bus, 2); 2180 #ifdef DEBUG 2181 v = EOREAD4(sc, port); 2182 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2183 printf("ehci: resume failed: %x\n", v); 2184 #endif 2185 break; 2186 case UHF_PORT_POWER: 2187 if (sc->sc_hasppc) 2188 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2189 break; 2190 case UHF_PORT_TEST: 2191 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2192 "%d\n", index)); 2193 break; 2194 case UHF_PORT_INDICATOR: 2195 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2196 "%d\n", index)); 2197 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2198 break; 2199 case UHF_C_PORT_CONNECTION: 2200 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2201 break; 2202 case UHF_C_PORT_ENABLE: 2203 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2204 break; 2205 case UHF_C_PORT_SUSPEND: 2206 /* how? */ 2207 break; 2208 case UHF_C_PORT_OVER_CURRENT: 2209 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2210 break; 2211 case UHF_C_PORT_RESET: 2212 sc->sc_isreset[index] = 0; 2213 break; 2214 default: 2215 err = USBD_IOERROR; 2216 goto ret; 2217 } 2218 #if 0 2219 switch(value) { 2220 case UHF_C_PORT_CONNECTION: 2221 case UHF_C_PORT_ENABLE: 2222 case UHF_C_PORT_SUSPEND: 2223 case UHF_C_PORT_OVER_CURRENT: 2224 case UHF_C_PORT_RESET: 2225 default: 2226 break; 2227 } 2228 #endif 2229 break; 2230 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2231 if (len == 0) 2232 break; 2233 if ((value & 0xff) != 0) { 2234 err = USBD_IOERROR; 2235 goto ret; 2236 } 2237 hubd = ehci_hubd; 2238 hubd.bNbrPorts = sc->sc_noport; 2239 v = EOREAD4(sc, EHCI_HCSPARAMS); 2240 USETW(hubd.wHubCharacteristics, 2241 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2242 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2243 ? UHD_PORT_IND : 0); 2244 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2245 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2246 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2247 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2248 l = min(len, hubd.bDescLength); 2249 totlen = l; 2250 memcpy(buf, &hubd, l); 2251 break; 2252 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2253 if (len != 4) { 2254 err = USBD_IOERROR; 2255 goto ret; 2256 } 2257 memset(buf, 0, len); /* ? XXX */ 2258 totlen = len; 2259 break; 2260 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2261 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2262 index)); 2263 if (index < 1 || index > sc->sc_noport) { 2264 err = USBD_IOERROR; 2265 goto ret; 2266 } 2267 if (len != 4) { 2268 err = USBD_IOERROR; 2269 goto ret; 2270 } 2271 v = EOREAD4(sc, EHCI_PORTSC(index)); 2272 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2273 v)); 2274 i = UPS_HIGH_SPEED; 2275 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2276 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2277 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2278 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2279 if (v & EHCI_PS_PR) i |= UPS_RESET; 2280 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2281 USETW(ps.wPortStatus, i); 2282 i = 0; 2283 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2284 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2285 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2286 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2287 USETW(ps.wPortChange, i); 2288 l = min(len, sizeof ps); 2289 memcpy(buf, &ps, l); 2290 totlen = l; 2291 break; 2292 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2293 err = USBD_IOERROR; 2294 goto ret; 2295 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2296 break; 2297 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2298 if (index < 1 || index > sc->sc_noport) { 2299 err = USBD_IOERROR; 2300 goto ret; 2301 } 2302 port = EHCI_PORTSC(index); 2303 v = EOREAD4(sc, port); 2304 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2305 v &= ~EHCI_PS_CLEAR; 2306 switch(value) { 2307 case UHF_PORT_ENABLE: 2308 EOWRITE4(sc, port, v | EHCI_PS_PE); 2309 break; 2310 case UHF_PORT_SUSPEND: 2311 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2312 break; 2313 case UHF_PORT_RESET: 2314 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2315 index)); 2316 if (EHCI_PS_IS_LOWSPEED(v)) { 2317 /* Low speed device, give up ownership. */ 2318 ehci_disown(sc, index, 1); 2319 break; 2320 } 2321 /* Start reset sequence. */ 2322 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2323 EOWRITE4(sc, port, v | EHCI_PS_PR); 2324 /* Wait for reset to complete. */ 2325 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2326 if (sc->sc_dying) { 2327 err = USBD_IOERROR; 2328 goto ret; 2329 } 2330 /* Terminate reset sequence. */ 2331 EOWRITE4(sc, port, v); 2332 /* Wait for HC to complete reset. */ 2333 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2334 if (sc->sc_dying) { 2335 err = USBD_IOERROR; 2336 goto ret; 2337 } 2338 v = EOREAD4(sc, port); 2339 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2340 if (v & EHCI_PS_PR) { 2341 printf("%s: port reset timeout\n", 2342 device_xname(sc->sc_dev)); 2343 return (USBD_TIMEOUT); 2344 } 2345 if (!(v & EHCI_PS_PE)) { 2346 /* Not a high speed device, give up ownership.*/ 2347 ehci_disown(sc, index, 0); 2348 break; 2349 } 2350 sc->sc_isreset[index] = 1; 2351 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2352 index, v)); 2353 break; 2354 case UHF_PORT_POWER: 2355 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2356 "%d (has PPC = %d)\n", index, 2357 sc->sc_hasppc)); 2358 if (sc->sc_hasppc) 2359 EOWRITE4(sc, port, v | EHCI_PS_PP); 2360 break; 2361 case UHF_PORT_TEST: 2362 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2363 "%d\n", index)); 2364 break; 2365 case UHF_PORT_INDICATOR: 2366 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2367 "%d\n", index)); 2368 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2369 break; 2370 default: 2371 err = USBD_IOERROR; 2372 goto ret; 2373 } 2374 break; 2375 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2376 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2377 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2378 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2379 break; 2380 default: 2381 err = USBD_IOERROR; 2382 goto ret; 2383 } 2384 xfer->actlen = totlen; 2385 err = USBD_NORMAL_COMPLETION; 2386 ret: 2387 xfer->status = err; 2388 s = splusb(); 2389 usb_transfer_complete(xfer); 2390 splx(s); 2391 return (USBD_IN_PROGRESS); 2392 } 2393 2394 void 2395 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2396 { 2397 int port; 2398 u_int32_t v; 2399 2400 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2401 #ifdef DIAGNOSTIC 2402 if (sc->sc_npcomp != 0) { 2403 int i = (index-1) / sc->sc_npcomp; 2404 if (i >= sc->sc_ncomp) 2405 printf("%s: strange port\n", 2406 device_xname(sc->sc_dev)); 2407 else 2408 printf("%s: handing over %s speed device on " 2409 "port %d to %s\n", 2410 device_xname(sc->sc_dev), 2411 lowspeed ? "low" : "full", 2412 index, device_xname(sc->sc_comps[i])); 2413 } else { 2414 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2415 } 2416 #endif 2417 port = EHCI_PORTSC(index); 2418 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2419 EOWRITE4(sc, port, v | EHCI_PS_PO); 2420 } 2421 2422 /* Abort a root control request. */ 2423 Static void 2424 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2425 { 2426 /* Nothing to do, all transfers are synchronous. */ 2427 } 2428 2429 /* Close the root pipe. */ 2430 Static void 2431 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2432 { 2433 DPRINTF(("ehci_root_ctrl_close\n")); 2434 /* Nothing to do. */ 2435 } 2436 2437 void 2438 ehci_root_intr_done(usbd_xfer_handle xfer) 2439 { 2440 xfer->hcpriv = NULL; 2441 } 2442 2443 Static usbd_status 2444 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2445 { 2446 usbd_status err; 2447 2448 /* Insert last in queue. */ 2449 err = usb_insert_transfer(xfer); 2450 if (err) 2451 return (err); 2452 2453 /* Pipe isn't running, start first */ 2454 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2455 } 2456 2457 Static usbd_status 2458 ehci_root_intr_start(usbd_xfer_handle xfer) 2459 { 2460 usbd_pipe_handle pipe = xfer->pipe; 2461 ehci_softc_t *sc = pipe->device->bus->hci_private; 2462 2463 if (sc->sc_dying) 2464 return (USBD_IOERROR); 2465 2466 sc->sc_intrxfer = xfer; 2467 2468 return (USBD_IN_PROGRESS); 2469 } 2470 2471 /* Abort a root interrupt request. */ 2472 Static void 2473 ehci_root_intr_abort(usbd_xfer_handle xfer) 2474 { 2475 int s; 2476 2477 if (xfer->pipe->intrxfer == xfer) { 2478 DPRINTF(("ehci_root_intr_abort: remove\n")); 2479 xfer->pipe->intrxfer = NULL; 2480 } 2481 xfer->status = USBD_CANCELLED; 2482 s = splusb(); 2483 usb_transfer_complete(xfer); 2484 splx(s); 2485 } 2486 2487 /* Close the root pipe. */ 2488 Static void 2489 ehci_root_intr_close(usbd_pipe_handle pipe) 2490 { 2491 ehci_softc_t *sc = pipe->device->bus->hci_private; 2492 2493 DPRINTF(("ehci_root_intr_close\n")); 2494 2495 sc->sc_intrxfer = NULL; 2496 } 2497 2498 void 2499 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2500 { 2501 xfer->hcpriv = NULL; 2502 } 2503 2504 /************************/ 2505 2506 ehci_soft_qh_t * 2507 ehci_alloc_sqh(ehci_softc_t *sc) 2508 { 2509 ehci_soft_qh_t *sqh; 2510 usbd_status err; 2511 int i, offs; 2512 usb_dma_t dma; 2513 2514 if (sc->sc_freeqhs == NULL) { 2515 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2516 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2517 EHCI_PAGE_SIZE, &dma); 2518 #ifdef EHCI_DEBUG 2519 if (err) 2520 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2521 #endif 2522 if (err) 2523 return (NULL); 2524 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2525 offs = i * EHCI_SQH_SIZE; 2526 sqh = KERNADDR(&dma, offs); 2527 sqh->physaddr = DMAADDR(&dma, offs); 2528 sqh->dma = dma; 2529 sqh->offs = offs; 2530 sqh->next = sc->sc_freeqhs; 2531 sc->sc_freeqhs = sqh; 2532 } 2533 } 2534 sqh = sc->sc_freeqhs; 2535 sc->sc_freeqhs = sqh->next; 2536 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2537 sqh->next = NULL; 2538 return (sqh); 2539 } 2540 2541 void 2542 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2543 { 2544 sqh->next = sc->sc_freeqhs; 2545 sc->sc_freeqhs = sqh; 2546 } 2547 2548 ehci_soft_qtd_t * 2549 ehci_alloc_sqtd(ehci_softc_t *sc) 2550 { 2551 ehci_soft_qtd_t *sqtd; 2552 usbd_status err; 2553 int i, offs; 2554 usb_dma_t dma; 2555 int s; 2556 2557 if (sc->sc_freeqtds == NULL) { 2558 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2559 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2560 EHCI_PAGE_SIZE, &dma); 2561 #ifdef EHCI_DEBUG 2562 if (err) 2563 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2564 #endif 2565 if (err) 2566 return (NULL); 2567 s = splusb(); 2568 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2569 offs = i * EHCI_SQTD_SIZE; 2570 sqtd = KERNADDR(&dma, offs); 2571 sqtd->physaddr = DMAADDR(&dma, offs); 2572 sqtd->dma = dma; 2573 sqtd->offs = offs; 2574 sqtd->nextqtd = sc->sc_freeqtds; 2575 sc->sc_freeqtds = sqtd; 2576 } 2577 splx(s); 2578 } 2579 2580 s = splusb(); 2581 sqtd = sc->sc_freeqtds; 2582 sc->sc_freeqtds = sqtd->nextqtd; 2583 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2584 sqtd->nextqtd = NULL; 2585 sqtd->xfer = NULL; 2586 splx(s); 2587 2588 return (sqtd); 2589 } 2590 2591 void 2592 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2593 { 2594 int s; 2595 2596 s = splusb(); 2597 sqtd->nextqtd = sc->sc_freeqtds; 2598 sc->sc_freeqtds = sqtd; 2599 splx(s); 2600 } 2601 2602 usbd_status 2603 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2604 int alen, int rd, usbd_xfer_handle xfer, 2605 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2606 { 2607 ehci_soft_qtd_t *next, *cur; 2608 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2609 u_int32_t qtdstatus; 2610 int len, curlen, mps; 2611 int i, tog; 2612 usb_dma_t *dma = &xfer->dmabuf; 2613 u_int16_t flags = xfer->flags; 2614 2615 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2616 2617 len = alen; 2618 dataphys = DMAADDR(dma, 0); 2619 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2620 qtdstatus = EHCI_QTD_ACTIVE | 2621 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2622 EHCI_QTD_SET_CERR(3) 2623 /* IOC set below */ 2624 /* BYTES set below */ 2625 ; 2626 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2627 tog = epipe->nexttoggle; 2628 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2629 2630 cur = ehci_alloc_sqtd(sc); 2631 *sp = cur; 2632 if (cur == NULL) 2633 goto nomem; 2634 2635 usb_syncmem(dma, 0, alen, 2636 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2637 for (;;) { 2638 dataphyspage = EHCI_PAGE(dataphys); 2639 /* The EHCI hardware can handle at most 5 pages. */ 2640 if (dataphyslastpage - dataphyspage < 2641 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2642 /* we can handle it in this QTD */ 2643 curlen = len; 2644 } else { 2645 /* must use multiple TDs, fill as much as possible. */ 2646 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2647 EHCI_PAGE_OFFSET(dataphys); 2648 #ifdef DIAGNOSTIC 2649 if (curlen > len) { 2650 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2651 "len=0x%x offs=0x%x\n", curlen, len, 2652 EHCI_PAGE_OFFSET(dataphys)); 2653 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2654 dataphyslastpage, dataphyspage, 2655 dataphys); 2656 curlen = len; 2657 } 2658 #endif 2659 /* the length must be a multiple of the max size */ 2660 curlen -= curlen % mps; 2661 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2662 "curlen=%d\n", curlen)); 2663 #ifdef DIAGNOSTIC 2664 if (curlen == 0) 2665 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2666 #endif 2667 } 2668 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2669 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2670 dataphys, dataphyslastpage, 2671 len, curlen)); 2672 len -= curlen; 2673 2674 /* 2675 * Allocate another transfer if there's more data left, 2676 * or if force last short transfer flag is set and we're 2677 * allocating a multiple of the max packet size. 2678 */ 2679 if (len != 0 || 2680 ((curlen % mps) == 0 && !rd && curlen != 0 && 2681 (flags & USBD_FORCE_SHORT_XFER))) { 2682 next = ehci_alloc_sqtd(sc); 2683 if (next == NULL) 2684 goto nomem; 2685 nextphys = htole32(next->physaddr); 2686 } else { 2687 next = NULL; 2688 nextphys = EHCI_NULL; 2689 } 2690 2691 for (i = 0; i * EHCI_PAGE_SIZE < 2692 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2693 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2694 if (i != 0) /* use offset only in first buffer */ 2695 a = EHCI_PAGE(a); 2696 cur->qtd.qtd_buffer[i] = htole32(a); 2697 cur->qtd.qtd_buffer_hi[i] = 0; 2698 #ifdef DIAGNOSTIC 2699 if (i >= EHCI_QTD_NBUFFERS) { 2700 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2701 goto nomem; 2702 } 2703 #endif 2704 } 2705 cur->nextqtd = next; 2706 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2707 cur->qtd.qtd_status = 2708 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2709 cur->xfer = xfer; 2710 cur->len = curlen; 2711 2712 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2713 dataphys, dataphys + curlen)); 2714 /* adjust the toggle based on the number of packets in this 2715 qtd */ 2716 if (((curlen + mps - 1) / mps) & 1) { 2717 tog ^= 1; 2718 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2719 } 2720 if (next == NULL) 2721 break; 2722 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2723 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2724 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2725 dataphys += curlen; 2726 cur = next; 2727 } 2728 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2729 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2730 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2731 *ep = cur; 2732 epipe->nexttoggle = tog; 2733 2734 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2735 *sp, *ep)); 2736 2737 return (USBD_NORMAL_COMPLETION); 2738 2739 nomem: 2740 /* XXX free chain */ 2741 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2742 return (USBD_NOMEM); 2743 } 2744 2745 Static void 2746 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2747 ehci_soft_qtd_t *sqtdend) 2748 { 2749 ehci_soft_qtd_t *p; 2750 int i; 2751 2752 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2753 sqtd, sqtdend)); 2754 2755 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2756 p = sqtd->nextqtd; 2757 ehci_free_sqtd(sc, sqtd); 2758 } 2759 } 2760 2761 ehci_soft_itd_t * 2762 ehci_alloc_itd(ehci_softc_t *sc) 2763 { 2764 struct ehci_soft_itd *itd, *freeitd; 2765 usbd_status err; 2766 int i, s, offs, frindex, previndex; 2767 usb_dma_t dma; 2768 2769 s = splusb(); 2770 2771 /* Find an itd that wasn't freed this frame or last frame. This can 2772 * discard itds that were freed before frindex wrapped around 2773 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2774 * interrupt and fiddling with list when that happens */ 2775 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2776 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2777 2778 freeitd = NULL; 2779 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2780 if (itd == NULL) 2781 break; 2782 if (itd->slot != frindex && itd->slot != previndex) { 2783 freeitd = itd; 2784 break; 2785 } 2786 } 2787 2788 if (freeitd == NULL) { 2789 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2790 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2791 EHCI_PAGE_SIZE, &dma); 2792 2793 if (err) { 2794 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2795 return NULL; 2796 } 2797 2798 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2799 offs = i * EHCI_ITD_SIZE; 2800 itd = KERNADDR(&dma, offs); 2801 itd->physaddr = DMAADDR(&dma, offs); 2802 itd->dma = dma; 2803 itd->offs = offs; 2804 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2805 } 2806 freeitd = LIST_FIRST(&sc->sc_freeitds); 2807 } 2808 2809 itd = freeitd; 2810 LIST_REMOVE(itd, u.free_list); 2811 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2812 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2813 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2814 BUS_DMASYNC_PREREAD); 2815 2816 itd->u.frame_list.next = NULL; 2817 itd->u.frame_list.prev = NULL; 2818 itd->xfer_next = NULL; 2819 itd->slot = 0; 2820 splx(s); 2821 2822 return itd; 2823 } 2824 2825 void 2826 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2827 { 2828 int s; 2829 2830 s = splusb(); 2831 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2832 splx(s); 2833 } 2834 2835 2836 2837 /****************/ 2838 2839 /* 2840 * Close a reqular pipe. 2841 * Assumes that there are no pending transactions. 2842 */ 2843 void 2844 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2845 { 2846 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2847 ehci_softc_t *sc = pipe->device->bus->hci_private; 2848 ehci_soft_qh_t *sqh = epipe->sqh; 2849 int s; 2850 2851 s = splusb(); 2852 ehci_rem_qh(sc, sqh, head); 2853 splx(s); 2854 ehci_free_sqh(sc, epipe->sqh); 2855 } 2856 2857 /* 2858 * Abort a device request. 2859 * If this routine is called at splusb() it guarantees that the request 2860 * will be removed from the hardware scheduling and that the callback 2861 * for it will be called with USBD_CANCELLED status. 2862 * It's impossible to guarantee that the requested transfer will not 2863 * have happened since the hardware runs concurrently. 2864 * If the transaction has already happened we rely on the ordinary 2865 * interrupt processing to process it. 2866 * XXX This is most probably wrong. 2867 */ 2868 void 2869 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2870 { 2871 #define exfer EXFER(xfer) 2872 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2873 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2874 ehci_soft_qh_t *sqh = epipe->sqh; 2875 ehci_soft_qtd_t *sqtd; 2876 ehci_physaddr_t cur; 2877 u_int32_t qhstatus; 2878 int s; 2879 int hit; 2880 int wake; 2881 2882 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2883 2884 if (sc->sc_dying) { 2885 /* If we're dying, just do the software part. */ 2886 s = splusb(); 2887 xfer->status = status; /* make software ignore it */ 2888 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2889 usb_transfer_complete(xfer); 2890 splx(s); 2891 return; 2892 } 2893 2894 if (xfer->device->bus->intr_context) 2895 panic("ehci_abort_xfer: not in process context"); 2896 2897 /* 2898 * If an abort is already in progress then just wait for it to 2899 * complete and return. 2900 */ 2901 if (xfer->hcflags & UXFER_ABORTING) { 2902 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2903 #ifdef DIAGNOSTIC 2904 if (status == USBD_TIMEOUT) 2905 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2906 #endif 2907 /* Override the status which might be USBD_TIMEOUT. */ 2908 xfer->status = status; 2909 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2910 xfer->hcflags |= UXFER_ABORTWAIT; 2911 while (xfer->hcflags & UXFER_ABORTING) 2912 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2913 return; 2914 } 2915 xfer->hcflags |= UXFER_ABORTING; 2916 2917 /* 2918 * Step 1: Make interrupt routine and hardware ignore xfer. 2919 */ 2920 s = splusb(); 2921 xfer->status = status; /* make software ignore it */ 2922 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2923 2924 usb_syncmem(&sqh->dma, 2925 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2926 sizeof(sqh->qh.qh_qtd.qtd_status), 2927 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2928 qhstatus = sqh->qh.qh_qtd.qtd_status; 2929 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2930 usb_syncmem(&sqh->dma, 2931 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2932 sizeof(sqh->qh.qh_qtd.qtd_status), 2933 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2934 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2935 usb_syncmem(&sqtd->dma, 2936 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2937 sizeof(sqtd->qtd.qtd_status), 2938 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2939 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2940 usb_syncmem(&sqtd->dma, 2941 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2942 sizeof(sqtd->qtd.qtd_status), 2943 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2944 if (sqtd == exfer->sqtdend) 2945 break; 2946 } 2947 splx(s); 2948 2949 /* 2950 * Step 2: Wait until we know hardware has finished any possible 2951 * use of the xfer. Also make sure the soft interrupt routine 2952 * has run. 2953 */ 2954 ehci_sync_hc(sc); 2955 s = splusb(); 2956 #ifdef USB_USE_SOFTINTR 2957 sc->sc_softwake = 1; 2958 #endif /* USB_USE_SOFTINTR */ 2959 usb_schedsoftintr(&sc->sc_bus); 2960 #ifdef USB_USE_SOFTINTR 2961 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2962 #endif /* USB_USE_SOFTINTR */ 2963 splx(s); 2964 2965 /* 2966 * Step 3: Remove any vestiges of the xfer from the hardware. 2967 * The complication here is that the hardware may have executed 2968 * beyond the xfer we're trying to abort. So as we're scanning 2969 * the TDs of this xfer we check if the hardware points to 2970 * any of them. 2971 */ 2972 s = splusb(); /* XXX why? */ 2973 2974 usb_syncmem(&sqh->dma, 2975 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2976 sizeof(sqh->qh.qh_curqtd), 2977 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2978 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2979 hit = 0; 2980 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2981 hit |= cur == sqtd->physaddr; 2982 if (sqtd == exfer->sqtdend) 2983 break; 2984 } 2985 sqtd = sqtd->nextqtd; 2986 /* Zap curqtd register if hardware pointed inside the xfer. */ 2987 if (hit && sqtd != NULL) { 2988 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 2989 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 2990 usb_syncmem(&sqh->dma, 2991 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2992 sizeof(sqh->qh.qh_curqtd), 2993 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2994 sqh->qh.qh_qtd.qtd_status = qhstatus; 2995 usb_syncmem(&sqh->dma, 2996 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2997 sizeof(sqh->qh.qh_qtd.qtd_status), 2998 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2999 } else { 3000 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3001 } 3002 3003 /* 3004 * Step 4: Execute callback. 3005 */ 3006 #ifdef DIAGNOSTIC 3007 exfer->isdone = 1; 3008 #endif 3009 wake = xfer->hcflags & UXFER_ABORTWAIT; 3010 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3011 usb_transfer_complete(xfer); 3012 if (wake) 3013 wakeup(&xfer->hcflags); 3014 3015 splx(s); 3016 #undef exfer 3017 } 3018 3019 void 3020 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3021 { 3022 ehci_isoc_trans_t trans_status; 3023 struct ehci_pipe *epipe; 3024 struct ehci_xfer *exfer; 3025 ehci_softc_t *sc; 3026 struct ehci_soft_itd *itd; 3027 int s, i, wake; 3028 3029 epipe = (struct ehci_pipe *) xfer->pipe; 3030 exfer = EXFER(xfer); 3031 sc = epipe->pipe.device->bus->hci_private; 3032 3033 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3034 3035 if (sc->sc_dying) { 3036 s = splusb(); 3037 xfer->status = status; 3038 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3039 usb_transfer_complete(xfer); 3040 splx(s); 3041 return; 3042 } 3043 3044 if (xfer->hcflags & UXFER_ABORTING) { 3045 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3046 3047 #ifdef DIAGNOSTIC 3048 if (status == USBD_TIMEOUT) 3049 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3050 #endif 3051 3052 xfer->status = status; 3053 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3054 xfer->hcflags |= UXFER_ABORTWAIT; 3055 while (xfer->hcflags & UXFER_ABORTING) 3056 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0); 3057 return; 3058 } 3059 xfer->hcflags |= UXFER_ABORTING; 3060 3061 xfer->status = status; 3062 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3063 3064 s = splusb(); 3065 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3066 usb_syncmem(&itd->dma, 3067 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3068 sizeof(itd->itd.itd_ctl), 3069 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3070 3071 for (i = 0; i < 8; i++) { 3072 trans_status = le32toh(itd->itd.itd_ctl[i]); 3073 trans_status &= ~EHCI_ITD_ACTIVE; 3074 itd->itd.itd_ctl[i] = htole32(trans_status); 3075 } 3076 3077 usb_syncmem(&itd->dma, 3078 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3079 sizeof(itd->itd.itd_ctl), 3080 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3081 } 3082 splx(s); 3083 3084 s = splusb(); 3085 #ifdef USB_USE_SOFTINTR 3086 sc->sc_softwake = 1; 3087 #endif /* USB_USE_SOFTINTR */ 3088 usb_schedsoftintr(&sc->sc_bus); 3089 #ifdef USB_USE_SOFTINTR 3090 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3091 #endif /* USB_USE_SOFTINTR */ 3092 splx(s); 3093 3094 #ifdef DIAGNOSTIC 3095 exfer->isdone = 1; 3096 #endif 3097 wake = xfer->hcflags & UXFER_ABORTWAIT; 3098 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3099 usb_transfer_complete(xfer); 3100 if (wake) 3101 wakeup(&xfer->hcflags); 3102 3103 return; 3104 } 3105 3106 void 3107 ehci_timeout(void *addr) 3108 { 3109 struct ehci_xfer *exfer = addr; 3110 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3111 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3112 3113 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3114 #ifdef USB_DEBUG 3115 if (ehcidebug > 1) 3116 usbd_dump_pipe(exfer->xfer.pipe); 3117 #endif 3118 3119 if (sc->sc_dying) { 3120 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3121 return; 3122 } 3123 3124 /* Execute the abort in a process context. */ 3125 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3126 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3127 USB_TASKQ_HC); 3128 } 3129 3130 void 3131 ehci_timeout_task(void *addr) 3132 { 3133 usbd_xfer_handle xfer = addr; 3134 int s; 3135 3136 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3137 3138 s = splusb(); 3139 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3140 splx(s); 3141 } 3142 3143 /************************/ 3144 3145 Static usbd_status 3146 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3147 { 3148 usbd_status err; 3149 3150 /* Insert last in queue. */ 3151 err = usb_insert_transfer(xfer); 3152 if (err) 3153 return (err); 3154 3155 /* Pipe isn't running, start first */ 3156 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3157 } 3158 3159 Static usbd_status 3160 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3161 { 3162 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3163 usbd_status err; 3164 3165 if (sc->sc_dying) 3166 return (USBD_IOERROR); 3167 3168 #ifdef DIAGNOSTIC 3169 if (!(xfer->rqflags & URQ_REQUEST)) { 3170 /* XXX panic */ 3171 printf("ehci_device_ctrl_transfer: not a request\n"); 3172 return (USBD_INVAL); 3173 } 3174 #endif 3175 3176 err = ehci_device_request(xfer); 3177 if (err) 3178 return (err); 3179 3180 if (sc->sc_bus.use_polling) 3181 ehci_waitintr(sc, xfer); 3182 return (USBD_IN_PROGRESS); 3183 } 3184 3185 void 3186 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3187 { 3188 struct ehci_xfer *ex = EXFER(xfer); 3189 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3190 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3191 usb_device_request_t *req = &xfer->request; 3192 int len = UGETW(req->wLength); 3193 int rd = req->bmRequestType & UT_READ; 3194 3195 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3196 3197 #ifdef DIAGNOSTIC 3198 if (!(xfer->rqflags & URQ_REQUEST)) { 3199 panic("ehci_ctrl_done: not a request"); 3200 } 3201 #endif 3202 3203 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3204 ehci_del_intr_list(ex); /* remove from active list */ 3205 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3206 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3207 BUS_DMASYNC_POSTWRITE); 3208 if (len) 3209 usb_syncmem(&xfer->dmabuf, 0, len, 3210 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3211 } 3212 3213 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3214 } 3215 3216 /* Abort a device control request. */ 3217 Static void 3218 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3219 { 3220 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3221 ehci_abort_xfer(xfer, USBD_CANCELLED); 3222 } 3223 3224 /* Close a device control pipe. */ 3225 Static void 3226 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3227 { 3228 ehci_softc_t *sc = pipe->device->bus->hci_private; 3229 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3230 3231 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3232 ehci_close_pipe(pipe, sc->sc_async_head); 3233 } 3234 3235 usbd_status 3236 ehci_device_request(usbd_xfer_handle xfer) 3237 { 3238 #define exfer EXFER(xfer) 3239 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3240 usb_device_request_t *req = &xfer->request; 3241 usbd_device_handle dev = epipe->pipe.device; 3242 ehci_softc_t *sc = dev->bus->hci_private; 3243 int addr = dev->address; 3244 ehci_soft_qtd_t *setup, *stat, *next; 3245 ehci_soft_qh_t *sqh; 3246 int isread; 3247 int len; 3248 usbd_status err; 3249 int s; 3250 3251 isread = req->bmRequestType & UT_READ; 3252 len = UGETW(req->wLength); 3253 3254 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3255 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3256 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3257 UGETW(req->wIndex), len, addr, 3258 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3259 3260 setup = ehci_alloc_sqtd(sc); 3261 if (setup == NULL) { 3262 err = USBD_NOMEM; 3263 goto bad1; 3264 } 3265 stat = ehci_alloc_sqtd(sc); 3266 if (stat == NULL) { 3267 err = USBD_NOMEM; 3268 goto bad2; 3269 } 3270 3271 sqh = epipe->sqh; 3272 epipe->u.ctl.length = len; 3273 3274 /* Update device address and length since they may have changed 3275 during the setup of the control pipe in usbd_new_device(). */ 3276 /* XXX This only needs to be done once, but it's too early in open. */ 3277 /* XXXX Should not touch ED here! */ 3278 sqh->qh.qh_endp = 3279 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3280 htole32( 3281 EHCI_QH_SET_ADDR(addr) | 3282 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3283 ); 3284 3285 /* Set up data transaction */ 3286 if (len != 0) { 3287 ehci_soft_qtd_t *end; 3288 3289 /* Start toggle at 1. */ 3290 epipe->nexttoggle = 1; 3291 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3292 &next, &end); 3293 if (err) 3294 goto bad3; 3295 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3296 end->nextqtd = stat; 3297 end->qtd.qtd_next = 3298 end->qtd.qtd_altnext = htole32(stat->physaddr); 3299 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3300 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3301 } else { 3302 next = stat; 3303 } 3304 3305 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3306 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3307 3308 /* Clear toggle */ 3309 setup->qtd.qtd_status = htole32( 3310 EHCI_QTD_ACTIVE | 3311 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3312 EHCI_QTD_SET_CERR(3) | 3313 EHCI_QTD_SET_TOGGLE(0) | 3314 EHCI_QTD_SET_BYTES(sizeof *req) 3315 ); 3316 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3317 setup->qtd.qtd_buffer_hi[0] = 0; 3318 setup->nextqtd = next; 3319 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3320 setup->xfer = xfer; 3321 setup->len = sizeof *req; 3322 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3323 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3324 3325 stat->qtd.qtd_status = htole32( 3326 EHCI_QTD_ACTIVE | 3327 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3328 EHCI_QTD_SET_CERR(3) | 3329 EHCI_QTD_SET_TOGGLE(1) | 3330 EHCI_QTD_IOC 3331 ); 3332 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3333 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3334 stat->nextqtd = NULL; 3335 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3336 stat->xfer = xfer; 3337 stat->len = 0; 3338 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3339 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3340 3341 #ifdef EHCI_DEBUG 3342 if (ehcidebug > 5) { 3343 DPRINTF(("ehci_device_request:\n")); 3344 ehci_dump_sqh(sqh); 3345 ehci_dump_sqtds(setup); 3346 } 3347 #endif 3348 3349 exfer->sqtdstart = setup; 3350 exfer->sqtdend = stat; 3351 #ifdef DIAGNOSTIC 3352 if (!exfer->isdone) { 3353 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3354 } 3355 exfer->isdone = 0; 3356 #endif 3357 3358 /* Insert qTD in QH list. */ 3359 s = splusb(); 3360 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3361 if (xfer->timeout && !sc->sc_bus.use_polling) { 3362 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3363 ehci_timeout, xfer); 3364 } 3365 ehci_add_intr_list(sc, exfer); 3366 xfer->status = USBD_IN_PROGRESS; 3367 splx(s); 3368 3369 #ifdef EHCI_DEBUG 3370 if (ehcidebug > 10) { 3371 DPRINTF(("ehci_device_request: status=%x\n", 3372 EOREAD4(sc, EHCI_USBSTS))); 3373 delay(10000); 3374 ehci_dump_regs(sc); 3375 ehci_dump_sqh(sc->sc_async_head); 3376 ehci_dump_sqh(sqh); 3377 ehci_dump_sqtds(setup); 3378 } 3379 #endif 3380 3381 return (USBD_NORMAL_COMPLETION); 3382 3383 bad3: 3384 ehci_free_sqtd(sc, stat); 3385 bad2: 3386 ehci_free_sqtd(sc, setup); 3387 bad1: 3388 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3389 xfer->status = err; 3390 usb_transfer_complete(xfer); 3391 return (err); 3392 #undef exfer 3393 } 3394 3395 /* 3396 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3397 * qTD status, or miss signalling occasionally under heavy load. If the host 3398 * machine is too fast, we we can miss transaction completion - when we scan 3399 * the active list the transaction still seems to be active. This generally 3400 * exhibits itself as a umass stall that never recovers. 3401 * 3402 * We work around this behaviour by setting up this callback after any softintr 3403 * that completes with transactions still pending, giving us another chance to 3404 * check for completion after the writeback has taken place. 3405 */ 3406 void 3407 ehci_intrlist_timeout(void *arg) 3408 { 3409 ehci_softc_t *sc = arg; 3410 int s = splusb(); 3411 3412 DPRINTF(("ehci_intrlist_timeout\n")); 3413 usb_schedsoftintr(&sc->sc_bus); 3414 3415 splx(s); 3416 } 3417 3418 /************************/ 3419 3420 Static usbd_status 3421 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3422 { 3423 usbd_status err; 3424 3425 /* Insert last in queue. */ 3426 err = usb_insert_transfer(xfer); 3427 if (err) 3428 return (err); 3429 3430 /* Pipe isn't running, start first */ 3431 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3432 } 3433 3434 usbd_status 3435 ehci_device_bulk_start(usbd_xfer_handle xfer) 3436 { 3437 #define exfer EXFER(xfer) 3438 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3439 usbd_device_handle dev = epipe->pipe.device; 3440 ehci_softc_t *sc = dev->bus->hci_private; 3441 ehci_soft_qtd_t *data, *dataend; 3442 ehci_soft_qh_t *sqh; 3443 usbd_status err; 3444 int len, isread, endpt; 3445 int s; 3446 3447 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3448 xfer, xfer->length, xfer->flags)); 3449 3450 if (sc->sc_dying) 3451 return (USBD_IOERROR); 3452 3453 #ifdef DIAGNOSTIC 3454 if (xfer->rqflags & URQ_REQUEST) 3455 panic("ehci_device_bulk_start: a request"); 3456 #endif 3457 3458 len = xfer->length; 3459 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3460 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3461 sqh = epipe->sqh; 3462 3463 epipe->u.bulk.length = len; 3464 3465 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3466 &dataend); 3467 if (err) { 3468 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3469 xfer->status = err; 3470 usb_transfer_complete(xfer); 3471 return (err); 3472 } 3473 3474 #ifdef EHCI_DEBUG 3475 if (ehcidebug > 5) { 3476 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3477 ehci_dump_sqh(sqh); 3478 ehci_dump_sqtds(data); 3479 } 3480 #endif 3481 3482 /* Set up interrupt info. */ 3483 exfer->sqtdstart = data; 3484 exfer->sqtdend = dataend; 3485 #ifdef DIAGNOSTIC 3486 if (!exfer->isdone) { 3487 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3488 } 3489 exfer->isdone = 0; 3490 #endif 3491 3492 s = splusb(); 3493 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3494 if (xfer->timeout && !sc->sc_bus.use_polling) { 3495 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3496 ehci_timeout, xfer); 3497 } 3498 ehci_add_intr_list(sc, exfer); 3499 xfer->status = USBD_IN_PROGRESS; 3500 splx(s); 3501 3502 #ifdef EHCI_DEBUG 3503 if (ehcidebug > 10) { 3504 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3505 delay(10000); 3506 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3507 ehci_dump_regs(sc); 3508 #if 0 3509 printf("async_head:\n"); 3510 ehci_dump_sqh(sc->sc_async_head); 3511 #endif 3512 printf("sqh:\n"); 3513 ehci_dump_sqh(sqh); 3514 ehci_dump_sqtds(data); 3515 } 3516 #endif 3517 3518 if (sc->sc_bus.use_polling) 3519 ehci_waitintr(sc, xfer); 3520 3521 return (USBD_IN_PROGRESS); 3522 #undef exfer 3523 } 3524 3525 Static void 3526 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3527 { 3528 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3529 ehci_abort_xfer(xfer, USBD_CANCELLED); 3530 } 3531 3532 /* 3533 * Close a device bulk pipe. 3534 */ 3535 Static void 3536 ehci_device_bulk_close(usbd_pipe_handle pipe) 3537 { 3538 ehci_softc_t *sc = pipe->device->bus->hci_private; 3539 3540 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3541 ehci_close_pipe(pipe, sc->sc_async_head); 3542 } 3543 3544 void 3545 ehci_device_bulk_done(usbd_xfer_handle xfer) 3546 { 3547 struct ehci_xfer *ex = EXFER(xfer); 3548 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3549 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3550 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3551 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3552 3553 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3554 xfer, xfer->actlen)); 3555 3556 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3557 ehci_del_intr_list(ex); /* remove from active list */ 3558 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3559 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3560 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3561 } 3562 3563 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3564 } 3565 3566 /************************/ 3567 3568 Static usbd_status 3569 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3570 { 3571 struct ehci_soft_islot *isp; 3572 int islot, lev; 3573 3574 /* Find a poll rate that is large enough. */ 3575 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3576 if (EHCI_ILEV_IVAL(lev) <= ival) 3577 break; 3578 3579 /* Pick an interrupt slot at the right level. */ 3580 /* XXX could do better than picking at random */ 3581 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3582 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3583 3584 sqh->islot = islot; 3585 isp = &sc->sc_islots[islot]; 3586 ehci_add_qh(sqh, isp->sqh); 3587 3588 return (USBD_NORMAL_COMPLETION); 3589 } 3590 3591 Static usbd_status 3592 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3593 { 3594 usbd_status err; 3595 3596 /* Insert last in queue. */ 3597 err = usb_insert_transfer(xfer); 3598 if (err) 3599 return (err); 3600 3601 /* 3602 * Pipe isn't running (otherwise err would be USBD_INPROG), 3603 * so start it first. 3604 */ 3605 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3606 } 3607 3608 Static usbd_status 3609 ehci_device_intr_start(usbd_xfer_handle xfer) 3610 { 3611 #define exfer EXFER(xfer) 3612 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3613 usbd_device_handle dev = xfer->pipe->device; 3614 ehci_softc_t *sc = dev->bus->hci_private; 3615 ehci_soft_qtd_t *data, *dataend; 3616 ehci_soft_qh_t *sqh; 3617 usbd_status err; 3618 int len, isread, endpt; 3619 int s; 3620 3621 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3622 xfer, xfer->length, xfer->flags)); 3623 3624 if (sc->sc_dying) 3625 return (USBD_IOERROR); 3626 3627 #ifdef DIAGNOSTIC 3628 if (xfer->rqflags & URQ_REQUEST) 3629 panic("ehci_device_intr_start: a request"); 3630 #endif 3631 3632 len = xfer->length; 3633 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3634 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3635 sqh = epipe->sqh; 3636 3637 epipe->u.intr.length = len; 3638 3639 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3640 &dataend); 3641 if (err) { 3642 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3643 xfer->status = err; 3644 usb_transfer_complete(xfer); 3645 return (err); 3646 } 3647 3648 #ifdef EHCI_DEBUG 3649 if (ehcidebug > 5) { 3650 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3651 ehci_dump_sqh(sqh); 3652 ehci_dump_sqtds(data); 3653 } 3654 #endif 3655 3656 /* Set up interrupt info. */ 3657 exfer->sqtdstart = data; 3658 exfer->sqtdend = dataend; 3659 #ifdef DIAGNOSTIC 3660 if (!exfer->isdone) { 3661 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3662 } 3663 exfer->isdone = 0; 3664 #endif 3665 3666 s = splusb(); 3667 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3668 if (xfer->timeout && !sc->sc_bus.use_polling) { 3669 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3670 ehci_timeout, xfer); 3671 } 3672 ehci_add_intr_list(sc, exfer); 3673 xfer->status = USBD_IN_PROGRESS; 3674 splx(s); 3675 3676 #ifdef EHCI_DEBUG 3677 if (ehcidebug > 10) { 3678 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3679 delay(10000); 3680 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3681 ehci_dump_regs(sc); 3682 printf("sqh:\n"); 3683 ehci_dump_sqh(sqh); 3684 ehci_dump_sqtds(data); 3685 } 3686 #endif 3687 3688 if (sc->sc_bus.use_polling) 3689 ehci_waitintr(sc, xfer); 3690 3691 return (USBD_IN_PROGRESS); 3692 #undef exfer 3693 } 3694 3695 Static void 3696 ehci_device_intr_abort(usbd_xfer_handle xfer) 3697 { 3698 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3699 if (xfer->pipe->intrxfer == xfer) { 3700 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3701 xfer->pipe->intrxfer = NULL; 3702 } 3703 /* 3704 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3705 * async doorbell. That's dependant on the async list, wheras 3706 * intr xfers are periodic, should not use this? 3707 */ 3708 ehci_abort_xfer(xfer, USBD_CANCELLED); 3709 } 3710 3711 Static void 3712 ehci_device_intr_close(usbd_pipe_handle pipe) 3713 { 3714 ehci_softc_t *sc = pipe->device->bus->hci_private; 3715 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3716 struct ehci_soft_islot *isp; 3717 3718 isp = &sc->sc_islots[epipe->sqh->islot]; 3719 ehci_close_pipe(pipe, isp->sqh); 3720 } 3721 3722 Static void 3723 ehci_device_intr_done(usbd_xfer_handle xfer) 3724 { 3725 #define exfer EXFER(xfer) 3726 struct ehci_xfer *ex = EXFER(xfer); 3727 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3728 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3729 ehci_soft_qtd_t *data, *dataend; 3730 ehci_soft_qh_t *sqh; 3731 usbd_status err; 3732 int len, isread, endpt, s; 3733 3734 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3735 xfer, xfer->actlen)); 3736 3737 if (xfer->pipe->repeat) { 3738 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3739 3740 len = epipe->u.intr.length; 3741 xfer->length = len; 3742 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3743 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3744 usb_syncmem(&xfer->dmabuf, 0, len, 3745 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3746 sqh = epipe->sqh; 3747 3748 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3749 &data, &dataend); 3750 if (err) { 3751 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3752 xfer->status = err; 3753 return; 3754 } 3755 3756 /* Set up interrupt info. */ 3757 exfer->sqtdstart = data; 3758 exfer->sqtdend = dataend; 3759 #ifdef DIAGNOSTIC 3760 if (!exfer->isdone) { 3761 printf("ehci_device_intr_done: not done, ex=%p\n", 3762 exfer); 3763 } 3764 exfer->isdone = 0; 3765 #endif 3766 3767 s = splusb(); 3768 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3769 if (xfer->timeout && !sc->sc_bus.use_polling) { 3770 usb_callout(xfer->timeout_handle, 3771 mstohz(xfer->timeout), ehci_timeout, xfer); 3772 } 3773 splx(s); 3774 3775 xfer->status = USBD_IN_PROGRESS; 3776 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3777 ehci_del_intr_list(ex); /* remove from active list */ 3778 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3779 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3780 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3781 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3782 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3783 } 3784 #undef exfer 3785 } 3786 3787 /************************/ 3788 3789 Static usbd_status 3790 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3791 { 3792 usbd_status err; 3793 3794 err = usb_insert_transfer(xfer); 3795 if (err && err != USBD_IN_PROGRESS) 3796 return err; 3797 3798 return ehci_device_isoc_start(xfer); 3799 } 3800 3801 Static usbd_status 3802 ehci_device_isoc_start(usbd_xfer_handle xfer) 3803 { 3804 struct ehci_pipe *epipe; 3805 usbd_device_handle dev; 3806 ehci_softc_t *sc; 3807 struct ehci_xfer *exfer; 3808 ehci_soft_itd_t *itd, *prev, *start, *stop; 3809 usb_dma_t *dma_buf; 3810 int i, j, k, frames, uframes, ufrperframe; 3811 int s, trans_count, offs, total_length; 3812 int frindex; 3813 3814 start = NULL; 3815 prev = NULL; 3816 itd = NULL; 3817 trans_count = 0; 3818 total_length = 0; 3819 exfer = (struct ehci_xfer *) xfer; 3820 sc = xfer->pipe->device->bus->hci_private; 3821 dev = xfer->pipe->device; 3822 epipe = (struct ehci_pipe *)xfer->pipe; 3823 3824 /* 3825 * To allow continuous transfers, above we start all transfers 3826 * immediately. However, we're still going to get usbd_start_next call 3827 * this when another xfer completes. So, check if this is already 3828 * in progress or not 3829 */ 3830 3831 if (exfer->itdstart != NULL) 3832 return USBD_IN_PROGRESS; 3833 3834 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3835 xfer, xfer->length, xfer->flags)); 3836 3837 if (sc->sc_dying) 3838 return USBD_IOERROR; 3839 3840 /* 3841 * To avoid complication, don't allow a request right now that'll span 3842 * the entire frame table. To within 4 frames, to allow some leeway 3843 * on either side of where the hc currently is. 3844 */ 3845 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3846 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3847 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3848 return USBD_INVAL; 3849 } 3850 3851 #ifdef DIAGNOSTIC 3852 if (xfer->rqflags & URQ_REQUEST) 3853 panic("ehci_device_isoc_start: request\n"); 3854 3855 if (!exfer->isdone) 3856 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3857 exfer->isdone = 0; 3858 #endif 3859 3860 /* 3861 * Step 1: Allocate and initialize itds, how many do we need? 3862 * One per transfer if interval >= 8 microframes, fewer if we use 3863 * multiple microframes per frame. 3864 */ 3865 3866 i = epipe->pipe.endpoint->edesc->bInterval; 3867 if (i > 16 || i == 0) { 3868 /* Spec page 271 says intervals > 16 are invalid */ 3869 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3870 return USBD_INVAL; 3871 } 3872 3873 switch (i) { 3874 case 1: 3875 ufrperframe = 8; 3876 break; 3877 case 2: 3878 ufrperframe = 4; 3879 break; 3880 case 3: 3881 ufrperframe = 2; 3882 break; 3883 default: 3884 ufrperframe = 1; 3885 break; 3886 } 3887 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3888 uframes = 8 / ufrperframe; 3889 3890 if (frames == 0) { 3891 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3892 return USBD_INVAL; 3893 } 3894 3895 dma_buf = &xfer->dmabuf; 3896 offs = 0; 3897 3898 for (i = 0; i < frames; i++) { 3899 int froffs = offs; 3900 itd = ehci_alloc_itd(sc); 3901 3902 if (prev != NULL) { 3903 prev->itd.itd_next = 3904 htole32(itd->physaddr | EHCI_LINK_ITD); 3905 usb_syncmem(&itd->dma, 3906 itd->offs + offsetof(ehci_itd_t, itd_next), 3907 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 3908 3909 prev->xfer_next = itd; 3910 } else { 3911 start = itd; 3912 } 3913 3914 /* 3915 * Step 1.5, initialize uframes 3916 */ 3917 for (j = 0; j < 8; j += uframes) { 3918 /* Calculate which page in the list this starts in */ 3919 int addr = DMAADDR(dma_buf, froffs); 3920 addr = EHCI_PAGE_OFFSET(addr); 3921 addr += (offs - froffs); 3922 addr = EHCI_PAGE(addr); 3923 addr /= EHCI_PAGE_SIZE; 3924 3925 /* This gets the initial offset into the first page, 3926 * looks how far further along the current uframe 3927 * offset is. Works out how many pages that is. 3928 */ 3929 3930 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3931 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3932 EHCI_ITD_SET_PG(addr) | 3933 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 3934 3935 total_length += xfer->frlengths[trans_count]; 3936 offs += xfer->frlengths[trans_count]; 3937 trans_count++; 3938 3939 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3940 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3941 break; 3942 } 3943 } 3944 3945 /* Step 1.75, set buffer pointers. To simplify matters, all 3946 * pointers are filled out for the next 7 hardware pages in 3947 * the dma block, so no need to worry what pages to cover 3948 * and what to not. 3949 */ 3950 3951 for (j=0; j < 7; j++) { 3952 /* 3953 * Don't try to lookup a page that's past the end 3954 * of buffer 3955 */ 3956 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 3957 if (page_offs >= dma_buf->block->size) 3958 break; 3959 3960 int page = DMAADDR(dma_buf, page_offs); 3961 page = EHCI_PAGE(page); 3962 itd->itd.itd_bufr[j] = 3963 htole32(EHCI_ITD_SET_BPTR(page) | 3964 EHCI_LINK_ITD); 3965 } 3966 3967 /* 3968 * Other special values 3969 */ 3970 3971 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3972 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3973 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3974 3975 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3976 ? 1 : 0; 3977 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3978 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3979 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3980 3981 /* FIXME: handle invalid trans */ 3982 itd->itd.itd_bufr[2] |= 3983 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3984 3985 usb_syncmem(&itd->dma, 3986 itd->offs + offsetof(ehci_itd_t, itd_next), 3987 sizeof(ehci_itd_t), 3988 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3989 3990 prev = itd; 3991 } /* End of frame */ 3992 3993 stop = itd; 3994 stop->xfer_next = NULL; 3995 exfer->isoc_len = total_length; 3996 3997 /* 3998 * Part 2: Transfer descriptors have now been set up, now they must 3999 * be scheduled into the period frame list. Erk. Not wanting to 4000 * complicate matters, transfer is denied if the transfer spans 4001 * more than the period frame list. 4002 */ 4003 4004 s = splusb(); 4005 4006 /* Start inserting frames */ 4007 if (epipe->u.isoc.cur_xfers > 0) { 4008 frindex = epipe->u.isoc.next_frame; 4009 } else { 4010 frindex = EOREAD4(sc, EHCI_FRINDEX); 4011 frindex = frindex >> 3; /* Erase microframe index */ 4012 frindex += 2; 4013 } 4014 4015 if (frindex >= sc->sc_flsize) 4016 frindex &= (sc->sc_flsize - 1); 4017 4018 /* Whats the frame interval? */ 4019 i = (1 << epipe->pipe.endpoint->edesc->bInterval); 4020 if (i / 8 == 0) 4021 i = 1; 4022 else 4023 i /= 8; 4024 4025 itd = start; 4026 for (j = 0; j < frames; j++) { 4027 if (itd == NULL) 4028 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4029 4030 itd->itd.itd_next = sc->sc_flist[frindex]; 4031 if (itd->itd.itd_next == 0) 4032 /* FIXME: frindex table gets initialized to NULL 4033 * or EHCI_NULL? */ 4034 itd->itd.itd_next = htole32(EHCI_NULL); 4035 4036 usb_syncmem(&itd->dma, 4037 itd->offs + offsetof(ehci_itd_t, itd_next), 4038 sizeof(itd->itd.itd_next), 4039 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4040 4041 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4042 4043 usb_syncmem(&sc->sc_fldma, 4044 sizeof(ehci_link_t) * frindex, 4045 sizeof(ehci_link_t), 4046 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4047 4048 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4049 sc->sc_softitds[frindex] = itd; 4050 if (itd->u.frame_list.next != NULL) 4051 itd->u.frame_list.next->u.frame_list.prev = itd; 4052 itd->slot = frindex; 4053 itd->u.frame_list.prev = NULL; 4054 4055 frindex += i; 4056 if (frindex >= sc->sc_flsize) 4057 frindex -= sc->sc_flsize; 4058 4059 itd = itd->xfer_next; 4060 } 4061 4062 epipe->u.isoc.cur_xfers++; 4063 epipe->u.isoc.next_frame = frindex; 4064 4065 exfer->itdstart = start; 4066 exfer->itdend = stop; 4067 exfer->sqtdstart = NULL; 4068 exfer->sqtdstart = NULL; 4069 4070 ehci_add_intr_list(sc, exfer); 4071 xfer->status = USBD_IN_PROGRESS; 4072 xfer->done = 0; 4073 splx(s); 4074 4075 if (sc->sc_bus.use_polling) { 4076 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4077 ehci_waitintr(sc, xfer); 4078 } 4079 4080 return USBD_IN_PROGRESS; 4081 } 4082 4083 Static void 4084 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4085 { 4086 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4087 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4088 } 4089 4090 Static void 4091 ehci_device_isoc_close(usbd_pipe_handle pipe) 4092 { 4093 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4094 } 4095 4096 Static void 4097 ehci_device_isoc_done(usbd_xfer_handle xfer) 4098 { 4099 struct ehci_xfer *exfer; 4100 ehci_softc_t *sc; 4101 struct ehci_pipe *epipe; 4102 int s; 4103 4104 exfer = EXFER(xfer); 4105 sc = xfer->pipe->device->bus->hci_private; 4106 epipe = (struct ehci_pipe *) xfer->pipe; 4107 4108 s = splusb(); 4109 epipe->u.isoc.cur_xfers--; 4110 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4111 ehci_del_intr_list(exfer); 4112 ehci_rem_free_itd_chain(sc, exfer); 4113 } 4114 splx(s); 4115 4116 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4117 BUS_DMASYNC_POSTREAD); 4118 4119 } 4120
Indexes created Wed Sep 24 14:09:57 GMT 2025