ehci.c revision 1.154.4.2
1 /* $NetBSD: ehci.c,v 1.154.4.2 2010/06/12 01:05:44 riz Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum and 9 * Jeremy Morse (jeremy.morse (at) gmail.com). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 35 * 36 * The EHCI 1.0 spec can be found at 37 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/usb_20.zip 40 * 41 */ 42 43 /* 44 * TODO: 45 * 1) hold off explorations by companion controllers until ehci has started. 46 * 47 * 2) The hub driver needs to handle and schedule the transaction translator, 48 * to assign place in frame where different devices get to go. See chapter 49 * on hubs in USB 2.0 for details. 50 * 51 * 3) command failures are not recovered correctly 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.154.4.2 2010/06/12 01:05:44 riz Exp $"); 56 57 #include "ohci.h" 58 #include "uhci.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/kernel.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/select.h> 66 #include <sys/proc.h> 67 #include <sys/queue.h> 68 #include <sys/mutex.h> 69 #include <sys/bus.h> 70 71 #include <machine/endian.h> 72 73 #include <dev/usb/usb.h> 74 #include <dev/usb/usbdi.h> 75 #include <dev/usb/usbdivar.h> 76 #include <dev/usb/usb_mem.h> 77 #include <dev/usb/usb_quirks.h> 78 79 #include <dev/usb/ehcireg.h> 80 #include <dev/usb/ehcivar.h> 81 #include <dev/usb/usbroothub_subr.h> 82 83 #ifdef EHCI_DEBUG 84 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 85 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 86 int ehcidebug = 0; 87 #ifndef __NetBSD__ 88 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 89 #endif 90 #else 91 #define DPRINTF(x) 92 #define DPRINTFN(n,x) 93 #endif 94 95 struct ehci_pipe { 96 struct usbd_pipe pipe; 97 int nexttoggle; 98 99 ehci_soft_qh_t *sqh; 100 union { 101 ehci_soft_qtd_t *qtd; 102 /* ehci_soft_itd_t *itd; */ 103 } tail; 104 union { 105 /* Control pipe */ 106 struct { 107 usb_dma_t reqdma; 108 u_int length; 109 } ctl; 110 /* Interrupt pipe */ 111 struct { 112 u_int length; 113 } intr; 114 /* Bulk pipe */ 115 struct { 116 u_int length; 117 } bulk; 118 /* Iso pipe */ 119 struct { 120 u_int next_frame; 121 u_int cur_xfers; 122 } isoc; 123 } u; 124 }; 125 126 Static usbd_status ehci_open(usbd_pipe_handle); 127 Static void ehci_poll(struct usbd_bus *); 128 Static void ehci_softintr(void *); 129 Static int ehci_intr1(ehci_softc_t *); 130 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 131 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 132 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 133 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 134 Static void ehci_idone(struct ehci_xfer *); 135 Static void ehci_timeout(void *); 136 Static void ehci_timeout_task(void *); 137 Static void ehci_intrlist_timeout(void *); 138 139 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 140 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 141 142 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 143 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 144 145 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 146 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 147 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 148 Static void ehci_root_ctrl_close(usbd_pipe_handle); 149 Static void ehci_root_ctrl_done(usbd_xfer_handle); 150 151 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 152 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 153 Static void ehci_root_intr_abort(usbd_xfer_handle); 154 Static void ehci_root_intr_close(usbd_pipe_handle); 155 Static void ehci_root_intr_done(usbd_xfer_handle); 156 157 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 158 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 159 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 160 Static void ehci_device_ctrl_close(usbd_pipe_handle); 161 Static void ehci_device_ctrl_done(usbd_xfer_handle); 162 163 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 164 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 165 Static void ehci_device_bulk_abort(usbd_xfer_handle); 166 Static void ehci_device_bulk_close(usbd_pipe_handle); 167 Static void ehci_device_bulk_done(usbd_xfer_handle); 168 169 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 170 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 171 Static void ehci_device_intr_abort(usbd_xfer_handle); 172 Static void ehci_device_intr_close(usbd_pipe_handle); 173 Static void ehci_device_intr_done(usbd_xfer_handle); 174 175 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 176 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 177 Static void ehci_device_isoc_abort(usbd_xfer_handle); 178 Static void ehci_device_isoc_close(usbd_pipe_handle); 179 Static void ehci_device_isoc_done(usbd_xfer_handle); 180 181 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 182 Static void ehci_noop(usbd_pipe_handle pipe); 183 184 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 185 Static void ehci_disown(ehci_softc_t *, int, int); 186 187 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 188 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 189 190 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 191 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 192 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 193 ehci_softc_t *, int, int, usbd_xfer_handle, 194 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 195 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 196 ehci_soft_qtd_t *); 197 198 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 199 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 200 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 201 struct ehci_xfer *exfer); 202 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 203 usbd_status status); 204 205 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 206 207 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 208 int ival); 209 210 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 211 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 212 ehci_soft_qh_t *); 213 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 214 Static void ehci_sync_hc(ehci_softc_t *); 215 216 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 217 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 218 219 #ifdef EHCI_DEBUG 220 Static void ehci_dump_regs(ehci_softc_t *); 221 void ehci_dump(void); 222 Static ehci_softc_t *theehci; 223 Static void ehci_dump_link(ehci_link_t, int); 224 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 225 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 226 Static void ehci_dump_qtd(ehci_qtd_t *); 227 Static void ehci_dump_sqh(ehci_soft_qh_t *); 228 #if notyet 229 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 230 Static void ehci_dump_itd(struct ehci_soft_itd *); 231 #endif 232 #ifdef DIAGNOSTIC 233 Static void ehci_dump_exfer(struct ehci_xfer *); 234 #endif 235 #endif 236 237 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 238 239 #define EHCI_INTR_ENDPT 1 240 241 #define ehci_add_intr_list(sc, ex) \ 242 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 243 #define ehci_del_intr_list(sc, ex) \ 244 do { \ 245 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 246 (ex)->inext.tqe_prev = NULL; \ 247 } while (0) 248 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 249 250 Static const struct usbd_bus_methods ehci_bus_methods = { 251 ehci_open, 252 ehci_softintr, 253 ehci_poll, 254 ehci_allocm, 255 ehci_freem, 256 ehci_allocx, 257 ehci_freex, 258 }; 259 260 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 261 ehci_root_ctrl_transfer, 262 ehci_root_ctrl_start, 263 ehci_root_ctrl_abort, 264 ehci_root_ctrl_close, 265 ehci_noop, 266 ehci_root_ctrl_done, 267 }; 268 269 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 270 ehci_root_intr_transfer, 271 ehci_root_intr_start, 272 ehci_root_intr_abort, 273 ehci_root_intr_close, 274 ehci_noop, 275 ehci_root_intr_done, 276 }; 277 278 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 279 ehci_device_ctrl_transfer, 280 ehci_device_ctrl_start, 281 ehci_device_ctrl_abort, 282 ehci_device_ctrl_close, 283 ehci_noop, 284 ehci_device_ctrl_done, 285 }; 286 287 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 288 ehci_device_intr_transfer, 289 ehci_device_intr_start, 290 ehci_device_intr_abort, 291 ehci_device_intr_close, 292 ehci_device_clear_toggle, 293 ehci_device_intr_done, 294 }; 295 296 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 297 ehci_device_bulk_transfer, 298 ehci_device_bulk_start, 299 ehci_device_bulk_abort, 300 ehci_device_bulk_close, 301 ehci_device_clear_toggle, 302 ehci_device_bulk_done, 303 }; 304 305 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 306 ehci_device_isoc_transfer, 307 ehci_device_isoc_start, 308 ehci_device_isoc_abort, 309 ehci_device_isoc_close, 310 ehci_noop, 311 ehci_device_isoc_done, 312 }; 313 314 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 315 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 316 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 317 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 318 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 319 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 320 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 321 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 322 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 323 }; 324 325 usbd_status 326 ehci_init(ehci_softc_t *sc) 327 { 328 u_int32_t vers, sparams, cparams, hcr; 329 u_int i; 330 usbd_status err; 331 ehci_soft_qh_t *sqh; 332 u_int ncomp; 333 334 DPRINTF(("ehci_init: start\n")); 335 #ifdef EHCI_DEBUG 336 theehci = sc; 337 #endif 338 339 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 340 341 vers = EREAD2(sc, EHCI_HCIVERSION); 342 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 343 vers >> 8, vers & 0xff); 344 345 sparams = EREAD4(sc, EHCI_HCSPARAMS); 346 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 347 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 348 ncomp = EHCI_HCS_N_CC(sparams); 349 if (ncomp != sc->sc_ncomp) { 350 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 351 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 352 #if NOHCI == 0 || NUHCI == 0 353 aprint_error("%s: ohci or uhci probably not configured\n", 354 device_xname(sc->sc_dev)); 355 #endif 356 if (ncomp < sc->sc_ncomp) 357 sc->sc_ncomp = ncomp; 358 } 359 if (sc->sc_ncomp > 0) { 360 aprint_normal("%s: companion controller%s, %d port%s each:", 361 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 362 EHCI_HCS_N_PCC(sparams), 363 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 364 for (i = 0; i < sc->sc_ncomp; i++) 365 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 366 aprint_normal("\n"); 367 } 368 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 369 cparams = EREAD4(sc, EHCI_HCCPARAMS); 370 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 371 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 372 373 if (EHCI_HCC_64BIT(cparams)) { 374 /* MUST clear segment register if 64 bit capable. */ 375 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 376 } 377 378 sc->sc_bus.usbrev = USBREV_2_0; 379 380 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 381 USB_MEM_RESERVE); 382 383 /* Reset the controller */ 384 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 385 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 386 usb_delay_ms(&sc->sc_bus, 1); 387 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 388 for (i = 0; i < 100; i++) { 389 usb_delay_ms(&sc->sc_bus, 1); 390 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 391 if (!hcr) 392 break; 393 } 394 if (hcr) { 395 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 396 return (USBD_IOERROR); 397 } 398 399 /* XXX need proper intr scheduling */ 400 sc->sc_rand = 96; 401 402 /* frame list size at default, read back what we got and use that */ 403 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 404 case 0: sc->sc_flsize = 1024; break; 405 case 1: sc->sc_flsize = 512; break; 406 case 2: sc->sc_flsize = 256; break; 407 case 3: return (USBD_IOERROR); 408 } 409 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 410 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 411 if (err) 412 return (err); 413 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 414 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 415 416 for (i = 0; i < sc->sc_flsize; i++) { 417 sc->sc_flist[i] = EHCI_NULL; 418 } 419 420 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 421 422 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 423 M_USB, M_NOWAIT | M_ZERO); 424 if (sc->sc_softitds == NULL) 425 return ENOMEM; 426 LIST_INIT(&sc->sc_freeitds); 427 TAILQ_INIT(&sc->sc_intrhead); 428 mutex_init(&sc->sc_intrhead_lock, MUTEX_DEFAULT, IPL_USB); 429 430 /* Set up the bus struct. */ 431 sc->sc_bus.methods = &ehci_bus_methods; 432 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 433 434 sc->sc_eintrs = EHCI_NORMAL_INTRS; 435 436 /* 437 * Allocate the interrupt dummy QHs. These are arranged to give poll 438 * intervals that are powers of 2 times 1ms. 439 */ 440 for (i = 0; i < EHCI_INTRQHS; i++) { 441 sqh = ehci_alloc_sqh(sc); 442 if (sqh == NULL) { 443 err = USBD_NOMEM; 444 goto bad1; 445 } 446 sc->sc_islots[i].sqh = sqh; 447 } 448 for (i = 0; i < EHCI_INTRQHS; i++) { 449 sqh = sc->sc_islots[i].sqh; 450 if (i == 0) { 451 /* The last (1ms) QH terminates. */ 452 sqh->qh.qh_link = EHCI_NULL; 453 sqh->next = NULL; 454 } else { 455 /* Otherwise the next QH has half the poll interval */ 456 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 457 sqh->qh.qh_link = htole32(sqh->next->physaddr | 458 EHCI_LINK_QH); 459 } 460 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 461 sqh->qh.qh_curqtd = EHCI_NULL; 462 sqh->next = NULL; 463 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 464 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 465 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 466 sqh->sqtd = NULL; 467 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 468 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 469 } 470 /* Point the frame list at the last level (128ms). */ 471 for (i = 0; i < sc->sc_flsize; i++) { 472 int j; 473 474 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 475 revbits[i & (EHCI_MAX_POLLRATE-1)]; 476 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 477 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 478 i)].sqh->physaddr); 479 } 480 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 481 BUS_DMASYNC_PREWRITE); 482 483 /* Allocate dummy QH that starts the async list. */ 484 sqh = ehci_alloc_sqh(sc); 485 if (sqh == NULL) { 486 err = USBD_NOMEM; 487 goto bad1; 488 } 489 /* Fill the QH */ 490 sqh->qh.qh_endp = 491 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 492 sqh->qh.qh_link = 493 htole32(sqh->physaddr | EHCI_LINK_QH); 494 sqh->qh.qh_curqtd = EHCI_NULL; 495 sqh->next = NULL; 496 /* Fill the overlay qTD */ 497 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 498 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 499 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 500 sqh->sqtd = NULL; 501 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 502 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 503 #ifdef EHCI_DEBUG 504 if (ehcidebug) { 505 ehci_dump_sqh(sqh); 506 } 507 #endif 508 509 /* Point to async list */ 510 sc->sc_async_head = sqh; 511 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 512 513 usb_callout_init(sc->sc_tmo_intrlist); 514 515 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE); 516 517 /* Turn on controller */ 518 EOWRITE4(sc, EHCI_USBCMD, 519 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 520 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 521 EHCI_CMD_ASE | 522 EHCI_CMD_PSE | 523 EHCI_CMD_RS); 524 525 /* Take over port ownership */ 526 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 527 528 for (i = 0; i < 100; i++) { 529 usb_delay_ms(&sc->sc_bus, 1); 530 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 531 if (!hcr) 532 break; 533 } 534 if (hcr) { 535 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 536 return (USBD_IOERROR); 537 } 538 539 /* Enable interrupts */ 540 DPRINTFN(1,("ehci_init: enabling\n")); 541 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 542 543 return (USBD_NORMAL_COMPLETION); 544 545 #if 0 546 bad2: 547 ehci_free_sqh(sc, sc->sc_async_head); 548 #endif 549 bad1: 550 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 551 return (err); 552 } 553 554 int 555 ehci_intr(void *v) 556 { 557 ehci_softc_t *sc = v; 558 559 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 560 return (0); 561 562 /* If we get an interrupt while polling, then just ignore it. */ 563 if (sc->sc_bus.use_polling) { 564 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 565 566 if (intrs) 567 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 568 #ifdef DIAGNOSTIC 569 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 570 #endif 571 return (0); 572 } 573 574 return (ehci_intr1(sc)); 575 } 576 577 Static int 578 ehci_intr1(ehci_softc_t *sc) 579 { 580 u_int32_t intrs, eintrs; 581 582 DPRINTFN(20,("ehci_intr1: enter\n")); 583 584 /* In case the interrupt occurs before initialization has completed. */ 585 if (sc == NULL) { 586 #ifdef DIAGNOSTIC 587 printf("ehci_intr1: sc == NULL\n"); 588 #endif 589 return (0); 590 } 591 592 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 593 if (!intrs) 594 return (0); 595 596 eintrs = intrs & sc->sc_eintrs; 597 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 598 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 599 (u_int)eintrs)); 600 if (!eintrs) 601 return (0); 602 603 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 604 sc->sc_bus.intr_context++; 605 sc->sc_bus.no_intrs++; 606 if (eintrs & EHCI_STS_IAA) { 607 DPRINTF(("ehci_intr1: door bell\n")); 608 wakeup(&sc->sc_async_head); 609 eintrs &= ~EHCI_STS_IAA; 610 } 611 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 612 DPRINTFN(5,("ehci_intr1: %s %s\n", 613 eintrs & EHCI_STS_INT ? "INT" : "", 614 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 615 usb_schedsoftintr(&sc->sc_bus); 616 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 617 } 618 if (eintrs & EHCI_STS_HSE) { 619 printf("%s: unrecoverable error, controller halted\n", 620 device_xname(sc->sc_dev)); 621 /* XXX what else */ 622 } 623 if (eintrs & EHCI_STS_PCD) { 624 ehci_pcd(sc, sc->sc_intrxfer); 625 eintrs &= ~EHCI_STS_PCD; 626 } 627 628 sc->sc_bus.intr_context--; 629 630 if (eintrs != 0) { 631 /* Block unprocessed interrupts. */ 632 sc->sc_eintrs &= ~eintrs; 633 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 634 printf("%s: blocking intrs 0x%x\n", 635 device_xname(sc->sc_dev), eintrs); 636 } 637 638 return (1); 639 } 640 641 642 void 643 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 644 { 645 usbd_pipe_handle pipe; 646 u_char *p; 647 int i, m; 648 649 if (xfer == NULL) { 650 /* Just ignore the change. */ 651 return; 652 } 653 654 pipe = xfer->pipe; 655 656 p = KERNADDR(&xfer->dmabuf, 0); 657 m = min(sc->sc_noport, xfer->length * 8 - 1); 658 memset(p, 0, xfer->length); 659 for (i = 1; i <= m; i++) { 660 /* Pick out CHANGE bits from the status reg. */ 661 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 662 p[i/8] |= 1 << (i%8); 663 } 664 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 665 xfer->actlen = xfer->length; 666 xfer->status = USBD_NORMAL_COMPLETION; 667 668 usb_transfer_complete(xfer); 669 } 670 671 void 672 ehci_softintr(void *v) 673 { 674 struct usbd_bus *bus = v; 675 ehci_softc_t *sc = bus->hci_private; 676 struct ehci_xfer *ex, *nextex; 677 678 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 679 sc->sc_bus.intr_context)); 680 681 sc->sc_bus.intr_context++; 682 683 /* 684 * The only explanation I can think of for why EHCI is as brain dead 685 * as UHCI interrupt-wise is that Intel was involved in both. 686 * An interrupt just tells us that something is done, we have no 687 * clue what, so we need to scan through all active transfers. :-( 688 */ 689 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 690 nextex = TAILQ_NEXT(ex, inext); 691 ehci_check_intr(sc, ex); 692 } 693 694 /* Schedule a callout to catch any dropped transactions. */ 695 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 696 !TAILQ_EMPTY(&sc->sc_intrhead)) 697 usb_callout(sc->sc_tmo_intrlist, hz, 698 ehci_intrlist_timeout, sc); 699 700 #ifdef USB_USE_SOFTINTR 701 if (sc->sc_softwake) { 702 sc->sc_softwake = 0; 703 wakeup(&sc->sc_softwake); 704 } 705 #endif /* USB_USE_SOFTINTR */ 706 707 sc->sc_bus.intr_context--; 708 } 709 710 /* Check for an interrupt. */ 711 void 712 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 713 { 714 int attr; 715 716 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 717 718 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 719 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 720 ehci_check_itd_intr(sc, ex); 721 else 722 ehci_check_qh_intr(sc, ex); 723 724 return; 725 } 726 727 void 728 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 729 { 730 ehci_soft_qtd_t *sqtd, *lsqtd; 731 __uint32_t status; 732 733 if (ex->sqtdstart == NULL) { 734 printf("ehci_check_qh_intr: not valid sqtd\n"); 735 return; 736 } 737 738 lsqtd = ex->sqtdend; 739 #ifdef DIAGNOSTIC 740 if (lsqtd == NULL) { 741 printf("ehci_check_qh_intr: lsqtd==0\n"); 742 return; 743 } 744 #endif 745 /* 746 * If the last TD is still active we need to check whether there 747 * is a an error somewhere in the middle, or whether there was a 748 * short packet (SPD and not ACTIVE). 749 */ 750 usb_syncmem(&lsqtd->dma, 751 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 752 sizeof(lsqtd->qtd.qtd_status), 753 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 754 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 755 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 756 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 757 usb_syncmem(&sqtd->dma, 758 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 759 sizeof(sqtd->qtd.qtd_status), 760 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 761 status = le32toh(sqtd->qtd.qtd_status); 762 usb_syncmem(&sqtd->dma, 763 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 764 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 765 /* If there's an active QTD the xfer isn't done. */ 766 if (status & EHCI_QTD_ACTIVE) 767 break; 768 /* Any kind of error makes the xfer done. */ 769 if (status & EHCI_QTD_HALTED) 770 goto done; 771 /* We want short packets, and it is short: it's done */ 772 if (EHCI_QTD_GET_BYTES(status) != 0) 773 goto done; 774 } 775 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 776 ex, ex->sqtdstart)); 777 usb_syncmem(&lsqtd->dma, 778 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 779 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 780 return; 781 } 782 done: 783 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 784 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 785 ehci_idone(ex); 786 } 787 788 void 789 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 790 ehci_soft_itd_t *itd; 791 int i; 792 793 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 794 return; 795 796 if (ex->itdstart == NULL) { 797 printf("ehci_check_itd_intr: not valid itd\n"); 798 return; 799 } 800 801 itd = ex->itdend; 802 #ifdef DIAGNOSTIC 803 if (itd == NULL) { 804 printf("ehci_check_itd_intr: itdend == 0\n"); 805 return; 806 } 807 #endif 808 809 /* 810 * check no active transfers in last itd, meaning we're finished 811 */ 812 813 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 814 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 815 BUS_DMASYNC_POSTREAD); 816 817 for (i = 0; i < 8; i++) { 818 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 819 break; 820 } 821 822 if (i == 8) { 823 goto done; /* All 8 descriptors inactive, it's done */ 824 } 825 826 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 827 ex->itdstart)); 828 return; 829 done: 830 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 831 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 832 ehci_idone(ex); 833 } 834 835 void 836 ehci_idone(struct ehci_xfer *ex) 837 { 838 usbd_xfer_handle xfer = &ex->xfer; 839 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 840 ehci_soft_qtd_t *sqtd, *lsqtd; 841 u_int32_t status = 0, nstatus = 0; 842 int actlen; 843 844 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 845 #ifdef DIAGNOSTIC 846 { 847 int s = splhigh(); 848 if (ex->isdone) { 849 splx(s); 850 #ifdef EHCI_DEBUG 851 printf("ehci_idone: ex is done!\n "); 852 ehci_dump_exfer(ex); 853 #else 854 printf("ehci_idone: ex=%p is done!\n", ex); 855 #endif 856 return; 857 } 858 ex->isdone = 1; 859 splx(s); 860 } 861 #endif 862 if (xfer->status == USBD_CANCELLED || 863 xfer->status == USBD_TIMEOUT) { 864 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 865 return; 866 } 867 868 #ifdef EHCI_DEBUG 869 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 870 if (ehcidebug > 10) 871 ehci_dump_sqtds(ex->sqtdstart); 872 #endif 873 874 /* The transfer is done, compute actual length and status. */ 875 876 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 877 == UE_ISOCHRONOUS) { 878 /* Isoc transfer */ 879 struct ehci_soft_itd *itd; 880 int i, nframes, len, uframes; 881 882 nframes = 0; 883 actlen = 0; 884 885 switch (xfer->pipe->endpoint->edesc->bInterval) { 886 case 0: 887 panic("ehci: isoc xfer suddenly has 0 bInterval, invalid\n"); 888 case 1: uframes = 1; break; 889 case 2: uframes = 2; break; 890 case 3: uframes = 4; break; 891 default: uframes = 8; break; 892 } 893 894 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 895 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 896 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 897 BUS_DMASYNC_POSTREAD); 898 899 for (i = 0; i < 8; i += uframes) { 900 /* XXX - driver didn't fill in the frame full 901 * of uframes. This leads to scheduling 902 * inefficiencies, but working around 903 * this doubles complexity of tracking 904 * an xfer. 905 */ 906 if (nframes >= xfer->nframes) 907 break; 908 909 status = le32toh(itd->itd.itd_ctl[i]); 910 len = EHCI_ITD_GET_LEN(status); 911 if (EHCI_ITD_GET_STATUS(status) != 0) 912 len = 0; /*No valid data on error*/ 913 914 xfer->frlengths[nframes++] = len; 915 actlen += len; 916 } 917 918 if (nframes >= xfer->nframes) 919 break; 920 } 921 922 xfer->actlen = actlen; 923 xfer->status = USBD_NORMAL_COMPLETION; 924 goto end; 925 } 926 927 /* Continue processing xfers using queue heads */ 928 929 lsqtd = ex->sqtdend; 930 actlen = 0; 931 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 932 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 933 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 934 nstatus = le32toh(sqtd->qtd.qtd_status); 935 if (nstatus & EHCI_QTD_ACTIVE) 936 break; 937 938 status = nstatus; 939 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 940 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 941 } 942 943 944 /* 945 * If there are left over TDs we need to update the toggle. 946 * The default pipe doesn't need it since control transfers 947 * start the toggle at 0 every time. 948 * For a short transfer we need to update the toggle for the missing 949 * packets within the qTD. 950 */ 951 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 952 xfer->pipe->device->default_pipe != xfer->pipe) { 953 DPRINTFN(2, ("ehci_idone: need toggle update " 954 "status=%08x nstatus=%08x\n", status, nstatus)); 955 #if 0 956 ehci_dump_sqh(epipe->sqh); 957 ehci_dump_sqtds(ex->sqtdstart); 958 #endif 959 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 960 } 961 962 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 963 xfer->length, actlen, status)); 964 xfer->actlen = actlen; 965 if (status & EHCI_QTD_HALTED) { 966 #ifdef EHCI_DEBUG 967 char sbuf[128]; 968 969 bitmask_snprintf((u_int32_t)status, 970 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 971 "\3MISSED\1PINGSTATE", sbuf, sizeof(sbuf)); 972 973 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 974 "status 0x%s\n", 975 xfer->pipe->device->address, 976 xfer->pipe->endpoint->edesc->bEndpointAddress, 977 sbuf)); 978 if (ehcidebug > 2) { 979 ehci_dump_sqh(epipe->sqh); 980 ehci_dump_sqtds(ex->sqtdstart); 981 } 982 #endif 983 /* low&full speed has an extra error flag */ 984 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 985 EHCI_QH_SPEED_HIGH) 986 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 987 else 988 status &= EHCI_QTD_STATERRS; 989 if (status == 0) /* no other errors means a stall */ { 990 xfer->status = USBD_STALLED; 991 } else { 992 xfer->status = USBD_IOERROR; /* more info XXX */ 993 } 994 /* XXX need to reset TT on missed microframe */ 995 if (status & EHCI_QTD_MISSEDMICRO) { 996 ehci_softc_t *sc = 997 xfer->pipe->device->bus->hci_private; 998 999 printf("%s: missed microframe, TT reset not " 1000 "implemented, hub might be inoperational\n", 1001 device_xname(sc->sc_dev)); 1002 } 1003 } else { 1004 xfer->status = USBD_NORMAL_COMPLETION; 1005 } 1006 1007 end: 1008 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1009 * during this call, before methods->done is called: dma sync required 1010 * beforehand? */ 1011 usb_transfer_complete(xfer); 1012 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1013 } 1014 1015 /* 1016 * Wait here until controller claims to have an interrupt. 1017 * Then call ehci_intr and return. Use timeout to avoid waiting 1018 * too long. 1019 */ 1020 void 1021 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1022 { 1023 int timo; 1024 u_int32_t intrs; 1025 1026 xfer->status = USBD_IN_PROGRESS; 1027 for (timo = xfer->timeout; timo >= 0; timo--) { 1028 usb_delay_ms(&sc->sc_bus, 1); 1029 if (sc->sc_dying) 1030 break; 1031 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1032 sc->sc_eintrs; 1033 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1034 #ifdef EHCI_DEBUG 1035 if (ehcidebug > 15) 1036 ehci_dump_regs(sc); 1037 #endif 1038 if (intrs) { 1039 ehci_intr1(sc); 1040 if (xfer->status != USBD_IN_PROGRESS) 1041 return; 1042 } 1043 } 1044 1045 /* Timeout */ 1046 DPRINTF(("ehci_waitintr: timeout\n")); 1047 xfer->status = USBD_TIMEOUT; 1048 usb_transfer_complete(xfer); 1049 /* XXX should free TD */ 1050 } 1051 1052 void 1053 ehci_poll(struct usbd_bus *bus) 1054 { 1055 ehci_softc_t *sc = bus->hci_private; 1056 #ifdef EHCI_DEBUG 1057 static int last; 1058 int new; 1059 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1060 if (new != last) { 1061 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1062 last = new; 1063 } 1064 #endif 1065 1066 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1067 ehci_intr1(sc); 1068 } 1069 1070 void 1071 ehci_childdet(device_t self, device_t child) 1072 { 1073 struct ehci_softc *sc = device_private(self); 1074 1075 KASSERT(sc->sc_child == child); 1076 sc->sc_child = NULL; 1077 } 1078 1079 int 1080 ehci_detach(struct ehci_softc *sc, int flags) 1081 { 1082 int rv = 0; 1083 1084 if (sc->sc_child != NULL) 1085 rv = config_detach(sc->sc_child, flags); 1086 1087 if (rv != 0) 1088 return (rv); 1089 1090 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 1091 1092 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1093 1094 /* XXX free other data structures XXX */ 1095 mutex_destroy(&sc->sc_doorbell_lock); 1096 mutex_destroy(&sc->sc_intrhead_lock); 1097 1098 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1099 1100 return (rv); 1101 } 1102 1103 1104 int 1105 ehci_activate(device_t self, enum devact act) 1106 { 1107 struct ehci_softc *sc = device_private(self); 1108 int rv = 0; 1109 1110 switch (act) { 1111 case DVACT_ACTIVATE: 1112 return (EOPNOTSUPP); 1113 1114 case DVACT_DEACTIVATE: 1115 sc->sc_dying = 1; 1116 if (sc->sc_child != NULL) 1117 rv = config_deactivate(sc->sc_child); 1118 break; 1119 } 1120 return (rv); 1121 } 1122 1123 /* 1124 * Handle suspend/resume. 1125 * 1126 * We need to switch to polling mode here, because this routine is 1127 * called from an interrupt context. This is all right since we 1128 * are almost suspended anyway. 1129 * 1130 * Note that this power handler isn't to be registered directly; the 1131 * bus glue needs to call out to it. 1132 */ 1133 bool 1134 ehci_suspend(device_t dv PMF_FN_ARGS) 1135 { 1136 ehci_softc_t *sc = device_private(dv); 1137 int i, s; 1138 uint32_t cmd, hcr; 1139 1140 s = splhardusb(); 1141 1142 sc->sc_bus.use_polling++; 1143 1144 for (i = 1; i <= sc->sc_noport; i++) { 1145 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1146 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1147 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1148 } 1149 1150 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1151 1152 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1153 EOWRITE4(sc, EHCI_USBCMD, cmd); 1154 1155 for (i = 0; i < 100; i++) { 1156 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1157 if (hcr == 0) 1158 break; 1159 1160 usb_delay_ms(&sc->sc_bus, 1); 1161 } 1162 if (hcr != 0) 1163 printf("%s: reset timeout\n", device_xname(dv)); 1164 1165 cmd &= ~EHCI_CMD_RS; 1166 EOWRITE4(sc, EHCI_USBCMD, cmd); 1167 1168 for (i = 0; i < 100; i++) { 1169 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1170 if (hcr == EHCI_STS_HCH) 1171 break; 1172 1173 usb_delay_ms(&sc->sc_bus, 1); 1174 } 1175 if (hcr != EHCI_STS_HCH) 1176 printf("%s: config timeout\n", device_xname(dv)); 1177 1178 sc->sc_bus.use_polling--; 1179 splx(s); 1180 1181 return true; 1182 } 1183 1184 bool 1185 ehci_resume(device_t dv PMF_FN_ARGS) 1186 { 1187 ehci_softc_t *sc = device_private(dv); 1188 int i; 1189 uint32_t cmd, hcr; 1190 1191 /* restore things in case the bios sucks */ 1192 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1193 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1194 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1195 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1196 1197 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1198 1199 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1200 1201 hcr = 0; 1202 for (i = 1; i <= sc->sc_noport; i++) { 1203 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1204 if ((cmd & EHCI_PS_PO) == 0 && 1205 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1206 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1207 hcr = 1; 1208 } 1209 } 1210 1211 if (hcr) { 1212 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1213 1214 for (i = 1; i <= sc->sc_noport; i++) { 1215 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1216 if ((cmd & EHCI_PS_PO) == 0 && 1217 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1218 EOWRITE4(sc, EHCI_PORTSC(i), 1219 cmd & ~EHCI_PS_FPR); 1220 } 1221 } 1222 1223 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1224 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1225 1226 for (i = 0; i < 100; i++) { 1227 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1228 if (hcr != EHCI_STS_HCH) 1229 break; 1230 1231 usb_delay_ms(&sc->sc_bus, 1); 1232 } 1233 if (hcr == EHCI_STS_HCH) 1234 printf("%s: config timeout\n", device_xname(dv)); 1235 1236 return true; 1237 } 1238 1239 /* 1240 * Shut down the controller when the system is going down. 1241 */ 1242 bool 1243 ehci_shutdown(device_t self, int flags) 1244 { 1245 ehci_softc_t *sc = device_private(self); 1246 1247 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1248 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1249 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1250 return true; 1251 } 1252 1253 usbd_status 1254 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1255 { 1256 struct ehci_softc *sc = bus->hci_private; 1257 usbd_status err; 1258 1259 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1260 if (err == USBD_NOMEM) 1261 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1262 #ifdef EHCI_DEBUG 1263 if (err) 1264 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1265 #endif 1266 return (err); 1267 } 1268 1269 void 1270 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1271 { 1272 struct ehci_softc *sc = bus->hci_private; 1273 1274 if (dma->block->flags & USB_DMA_RESERVE) { 1275 usb_reserve_freem(&sc->sc_dma_reserve, 1276 dma); 1277 return; 1278 } 1279 usb_freemem(&sc->sc_bus, dma); 1280 } 1281 1282 usbd_xfer_handle 1283 ehci_allocx(struct usbd_bus *bus) 1284 { 1285 struct ehci_softc *sc = bus->hci_private; 1286 usbd_xfer_handle xfer; 1287 1288 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1289 if (xfer != NULL) { 1290 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1291 #ifdef DIAGNOSTIC 1292 if (xfer->busy_free != XFER_FREE) { 1293 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1294 xfer->busy_free); 1295 } 1296 #endif 1297 } else { 1298 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1299 } 1300 if (xfer != NULL) { 1301 memset(xfer, 0, sizeof(struct ehci_xfer)); 1302 #ifdef DIAGNOSTIC 1303 EXFER(xfer)->isdone = 1; 1304 xfer->busy_free = XFER_BUSY; 1305 #endif 1306 } 1307 return (xfer); 1308 } 1309 1310 void 1311 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1312 { 1313 struct ehci_softc *sc = bus->hci_private; 1314 1315 #ifdef DIAGNOSTIC 1316 if (xfer->busy_free != XFER_BUSY) { 1317 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1318 xfer->busy_free); 1319 } 1320 xfer->busy_free = XFER_FREE; 1321 if (!EXFER(xfer)->isdone) { 1322 printf("ehci_freex: !isdone\n"); 1323 } 1324 #endif 1325 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1326 } 1327 1328 Static void 1329 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1330 { 1331 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1332 1333 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1334 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1335 #ifdef USB_DEBUG 1336 if (ehcidebug) 1337 usbd_dump_pipe(pipe); 1338 #endif 1339 epipe->nexttoggle = 0; 1340 } 1341 1342 Static void 1343 ehci_noop(usbd_pipe_handle pipe) 1344 { 1345 } 1346 1347 #ifdef EHCI_DEBUG 1348 void 1349 ehci_dump_regs(ehci_softc_t *sc) 1350 { 1351 int i; 1352 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1353 EOREAD4(sc, EHCI_USBCMD), 1354 EOREAD4(sc, EHCI_USBSTS), 1355 EOREAD4(sc, EHCI_USBINTR)); 1356 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1357 EOREAD4(sc, EHCI_FRINDEX), 1358 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1359 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1360 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1361 for (i = 1; i <= sc->sc_noport; i++) 1362 printf("port %d status=0x%08x\n", i, 1363 EOREAD4(sc, EHCI_PORTSC(i))); 1364 } 1365 1366 /* 1367 * Unused function - this is meant to be called from a kernel 1368 * debugger. 1369 */ 1370 void 1371 ehci_dump() 1372 { 1373 ehci_dump_regs(theehci); 1374 } 1375 1376 void 1377 ehci_dump_link(ehci_link_t link, int type) 1378 { 1379 link = le32toh(link); 1380 printf("0x%08x", link); 1381 if (link & EHCI_LINK_TERMINATE) 1382 printf("<T>"); 1383 else { 1384 printf("<"); 1385 if (type) { 1386 switch (EHCI_LINK_TYPE(link)) { 1387 case EHCI_LINK_ITD: printf("ITD"); break; 1388 case EHCI_LINK_QH: printf("QH"); break; 1389 case EHCI_LINK_SITD: printf("SITD"); break; 1390 case EHCI_LINK_FSTN: printf("FSTN"); break; 1391 } 1392 } 1393 printf(">"); 1394 } 1395 } 1396 1397 void 1398 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1399 { 1400 int i; 1401 u_int32_t stop; 1402 1403 stop = 0; 1404 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1405 ehci_dump_sqtd(sqtd); 1406 usb_syncmem(&sqtd->dma, 1407 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1408 sizeof(sqtd->qtd), 1409 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1410 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1411 usb_syncmem(&sqtd->dma, 1412 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1413 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1414 } 1415 if (sqtd) 1416 printf("dump aborted, too many TDs\n"); 1417 } 1418 1419 void 1420 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1421 { 1422 usb_syncmem(&sqtd->dma, sqtd->offs, 1423 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1424 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1425 ehci_dump_qtd(&sqtd->qtd); 1426 usb_syncmem(&sqtd->dma, sqtd->offs, 1427 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1428 } 1429 1430 void 1431 ehci_dump_qtd(ehci_qtd_t *qtd) 1432 { 1433 u_int32_t s; 1434 char sbuf[128]; 1435 1436 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1437 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1438 printf("\n"); 1439 s = le32toh(qtd->qtd_status); 1440 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1441 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1442 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1443 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1444 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1445 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1446 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1447 EHCI_QTD_GET_PID(s), sbuf); 1448 for (s = 0; s < 5; s++) 1449 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1450 } 1451 1452 void 1453 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1454 { 1455 ehci_qh_t *qh = &sqh->qh; 1456 u_int32_t endp, endphub; 1457 1458 usb_syncmem(&sqh->dma, sqh->offs, 1459 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1460 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1461 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1462 endp = le32toh(qh->qh_endp); 1463 printf(" endp=0x%08x\n", endp); 1464 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1465 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1466 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1467 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1468 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1469 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1470 EHCI_QH_GET_NRL(endp)); 1471 endphub = le32toh(qh->qh_endphub); 1472 printf(" endphub=0x%08x\n", endphub); 1473 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1474 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1475 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1476 EHCI_QH_GET_MULT(endphub)); 1477 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1478 printf("Overlay qTD:\n"); 1479 ehci_dump_qtd(&qh->qh_qtd); 1480 usb_syncmem(&sqh->dma, sqh->offs, 1481 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1482 } 1483 1484 #if notyet 1485 void 1486 ehci_dump_itd(struct ehci_soft_itd *itd) 1487 { 1488 ehci_isoc_trans_t t; 1489 ehci_isoc_bufr_ptr_t b, b2, b3; 1490 int i; 1491 1492 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1493 1494 for (i = 0; i < 8;i++) { 1495 t = le32toh(itd->itd.itd_ctl[i]); 1496 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1497 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1498 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1499 EHCI_ITD_GET_OFFS(t)); 1500 } 1501 printf("ITDbufr: "); 1502 for (i = 0; i < 7; i++) 1503 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1504 1505 b = le32toh(itd->itd.itd_bufr[0]); 1506 b2 = le32toh(itd->itd.itd_bufr[1]); 1507 b3 = le32toh(itd->itd.itd_bufr[2]); 1508 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1509 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1510 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1511 } 1512 1513 void 1514 ehci_dump_sitd(struct ehci_soft_itd *itd) 1515 { 1516 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1517 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1518 itd->xfer_next, itd->physaddr, itd->slot); 1519 } 1520 #endif 1521 1522 #ifdef DIAGNOSTIC 1523 void 1524 ehci_dump_exfer(struct ehci_xfer *ex) 1525 { 1526 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1527 } 1528 #endif 1529 #endif 1530 1531 usbd_status 1532 ehci_open(usbd_pipe_handle pipe) 1533 { 1534 usbd_device_handle dev = pipe->device; 1535 ehci_softc_t *sc = dev->bus->hci_private; 1536 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1537 u_int8_t addr = dev->address; 1538 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1539 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1540 ehci_soft_qh_t *sqh; 1541 usbd_status err; 1542 int s; 1543 int ival, speed, naks; 1544 int hshubaddr, hshubport; 1545 1546 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1547 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1548 1549 if (dev->myhsport) { 1550 hshubaddr = dev->myhsport->parent->address; 1551 hshubport = dev->myhsport->portno; 1552 } else { 1553 hshubaddr = 0; 1554 hshubport = 0; 1555 } 1556 1557 if (sc->sc_dying) 1558 return (USBD_IOERROR); 1559 1560 epipe->nexttoggle = 0; 1561 1562 if (addr == sc->sc_addr) { 1563 switch (ed->bEndpointAddress) { 1564 case USB_CONTROL_ENDPOINT: 1565 pipe->methods = &ehci_root_ctrl_methods; 1566 break; 1567 case UE_DIR_IN | EHCI_INTR_ENDPT: 1568 pipe->methods = &ehci_root_intr_methods; 1569 break; 1570 default: 1571 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1572 ed->bEndpointAddress)); 1573 return (USBD_INVAL); 1574 } 1575 return (USBD_NORMAL_COMPLETION); 1576 } 1577 1578 /* XXX All this stuff is only valid for async. */ 1579 switch (dev->speed) { 1580 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1581 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1582 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1583 default: panic("ehci_open: bad device speed %d", dev->speed); 1584 } 1585 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1586 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1587 "isoc endpoint.\n"); 1588 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1589 "attached to a USB2 hub, and transaction translations are " 1590 "not yet supported.\n"); 1591 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1592 "root hub instead.\n"); 1593 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1594 hshubaddr, hshubport)); 1595 return USBD_INVAL; 1596 } 1597 1598 naks = 8; /* XXX */ 1599 1600 /* Allocate sqh for everything, save isoc xfers */ 1601 if (xfertype != UE_ISOCHRONOUS) { 1602 sqh = ehci_alloc_sqh(sc); 1603 if (sqh == NULL) 1604 return (USBD_NOMEM); 1605 /* qh_link filled when the QH is added */ 1606 sqh->qh.qh_endp = htole32( 1607 EHCI_QH_SET_ADDR(addr) | 1608 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1609 EHCI_QH_SET_EPS(speed) | 1610 EHCI_QH_DTC | 1611 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1612 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1613 EHCI_QH_CTL : 0) | 1614 EHCI_QH_SET_NRL(naks) 1615 ); 1616 sqh->qh.qh_endphub = htole32( 1617 EHCI_QH_SET_MULT(1) | 1618 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1619 ); 1620 if (speed != EHCI_QH_SPEED_HIGH) 1621 sqh->qh.qh_endphub |= htole32( 1622 EHCI_QH_SET_PORT(hshubport) | 1623 EHCI_QH_SET_HUBA(hshubaddr) | 1624 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1625 ); 1626 sqh->qh.qh_curqtd = EHCI_NULL; 1627 /* Fill the overlay qTD */ 1628 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1629 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1630 sqh->qh.qh_qtd.qtd_status = htole32(0); 1631 1632 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1633 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1634 epipe->sqh = sqh; 1635 } else { 1636 sqh = NULL; 1637 } /*xfertype == UE_ISOC*/ 1638 1639 switch (xfertype) { 1640 case UE_CONTROL: 1641 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1642 0, &epipe->u.ctl.reqdma); 1643 #ifdef EHCI_DEBUG 1644 if (err) 1645 printf("ehci_open: usb_allocmem()=%d\n", err); 1646 #endif 1647 if (err) 1648 goto bad; 1649 pipe->methods = &ehci_device_ctrl_methods; 1650 s = splusb(); 1651 ehci_add_qh(sqh, sc->sc_async_head); 1652 splx(s); 1653 break; 1654 case UE_BULK: 1655 pipe->methods = &ehci_device_bulk_methods; 1656 s = splusb(); 1657 ehci_add_qh(sqh, sc->sc_async_head); 1658 splx(s); 1659 break; 1660 case UE_INTERRUPT: 1661 pipe->methods = &ehci_device_intr_methods; 1662 ival = pipe->interval; 1663 if (ival == USBD_DEFAULT_INTERVAL) { 1664 if (speed == EHCI_QH_SPEED_HIGH) { 1665 if (ed->bInterval > 16) { 1666 /* 1667 * illegal with high-speed, but there 1668 * were documentation bugs in the spec, 1669 * so be generous 1670 */ 1671 ival = 256; 1672 } else 1673 ival = (1 << (ed->bInterval - 1)) / 8; 1674 } else 1675 ival = ed->bInterval; 1676 } 1677 err = ehci_device_setintr(sc, sqh, ival); 1678 if (err) 1679 goto bad; 1680 break; 1681 case UE_ISOCHRONOUS: 1682 pipe->methods = &ehci_device_isoc_methods; 1683 if (ed->bInterval == 0 || ed->bInterval > 16) { 1684 printf("ehci: opening pipe with invalid bInterval\n"); 1685 err = USBD_INVAL; 1686 goto bad; 1687 } 1688 if (UGETW(ed->wMaxPacketSize) == 0) { 1689 printf("ehci: zero length endpoint open request\n"); 1690 err = USBD_INVAL; 1691 goto bad; 1692 } 1693 epipe->u.isoc.next_frame = 0; 1694 epipe->u.isoc.cur_xfers = 0; 1695 break; 1696 default: 1697 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1698 err = USBD_INVAL; 1699 goto bad; 1700 } 1701 return (USBD_NORMAL_COMPLETION); 1702 1703 bad: 1704 if (sqh != NULL) 1705 ehci_free_sqh(sc, sqh); 1706 return (err); 1707 } 1708 1709 /* 1710 * Add an ED to the schedule. Called at splusb(). 1711 */ 1712 void 1713 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1714 { 1715 SPLUSBCHECK; 1716 1717 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1718 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1719 sqh->next = head->next; 1720 sqh->qh.qh_link = head->qh.qh_link; 1721 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1722 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1723 head->next = sqh; 1724 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1725 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1726 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1727 1728 #ifdef EHCI_DEBUG 1729 if (ehcidebug > 5) { 1730 printf("ehci_add_qh:\n"); 1731 ehci_dump_sqh(sqh); 1732 } 1733 #endif 1734 } 1735 1736 /* 1737 * Remove an ED from the schedule. Called at splusb(). 1738 */ 1739 void 1740 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1741 { 1742 ehci_soft_qh_t *p; 1743 1744 SPLUSBCHECK; 1745 /* XXX */ 1746 for (p = head; p != NULL && p->next != sqh; p = p->next) 1747 ; 1748 if (p == NULL) 1749 panic("ehci_rem_qh: ED not found"); 1750 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1751 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1752 p->next = sqh->next; 1753 p->qh.qh_link = sqh->qh.qh_link; 1754 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1755 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1756 1757 ehci_sync_hc(sc); 1758 } 1759 1760 void 1761 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1762 { 1763 int i; 1764 u_int32_t status; 1765 1766 /* Save toggle bit and ping status. */ 1767 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1768 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1769 status = sqh->qh.qh_qtd.qtd_status & 1770 htole32(EHCI_QTD_TOGGLE_MASK | 1771 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1772 /* Set HALTED to make hw leave it alone. */ 1773 sqh->qh.qh_qtd.qtd_status = 1774 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1775 usb_syncmem(&sqh->dma, 1776 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1777 sizeof(sqh->qh.qh_qtd.qtd_status), 1778 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1779 sqh->qh.qh_curqtd = 0; 1780 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1781 sqh->qh.qh_qtd.qtd_altnext = 0; 1782 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1783 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1784 sqh->sqtd = sqtd; 1785 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1786 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1787 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1788 sqh->qh.qh_qtd.qtd_status = status; 1789 usb_syncmem(&sqh->dma, 1790 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1791 sizeof(sqh->qh.qh_qtd.qtd_status), 1792 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1793 } 1794 1795 /* 1796 * Ensure that the HC has released all references to the QH. We do this 1797 * by asking for a Async Advance Doorbell interrupt and then we wait for 1798 * the interrupt. 1799 * To make this easier we first obtain exclusive use of the doorbell. 1800 */ 1801 void 1802 ehci_sync_hc(ehci_softc_t *sc) 1803 { 1804 int s, error; 1805 1806 if (sc->sc_dying) { 1807 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1808 return; 1809 } 1810 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1811 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */ 1812 s = splhardusb(); 1813 /* ask for doorbell */ 1814 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1815 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1816 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1817 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1818 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1819 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1820 splx(s); 1821 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */ 1822 #ifdef DIAGNOSTIC 1823 if (error) 1824 printf("ehci_sync_hc: tsleep() = %d\n", error); 1825 #endif 1826 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1827 } 1828 1829 /*Call at splusb*/ 1830 void 1831 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1832 { 1833 struct ehci_soft_itd *itd, *prev; 1834 1835 prev = NULL; 1836 1837 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1838 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1839 1840 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1841 prev = itd->u.frame_list.prev; 1842 /* Unlink itd from hardware chain, or frame array */ 1843 if (prev == NULL) { /* We're at the table head */ 1844 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1845 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1846 usb_syncmem(&sc->sc_fldma, 1847 sizeof(ehci_link_t) * itd->slot, 1848 sizeof(ehci_link_t), 1849 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1850 1851 if (itd->u.frame_list.next != NULL) 1852 itd->u.frame_list.next->u.frame_list.prev = NULL; 1853 } else { 1854 /* XXX this part is untested... */ 1855 prev->itd.itd_next = itd->itd.itd_next; 1856 usb_syncmem(&itd->dma, 1857 itd->offs + offsetof(ehci_itd_t, itd_next), 1858 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1859 1860 prev->u.frame_list.next = itd->u.frame_list.next; 1861 if (itd->u.frame_list.next != NULL) 1862 itd->u.frame_list.next->u.frame_list.prev = prev; 1863 } 1864 } 1865 1866 prev = NULL; 1867 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1868 if (prev != NULL) 1869 ehci_free_itd(sc, prev); 1870 prev = itd; 1871 } 1872 if (prev) 1873 ehci_free_itd(sc, prev); 1874 exfer->itdstart = NULL; 1875 exfer->itdend = NULL; 1876 } 1877 1878 /***********/ 1879 1880 /* 1881 * Data structures and routines to emulate the root hub. 1882 */ 1883 Static usb_device_descriptor_t ehci_devd = { 1884 USB_DEVICE_DESCRIPTOR_SIZE, 1885 UDESC_DEVICE, /* type */ 1886 {0x00, 0x02}, /* USB version */ 1887 UDCLASS_HUB, /* class */ 1888 UDSUBCLASS_HUB, /* subclass */ 1889 UDPROTO_HSHUBSTT, /* protocol */ 1890 64, /* max packet */ 1891 {0},{0},{0x00,0x01}, /* device id */ 1892 1,2,0, /* string indicies */ 1893 1 /* # of configurations */ 1894 }; 1895 1896 Static const usb_device_qualifier_t ehci_odevd = { 1897 USB_DEVICE_DESCRIPTOR_SIZE, 1898 UDESC_DEVICE_QUALIFIER, /* type */ 1899 {0x00, 0x02}, /* USB version */ 1900 UDCLASS_HUB, /* class */ 1901 UDSUBCLASS_HUB, /* subclass */ 1902 UDPROTO_FSHUB, /* protocol */ 1903 64, /* max packet */ 1904 1, /* # of configurations */ 1905 0 1906 }; 1907 1908 Static const usb_config_descriptor_t ehci_confd = { 1909 USB_CONFIG_DESCRIPTOR_SIZE, 1910 UDESC_CONFIG, 1911 {USB_CONFIG_DESCRIPTOR_SIZE + 1912 USB_INTERFACE_DESCRIPTOR_SIZE + 1913 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1914 1, 1915 1, 1916 0, 1917 UC_ATTR_MBO | UC_SELF_POWERED, 1918 0 /* max power */ 1919 }; 1920 1921 Static const usb_interface_descriptor_t ehci_ifcd = { 1922 USB_INTERFACE_DESCRIPTOR_SIZE, 1923 UDESC_INTERFACE, 1924 0, 1925 0, 1926 1, 1927 UICLASS_HUB, 1928 UISUBCLASS_HUB, 1929 UIPROTO_HSHUBSTT, 1930 0 1931 }; 1932 1933 Static const usb_endpoint_descriptor_t ehci_endpd = { 1934 USB_ENDPOINT_DESCRIPTOR_SIZE, 1935 UDESC_ENDPOINT, 1936 UE_DIR_IN | EHCI_INTR_ENDPT, 1937 UE_INTERRUPT, 1938 {8, 0}, /* max packet */ 1939 12 1940 }; 1941 1942 Static const usb_hub_descriptor_t ehci_hubd = { 1943 USB_HUB_DESCRIPTOR_SIZE, 1944 UDESC_HUB, 1945 0, 1946 {0,0}, 1947 0, 1948 0, 1949 {""}, 1950 {""}, 1951 }; 1952 1953 /* 1954 * Simulate a hardware hub by handling all the necessary requests. 1955 */ 1956 Static usbd_status 1957 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1958 { 1959 usbd_status err; 1960 1961 /* Insert last in queue. */ 1962 err = usb_insert_transfer(xfer); 1963 if (err) 1964 return (err); 1965 1966 /* Pipe isn't running, start first */ 1967 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1968 } 1969 1970 Static usbd_status 1971 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1972 { 1973 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1974 usb_device_request_t *req; 1975 void *buf = NULL; 1976 int port, i; 1977 int s, len, value, index, l, totlen = 0; 1978 usb_port_status_t ps; 1979 usb_hub_descriptor_t hubd; 1980 usbd_status err; 1981 u_int32_t v; 1982 1983 if (sc->sc_dying) 1984 return (USBD_IOERROR); 1985 1986 #ifdef DIAGNOSTIC 1987 if (!(xfer->rqflags & URQ_REQUEST)) 1988 /* XXX panic */ 1989 return (USBD_INVAL); 1990 #endif 1991 req = &xfer->request; 1992 1993 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1994 req->bmRequestType, req->bRequest)); 1995 1996 len = UGETW(req->wLength); 1997 value = UGETW(req->wValue); 1998 index = UGETW(req->wIndex); 1999 2000 if (len != 0) 2001 buf = KERNADDR(&xfer->dmabuf, 0); 2002 2003 #define C(x,y) ((x) | ((y) << 8)) 2004 switch(C(req->bRequest, req->bmRequestType)) { 2005 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2006 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2007 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2008 /* 2009 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2010 * for the integrated root hub. 2011 */ 2012 break; 2013 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2014 if (len > 0) { 2015 *(u_int8_t *)buf = sc->sc_conf; 2016 totlen = 1; 2017 } 2018 break; 2019 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2020 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2021 if (len == 0) 2022 break; 2023 switch(value >> 8) { 2024 case UDESC_DEVICE: 2025 if ((value & 0xff) != 0) { 2026 err = USBD_IOERROR; 2027 goto ret; 2028 } 2029 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2030 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2031 memcpy(buf, &ehci_devd, l); 2032 break; 2033 /* 2034 * We can't really operate at another speed, but the spec says 2035 * we need this descriptor. 2036 */ 2037 case UDESC_DEVICE_QUALIFIER: 2038 if ((value & 0xff) != 0) { 2039 err = USBD_IOERROR; 2040 goto ret; 2041 } 2042 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2043 memcpy(buf, &ehci_odevd, l); 2044 break; 2045 /* 2046 * We can't really operate at another speed, but the spec says 2047 * we need this descriptor. 2048 */ 2049 case UDESC_OTHER_SPEED_CONFIGURATION: 2050 case UDESC_CONFIG: 2051 if ((value & 0xff) != 0) { 2052 err = USBD_IOERROR; 2053 goto ret; 2054 } 2055 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2056 memcpy(buf, &ehci_confd, l); 2057 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2058 value >> 8; 2059 buf = (char *)buf + l; 2060 len -= l; 2061 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2062 totlen += l; 2063 memcpy(buf, &ehci_ifcd, l); 2064 buf = (char *)buf + l; 2065 len -= l; 2066 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2067 totlen += l; 2068 memcpy(buf, &ehci_endpd, l); 2069 break; 2070 case UDESC_STRING: 2071 #define sd ((usb_string_descriptor_t *)buf) 2072 switch (value & 0xff) { 2073 case 0: /* Language table */ 2074 totlen = usb_makelangtbl(sd, len); 2075 break; 2076 case 1: /* Vendor */ 2077 totlen = usb_makestrdesc(sd, len, 2078 sc->sc_vendor); 2079 break; 2080 case 2: /* Product */ 2081 totlen = usb_makestrdesc(sd, len, 2082 "EHCI root hub"); 2083 break; 2084 } 2085 #undef sd 2086 break; 2087 default: 2088 err = USBD_IOERROR; 2089 goto ret; 2090 } 2091 break; 2092 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2093 if (len > 0) { 2094 *(u_int8_t *)buf = 0; 2095 totlen = 1; 2096 } 2097 break; 2098 case C(UR_GET_STATUS, UT_READ_DEVICE): 2099 if (len > 1) { 2100 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2101 totlen = 2; 2102 } 2103 break; 2104 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2105 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2106 if (len > 1) { 2107 USETW(((usb_status_t *)buf)->wStatus, 0); 2108 totlen = 2; 2109 } 2110 break; 2111 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2112 if (value >= USB_MAX_DEVICES) { 2113 err = USBD_IOERROR; 2114 goto ret; 2115 } 2116 sc->sc_addr = value; 2117 break; 2118 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2119 if (value != 0 && value != 1) { 2120 err = USBD_IOERROR; 2121 goto ret; 2122 } 2123 sc->sc_conf = value; 2124 break; 2125 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2126 break; 2127 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2128 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2129 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2130 err = USBD_IOERROR; 2131 goto ret; 2132 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2133 break; 2134 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2135 break; 2136 /* Hub requests */ 2137 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2138 break; 2139 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2140 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2141 "port=%d feature=%d\n", 2142 index, value)); 2143 if (index < 1 || index > sc->sc_noport) { 2144 err = USBD_IOERROR; 2145 goto ret; 2146 } 2147 port = EHCI_PORTSC(index); 2148 v = EOREAD4(sc, port); 2149 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2150 v &= ~EHCI_PS_CLEAR; 2151 switch(value) { 2152 case UHF_PORT_ENABLE: 2153 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2154 break; 2155 case UHF_PORT_SUSPEND: 2156 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2157 break; 2158 v &= ~EHCI_PS_SUSP; 2159 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2160 /* see USB2 spec ch. 7.1.7.7 */ 2161 usb_delay_ms(&sc->sc_bus, 20); 2162 EOWRITE4(sc, port, v); 2163 usb_delay_ms(&sc->sc_bus, 2); 2164 #ifdef DEBUG 2165 v = EOREAD4(sc, port); 2166 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2167 printf("ehci: resume failed: %x\n", v); 2168 #endif 2169 break; 2170 case UHF_PORT_POWER: 2171 if (sc->sc_hasppc) 2172 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2173 break; 2174 case UHF_PORT_TEST: 2175 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2176 "%d\n", index)); 2177 break; 2178 case UHF_PORT_INDICATOR: 2179 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2180 "%d\n", index)); 2181 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2182 break; 2183 case UHF_C_PORT_CONNECTION: 2184 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2185 break; 2186 case UHF_C_PORT_ENABLE: 2187 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2188 break; 2189 case UHF_C_PORT_SUSPEND: 2190 /* how? */ 2191 break; 2192 case UHF_C_PORT_OVER_CURRENT: 2193 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2194 break; 2195 case UHF_C_PORT_RESET: 2196 sc->sc_isreset[index] = 0; 2197 break; 2198 default: 2199 err = USBD_IOERROR; 2200 goto ret; 2201 } 2202 #if 0 2203 switch(value) { 2204 case UHF_C_PORT_CONNECTION: 2205 case UHF_C_PORT_ENABLE: 2206 case UHF_C_PORT_SUSPEND: 2207 case UHF_C_PORT_OVER_CURRENT: 2208 case UHF_C_PORT_RESET: 2209 default: 2210 break; 2211 } 2212 #endif 2213 break; 2214 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2215 if (len == 0) 2216 break; 2217 if ((value & 0xff) != 0) { 2218 err = USBD_IOERROR; 2219 goto ret; 2220 } 2221 hubd = ehci_hubd; 2222 hubd.bNbrPorts = sc->sc_noport; 2223 v = EOREAD4(sc, EHCI_HCSPARAMS); 2224 USETW(hubd.wHubCharacteristics, 2225 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2226 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2227 ? UHD_PORT_IND : 0); 2228 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2229 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2230 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2231 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2232 l = min(len, hubd.bDescLength); 2233 totlen = l; 2234 memcpy(buf, &hubd, l); 2235 break; 2236 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2237 if (len != 4) { 2238 err = USBD_IOERROR; 2239 goto ret; 2240 } 2241 memset(buf, 0, len); /* ? XXX */ 2242 totlen = len; 2243 break; 2244 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2245 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2246 index)); 2247 if (index < 1 || index > sc->sc_noport) { 2248 err = USBD_IOERROR; 2249 goto ret; 2250 } 2251 if (len != 4) { 2252 err = USBD_IOERROR; 2253 goto ret; 2254 } 2255 v = EOREAD4(sc, EHCI_PORTSC(index)); 2256 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2257 v)); 2258 i = UPS_HIGH_SPEED; 2259 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2260 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2261 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2262 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2263 if (v & EHCI_PS_PR) i |= UPS_RESET; 2264 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2265 USETW(ps.wPortStatus, i); 2266 i = 0; 2267 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2268 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2269 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2270 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2271 USETW(ps.wPortChange, i); 2272 l = min(len, sizeof ps); 2273 memcpy(buf, &ps, l); 2274 totlen = l; 2275 break; 2276 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2277 err = USBD_IOERROR; 2278 goto ret; 2279 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2280 break; 2281 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2282 if (index < 1 || index > sc->sc_noport) { 2283 err = USBD_IOERROR; 2284 goto ret; 2285 } 2286 port = EHCI_PORTSC(index); 2287 v = EOREAD4(sc, port); 2288 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2289 v &= ~EHCI_PS_CLEAR; 2290 switch(value) { 2291 case UHF_PORT_ENABLE: 2292 EOWRITE4(sc, port, v | EHCI_PS_PE); 2293 break; 2294 case UHF_PORT_SUSPEND: 2295 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2296 break; 2297 case UHF_PORT_RESET: 2298 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2299 index)); 2300 if (EHCI_PS_IS_LOWSPEED(v)) { 2301 /* Low speed device, give up ownership. */ 2302 ehci_disown(sc, index, 1); 2303 break; 2304 } 2305 /* Start reset sequence. */ 2306 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2307 EOWRITE4(sc, port, v | EHCI_PS_PR); 2308 /* Wait for reset to complete. */ 2309 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2310 if (sc->sc_dying) { 2311 err = USBD_IOERROR; 2312 goto ret; 2313 } 2314 /* Terminate reset sequence. */ 2315 EOWRITE4(sc, port, v); 2316 /* Wait for HC to complete reset. */ 2317 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2318 if (sc->sc_dying) { 2319 err = USBD_IOERROR; 2320 goto ret; 2321 } 2322 v = EOREAD4(sc, port); 2323 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2324 if (v & EHCI_PS_PR) { 2325 printf("%s: port reset timeout\n", 2326 device_xname(sc->sc_dev)); 2327 return (USBD_TIMEOUT); 2328 } 2329 if (!(v & EHCI_PS_PE)) { 2330 /* Not a high speed device, give up ownership.*/ 2331 ehci_disown(sc, index, 0); 2332 break; 2333 } 2334 sc->sc_isreset[index] = 1; 2335 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2336 index, v)); 2337 break; 2338 case UHF_PORT_POWER: 2339 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2340 "%d (has PPC = %d)\n", index, 2341 sc->sc_hasppc)); 2342 if (sc->sc_hasppc) 2343 EOWRITE4(sc, port, v | EHCI_PS_PP); 2344 break; 2345 case UHF_PORT_TEST: 2346 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2347 "%d\n", index)); 2348 break; 2349 case UHF_PORT_INDICATOR: 2350 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2351 "%d\n", index)); 2352 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2353 break; 2354 default: 2355 err = USBD_IOERROR; 2356 goto ret; 2357 } 2358 break; 2359 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2360 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2361 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2362 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2363 break; 2364 default: 2365 err = USBD_IOERROR; 2366 goto ret; 2367 } 2368 xfer->actlen = totlen; 2369 err = USBD_NORMAL_COMPLETION; 2370 ret: 2371 xfer->status = err; 2372 s = splusb(); 2373 usb_transfer_complete(xfer); 2374 splx(s); 2375 return (USBD_IN_PROGRESS); 2376 } 2377 2378 void 2379 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2380 { 2381 int port; 2382 u_int32_t v; 2383 2384 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2385 #ifdef DIAGNOSTIC 2386 if (sc->sc_npcomp != 0) { 2387 int i = (index-1) / sc->sc_npcomp; 2388 if (i >= sc->sc_ncomp) 2389 printf("%s: strange port\n", 2390 device_xname(sc->sc_dev)); 2391 else 2392 printf("%s: handing over %s speed device on " 2393 "port %d to %s\n", 2394 device_xname(sc->sc_dev), 2395 lowspeed ? "low" : "full", 2396 index, device_xname(sc->sc_comps[i])); 2397 } else { 2398 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2399 } 2400 #endif 2401 port = EHCI_PORTSC(index); 2402 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2403 EOWRITE4(sc, port, v | EHCI_PS_PO); 2404 } 2405 2406 /* Abort a root control request. */ 2407 Static void 2408 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2409 { 2410 /* Nothing to do, all transfers are synchronous. */ 2411 } 2412 2413 /* Close the root pipe. */ 2414 Static void 2415 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2416 { 2417 DPRINTF(("ehci_root_ctrl_close\n")); 2418 /* Nothing to do. */ 2419 } 2420 2421 void 2422 ehci_root_intr_done(usbd_xfer_handle xfer) 2423 { 2424 xfer->hcpriv = NULL; 2425 } 2426 2427 Static usbd_status 2428 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2429 { 2430 usbd_status err; 2431 2432 /* Insert last in queue. */ 2433 err = usb_insert_transfer(xfer); 2434 if (err) 2435 return (err); 2436 2437 /* Pipe isn't running, start first */ 2438 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2439 } 2440 2441 Static usbd_status 2442 ehci_root_intr_start(usbd_xfer_handle xfer) 2443 { 2444 usbd_pipe_handle pipe = xfer->pipe; 2445 ehci_softc_t *sc = pipe->device->bus->hci_private; 2446 2447 if (sc->sc_dying) 2448 return (USBD_IOERROR); 2449 2450 sc->sc_intrxfer = xfer; 2451 2452 return (USBD_IN_PROGRESS); 2453 } 2454 2455 /* Abort a root interrupt request. */ 2456 Static void 2457 ehci_root_intr_abort(usbd_xfer_handle xfer) 2458 { 2459 int s; 2460 2461 if (xfer->pipe->intrxfer == xfer) { 2462 DPRINTF(("ehci_root_intr_abort: remove\n")); 2463 xfer->pipe->intrxfer = NULL; 2464 } 2465 xfer->status = USBD_CANCELLED; 2466 s = splusb(); 2467 usb_transfer_complete(xfer); 2468 splx(s); 2469 } 2470 2471 /* Close the root pipe. */ 2472 Static void 2473 ehci_root_intr_close(usbd_pipe_handle pipe) 2474 { 2475 ehci_softc_t *sc = pipe->device->bus->hci_private; 2476 2477 DPRINTF(("ehci_root_intr_close\n")); 2478 2479 sc->sc_intrxfer = NULL; 2480 } 2481 2482 void 2483 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2484 { 2485 xfer->hcpriv = NULL; 2486 } 2487 2488 /************************/ 2489 2490 ehci_soft_qh_t * 2491 ehci_alloc_sqh(ehci_softc_t *sc) 2492 { 2493 ehci_soft_qh_t *sqh; 2494 usbd_status err; 2495 int i, offs; 2496 usb_dma_t dma; 2497 2498 if (sc->sc_freeqhs == NULL) { 2499 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2500 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2501 EHCI_PAGE_SIZE, &dma); 2502 #ifdef EHCI_DEBUG 2503 if (err) 2504 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2505 #endif 2506 if (err) 2507 return (NULL); 2508 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2509 offs = i * EHCI_SQH_SIZE; 2510 sqh = KERNADDR(&dma, offs); 2511 sqh->physaddr = DMAADDR(&dma, offs); 2512 sqh->dma = dma; 2513 sqh->offs = offs; 2514 sqh->next = sc->sc_freeqhs; 2515 sc->sc_freeqhs = sqh; 2516 } 2517 } 2518 sqh = sc->sc_freeqhs; 2519 sc->sc_freeqhs = sqh->next; 2520 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2521 sqh->next = NULL; 2522 return (sqh); 2523 } 2524 2525 void 2526 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2527 { 2528 sqh->next = sc->sc_freeqhs; 2529 sc->sc_freeqhs = sqh; 2530 } 2531 2532 ehci_soft_qtd_t * 2533 ehci_alloc_sqtd(ehci_softc_t *sc) 2534 { 2535 ehci_soft_qtd_t *sqtd; 2536 usbd_status err; 2537 int i, offs; 2538 usb_dma_t dma; 2539 int s; 2540 2541 if (sc->sc_freeqtds == NULL) { 2542 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2543 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2544 EHCI_PAGE_SIZE, &dma); 2545 #ifdef EHCI_DEBUG 2546 if (err) 2547 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2548 #endif 2549 if (err) 2550 return (NULL); 2551 s = splusb(); 2552 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2553 offs = i * EHCI_SQTD_SIZE; 2554 sqtd = KERNADDR(&dma, offs); 2555 sqtd->physaddr = DMAADDR(&dma, offs); 2556 sqtd->dma = dma; 2557 sqtd->offs = offs; 2558 sqtd->nextqtd = sc->sc_freeqtds; 2559 sc->sc_freeqtds = sqtd; 2560 } 2561 splx(s); 2562 } 2563 2564 s = splusb(); 2565 sqtd = sc->sc_freeqtds; 2566 sc->sc_freeqtds = sqtd->nextqtd; 2567 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2568 sqtd->nextqtd = NULL; 2569 sqtd->xfer = NULL; 2570 splx(s); 2571 2572 return (sqtd); 2573 } 2574 2575 void 2576 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2577 { 2578 int s; 2579 2580 s = splusb(); 2581 sqtd->nextqtd = sc->sc_freeqtds; 2582 sc->sc_freeqtds = sqtd; 2583 splx(s); 2584 } 2585 2586 usbd_status 2587 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2588 int alen, int rd, usbd_xfer_handle xfer, 2589 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2590 { 2591 ehci_soft_qtd_t *next, *cur; 2592 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2593 u_int32_t qtdstatus; 2594 int len, curlen, mps; 2595 int i, tog; 2596 usb_dma_t *dma = &xfer->dmabuf; 2597 u_int16_t flags = xfer->flags; 2598 2599 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2600 2601 len = alen; 2602 dataphys = DMAADDR(dma, 0); 2603 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2604 qtdstatus = EHCI_QTD_ACTIVE | 2605 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2606 EHCI_QTD_SET_CERR(3) 2607 /* IOC set below */ 2608 /* BYTES set below */ 2609 ; 2610 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2611 tog = epipe->nexttoggle; 2612 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2613 2614 cur = ehci_alloc_sqtd(sc); 2615 *sp = cur; 2616 if (cur == NULL) 2617 goto nomem; 2618 2619 usb_syncmem(dma, 0, alen, 2620 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2621 for (;;) { 2622 dataphyspage = EHCI_PAGE(dataphys); 2623 /* The EHCI hardware can handle at most 5 pages. */ 2624 if (dataphyslastpage - dataphyspage < 2625 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2626 /* we can handle it in this QTD */ 2627 curlen = len; 2628 } else { 2629 /* must use multiple TDs, fill as much as possible. */ 2630 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2631 EHCI_PAGE_OFFSET(dataphys); 2632 #ifdef DIAGNOSTIC 2633 if (curlen > len) { 2634 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2635 "len=0x%x offs=0x%x\n", curlen, len, 2636 EHCI_PAGE_OFFSET(dataphys)); 2637 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2638 dataphyslastpage, dataphyspage, 2639 dataphys); 2640 curlen = len; 2641 } 2642 #endif 2643 /* the length must be a multiple of the max size */ 2644 curlen -= curlen % mps; 2645 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2646 "curlen=%d\n", curlen)); 2647 #ifdef DIAGNOSTIC 2648 if (curlen == 0) 2649 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2650 #endif 2651 } 2652 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2653 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2654 dataphys, dataphyslastpage, 2655 len, curlen)); 2656 len -= curlen; 2657 2658 /* 2659 * Allocate another transfer if there's more data left, 2660 * or if force last short transfer flag is set and we're 2661 * allocating a multiple of the max packet size. 2662 */ 2663 if (len != 0 || 2664 ((curlen % mps) == 0 && !rd && curlen != 0 && 2665 (flags & USBD_FORCE_SHORT_XFER))) { 2666 next = ehci_alloc_sqtd(sc); 2667 if (next == NULL) 2668 goto nomem; 2669 nextphys = htole32(next->physaddr); 2670 } else { 2671 next = NULL; 2672 nextphys = EHCI_NULL; 2673 } 2674 2675 for (i = 0; i * EHCI_PAGE_SIZE < 2676 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2677 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2678 if (i != 0) /* use offset only in first buffer */ 2679 a = EHCI_PAGE(a); 2680 cur->qtd.qtd_buffer[i] = htole32(a); 2681 cur->qtd.qtd_buffer_hi[i] = 0; 2682 #ifdef DIAGNOSTIC 2683 if (i >= EHCI_QTD_NBUFFERS) { 2684 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2685 goto nomem; 2686 } 2687 #endif 2688 } 2689 cur->nextqtd = next; 2690 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2691 cur->qtd.qtd_status = 2692 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2693 cur->xfer = xfer; 2694 cur->len = curlen; 2695 2696 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2697 dataphys, dataphys + curlen)); 2698 /* adjust the toggle based on the number of packets in this 2699 qtd */ 2700 if (((curlen + mps - 1) / mps) & 1) { 2701 tog ^= 1; 2702 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2703 } 2704 if (next == NULL) 2705 break; 2706 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2707 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2708 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2709 dataphys += curlen; 2710 cur = next; 2711 } 2712 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2713 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2714 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2715 *ep = cur; 2716 epipe->nexttoggle = tog; 2717 2718 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2719 *sp, *ep)); 2720 2721 return (USBD_NORMAL_COMPLETION); 2722 2723 nomem: 2724 /* XXX free chain */ 2725 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2726 return (USBD_NOMEM); 2727 } 2728 2729 Static void 2730 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2731 ehci_soft_qtd_t *sqtdend) 2732 { 2733 ehci_soft_qtd_t *p; 2734 int i; 2735 2736 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2737 sqtd, sqtdend)); 2738 2739 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2740 p = sqtd->nextqtd; 2741 ehci_free_sqtd(sc, sqtd); 2742 } 2743 } 2744 2745 ehci_soft_itd_t * 2746 ehci_alloc_itd(ehci_softc_t *sc) 2747 { 2748 struct ehci_soft_itd *itd, *freeitd; 2749 usbd_status err; 2750 int i, s, offs, frindex, previndex; 2751 usb_dma_t dma; 2752 2753 s = splusb(); 2754 2755 /* Find an itd that wasn't freed this frame or last frame. This can 2756 * discard itds that were freed before frindex wrapped around 2757 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2758 * interrupt and fiddling with list when that happens */ 2759 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2760 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2761 2762 freeitd = NULL; 2763 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2764 if (itd == NULL) 2765 break; 2766 if (itd->slot != frindex && itd->slot != previndex) { 2767 freeitd = itd; 2768 break; 2769 } 2770 } 2771 2772 if (freeitd == NULL) { 2773 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2774 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2775 EHCI_PAGE_SIZE, &dma); 2776 2777 if (err) { 2778 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2779 return NULL; 2780 } 2781 2782 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2783 offs = i * EHCI_ITD_SIZE; 2784 itd = KERNADDR(&dma, offs); 2785 itd->physaddr = DMAADDR(&dma, offs); 2786 itd->dma = dma; 2787 itd->offs = offs; 2788 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2789 } 2790 freeitd = LIST_FIRST(&sc->sc_freeitds); 2791 } 2792 2793 itd = freeitd; 2794 LIST_REMOVE(itd, u.free_list); 2795 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2796 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2797 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2798 BUS_DMASYNC_PREREAD); 2799 2800 itd->u.frame_list.next = NULL; 2801 itd->u.frame_list.prev = NULL; 2802 itd->xfer_next = NULL; 2803 itd->slot = 0; 2804 splx(s); 2805 2806 return itd; 2807 } 2808 2809 void 2810 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2811 { 2812 int s; 2813 2814 s = splusb(); 2815 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2816 splx(s); 2817 } 2818 2819 2820 2821 /****************/ 2822 2823 /* 2824 * Close a reqular pipe. 2825 * Assumes that there are no pending transactions. 2826 */ 2827 void 2828 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2829 { 2830 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2831 ehci_softc_t *sc = pipe->device->bus->hci_private; 2832 ehci_soft_qh_t *sqh = epipe->sqh; 2833 int s; 2834 2835 s = splusb(); 2836 ehci_rem_qh(sc, sqh, head); 2837 splx(s); 2838 ehci_free_sqh(sc, epipe->sqh); 2839 } 2840 2841 /* 2842 * Abort a device request. 2843 * If this routine is called at splusb() it guarantees that the request 2844 * will be removed from the hardware scheduling and that the callback 2845 * for it will be called with USBD_CANCELLED status. 2846 * It's impossible to guarantee that the requested transfer will not 2847 * have happened since the hardware runs concurrently. 2848 * If the transaction has already happened we rely on the ordinary 2849 * interrupt processing to process it. 2850 * XXX This is most probably wrong. 2851 */ 2852 void 2853 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2854 { 2855 #define exfer EXFER(xfer) 2856 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2857 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2858 ehci_soft_qh_t *sqh = epipe->sqh; 2859 ehci_soft_qtd_t *sqtd; 2860 ehci_physaddr_t cur; 2861 u_int32_t qhstatus; 2862 int s; 2863 int hit; 2864 int wake; 2865 2866 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2867 2868 if (sc->sc_dying) { 2869 /* If we're dying, just do the software part. */ 2870 s = splusb(); 2871 xfer->status = status; /* make software ignore it */ 2872 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2873 usb_transfer_complete(xfer); 2874 splx(s); 2875 return; 2876 } 2877 2878 if (xfer->device->bus->intr_context) 2879 panic("ehci_abort_xfer: not in process context"); 2880 2881 /* 2882 * If an abort is already in progress then just wait for it to 2883 * complete and return. 2884 */ 2885 if (xfer->hcflags & UXFER_ABORTING) { 2886 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2887 #ifdef DIAGNOSTIC 2888 if (status == USBD_TIMEOUT) 2889 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2890 #endif 2891 /* Override the status which might be USBD_TIMEOUT. */ 2892 xfer->status = status; 2893 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2894 xfer->hcflags |= UXFER_ABORTWAIT; 2895 while (xfer->hcflags & UXFER_ABORTING) 2896 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2897 return; 2898 } 2899 xfer->hcflags |= UXFER_ABORTING; 2900 2901 /* 2902 * Step 1: Make interrupt routine and hardware ignore xfer. 2903 */ 2904 s = splusb(); 2905 xfer->status = status; /* make software ignore it */ 2906 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2907 2908 usb_syncmem(&sqh->dma, 2909 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2910 sizeof(sqh->qh.qh_qtd.qtd_status), 2911 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2912 qhstatus = sqh->qh.qh_qtd.qtd_status; 2913 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2914 usb_syncmem(&sqh->dma, 2915 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2916 sizeof(sqh->qh.qh_qtd.qtd_status), 2917 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2918 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2919 usb_syncmem(&sqtd->dma, 2920 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2921 sizeof(sqtd->qtd.qtd_status), 2922 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2923 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2924 usb_syncmem(&sqtd->dma, 2925 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2926 sizeof(sqtd->qtd.qtd_status), 2927 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2928 if (sqtd == exfer->sqtdend) 2929 break; 2930 } 2931 splx(s); 2932 2933 /* 2934 * Step 2: Wait until we know hardware has finished any possible 2935 * use of the xfer. Also make sure the soft interrupt routine 2936 * has run. 2937 */ 2938 ehci_sync_hc(sc); 2939 s = splusb(); 2940 #ifdef USB_USE_SOFTINTR 2941 sc->sc_softwake = 1; 2942 #endif /* USB_USE_SOFTINTR */ 2943 usb_schedsoftintr(&sc->sc_bus); 2944 #ifdef USB_USE_SOFTINTR 2945 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2946 #endif /* USB_USE_SOFTINTR */ 2947 splx(s); 2948 2949 /* 2950 * Step 3: Remove any vestiges of the xfer from the hardware. 2951 * The complication here is that the hardware may have executed 2952 * beyond the xfer we're trying to abort. So as we're scanning 2953 * the TDs of this xfer we check if the hardware points to 2954 * any of them. 2955 */ 2956 s = splusb(); /* XXX why? */ 2957 2958 usb_syncmem(&sqh->dma, 2959 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2960 sizeof(sqh->qh.qh_curqtd), 2961 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2962 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2963 hit = 0; 2964 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2965 hit |= cur == sqtd->physaddr; 2966 if (sqtd == exfer->sqtdend) 2967 break; 2968 } 2969 sqtd = sqtd->nextqtd; 2970 /* Zap curqtd register if hardware pointed inside the xfer. */ 2971 if (hit && sqtd != NULL) { 2972 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 2973 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 2974 usb_syncmem(&sqh->dma, 2975 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2976 sizeof(sqh->qh.qh_curqtd), 2977 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2978 sqh->qh.qh_qtd.qtd_status = qhstatus; 2979 usb_syncmem(&sqh->dma, 2980 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2981 sizeof(sqh->qh.qh_qtd.qtd_status), 2982 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2983 } else { 2984 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2985 } 2986 2987 /* 2988 * Step 4: Execute callback. 2989 */ 2990 #ifdef DIAGNOSTIC 2991 exfer->isdone = 1; 2992 #endif 2993 wake = xfer->hcflags & UXFER_ABORTWAIT; 2994 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2995 usb_transfer_complete(xfer); 2996 if (wake) 2997 wakeup(&xfer->hcflags); 2998 2999 splx(s); 3000 #undef exfer 3001 } 3002 3003 void 3004 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3005 { 3006 ehci_isoc_trans_t trans_status; 3007 struct ehci_pipe *epipe; 3008 struct ehci_xfer *exfer; 3009 ehci_softc_t *sc; 3010 struct ehci_soft_itd *itd; 3011 int s, i, wake; 3012 3013 epipe = (struct ehci_pipe *) xfer->pipe; 3014 exfer = EXFER(xfer); 3015 sc = epipe->pipe.device->bus->hci_private; 3016 3017 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3018 3019 if (sc->sc_dying) { 3020 s = splusb(); 3021 xfer->status = status; 3022 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3023 usb_transfer_complete(xfer); 3024 splx(s); 3025 return; 3026 } 3027 3028 if (xfer->hcflags & UXFER_ABORTING) { 3029 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3030 3031 #ifdef DIAGNOSTIC 3032 if (status == USBD_TIMEOUT) 3033 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3034 #endif 3035 3036 xfer->status = status; 3037 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3038 xfer->hcflags |= UXFER_ABORTWAIT; 3039 while (xfer->hcflags & UXFER_ABORTING) 3040 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0); 3041 return; 3042 } 3043 xfer->hcflags |= UXFER_ABORTING; 3044 3045 xfer->status = status; 3046 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3047 3048 s = splusb(); 3049 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3050 usb_syncmem(&itd->dma, 3051 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3052 sizeof(itd->itd.itd_ctl), 3053 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3054 3055 for (i = 0; i < 8; i++) { 3056 trans_status = le32toh(itd->itd.itd_ctl[i]); 3057 trans_status &= ~EHCI_ITD_ACTIVE; 3058 itd->itd.itd_ctl[i] = htole32(trans_status); 3059 } 3060 3061 usb_syncmem(&itd->dma, 3062 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3063 sizeof(itd->itd.itd_ctl), 3064 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3065 } 3066 splx(s); 3067 3068 s = splusb(); 3069 #ifdef USB_USE_SOFTINTR 3070 sc->sc_softwake = 1; 3071 #endif /* USB_USE_SOFTINTR */ 3072 usb_schedsoftintr(&sc->sc_bus); 3073 #ifdef USB_USE_SOFTINTR 3074 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3075 #endif /* USB_USE_SOFTINTR */ 3076 splx(s); 3077 3078 #ifdef DIAGNOSTIC 3079 exfer->isdone = 1; 3080 #endif 3081 wake = xfer->hcflags & UXFER_ABORTWAIT; 3082 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3083 usb_transfer_complete(xfer); 3084 if (wake) 3085 wakeup(&xfer->hcflags); 3086 3087 return; 3088 } 3089 3090 void 3091 ehci_timeout(void *addr) 3092 { 3093 struct ehci_xfer *exfer = addr; 3094 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3095 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3096 3097 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3098 #ifdef USB_DEBUG 3099 if (ehcidebug > 1) 3100 usbd_dump_pipe(exfer->xfer.pipe); 3101 #endif 3102 3103 if (sc->sc_dying) { 3104 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3105 return; 3106 } 3107 3108 /* Execute the abort in a process context. */ 3109 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3110 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3111 USB_TASKQ_HC); 3112 } 3113 3114 void 3115 ehci_timeout_task(void *addr) 3116 { 3117 usbd_xfer_handle xfer = addr; 3118 int s; 3119 3120 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3121 3122 s = splusb(); 3123 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3124 splx(s); 3125 } 3126 3127 /************************/ 3128 3129 Static usbd_status 3130 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3131 { 3132 usbd_status err; 3133 3134 /* Insert last in queue. */ 3135 err = usb_insert_transfer(xfer); 3136 if (err) 3137 return (err); 3138 3139 /* Pipe isn't running, start first */ 3140 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3141 } 3142 3143 Static usbd_status 3144 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3145 { 3146 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3147 usbd_status err; 3148 3149 if (sc->sc_dying) 3150 return (USBD_IOERROR); 3151 3152 #ifdef DIAGNOSTIC 3153 if (!(xfer->rqflags & URQ_REQUEST)) { 3154 /* XXX panic */ 3155 printf("ehci_device_ctrl_transfer: not a request\n"); 3156 return (USBD_INVAL); 3157 } 3158 #endif 3159 3160 err = ehci_device_request(xfer); 3161 if (err) 3162 return (err); 3163 3164 if (sc->sc_bus.use_polling) 3165 ehci_waitintr(sc, xfer); 3166 return (USBD_IN_PROGRESS); 3167 } 3168 3169 void 3170 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3171 { 3172 struct ehci_xfer *ex = EXFER(xfer); 3173 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3174 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3175 usb_device_request_t *req = &xfer->request; 3176 int len = UGETW(req->wLength); 3177 int rd = req->bmRequestType & UT_READ; 3178 3179 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3180 3181 #ifdef DIAGNOSTIC 3182 if (!(xfer->rqflags & URQ_REQUEST)) { 3183 panic("ehci_ctrl_done: not a request"); 3184 } 3185 #endif 3186 3187 mutex_enter(&sc->sc_intrhead_lock); 3188 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3189 ehci_del_intr_list(sc, ex); /* remove from active list */ 3190 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3191 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3192 BUS_DMASYNC_POSTWRITE); 3193 if (len) 3194 usb_syncmem(&xfer->dmabuf, 0, len, 3195 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3196 } 3197 mutex_exit(&sc->sc_intrhead_lock); 3198 3199 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3200 } 3201 3202 /* Abort a device control request. */ 3203 Static void 3204 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3205 { 3206 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3207 ehci_abort_xfer(xfer, USBD_CANCELLED); 3208 } 3209 3210 /* Close a device control pipe. */ 3211 Static void 3212 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3213 { 3214 ehci_softc_t *sc = pipe->device->bus->hci_private; 3215 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3216 3217 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3218 ehci_close_pipe(pipe, sc->sc_async_head); 3219 } 3220 3221 usbd_status 3222 ehci_device_request(usbd_xfer_handle xfer) 3223 { 3224 #define exfer EXFER(xfer) 3225 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3226 usb_device_request_t *req = &xfer->request; 3227 usbd_device_handle dev = epipe->pipe.device; 3228 ehci_softc_t *sc = dev->bus->hci_private; 3229 int addr = dev->address; 3230 ehci_soft_qtd_t *setup, *stat, *next; 3231 ehci_soft_qh_t *sqh; 3232 int isread; 3233 int len; 3234 usbd_status err; 3235 int s; 3236 3237 isread = req->bmRequestType & UT_READ; 3238 len = UGETW(req->wLength); 3239 3240 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3241 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3242 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3243 UGETW(req->wIndex), len, addr, 3244 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3245 3246 setup = ehci_alloc_sqtd(sc); 3247 if (setup == NULL) { 3248 err = USBD_NOMEM; 3249 goto bad1; 3250 } 3251 stat = ehci_alloc_sqtd(sc); 3252 if (stat == NULL) { 3253 err = USBD_NOMEM; 3254 goto bad2; 3255 } 3256 3257 sqh = epipe->sqh; 3258 epipe->u.ctl.length = len; 3259 3260 /* Update device address and length since they may have changed 3261 during the setup of the control pipe in usbd_new_device(). */ 3262 /* XXX This only needs to be done once, but it's too early in open. */ 3263 /* XXXX Should not touch ED here! */ 3264 sqh->qh.qh_endp = 3265 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3266 htole32( 3267 EHCI_QH_SET_ADDR(addr) | 3268 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3269 ); 3270 3271 /* Set up data transaction */ 3272 if (len != 0) { 3273 ehci_soft_qtd_t *end; 3274 3275 /* Start toggle at 1. */ 3276 epipe->nexttoggle = 1; 3277 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3278 &next, &end); 3279 if (err) 3280 goto bad3; 3281 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3282 end->nextqtd = stat; 3283 end->qtd.qtd_next = 3284 end->qtd.qtd_altnext = htole32(stat->physaddr); 3285 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3286 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3287 } else { 3288 next = stat; 3289 } 3290 3291 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3292 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3293 3294 /* Clear toggle */ 3295 setup->qtd.qtd_status = htole32( 3296 EHCI_QTD_ACTIVE | 3297 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3298 EHCI_QTD_SET_CERR(3) | 3299 EHCI_QTD_SET_TOGGLE(0) | 3300 EHCI_QTD_SET_BYTES(sizeof *req) 3301 ); 3302 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3303 setup->qtd.qtd_buffer_hi[0] = 0; 3304 setup->nextqtd = next; 3305 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3306 setup->xfer = xfer; 3307 setup->len = sizeof *req; 3308 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3309 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3310 3311 stat->qtd.qtd_status = htole32( 3312 EHCI_QTD_ACTIVE | 3313 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3314 EHCI_QTD_SET_CERR(3) | 3315 EHCI_QTD_SET_TOGGLE(1) | 3316 EHCI_QTD_IOC 3317 ); 3318 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3319 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3320 stat->nextqtd = NULL; 3321 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3322 stat->xfer = xfer; 3323 stat->len = 0; 3324 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3325 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3326 3327 #ifdef EHCI_DEBUG 3328 if (ehcidebug > 5) { 3329 DPRINTF(("ehci_device_request:\n")); 3330 ehci_dump_sqh(sqh); 3331 ehci_dump_sqtds(setup); 3332 } 3333 #endif 3334 3335 exfer->sqtdstart = setup; 3336 exfer->sqtdend = stat; 3337 #ifdef DIAGNOSTIC 3338 if (!exfer->isdone) { 3339 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3340 } 3341 exfer->isdone = 0; 3342 #endif 3343 3344 /* Insert qTD in QH list. */ 3345 s = splusb(); 3346 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3347 if (xfer->timeout && !sc->sc_bus.use_polling) { 3348 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3349 ehci_timeout, xfer); 3350 } 3351 mutex_enter(&sc->sc_intrhead_lock); 3352 ehci_add_intr_list(sc, exfer); 3353 mutex_exit(&sc->sc_intrhead_lock); 3354 xfer->status = USBD_IN_PROGRESS; 3355 splx(s); 3356 3357 #ifdef EHCI_DEBUG 3358 if (ehcidebug > 10) { 3359 DPRINTF(("ehci_device_request: status=%x\n", 3360 EOREAD4(sc, EHCI_USBSTS))); 3361 delay(10000); 3362 ehci_dump_regs(sc); 3363 ehci_dump_sqh(sc->sc_async_head); 3364 ehci_dump_sqh(sqh); 3365 ehci_dump_sqtds(setup); 3366 } 3367 #endif 3368 3369 return (USBD_NORMAL_COMPLETION); 3370 3371 bad3: 3372 ehci_free_sqtd(sc, stat); 3373 bad2: 3374 ehci_free_sqtd(sc, setup); 3375 bad1: 3376 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3377 xfer->status = err; 3378 usb_transfer_complete(xfer); 3379 return (err); 3380 #undef exfer 3381 } 3382 3383 /* 3384 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3385 * qTD status, or miss signalling occasionally under heavy load. If the host 3386 * machine is too fast, we we can miss transaction completion - when we scan 3387 * the active list the transaction still seems to be active. This generally 3388 * exhibits itself as a umass stall that never recovers. 3389 * 3390 * We work around this behaviour by setting up this callback after any softintr 3391 * that completes with transactions still pending, giving us another chance to 3392 * check for completion after the writeback has taken place. 3393 */ 3394 void 3395 ehci_intrlist_timeout(void *arg) 3396 { 3397 ehci_softc_t *sc = arg; 3398 int s = splusb(); 3399 3400 DPRINTF(("ehci_intrlist_timeout\n")); 3401 usb_schedsoftintr(&sc->sc_bus); 3402 3403 splx(s); 3404 } 3405 3406 /************************/ 3407 3408 Static usbd_status 3409 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3410 { 3411 usbd_status err; 3412 3413 /* Insert last in queue. */ 3414 err = usb_insert_transfer(xfer); 3415 if (err) 3416 return (err); 3417 3418 /* Pipe isn't running, start first */ 3419 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3420 } 3421 3422 usbd_status 3423 ehci_device_bulk_start(usbd_xfer_handle xfer) 3424 { 3425 #define exfer EXFER(xfer) 3426 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3427 usbd_device_handle dev = epipe->pipe.device; 3428 ehci_softc_t *sc = dev->bus->hci_private; 3429 ehci_soft_qtd_t *data, *dataend; 3430 ehci_soft_qh_t *sqh; 3431 usbd_status err; 3432 int len, isread, endpt; 3433 int s; 3434 3435 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3436 xfer, xfer->length, xfer->flags)); 3437 3438 if (sc->sc_dying) 3439 return (USBD_IOERROR); 3440 3441 #ifdef DIAGNOSTIC 3442 if (xfer->rqflags & URQ_REQUEST) 3443 panic("ehci_device_bulk_start: a request"); 3444 #endif 3445 3446 len = xfer->length; 3447 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3448 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3449 sqh = epipe->sqh; 3450 3451 epipe->u.bulk.length = len; 3452 3453 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3454 &dataend); 3455 if (err) { 3456 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3457 xfer->status = err; 3458 usb_transfer_complete(xfer); 3459 return (err); 3460 } 3461 3462 #ifdef EHCI_DEBUG 3463 if (ehcidebug > 5) { 3464 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3465 ehci_dump_sqh(sqh); 3466 ehci_dump_sqtds(data); 3467 } 3468 #endif 3469 3470 /* Set up interrupt info. */ 3471 exfer->sqtdstart = data; 3472 exfer->sqtdend = dataend; 3473 #ifdef DIAGNOSTIC 3474 if (!exfer->isdone) { 3475 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3476 } 3477 exfer->isdone = 0; 3478 #endif 3479 3480 s = splusb(); 3481 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3482 if (xfer->timeout && !sc->sc_bus.use_polling) { 3483 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3484 ehci_timeout, xfer); 3485 } 3486 mutex_enter(&sc->sc_intrhead_lock); 3487 ehci_add_intr_list(sc, exfer); 3488 mutex_exit(&sc->sc_intrhead_lock); 3489 xfer->status = USBD_IN_PROGRESS; 3490 splx(s); 3491 3492 #ifdef EHCI_DEBUG 3493 if (ehcidebug > 10) { 3494 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3495 delay(10000); 3496 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3497 ehci_dump_regs(sc); 3498 #if 0 3499 printf("async_head:\n"); 3500 ehci_dump_sqh(sc->sc_async_head); 3501 #endif 3502 printf("sqh:\n"); 3503 ehci_dump_sqh(sqh); 3504 ehci_dump_sqtds(data); 3505 } 3506 #endif 3507 3508 if (sc->sc_bus.use_polling) 3509 ehci_waitintr(sc, xfer); 3510 3511 return (USBD_IN_PROGRESS); 3512 #undef exfer 3513 } 3514 3515 Static void 3516 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3517 { 3518 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3519 ehci_abort_xfer(xfer, USBD_CANCELLED); 3520 } 3521 3522 /* 3523 * Close a device bulk pipe. 3524 */ 3525 Static void 3526 ehci_device_bulk_close(usbd_pipe_handle pipe) 3527 { 3528 ehci_softc_t *sc = pipe->device->bus->hci_private; 3529 3530 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3531 ehci_close_pipe(pipe, sc->sc_async_head); 3532 } 3533 3534 void 3535 ehci_device_bulk_done(usbd_xfer_handle xfer) 3536 { 3537 struct ehci_xfer *ex = EXFER(xfer); 3538 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3539 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3540 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3541 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3542 3543 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3544 xfer, xfer->actlen)); 3545 3546 mutex_enter(&sc->sc_intrhead_lock); 3547 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3548 ehci_del_intr_list(sc, ex); /* remove from active list */ 3549 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3550 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3551 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3552 } 3553 mutex_exit(&sc->sc_intrhead_lock); 3554 3555 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3556 } 3557 3558 /************************/ 3559 3560 Static usbd_status 3561 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3562 { 3563 struct ehci_soft_islot *isp; 3564 int islot, lev; 3565 3566 /* Find a poll rate that is large enough. */ 3567 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3568 if (EHCI_ILEV_IVAL(lev) <= ival) 3569 break; 3570 3571 /* Pick an interrupt slot at the right level. */ 3572 /* XXX could do better than picking at random */ 3573 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3574 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3575 3576 sqh->islot = islot; 3577 isp = &sc->sc_islots[islot]; 3578 ehci_add_qh(sqh, isp->sqh); 3579 3580 return (USBD_NORMAL_COMPLETION); 3581 } 3582 3583 Static usbd_status 3584 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3585 { 3586 usbd_status err; 3587 3588 /* Insert last in queue. */ 3589 err = usb_insert_transfer(xfer); 3590 if (err) 3591 return (err); 3592 3593 /* 3594 * Pipe isn't running (otherwise err would be USBD_INPROG), 3595 * so start it first. 3596 */ 3597 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3598 } 3599 3600 Static usbd_status 3601 ehci_device_intr_start(usbd_xfer_handle xfer) 3602 { 3603 #define exfer EXFER(xfer) 3604 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3605 usbd_device_handle dev = xfer->pipe->device; 3606 ehci_softc_t *sc = dev->bus->hci_private; 3607 ehci_soft_qtd_t *data, *dataend; 3608 ehci_soft_qh_t *sqh; 3609 usbd_status err; 3610 int len, isread, endpt; 3611 int s; 3612 3613 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3614 xfer, xfer->length, xfer->flags)); 3615 3616 if (sc->sc_dying) 3617 return (USBD_IOERROR); 3618 3619 #ifdef DIAGNOSTIC 3620 if (xfer->rqflags & URQ_REQUEST) 3621 panic("ehci_device_intr_start: a request"); 3622 #endif 3623 3624 len = xfer->length; 3625 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3626 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3627 sqh = epipe->sqh; 3628 3629 epipe->u.intr.length = len; 3630 3631 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3632 &dataend); 3633 if (err) { 3634 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3635 xfer->status = err; 3636 usb_transfer_complete(xfer); 3637 return (err); 3638 } 3639 3640 #ifdef EHCI_DEBUG 3641 if (ehcidebug > 5) { 3642 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3643 ehci_dump_sqh(sqh); 3644 ehci_dump_sqtds(data); 3645 } 3646 #endif 3647 3648 /* Set up interrupt info. */ 3649 exfer->sqtdstart = data; 3650 exfer->sqtdend = dataend; 3651 #ifdef DIAGNOSTIC 3652 if (!exfer->isdone) { 3653 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3654 } 3655 exfer->isdone = 0; 3656 #endif 3657 3658 s = splusb(); 3659 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3660 if (xfer->timeout && !sc->sc_bus.use_polling) { 3661 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3662 ehci_timeout, xfer); 3663 } 3664 mutex_enter(&sc->sc_intrhead_lock); 3665 ehci_add_intr_list(sc, exfer); 3666 mutex_exit(&sc->sc_intrhead_lock); 3667 xfer->status = USBD_IN_PROGRESS; 3668 splx(s); 3669 3670 #ifdef EHCI_DEBUG 3671 if (ehcidebug > 10) { 3672 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3673 delay(10000); 3674 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3675 ehci_dump_regs(sc); 3676 printf("sqh:\n"); 3677 ehci_dump_sqh(sqh); 3678 ehci_dump_sqtds(data); 3679 } 3680 #endif 3681 3682 if (sc->sc_bus.use_polling) 3683 ehci_waitintr(sc, xfer); 3684 3685 return (USBD_IN_PROGRESS); 3686 #undef exfer 3687 } 3688 3689 Static void 3690 ehci_device_intr_abort(usbd_xfer_handle xfer) 3691 { 3692 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3693 if (xfer->pipe->intrxfer == xfer) { 3694 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3695 xfer->pipe->intrxfer = NULL; 3696 } 3697 /* 3698 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3699 * async doorbell. That's dependant on the async list, wheras 3700 * intr xfers are periodic, should not use this? 3701 */ 3702 ehci_abort_xfer(xfer, USBD_CANCELLED); 3703 } 3704 3705 Static void 3706 ehci_device_intr_close(usbd_pipe_handle pipe) 3707 { 3708 ehci_softc_t *sc = pipe->device->bus->hci_private; 3709 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3710 struct ehci_soft_islot *isp; 3711 3712 isp = &sc->sc_islots[epipe->sqh->islot]; 3713 ehci_close_pipe(pipe, isp->sqh); 3714 } 3715 3716 Static void 3717 ehci_device_intr_done(usbd_xfer_handle xfer) 3718 { 3719 #define exfer EXFER(xfer) 3720 struct ehci_xfer *ex = EXFER(xfer); 3721 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3722 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3723 ehci_soft_qtd_t *data, *dataend; 3724 ehci_soft_qh_t *sqh; 3725 usbd_status err; 3726 int len, isread, endpt, s; 3727 3728 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3729 xfer, xfer->actlen)); 3730 3731 mutex_enter(&sc->sc_intrhead_lock); 3732 if (xfer->pipe->repeat) { 3733 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3734 3735 len = epipe->u.intr.length; 3736 xfer->length = len; 3737 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3738 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3739 usb_syncmem(&xfer->dmabuf, 0, len, 3740 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3741 sqh = epipe->sqh; 3742 3743 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3744 &data, &dataend); 3745 if (err) { 3746 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3747 xfer->status = err; 3748 mutex_exit(&sc->sc_intrhead_lock); 3749 return; 3750 } 3751 3752 /* Set up interrupt info. */ 3753 exfer->sqtdstart = data; 3754 exfer->sqtdend = dataend; 3755 #ifdef DIAGNOSTIC 3756 if (!exfer->isdone) { 3757 printf("ehci_device_intr_done: not done, ex=%p\n", 3758 exfer); 3759 } 3760 exfer->isdone = 0; 3761 #endif 3762 3763 s = splusb(); 3764 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3765 if (xfer->timeout && !sc->sc_bus.use_polling) { 3766 usb_callout(xfer->timeout_handle, 3767 mstohz(xfer->timeout), ehci_timeout, xfer); 3768 } 3769 splx(s); 3770 3771 xfer->status = USBD_IN_PROGRESS; 3772 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3773 ehci_del_intr_list(sc, ex); /* remove from active list */ 3774 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3775 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3776 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3777 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3778 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3779 } 3780 mutex_exit(&sc->sc_intrhead_lock); 3781 #undef exfer 3782 } 3783 3784 /************************/ 3785 3786 Static usbd_status 3787 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3788 { 3789 usbd_status err; 3790 3791 err = usb_insert_transfer(xfer); 3792 if (err && err != USBD_IN_PROGRESS) 3793 return err; 3794 3795 return ehci_device_isoc_start(xfer); 3796 } 3797 3798 Static usbd_status 3799 ehci_device_isoc_start(usbd_xfer_handle xfer) 3800 { 3801 struct ehci_pipe *epipe; 3802 usbd_device_handle dev; 3803 ehci_softc_t *sc; 3804 struct ehci_xfer *exfer; 3805 ehci_soft_itd_t *itd, *prev, *start, *stop; 3806 usb_dma_t *dma_buf; 3807 int i, j, k, frames, uframes, ufrperframe; 3808 int s, trans_count, offs, total_length; 3809 int frindex; 3810 3811 start = NULL; 3812 prev = NULL; 3813 itd = NULL; 3814 trans_count = 0; 3815 total_length = 0; 3816 exfer = (struct ehci_xfer *) xfer; 3817 sc = xfer->pipe->device->bus->hci_private; 3818 dev = xfer->pipe->device; 3819 epipe = (struct ehci_pipe *)xfer->pipe; 3820 3821 /* 3822 * To allow continuous transfers, above we start all transfers 3823 * immediately. However, we're still going to get usbd_start_next call 3824 * this when another xfer completes. So, check if this is already 3825 * in progress or not 3826 */ 3827 3828 if (exfer->itdstart != NULL) 3829 return USBD_IN_PROGRESS; 3830 3831 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3832 xfer, xfer->length, xfer->flags)); 3833 3834 if (sc->sc_dying) 3835 return USBD_IOERROR; 3836 3837 /* 3838 * To avoid complication, don't allow a request right now that'll span 3839 * the entire frame table. To within 4 frames, to allow some leeway 3840 * on either side of where the hc currently is. 3841 */ 3842 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3843 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3844 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3845 return USBD_INVAL; 3846 } 3847 3848 #ifdef DIAGNOSTIC 3849 if (xfer->rqflags & URQ_REQUEST) 3850 panic("ehci_device_isoc_start: request\n"); 3851 3852 if (!exfer->isdone) 3853 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3854 exfer->isdone = 0; 3855 #endif 3856 3857 /* 3858 * Step 1: Allocate and initialize itds, how many do we need? 3859 * One per transfer if interval >= 8 microframes, fewer if we use 3860 * multiple microframes per frame. 3861 */ 3862 3863 i = epipe->pipe.endpoint->edesc->bInterval; 3864 if (i > 16 || i == 0) { 3865 /* Spec page 271 says intervals > 16 are invalid */ 3866 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3867 return USBD_INVAL; 3868 } 3869 3870 switch (i) { 3871 case 1: 3872 ufrperframe = 8; 3873 break; 3874 case 2: 3875 ufrperframe = 4; 3876 break; 3877 case 3: 3878 ufrperframe = 2; 3879 break; 3880 default: 3881 ufrperframe = 1; 3882 break; 3883 } 3884 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3885 uframes = 8 / ufrperframe; 3886 3887 if (frames == 0) { 3888 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3889 return USBD_INVAL; 3890 } 3891 3892 dma_buf = &xfer->dmabuf; 3893 offs = 0; 3894 3895 for (i = 0; i < frames; i++) { 3896 int froffs = offs; 3897 itd = ehci_alloc_itd(sc); 3898 3899 if (prev != NULL) { 3900 prev->itd.itd_next = 3901 htole32(itd->physaddr | EHCI_LINK_ITD); 3902 usb_syncmem(&itd->dma, 3903 itd->offs + offsetof(ehci_itd_t, itd_next), 3904 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 3905 3906 prev->xfer_next = itd; 3907 } else { 3908 start = itd; 3909 } 3910 3911 /* 3912 * Step 1.5, initialize uframes 3913 */ 3914 for (j = 0; j < 8; j += uframes) { 3915 /* Calculate which page in the list this starts in */ 3916 int addr = DMAADDR(dma_buf, froffs); 3917 addr = EHCI_PAGE_OFFSET(addr); 3918 addr += (offs - froffs); 3919 addr = EHCI_PAGE(addr); 3920 addr /= EHCI_PAGE_SIZE; 3921 3922 /* This gets the initial offset into the first page, 3923 * looks how far further along the current uframe 3924 * offset is. Works out how many pages that is. 3925 */ 3926 3927 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3928 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3929 EHCI_ITD_SET_PG(addr) | 3930 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 3931 3932 total_length += xfer->frlengths[trans_count]; 3933 offs += xfer->frlengths[trans_count]; 3934 trans_count++; 3935 3936 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3937 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3938 break; 3939 } 3940 } 3941 3942 /* Step 1.75, set buffer pointers. To simplify matters, all 3943 * pointers are filled out for the next 7 hardware pages in 3944 * the dma block, so no need to worry what pages to cover 3945 * and what to not. 3946 */ 3947 3948 for (j=0; j < 7; j++) { 3949 /* 3950 * Don't try to lookup a page that's past the end 3951 * of buffer 3952 */ 3953 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 3954 if (page_offs >= dma_buf->block->size) 3955 break; 3956 3957 long long page = DMAADDR(dma_buf, page_offs); 3958 page = EHCI_PAGE(page); 3959 itd->itd.itd_bufr[j] = 3960 htole32(EHCI_ITD_SET_BPTR(page)); 3961 itd->itd.itd_bufr_hi[j] = 3962 htole32(page >> 32); 3963 } 3964 3965 /* 3966 * Other special values 3967 */ 3968 3969 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3970 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3971 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3972 3973 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3974 ? 1 : 0; 3975 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3976 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3977 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3978 3979 /* FIXME: handle invalid trans */ 3980 itd->itd.itd_bufr[2] |= 3981 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3982 3983 usb_syncmem(&itd->dma, 3984 itd->offs + offsetof(ehci_itd_t, itd_next), 3985 sizeof(ehci_itd_t), 3986 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3987 3988 prev = itd; 3989 } /* End of frame */ 3990 3991 stop = itd; 3992 stop->xfer_next = NULL; 3993 exfer->isoc_len = total_length; 3994 3995 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 3996 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3997 3998 /* 3999 * Part 2: Transfer descriptors have now been set up, now they must 4000 * be scheduled into the period frame list. Erk. Not wanting to 4001 * complicate matters, transfer is denied if the transfer spans 4002 * more than the period frame list. 4003 */ 4004 4005 s = splusb(); 4006 4007 /* Start inserting frames */ 4008 if (epipe->u.isoc.cur_xfers > 0) { 4009 frindex = epipe->u.isoc.next_frame; 4010 } else { 4011 frindex = EOREAD4(sc, EHCI_FRINDEX); 4012 frindex = frindex >> 3; /* Erase microframe index */ 4013 frindex += 2; 4014 } 4015 4016 if (frindex >= sc->sc_flsize) 4017 frindex &= (sc->sc_flsize - 1); 4018 4019 /* Whats the frame interval? */ 4020 i = (1 << epipe->pipe.endpoint->edesc->bInterval); 4021 if (i / 8 == 0) 4022 i = 1; 4023 else 4024 i /= 8; 4025 4026 itd = start; 4027 for (j = 0; j < frames; j++) { 4028 if (itd == NULL) 4029 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4030 4031 itd->itd.itd_next = sc->sc_flist[frindex]; 4032 if (itd->itd.itd_next == 0) 4033 /* FIXME: frindex table gets initialized to NULL 4034 * or EHCI_NULL? */ 4035 itd->itd.itd_next = htole32(EHCI_NULL); 4036 4037 usb_syncmem(&itd->dma, 4038 itd->offs + offsetof(ehci_itd_t, itd_next), 4039 sizeof(itd->itd.itd_next), 4040 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4041 4042 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4043 4044 usb_syncmem(&sc->sc_fldma, 4045 sizeof(ehci_link_t) * frindex, 4046 sizeof(ehci_link_t), 4047 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4048 4049 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4050 sc->sc_softitds[frindex] = itd; 4051 if (itd->u.frame_list.next != NULL) 4052 itd->u.frame_list.next->u.frame_list.prev = itd; 4053 itd->slot = frindex; 4054 itd->u.frame_list.prev = NULL; 4055 4056 frindex += i; 4057 if (frindex >= sc->sc_flsize) 4058 frindex -= sc->sc_flsize; 4059 4060 itd = itd->xfer_next; 4061 } 4062 4063 epipe->u.isoc.cur_xfers++; 4064 epipe->u.isoc.next_frame = frindex; 4065 4066 exfer->itdstart = start; 4067 exfer->itdend = stop; 4068 exfer->sqtdstart = NULL; 4069 exfer->sqtdstart = NULL; 4070 4071 mutex_enter(&sc->sc_intrhead_lock); 4072 ehci_add_intr_list(sc, exfer); 4073 mutex_exit(&sc->sc_intrhead_lock); 4074 xfer->status = USBD_IN_PROGRESS; 4075 xfer->done = 0; 4076 splx(s); 4077 4078 if (sc->sc_bus.use_polling) { 4079 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4080 ehci_waitintr(sc, xfer); 4081 } 4082 4083 return USBD_IN_PROGRESS; 4084 } 4085 4086 Static void 4087 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4088 { 4089 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4090 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4091 } 4092 4093 Static void 4094 ehci_device_isoc_close(usbd_pipe_handle pipe) 4095 { 4096 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4097 } 4098 4099 Static void 4100 ehci_device_isoc_done(usbd_xfer_handle xfer) 4101 { 4102 struct ehci_xfer *exfer; 4103 ehci_softc_t *sc; 4104 struct ehci_pipe *epipe; 4105 int s; 4106 4107 exfer = EXFER(xfer); 4108 sc = xfer->pipe->device->bus->hci_private; 4109 epipe = (struct ehci_pipe *) xfer->pipe; 4110 4111 s = splusb(); 4112 epipe->u.isoc.cur_xfers--; 4113 mutex_enter(&sc->sc_intrhead_lock); 4114 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4115 ehci_del_intr_list(sc, exfer); 4116 ehci_rem_free_itd_chain(sc, exfer); 4117 } 4118 mutex_exit(&sc->sc_intrhead_lock); 4119 splx(s); 4120 4121 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4122 BUS_DMASYNC_POSTREAD); 4123 4124 } 4125
Indexes created Thu Oct 02 01:09:59 GMT 2025