ehci.c revision 1.154.4.2.4.1
1 /* $NetBSD: ehci.c,v 1.154.4.2.4.1 2011/01/07 02:50:47 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum and 9 * Jeremy Morse (jeremy.morse (at) gmail.com). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 35 * 36 * The EHCI 1.0 spec can be found at 37 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/usb_20.zip 40 * 41 */ 42 43 /* 44 * TODO: 45 * 1) hold off explorations by companion controllers until ehci has started. 46 * 47 * 2) The hub driver needs to handle and schedule the transaction translator, 48 * to assign place in frame where different devices get to go. See chapter 49 * on hubs in USB 2.0 for details. 50 * 51 * 3) command failures are not recovered correctly 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.154.4.2.4.1 2011/01/07 02:50:47 matt Exp $"); 56 57 #include "ohci.h" 58 #include "uhci.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/kernel.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/select.h> 66 #include <sys/proc.h> 67 #include <sys/queue.h> 68 #include <sys/mutex.h> 69 #include <sys/bus.h> 70 71 #include <machine/endian.h> 72 73 #include <dev/usb/usb.h> 74 #include <dev/usb/usbdi.h> 75 #include <dev/usb/usbdivar.h> 76 #include <dev/usb/usb_mem.h> 77 #include <dev/usb/usb_quirks.h> 78 79 #include <dev/usb/ehcireg.h> 80 #include <dev/usb/ehcivar.h> 81 #include <dev/usb/usbroothub_subr.h> 82 83 #ifdef EHCI_DEBUG 84 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 85 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 86 int ehcidebug = 0; 87 #ifndef __NetBSD__ 88 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 89 #endif 90 #else 91 #define DPRINTF(x) 92 #define DPRINTFN(n,x) 93 #endif 94 95 struct ehci_pipe { 96 struct usbd_pipe pipe; 97 int nexttoggle; 98 99 ehci_soft_qh_t *sqh; 100 union { 101 ehci_soft_qtd_t *qtd; 102 /* ehci_soft_itd_t *itd; */ 103 } tail; 104 union { 105 /* Control pipe */ 106 struct { 107 usb_dma_t reqdma; 108 u_int length; 109 } ctl; 110 /* Interrupt pipe */ 111 struct { 112 u_int length; 113 } intr; 114 /* Bulk pipe */ 115 struct { 116 u_int length; 117 } bulk; 118 /* Iso pipe */ 119 struct { 120 u_int next_frame; 121 u_int cur_xfers; 122 } isoc; 123 } u; 124 }; 125 126 Static usbd_status ehci_open(usbd_pipe_handle); 127 Static void ehci_poll(struct usbd_bus *); 128 Static void ehci_softintr(void *); 129 Static int ehci_intr1(ehci_softc_t *); 130 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 131 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 132 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 133 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 134 Static void ehci_idone(struct ehci_xfer *); 135 Static void ehci_timeout(void *); 136 Static void ehci_timeout_task(void *); 137 Static void ehci_intrlist_timeout(void *); 138 139 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 140 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 141 142 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 143 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 144 145 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 146 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 147 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 148 Static void ehci_root_ctrl_close(usbd_pipe_handle); 149 Static void ehci_root_ctrl_done(usbd_xfer_handle); 150 151 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 152 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 153 Static void ehci_root_intr_abort(usbd_xfer_handle); 154 Static void ehci_root_intr_close(usbd_pipe_handle); 155 Static void ehci_root_intr_done(usbd_xfer_handle); 156 157 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 158 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 159 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 160 Static void ehci_device_ctrl_close(usbd_pipe_handle); 161 Static void ehci_device_ctrl_done(usbd_xfer_handle); 162 163 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 164 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 165 Static void ehci_device_bulk_abort(usbd_xfer_handle); 166 Static void ehci_device_bulk_close(usbd_pipe_handle); 167 Static void ehci_device_bulk_done(usbd_xfer_handle); 168 169 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 170 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 171 Static void ehci_device_intr_abort(usbd_xfer_handle); 172 Static void ehci_device_intr_close(usbd_pipe_handle); 173 Static void ehci_device_intr_done(usbd_xfer_handle); 174 175 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 176 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 177 Static void ehci_device_isoc_abort(usbd_xfer_handle); 178 Static void ehci_device_isoc_close(usbd_pipe_handle); 179 Static void ehci_device_isoc_done(usbd_xfer_handle); 180 181 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 182 Static void ehci_noop(usbd_pipe_handle pipe); 183 184 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 185 Static void ehci_disown(ehci_softc_t *, int, int); 186 187 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 188 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 189 190 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 191 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 192 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 193 ehci_softc_t *, int, int, usbd_xfer_handle, 194 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 195 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 196 ehci_soft_qtd_t *); 197 198 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 199 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 200 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 201 struct ehci_xfer *exfer); 202 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 203 usbd_status status); 204 205 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 206 207 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 208 int ival); 209 210 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 211 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 212 ehci_soft_qh_t *); 213 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 214 Static void ehci_sync_hc(ehci_softc_t *); 215 216 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 217 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 218 219 #ifdef EHCI_DEBUG 220 Static void ehci_dump_regs(ehci_softc_t *); 221 void ehci_dump(void); 222 Static ehci_softc_t *theehci; 223 Static void ehci_dump_link(ehci_link_t, int); 224 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 225 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 226 Static void ehci_dump_qtd(ehci_qtd_t *); 227 Static void ehci_dump_sqh(ehci_soft_qh_t *); 228 #if notyet 229 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 230 Static void ehci_dump_itd(struct ehci_soft_itd *); 231 #endif 232 #ifdef DIAGNOSTIC 233 Static void ehci_dump_exfer(struct ehci_xfer *); 234 #endif 235 #endif 236 237 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 238 239 #define EHCI_INTR_ENDPT 1 240 241 #define ehci_add_intr_list(sc, ex) \ 242 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 243 #define ehci_del_intr_list(sc, ex) \ 244 do { \ 245 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 246 (ex)->inext.tqe_prev = NULL; \ 247 } while (0) 248 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 249 250 Static const struct usbd_bus_methods ehci_bus_methods = { 251 ehci_open, 252 ehci_softintr, 253 ehci_poll, 254 ehci_allocm, 255 ehci_freem, 256 ehci_allocx, 257 ehci_freex, 258 }; 259 260 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 261 ehci_root_ctrl_transfer, 262 ehci_root_ctrl_start, 263 ehci_root_ctrl_abort, 264 ehci_root_ctrl_close, 265 ehci_noop, 266 ehci_root_ctrl_done, 267 }; 268 269 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 270 ehci_root_intr_transfer, 271 ehci_root_intr_start, 272 ehci_root_intr_abort, 273 ehci_root_intr_close, 274 ehci_noop, 275 ehci_root_intr_done, 276 }; 277 278 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 279 ehci_device_ctrl_transfer, 280 ehci_device_ctrl_start, 281 ehci_device_ctrl_abort, 282 ehci_device_ctrl_close, 283 ehci_noop, 284 ehci_device_ctrl_done, 285 }; 286 287 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 288 ehci_device_intr_transfer, 289 ehci_device_intr_start, 290 ehci_device_intr_abort, 291 ehci_device_intr_close, 292 ehci_device_clear_toggle, 293 ehci_device_intr_done, 294 }; 295 296 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 297 ehci_device_bulk_transfer, 298 ehci_device_bulk_start, 299 ehci_device_bulk_abort, 300 ehci_device_bulk_close, 301 ehci_device_clear_toggle, 302 ehci_device_bulk_done, 303 }; 304 305 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 306 ehci_device_isoc_transfer, 307 ehci_device_isoc_start, 308 ehci_device_isoc_abort, 309 ehci_device_isoc_close, 310 ehci_noop, 311 ehci_device_isoc_done, 312 }; 313 314 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 315 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 316 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 317 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 318 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 319 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 320 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 321 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 322 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 323 }; 324 325 usbd_status 326 ehci_init(ehci_softc_t *sc) 327 { 328 u_int32_t vers, sparams, cparams, hcr; 329 u_int i; 330 usbd_status err; 331 ehci_soft_qh_t *sqh; 332 u_int ncomp; 333 334 DPRINTF(("ehci_init: start\n")); 335 #ifdef EHCI_DEBUG 336 theehci = sc; 337 #endif 338 339 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 340 341 vers = EREAD2(sc, EHCI_HCIVERSION); 342 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 343 vers >> 8, vers & 0xff); 344 345 sparams = EREAD4(sc, EHCI_HCSPARAMS); 346 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 347 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 348 ncomp = EHCI_HCS_N_CC(sparams); 349 if (ncomp != sc->sc_ncomp) { 350 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 351 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 352 #if NOHCI == 0 || NUHCI == 0 353 aprint_error("%s: ohci or uhci probably not configured\n", 354 device_xname(sc->sc_dev)); 355 #endif 356 if (ncomp < sc->sc_ncomp) 357 sc->sc_ncomp = ncomp; 358 } 359 if (sc->sc_ncomp > 0) { 360 aprint_normal("%s: companion controller%s, %d port%s each:", 361 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 362 EHCI_HCS_N_PCC(sparams), 363 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 364 for (i = 0; i < sc->sc_ncomp; i++) 365 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 366 aprint_normal("\n"); 367 } 368 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 369 cparams = EREAD4(sc, EHCI_HCCPARAMS); 370 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 371 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 372 373 if (EHCI_HCC_64BIT(cparams)) { 374 /* MUST clear segment register if 64 bit capable. */ 375 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 376 } 377 378 sc->sc_bus.usbrev = USBREV_2_0; 379 380 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 381 USB_MEM_RESERVE); 382 383 /* Reset the controller */ 384 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 385 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 386 usb_delay_ms(&sc->sc_bus, 1); 387 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 388 for (i = 0; i < 100; i++) { 389 usb_delay_ms(&sc->sc_bus, 1); 390 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 391 if (!hcr) 392 break; 393 } 394 if (hcr) { 395 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 396 return (USBD_IOERROR); 397 } 398 399 /* 400 * If we are doing embedded transaction translation function, force 401 * the controller to host mode. 402 */ 403 if (sc->sc_flags & EHCIF_ETTF) { 404 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 405 usbmode &= ~EHCI_USBMODE_CM; 406 usbmode |= EHCI_USBMODE_CM_HOST; 407 EWRITE4(sc, EHCI_USBMODE, usbmode); 408 } 409 410 /* XXX need proper intr scheduling */ 411 sc->sc_rand = 96; 412 413 /* frame list size at default, read back what we got and use that */ 414 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 415 case 0: sc->sc_flsize = 1024; break; 416 case 1: sc->sc_flsize = 512; break; 417 case 2: sc->sc_flsize = 256; break; 418 case 3: return (USBD_IOERROR); 419 } 420 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 421 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 422 if (err) 423 return (err); 424 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 425 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 426 427 for (i = 0; i < sc->sc_flsize; i++) { 428 sc->sc_flist[i] = EHCI_NULL; 429 } 430 431 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 432 433 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 434 M_USB, M_NOWAIT | M_ZERO); 435 if (sc->sc_softitds == NULL) 436 return ENOMEM; 437 LIST_INIT(&sc->sc_freeitds); 438 TAILQ_INIT(&sc->sc_intrhead); 439 mutex_init(&sc->sc_intrhead_lock, MUTEX_DEFAULT, IPL_USB); 440 441 /* Set up the bus struct. */ 442 sc->sc_bus.methods = &ehci_bus_methods; 443 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 444 445 sc->sc_eintrs = EHCI_NORMAL_INTRS; 446 447 /* 448 * Allocate the interrupt dummy QHs. These are arranged to give poll 449 * intervals that are powers of 2 times 1ms. 450 */ 451 for (i = 0; i < EHCI_INTRQHS; i++) { 452 sqh = ehci_alloc_sqh(sc); 453 if (sqh == NULL) { 454 err = USBD_NOMEM; 455 goto bad1; 456 } 457 sc->sc_islots[i].sqh = sqh; 458 } 459 for (i = 0; i < EHCI_INTRQHS; i++) { 460 sqh = sc->sc_islots[i].sqh; 461 if (i == 0) { 462 /* The last (1ms) QH terminates. */ 463 sqh->qh.qh_link = EHCI_NULL; 464 sqh->next = NULL; 465 } else { 466 /* Otherwise the next QH has half the poll interval */ 467 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 468 sqh->qh.qh_link = htole32(sqh->next->physaddr | 469 EHCI_LINK_QH); 470 } 471 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 472 sqh->qh.qh_curqtd = EHCI_NULL; 473 sqh->next = NULL; 474 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 475 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 476 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 477 sqh->sqtd = NULL; 478 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 479 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 480 } 481 /* Point the frame list at the last level (128ms). */ 482 for (i = 0; i < sc->sc_flsize; i++) { 483 int j; 484 485 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 486 revbits[i & (EHCI_MAX_POLLRATE-1)]; 487 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 488 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 489 i)].sqh->physaddr); 490 } 491 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 492 BUS_DMASYNC_PREWRITE); 493 494 /* Allocate dummy QH that starts the async list. */ 495 sqh = ehci_alloc_sqh(sc); 496 if (sqh == NULL) { 497 err = USBD_NOMEM; 498 goto bad1; 499 } 500 /* Fill the QH */ 501 sqh->qh.qh_endp = 502 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 503 sqh->qh.qh_link = 504 htole32(sqh->physaddr | EHCI_LINK_QH); 505 sqh->qh.qh_curqtd = EHCI_NULL; 506 sqh->next = NULL; 507 /* Fill the overlay qTD */ 508 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 509 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 510 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 511 sqh->sqtd = NULL; 512 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 513 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 514 #ifdef EHCI_DEBUG 515 if (ehcidebug) { 516 ehci_dump_sqh(sqh); 517 } 518 #endif 519 520 /* Point to async list */ 521 sc->sc_async_head = sqh; 522 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 523 524 usb_callout_init(sc->sc_tmo_intrlist); 525 526 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE); 527 528 /* Turn on controller */ 529 EOWRITE4(sc, EHCI_USBCMD, 530 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 531 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 532 EHCI_CMD_ASE | 533 EHCI_CMD_PSE | 534 EHCI_CMD_RS); 535 536 /* Take over port ownership */ 537 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 538 539 for (i = 0; i < 100; i++) { 540 usb_delay_ms(&sc->sc_bus, 1); 541 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 542 if (!hcr) 543 break; 544 } 545 if (hcr) { 546 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 547 return (USBD_IOERROR); 548 } 549 550 /* Enable interrupts */ 551 DPRINTFN(1,("ehci_init: enabling\n")); 552 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 553 554 return (USBD_NORMAL_COMPLETION); 555 556 #if 0 557 bad2: 558 ehci_free_sqh(sc, sc->sc_async_head); 559 #endif 560 bad1: 561 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 562 return (err); 563 } 564 565 int 566 ehci_intr(void *v) 567 { 568 ehci_softc_t *sc = v; 569 570 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 571 return (0); 572 573 /* If we get an interrupt while polling, then just ignore it. */ 574 if (sc->sc_bus.use_polling) { 575 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 576 577 if (intrs) 578 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 579 #ifdef DIAGNOSTIC 580 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 581 #endif 582 return (0); 583 } 584 585 return (ehci_intr1(sc)); 586 } 587 588 Static int 589 ehci_intr1(ehci_softc_t *sc) 590 { 591 u_int32_t intrs, eintrs; 592 593 DPRINTFN(20,("ehci_intr1: enter\n")); 594 595 /* In case the interrupt occurs before initialization has completed. */ 596 if (sc == NULL) { 597 #ifdef DIAGNOSTIC 598 printf("ehci_intr1: sc == NULL\n"); 599 #endif 600 return (0); 601 } 602 603 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 604 if (!intrs) 605 return (0); 606 607 eintrs = intrs & sc->sc_eintrs; 608 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 609 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 610 (u_int)eintrs)); 611 if (!eintrs) 612 return (0); 613 614 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 615 sc->sc_bus.intr_context++; 616 sc->sc_bus.no_intrs++; 617 if (eintrs & EHCI_STS_IAA) { 618 DPRINTF(("ehci_intr1: door bell\n")); 619 wakeup(&sc->sc_async_head); 620 eintrs &= ~EHCI_STS_IAA; 621 } 622 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 623 DPRINTFN(5,("ehci_intr1: %s %s\n", 624 eintrs & EHCI_STS_INT ? "INT" : "", 625 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 626 usb_schedsoftintr(&sc->sc_bus); 627 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 628 } 629 if (eintrs & EHCI_STS_HSE) { 630 printf("%s: unrecoverable error, controller halted\n", 631 device_xname(sc->sc_dev)); 632 /* XXX what else */ 633 } 634 if (eintrs & EHCI_STS_PCD) { 635 ehci_pcd(sc, sc->sc_intrxfer); 636 eintrs &= ~EHCI_STS_PCD; 637 } 638 639 sc->sc_bus.intr_context--; 640 641 if (eintrs != 0) { 642 /* Block unprocessed interrupts. */ 643 sc->sc_eintrs &= ~eintrs; 644 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 645 printf("%s: blocking intrs 0x%x\n", 646 device_xname(sc->sc_dev), eintrs); 647 } 648 649 return (1); 650 } 651 652 653 void 654 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 655 { 656 usbd_pipe_handle pipe; 657 u_char *p; 658 int i, m; 659 660 if (xfer == NULL) { 661 /* Just ignore the change. */ 662 return; 663 } 664 665 pipe = xfer->pipe; 666 667 p = KERNADDR(&xfer->dmabuf, 0); 668 m = min(sc->sc_noport, xfer->length * 8 - 1); 669 memset(p, 0, xfer->length); 670 for (i = 1; i <= m; i++) { 671 /* Pick out CHANGE bits from the status reg. */ 672 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 673 p[i/8] |= 1 << (i%8); 674 } 675 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 676 xfer->actlen = xfer->length; 677 xfer->status = USBD_NORMAL_COMPLETION; 678 679 usb_transfer_complete(xfer); 680 } 681 682 void 683 ehci_softintr(void *v) 684 { 685 struct usbd_bus *bus = v; 686 ehci_softc_t *sc = bus->hci_private; 687 struct ehci_xfer *ex, *nextex; 688 689 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 690 sc->sc_bus.intr_context)); 691 692 sc->sc_bus.intr_context++; 693 694 /* 695 * The only explanation I can think of for why EHCI is as brain dead 696 * as UHCI interrupt-wise is that Intel was involved in both. 697 * An interrupt just tells us that something is done, we have no 698 * clue what, so we need to scan through all active transfers. :-( 699 */ 700 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 701 nextex = TAILQ_NEXT(ex, inext); 702 ehci_check_intr(sc, ex); 703 } 704 705 /* Schedule a callout to catch any dropped transactions. */ 706 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 707 !TAILQ_EMPTY(&sc->sc_intrhead)) 708 usb_callout(sc->sc_tmo_intrlist, hz, 709 ehci_intrlist_timeout, sc); 710 711 #ifdef USB_USE_SOFTINTR 712 if (sc->sc_softwake) { 713 sc->sc_softwake = 0; 714 wakeup(&sc->sc_softwake); 715 } 716 #endif /* USB_USE_SOFTINTR */ 717 718 sc->sc_bus.intr_context--; 719 } 720 721 /* Check for an interrupt. */ 722 void 723 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 724 { 725 int attr; 726 727 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 728 729 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 730 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 731 ehci_check_itd_intr(sc, ex); 732 else 733 ehci_check_qh_intr(sc, ex); 734 735 return; 736 } 737 738 void 739 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 740 { 741 ehci_soft_qtd_t *sqtd, *lsqtd; 742 __uint32_t status; 743 744 if (ex->sqtdstart == NULL) { 745 printf("ehci_check_qh_intr: not valid sqtd\n"); 746 return; 747 } 748 749 lsqtd = ex->sqtdend; 750 #ifdef DIAGNOSTIC 751 if (lsqtd == NULL) { 752 printf("ehci_check_qh_intr: lsqtd==0\n"); 753 return; 754 } 755 #endif 756 /* 757 * If the last TD is still active we need to check whether there 758 * is a an error somewhere in the middle, or whether there was a 759 * short packet (SPD and not ACTIVE). 760 */ 761 usb_syncmem(&lsqtd->dma, 762 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 763 sizeof(lsqtd->qtd.qtd_status), 764 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 765 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 766 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 767 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 768 usb_syncmem(&sqtd->dma, 769 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 770 sizeof(sqtd->qtd.qtd_status), 771 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 772 status = le32toh(sqtd->qtd.qtd_status); 773 usb_syncmem(&sqtd->dma, 774 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 775 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 776 /* If there's an active QTD the xfer isn't done. */ 777 if (status & EHCI_QTD_ACTIVE) 778 break; 779 /* Any kind of error makes the xfer done. */ 780 if (status & EHCI_QTD_HALTED) 781 goto done; 782 /* We want short packets, and it is short: it's done */ 783 if (EHCI_QTD_GET_BYTES(status) != 0) 784 goto done; 785 } 786 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 787 ex, ex->sqtdstart)); 788 usb_syncmem(&lsqtd->dma, 789 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 790 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 791 return; 792 } 793 done: 794 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 795 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 796 ehci_idone(ex); 797 } 798 799 void 800 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 801 ehci_soft_itd_t *itd; 802 int i; 803 804 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 805 return; 806 807 if (ex->itdstart == NULL) { 808 printf("ehci_check_itd_intr: not valid itd\n"); 809 return; 810 } 811 812 itd = ex->itdend; 813 #ifdef DIAGNOSTIC 814 if (itd == NULL) { 815 printf("ehci_check_itd_intr: itdend == 0\n"); 816 return; 817 } 818 #endif 819 820 /* 821 * check no active transfers in last itd, meaning we're finished 822 */ 823 824 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 825 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 826 BUS_DMASYNC_POSTREAD); 827 828 for (i = 0; i < 8; i++) { 829 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 830 break; 831 } 832 833 if (i == 8) { 834 goto done; /* All 8 descriptors inactive, it's done */ 835 } 836 837 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 838 ex->itdstart)); 839 return; 840 done: 841 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 842 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 843 ehci_idone(ex); 844 } 845 846 void 847 ehci_idone(struct ehci_xfer *ex) 848 { 849 usbd_xfer_handle xfer = &ex->xfer; 850 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 851 ehci_soft_qtd_t *sqtd, *lsqtd; 852 u_int32_t status = 0, nstatus = 0; 853 int actlen; 854 855 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 856 #ifdef DIAGNOSTIC 857 { 858 int s = splhigh(); 859 if (ex->isdone) { 860 splx(s); 861 #ifdef EHCI_DEBUG 862 printf("ehci_idone: ex is done!\n "); 863 ehci_dump_exfer(ex); 864 #else 865 printf("ehci_idone: ex=%p is done!\n", ex); 866 #endif 867 return; 868 } 869 ex->isdone = 1; 870 splx(s); 871 } 872 #endif 873 if (xfer->status == USBD_CANCELLED || 874 xfer->status == USBD_TIMEOUT) { 875 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 876 return; 877 } 878 879 #ifdef EHCI_DEBUG 880 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 881 if (ehcidebug > 10) 882 ehci_dump_sqtds(ex->sqtdstart); 883 #endif 884 885 /* The transfer is done, compute actual length and status. */ 886 887 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 888 == UE_ISOCHRONOUS) { 889 /* Isoc transfer */ 890 struct ehci_soft_itd *itd; 891 int i, nframes, len, uframes; 892 893 nframes = 0; 894 actlen = 0; 895 896 switch (xfer->pipe->endpoint->edesc->bInterval) { 897 case 0: 898 panic("ehci: isoc xfer suddenly has 0 bInterval, invalid\n"); 899 case 1: uframes = 1; break; 900 case 2: uframes = 2; break; 901 case 3: uframes = 4; break; 902 default: uframes = 8; break; 903 } 904 905 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 906 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 907 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 908 BUS_DMASYNC_POSTREAD); 909 910 for (i = 0; i < 8; i += uframes) { 911 /* XXX - driver didn't fill in the frame full 912 * of uframes. This leads to scheduling 913 * inefficiencies, but working around 914 * this doubles complexity of tracking 915 * an xfer. 916 */ 917 if (nframes >= xfer->nframes) 918 break; 919 920 status = le32toh(itd->itd.itd_ctl[i]); 921 len = EHCI_ITD_GET_LEN(status); 922 if (EHCI_ITD_GET_STATUS(status) != 0) 923 len = 0; /*No valid data on error*/ 924 925 xfer->frlengths[nframes++] = len; 926 actlen += len; 927 } 928 929 if (nframes >= xfer->nframes) 930 break; 931 } 932 933 xfer->actlen = actlen; 934 xfer->status = USBD_NORMAL_COMPLETION; 935 goto end; 936 } 937 938 /* Continue processing xfers using queue heads */ 939 940 lsqtd = ex->sqtdend; 941 actlen = 0; 942 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 943 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 944 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 945 nstatus = le32toh(sqtd->qtd.qtd_status); 946 if (nstatus & EHCI_QTD_ACTIVE) 947 break; 948 949 status = nstatus; 950 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 951 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 952 } 953 954 955 /* 956 * If there are left over TDs we need to update the toggle. 957 * The default pipe doesn't need it since control transfers 958 * start the toggle at 0 every time. 959 * For a short transfer we need to update the toggle for the missing 960 * packets within the qTD. 961 */ 962 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 963 xfer->pipe->device->default_pipe != xfer->pipe) { 964 DPRINTFN(2, ("ehci_idone: need toggle update " 965 "status=%08x nstatus=%08x\n", status, nstatus)); 966 #if 0 967 ehci_dump_sqh(epipe->sqh); 968 ehci_dump_sqtds(ex->sqtdstart); 969 #endif 970 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 971 } 972 973 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 974 xfer->length, actlen, status)); 975 xfer->actlen = actlen; 976 if (status & EHCI_QTD_HALTED) { 977 #ifdef EHCI_DEBUG 978 char sbuf[128]; 979 980 bitmask_snprintf((u_int32_t)status, 981 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR" 982 "\3MISSED\1PINGSTATE", sbuf, sizeof(sbuf)); 983 984 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 985 "status 0x%s\n", 986 xfer->pipe->device->address, 987 xfer->pipe->endpoint->edesc->bEndpointAddress, 988 sbuf)); 989 if (ehcidebug > 2) { 990 ehci_dump_sqh(epipe->sqh); 991 ehci_dump_sqtds(ex->sqtdstart); 992 } 993 #endif 994 /* low&full speed has an extra error flag */ 995 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 996 EHCI_QH_SPEED_HIGH) 997 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 998 else 999 status &= EHCI_QTD_STATERRS; 1000 if (status == 0) /* no other errors means a stall */ { 1001 xfer->status = USBD_STALLED; 1002 } else { 1003 xfer->status = USBD_IOERROR; /* more info XXX */ 1004 } 1005 /* XXX need to reset TT on missed microframe */ 1006 if (status & EHCI_QTD_MISSEDMICRO) { 1007 ehci_softc_t *sc = 1008 xfer->pipe->device->bus->hci_private; 1009 1010 printf("%s: missed microframe, TT reset not " 1011 "implemented, hub might be inoperational\n", 1012 device_xname(sc->sc_dev)); 1013 } 1014 } else { 1015 xfer->status = USBD_NORMAL_COMPLETION; 1016 } 1017 1018 end: 1019 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1020 * during this call, before methods->done is called: dma sync required 1021 * beforehand? */ 1022 usb_transfer_complete(xfer); 1023 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1024 } 1025 1026 /* 1027 * Wait here until controller claims to have an interrupt. 1028 * Then call ehci_intr and return. Use timeout to avoid waiting 1029 * too long. 1030 */ 1031 void 1032 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1033 { 1034 int timo; 1035 u_int32_t intrs; 1036 1037 xfer->status = USBD_IN_PROGRESS; 1038 for (timo = xfer->timeout; timo >= 0; timo--) { 1039 usb_delay_ms(&sc->sc_bus, 1); 1040 if (sc->sc_dying) 1041 break; 1042 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1043 sc->sc_eintrs; 1044 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1045 #ifdef EHCI_DEBUG 1046 if (ehcidebug > 15) 1047 ehci_dump_regs(sc); 1048 #endif 1049 if (intrs) { 1050 ehci_intr1(sc); 1051 if (xfer->status != USBD_IN_PROGRESS) 1052 return; 1053 } 1054 } 1055 1056 /* Timeout */ 1057 DPRINTF(("ehci_waitintr: timeout\n")); 1058 xfer->status = USBD_TIMEOUT; 1059 usb_transfer_complete(xfer); 1060 /* XXX should free TD */ 1061 } 1062 1063 void 1064 ehci_poll(struct usbd_bus *bus) 1065 { 1066 ehci_softc_t *sc = bus->hci_private; 1067 #ifdef EHCI_DEBUG 1068 static int last; 1069 int new; 1070 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1071 if (new != last) { 1072 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1073 last = new; 1074 } 1075 #endif 1076 1077 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1078 ehci_intr1(sc); 1079 } 1080 1081 void 1082 ehci_childdet(device_t self, device_t child) 1083 { 1084 struct ehci_softc *sc = device_private(self); 1085 1086 KASSERT(sc->sc_child == child); 1087 sc->sc_child = NULL; 1088 } 1089 1090 int 1091 ehci_detach(struct ehci_softc *sc, int flags) 1092 { 1093 int rv = 0; 1094 1095 if (sc->sc_child != NULL) 1096 rv = config_detach(sc->sc_child, flags); 1097 1098 if (rv != 0) 1099 return (rv); 1100 1101 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 1102 1103 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1104 1105 /* XXX free other data structures XXX */ 1106 mutex_destroy(&sc->sc_doorbell_lock); 1107 mutex_destroy(&sc->sc_intrhead_lock); 1108 1109 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1110 1111 return (rv); 1112 } 1113 1114 1115 int 1116 ehci_activate(device_t self, enum devact act) 1117 { 1118 struct ehci_softc *sc = device_private(self); 1119 int rv = 0; 1120 1121 switch (act) { 1122 case DVACT_ACTIVATE: 1123 return (EOPNOTSUPP); 1124 1125 case DVACT_DEACTIVATE: 1126 sc->sc_dying = 1; 1127 if (sc->sc_child != NULL) 1128 rv = config_deactivate(sc->sc_child); 1129 break; 1130 } 1131 return (rv); 1132 } 1133 1134 /* 1135 * Handle suspend/resume. 1136 * 1137 * We need to switch to polling mode here, because this routine is 1138 * called from an interrupt context. This is all right since we 1139 * are almost suspended anyway. 1140 * 1141 * Note that this power handler isn't to be registered directly; the 1142 * bus glue needs to call out to it. 1143 */ 1144 bool 1145 ehci_suspend(device_t dv PMF_FN_ARGS) 1146 { 1147 ehci_softc_t *sc = device_private(dv); 1148 int i, s; 1149 uint32_t cmd, hcr; 1150 1151 s = splhardusb(); 1152 1153 sc->sc_bus.use_polling++; 1154 1155 for (i = 1; i <= sc->sc_noport; i++) { 1156 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1157 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1158 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1159 } 1160 1161 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1162 1163 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1164 EOWRITE4(sc, EHCI_USBCMD, cmd); 1165 1166 for (i = 0; i < 100; i++) { 1167 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1168 if (hcr == 0) 1169 break; 1170 1171 usb_delay_ms(&sc->sc_bus, 1); 1172 } 1173 if (hcr != 0) 1174 printf("%s: reset timeout\n", device_xname(dv)); 1175 1176 cmd &= ~EHCI_CMD_RS; 1177 EOWRITE4(sc, EHCI_USBCMD, cmd); 1178 1179 for (i = 0; i < 100; i++) { 1180 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1181 if (hcr == EHCI_STS_HCH) 1182 break; 1183 1184 usb_delay_ms(&sc->sc_bus, 1); 1185 } 1186 if (hcr != EHCI_STS_HCH) 1187 printf("%s: config timeout\n", device_xname(dv)); 1188 1189 sc->sc_bus.use_polling--; 1190 splx(s); 1191 1192 return true; 1193 } 1194 1195 bool 1196 ehci_resume(device_t dv PMF_FN_ARGS) 1197 { 1198 ehci_softc_t *sc = device_private(dv); 1199 int i; 1200 uint32_t cmd, hcr; 1201 1202 /* restore things in case the bios sucks */ 1203 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1204 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1205 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1206 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1207 1208 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1209 1210 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1211 1212 hcr = 0; 1213 for (i = 1; i <= sc->sc_noport; i++) { 1214 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1215 if ((cmd & EHCI_PS_PO) == 0 && 1216 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1217 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1218 hcr = 1; 1219 } 1220 } 1221 1222 if (hcr) { 1223 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1224 1225 for (i = 1; i <= sc->sc_noport; i++) { 1226 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1227 if ((cmd & EHCI_PS_PO) == 0 && 1228 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1229 EOWRITE4(sc, EHCI_PORTSC(i), 1230 cmd & ~EHCI_PS_FPR); 1231 } 1232 } 1233 1234 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1235 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1236 1237 for (i = 0; i < 100; i++) { 1238 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1239 if (hcr != EHCI_STS_HCH) 1240 break; 1241 1242 usb_delay_ms(&sc->sc_bus, 1); 1243 } 1244 if (hcr == EHCI_STS_HCH) 1245 printf("%s: config timeout\n", device_xname(dv)); 1246 1247 return true; 1248 } 1249 1250 /* 1251 * Shut down the controller when the system is going down. 1252 */ 1253 bool 1254 ehci_shutdown(device_t self, int flags) 1255 { 1256 ehci_softc_t *sc = device_private(self); 1257 1258 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1259 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1260 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1261 return true; 1262 } 1263 1264 usbd_status 1265 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1266 { 1267 struct ehci_softc *sc = bus->hci_private; 1268 usbd_status err; 1269 1270 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1271 if (err == USBD_NOMEM) 1272 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1273 #ifdef EHCI_DEBUG 1274 if (err) 1275 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1276 #endif 1277 return (err); 1278 } 1279 1280 void 1281 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1282 { 1283 struct ehci_softc *sc = bus->hci_private; 1284 1285 if (dma->block->flags & USB_DMA_RESERVE) { 1286 usb_reserve_freem(&sc->sc_dma_reserve, 1287 dma); 1288 return; 1289 } 1290 usb_freemem(&sc->sc_bus, dma); 1291 } 1292 1293 usbd_xfer_handle 1294 ehci_allocx(struct usbd_bus *bus) 1295 { 1296 struct ehci_softc *sc = bus->hci_private; 1297 usbd_xfer_handle xfer; 1298 1299 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1300 if (xfer != NULL) { 1301 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1302 #ifdef DIAGNOSTIC 1303 if (xfer->busy_free != XFER_FREE) { 1304 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1305 xfer->busy_free); 1306 } 1307 #endif 1308 } else { 1309 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1310 } 1311 if (xfer != NULL) { 1312 memset(xfer, 0, sizeof(struct ehci_xfer)); 1313 #ifdef DIAGNOSTIC 1314 EXFER(xfer)->isdone = 1; 1315 xfer->busy_free = XFER_BUSY; 1316 #endif 1317 } 1318 return (xfer); 1319 } 1320 1321 void 1322 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1323 { 1324 struct ehci_softc *sc = bus->hci_private; 1325 1326 #ifdef DIAGNOSTIC 1327 if (xfer->busy_free != XFER_BUSY) { 1328 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1329 xfer->busy_free); 1330 } 1331 xfer->busy_free = XFER_FREE; 1332 if (!EXFER(xfer)->isdone) { 1333 printf("ehci_freex: !isdone\n"); 1334 } 1335 #endif 1336 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1337 } 1338 1339 Static void 1340 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1341 { 1342 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1343 1344 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1345 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1346 #ifdef USB_DEBUG 1347 if (ehcidebug) 1348 usbd_dump_pipe(pipe); 1349 #endif 1350 epipe->nexttoggle = 0; 1351 } 1352 1353 Static void 1354 ehci_noop(usbd_pipe_handle pipe) 1355 { 1356 } 1357 1358 #ifdef EHCI_DEBUG 1359 void 1360 ehci_dump_regs(ehci_softc_t *sc) 1361 { 1362 int i; 1363 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1364 EOREAD4(sc, EHCI_USBCMD), 1365 EOREAD4(sc, EHCI_USBSTS), 1366 EOREAD4(sc, EHCI_USBINTR)); 1367 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1368 EOREAD4(sc, EHCI_FRINDEX), 1369 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1370 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1371 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1372 for (i = 1; i <= sc->sc_noport; i++) 1373 printf("port %d status=0x%08x\n", i, 1374 EOREAD4(sc, EHCI_PORTSC(i))); 1375 } 1376 1377 /* 1378 * Unused function - this is meant to be called from a kernel 1379 * debugger. 1380 */ 1381 void 1382 ehci_dump() 1383 { 1384 ehci_dump_regs(theehci); 1385 } 1386 1387 void 1388 ehci_dump_link(ehci_link_t link, int type) 1389 { 1390 link = le32toh(link); 1391 printf("0x%08x", link); 1392 if (link & EHCI_LINK_TERMINATE) 1393 printf("<T>"); 1394 else { 1395 printf("<"); 1396 if (type) { 1397 switch (EHCI_LINK_TYPE(link)) { 1398 case EHCI_LINK_ITD: printf("ITD"); break; 1399 case EHCI_LINK_QH: printf("QH"); break; 1400 case EHCI_LINK_SITD: printf("SITD"); break; 1401 case EHCI_LINK_FSTN: printf("FSTN"); break; 1402 } 1403 } 1404 printf(">"); 1405 } 1406 } 1407 1408 void 1409 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1410 { 1411 int i; 1412 u_int32_t stop; 1413 1414 stop = 0; 1415 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1416 ehci_dump_sqtd(sqtd); 1417 usb_syncmem(&sqtd->dma, 1418 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1419 sizeof(sqtd->qtd), 1420 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1421 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1422 usb_syncmem(&sqtd->dma, 1423 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1424 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1425 } 1426 if (sqtd) 1427 printf("dump aborted, too many TDs\n"); 1428 } 1429 1430 void 1431 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1432 { 1433 usb_syncmem(&sqtd->dma, sqtd->offs, 1434 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1435 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1436 ehci_dump_qtd(&sqtd->qtd); 1437 usb_syncmem(&sqtd->dma, sqtd->offs, 1438 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1439 } 1440 1441 void 1442 ehci_dump_qtd(ehci_qtd_t *qtd) 1443 { 1444 u_int32_t s; 1445 char sbuf[128]; 1446 1447 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1448 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1449 printf("\n"); 1450 s = le32toh(qtd->qtd_status); 1451 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 1452 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1453 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 1454 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1455 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1456 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1457 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1458 EHCI_QTD_GET_PID(s), sbuf); 1459 for (s = 0; s < 5; s++) 1460 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1461 } 1462 1463 void 1464 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1465 { 1466 ehci_qh_t *qh = &sqh->qh; 1467 u_int32_t endp, endphub; 1468 1469 usb_syncmem(&sqh->dma, sqh->offs, 1470 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1471 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1472 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1473 endp = le32toh(qh->qh_endp); 1474 printf(" endp=0x%08x\n", endp); 1475 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1476 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1477 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1478 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1479 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1480 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1481 EHCI_QH_GET_NRL(endp)); 1482 endphub = le32toh(qh->qh_endphub); 1483 printf(" endphub=0x%08x\n", endphub); 1484 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1485 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1486 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1487 EHCI_QH_GET_MULT(endphub)); 1488 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1489 printf("Overlay qTD:\n"); 1490 ehci_dump_qtd(&qh->qh_qtd); 1491 usb_syncmem(&sqh->dma, sqh->offs, 1492 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1493 } 1494 1495 #if notyet 1496 void 1497 ehci_dump_itd(struct ehci_soft_itd *itd) 1498 { 1499 ehci_isoc_trans_t t; 1500 ehci_isoc_bufr_ptr_t b, b2, b3; 1501 int i; 1502 1503 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1504 1505 for (i = 0; i < 8;i++) { 1506 t = le32toh(itd->itd.itd_ctl[i]); 1507 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1508 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1509 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1510 EHCI_ITD_GET_OFFS(t)); 1511 } 1512 printf("ITDbufr: "); 1513 for (i = 0; i < 7; i++) 1514 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1515 1516 b = le32toh(itd->itd.itd_bufr[0]); 1517 b2 = le32toh(itd->itd.itd_bufr[1]); 1518 b3 = le32toh(itd->itd.itd_bufr[2]); 1519 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1520 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1521 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1522 } 1523 1524 void 1525 ehci_dump_sitd(struct ehci_soft_itd *itd) 1526 { 1527 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1528 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1529 itd->xfer_next, itd->physaddr, itd->slot); 1530 } 1531 #endif 1532 1533 #ifdef DIAGNOSTIC 1534 void 1535 ehci_dump_exfer(struct ehci_xfer *ex) 1536 { 1537 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1538 } 1539 #endif 1540 #endif 1541 1542 usbd_status 1543 ehci_open(usbd_pipe_handle pipe) 1544 { 1545 usbd_device_handle dev = pipe->device; 1546 ehci_softc_t *sc = dev->bus->hci_private; 1547 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1548 u_int8_t addr = dev->address; 1549 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1550 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1551 ehci_soft_qh_t *sqh; 1552 usbd_status err; 1553 int s; 1554 int ival, speed, naks; 1555 int hshubaddr, hshubport; 1556 1557 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1558 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1559 1560 if (dev->myhsport) { 1561 /* 1562 * When directly attached FS/LS device while doing embedded 1563 * transaction translations and we are the hub, set the hub 1564 * adddress to 0 (us). 1565 */ 1566 if (!(sc->sc_flags & EHCIF_ETTF) 1567 || (dev->myhsport->parent->address != sc->sc_addr)) { 1568 hshubaddr = dev->myhsport->parent->address; 1569 } else { 1570 hshubaddr = 0; 1571 } 1572 hshubport = dev->myhsport->portno; 1573 } else { 1574 hshubaddr = 0; 1575 hshubport = 0; 1576 } 1577 1578 if (sc->sc_dying) 1579 return (USBD_IOERROR); 1580 1581 epipe->nexttoggle = 0; 1582 1583 if (addr == sc->sc_addr) { 1584 switch (ed->bEndpointAddress) { 1585 case USB_CONTROL_ENDPOINT: 1586 pipe->methods = &ehci_root_ctrl_methods; 1587 break; 1588 case UE_DIR_IN | EHCI_INTR_ENDPT: 1589 pipe->methods = &ehci_root_intr_methods; 1590 break; 1591 default: 1592 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1593 ed->bEndpointAddress)); 1594 return (USBD_INVAL); 1595 } 1596 return (USBD_NORMAL_COMPLETION); 1597 } 1598 1599 /* XXX All this stuff is only valid for async. */ 1600 switch (dev->speed) { 1601 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1602 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1603 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1604 default: panic("ehci_open: bad device speed %d", dev->speed); 1605 } 1606 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1607 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1608 "isoc endpoint.\n"); 1609 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1610 "attached to a USB2 hub, and transaction translations are " 1611 "not yet supported.\n"); 1612 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1613 "root hub instead.\n"); 1614 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1615 hshubaddr, hshubport)); 1616 return USBD_INVAL; 1617 } 1618 1619 naks = 8; /* XXX */ 1620 1621 /* Allocate sqh for everything, save isoc xfers */ 1622 if (xfertype != UE_ISOCHRONOUS) { 1623 sqh = ehci_alloc_sqh(sc); 1624 if (sqh == NULL) 1625 return (USBD_NOMEM); 1626 /* qh_link filled when the QH is added */ 1627 sqh->qh.qh_endp = htole32( 1628 EHCI_QH_SET_ADDR(addr) | 1629 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1630 EHCI_QH_SET_EPS(speed) | 1631 EHCI_QH_DTC | 1632 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1633 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1634 EHCI_QH_CTL : 0) | 1635 EHCI_QH_SET_NRL(naks) 1636 ); 1637 sqh->qh.qh_endphub = htole32( 1638 EHCI_QH_SET_MULT(1) | 1639 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1640 ); 1641 if (speed != EHCI_QH_SPEED_HIGH) 1642 sqh->qh.qh_endphub |= htole32( 1643 EHCI_QH_SET_PORT(hshubport) | 1644 EHCI_QH_SET_HUBA(hshubaddr) | 1645 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1646 ); 1647 sqh->qh.qh_curqtd = EHCI_NULL; 1648 /* Fill the overlay qTD */ 1649 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1650 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1651 sqh->qh.qh_qtd.qtd_status = htole32(0); 1652 1653 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1654 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1655 epipe->sqh = sqh; 1656 } else { 1657 sqh = NULL; 1658 } /*xfertype == UE_ISOC*/ 1659 1660 switch (xfertype) { 1661 case UE_CONTROL: 1662 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1663 0, &epipe->u.ctl.reqdma); 1664 #ifdef EHCI_DEBUG 1665 if (err) 1666 printf("ehci_open: usb_allocmem()=%d\n", err); 1667 #endif 1668 if (err) 1669 goto bad; 1670 pipe->methods = &ehci_device_ctrl_methods; 1671 s = splusb(); 1672 ehci_add_qh(sqh, sc->sc_async_head); 1673 splx(s); 1674 break; 1675 case UE_BULK: 1676 pipe->methods = &ehci_device_bulk_methods; 1677 s = splusb(); 1678 ehci_add_qh(sqh, sc->sc_async_head); 1679 splx(s); 1680 break; 1681 case UE_INTERRUPT: 1682 pipe->methods = &ehci_device_intr_methods; 1683 ival = pipe->interval; 1684 if (ival == USBD_DEFAULT_INTERVAL) { 1685 if (speed == EHCI_QH_SPEED_HIGH) { 1686 if (ed->bInterval > 16) { 1687 /* 1688 * illegal with high-speed, but there 1689 * were documentation bugs in the spec, 1690 * so be generous 1691 */ 1692 ival = 256; 1693 } else 1694 ival = (1 << (ed->bInterval - 1)) / 8; 1695 } else 1696 ival = ed->bInterval; 1697 } 1698 err = ehci_device_setintr(sc, sqh, ival); 1699 if (err) 1700 goto bad; 1701 break; 1702 case UE_ISOCHRONOUS: 1703 pipe->methods = &ehci_device_isoc_methods; 1704 if (ed->bInterval == 0 || ed->bInterval > 16) { 1705 printf("ehci: opening pipe with invalid bInterval\n"); 1706 err = USBD_INVAL; 1707 goto bad; 1708 } 1709 if (UGETW(ed->wMaxPacketSize) == 0) { 1710 printf("ehci: zero length endpoint open request\n"); 1711 err = USBD_INVAL; 1712 goto bad; 1713 } 1714 epipe->u.isoc.next_frame = 0; 1715 epipe->u.isoc.cur_xfers = 0; 1716 break; 1717 default: 1718 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1719 err = USBD_INVAL; 1720 goto bad; 1721 } 1722 return (USBD_NORMAL_COMPLETION); 1723 1724 bad: 1725 if (sqh != NULL) 1726 ehci_free_sqh(sc, sqh); 1727 return (err); 1728 } 1729 1730 /* 1731 * Add an ED to the schedule. Called at splusb(). 1732 */ 1733 void 1734 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1735 { 1736 SPLUSBCHECK; 1737 1738 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1739 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1740 sqh->next = head->next; 1741 sqh->qh.qh_link = head->qh.qh_link; 1742 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1743 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1744 head->next = sqh; 1745 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1746 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1747 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1748 1749 #ifdef EHCI_DEBUG 1750 if (ehcidebug > 5) { 1751 printf("ehci_add_qh:\n"); 1752 ehci_dump_sqh(sqh); 1753 } 1754 #endif 1755 } 1756 1757 /* 1758 * Remove an ED from the schedule. Called at splusb(). 1759 */ 1760 void 1761 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1762 { 1763 ehci_soft_qh_t *p; 1764 1765 SPLUSBCHECK; 1766 /* XXX */ 1767 for (p = head; p != NULL && p->next != sqh; p = p->next) 1768 ; 1769 if (p == NULL) 1770 panic("ehci_rem_qh: ED not found"); 1771 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1772 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1773 p->next = sqh->next; 1774 p->qh.qh_link = sqh->qh.qh_link; 1775 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1776 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1777 1778 ehci_sync_hc(sc); 1779 } 1780 1781 void 1782 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1783 { 1784 int i; 1785 u_int32_t status; 1786 1787 /* Save toggle bit and ping status. */ 1788 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1789 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1790 status = sqh->qh.qh_qtd.qtd_status & 1791 htole32(EHCI_QTD_TOGGLE_MASK | 1792 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1793 /* Set HALTED to make hw leave it alone. */ 1794 sqh->qh.qh_qtd.qtd_status = 1795 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1796 usb_syncmem(&sqh->dma, 1797 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1798 sizeof(sqh->qh.qh_qtd.qtd_status), 1799 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1800 sqh->qh.qh_curqtd = 0; 1801 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1802 sqh->qh.qh_qtd.qtd_altnext = 0; 1803 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1804 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1805 sqh->sqtd = sqtd; 1806 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1807 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1808 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1809 sqh->qh.qh_qtd.qtd_status = status; 1810 usb_syncmem(&sqh->dma, 1811 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1812 sizeof(sqh->qh.qh_qtd.qtd_status), 1813 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1814 } 1815 1816 /* 1817 * Ensure that the HC has released all references to the QH. We do this 1818 * by asking for a Async Advance Doorbell interrupt and then we wait for 1819 * the interrupt. 1820 * To make this easier we first obtain exclusive use of the doorbell. 1821 */ 1822 void 1823 ehci_sync_hc(ehci_softc_t *sc) 1824 { 1825 int s, error; 1826 1827 if (sc->sc_dying) { 1828 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1829 return; 1830 } 1831 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1832 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */ 1833 s = splhardusb(); 1834 /* ask for doorbell */ 1835 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1836 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1837 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1838 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1839 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1840 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1841 splx(s); 1842 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */ 1843 #ifdef DIAGNOSTIC 1844 if (error) 1845 printf("ehci_sync_hc: tsleep() = %d\n", error); 1846 #endif 1847 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1848 } 1849 1850 /*Call at splusb*/ 1851 void 1852 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1853 { 1854 struct ehci_soft_itd *itd, *prev; 1855 1856 prev = NULL; 1857 1858 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1859 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1860 1861 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1862 prev = itd->u.frame_list.prev; 1863 /* Unlink itd from hardware chain, or frame array */ 1864 if (prev == NULL) { /* We're at the table head */ 1865 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1866 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1867 usb_syncmem(&sc->sc_fldma, 1868 sizeof(ehci_link_t) * itd->slot, 1869 sizeof(ehci_link_t), 1870 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1871 1872 if (itd->u.frame_list.next != NULL) 1873 itd->u.frame_list.next->u.frame_list.prev = NULL; 1874 } else { 1875 /* XXX this part is untested... */ 1876 prev->itd.itd_next = itd->itd.itd_next; 1877 usb_syncmem(&itd->dma, 1878 itd->offs + offsetof(ehci_itd_t, itd_next), 1879 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1880 1881 prev->u.frame_list.next = itd->u.frame_list.next; 1882 if (itd->u.frame_list.next != NULL) 1883 itd->u.frame_list.next->u.frame_list.prev = prev; 1884 } 1885 } 1886 1887 prev = NULL; 1888 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1889 if (prev != NULL) 1890 ehci_free_itd(sc, prev); 1891 prev = itd; 1892 } 1893 if (prev) 1894 ehci_free_itd(sc, prev); 1895 exfer->itdstart = NULL; 1896 exfer->itdend = NULL; 1897 } 1898 1899 /***********/ 1900 1901 /* 1902 * Data structures and routines to emulate the root hub. 1903 */ 1904 Static usb_device_descriptor_t ehci_devd = { 1905 USB_DEVICE_DESCRIPTOR_SIZE, 1906 UDESC_DEVICE, /* type */ 1907 {0x00, 0x02}, /* USB version */ 1908 UDCLASS_HUB, /* class */ 1909 UDSUBCLASS_HUB, /* subclass */ 1910 UDPROTO_HSHUBSTT, /* protocol */ 1911 64, /* max packet */ 1912 {0},{0},{0x00,0x01}, /* device id */ 1913 1,2,0, /* string indicies */ 1914 1 /* # of configurations */ 1915 }; 1916 1917 Static const usb_device_qualifier_t ehci_odevd = { 1918 USB_DEVICE_DESCRIPTOR_SIZE, 1919 UDESC_DEVICE_QUALIFIER, /* type */ 1920 {0x00, 0x02}, /* USB version */ 1921 UDCLASS_HUB, /* class */ 1922 UDSUBCLASS_HUB, /* subclass */ 1923 UDPROTO_FSHUB, /* protocol */ 1924 64, /* max packet */ 1925 1, /* # of configurations */ 1926 0 1927 }; 1928 1929 Static const usb_config_descriptor_t ehci_confd = { 1930 USB_CONFIG_DESCRIPTOR_SIZE, 1931 UDESC_CONFIG, 1932 {USB_CONFIG_DESCRIPTOR_SIZE + 1933 USB_INTERFACE_DESCRIPTOR_SIZE + 1934 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1935 1, 1936 1, 1937 0, 1938 UC_ATTR_MBO | UC_SELF_POWERED, 1939 0 /* max power */ 1940 }; 1941 1942 Static const usb_interface_descriptor_t ehci_ifcd = { 1943 USB_INTERFACE_DESCRIPTOR_SIZE, 1944 UDESC_INTERFACE, 1945 0, 1946 0, 1947 1, 1948 UICLASS_HUB, 1949 UISUBCLASS_HUB, 1950 UIPROTO_HSHUBSTT, 1951 0 1952 }; 1953 1954 Static const usb_endpoint_descriptor_t ehci_endpd = { 1955 USB_ENDPOINT_DESCRIPTOR_SIZE, 1956 UDESC_ENDPOINT, 1957 UE_DIR_IN | EHCI_INTR_ENDPT, 1958 UE_INTERRUPT, 1959 {8, 0}, /* max packet */ 1960 12 1961 }; 1962 1963 Static const usb_hub_descriptor_t ehci_hubd = { 1964 USB_HUB_DESCRIPTOR_SIZE, 1965 UDESC_HUB, 1966 0, 1967 {0,0}, 1968 0, 1969 0, 1970 {""}, 1971 {""}, 1972 }; 1973 1974 /* 1975 * Simulate a hardware hub by handling all the necessary requests. 1976 */ 1977 Static usbd_status 1978 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1979 { 1980 usbd_status err; 1981 1982 /* Insert last in queue. */ 1983 err = usb_insert_transfer(xfer); 1984 if (err) 1985 return (err); 1986 1987 /* Pipe isn't running, start first */ 1988 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1989 } 1990 1991 Static usbd_status 1992 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1993 { 1994 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1995 usb_device_request_t *req; 1996 void *buf = NULL; 1997 int port, i; 1998 int s, len, value, index, l, totlen = 0; 1999 usb_port_status_t ps; 2000 usb_hub_descriptor_t hubd; 2001 usbd_status err; 2002 u_int32_t v; 2003 2004 if (sc->sc_dying) 2005 return (USBD_IOERROR); 2006 2007 #ifdef DIAGNOSTIC 2008 if (!(xfer->rqflags & URQ_REQUEST)) 2009 /* XXX panic */ 2010 return (USBD_INVAL); 2011 #endif 2012 req = &xfer->request; 2013 2014 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2015 req->bmRequestType, req->bRequest)); 2016 2017 len = UGETW(req->wLength); 2018 value = UGETW(req->wValue); 2019 index = UGETW(req->wIndex); 2020 2021 if (len != 0) 2022 buf = KERNADDR(&xfer->dmabuf, 0); 2023 2024 #define C(x,y) ((x) | ((y) << 8)) 2025 switch(C(req->bRequest, req->bmRequestType)) { 2026 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2027 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2028 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2029 /* 2030 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2031 * for the integrated root hub. 2032 */ 2033 break; 2034 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2035 if (len > 0) { 2036 *(u_int8_t *)buf = sc->sc_conf; 2037 totlen = 1; 2038 } 2039 break; 2040 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2041 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2042 if (len == 0) 2043 break; 2044 switch(value >> 8) { 2045 case UDESC_DEVICE: 2046 if ((value & 0xff) != 0) { 2047 err = USBD_IOERROR; 2048 goto ret; 2049 } 2050 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2051 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2052 memcpy(buf, &ehci_devd, l); 2053 break; 2054 /* 2055 * We can't really operate at another speed, but the spec says 2056 * we need this descriptor. 2057 */ 2058 case UDESC_DEVICE_QUALIFIER: 2059 if ((value & 0xff) != 0) { 2060 err = USBD_IOERROR; 2061 goto ret; 2062 } 2063 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2064 memcpy(buf, &ehci_odevd, l); 2065 break; 2066 /* 2067 * We can't really operate at another speed, but the spec says 2068 * we need this descriptor. 2069 */ 2070 case UDESC_OTHER_SPEED_CONFIGURATION: 2071 case UDESC_CONFIG: 2072 if ((value & 0xff) != 0) { 2073 err = USBD_IOERROR; 2074 goto ret; 2075 } 2076 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2077 memcpy(buf, &ehci_confd, l); 2078 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2079 value >> 8; 2080 buf = (char *)buf + l; 2081 len -= l; 2082 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2083 totlen += l; 2084 memcpy(buf, &ehci_ifcd, l); 2085 buf = (char *)buf + l; 2086 len -= l; 2087 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2088 totlen += l; 2089 memcpy(buf, &ehci_endpd, l); 2090 break; 2091 case UDESC_STRING: 2092 #define sd ((usb_string_descriptor_t *)buf) 2093 switch (value & 0xff) { 2094 case 0: /* Language table */ 2095 totlen = usb_makelangtbl(sd, len); 2096 break; 2097 case 1: /* Vendor */ 2098 totlen = usb_makestrdesc(sd, len, 2099 sc->sc_vendor); 2100 break; 2101 case 2: /* Product */ 2102 totlen = usb_makestrdesc(sd, len, 2103 "EHCI root hub"); 2104 break; 2105 } 2106 #undef sd 2107 break; 2108 default: 2109 err = USBD_IOERROR; 2110 goto ret; 2111 } 2112 break; 2113 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2114 if (len > 0) { 2115 *(u_int8_t *)buf = 0; 2116 totlen = 1; 2117 } 2118 break; 2119 case C(UR_GET_STATUS, UT_READ_DEVICE): 2120 if (len > 1) { 2121 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2122 totlen = 2; 2123 } 2124 break; 2125 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2126 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2127 if (len > 1) { 2128 USETW(((usb_status_t *)buf)->wStatus, 0); 2129 totlen = 2; 2130 } 2131 break; 2132 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2133 if (value >= USB_MAX_DEVICES) { 2134 err = USBD_IOERROR; 2135 goto ret; 2136 } 2137 sc->sc_addr = value; 2138 break; 2139 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2140 if (value != 0 && value != 1) { 2141 err = USBD_IOERROR; 2142 goto ret; 2143 } 2144 sc->sc_conf = value; 2145 break; 2146 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2147 break; 2148 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2149 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2150 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2151 err = USBD_IOERROR; 2152 goto ret; 2153 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2154 break; 2155 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2156 break; 2157 /* Hub requests */ 2158 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2159 break; 2160 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2161 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2162 "port=%d feature=%d\n", 2163 index, value)); 2164 if (index < 1 || index > sc->sc_noport) { 2165 err = USBD_IOERROR; 2166 goto ret; 2167 } 2168 port = EHCI_PORTSC(index); 2169 v = EOREAD4(sc, port); 2170 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2171 v &= ~EHCI_PS_CLEAR; 2172 switch(value) { 2173 case UHF_PORT_ENABLE: 2174 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2175 break; 2176 case UHF_PORT_SUSPEND: 2177 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2178 break; 2179 v &= ~EHCI_PS_SUSP; 2180 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2181 /* see USB2 spec ch. 7.1.7.7 */ 2182 usb_delay_ms(&sc->sc_bus, 20); 2183 EOWRITE4(sc, port, v); 2184 usb_delay_ms(&sc->sc_bus, 2); 2185 #ifdef DEBUG 2186 v = EOREAD4(sc, port); 2187 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2188 printf("ehci: resume failed: %x\n", v); 2189 #endif 2190 break; 2191 case UHF_PORT_POWER: 2192 if (sc->sc_hasppc) 2193 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2194 break; 2195 case UHF_PORT_TEST: 2196 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2197 "%d\n", index)); 2198 break; 2199 case UHF_PORT_INDICATOR: 2200 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2201 "%d\n", index)); 2202 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2203 break; 2204 case UHF_C_PORT_CONNECTION: 2205 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2206 break; 2207 case UHF_C_PORT_ENABLE: 2208 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2209 break; 2210 case UHF_C_PORT_SUSPEND: 2211 /* how? */ 2212 break; 2213 case UHF_C_PORT_OVER_CURRENT: 2214 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2215 break; 2216 case UHF_C_PORT_RESET: 2217 sc->sc_isreset[index] = 0; 2218 break; 2219 default: 2220 err = USBD_IOERROR; 2221 goto ret; 2222 } 2223 #if 0 2224 switch(value) { 2225 case UHF_C_PORT_CONNECTION: 2226 case UHF_C_PORT_ENABLE: 2227 case UHF_C_PORT_SUSPEND: 2228 case UHF_C_PORT_OVER_CURRENT: 2229 case UHF_C_PORT_RESET: 2230 default: 2231 break; 2232 } 2233 #endif 2234 break; 2235 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2236 if (len == 0) 2237 break; 2238 if ((value & 0xff) != 0) { 2239 err = USBD_IOERROR; 2240 goto ret; 2241 } 2242 hubd = ehci_hubd; 2243 hubd.bNbrPorts = sc->sc_noport; 2244 v = EOREAD4(sc, EHCI_HCSPARAMS); 2245 USETW(hubd.wHubCharacteristics, 2246 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2247 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2248 ? UHD_PORT_IND : 0); 2249 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2250 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2251 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2252 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2253 l = min(len, hubd.bDescLength); 2254 totlen = l; 2255 memcpy(buf, &hubd, l); 2256 break; 2257 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2258 if (len != 4) { 2259 err = USBD_IOERROR; 2260 goto ret; 2261 } 2262 memset(buf, 0, len); /* ? XXX */ 2263 totlen = len; 2264 break; 2265 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2266 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2267 index)); 2268 if (index < 1 || index > sc->sc_noport) { 2269 err = USBD_IOERROR; 2270 goto ret; 2271 } 2272 if (len != 4) { 2273 err = USBD_IOERROR; 2274 goto ret; 2275 } 2276 v = EOREAD4(sc, EHCI_PORTSC(index)); 2277 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2278 v)); 2279 2280 if (sc->sc_flags & EHCIF_ETTF) { 2281 /* 2282 * If we are doing embedded transaction translation, 2283 * then directly attached LS/FS devices are reset by 2284 * the EHCI controller itself. PSPD is encoded 2285 * the same way as in USBSTATUS. 2286 */ 2287 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2288 } else { 2289 i = UPS_HIGH_SPEED; 2290 } 2291 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2292 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2293 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2294 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2295 if (v & EHCI_PS_PR) i |= UPS_RESET; 2296 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2297 USETW(ps.wPortStatus, i); 2298 i = 0; 2299 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2300 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2301 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2302 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2303 USETW(ps.wPortChange, i); 2304 l = min(len, sizeof ps); 2305 memcpy(buf, &ps, l); 2306 totlen = l; 2307 break; 2308 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2309 err = USBD_IOERROR; 2310 goto ret; 2311 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2312 break; 2313 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2314 if (index < 1 || index > sc->sc_noport) { 2315 err = USBD_IOERROR; 2316 goto ret; 2317 } 2318 port = EHCI_PORTSC(index); 2319 v = EOREAD4(sc, port); 2320 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2321 v &= ~EHCI_PS_CLEAR; 2322 switch(value) { 2323 case UHF_PORT_ENABLE: 2324 EOWRITE4(sc, port, v | EHCI_PS_PE); 2325 break; 2326 case UHF_PORT_SUSPEND: 2327 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2328 break; 2329 case UHF_PORT_RESET: 2330 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2331 index)); 2332 if (EHCI_PS_IS_LOWSPEED(v) 2333 && !(sc->sc_flags & EHCIF_ETTF)) { 2334 /* 2335 * Low speed device on non-ETTF controller, 2336 * give up ownership. 2337 */ 2338 ehci_disown(sc, index, 1); 2339 break; 2340 } 2341 /* Start reset sequence. */ 2342 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2343 EOWRITE4(sc, port, v | EHCI_PS_PR); 2344 /* Wait for reset to complete. */ 2345 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2346 if (sc->sc_dying) { 2347 err = USBD_IOERROR; 2348 goto ret; 2349 } 2350 /* 2351 * An embedded transaction translater will automatically 2352 * terminate the reset sequence so there's no need to 2353 * it. 2354 */ 2355 if (!(sc->sc_flags & EHCIF_ETTF)) { 2356 /* Terminate reset sequence. */ 2357 EOWRITE4(sc, port, v); 2358 /* Wait for HC to complete reset. */ 2359 usb_delay_ms(&sc->sc_bus, 2360 EHCI_PORT_RESET_COMPLETE); 2361 if (sc->sc_dying) { 2362 err = USBD_IOERROR; 2363 goto ret; 2364 } 2365 } 2366 2367 v = EOREAD4(sc, port); 2368 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2369 if (v & EHCI_PS_PR) { 2370 printf("%s: port reset timeout\n", 2371 device_xname(sc->sc_dev)); 2372 return (USBD_TIMEOUT); 2373 } 2374 if (!(v & EHCI_PS_PE)) { 2375 /* Not a high speed device, give up ownership.*/ 2376 ehci_disown(sc, index, 0); 2377 break; 2378 } 2379 sc->sc_isreset[index] = 1; 2380 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2381 index, v)); 2382 break; 2383 case UHF_PORT_POWER: 2384 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2385 "%d (has PPC = %d)\n", index, 2386 sc->sc_hasppc)); 2387 if (sc->sc_hasppc) 2388 EOWRITE4(sc, port, v | EHCI_PS_PP); 2389 break; 2390 case UHF_PORT_TEST: 2391 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2392 "%d\n", index)); 2393 break; 2394 case UHF_PORT_INDICATOR: 2395 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2396 "%d\n", index)); 2397 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2398 break; 2399 default: 2400 err = USBD_IOERROR; 2401 goto ret; 2402 } 2403 break; 2404 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2405 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2406 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2407 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2408 break; 2409 default: 2410 err = USBD_IOERROR; 2411 goto ret; 2412 } 2413 xfer->actlen = totlen; 2414 err = USBD_NORMAL_COMPLETION; 2415 ret: 2416 xfer->status = err; 2417 s = splusb(); 2418 usb_transfer_complete(xfer); 2419 splx(s); 2420 return (USBD_IN_PROGRESS); 2421 } 2422 2423 void 2424 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2425 { 2426 int port; 2427 u_int32_t v; 2428 2429 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2430 #ifdef DIAGNOSTIC 2431 if (sc->sc_npcomp != 0) { 2432 int i = (index-1) / sc->sc_npcomp; 2433 if (i >= sc->sc_ncomp) 2434 printf("%s: strange port\n", 2435 device_xname(sc->sc_dev)); 2436 else 2437 printf("%s: handing over %s speed device on " 2438 "port %d to %s\n", 2439 device_xname(sc->sc_dev), 2440 lowspeed ? "low" : "full", 2441 index, device_xname(sc->sc_comps[i])); 2442 } else { 2443 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2444 } 2445 #endif 2446 port = EHCI_PORTSC(index); 2447 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2448 EOWRITE4(sc, port, v | EHCI_PS_PO); 2449 } 2450 2451 /* Abort a root control request. */ 2452 Static void 2453 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2454 { 2455 /* Nothing to do, all transfers are synchronous. */ 2456 } 2457 2458 /* Close the root pipe. */ 2459 Static void 2460 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2461 { 2462 DPRINTF(("ehci_root_ctrl_close\n")); 2463 /* Nothing to do. */ 2464 } 2465 2466 void 2467 ehci_root_intr_done(usbd_xfer_handle xfer) 2468 { 2469 xfer->hcpriv = NULL; 2470 } 2471 2472 Static usbd_status 2473 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2474 { 2475 usbd_status err; 2476 2477 /* Insert last in queue. */ 2478 err = usb_insert_transfer(xfer); 2479 if (err) 2480 return (err); 2481 2482 /* Pipe isn't running, start first */ 2483 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2484 } 2485 2486 Static usbd_status 2487 ehci_root_intr_start(usbd_xfer_handle xfer) 2488 { 2489 usbd_pipe_handle pipe = xfer->pipe; 2490 ehci_softc_t *sc = pipe->device->bus->hci_private; 2491 2492 if (sc->sc_dying) 2493 return (USBD_IOERROR); 2494 2495 sc->sc_intrxfer = xfer; 2496 2497 return (USBD_IN_PROGRESS); 2498 } 2499 2500 /* Abort a root interrupt request. */ 2501 Static void 2502 ehci_root_intr_abort(usbd_xfer_handle xfer) 2503 { 2504 int s; 2505 2506 if (xfer->pipe->intrxfer == xfer) { 2507 DPRINTF(("ehci_root_intr_abort: remove\n")); 2508 xfer->pipe->intrxfer = NULL; 2509 } 2510 xfer->status = USBD_CANCELLED; 2511 s = splusb(); 2512 usb_transfer_complete(xfer); 2513 splx(s); 2514 } 2515 2516 /* Close the root pipe. */ 2517 Static void 2518 ehci_root_intr_close(usbd_pipe_handle pipe) 2519 { 2520 ehci_softc_t *sc = pipe->device->bus->hci_private; 2521 2522 DPRINTF(("ehci_root_intr_close\n")); 2523 2524 sc->sc_intrxfer = NULL; 2525 } 2526 2527 void 2528 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2529 { 2530 xfer->hcpriv = NULL; 2531 } 2532 2533 /************************/ 2534 2535 ehci_soft_qh_t * 2536 ehci_alloc_sqh(ehci_softc_t *sc) 2537 { 2538 ehci_soft_qh_t *sqh; 2539 usbd_status err; 2540 int i, offs; 2541 usb_dma_t dma; 2542 2543 if (sc->sc_freeqhs == NULL) { 2544 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2545 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2546 EHCI_PAGE_SIZE, &dma); 2547 #ifdef EHCI_DEBUG 2548 if (err) 2549 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2550 #endif 2551 if (err) 2552 return (NULL); 2553 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2554 offs = i * EHCI_SQH_SIZE; 2555 sqh = KERNADDR(&dma, offs); 2556 sqh->physaddr = DMAADDR(&dma, offs); 2557 sqh->dma = dma; 2558 sqh->offs = offs; 2559 sqh->next = sc->sc_freeqhs; 2560 sc->sc_freeqhs = sqh; 2561 } 2562 } 2563 sqh = sc->sc_freeqhs; 2564 sc->sc_freeqhs = sqh->next; 2565 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2566 sqh->next = NULL; 2567 return (sqh); 2568 } 2569 2570 void 2571 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2572 { 2573 sqh->next = sc->sc_freeqhs; 2574 sc->sc_freeqhs = sqh; 2575 } 2576 2577 ehci_soft_qtd_t * 2578 ehci_alloc_sqtd(ehci_softc_t *sc) 2579 { 2580 ehci_soft_qtd_t *sqtd; 2581 usbd_status err; 2582 int i, offs; 2583 usb_dma_t dma; 2584 int s; 2585 2586 if (sc->sc_freeqtds == NULL) { 2587 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2588 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2589 EHCI_PAGE_SIZE, &dma); 2590 #ifdef EHCI_DEBUG 2591 if (err) 2592 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2593 #endif 2594 if (err) 2595 return (NULL); 2596 s = splusb(); 2597 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2598 offs = i * EHCI_SQTD_SIZE; 2599 sqtd = KERNADDR(&dma, offs); 2600 sqtd->physaddr = DMAADDR(&dma, offs); 2601 sqtd->dma = dma; 2602 sqtd->offs = offs; 2603 sqtd->nextqtd = sc->sc_freeqtds; 2604 sc->sc_freeqtds = sqtd; 2605 } 2606 splx(s); 2607 } 2608 2609 s = splusb(); 2610 sqtd = sc->sc_freeqtds; 2611 sc->sc_freeqtds = sqtd->nextqtd; 2612 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2613 sqtd->nextqtd = NULL; 2614 sqtd->xfer = NULL; 2615 splx(s); 2616 2617 return (sqtd); 2618 } 2619 2620 void 2621 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2622 { 2623 int s; 2624 2625 s = splusb(); 2626 sqtd->nextqtd = sc->sc_freeqtds; 2627 sc->sc_freeqtds = sqtd; 2628 splx(s); 2629 } 2630 2631 usbd_status 2632 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2633 int alen, int rd, usbd_xfer_handle xfer, 2634 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2635 { 2636 ehci_soft_qtd_t *next, *cur; 2637 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2638 u_int32_t qtdstatus; 2639 int len, curlen, mps; 2640 int i, tog; 2641 usb_dma_t *dma = &xfer->dmabuf; 2642 u_int16_t flags = xfer->flags; 2643 2644 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2645 2646 len = alen; 2647 dataphys = DMAADDR(dma, 0); 2648 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2649 qtdstatus = EHCI_QTD_ACTIVE | 2650 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2651 EHCI_QTD_SET_CERR(3) 2652 /* IOC set below */ 2653 /* BYTES set below */ 2654 ; 2655 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2656 tog = epipe->nexttoggle; 2657 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2658 2659 cur = ehci_alloc_sqtd(sc); 2660 *sp = cur; 2661 if (cur == NULL) 2662 goto nomem; 2663 2664 usb_syncmem(dma, 0, alen, 2665 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2666 for (;;) { 2667 dataphyspage = EHCI_PAGE(dataphys); 2668 /* The EHCI hardware can handle at most 5 pages. */ 2669 if (dataphyslastpage - dataphyspage < 2670 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2671 /* we can handle it in this QTD */ 2672 curlen = len; 2673 } else { 2674 /* must use multiple TDs, fill as much as possible. */ 2675 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2676 EHCI_PAGE_OFFSET(dataphys); 2677 #ifdef DIAGNOSTIC 2678 if (curlen > len) { 2679 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2680 "len=0x%x offs=0x%x\n", curlen, len, 2681 EHCI_PAGE_OFFSET(dataphys)); 2682 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2683 dataphyslastpage, dataphyspage, 2684 dataphys); 2685 curlen = len; 2686 } 2687 #endif 2688 /* the length must be a multiple of the max size */ 2689 curlen -= curlen % mps; 2690 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2691 "curlen=%d\n", curlen)); 2692 #ifdef DIAGNOSTIC 2693 if (curlen == 0) 2694 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2695 #endif 2696 } 2697 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2698 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2699 dataphys, dataphyslastpage, 2700 len, curlen)); 2701 len -= curlen; 2702 2703 /* 2704 * Allocate another transfer if there's more data left, 2705 * or if force last short transfer flag is set and we're 2706 * allocating a multiple of the max packet size. 2707 */ 2708 if (len != 0 || 2709 ((curlen % mps) == 0 && !rd && curlen != 0 && 2710 (flags & USBD_FORCE_SHORT_XFER))) { 2711 next = ehci_alloc_sqtd(sc); 2712 if (next == NULL) 2713 goto nomem; 2714 nextphys = htole32(next->physaddr); 2715 } else { 2716 next = NULL; 2717 nextphys = EHCI_NULL; 2718 } 2719 2720 for (i = 0; i * EHCI_PAGE_SIZE < 2721 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2722 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2723 if (i != 0) /* use offset only in first buffer */ 2724 a = EHCI_PAGE(a); 2725 cur->qtd.qtd_buffer[i] = htole32(a); 2726 cur->qtd.qtd_buffer_hi[i] = 0; 2727 #ifdef DIAGNOSTIC 2728 if (i >= EHCI_QTD_NBUFFERS) { 2729 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2730 goto nomem; 2731 } 2732 #endif 2733 } 2734 cur->nextqtd = next; 2735 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2736 cur->qtd.qtd_status = 2737 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2738 cur->xfer = xfer; 2739 cur->len = curlen; 2740 2741 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2742 dataphys, dataphys + curlen)); 2743 /* adjust the toggle based on the number of packets in this 2744 qtd */ 2745 if (((curlen + mps - 1) / mps) & 1) { 2746 tog ^= 1; 2747 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2748 } 2749 if (next == NULL) 2750 break; 2751 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2752 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2753 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2754 dataphys += curlen; 2755 cur = next; 2756 } 2757 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2758 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2759 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2760 *ep = cur; 2761 epipe->nexttoggle = tog; 2762 2763 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2764 *sp, *ep)); 2765 2766 return (USBD_NORMAL_COMPLETION); 2767 2768 nomem: 2769 /* XXX free chain */ 2770 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2771 return (USBD_NOMEM); 2772 } 2773 2774 Static void 2775 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2776 ehci_soft_qtd_t *sqtdend) 2777 { 2778 ehci_soft_qtd_t *p; 2779 int i; 2780 2781 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2782 sqtd, sqtdend)); 2783 2784 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2785 p = sqtd->nextqtd; 2786 ehci_free_sqtd(sc, sqtd); 2787 } 2788 } 2789 2790 ehci_soft_itd_t * 2791 ehci_alloc_itd(ehci_softc_t *sc) 2792 { 2793 struct ehci_soft_itd *itd, *freeitd; 2794 usbd_status err; 2795 int i, s, offs, frindex, previndex; 2796 usb_dma_t dma; 2797 2798 s = splusb(); 2799 2800 /* Find an itd that wasn't freed this frame or last frame. This can 2801 * discard itds that were freed before frindex wrapped around 2802 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2803 * interrupt and fiddling with list when that happens */ 2804 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2805 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2806 2807 freeitd = NULL; 2808 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2809 if (itd == NULL) 2810 break; 2811 if (itd->slot != frindex && itd->slot != previndex) { 2812 freeitd = itd; 2813 break; 2814 } 2815 } 2816 2817 if (freeitd == NULL) { 2818 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2819 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2820 EHCI_PAGE_SIZE, &dma); 2821 2822 if (err) { 2823 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2824 return NULL; 2825 } 2826 2827 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2828 offs = i * EHCI_ITD_SIZE; 2829 itd = KERNADDR(&dma, offs); 2830 itd->physaddr = DMAADDR(&dma, offs); 2831 itd->dma = dma; 2832 itd->offs = offs; 2833 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2834 } 2835 freeitd = LIST_FIRST(&sc->sc_freeitds); 2836 } 2837 2838 itd = freeitd; 2839 LIST_REMOVE(itd, u.free_list); 2840 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2841 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2842 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2843 BUS_DMASYNC_PREREAD); 2844 2845 itd->u.frame_list.next = NULL; 2846 itd->u.frame_list.prev = NULL; 2847 itd->xfer_next = NULL; 2848 itd->slot = 0; 2849 splx(s); 2850 2851 return itd; 2852 } 2853 2854 void 2855 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2856 { 2857 int s; 2858 2859 s = splusb(); 2860 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2861 splx(s); 2862 } 2863 2864 2865 2866 /****************/ 2867 2868 /* 2869 * Close a reqular pipe. 2870 * Assumes that there are no pending transactions. 2871 */ 2872 void 2873 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2874 { 2875 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2876 ehci_softc_t *sc = pipe->device->bus->hci_private; 2877 ehci_soft_qh_t *sqh = epipe->sqh; 2878 int s; 2879 2880 s = splusb(); 2881 ehci_rem_qh(sc, sqh, head); 2882 splx(s); 2883 ehci_free_sqh(sc, epipe->sqh); 2884 } 2885 2886 /* 2887 * Abort a device request. 2888 * If this routine is called at splusb() it guarantees that the request 2889 * will be removed from the hardware scheduling and that the callback 2890 * for it will be called with USBD_CANCELLED status. 2891 * It's impossible to guarantee that the requested transfer will not 2892 * have happened since the hardware runs concurrently. 2893 * If the transaction has already happened we rely on the ordinary 2894 * interrupt processing to process it. 2895 * XXX This is most probably wrong. 2896 */ 2897 void 2898 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2899 { 2900 #define exfer EXFER(xfer) 2901 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2902 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2903 ehci_soft_qh_t *sqh = epipe->sqh; 2904 ehci_soft_qtd_t *sqtd; 2905 ehci_physaddr_t cur; 2906 u_int32_t qhstatus; 2907 int s; 2908 int hit; 2909 int wake; 2910 2911 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2912 2913 if (sc->sc_dying) { 2914 /* If we're dying, just do the software part. */ 2915 s = splusb(); 2916 xfer->status = status; /* make software ignore it */ 2917 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2918 usb_transfer_complete(xfer); 2919 splx(s); 2920 return; 2921 } 2922 2923 if (xfer->device->bus->intr_context) 2924 panic("ehci_abort_xfer: not in process context"); 2925 2926 /* 2927 * If an abort is already in progress then just wait for it to 2928 * complete and return. 2929 */ 2930 if (xfer->hcflags & UXFER_ABORTING) { 2931 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2932 #ifdef DIAGNOSTIC 2933 if (status == USBD_TIMEOUT) 2934 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2935 #endif 2936 /* Override the status which might be USBD_TIMEOUT. */ 2937 xfer->status = status; 2938 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2939 xfer->hcflags |= UXFER_ABORTWAIT; 2940 while (xfer->hcflags & UXFER_ABORTING) 2941 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2942 return; 2943 } 2944 xfer->hcflags |= UXFER_ABORTING; 2945 2946 /* 2947 * Step 1: Make interrupt routine and hardware ignore xfer. 2948 */ 2949 s = splusb(); 2950 xfer->status = status; /* make software ignore it */ 2951 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2952 2953 usb_syncmem(&sqh->dma, 2954 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2955 sizeof(sqh->qh.qh_qtd.qtd_status), 2956 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2957 qhstatus = sqh->qh.qh_qtd.qtd_status; 2958 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2959 usb_syncmem(&sqh->dma, 2960 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2961 sizeof(sqh->qh.qh_qtd.qtd_status), 2962 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2963 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2964 usb_syncmem(&sqtd->dma, 2965 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2966 sizeof(sqtd->qtd.qtd_status), 2967 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2968 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2969 usb_syncmem(&sqtd->dma, 2970 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2971 sizeof(sqtd->qtd.qtd_status), 2972 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2973 if (sqtd == exfer->sqtdend) 2974 break; 2975 } 2976 splx(s); 2977 2978 /* 2979 * Step 2: Wait until we know hardware has finished any possible 2980 * use of the xfer. Also make sure the soft interrupt routine 2981 * has run. 2982 */ 2983 ehci_sync_hc(sc); 2984 s = splusb(); 2985 #ifdef USB_USE_SOFTINTR 2986 sc->sc_softwake = 1; 2987 #endif /* USB_USE_SOFTINTR */ 2988 usb_schedsoftintr(&sc->sc_bus); 2989 #ifdef USB_USE_SOFTINTR 2990 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2991 #endif /* USB_USE_SOFTINTR */ 2992 splx(s); 2993 2994 /* 2995 * Step 3: Remove any vestiges of the xfer from the hardware. 2996 * The complication here is that the hardware may have executed 2997 * beyond the xfer we're trying to abort. So as we're scanning 2998 * the TDs of this xfer we check if the hardware points to 2999 * any of them. 3000 */ 3001 s = splusb(); /* XXX why? */ 3002 3003 usb_syncmem(&sqh->dma, 3004 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3005 sizeof(sqh->qh.qh_curqtd), 3006 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3007 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3008 hit = 0; 3009 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3010 hit |= cur == sqtd->physaddr; 3011 if (sqtd == exfer->sqtdend) 3012 break; 3013 } 3014 sqtd = sqtd->nextqtd; 3015 /* Zap curqtd register if hardware pointed inside the xfer. */ 3016 if (hit && sqtd != NULL) { 3017 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3018 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3019 usb_syncmem(&sqh->dma, 3020 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3021 sizeof(sqh->qh.qh_curqtd), 3022 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3023 sqh->qh.qh_qtd.qtd_status = qhstatus; 3024 usb_syncmem(&sqh->dma, 3025 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3026 sizeof(sqh->qh.qh_qtd.qtd_status), 3027 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3028 } else { 3029 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3030 } 3031 3032 /* 3033 * Step 4: Execute callback. 3034 */ 3035 #ifdef DIAGNOSTIC 3036 exfer->isdone = 1; 3037 #endif 3038 wake = xfer->hcflags & UXFER_ABORTWAIT; 3039 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3040 usb_transfer_complete(xfer); 3041 if (wake) 3042 wakeup(&xfer->hcflags); 3043 3044 splx(s); 3045 #undef exfer 3046 } 3047 3048 void 3049 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3050 { 3051 ehci_isoc_trans_t trans_status; 3052 struct ehci_pipe *epipe; 3053 struct ehci_xfer *exfer; 3054 ehci_softc_t *sc; 3055 struct ehci_soft_itd *itd; 3056 int s, i, wake; 3057 3058 epipe = (struct ehci_pipe *) xfer->pipe; 3059 exfer = EXFER(xfer); 3060 sc = epipe->pipe.device->bus->hci_private; 3061 3062 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3063 3064 if (sc->sc_dying) { 3065 s = splusb(); 3066 xfer->status = status; 3067 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3068 usb_transfer_complete(xfer); 3069 splx(s); 3070 return; 3071 } 3072 3073 if (xfer->hcflags & UXFER_ABORTING) { 3074 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3075 3076 #ifdef DIAGNOSTIC 3077 if (status == USBD_TIMEOUT) 3078 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3079 #endif 3080 3081 xfer->status = status; 3082 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3083 xfer->hcflags |= UXFER_ABORTWAIT; 3084 while (xfer->hcflags & UXFER_ABORTING) 3085 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0); 3086 return; 3087 } 3088 xfer->hcflags |= UXFER_ABORTING; 3089 3090 xfer->status = status; 3091 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3092 3093 s = splusb(); 3094 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3095 usb_syncmem(&itd->dma, 3096 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3097 sizeof(itd->itd.itd_ctl), 3098 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3099 3100 for (i = 0; i < 8; i++) { 3101 trans_status = le32toh(itd->itd.itd_ctl[i]); 3102 trans_status &= ~EHCI_ITD_ACTIVE; 3103 itd->itd.itd_ctl[i] = htole32(trans_status); 3104 } 3105 3106 usb_syncmem(&itd->dma, 3107 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3108 sizeof(itd->itd.itd_ctl), 3109 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3110 } 3111 splx(s); 3112 3113 s = splusb(); 3114 #ifdef USB_USE_SOFTINTR 3115 sc->sc_softwake = 1; 3116 #endif /* USB_USE_SOFTINTR */ 3117 usb_schedsoftintr(&sc->sc_bus); 3118 #ifdef USB_USE_SOFTINTR 3119 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3120 #endif /* USB_USE_SOFTINTR */ 3121 splx(s); 3122 3123 #ifdef DIAGNOSTIC 3124 exfer->isdone = 1; 3125 #endif 3126 wake = xfer->hcflags & UXFER_ABORTWAIT; 3127 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3128 usb_transfer_complete(xfer); 3129 if (wake) 3130 wakeup(&xfer->hcflags); 3131 3132 return; 3133 } 3134 3135 void 3136 ehci_timeout(void *addr) 3137 { 3138 struct ehci_xfer *exfer = addr; 3139 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3140 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3141 3142 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3143 #ifdef USB_DEBUG 3144 if (ehcidebug > 1) 3145 usbd_dump_pipe(exfer->xfer.pipe); 3146 #endif 3147 3148 if (sc->sc_dying) { 3149 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3150 return; 3151 } 3152 3153 /* Execute the abort in a process context. */ 3154 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3155 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3156 USB_TASKQ_HC); 3157 } 3158 3159 void 3160 ehci_timeout_task(void *addr) 3161 { 3162 usbd_xfer_handle xfer = addr; 3163 int s; 3164 3165 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3166 3167 s = splusb(); 3168 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3169 splx(s); 3170 } 3171 3172 /************************/ 3173 3174 Static usbd_status 3175 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3176 { 3177 usbd_status err; 3178 3179 /* Insert last in queue. */ 3180 err = usb_insert_transfer(xfer); 3181 if (err) 3182 return (err); 3183 3184 /* Pipe isn't running, start first */ 3185 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3186 } 3187 3188 Static usbd_status 3189 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3190 { 3191 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3192 usbd_status err; 3193 3194 if (sc->sc_dying) 3195 return (USBD_IOERROR); 3196 3197 #ifdef DIAGNOSTIC 3198 if (!(xfer->rqflags & URQ_REQUEST)) { 3199 /* XXX panic */ 3200 printf("ehci_device_ctrl_transfer: not a request\n"); 3201 return (USBD_INVAL); 3202 } 3203 #endif 3204 3205 err = ehci_device_request(xfer); 3206 if (err) 3207 return (err); 3208 3209 if (sc->sc_bus.use_polling) 3210 ehci_waitintr(sc, xfer); 3211 return (USBD_IN_PROGRESS); 3212 } 3213 3214 void 3215 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3216 { 3217 struct ehci_xfer *ex = EXFER(xfer); 3218 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3219 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3220 usb_device_request_t *req = &xfer->request; 3221 int len = UGETW(req->wLength); 3222 int rd = req->bmRequestType & UT_READ; 3223 3224 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3225 3226 #ifdef DIAGNOSTIC 3227 if (!(xfer->rqflags & URQ_REQUEST)) { 3228 panic("ehci_ctrl_done: not a request"); 3229 } 3230 #endif 3231 3232 mutex_enter(&sc->sc_intrhead_lock); 3233 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3234 ehci_del_intr_list(sc, ex); /* remove from active list */ 3235 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3236 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3237 BUS_DMASYNC_POSTWRITE); 3238 if (len) 3239 usb_syncmem(&xfer->dmabuf, 0, len, 3240 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3241 } 3242 mutex_exit(&sc->sc_intrhead_lock); 3243 3244 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3245 } 3246 3247 /* Abort a device control request. */ 3248 Static void 3249 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3250 { 3251 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3252 ehci_abort_xfer(xfer, USBD_CANCELLED); 3253 } 3254 3255 /* Close a device control pipe. */ 3256 Static void 3257 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3258 { 3259 ehci_softc_t *sc = pipe->device->bus->hci_private; 3260 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3261 3262 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3263 ehci_close_pipe(pipe, sc->sc_async_head); 3264 } 3265 3266 usbd_status 3267 ehci_device_request(usbd_xfer_handle xfer) 3268 { 3269 #define exfer EXFER(xfer) 3270 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3271 usb_device_request_t *req = &xfer->request; 3272 usbd_device_handle dev = epipe->pipe.device; 3273 ehci_softc_t *sc = dev->bus->hci_private; 3274 int addr = dev->address; 3275 ehci_soft_qtd_t *setup, *stat, *next; 3276 ehci_soft_qh_t *sqh; 3277 int isread; 3278 int len; 3279 usbd_status err; 3280 int s; 3281 3282 isread = req->bmRequestType & UT_READ; 3283 len = UGETW(req->wLength); 3284 3285 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3286 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3287 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3288 UGETW(req->wIndex), len, addr, 3289 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3290 3291 setup = ehci_alloc_sqtd(sc); 3292 if (setup == NULL) { 3293 err = USBD_NOMEM; 3294 goto bad1; 3295 } 3296 stat = ehci_alloc_sqtd(sc); 3297 if (stat == NULL) { 3298 err = USBD_NOMEM; 3299 goto bad2; 3300 } 3301 3302 sqh = epipe->sqh; 3303 epipe->u.ctl.length = len; 3304 3305 /* Update device address and length since they may have changed 3306 during the setup of the control pipe in usbd_new_device(). */ 3307 /* XXX This only needs to be done once, but it's too early in open. */ 3308 /* XXXX Should not touch ED here! */ 3309 sqh->qh.qh_endp = 3310 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3311 htole32( 3312 EHCI_QH_SET_ADDR(addr) | 3313 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3314 ); 3315 3316 /* Set up data transaction */ 3317 if (len != 0) { 3318 ehci_soft_qtd_t *end; 3319 3320 /* Start toggle at 1. */ 3321 epipe->nexttoggle = 1; 3322 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3323 &next, &end); 3324 if (err) 3325 goto bad3; 3326 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3327 end->nextqtd = stat; 3328 end->qtd.qtd_next = 3329 end->qtd.qtd_altnext = htole32(stat->physaddr); 3330 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3331 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3332 } else { 3333 next = stat; 3334 } 3335 3336 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3337 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3338 3339 /* Clear toggle */ 3340 setup->qtd.qtd_status = htole32( 3341 EHCI_QTD_ACTIVE | 3342 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3343 EHCI_QTD_SET_CERR(3) | 3344 EHCI_QTD_SET_TOGGLE(0) | 3345 EHCI_QTD_SET_BYTES(sizeof *req) 3346 ); 3347 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3348 setup->qtd.qtd_buffer_hi[0] = 0; 3349 setup->nextqtd = next; 3350 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3351 setup->xfer = xfer; 3352 setup->len = sizeof *req; 3353 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3354 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3355 3356 stat->qtd.qtd_status = htole32( 3357 EHCI_QTD_ACTIVE | 3358 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3359 EHCI_QTD_SET_CERR(3) | 3360 EHCI_QTD_SET_TOGGLE(1) | 3361 EHCI_QTD_IOC 3362 ); 3363 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3364 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3365 stat->nextqtd = NULL; 3366 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3367 stat->xfer = xfer; 3368 stat->len = 0; 3369 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3370 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3371 3372 #ifdef EHCI_DEBUG 3373 if (ehcidebug > 5) { 3374 DPRINTF(("ehci_device_request:\n")); 3375 ehci_dump_sqh(sqh); 3376 ehci_dump_sqtds(setup); 3377 } 3378 #endif 3379 3380 exfer->sqtdstart = setup; 3381 exfer->sqtdend = stat; 3382 #ifdef DIAGNOSTIC 3383 if (!exfer->isdone) { 3384 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3385 } 3386 exfer->isdone = 0; 3387 #endif 3388 3389 /* Insert qTD in QH list. */ 3390 s = splusb(); 3391 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3392 if (xfer->timeout && !sc->sc_bus.use_polling) { 3393 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3394 ehci_timeout, xfer); 3395 } 3396 mutex_enter(&sc->sc_intrhead_lock); 3397 ehci_add_intr_list(sc, exfer); 3398 mutex_exit(&sc->sc_intrhead_lock); 3399 xfer->status = USBD_IN_PROGRESS; 3400 splx(s); 3401 3402 #ifdef EHCI_DEBUG 3403 if (ehcidebug > 10) { 3404 DPRINTF(("ehci_device_request: status=%x\n", 3405 EOREAD4(sc, EHCI_USBSTS))); 3406 delay(10000); 3407 ehci_dump_regs(sc); 3408 ehci_dump_sqh(sc->sc_async_head); 3409 ehci_dump_sqh(sqh); 3410 ehci_dump_sqtds(setup); 3411 } 3412 #endif 3413 3414 return (USBD_NORMAL_COMPLETION); 3415 3416 bad3: 3417 ehci_free_sqtd(sc, stat); 3418 bad2: 3419 ehci_free_sqtd(sc, setup); 3420 bad1: 3421 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3422 xfer->status = err; 3423 usb_transfer_complete(xfer); 3424 return (err); 3425 #undef exfer 3426 } 3427 3428 /* 3429 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3430 * qTD status, or miss signalling occasionally under heavy load. If the host 3431 * machine is too fast, we we can miss transaction completion - when we scan 3432 * the active list the transaction still seems to be active. This generally 3433 * exhibits itself as a umass stall that never recovers. 3434 * 3435 * We work around this behaviour by setting up this callback after any softintr 3436 * that completes with transactions still pending, giving us another chance to 3437 * check for completion after the writeback has taken place. 3438 */ 3439 void 3440 ehci_intrlist_timeout(void *arg) 3441 { 3442 ehci_softc_t *sc = arg; 3443 int s = splusb(); 3444 3445 DPRINTF(("ehci_intrlist_timeout\n")); 3446 usb_schedsoftintr(&sc->sc_bus); 3447 3448 splx(s); 3449 } 3450 3451 /************************/ 3452 3453 Static usbd_status 3454 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3455 { 3456 usbd_status err; 3457 3458 /* Insert last in queue. */ 3459 err = usb_insert_transfer(xfer); 3460 if (err) 3461 return (err); 3462 3463 /* Pipe isn't running, start first */ 3464 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3465 } 3466 3467 usbd_status 3468 ehci_device_bulk_start(usbd_xfer_handle xfer) 3469 { 3470 #define exfer EXFER(xfer) 3471 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3472 usbd_device_handle dev = epipe->pipe.device; 3473 ehci_softc_t *sc = dev->bus->hci_private; 3474 ehci_soft_qtd_t *data, *dataend; 3475 ehci_soft_qh_t *sqh; 3476 usbd_status err; 3477 int len, isread, endpt; 3478 int s; 3479 3480 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3481 xfer, xfer->length, xfer->flags)); 3482 3483 if (sc->sc_dying) 3484 return (USBD_IOERROR); 3485 3486 #ifdef DIAGNOSTIC 3487 if (xfer->rqflags & URQ_REQUEST) 3488 panic("ehci_device_bulk_start: a request"); 3489 #endif 3490 3491 len = xfer->length; 3492 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3493 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3494 sqh = epipe->sqh; 3495 3496 epipe->u.bulk.length = len; 3497 3498 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3499 &dataend); 3500 if (err) { 3501 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3502 xfer->status = err; 3503 usb_transfer_complete(xfer); 3504 return (err); 3505 } 3506 3507 #ifdef EHCI_DEBUG 3508 if (ehcidebug > 5) { 3509 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3510 ehci_dump_sqh(sqh); 3511 ehci_dump_sqtds(data); 3512 } 3513 #endif 3514 3515 /* Set up interrupt info. */ 3516 exfer->sqtdstart = data; 3517 exfer->sqtdend = dataend; 3518 #ifdef DIAGNOSTIC 3519 if (!exfer->isdone) { 3520 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3521 } 3522 exfer->isdone = 0; 3523 #endif 3524 3525 s = splusb(); 3526 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3527 if (xfer->timeout && !sc->sc_bus.use_polling) { 3528 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3529 ehci_timeout, xfer); 3530 } 3531 mutex_enter(&sc->sc_intrhead_lock); 3532 ehci_add_intr_list(sc, exfer); 3533 mutex_exit(&sc->sc_intrhead_lock); 3534 xfer->status = USBD_IN_PROGRESS; 3535 splx(s); 3536 3537 #ifdef EHCI_DEBUG 3538 if (ehcidebug > 10) { 3539 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3540 delay(10000); 3541 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3542 ehci_dump_regs(sc); 3543 #if 0 3544 printf("async_head:\n"); 3545 ehci_dump_sqh(sc->sc_async_head); 3546 #endif 3547 printf("sqh:\n"); 3548 ehci_dump_sqh(sqh); 3549 ehci_dump_sqtds(data); 3550 } 3551 #endif 3552 3553 if (sc->sc_bus.use_polling) 3554 ehci_waitintr(sc, xfer); 3555 3556 return (USBD_IN_PROGRESS); 3557 #undef exfer 3558 } 3559 3560 Static void 3561 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3562 { 3563 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3564 ehci_abort_xfer(xfer, USBD_CANCELLED); 3565 } 3566 3567 /* 3568 * Close a device bulk pipe. 3569 */ 3570 Static void 3571 ehci_device_bulk_close(usbd_pipe_handle pipe) 3572 { 3573 ehci_softc_t *sc = pipe->device->bus->hci_private; 3574 3575 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3576 ehci_close_pipe(pipe, sc->sc_async_head); 3577 } 3578 3579 void 3580 ehci_device_bulk_done(usbd_xfer_handle xfer) 3581 { 3582 struct ehci_xfer *ex = EXFER(xfer); 3583 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3584 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3585 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3586 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3587 3588 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3589 xfer, xfer->actlen)); 3590 3591 mutex_enter(&sc->sc_intrhead_lock); 3592 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3593 ehci_del_intr_list(sc, ex); /* remove from active list */ 3594 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3595 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3596 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3597 } 3598 mutex_exit(&sc->sc_intrhead_lock); 3599 3600 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3601 } 3602 3603 /************************/ 3604 3605 Static usbd_status 3606 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3607 { 3608 struct ehci_soft_islot *isp; 3609 int islot, lev; 3610 3611 /* Find a poll rate that is large enough. */ 3612 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3613 if (EHCI_ILEV_IVAL(lev) <= ival) 3614 break; 3615 3616 /* Pick an interrupt slot at the right level. */ 3617 /* XXX could do better than picking at random */ 3618 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3619 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3620 3621 sqh->islot = islot; 3622 isp = &sc->sc_islots[islot]; 3623 ehci_add_qh(sqh, isp->sqh); 3624 3625 return (USBD_NORMAL_COMPLETION); 3626 } 3627 3628 Static usbd_status 3629 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3630 { 3631 usbd_status err; 3632 3633 /* Insert last in queue. */ 3634 err = usb_insert_transfer(xfer); 3635 if (err) 3636 return (err); 3637 3638 /* 3639 * Pipe isn't running (otherwise err would be USBD_INPROG), 3640 * so start it first. 3641 */ 3642 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3643 } 3644 3645 Static usbd_status 3646 ehci_device_intr_start(usbd_xfer_handle xfer) 3647 { 3648 #define exfer EXFER(xfer) 3649 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3650 usbd_device_handle dev = xfer->pipe->device; 3651 ehci_softc_t *sc = dev->bus->hci_private; 3652 ehci_soft_qtd_t *data, *dataend; 3653 ehci_soft_qh_t *sqh; 3654 usbd_status err; 3655 int len, isread, endpt; 3656 int s; 3657 3658 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3659 xfer, xfer->length, xfer->flags)); 3660 3661 if (sc->sc_dying) 3662 return (USBD_IOERROR); 3663 3664 #ifdef DIAGNOSTIC 3665 if (xfer->rqflags & URQ_REQUEST) 3666 panic("ehci_device_intr_start: a request"); 3667 #endif 3668 3669 len = xfer->length; 3670 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3671 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3672 sqh = epipe->sqh; 3673 3674 epipe->u.intr.length = len; 3675 3676 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3677 &dataend); 3678 if (err) { 3679 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3680 xfer->status = err; 3681 usb_transfer_complete(xfer); 3682 return (err); 3683 } 3684 3685 #ifdef EHCI_DEBUG 3686 if (ehcidebug > 5) { 3687 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3688 ehci_dump_sqh(sqh); 3689 ehci_dump_sqtds(data); 3690 } 3691 #endif 3692 3693 /* Set up interrupt info. */ 3694 exfer->sqtdstart = data; 3695 exfer->sqtdend = dataend; 3696 #ifdef DIAGNOSTIC 3697 if (!exfer->isdone) { 3698 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3699 } 3700 exfer->isdone = 0; 3701 #endif 3702 3703 s = splusb(); 3704 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3705 if (xfer->timeout && !sc->sc_bus.use_polling) { 3706 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3707 ehci_timeout, xfer); 3708 } 3709 mutex_enter(&sc->sc_intrhead_lock); 3710 ehci_add_intr_list(sc, exfer); 3711 mutex_exit(&sc->sc_intrhead_lock); 3712 xfer->status = USBD_IN_PROGRESS; 3713 splx(s); 3714 3715 #ifdef EHCI_DEBUG 3716 if (ehcidebug > 10) { 3717 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3718 delay(10000); 3719 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3720 ehci_dump_regs(sc); 3721 printf("sqh:\n"); 3722 ehci_dump_sqh(sqh); 3723 ehci_dump_sqtds(data); 3724 } 3725 #endif 3726 3727 if (sc->sc_bus.use_polling) 3728 ehci_waitintr(sc, xfer); 3729 3730 return (USBD_IN_PROGRESS); 3731 #undef exfer 3732 } 3733 3734 Static void 3735 ehci_device_intr_abort(usbd_xfer_handle xfer) 3736 { 3737 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3738 if (xfer->pipe->intrxfer == xfer) { 3739 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3740 xfer->pipe->intrxfer = NULL; 3741 } 3742 /* 3743 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3744 * async doorbell. That's dependant on the async list, wheras 3745 * intr xfers are periodic, should not use this? 3746 */ 3747 ehci_abort_xfer(xfer, USBD_CANCELLED); 3748 } 3749 3750 Static void 3751 ehci_device_intr_close(usbd_pipe_handle pipe) 3752 { 3753 ehci_softc_t *sc = pipe->device->bus->hci_private; 3754 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3755 struct ehci_soft_islot *isp; 3756 3757 isp = &sc->sc_islots[epipe->sqh->islot]; 3758 ehci_close_pipe(pipe, isp->sqh); 3759 } 3760 3761 Static void 3762 ehci_device_intr_done(usbd_xfer_handle xfer) 3763 { 3764 #define exfer EXFER(xfer) 3765 struct ehci_xfer *ex = EXFER(xfer); 3766 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3767 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3768 ehci_soft_qtd_t *data, *dataend; 3769 ehci_soft_qh_t *sqh; 3770 usbd_status err; 3771 int len, isread, endpt, s; 3772 3773 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3774 xfer, xfer->actlen)); 3775 3776 mutex_enter(&sc->sc_intrhead_lock); 3777 if (xfer->pipe->repeat) { 3778 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3779 3780 len = epipe->u.intr.length; 3781 xfer->length = len; 3782 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3783 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3784 usb_syncmem(&xfer->dmabuf, 0, len, 3785 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3786 sqh = epipe->sqh; 3787 3788 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3789 &data, &dataend); 3790 if (err) { 3791 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3792 xfer->status = err; 3793 mutex_exit(&sc->sc_intrhead_lock); 3794 return; 3795 } 3796 3797 /* Set up interrupt info. */ 3798 exfer->sqtdstart = data; 3799 exfer->sqtdend = dataend; 3800 #ifdef DIAGNOSTIC 3801 if (!exfer->isdone) { 3802 printf("ehci_device_intr_done: not done, ex=%p\n", 3803 exfer); 3804 } 3805 exfer->isdone = 0; 3806 #endif 3807 3808 s = splusb(); 3809 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3810 if (xfer->timeout && !sc->sc_bus.use_polling) { 3811 usb_callout(xfer->timeout_handle, 3812 mstohz(xfer->timeout), ehci_timeout, xfer); 3813 } 3814 splx(s); 3815 3816 xfer->status = USBD_IN_PROGRESS; 3817 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3818 ehci_del_intr_list(sc, ex); /* remove from active list */ 3819 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3820 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3821 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3822 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3823 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3824 } 3825 mutex_exit(&sc->sc_intrhead_lock); 3826 #undef exfer 3827 } 3828 3829 /************************/ 3830 3831 Static usbd_status 3832 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3833 { 3834 usbd_status err; 3835 3836 err = usb_insert_transfer(xfer); 3837 if (err && err != USBD_IN_PROGRESS) 3838 return err; 3839 3840 return ehci_device_isoc_start(xfer); 3841 } 3842 3843 Static usbd_status 3844 ehci_device_isoc_start(usbd_xfer_handle xfer) 3845 { 3846 struct ehci_pipe *epipe; 3847 usbd_device_handle dev; 3848 ehci_softc_t *sc; 3849 struct ehci_xfer *exfer; 3850 ehci_soft_itd_t *itd, *prev, *start, *stop; 3851 usb_dma_t *dma_buf; 3852 int i, j, k, frames, uframes, ufrperframe; 3853 int s, trans_count, offs, total_length; 3854 int frindex; 3855 3856 start = NULL; 3857 prev = NULL; 3858 itd = NULL; 3859 trans_count = 0; 3860 total_length = 0; 3861 exfer = (struct ehci_xfer *) xfer; 3862 sc = xfer->pipe->device->bus->hci_private; 3863 dev = xfer->pipe->device; 3864 epipe = (struct ehci_pipe *)xfer->pipe; 3865 3866 /* 3867 * To allow continuous transfers, above we start all transfers 3868 * immediately. However, we're still going to get usbd_start_next call 3869 * this when another xfer completes. So, check if this is already 3870 * in progress or not 3871 */ 3872 3873 if (exfer->itdstart != NULL) 3874 return USBD_IN_PROGRESS; 3875 3876 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3877 xfer, xfer->length, xfer->flags)); 3878 3879 if (sc->sc_dying) 3880 return USBD_IOERROR; 3881 3882 /* 3883 * To avoid complication, don't allow a request right now that'll span 3884 * the entire frame table. To within 4 frames, to allow some leeway 3885 * on either side of where the hc currently is. 3886 */ 3887 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3888 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3889 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3890 return USBD_INVAL; 3891 } 3892 3893 #ifdef DIAGNOSTIC 3894 if (xfer->rqflags & URQ_REQUEST) 3895 panic("ehci_device_isoc_start: request\n"); 3896 3897 if (!exfer->isdone) 3898 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3899 exfer->isdone = 0; 3900 #endif 3901 3902 /* 3903 * Step 1: Allocate and initialize itds, how many do we need? 3904 * One per transfer if interval >= 8 microframes, fewer if we use 3905 * multiple microframes per frame. 3906 */ 3907 3908 i = epipe->pipe.endpoint->edesc->bInterval; 3909 if (i > 16 || i == 0) { 3910 /* Spec page 271 says intervals > 16 are invalid */ 3911 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3912 return USBD_INVAL; 3913 } 3914 3915 switch (i) { 3916 case 1: 3917 ufrperframe = 8; 3918 break; 3919 case 2: 3920 ufrperframe = 4; 3921 break; 3922 case 3: 3923 ufrperframe = 2; 3924 break; 3925 default: 3926 ufrperframe = 1; 3927 break; 3928 } 3929 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3930 uframes = 8 / ufrperframe; 3931 3932 if (frames == 0) { 3933 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3934 return USBD_INVAL; 3935 } 3936 3937 dma_buf = &xfer->dmabuf; 3938 offs = 0; 3939 3940 for (i = 0; i < frames; i++) { 3941 int froffs = offs; 3942 itd = ehci_alloc_itd(sc); 3943 3944 if (prev != NULL) { 3945 prev->itd.itd_next = 3946 htole32(itd->physaddr | EHCI_LINK_ITD); 3947 usb_syncmem(&itd->dma, 3948 itd->offs + offsetof(ehci_itd_t, itd_next), 3949 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 3950 3951 prev->xfer_next = itd; 3952 } else { 3953 start = itd; 3954 } 3955 3956 /* 3957 * Step 1.5, initialize uframes 3958 */ 3959 for (j = 0; j < 8; j += uframes) { 3960 /* Calculate which page in the list this starts in */ 3961 int addr = DMAADDR(dma_buf, froffs); 3962 addr = EHCI_PAGE_OFFSET(addr); 3963 addr += (offs - froffs); 3964 addr = EHCI_PAGE(addr); 3965 addr /= EHCI_PAGE_SIZE; 3966 3967 /* This gets the initial offset into the first page, 3968 * looks how far further along the current uframe 3969 * offset is. Works out how many pages that is. 3970 */ 3971 3972 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3973 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3974 EHCI_ITD_SET_PG(addr) | 3975 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 3976 3977 total_length += xfer->frlengths[trans_count]; 3978 offs += xfer->frlengths[trans_count]; 3979 trans_count++; 3980 3981 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3982 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3983 break; 3984 } 3985 } 3986 3987 /* Step 1.75, set buffer pointers. To simplify matters, all 3988 * pointers are filled out for the next 7 hardware pages in 3989 * the dma block, so no need to worry what pages to cover 3990 * and what to not. 3991 */ 3992 3993 for (j=0; j < 7; j++) { 3994 /* 3995 * Don't try to lookup a page that's past the end 3996 * of buffer 3997 */ 3998 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 3999 if (page_offs >= dma_buf->block->size) 4000 break; 4001 4002 long long page = DMAADDR(dma_buf, page_offs); 4003 page = EHCI_PAGE(page); 4004 itd->itd.itd_bufr[j] = 4005 htole32(EHCI_ITD_SET_BPTR(page)); 4006 itd->itd.itd_bufr_hi[j] = 4007 htole32(page >> 32); 4008 } 4009 4010 /* 4011 * Other special values 4012 */ 4013 4014 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4015 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4016 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4017 4018 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4019 ? 1 : 0; 4020 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4021 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4022 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4023 4024 /* FIXME: handle invalid trans */ 4025 itd->itd.itd_bufr[2] |= 4026 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4027 4028 usb_syncmem(&itd->dma, 4029 itd->offs + offsetof(ehci_itd_t, itd_next), 4030 sizeof(ehci_itd_t), 4031 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4032 4033 prev = itd; 4034 } /* End of frame */ 4035 4036 stop = itd; 4037 stop->xfer_next = NULL; 4038 exfer->isoc_len = total_length; 4039 4040 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4041 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4042 4043 /* 4044 * Part 2: Transfer descriptors have now been set up, now they must 4045 * be scheduled into the period frame list. Erk. Not wanting to 4046 * complicate matters, transfer is denied if the transfer spans 4047 * more than the period frame list. 4048 */ 4049 4050 s = splusb(); 4051 4052 /* Start inserting frames */ 4053 if (epipe->u.isoc.cur_xfers > 0) { 4054 frindex = epipe->u.isoc.next_frame; 4055 } else { 4056 frindex = EOREAD4(sc, EHCI_FRINDEX); 4057 frindex = frindex >> 3; /* Erase microframe index */ 4058 frindex += 2; 4059 } 4060 4061 if (frindex >= sc->sc_flsize) 4062 frindex &= (sc->sc_flsize - 1); 4063 4064 /* Whats the frame interval? */ 4065 i = (1 << epipe->pipe.endpoint->edesc->bInterval); 4066 if (i / 8 == 0) 4067 i = 1; 4068 else 4069 i /= 8; 4070 4071 itd = start; 4072 for (j = 0; j < frames; j++) { 4073 if (itd == NULL) 4074 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4075 4076 itd->itd.itd_next = sc->sc_flist[frindex]; 4077 if (itd->itd.itd_next == 0) 4078 /* FIXME: frindex table gets initialized to NULL 4079 * or EHCI_NULL? */ 4080 itd->itd.itd_next = htole32(EHCI_NULL); 4081 4082 usb_syncmem(&itd->dma, 4083 itd->offs + offsetof(ehci_itd_t, itd_next), 4084 sizeof(itd->itd.itd_next), 4085 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4086 4087 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4088 4089 usb_syncmem(&sc->sc_fldma, 4090 sizeof(ehci_link_t) * frindex, 4091 sizeof(ehci_link_t), 4092 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4093 4094 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4095 sc->sc_softitds[frindex] = itd; 4096 if (itd->u.frame_list.next != NULL) 4097 itd->u.frame_list.next->u.frame_list.prev = itd; 4098 itd->slot = frindex; 4099 itd->u.frame_list.prev = NULL; 4100 4101 frindex += i; 4102 if (frindex >= sc->sc_flsize) 4103 frindex -= sc->sc_flsize; 4104 4105 itd = itd->xfer_next; 4106 } 4107 4108 epipe->u.isoc.cur_xfers++; 4109 epipe->u.isoc.next_frame = frindex; 4110 4111 exfer->itdstart = start; 4112 exfer->itdend = stop; 4113 exfer->sqtdstart = NULL; 4114 exfer->sqtdstart = NULL; 4115 4116 mutex_enter(&sc->sc_intrhead_lock); 4117 ehci_add_intr_list(sc, exfer); 4118 mutex_exit(&sc->sc_intrhead_lock); 4119 xfer->status = USBD_IN_PROGRESS; 4120 xfer->done = 0; 4121 splx(s); 4122 4123 if (sc->sc_bus.use_polling) { 4124 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4125 ehci_waitintr(sc, xfer); 4126 } 4127 4128 return USBD_IN_PROGRESS; 4129 } 4130 4131 Static void 4132 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4133 { 4134 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4135 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4136 } 4137 4138 Static void 4139 ehci_device_isoc_close(usbd_pipe_handle pipe) 4140 { 4141 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4142 } 4143 4144 Static void 4145 ehci_device_isoc_done(usbd_xfer_handle xfer) 4146 { 4147 struct ehci_xfer *exfer; 4148 ehci_softc_t *sc; 4149 struct ehci_pipe *epipe; 4150 int s; 4151 4152 exfer = EXFER(xfer); 4153 sc = xfer->pipe->device->bus->hci_private; 4154 epipe = (struct ehci_pipe *) xfer->pipe; 4155 4156 s = splusb(); 4157 epipe->u.isoc.cur_xfers--; 4158 mutex_enter(&sc->sc_intrhead_lock); 4159 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4160 ehci_del_intr_list(sc, exfer); 4161 ehci_rem_free_itd_chain(sc, exfer); 4162 } 4163 mutex_exit(&sc->sc_intrhead_lock); 4164 splx(s); 4165 4166 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4167 BUS_DMASYNC_POSTREAD); 4168 4169 } 4170
Indexes created Thu Oct 02 01:09:59 GMT 2025