ehci.c revision 1.158
1 /* $NetBSD: ehci.c,v 1.158 2009/07/27 14:41:19 sketch Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum and 9 * Jeremy Morse (jeremy.morse (at) gmail.com). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 35 * 36 * The EHCI 1.0 spec can be found at 37 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/usb_20.zip 40 * 41 */ 42 43 /* 44 * TODO: 45 * 1) hold off explorations by companion controllers until ehci has started. 46 * 47 * 2) The hub driver needs to handle and schedule the transaction translator, 48 * to assign place in frame where different devices get to go. See chapter 49 * on hubs in USB 2.0 for details. 50 * 51 * 3) command failures are not recovered correctly 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.158 2009/07/27 14:41:19 sketch Exp $"); 56 57 #include "ohci.h" 58 #include "uhci.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/kernel.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/select.h> 66 #include <sys/proc.h> 67 #include <sys/queue.h> 68 #include <sys/mutex.h> 69 #include <sys/bus.h> 70 71 #include <machine/endian.h> 72 73 #include <dev/usb/usb.h> 74 #include <dev/usb/usbdi.h> 75 #include <dev/usb/usbdivar.h> 76 #include <dev/usb/usb_mem.h> 77 #include <dev/usb/usb_quirks.h> 78 79 #include <dev/usb/ehcireg.h> 80 #include <dev/usb/ehcivar.h> 81 #include <dev/usb/usbroothub_subr.h> 82 83 #ifdef EHCI_DEBUG 84 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 85 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 86 int ehcidebug = 0; 87 #ifndef __NetBSD__ 88 #define snprintb((q), (f), "%b", q,f,b,l) snprintf((b), (l)) 89 #endif 90 #else 91 #define DPRINTF(x) 92 #define DPRINTFN(n,x) 93 #endif 94 95 struct ehci_pipe { 96 struct usbd_pipe pipe; 97 int nexttoggle; 98 99 ehci_soft_qh_t *sqh; 100 union { 101 ehci_soft_qtd_t *qtd; 102 /* ehci_soft_itd_t *itd; */ 103 } tail; 104 union { 105 /* Control pipe */ 106 struct { 107 usb_dma_t reqdma; 108 u_int length; 109 } ctl; 110 /* Interrupt pipe */ 111 struct { 112 u_int length; 113 } intr; 114 /* Bulk pipe */ 115 struct { 116 u_int length; 117 } bulk; 118 /* Iso pipe */ 119 struct { 120 u_int next_frame; 121 u_int cur_xfers; 122 } isoc; 123 } u; 124 }; 125 126 Static usbd_status ehci_open(usbd_pipe_handle); 127 Static void ehci_poll(struct usbd_bus *); 128 Static void ehci_softintr(void *); 129 Static int ehci_intr1(ehci_softc_t *); 130 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 131 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 132 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 133 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 134 Static void ehci_idone(struct ehci_xfer *); 135 Static void ehci_timeout(void *); 136 Static void ehci_timeout_task(void *); 137 Static void ehci_intrlist_timeout(void *); 138 139 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 140 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 141 142 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 143 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 144 145 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 146 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 147 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 148 Static void ehci_root_ctrl_close(usbd_pipe_handle); 149 Static void ehci_root_ctrl_done(usbd_xfer_handle); 150 151 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 152 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 153 Static void ehci_root_intr_abort(usbd_xfer_handle); 154 Static void ehci_root_intr_close(usbd_pipe_handle); 155 Static void ehci_root_intr_done(usbd_xfer_handle); 156 157 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 158 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 159 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 160 Static void ehci_device_ctrl_close(usbd_pipe_handle); 161 Static void ehci_device_ctrl_done(usbd_xfer_handle); 162 163 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 164 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 165 Static void ehci_device_bulk_abort(usbd_xfer_handle); 166 Static void ehci_device_bulk_close(usbd_pipe_handle); 167 Static void ehci_device_bulk_done(usbd_xfer_handle); 168 169 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 170 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 171 Static void ehci_device_intr_abort(usbd_xfer_handle); 172 Static void ehci_device_intr_close(usbd_pipe_handle); 173 Static void ehci_device_intr_done(usbd_xfer_handle); 174 175 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 176 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 177 Static void ehci_device_isoc_abort(usbd_xfer_handle); 178 Static void ehci_device_isoc_close(usbd_pipe_handle); 179 Static void ehci_device_isoc_done(usbd_xfer_handle); 180 181 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 182 Static void ehci_noop(usbd_pipe_handle pipe); 183 184 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 185 Static void ehci_disown(ehci_softc_t *, int, int); 186 187 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 188 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 189 190 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 191 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 192 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 193 ehci_softc_t *, int, int, usbd_xfer_handle, 194 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 195 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 196 ehci_soft_qtd_t *); 197 198 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 199 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 200 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 201 struct ehci_xfer *exfer); 202 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 203 usbd_status status); 204 205 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 206 207 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 208 int ival); 209 210 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 211 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 212 ehci_soft_qh_t *); 213 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 214 Static void ehci_sync_hc(ehci_softc_t *); 215 216 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 217 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 218 219 #ifdef EHCI_DEBUG 220 Static void ehci_dump_regs(ehci_softc_t *); 221 void ehci_dump(void); 222 Static ehci_softc_t *theehci; 223 Static void ehci_dump_link(ehci_link_t, int); 224 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 225 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 226 Static void ehci_dump_qtd(ehci_qtd_t *); 227 Static void ehci_dump_sqh(ehci_soft_qh_t *); 228 #if notyet 229 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 230 Static void ehci_dump_itd(struct ehci_soft_itd *); 231 #endif 232 #ifdef DIAGNOSTIC 233 Static void ehci_dump_exfer(struct ehci_xfer *); 234 #endif 235 #endif 236 237 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 238 239 #define EHCI_INTR_ENDPT 1 240 241 #define ehci_add_intr_list(sc, ex) \ 242 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 243 #define ehci_del_intr_list(sc, ex) \ 244 do { \ 245 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 246 (ex)->inext.tqe_prev = NULL; \ 247 } while (0) 248 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 249 250 Static const struct usbd_bus_methods ehci_bus_methods = { 251 ehci_open, 252 ehci_softintr, 253 ehci_poll, 254 ehci_allocm, 255 ehci_freem, 256 ehci_allocx, 257 ehci_freex, 258 }; 259 260 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 261 ehci_root_ctrl_transfer, 262 ehci_root_ctrl_start, 263 ehci_root_ctrl_abort, 264 ehci_root_ctrl_close, 265 ehci_noop, 266 ehci_root_ctrl_done, 267 }; 268 269 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 270 ehci_root_intr_transfer, 271 ehci_root_intr_start, 272 ehci_root_intr_abort, 273 ehci_root_intr_close, 274 ehci_noop, 275 ehci_root_intr_done, 276 }; 277 278 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 279 ehci_device_ctrl_transfer, 280 ehci_device_ctrl_start, 281 ehci_device_ctrl_abort, 282 ehci_device_ctrl_close, 283 ehci_noop, 284 ehci_device_ctrl_done, 285 }; 286 287 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 288 ehci_device_intr_transfer, 289 ehci_device_intr_start, 290 ehci_device_intr_abort, 291 ehci_device_intr_close, 292 ehci_device_clear_toggle, 293 ehci_device_intr_done, 294 }; 295 296 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 297 ehci_device_bulk_transfer, 298 ehci_device_bulk_start, 299 ehci_device_bulk_abort, 300 ehci_device_bulk_close, 301 ehci_device_clear_toggle, 302 ehci_device_bulk_done, 303 }; 304 305 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 306 ehci_device_isoc_transfer, 307 ehci_device_isoc_start, 308 ehci_device_isoc_abort, 309 ehci_device_isoc_close, 310 ehci_noop, 311 ehci_device_isoc_done, 312 }; 313 314 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 315 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 316 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 317 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 318 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 319 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 320 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 321 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 322 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 323 }; 324 325 usbd_status 326 ehci_init(ehci_softc_t *sc) 327 { 328 u_int32_t vers, sparams, cparams, hcr; 329 u_int i; 330 usbd_status err; 331 ehci_soft_qh_t *sqh; 332 u_int ncomp; 333 334 DPRINTF(("ehci_init: start\n")); 335 #ifdef EHCI_DEBUG 336 theehci = sc; 337 #endif 338 339 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 340 341 vers = EREAD2(sc, EHCI_HCIVERSION); 342 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 343 vers >> 8, vers & 0xff); 344 345 sparams = EREAD4(sc, EHCI_HCSPARAMS); 346 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 347 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 348 ncomp = EHCI_HCS_N_CC(sparams); 349 if (ncomp != sc->sc_ncomp) { 350 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 351 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 352 #if NOHCI == 0 || NUHCI == 0 353 aprint_error("%s: ohci or uhci probably not configured\n", 354 device_xname(sc->sc_dev)); 355 #endif 356 if (ncomp < sc->sc_ncomp) 357 sc->sc_ncomp = ncomp; 358 } 359 if (sc->sc_ncomp > 0) { 360 aprint_normal("%s: companion controller%s, %d port%s each:", 361 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 362 EHCI_HCS_N_PCC(sparams), 363 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 364 for (i = 0; i < sc->sc_ncomp; i++) 365 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 366 aprint_normal("\n"); 367 } 368 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 369 cparams = EREAD4(sc, EHCI_HCCPARAMS); 370 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 371 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 372 373 if (EHCI_HCC_64BIT(cparams)) { 374 /* MUST clear segment register if 64 bit capable. */ 375 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 376 } 377 378 sc->sc_bus.usbrev = USBREV_2_0; 379 380 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 381 USB_MEM_RESERVE); 382 383 /* Reset the controller */ 384 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 385 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 386 usb_delay_ms(&sc->sc_bus, 1); 387 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 388 for (i = 0; i < 100; i++) { 389 usb_delay_ms(&sc->sc_bus, 1); 390 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 391 if (!hcr) 392 break; 393 } 394 if (hcr) { 395 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 396 return (USBD_IOERROR); 397 } 398 399 /* XXX need proper intr scheduling */ 400 sc->sc_rand = 96; 401 402 /* frame list size at default, read back what we got and use that */ 403 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 404 case 0: sc->sc_flsize = 1024; break; 405 case 1: sc->sc_flsize = 512; break; 406 case 2: sc->sc_flsize = 256; break; 407 case 3: return (USBD_IOERROR); 408 } 409 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 410 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 411 if (err) 412 return (err); 413 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 414 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 415 416 for (i = 0; i < sc->sc_flsize; i++) { 417 sc->sc_flist[i] = EHCI_NULL; 418 } 419 420 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 421 422 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 423 M_USB, M_NOWAIT | M_ZERO); 424 if (sc->sc_softitds == NULL) 425 return ENOMEM; 426 LIST_INIT(&sc->sc_freeitds); 427 TAILQ_INIT(&sc->sc_intrhead); 428 mutex_init(&sc->sc_intrhead_lock, MUTEX_DEFAULT, IPL_USB); 429 430 /* Set up the bus struct. */ 431 sc->sc_bus.methods = &ehci_bus_methods; 432 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 433 434 sc->sc_eintrs = EHCI_NORMAL_INTRS; 435 436 /* 437 * Allocate the interrupt dummy QHs. These are arranged to give poll 438 * intervals that are powers of 2 times 1ms. 439 */ 440 for (i = 0; i < EHCI_INTRQHS; i++) { 441 sqh = ehci_alloc_sqh(sc); 442 if (sqh == NULL) { 443 err = USBD_NOMEM; 444 goto bad1; 445 } 446 sc->sc_islots[i].sqh = sqh; 447 } 448 for (i = 0; i < EHCI_INTRQHS; i++) { 449 sqh = sc->sc_islots[i].sqh; 450 if (i == 0) { 451 /* The last (1ms) QH terminates. */ 452 sqh->qh.qh_link = EHCI_NULL; 453 sqh->next = NULL; 454 } else { 455 /* Otherwise the next QH has half the poll interval */ 456 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 457 sqh->qh.qh_link = htole32(sqh->next->physaddr | 458 EHCI_LINK_QH); 459 } 460 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 461 sqh->qh.qh_curqtd = EHCI_NULL; 462 sqh->next = NULL; 463 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 464 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 465 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 466 sqh->sqtd = NULL; 467 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 468 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 469 } 470 /* Point the frame list at the last level (128ms). */ 471 for (i = 0; i < sc->sc_flsize; i++) { 472 int j; 473 474 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 475 revbits[i & (EHCI_MAX_POLLRATE-1)]; 476 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 477 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 478 i)].sqh->physaddr); 479 } 480 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 481 BUS_DMASYNC_PREWRITE); 482 483 /* Allocate dummy QH that starts the async list. */ 484 sqh = ehci_alloc_sqh(sc); 485 if (sqh == NULL) { 486 err = USBD_NOMEM; 487 goto bad1; 488 } 489 /* Fill the QH */ 490 sqh->qh.qh_endp = 491 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 492 sqh->qh.qh_link = 493 htole32(sqh->physaddr | EHCI_LINK_QH); 494 sqh->qh.qh_curqtd = EHCI_NULL; 495 sqh->next = NULL; 496 /* Fill the overlay qTD */ 497 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 498 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 499 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 500 sqh->sqtd = NULL; 501 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 502 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 503 #ifdef EHCI_DEBUG 504 if (ehcidebug) { 505 ehci_dump_sqh(sqh); 506 } 507 #endif 508 509 /* Point to async list */ 510 sc->sc_async_head = sqh; 511 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 512 513 usb_callout_init(sc->sc_tmo_intrlist); 514 515 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE); 516 517 /* Turn on controller */ 518 EOWRITE4(sc, EHCI_USBCMD, 519 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 520 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 521 EHCI_CMD_ASE | 522 EHCI_CMD_PSE | 523 EHCI_CMD_RS); 524 525 /* Take over port ownership */ 526 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 527 528 for (i = 0; i < 100; i++) { 529 usb_delay_ms(&sc->sc_bus, 1); 530 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 531 if (!hcr) 532 break; 533 } 534 if (hcr) { 535 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 536 return (USBD_IOERROR); 537 } 538 539 /* Enable interrupts */ 540 DPRINTFN(1,("ehci_init: enabling\n")); 541 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 542 543 return (USBD_NORMAL_COMPLETION); 544 545 #if 0 546 bad2: 547 ehci_free_sqh(sc, sc->sc_async_head); 548 #endif 549 bad1: 550 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 551 return (err); 552 } 553 554 int 555 ehci_intr(void *v) 556 { 557 ehci_softc_t *sc = v; 558 559 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 560 return (0); 561 562 /* If we get an interrupt while polling, then just ignore it. */ 563 if (sc->sc_bus.use_polling) { 564 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 565 566 if (intrs) 567 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 568 #ifdef DIAGNOSTIC 569 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 570 #endif 571 return (0); 572 } 573 574 return (ehci_intr1(sc)); 575 } 576 577 Static int 578 ehci_intr1(ehci_softc_t *sc) 579 { 580 u_int32_t intrs, eintrs; 581 582 DPRINTFN(20,("ehci_intr1: enter\n")); 583 584 /* In case the interrupt occurs before initialization has completed. */ 585 if (sc == NULL) { 586 #ifdef DIAGNOSTIC 587 printf("ehci_intr1: sc == NULL\n"); 588 #endif 589 return (0); 590 } 591 592 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 593 if (!intrs) 594 return (0); 595 596 eintrs = intrs & sc->sc_eintrs; 597 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 598 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 599 (u_int)eintrs)); 600 if (!eintrs) 601 return (0); 602 603 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 604 sc->sc_bus.intr_context++; 605 sc->sc_bus.no_intrs++; 606 if (eintrs & EHCI_STS_IAA) { 607 DPRINTF(("ehci_intr1: door bell\n")); 608 wakeup(&sc->sc_async_head); 609 eintrs &= ~EHCI_STS_IAA; 610 } 611 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 612 DPRINTFN(5,("ehci_intr1: %s %s\n", 613 eintrs & EHCI_STS_INT ? "INT" : "", 614 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 615 usb_schedsoftintr(&sc->sc_bus); 616 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 617 } 618 if (eintrs & EHCI_STS_HSE) { 619 printf("%s: unrecoverable error, controller halted\n", 620 device_xname(sc->sc_dev)); 621 /* XXX what else */ 622 } 623 if (eintrs & EHCI_STS_PCD) { 624 ehci_pcd(sc, sc->sc_intrxfer); 625 eintrs &= ~EHCI_STS_PCD; 626 } 627 628 sc->sc_bus.intr_context--; 629 630 if (eintrs != 0) { 631 /* Block unprocessed interrupts. */ 632 sc->sc_eintrs &= ~eintrs; 633 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 634 printf("%s: blocking intrs 0x%x\n", 635 device_xname(sc->sc_dev), eintrs); 636 } 637 638 return (1); 639 } 640 641 642 void 643 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 644 { 645 usbd_pipe_handle pipe; 646 u_char *p; 647 int i, m; 648 649 if (xfer == NULL) { 650 /* Just ignore the change. */ 651 return; 652 } 653 654 pipe = xfer->pipe; 655 656 p = KERNADDR(&xfer->dmabuf, 0); 657 m = min(sc->sc_noport, xfer->length * 8 - 1); 658 memset(p, 0, xfer->length); 659 for (i = 1; i <= m; i++) { 660 /* Pick out CHANGE bits from the status reg. */ 661 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 662 p[i/8] |= 1 << (i%8); 663 } 664 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 665 xfer->actlen = xfer->length; 666 xfer->status = USBD_NORMAL_COMPLETION; 667 668 usb_transfer_complete(xfer); 669 } 670 671 void 672 ehci_softintr(void *v) 673 { 674 struct usbd_bus *bus = v; 675 ehci_softc_t *sc = bus->hci_private; 676 struct ehci_xfer *ex, *nextex; 677 678 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 679 sc->sc_bus.intr_context)); 680 681 sc->sc_bus.intr_context++; 682 683 /* 684 * The only explanation I can think of for why EHCI is as brain dead 685 * as UHCI interrupt-wise is that Intel was involved in both. 686 * An interrupt just tells us that something is done, we have no 687 * clue what, so we need to scan through all active transfers. :-( 688 */ 689 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 690 nextex = TAILQ_NEXT(ex, inext); 691 ehci_check_intr(sc, ex); 692 } 693 694 /* Schedule a callout to catch any dropped transactions. */ 695 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 696 !TAILQ_EMPTY(&sc->sc_intrhead)) 697 usb_callout(sc->sc_tmo_intrlist, hz, 698 ehci_intrlist_timeout, sc); 699 700 #ifdef USB_USE_SOFTINTR 701 if (sc->sc_softwake) { 702 sc->sc_softwake = 0; 703 wakeup(&sc->sc_softwake); 704 } 705 #endif /* USB_USE_SOFTINTR */ 706 707 sc->sc_bus.intr_context--; 708 } 709 710 /* Check for an interrupt. */ 711 void 712 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 713 { 714 int attr; 715 716 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 717 718 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 719 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 720 ehci_check_itd_intr(sc, ex); 721 else 722 ehci_check_qh_intr(sc, ex); 723 724 return; 725 } 726 727 void 728 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 729 { 730 ehci_soft_qtd_t *sqtd, *lsqtd; 731 __uint32_t status; 732 733 if (ex->sqtdstart == NULL) { 734 printf("ehci_check_qh_intr: not valid sqtd\n"); 735 return; 736 } 737 738 lsqtd = ex->sqtdend; 739 #ifdef DIAGNOSTIC 740 if (lsqtd == NULL) { 741 printf("ehci_check_qh_intr: lsqtd==0\n"); 742 return; 743 } 744 #endif 745 /* 746 * If the last TD is still active we need to check whether there 747 * is a an error somewhere in the middle, or whether there was a 748 * short packet (SPD and not ACTIVE). 749 */ 750 usb_syncmem(&lsqtd->dma, 751 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 752 sizeof(lsqtd->qtd.qtd_status), 753 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 754 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 755 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 756 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 757 usb_syncmem(&sqtd->dma, 758 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 759 sizeof(sqtd->qtd.qtd_status), 760 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 761 status = le32toh(sqtd->qtd.qtd_status); 762 usb_syncmem(&sqtd->dma, 763 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 764 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 765 /* If there's an active QTD the xfer isn't done. */ 766 if (status & EHCI_QTD_ACTIVE) 767 break; 768 /* Any kind of error makes the xfer done. */ 769 if (status & EHCI_QTD_HALTED) 770 goto done; 771 /* We want short packets, and it is short: it's done */ 772 if (EHCI_QTD_GET_BYTES(status) != 0) 773 goto done; 774 } 775 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 776 ex, ex->sqtdstart)); 777 usb_syncmem(&lsqtd->dma, 778 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 779 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 780 return; 781 } 782 done: 783 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 784 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 785 ehci_idone(ex); 786 } 787 788 void 789 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 790 ehci_soft_itd_t *itd; 791 int i; 792 793 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 794 return; 795 796 if (ex->itdstart == NULL) { 797 printf("ehci_check_itd_intr: not valid itd\n"); 798 return; 799 } 800 801 itd = ex->itdend; 802 #ifdef DIAGNOSTIC 803 if (itd == NULL) { 804 printf("ehci_check_itd_intr: itdend == 0\n"); 805 return; 806 } 807 #endif 808 809 /* 810 * check no active transfers in last itd, meaning we're finished 811 */ 812 813 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 814 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 815 BUS_DMASYNC_POSTREAD); 816 817 for (i = 0; i < 8; i++) { 818 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 819 break; 820 } 821 822 if (i == 8) { 823 goto done; /* All 8 descriptors inactive, it's done */ 824 } 825 826 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 827 ex->itdstart)); 828 return; 829 done: 830 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 831 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex); 832 ehci_idone(ex); 833 } 834 835 void 836 ehci_idone(struct ehci_xfer *ex) 837 { 838 usbd_xfer_handle xfer = &ex->xfer; 839 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 840 ehci_soft_qtd_t *sqtd, *lsqtd; 841 u_int32_t status = 0, nstatus = 0; 842 int actlen; 843 844 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 845 #ifdef DIAGNOSTIC 846 { 847 int s = splhigh(); 848 if (ex->isdone) { 849 splx(s); 850 #ifdef EHCI_DEBUG 851 printf("ehci_idone: ex is done!\n "); 852 ehci_dump_exfer(ex); 853 #else 854 printf("ehci_idone: ex=%p is done!\n", ex); 855 #endif 856 return; 857 } 858 ex->isdone = 1; 859 splx(s); 860 } 861 #endif 862 if (xfer->status == USBD_CANCELLED || 863 xfer->status == USBD_TIMEOUT) { 864 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 865 return; 866 } 867 868 #ifdef EHCI_DEBUG 869 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 870 if (ehcidebug > 10) 871 ehci_dump_sqtds(ex->sqtdstart); 872 #endif 873 874 /* The transfer is done, compute actual length and status. */ 875 876 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 877 == UE_ISOCHRONOUS) { 878 /* Isoc transfer */ 879 struct ehci_soft_itd *itd; 880 int i, nframes, len, uframes; 881 882 nframes = 0; 883 actlen = 0; 884 885 switch (xfer->pipe->endpoint->edesc->bInterval) { 886 case 0: 887 panic("ehci: isoc xfer suddenly has 0 bInterval, invalid\n"); 888 case 1: uframes = 1; break; 889 case 2: uframes = 2; break; 890 case 3: uframes = 4; break; 891 default: uframes = 8; break; 892 } 893 894 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 895 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 896 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 897 BUS_DMASYNC_POSTREAD); 898 899 for (i = 0; i < 8; i += uframes) { 900 /* XXX - driver didn't fill in the frame full 901 * of uframes. This leads to scheduling 902 * inefficiencies, but working around 903 * this doubles complexity of tracking 904 * an xfer. 905 */ 906 if (nframes >= xfer->nframes) 907 break; 908 909 status = le32toh(itd->itd.itd_ctl[i]); 910 len = EHCI_ITD_GET_LEN(status); 911 if (EHCI_ITD_GET_STATUS(status) != 0) 912 len = 0; /*No valid data on error*/ 913 914 xfer->frlengths[nframes++] = len; 915 actlen += len; 916 } 917 918 if (nframes >= xfer->nframes) 919 break; 920 } 921 922 xfer->actlen = actlen; 923 xfer->status = USBD_NORMAL_COMPLETION; 924 goto end; 925 } 926 927 /* Continue processing xfers using queue heads */ 928 929 lsqtd = ex->sqtdend; 930 actlen = 0; 931 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 932 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 933 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 934 nstatus = le32toh(sqtd->qtd.qtd_status); 935 if (nstatus & EHCI_QTD_ACTIVE) 936 break; 937 938 status = nstatus; 939 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 940 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 941 } 942 943 944 /* 945 * If there are left over TDs we need to update the toggle. 946 * The default pipe doesn't need it since control transfers 947 * start the toggle at 0 every time. 948 * For a short transfer we need to update the toggle for the missing 949 * packets within the qTD. 950 */ 951 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 952 xfer->pipe->device->default_pipe != xfer->pipe) { 953 DPRINTFN(2, ("ehci_idone: need toggle update " 954 "status=%08x nstatus=%08x\n", status, nstatus)); 955 #if 0 956 ehci_dump_sqh(epipe->sqh); 957 ehci_dump_sqtds(ex->sqtdstart); 958 #endif 959 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 960 } 961 962 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 963 xfer->length, actlen, status)); 964 xfer->actlen = actlen; 965 if (status & EHCI_QTD_HALTED) { 966 #ifdef EHCI_DEBUG 967 char sbuf[128]; 968 969 snprintb(sbuf, sizeof(sbuf), 970 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 971 (u_int32_t)status); 972 973 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 974 "status 0x%s\n", 975 xfer->pipe->device->address, 976 xfer->pipe->endpoint->edesc->bEndpointAddress, 977 sbuf)); 978 if (ehcidebug > 2) { 979 ehci_dump_sqh(epipe->sqh); 980 ehci_dump_sqtds(ex->sqtdstart); 981 } 982 #endif 983 /* low&full speed has an extra error flag */ 984 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 985 EHCI_QH_SPEED_HIGH) 986 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 987 else 988 status &= EHCI_QTD_STATERRS; 989 if (status == 0) /* no other errors means a stall */ { 990 xfer->status = USBD_STALLED; 991 } else { 992 xfer->status = USBD_IOERROR; /* more info XXX */ 993 } 994 /* XXX need to reset TT on missed microframe */ 995 if (status & EHCI_QTD_MISSEDMICRO) { 996 ehci_softc_t *sc = 997 xfer->pipe->device->bus->hci_private; 998 999 printf("%s: missed microframe, TT reset not " 1000 "implemented, hub might be inoperational\n", 1001 device_xname(sc->sc_dev)); 1002 } 1003 } else { 1004 xfer->status = USBD_NORMAL_COMPLETION; 1005 } 1006 1007 end: 1008 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1009 * during this call, before methods->done is called: dma sync required 1010 * beforehand? */ 1011 usb_transfer_complete(xfer); 1012 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1013 } 1014 1015 /* 1016 * Wait here until controller claims to have an interrupt. 1017 * Then call ehci_intr and return. Use timeout to avoid waiting 1018 * too long. 1019 */ 1020 void 1021 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1022 { 1023 int timo; 1024 u_int32_t intrs; 1025 1026 xfer->status = USBD_IN_PROGRESS; 1027 for (timo = xfer->timeout; timo >= 0; timo--) { 1028 usb_delay_ms(&sc->sc_bus, 1); 1029 if (sc->sc_dying) 1030 break; 1031 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1032 sc->sc_eintrs; 1033 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1034 #ifdef EHCI_DEBUG 1035 if (ehcidebug > 15) 1036 ehci_dump_regs(sc); 1037 #endif 1038 if (intrs) { 1039 ehci_intr1(sc); 1040 if (xfer->status != USBD_IN_PROGRESS) 1041 return; 1042 } 1043 } 1044 1045 /* Timeout */ 1046 DPRINTF(("ehci_waitintr: timeout\n")); 1047 xfer->status = USBD_TIMEOUT; 1048 usb_transfer_complete(xfer); 1049 /* XXX should free TD */ 1050 } 1051 1052 void 1053 ehci_poll(struct usbd_bus *bus) 1054 { 1055 ehci_softc_t *sc = bus->hci_private; 1056 #ifdef EHCI_DEBUG 1057 static int last; 1058 int new; 1059 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1060 if (new != last) { 1061 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1062 last = new; 1063 } 1064 #endif 1065 1066 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1067 ehci_intr1(sc); 1068 } 1069 1070 void 1071 ehci_childdet(device_t self, device_t child) 1072 { 1073 struct ehci_softc *sc = device_private(self); 1074 1075 KASSERT(sc->sc_child == child); 1076 sc->sc_child = NULL; 1077 } 1078 1079 int 1080 ehci_detach(struct ehci_softc *sc, int flags) 1081 { 1082 int rv = 0; 1083 1084 if (sc->sc_child != NULL) 1085 rv = config_detach(sc->sc_child, flags); 1086 1087 if (rv != 0) 1088 return (rv); 1089 1090 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc); 1091 1092 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1093 1094 /* XXX free other data structures XXX */ 1095 mutex_destroy(&sc->sc_doorbell_lock); 1096 mutex_destroy(&sc->sc_intrhead_lock); 1097 1098 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1099 1100 return (rv); 1101 } 1102 1103 1104 int 1105 ehci_activate(device_t self, enum devact act) 1106 { 1107 struct ehci_softc *sc = device_private(self); 1108 int rv = 0; 1109 1110 switch (act) { 1111 case DVACT_ACTIVATE: 1112 return (EOPNOTSUPP); 1113 1114 case DVACT_DEACTIVATE: 1115 sc->sc_dying = 1; 1116 if (sc->sc_child != NULL) 1117 rv = config_deactivate(sc->sc_child); 1118 break; 1119 } 1120 return (rv); 1121 } 1122 1123 /* 1124 * Handle suspend/resume. 1125 * 1126 * We need to switch to polling mode here, because this routine is 1127 * called from an interrupt context. This is all right since we 1128 * are almost suspended anyway. 1129 * 1130 * Note that this power handler isn't to be registered directly; the 1131 * bus glue needs to call out to it. 1132 */ 1133 bool 1134 ehci_suspend(device_t dv PMF_FN_ARGS) 1135 { 1136 ehci_softc_t *sc = device_private(dv); 1137 int i, s; 1138 uint32_t cmd, hcr; 1139 1140 s = splhardusb(); 1141 1142 sc->sc_bus.use_polling++; 1143 1144 for (i = 1; i <= sc->sc_noport; i++) { 1145 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1146 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1147 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1148 } 1149 1150 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1151 1152 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1153 EOWRITE4(sc, EHCI_USBCMD, cmd); 1154 1155 for (i = 0; i < 100; i++) { 1156 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1157 if (hcr == 0) 1158 break; 1159 1160 usb_delay_ms(&sc->sc_bus, 1); 1161 } 1162 if (hcr != 0) 1163 printf("%s: reset timeout\n", device_xname(dv)); 1164 1165 cmd &= ~EHCI_CMD_RS; 1166 EOWRITE4(sc, EHCI_USBCMD, cmd); 1167 1168 for (i = 0; i < 100; i++) { 1169 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1170 if (hcr == EHCI_STS_HCH) 1171 break; 1172 1173 usb_delay_ms(&sc->sc_bus, 1); 1174 } 1175 if (hcr != EHCI_STS_HCH) 1176 printf("%s: config timeout\n", device_xname(dv)); 1177 1178 sc->sc_bus.use_polling--; 1179 splx(s); 1180 1181 return true; 1182 } 1183 1184 bool 1185 ehci_resume(device_t dv PMF_FN_ARGS) 1186 { 1187 ehci_softc_t *sc = device_private(dv); 1188 int i; 1189 uint32_t cmd, hcr; 1190 1191 /* restore things in case the bios sucks */ 1192 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1193 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1194 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1195 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1196 1197 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1198 1199 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1200 1201 hcr = 0; 1202 for (i = 1; i <= sc->sc_noport; i++) { 1203 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1204 if ((cmd & EHCI_PS_PO) == 0 && 1205 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1206 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1207 hcr = 1; 1208 } 1209 } 1210 1211 if (hcr) { 1212 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1213 1214 for (i = 1; i <= sc->sc_noport; i++) { 1215 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1216 if ((cmd & EHCI_PS_PO) == 0 && 1217 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1218 EOWRITE4(sc, EHCI_PORTSC(i), 1219 cmd & ~EHCI_PS_FPR); 1220 } 1221 } 1222 1223 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1224 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1225 1226 for (i = 0; i < 100; i++) { 1227 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1228 if (hcr != EHCI_STS_HCH) 1229 break; 1230 1231 usb_delay_ms(&sc->sc_bus, 1); 1232 } 1233 if (hcr == EHCI_STS_HCH) 1234 printf("%s: config timeout\n", device_xname(dv)); 1235 1236 return true; 1237 } 1238 1239 /* 1240 * Shut down the controller when the system is going down. 1241 */ 1242 bool 1243 ehci_shutdown(device_t self, int flags) 1244 { 1245 ehci_softc_t *sc = device_private(self); 1246 1247 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1248 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1249 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1250 return true; 1251 } 1252 1253 usbd_status 1254 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1255 { 1256 struct ehci_softc *sc = bus->hci_private; 1257 usbd_status err; 1258 1259 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1260 if (err == USBD_NOMEM) 1261 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1262 #ifdef EHCI_DEBUG 1263 if (err) 1264 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1265 #endif 1266 return (err); 1267 } 1268 1269 void 1270 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1271 { 1272 struct ehci_softc *sc = bus->hci_private; 1273 1274 if (dma->block->flags & USB_DMA_RESERVE) { 1275 usb_reserve_freem(&sc->sc_dma_reserve, 1276 dma); 1277 return; 1278 } 1279 usb_freemem(&sc->sc_bus, dma); 1280 } 1281 1282 usbd_xfer_handle 1283 ehci_allocx(struct usbd_bus *bus) 1284 { 1285 struct ehci_softc *sc = bus->hci_private; 1286 usbd_xfer_handle xfer; 1287 1288 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1289 if (xfer != NULL) { 1290 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1291 #ifdef DIAGNOSTIC 1292 if (xfer->busy_free != XFER_FREE) { 1293 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1294 xfer->busy_free); 1295 } 1296 #endif 1297 } else { 1298 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1299 } 1300 if (xfer != NULL) { 1301 memset(xfer, 0, sizeof(struct ehci_xfer)); 1302 #ifdef DIAGNOSTIC 1303 EXFER(xfer)->isdone = 1; 1304 xfer->busy_free = XFER_BUSY; 1305 #endif 1306 } 1307 return (xfer); 1308 } 1309 1310 void 1311 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1312 { 1313 struct ehci_softc *sc = bus->hci_private; 1314 1315 #ifdef DIAGNOSTIC 1316 if (xfer->busy_free != XFER_BUSY) { 1317 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1318 xfer->busy_free); 1319 } 1320 xfer->busy_free = XFER_FREE; 1321 if (!EXFER(xfer)->isdone) { 1322 printf("ehci_freex: !isdone\n"); 1323 } 1324 #endif 1325 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1326 } 1327 1328 Static void 1329 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1330 { 1331 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1332 1333 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1334 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1335 #ifdef EHCI_DEBUG 1336 if (ehcidebug) 1337 usbd_dump_pipe(pipe); 1338 #endif 1339 epipe->nexttoggle = 0; 1340 } 1341 1342 Static void 1343 ehci_noop(usbd_pipe_handle pipe) 1344 { 1345 } 1346 1347 #ifdef EHCI_DEBUG 1348 void 1349 ehci_dump_regs(ehci_softc_t *sc) 1350 { 1351 int i; 1352 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1353 EOREAD4(sc, EHCI_USBCMD), 1354 EOREAD4(sc, EHCI_USBSTS), 1355 EOREAD4(sc, EHCI_USBINTR)); 1356 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1357 EOREAD4(sc, EHCI_FRINDEX), 1358 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1359 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1360 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1361 for (i = 1; i <= sc->sc_noport; i++) 1362 printf("port %d status=0x%08x\n", i, 1363 EOREAD4(sc, EHCI_PORTSC(i))); 1364 } 1365 1366 /* 1367 * Unused function - this is meant to be called from a kernel 1368 * debugger. 1369 */ 1370 void 1371 ehci_dump(void) 1372 { 1373 ehci_dump_regs(theehci); 1374 } 1375 1376 void 1377 ehci_dump_link(ehci_link_t link, int type) 1378 { 1379 link = le32toh(link); 1380 printf("0x%08x", link); 1381 if (link & EHCI_LINK_TERMINATE) 1382 printf("<T>"); 1383 else { 1384 printf("<"); 1385 if (type) { 1386 switch (EHCI_LINK_TYPE(link)) { 1387 case EHCI_LINK_ITD: printf("ITD"); break; 1388 case EHCI_LINK_QH: printf("QH"); break; 1389 case EHCI_LINK_SITD: printf("SITD"); break; 1390 case EHCI_LINK_FSTN: printf("FSTN"); break; 1391 } 1392 } 1393 printf(">"); 1394 } 1395 } 1396 1397 void 1398 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1399 { 1400 int i; 1401 u_int32_t stop; 1402 1403 stop = 0; 1404 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1405 ehci_dump_sqtd(sqtd); 1406 usb_syncmem(&sqtd->dma, 1407 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1408 sizeof(sqtd->qtd), 1409 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1410 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1411 usb_syncmem(&sqtd->dma, 1412 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1413 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1414 } 1415 if (sqtd) 1416 printf("dump aborted, too many TDs\n"); 1417 } 1418 1419 void 1420 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1421 { 1422 usb_syncmem(&sqtd->dma, sqtd->offs, 1423 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1424 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1425 ehci_dump_qtd(&sqtd->qtd); 1426 usb_syncmem(&sqtd->dma, sqtd->offs, 1427 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1428 } 1429 1430 void 1431 ehci_dump_qtd(ehci_qtd_t *qtd) 1432 { 1433 u_int32_t s; 1434 char sbuf[128]; 1435 1436 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1437 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1438 printf("\n"); 1439 s = le32toh(qtd->qtd_status); 1440 snprintb(sbuf, sizeof(sbuf), 1441 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1442 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1443 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1444 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1445 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1446 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1447 EHCI_QTD_GET_PID(s), sbuf); 1448 for (s = 0; s < 5; s++) 1449 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1450 } 1451 1452 void 1453 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1454 { 1455 ehci_qh_t *qh = &sqh->qh; 1456 u_int32_t endp, endphub; 1457 1458 usb_syncmem(&sqh->dma, sqh->offs, 1459 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1460 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1461 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1462 endp = le32toh(qh->qh_endp); 1463 printf(" endp=0x%08x\n", endp); 1464 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1465 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1466 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1467 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1468 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1469 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1470 EHCI_QH_GET_NRL(endp)); 1471 endphub = le32toh(qh->qh_endphub); 1472 printf(" endphub=0x%08x\n", endphub); 1473 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1474 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1475 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1476 EHCI_QH_GET_MULT(endphub)); 1477 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1478 printf("Overlay qTD:\n"); 1479 ehci_dump_qtd(&qh->qh_qtd); 1480 usb_syncmem(&sqh->dma, sqh->offs, 1481 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1482 } 1483 1484 #if notyet 1485 void 1486 ehci_dump_itd(struct ehci_soft_itd *itd) 1487 { 1488 ehci_isoc_trans_t t; 1489 ehci_isoc_bufr_ptr_t b, b2, b3; 1490 int i; 1491 1492 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1493 1494 for (i = 0; i < 8;i++) { 1495 t = le32toh(itd->itd.itd_ctl[i]); 1496 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1497 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1498 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1499 EHCI_ITD_GET_OFFS(t)); 1500 } 1501 printf("ITDbufr: "); 1502 for (i = 0; i < 7; i++) 1503 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1504 1505 b = le32toh(itd->itd.itd_bufr[0]); 1506 b2 = le32toh(itd->itd.itd_bufr[1]); 1507 b3 = le32toh(itd->itd.itd_bufr[2]); 1508 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1509 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1510 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1511 } 1512 1513 void 1514 ehci_dump_sitd(struct ehci_soft_itd *itd) 1515 { 1516 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1517 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1518 itd->xfer_next, itd->physaddr, itd->slot); 1519 } 1520 #endif 1521 1522 #ifdef DIAGNOSTIC 1523 void 1524 ehci_dump_exfer(struct ehci_xfer *ex) 1525 { 1526 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1527 } 1528 #endif 1529 #endif 1530 1531 usbd_status 1532 ehci_open(usbd_pipe_handle pipe) 1533 { 1534 usbd_device_handle dev = pipe->device; 1535 ehci_softc_t *sc = dev->bus->hci_private; 1536 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1537 u_int8_t addr = dev->address; 1538 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1539 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1540 ehci_soft_qh_t *sqh; 1541 usbd_status err; 1542 int s; 1543 int ival, speed, naks; 1544 int hshubaddr, hshubport; 1545 1546 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1547 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1548 1549 if (dev->myhsport) { 1550 hshubaddr = dev->myhsport->parent->address; 1551 hshubport = dev->myhsport->portno; 1552 } else { 1553 hshubaddr = 0; 1554 hshubport = 0; 1555 } 1556 1557 if (sc->sc_dying) 1558 return (USBD_IOERROR); 1559 1560 epipe->nexttoggle = 0; 1561 1562 if (addr == sc->sc_addr) { 1563 switch (ed->bEndpointAddress) { 1564 case USB_CONTROL_ENDPOINT: 1565 pipe->methods = &ehci_root_ctrl_methods; 1566 break; 1567 case UE_DIR_IN | EHCI_INTR_ENDPT: 1568 pipe->methods = &ehci_root_intr_methods; 1569 break; 1570 default: 1571 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1572 ed->bEndpointAddress)); 1573 return (USBD_INVAL); 1574 } 1575 return (USBD_NORMAL_COMPLETION); 1576 } 1577 1578 /* XXX All this stuff is only valid for async. */ 1579 switch (dev->speed) { 1580 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1581 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1582 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1583 default: panic("ehci_open: bad device speed %d", dev->speed); 1584 } 1585 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1586 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1587 "isoc endpoint.\n"); 1588 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1589 "attached to a USB2 hub, and transaction translations are " 1590 "not yet supported.\n"); 1591 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1592 "root hub instead.\n"); 1593 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1594 hshubaddr, hshubport)); 1595 return USBD_INVAL; 1596 } 1597 1598 naks = 8; /* XXX */ 1599 1600 /* Allocate sqh for everything, save isoc xfers */ 1601 if (xfertype != UE_ISOCHRONOUS) { 1602 sqh = ehci_alloc_sqh(sc); 1603 if (sqh == NULL) 1604 return (USBD_NOMEM); 1605 /* qh_link filled when the QH is added */ 1606 sqh->qh.qh_endp = htole32( 1607 EHCI_QH_SET_ADDR(addr) | 1608 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1609 EHCI_QH_SET_EPS(speed) | 1610 EHCI_QH_DTC | 1611 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1612 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1613 EHCI_QH_CTL : 0) | 1614 EHCI_QH_SET_NRL(naks) 1615 ); 1616 sqh->qh.qh_endphub = htole32( 1617 EHCI_QH_SET_MULT(1) | 1618 EHCI_QH_SET_HUBA(hshubaddr) | 1619 EHCI_QH_SET_PORT(hshubport) | 1620 EHCI_QH_SET_CMASK(0x08) | /* XXX */ 1621 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1622 ); 1623 sqh->qh.qh_curqtd = EHCI_NULL; 1624 /* Fill the overlay qTD */ 1625 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1626 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1627 sqh->qh.qh_qtd.qtd_status = htole32(0); 1628 1629 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1630 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1631 epipe->sqh = sqh; 1632 } else { 1633 sqh = NULL; 1634 } /*xfertype == UE_ISOC*/ 1635 1636 switch (xfertype) { 1637 case UE_CONTROL: 1638 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1639 0, &epipe->u.ctl.reqdma); 1640 #ifdef EHCI_DEBUG 1641 if (err) 1642 printf("ehci_open: usb_allocmem()=%d\n", err); 1643 #endif 1644 if (err) 1645 goto bad; 1646 pipe->methods = &ehci_device_ctrl_methods; 1647 s = splusb(); 1648 ehci_add_qh(sqh, sc->sc_async_head); 1649 splx(s); 1650 break; 1651 case UE_BULK: 1652 pipe->methods = &ehci_device_bulk_methods; 1653 s = splusb(); 1654 ehci_add_qh(sqh, sc->sc_async_head); 1655 splx(s); 1656 break; 1657 case UE_INTERRUPT: 1658 pipe->methods = &ehci_device_intr_methods; 1659 ival = pipe->interval; 1660 if (ival == USBD_DEFAULT_INTERVAL) { 1661 if (speed == EHCI_QH_SPEED_HIGH) { 1662 if (ed->bInterval > 16) { 1663 /* 1664 * illegal with high-speed, but there 1665 * were documentation bugs in the spec, 1666 * so be generous 1667 */ 1668 ival = 256; 1669 } else 1670 ival = (1 << (ed->bInterval - 1)) / 8; 1671 } else 1672 ival = ed->bInterval; 1673 } 1674 err = ehci_device_setintr(sc, sqh, ival); 1675 if (err) 1676 goto bad; 1677 break; 1678 case UE_ISOCHRONOUS: 1679 pipe->methods = &ehci_device_isoc_methods; 1680 if (ed->bInterval == 0 || ed->bInterval > 16) { 1681 printf("ehci: opening pipe with invalid bInterval\n"); 1682 err = USBD_INVAL; 1683 goto bad; 1684 } 1685 if (UGETW(ed->wMaxPacketSize) == 0) { 1686 printf("ehci: zero length endpoint open request\n"); 1687 err = USBD_INVAL; 1688 goto bad; 1689 } 1690 epipe->u.isoc.next_frame = 0; 1691 epipe->u.isoc.cur_xfers = 0; 1692 break; 1693 default: 1694 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1695 err = USBD_INVAL; 1696 goto bad; 1697 } 1698 return (USBD_NORMAL_COMPLETION); 1699 1700 bad: 1701 if (sqh != NULL) 1702 ehci_free_sqh(sc, sqh); 1703 return (err); 1704 } 1705 1706 /* 1707 * Add an ED to the schedule. Called at splusb(). 1708 */ 1709 void 1710 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1711 { 1712 SPLUSBCHECK; 1713 1714 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1715 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1716 sqh->next = head->next; 1717 sqh->qh.qh_link = head->qh.qh_link; 1718 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1719 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1720 head->next = sqh; 1721 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1722 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1723 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1724 1725 #ifdef EHCI_DEBUG 1726 if (ehcidebug > 5) { 1727 printf("ehci_add_qh:\n"); 1728 ehci_dump_sqh(sqh); 1729 } 1730 #endif 1731 } 1732 1733 /* 1734 * Remove an ED from the schedule. Called at splusb(). 1735 */ 1736 void 1737 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1738 { 1739 ehci_soft_qh_t *p; 1740 1741 SPLUSBCHECK; 1742 /* XXX */ 1743 for (p = head; p != NULL && p->next != sqh; p = p->next) 1744 ; 1745 if (p == NULL) 1746 panic("ehci_rem_qh: ED not found"); 1747 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1748 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1749 p->next = sqh->next; 1750 p->qh.qh_link = sqh->qh.qh_link; 1751 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1752 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1753 1754 ehci_sync_hc(sc); 1755 } 1756 1757 void 1758 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1759 { 1760 int i; 1761 u_int32_t status; 1762 1763 /* Save toggle bit and ping status. */ 1764 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1765 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1766 status = sqh->qh.qh_qtd.qtd_status & 1767 htole32(EHCI_QTD_TOGGLE_MASK | 1768 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1769 /* Set HALTED to make hw leave it alone. */ 1770 sqh->qh.qh_qtd.qtd_status = 1771 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1772 usb_syncmem(&sqh->dma, 1773 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1774 sizeof(sqh->qh.qh_qtd.qtd_status), 1775 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1776 sqh->qh.qh_curqtd = 0; 1777 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1778 sqh->qh.qh_qtd.qtd_altnext = 0; 1779 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1780 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1781 sqh->sqtd = sqtd; 1782 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1783 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1784 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1785 sqh->qh.qh_qtd.qtd_status = status; 1786 usb_syncmem(&sqh->dma, 1787 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1788 sizeof(sqh->qh.qh_qtd.qtd_status), 1789 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1790 } 1791 1792 /* 1793 * Ensure that the HC has released all references to the QH. We do this 1794 * by asking for a Async Advance Doorbell interrupt and then we wait for 1795 * the interrupt. 1796 * To make this easier we first obtain exclusive use of the doorbell. 1797 */ 1798 void 1799 ehci_sync_hc(ehci_softc_t *sc) 1800 { 1801 int s, error; 1802 1803 if (sc->sc_dying) { 1804 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1805 return; 1806 } 1807 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1808 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */ 1809 s = splhardusb(); 1810 /* ask for doorbell */ 1811 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1812 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1813 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1814 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1815 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1816 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1817 splx(s); 1818 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */ 1819 #ifdef DIAGNOSTIC 1820 if (error) 1821 printf("ehci_sync_hc: tsleep() = %d\n", error); 1822 #endif 1823 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1824 } 1825 1826 /*Call at splusb*/ 1827 void 1828 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1829 { 1830 struct ehci_soft_itd *itd, *prev; 1831 1832 prev = NULL; 1833 1834 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1835 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1836 1837 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1838 prev = itd->u.frame_list.prev; 1839 /* Unlink itd from hardware chain, or frame array */ 1840 if (prev == NULL) { /* We're at the table head */ 1841 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1842 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1843 usb_syncmem(&sc->sc_fldma, 1844 sizeof(ehci_link_t) * itd->slot, 1845 sizeof(ehci_link_t), 1846 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1847 1848 if (itd->u.frame_list.next != NULL) 1849 itd->u.frame_list.next->u.frame_list.prev = NULL; 1850 } else { 1851 /* XXX this part is untested... */ 1852 prev->itd.itd_next = itd->itd.itd_next; 1853 usb_syncmem(&itd->dma, 1854 itd->offs + offsetof(ehci_itd_t, itd_next), 1855 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1856 1857 prev->u.frame_list.next = itd->u.frame_list.next; 1858 if (itd->u.frame_list.next != NULL) 1859 itd->u.frame_list.next->u.frame_list.prev = prev; 1860 } 1861 } 1862 1863 prev = NULL; 1864 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1865 if (prev != NULL) 1866 ehci_free_itd(sc, prev); 1867 prev = itd; 1868 } 1869 if (prev) 1870 ehci_free_itd(sc, prev); 1871 exfer->itdstart = NULL; 1872 exfer->itdend = NULL; 1873 } 1874 1875 /***********/ 1876 1877 /* 1878 * Data structures and routines to emulate the root hub. 1879 */ 1880 Static usb_device_descriptor_t ehci_devd = { 1881 USB_DEVICE_DESCRIPTOR_SIZE, 1882 UDESC_DEVICE, /* type */ 1883 {0x00, 0x02}, /* USB version */ 1884 UDCLASS_HUB, /* class */ 1885 UDSUBCLASS_HUB, /* subclass */ 1886 UDPROTO_HSHUBSTT, /* protocol */ 1887 64, /* max packet */ 1888 {0},{0},{0x00,0x01}, /* device id */ 1889 1,2,0, /* string indicies */ 1890 1 /* # of configurations */ 1891 }; 1892 1893 Static const usb_device_qualifier_t ehci_odevd = { 1894 USB_DEVICE_DESCRIPTOR_SIZE, 1895 UDESC_DEVICE_QUALIFIER, /* type */ 1896 {0x00, 0x02}, /* USB version */ 1897 UDCLASS_HUB, /* class */ 1898 UDSUBCLASS_HUB, /* subclass */ 1899 UDPROTO_FSHUB, /* protocol */ 1900 64, /* max packet */ 1901 1, /* # of configurations */ 1902 0 1903 }; 1904 1905 Static const usb_config_descriptor_t ehci_confd = { 1906 USB_CONFIG_DESCRIPTOR_SIZE, 1907 UDESC_CONFIG, 1908 {USB_CONFIG_DESCRIPTOR_SIZE + 1909 USB_INTERFACE_DESCRIPTOR_SIZE + 1910 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1911 1, 1912 1, 1913 0, 1914 UC_ATTR_MBO | UC_SELF_POWERED, 1915 0 /* max power */ 1916 }; 1917 1918 Static const usb_interface_descriptor_t ehci_ifcd = { 1919 USB_INTERFACE_DESCRIPTOR_SIZE, 1920 UDESC_INTERFACE, 1921 0, 1922 0, 1923 1, 1924 UICLASS_HUB, 1925 UISUBCLASS_HUB, 1926 UIPROTO_HSHUBSTT, 1927 0 1928 }; 1929 1930 Static const usb_endpoint_descriptor_t ehci_endpd = { 1931 USB_ENDPOINT_DESCRIPTOR_SIZE, 1932 UDESC_ENDPOINT, 1933 UE_DIR_IN | EHCI_INTR_ENDPT, 1934 UE_INTERRUPT, 1935 {8, 0}, /* max packet */ 1936 12 1937 }; 1938 1939 Static const usb_hub_descriptor_t ehci_hubd = { 1940 USB_HUB_DESCRIPTOR_SIZE, 1941 UDESC_HUB, 1942 0, 1943 {0,0}, 1944 0, 1945 0, 1946 {""}, 1947 {""}, 1948 }; 1949 1950 /* 1951 * Simulate a hardware hub by handling all the necessary requests. 1952 */ 1953 Static usbd_status 1954 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1955 { 1956 usbd_status err; 1957 1958 /* Insert last in queue. */ 1959 err = usb_insert_transfer(xfer); 1960 if (err) 1961 return (err); 1962 1963 /* Pipe isn't running, start first */ 1964 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1965 } 1966 1967 Static usbd_status 1968 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1969 { 1970 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1971 usb_device_request_t *req; 1972 void *buf = NULL; 1973 int port, i; 1974 int s, len, value, index, l, totlen = 0; 1975 usb_port_status_t ps; 1976 usb_hub_descriptor_t hubd; 1977 usbd_status err; 1978 u_int32_t v; 1979 1980 if (sc->sc_dying) 1981 return (USBD_IOERROR); 1982 1983 #ifdef DIAGNOSTIC 1984 if (!(xfer->rqflags & URQ_REQUEST)) 1985 /* XXX panic */ 1986 return (USBD_INVAL); 1987 #endif 1988 req = &xfer->request; 1989 1990 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1991 req->bmRequestType, req->bRequest)); 1992 1993 len = UGETW(req->wLength); 1994 value = UGETW(req->wValue); 1995 index = UGETW(req->wIndex); 1996 1997 if (len != 0) 1998 buf = KERNADDR(&xfer->dmabuf, 0); 1999 2000 #define C(x,y) ((x) | ((y) << 8)) 2001 switch(C(req->bRequest, req->bmRequestType)) { 2002 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2003 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2004 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2005 /* 2006 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2007 * for the integrated root hub. 2008 */ 2009 break; 2010 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2011 if (len > 0) { 2012 *(u_int8_t *)buf = sc->sc_conf; 2013 totlen = 1; 2014 } 2015 break; 2016 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2017 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2018 if (len == 0) 2019 break; 2020 switch(value >> 8) { 2021 case UDESC_DEVICE: 2022 if ((value & 0xff) != 0) { 2023 err = USBD_IOERROR; 2024 goto ret; 2025 } 2026 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2027 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2028 memcpy(buf, &ehci_devd, l); 2029 break; 2030 /* 2031 * We can't really operate at another speed, but the spec says 2032 * we need this descriptor. 2033 */ 2034 case UDESC_DEVICE_QUALIFIER: 2035 if ((value & 0xff) != 0) { 2036 err = USBD_IOERROR; 2037 goto ret; 2038 } 2039 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2040 memcpy(buf, &ehci_odevd, l); 2041 break; 2042 /* 2043 * We can't really operate at another speed, but the spec says 2044 * we need this descriptor. 2045 */ 2046 case UDESC_OTHER_SPEED_CONFIGURATION: 2047 case UDESC_CONFIG: 2048 if ((value & 0xff) != 0) { 2049 err = USBD_IOERROR; 2050 goto ret; 2051 } 2052 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2053 memcpy(buf, &ehci_confd, l); 2054 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2055 value >> 8; 2056 buf = (char *)buf + l; 2057 len -= l; 2058 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2059 totlen += l; 2060 memcpy(buf, &ehci_ifcd, l); 2061 buf = (char *)buf + l; 2062 len -= l; 2063 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2064 totlen += l; 2065 memcpy(buf, &ehci_endpd, l); 2066 break; 2067 case UDESC_STRING: 2068 #define sd ((usb_string_descriptor_t *)buf) 2069 switch (value & 0xff) { 2070 case 0: /* Language table */ 2071 totlen = usb_makelangtbl(sd, len); 2072 break; 2073 case 1: /* Vendor */ 2074 totlen = usb_makestrdesc(sd, len, 2075 sc->sc_vendor); 2076 break; 2077 case 2: /* Product */ 2078 totlen = usb_makestrdesc(sd, len, 2079 "EHCI root hub"); 2080 break; 2081 } 2082 #undef sd 2083 break; 2084 default: 2085 err = USBD_IOERROR; 2086 goto ret; 2087 } 2088 break; 2089 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2090 if (len > 0) { 2091 *(u_int8_t *)buf = 0; 2092 totlen = 1; 2093 } 2094 break; 2095 case C(UR_GET_STATUS, UT_READ_DEVICE): 2096 if (len > 1) { 2097 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2098 totlen = 2; 2099 } 2100 break; 2101 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2102 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2103 if (len > 1) { 2104 USETW(((usb_status_t *)buf)->wStatus, 0); 2105 totlen = 2; 2106 } 2107 break; 2108 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2109 if (value >= USB_MAX_DEVICES) { 2110 err = USBD_IOERROR; 2111 goto ret; 2112 } 2113 sc->sc_addr = value; 2114 break; 2115 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2116 if (value != 0 && value != 1) { 2117 err = USBD_IOERROR; 2118 goto ret; 2119 } 2120 sc->sc_conf = value; 2121 break; 2122 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2123 break; 2124 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2125 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2126 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2127 err = USBD_IOERROR; 2128 goto ret; 2129 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2130 break; 2131 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2132 break; 2133 /* Hub requests */ 2134 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2135 break; 2136 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2137 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2138 "port=%d feature=%d\n", 2139 index, value)); 2140 if (index < 1 || index > sc->sc_noport) { 2141 err = USBD_IOERROR; 2142 goto ret; 2143 } 2144 port = EHCI_PORTSC(index); 2145 v = EOREAD4(sc, port); 2146 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2147 v &= ~EHCI_PS_CLEAR; 2148 switch(value) { 2149 case UHF_PORT_ENABLE: 2150 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2151 break; 2152 case UHF_PORT_SUSPEND: 2153 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2154 break; 2155 v &= ~EHCI_PS_SUSP; 2156 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2157 /* see USB2 spec ch. 7.1.7.7 */ 2158 usb_delay_ms(&sc->sc_bus, 20); 2159 EOWRITE4(sc, port, v); 2160 usb_delay_ms(&sc->sc_bus, 2); 2161 #ifdef DEBUG 2162 v = EOREAD4(sc, port); 2163 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2164 printf("ehci: resume failed: %x\n", v); 2165 #endif 2166 break; 2167 case UHF_PORT_POWER: 2168 if (sc->sc_hasppc) 2169 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2170 break; 2171 case UHF_PORT_TEST: 2172 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2173 "%d\n", index)); 2174 break; 2175 case UHF_PORT_INDICATOR: 2176 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2177 "%d\n", index)); 2178 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2179 break; 2180 case UHF_C_PORT_CONNECTION: 2181 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2182 break; 2183 case UHF_C_PORT_ENABLE: 2184 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2185 break; 2186 case UHF_C_PORT_SUSPEND: 2187 /* how? */ 2188 break; 2189 case UHF_C_PORT_OVER_CURRENT: 2190 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2191 break; 2192 case UHF_C_PORT_RESET: 2193 sc->sc_isreset[index] = 0; 2194 break; 2195 default: 2196 err = USBD_IOERROR; 2197 goto ret; 2198 } 2199 #if 0 2200 switch(value) { 2201 case UHF_C_PORT_CONNECTION: 2202 case UHF_C_PORT_ENABLE: 2203 case UHF_C_PORT_SUSPEND: 2204 case UHF_C_PORT_OVER_CURRENT: 2205 case UHF_C_PORT_RESET: 2206 default: 2207 break; 2208 } 2209 #endif 2210 break; 2211 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2212 if (len == 0) 2213 break; 2214 if ((value & 0xff) != 0) { 2215 err = USBD_IOERROR; 2216 goto ret; 2217 } 2218 hubd = ehci_hubd; 2219 hubd.bNbrPorts = sc->sc_noport; 2220 v = EOREAD4(sc, EHCI_HCSPARAMS); 2221 USETW(hubd.wHubCharacteristics, 2222 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2223 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2224 ? UHD_PORT_IND : 0); 2225 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2226 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2227 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2228 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2229 l = min(len, hubd.bDescLength); 2230 totlen = l; 2231 memcpy(buf, &hubd, l); 2232 break; 2233 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2234 if (len != 4) { 2235 err = USBD_IOERROR; 2236 goto ret; 2237 } 2238 memset(buf, 0, len); /* ? XXX */ 2239 totlen = len; 2240 break; 2241 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2242 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2243 index)); 2244 if (index < 1 || index > sc->sc_noport) { 2245 err = USBD_IOERROR; 2246 goto ret; 2247 } 2248 if (len != 4) { 2249 err = USBD_IOERROR; 2250 goto ret; 2251 } 2252 v = EOREAD4(sc, EHCI_PORTSC(index)); 2253 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2254 v)); 2255 i = UPS_HIGH_SPEED; 2256 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2257 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2258 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2259 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2260 if (v & EHCI_PS_PR) i |= UPS_RESET; 2261 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2262 USETW(ps.wPortStatus, i); 2263 i = 0; 2264 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2265 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2266 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2267 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2268 USETW(ps.wPortChange, i); 2269 l = min(len, sizeof ps); 2270 memcpy(buf, &ps, l); 2271 totlen = l; 2272 break; 2273 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2274 err = USBD_IOERROR; 2275 goto ret; 2276 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2277 break; 2278 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2279 if (index < 1 || index > sc->sc_noport) { 2280 err = USBD_IOERROR; 2281 goto ret; 2282 } 2283 port = EHCI_PORTSC(index); 2284 v = EOREAD4(sc, port); 2285 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2286 v &= ~EHCI_PS_CLEAR; 2287 switch(value) { 2288 case UHF_PORT_ENABLE: 2289 EOWRITE4(sc, port, v | EHCI_PS_PE); 2290 break; 2291 case UHF_PORT_SUSPEND: 2292 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2293 break; 2294 case UHF_PORT_RESET: 2295 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2296 index)); 2297 if (EHCI_PS_IS_LOWSPEED(v)) { 2298 /* Low speed device, give up ownership. */ 2299 ehci_disown(sc, index, 1); 2300 break; 2301 } 2302 /* Start reset sequence. */ 2303 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2304 EOWRITE4(sc, port, v | EHCI_PS_PR); 2305 /* Wait for reset to complete. */ 2306 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2307 if (sc->sc_dying) { 2308 err = USBD_IOERROR; 2309 goto ret; 2310 } 2311 /* Terminate reset sequence. */ 2312 EOWRITE4(sc, port, v); 2313 /* Wait for HC to complete reset. */ 2314 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2315 if (sc->sc_dying) { 2316 err = USBD_IOERROR; 2317 goto ret; 2318 } 2319 v = EOREAD4(sc, port); 2320 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2321 if (v & EHCI_PS_PR) { 2322 printf("%s: port reset timeout\n", 2323 device_xname(sc->sc_dev)); 2324 return (USBD_TIMEOUT); 2325 } 2326 if (!(v & EHCI_PS_PE)) { 2327 /* Not a high speed device, give up ownership.*/ 2328 ehci_disown(sc, index, 0); 2329 break; 2330 } 2331 sc->sc_isreset[index] = 1; 2332 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2333 index, v)); 2334 break; 2335 case UHF_PORT_POWER: 2336 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2337 "%d (has PPC = %d)\n", index, 2338 sc->sc_hasppc)); 2339 if (sc->sc_hasppc) 2340 EOWRITE4(sc, port, v | EHCI_PS_PP); 2341 break; 2342 case UHF_PORT_TEST: 2343 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2344 "%d\n", index)); 2345 break; 2346 case UHF_PORT_INDICATOR: 2347 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2348 "%d\n", index)); 2349 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2350 break; 2351 default: 2352 err = USBD_IOERROR; 2353 goto ret; 2354 } 2355 break; 2356 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2357 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2358 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2359 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2360 break; 2361 default: 2362 err = USBD_IOERROR; 2363 goto ret; 2364 } 2365 xfer->actlen = totlen; 2366 err = USBD_NORMAL_COMPLETION; 2367 ret: 2368 xfer->status = err; 2369 s = splusb(); 2370 usb_transfer_complete(xfer); 2371 splx(s); 2372 return (USBD_IN_PROGRESS); 2373 } 2374 2375 void 2376 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2377 { 2378 int port; 2379 u_int32_t v; 2380 2381 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2382 #ifdef DIAGNOSTIC 2383 if (sc->sc_npcomp != 0) { 2384 int i = (index-1) / sc->sc_npcomp; 2385 if (i >= sc->sc_ncomp) 2386 printf("%s: strange port\n", 2387 device_xname(sc->sc_dev)); 2388 else 2389 printf("%s: handing over %s speed device on " 2390 "port %d to %s\n", 2391 device_xname(sc->sc_dev), 2392 lowspeed ? "low" : "full", 2393 index, device_xname(sc->sc_comps[i])); 2394 } else { 2395 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2396 } 2397 #endif 2398 port = EHCI_PORTSC(index); 2399 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2400 EOWRITE4(sc, port, v | EHCI_PS_PO); 2401 } 2402 2403 /* Abort a root control request. */ 2404 Static void 2405 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2406 { 2407 /* Nothing to do, all transfers are synchronous. */ 2408 } 2409 2410 /* Close the root pipe. */ 2411 Static void 2412 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2413 { 2414 DPRINTF(("ehci_root_ctrl_close\n")); 2415 /* Nothing to do. */ 2416 } 2417 2418 void 2419 ehci_root_intr_done(usbd_xfer_handle xfer) 2420 { 2421 xfer->hcpriv = NULL; 2422 } 2423 2424 Static usbd_status 2425 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2426 { 2427 usbd_status err; 2428 2429 /* Insert last in queue. */ 2430 err = usb_insert_transfer(xfer); 2431 if (err) 2432 return (err); 2433 2434 /* Pipe isn't running, start first */ 2435 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2436 } 2437 2438 Static usbd_status 2439 ehci_root_intr_start(usbd_xfer_handle xfer) 2440 { 2441 usbd_pipe_handle pipe = xfer->pipe; 2442 ehci_softc_t *sc = pipe->device->bus->hci_private; 2443 2444 if (sc->sc_dying) 2445 return (USBD_IOERROR); 2446 2447 sc->sc_intrxfer = xfer; 2448 2449 return (USBD_IN_PROGRESS); 2450 } 2451 2452 /* Abort a root interrupt request. */ 2453 Static void 2454 ehci_root_intr_abort(usbd_xfer_handle xfer) 2455 { 2456 int s; 2457 2458 if (xfer->pipe->intrxfer == xfer) { 2459 DPRINTF(("ehci_root_intr_abort: remove\n")); 2460 xfer->pipe->intrxfer = NULL; 2461 } 2462 xfer->status = USBD_CANCELLED; 2463 s = splusb(); 2464 usb_transfer_complete(xfer); 2465 splx(s); 2466 } 2467 2468 /* Close the root pipe. */ 2469 Static void 2470 ehci_root_intr_close(usbd_pipe_handle pipe) 2471 { 2472 ehci_softc_t *sc = pipe->device->bus->hci_private; 2473 2474 DPRINTF(("ehci_root_intr_close\n")); 2475 2476 sc->sc_intrxfer = NULL; 2477 } 2478 2479 void 2480 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2481 { 2482 xfer->hcpriv = NULL; 2483 } 2484 2485 /************************/ 2486 2487 ehci_soft_qh_t * 2488 ehci_alloc_sqh(ehci_softc_t *sc) 2489 { 2490 ehci_soft_qh_t *sqh; 2491 usbd_status err; 2492 int i, offs; 2493 usb_dma_t dma; 2494 2495 if (sc->sc_freeqhs == NULL) { 2496 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2497 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2498 EHCI_PAGE_SIZE, &dma); 2499 #ifdef EHCI_DEBUG 2500 if (err) 2501 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2502 #endif 2503 if (err) 2504 return (NULL); 2505 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2506 offs = i * EHCI_SQH_SIZE; 2507 sqh = KERNADDR(&dma, offs); 2508 sqh->physaddr = DMAADDR(&dma, offs); 2509 sqh->dma = dma; 2510 sqh->offs = offs; 2511 sqh->next = sc->sc_freeqhs; 2512 sc->sc_freeqhs = sqh; 2513 } 2514 } 2515 sqh = sc->sc_freeqhs; 2516 sc->sc_freeqhs = sqh->next; 2517 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2518 sqh->next = NULL; 2519 return (sqh); 2520 } 2521 2522 void 2523 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2524 { 2525 sqh->next = sc->sc_freeqhs; 2526 sc->sc_freeqhs = sqh; 2527 } 2528 2529 ehci_soft_qtd_t * 2530 ehci_alloc_sqtd(ehci_softc_t *sc) 2531 { 2532 ehci_soft_qtd_t *sqtd; 2533 usbd_status err; 2534 int i, offs; 2535 usb_dma_t dma; 2536 int s; 2537 2538 if (sc->sc_freeqtds == NULL) { 2539 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2540 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2541 EHCI_PAGE_SIZE, &dma); 2542 #ifdef EHCI_DEBUG 2543 if (err) 2544 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2545 #endif 2546 if (err) 2547 return (NULL); 2548 s = splusb(); 2549 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2550 offs = i * EHCI_SQTD_SIZE; 2551 sqtd = KERNADDR(&dma, offs); 2552 sqtd->physaddr = DMAADDR(&dma, offs); 2553 sqtd->dma = dma; 2554 sqtd->offs = offs; 2555 sqtd->nextqtd = sc->sc_freeqtds; 2556 sc->sc_freeqtds = sqtd; 2557 } 2558 splx(s); 2559 } 2560 2561 s = splusb(); 2562 sqtd = sc->sc_freeqtds; 2563 sc->sc_freeqtds = sqtd->nextqtd; 2564 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2565 sqtd->nextqtd = NULL; 2566 sqtd->xfer = NULL; 2567 splx(s); 2568 2569 return (sqtd); 2570 } 2571 2572 void 2573 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2574 { 2575 int s; 2576 2577 s = splusb(); 2578 sqtd->nextqtd = sc->sc_freeqtds; 2579 sc->sc_freeqtds = sqtd; 2580 splx(s); 2581 } 2582 2583 usbd_status 2584 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2585 int alen, int rd, usbd_xfer_handle xfer, 2586 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2587 { 2588 ehci_soft_qtd_t *next, *cur; 2589 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2590 u_int32_t qtdstatus; 2591 int len, curlen, mps; 2592 int i, tog; 2593 usb_dma_t *dma = &xfer->dmabuf; 2594 u_int16_t flags = xfer->flags; 2595 2596 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2597 2598 len = alen; 2599 dataphys = DMAADDR(dma, 0); 2600 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2601 qtdstatus = EHCI_QTD_ACTIVE | 2602 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2603 EHCI_QTD_SET_CERR(3) 2604 /* IOC set below */ 2605 /* BYTES set below */ 2606 ; 2607 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2608 tog = epipe->nexttoggle; 2609 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2610 2611 cur = ehci_alloc_sqtd(sc); 2612 *sp = cur; 2613 if (cur == NULL) 2614 goto nomem; 2615 2616 usb_syncmem(dma, 0, alen, 2617 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2618 for (;;) { 2619 dataphyspage = EHCI_PAGE(dataphys); 2620 /* The EHCI hardware can handle at most 5 pages. */ 2621 if (dataphyslastpage - dataphyspage < 2622 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2623 /* we can handle it in this QTD */ 2624 curlen = len; 2625 } else { 2626 /* must use multiple TDs, fill as much as possible. */ 2627 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2628 EHCI_PAGE_OFFSET(dataphys); 2629 #ifdef DIAGNOSTIC 2630 if (curlen > len) { 2631 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2632 "len=0x%x offs=0x%x\n", curlen, len, 2633 EHCI_PAGE_OFFSET(dataphys)); 2634 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2635 dataphyslastpage, dataphyspage, 2636 dataphys); 2637 curlen = len; 2638 } 2639 #endif 2640 /* the length must be a multiple of the max size */ 2641 curlen -= curlen % mps; 2642 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2643 "curlen=%d\n", curlen)); 2644 #ifdef DIAGNOSTIC 2645 if (curlen == 0) 2646 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2647 #endif 2648 } 2649 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2650 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2651 dataphys, dataphyslastpage, 2652 len, curlen)); 2653 len -= curlen; 2654 2655 /* 2656 * Allocate another transfer if there's more data left, 2657 * or if force last short transfer flag is set and we're 2658 * allocating a multiple of the max packet size. 2659 */ 2660 if (len != 0 || 2661 ((curlen % mps) == 0 && !rd && curlen != 0 && 2662 (flags & USBD_FORCE_SHORT_XFER))) { 2663 next = ehci_alloc_sqtd(sc); 2664 if (next == NULL) 2665 goto nomem; 2666 nextphys = htole32(next->physaddr); 2667 } else { 2668 next = NULL; 2669 nextphys = EHCI_NULL; 2670 } 2671 2672 for (i = 0; i * EHCI_PAGE_SIZE < 2673 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2674 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2675 if (i != 0) /* use offset only in first buffer */ 2676 a = EHCI_PAGE(a); 2677 cur->qtd.qtd_buffer[i] = htole32(a); 2678 cur->qtd.qtd_buffer_hi[i] = 0; 2679 #ifdef DIAGNOSTIC 2680 if (i >= EHCI_QTD_NBUFFERS) { 2681 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2682 goto nomem; 2683 } 2684 #endif 2685 } 2686 cur->nextqtd = next; 2687 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2688 cur->qtd.qtd_status = 2689 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2690 cur->xfer = xfer; 2691 cur->len = curlen; 2692 2693 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2694 dataphys, dataphys + curlen)); 2695 /* adjust the toggle based on the number of packets in this 2696 qtd */ 2697 if (((curlen + mps - 1) / mps) & 1) { 2698 tog ^= 1; 2699 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2700 } 2701 if (next == NULL) 2702 break; 2703 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2704 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2705 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2706 dataphys += curlen; 2707 cur = next; 2708 } 2709 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2710 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2711 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2712 *ep = cur; 2713 epipe->nexttoggle = tog; 2714 2715 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2716 *sp, *ep)); 2717 2718 return (USBD_NORMAL_COMPLETION); 2719 2720 nomem: 2721 /* XXX free chain */ 2722 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2723 return (USBD_NOMEM); 2724 } 2725 2726 Static void 2727 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2728 ehci_soft_qtd_t *sqtdend) 2729 { 2730 ehci_soft_qtd_t *p; 2731 int i; 2732 2733 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2734 sqtd, sqtdend)); 2735 2736 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2737 p = sqtd->nextqtd; 2738 ehci_free_sqtd(sc, sqtd); 2739 } 2740 } 2741 2742 ehci_soft_itd_t * 2743 ehci_alloc_itd(ehci_softc_t *sc) 2744 { 2745 struct ehci_soft_itd *itd, *freeitd; 2746 usbd_status err; 2747 int i, s, offs, frindex, previndex; 2748 usb_dma_t dma; 2749 2750 s = splusb(); 2751 2752 /* Find an itd that wasn't freed this frame or last frame. This can 2753 * discard itds that were freed before frindex wrapped around 2754 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2755 * interrupt and fiddling with list when that happens */ 2756 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2757 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2758 2759 freeitd = NULL; 2760 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2761 if (itd == NULL) 2762 break; 2763 if (itd->slot != frindex && itd->slot != previndex) { 2764 freeitd = itd; 2765 break; 2766 } 2767 } 2768 2769 if (freeitd == NULL) { 2770 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2771 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2772 EHCI_PAGE_SIZE, &dma); 2773 2774 if (err) { 2775 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2776 return NULL; 2777 } 2778 2779 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2780 offs = i * EHCI_ITD_SIZE; 2781 itd = KERNADDR(&dma, offs); 2782 itd->physaddr = DMAADDR(&dma, offs); 2783 itd->dma = dma; 2784 itd->offs = offs; 2785 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2786 } 2787 freeitd = LIST_FIRST(&sc->sc_freeitds); 2788 } 2789 2790 itd = freeitd; 2791 LIST_REMOVE(itd, u.free_list); 2792 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2793 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2794 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2795 BUS_DMASYNC_PREREAD); 2796 2797 itd->u.frame_list.next = NULL; 2798 itd->u.frame_list.prev = NULL; 2799 itd->xfer_next = NULL; 2800 itd->slot = 0; 2801 splx(s); 2802 2803 return itd; 2804 } 2805 2806 void 2807 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2808 { 2809 int s; 2810 2811 s = splusb(); 2812 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2813 splx(s); 2814 } 2815 2816 2817 2818 /****************/ 2819 2820 /* 2821 * Close a reqular pipe. 2822 * Assumes that there are no pending transactions. 2823 */ 2824 void 2825 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2826 { 2827 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2828 ehci_softc_t *sc = pipe->device->bus->hci_private; 2829 ehci_soft_qh_t *sqh = epipe->sqh; 2830 int s; 2831 2832 s = splusb(); 2833 ehci_rem_qh(sc, sqh, head); 2834 splx(s); 2835 ehci_free_sqh(sc, epipe->sqh); 2836 } 2837 2838 /* 2839 * Abort a device request. 2840 * If this routine is called at splusb() it guarantees that the request 2841 * will be removed from the hardware scheduling and that the callback 2842 * for it will be called with USBD_CANCELLED status. 2843 * It's impossible to guarantee that the requested transfer will not 2844 * have happened since the hardware runs concurrently. 2845 * If the transaction has already happened we rely on the ordinary 2846 * interrupt processing to process it. 2847 * XXX This is most probably wrong. 2848 */ 2849 void 2850 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2851 { 2852 #define exfer EXFER(xfer) 2853 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2854 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2855 ehci_soft_qh_t *sqh = epipe->sqh; 2856 ehci_soft_qtd_t *sqtd; 2857 ehci_physaddr_t cur; 2858 u_int32_t qhstatus; 2859 int s; 2860 int hit; 2861 int wake; 2862 2863 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2864 2865 if (sc->sc_dying) { 2866 /* If we're dying, just do the software part. */ 2867 s = splusb(); 2868 xfer->status = status; /* make software ignore it */ 2869 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2870 usb_transfer_complete(xfer); 2871 splx(s); 2872 return; 2873 } 2874 2875 if (xfer->device->bus->intr_context) 2876 panic("ehci_abort_xfer: not in process context"); 2877 2878 /* 2879 * If an abort is already in progress then just wait for it to 2880 * complete and return. 2881 */ 2882 if (xfer->hcflags & UXFER_ABORTING) { 2883 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2884 #ifdef DIAGNOSTIC 2885 if (status == USBD_TIMEOUT) 2886 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2887 #endif 2888 /* Override the status which might be USBD_TIMEOUT. */ 2889 xfer->status = status; 2890 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2891 xfer->hcflags |= UXFER_ABORTWAIT; 2892 while (xfer->hcflags & UXFER_ABORTING) 2893 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2894 return; 2895 } 2896 xfer->hcflags |= UXFER_ABORTING; 2897 2898 /* 2899 * Step 1: Make interrupt routine and hardware ignore xfer. 2900 */ 2901 s = splusb(); 2902 xfer->status = status; /* make software ignore it */ 2903 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 2904 2905 usb_syncmem(&sqh->dma, 2906 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2907 sizeof(sqh->qh.qh_qtd.qtd_status), 2908 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2909 qhstatus = sqh->qh.qh_qtd.qtd_status; 2910 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2911 usb_syncmem(&sqh->dma, 2912 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2913 sizeof(sqh->qh.qh_qtd.qtd_status), 2914 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2915 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2916 usb_syncmem(&sqtd->dma, 2917 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2918 sizeof(sqtd->qtd.qtd_status), 2919 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2920 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2921 usb_syncmem(&sqtd->dma, 2922 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2923 sizeof(sqtd->qtd.qtd_status), 2924 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2925 if (sqtd == exfer->sqtdend) 2926 break; 2927 } 2928 splx(s); 2929 2930 /* 2931 * Step 2: Wait until we know hardware has finished any possible 2932 * use of the xfer. Also make sure the soft interrupt routine 2933 * has run. 2934 */ 2935 ehci_sync_hc(sc); 2936 s = splusb(); 2937 #ifdef USB_USE_SOFTINTR 2938 sc->sc_softwake = 1; 2939 #endif /* USB_USE_SOFTINTR */ 2940 usb_schedsoftintr(&sc->sc_bus); 2941 #ifdef USB_USE_SOFTINTR 2942 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2943 #endif /* USB_USE_SOFTINTR */ 2944 splx(s); 2945 2946 /* 2947 * Step 3: Remove any vestiges of the xfer from the hardware. 2948 * The complication here is that the hardware may have executed 2949 * beyond the xfer we're trying to abort. So as we're scanning 2950 * the TDs of this xfer we check if the hardware points to 2951 * any of them. 2952 */ 2953 s = splusb(); /* XXX why? */ 2954 2955 usb_syncmem(&sqh->dma, 2956 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2957 sizeof(sqh->qh.qh_curqtd), 2958 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2959 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2960 hit = 0; 2961 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2962 hit |= cur == sqtd->physaddr; 2963 if (sqtd == exfer->sqtdend) 2964 break; 2965 } 2966 sqtd = sqtd->nextqtd; 2967 /* Zap curqtd register if hardware pointed inside the xfer. */ 2968 if (hit && sqtd != NULL) { 2969 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 2970 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 2971 usb_syncmem(&sqh->dma, 2972 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2973 sizeof(sqh->qh.qh_curqtd), 2974 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2975 sqh->qh.qh_qtd.qtd_status = qhstatus; 2976 usb_syncmem(&sqh->dma, 2977 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2978 sizeof(sqh->qh.qh_qtd.qtd_status), 2979 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2980 } else { 2981 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2982 } 2983 2984 /* 2985 * Step 4: Execute callback. 2986 */ 2987 #ifdef DIAGNOSTIC 2988 exfer->isdone = 1; 2989 #endif 2990 wake = xfer->hcflags & UXFER_ABORTWAIT; 2991 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2992 usb_transfer_complete(xfer); 2993 if (wake) 2994 wakeup(&xfer->hcflags); 2995 2996 splx(s); 2997 #undef exfer 2998 } 2999 3000 void 3001 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3002 { 3003 ehci_isoc_trans_t trans_status; 3004 struct ehci_pipe *epipe; 3005 struct ehci_xfer *exfer; 3006 ehci_softc_t *sc; 3007 struct ehci_soft_itd *itd; 3008 int s, i, wake; 3009 3010 epipe = (struct ehci_pipe *) xfer->pipe; 3011 exfer = EXFER(xfer); 3012 sc = epipe->pipe.device->bus->hci_private; 3013 3014 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3015 3016 if (sc->sc_dying) { 3017 s = splusb(); 3018 xfer->status = status; 3019 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3020 usb_transfer_complete(xfer); 3021 splx(s); 3022 return; 3023 } 3024 3025 if (xfer->hcflags & UXFER_ABORTING) { 3026 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3027 3028 #ifdef DIAGNOSTIC 3029 if (status == USBD_TIMEOUT) 3030 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3031 #endif 3032 3033 xfer->status = status; 3034 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3035 xfer->hcflags |= UXFER_ABORTWAIT; 3036 while (xfer->hcflags & UXFER_ABORTING) 3037 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0); 3038 return; 3039 } 3040 xfer->hcflags |= UXFER_ABORTING; 3041 3042 xfer->status = status; 3043 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 3044 3045 s = splusb(); 3046 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3047 usb_syncmem(&itd->dma, 3048 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3049 sizeof(itd->itd.itd_ctl), 3050 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3051 3052 for (i = 0; i < 8; i++) { 3053 trans_status = le32toh(itd->itd.itd_ctl[i]); 3054 trans_status &= ~EHCI_ITD_ACTIVE; 3055 itd->itd.itd_ctl[i] = htole32(trans_status); 3056 } 3057 3058 usb_syncmem(&itd->dma, 3059 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3060 sizeof(itd->itd.itd_ctl), 3061 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3062 } 3063 splx(s); 3064 3065 s = splusb(); 3066 #ifdef USB_USE_SOFTINTR 3067 sc->sc_softwake = 1; 3068 #endif /* USB_USE_SOFTINTR */ 3069 usb_schedsoftintr(&sc->sc_bus); 3070 #ifdef USB_USE_SOFTINTR 3071 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3072 #endif /* USB_USE_SOFTINTR */ 3073 splx(s); 3074 3075 #ifdef DIAGNOSTIC 3076 exfer->isdone = 1; 3077 #endif 3078 wake = xfer->hcflags & UXFER_ABORTWAIT; 3079 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3080 usb_transfer_complete(xfer); 3081 if (wake) 3082 wakeup(&xfer->hcflags); 3083 3084 return; 3085 } 3086 3087 void 3088 ehci_timeout(void *addr) 3089 { 3090 struct ehci_xfer *exfer = addr; 3091 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3092 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3093 3094 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3095 #ifdef EHCI_DEBUG 3096 if (ehcidebug > 1) 3097 usbd_dump_pipe(exfer->xfer.pipe); 3098 #endif 3099 3100 if (sc->sc_dying) { 3101 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3102 return; 3103 } 3104 3105 /* Execute the abort in a process context. */ 3106 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3107 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3108 USB_TASKQ_HC); 3109 } 3110 3111 void 3112 ehci_timeout_task(void *addr) 3113 { 3114 usbd_xfer_handle xfer = addr; 3115 int s; 3116 3117 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3118 3119 s = splusb(); 3120 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3121 splx(s); 3122 } 3123 3124 /************************/ 3125 3126 Static usbd_status 3127 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3128 { 3129 usbd_status err; 3130 3131 /* Insert last in queue. */ 3132 err = usb_insert_transfer(xfer); 3133 if (err) 3134 return (err); 3135 3136 /* Pipe isn't running, start first */ 3137 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3138 } 3139 3140 Static usbd_status 3141 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3142 { 3143 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3144 usbd_status err; 3145 3146 if (sc->sc_dying) 3147 return (USBD_IOERROR); 3148 3149 #ifdef DIAGNOSTIC 3150 if (!(xfer->rqflags & URQ_REQUEST)) { 3151 /* XXX panic */ 3152 printf("ehci_device_ctrl_transfer: not a request\n"); 3153 return (USBD_INVAL); 3154 } 3155 #endif 3156 3157 err = ehci_device_request(xfer); 3158 if (err) 3159 return (err); 3160 3161 if (sc->sc_bus.use_polling) 3162 ehci_waitintr(sc, xfer); 3163 return (USBD_IN_PROGRESS); 3164 } 3165 3166 void 3167 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3168 { 3169 struct ehci_xfer *ex = EXFER(xfer); 3170 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3171 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3172 usb_device_request_t *req = &xfer->request; 3173 int len = UGETW(req->wLength); 3174 int rd = req->bmRequestType & UT_READ; 3175 3176 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3177 3178 #ifdef DIAGNOSTIC 3179 if (!(xfer->rqflags & URQ_REQUEST)) { 3180 panic("ehci_ctrl_done: not a request"); 3181 } 3182 #endif 3183 3184 mutex_enter(&sc->sc_intrhead_lock); 3185 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3186 ehci_del_intr_list(sc, ex); /* remove from active list */ 3187 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3188 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3189 BUS_DMASYNC_POSTWRITE); 3190 if (len) 3191 usb_syncmem(&xfer->dmabuf, 0, len, 3192 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3193 } 3194 mutex_exit(&sc->sc_intrhead_lock); 3195 3196 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3197 } 3198 3199 /* Abort a device control request. */ 3200 Static void 3201 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3202 { 3203 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3204 ehci_abort_xfer(xfer, USBD_CANCELLED); 3205 } 3206 3207 /* Close a device control pipe. */ 3208 Static void 3209 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3210 { 3211 ehci_softc_t *sc = pipe->device->bus->hci_private; 3212 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3213 3214 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3215 ehci_close_pipe(pipe, sc->sc_async_head); 3216 } 3217 3218 usbd_status 3219 ehci_device_request(usbd_xfer_handle xfer) 3220 { 3221 #define exfer EXFER(xfer) 3222 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3223 usb_device_request_t *req = &xfer->request; 3224 usbd_device_handle dev = epipe->pipe.device; 3225 ehci_softc_t *sc = dev->bus->hci_private; 3226 int addr = dev->address; 3227 ehci_soft_qtd_t *setup, *stat, *next; 3228 ehci_soft_qh_t *sqh; 3229 int isread; 3230 int len; 3231 usbd_status err; 3232 int s; 3233 3234 isread = req->bmRequestType & UT_READ; 3235 len = UGETW(req->wLength); 3236 3237 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3238 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3239 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3240 UGETW(req->wIndex), len, addr, 3241 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3242 3243 setup = ehci_alloc_sqtd(sc); 3244 if (setup == NULL) { 3245 err = USBD_NOMEM; 3246 goto bad1; 3247 } 3248 stat = ehci_alloc_sqtd(sc); 3249 if (stat == NULL) { 3250 err = USBD_NOMEM; 3251 goto bad2; 3252 } 3253 3254 sqh = epipe->sqh; 3255 epipe->u.ctl.length = len; 3256 3257 /* Update device address and length since they may have changed 3258 during the setup of the control pipe in usbd_new_device(). */ 3259 /* XXX This only needs to be done once, but it's too early in open. */ 3260 /* XXXX Should not touch ED here! */ 3261 sqh->qh.qh_endp = 3262 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3263 htole32( 3264 EHCI_QH_SET_ADDR(addr) | 3265 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3266 ); 3267 3268 /* Set up data transaction */ 3269 if (len != 0) { 3270 ehci_soft_qtd_t *end; 3271 3272 /* Start toggle at 1. */ 3273 epipe->nexttoggle = 1; 3274 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3275 &next, &end); 3276 if (err) 3277 goto bad3; 3278 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3279 end->nextqtd = stat; 3280 end->qtd.qtd_next = 3281 end->qtd.qtd_altnext = htole32(stat->physaddr); 3282 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3283 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3284 } else { 3285 next = stat; 3286 } 3287 3288 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3289 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3290 3291 /* Clear toggle */ 3292 setup->qtd.qtd_status = htole32( 3293 EHCI_QTD_ACTIVE | 3294 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3295 EHCI_QTD_SET_CERR(3) | 3296 EHCI_QTD_SET_TOGGLE(0) | 3297 EHCI_QTD_SET_BYTES(sizeof *req) 3298 ); 3299 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3300 setup->qtd.qtd_buffer_hi[0] = 0; 3301 setup->nextqtd = next; 3302 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3303 setup->xfer = xfer; 3304 setup->len = sizeof *req; 3305 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3306 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3307 3308 stat->qtd.qtd_status = htole32( 3309 EHCI_QTD_ACTIVE | 3310 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3311 EHCI_QTD_SET_CERR(3) | 3312 EHCI_QTD_SET_TOGGLE(1) | 3313 EHCI_QTD_IOC 3314 ); 3315 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3316 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3317 stat->nextqtd = NULL; 3318 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3319 stat->xfer = xfer; 3320 stat->len = 0; 3321 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3322 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3323 3324 #ifdef EHCI_DEBUG 3325 if (ehcidebug > 5) { 3326 DPRINTF(("ehci_device_request:\n")); 3327 ehci_dump_sqh(sqh); 3328 ehci_dump_sqtds(setup); 3329 } 3330 #endif 3331 3332 exfer->sqtdstart = setup; 3333 exfer->sqtdend = stat; 3334 #ifdef DIAGNOSTIC 3335 if (!exfer->isdone) { 3336 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3337 } 3338 exfer->isdone = 0; 3339 #endif 3340 3341 /* Insert qTD in QH list. */ 3342 s = splusb(); 3343 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3344 if (xfer->timeout && !sc->sc_bus.use_polling) { 3345 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3346 ehci_timeout, xfer); 3347 } 3348 mutex_enter(&sc->sc_intrhead_lock); 3349 ehci_add_intr_list(sc, exfer); 3350 mutex_exit(&sc->sc_intrhead_lock); 3351 xfer->status = USBD_IN_PROGRESS; 3352 splx(s); 3353 3354 #ifdef EHCI_DEBUG 3355 if (ehcidebug > 10) { 3356 DPRINTF(("ehci_device_request: status=%x\n", 3357 EOREAD4(sc, EHCI_USBSTS))); 3358 delay(10000); 3359 ehci_dump_regs(sc); 3360 ehci_dump_sqh(sc->sc_async_head); 3361 ehci_dump_sqh(sqh); 3362 ehci_dump_sqtds(setup); 3363 } 3364 #endif 3365 3366 return (USBD_NORMAL_COMPLETION); 3367 3368 bad3: 3369 ehci_free_sqtd(sc, stat); 3370 bad2: 3371 ehci_free_sqtd(sc, setup); 3372 bad1: 3373 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3374 xfer->status = err; 3375 usb_transfer_complete(xfer); 3376 return (err); 3377 #undef exfer 3378 } 3379 3380 /* 3381 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3382 * qTD status, or miss signalling occasionally under heavy load. If the host 3383 * machine is too fast, we we can miss transaction completion - when we scan 3384 * the active list the transaction still seems to be active. This generally 3385 * exhibits itself as a umass stall that never recovers. 3386 * 3387 * We work around this behaviour by setting up this callback after any softintr 3388 * that completes with transactions still pending, giving us another chance to 3389 * check for completion after the writeback has taken place. 3390 */ 3391 void 3392 ehci_intrlist_timeout(void *arg) 3393 { 3394 ehci_softc_t *sc = arg; 3395 int s = splusb(); 3396 3397 DPRINTF(("ehci_intrlist_timeout\n")); 3398 usb_schedsoftintr(&sc->sc_bus); 3399 3400 splx(s); 3401 } 3402 3403 /************************/ 3404 3405 Static usbd_status 3406 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3407 { 3408 usbd_status err; 3409 3410 /* Insert last in queue. */ 3411 err = usb_insert_transfer(xfer); 3412 if (err) 3413 return (err); 3414 3415 /* Pipe isn't running, start first */ 3416 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3417 } 3418 3419 usbd_status 3420 ehci_device_bulk_start(usbd_xfer_handle xfer) 3421 { 3422 #define exfer EXFER(xfer) 3423 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3424 usbd_device_handle dev = epipe->pipe.device; 3425 ehci_softc_t *sc = dev->bus->hci_private; 3426 ehci_soft_qtd_t *data, *dataend; 3427 ehci_soft_qh_t *sqh; 3428 usbd_status err; 3429 int len, isread, endpt; 3430 int s; 3431 3432 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3433 xfer, xfer->length, xfer->flags)); 3434 3435 if (sc->sc_dying) 3436 return (USBD_IOERROR); 3437 3438 #ifdef DIAGNOSTIC 3439 if (xfer->rqflags & URQ_REQUEST) 3440 panic("ehci_device_bulk_start: a request"); 3441 #endif 3442 3443 len = xfer->length; 3444 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3445 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3446 sqh = epipe->sqh; 3447 3448 epipe->u.bulk.length = len; 3449 3450 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3451 &dataend); 3452 if (err) { 3453 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3454 xfer->status = err; 3455 usb_transfer_complete(xfer); 3456 return (err); 3457 } 3458 3459 #ifdef EHCI_DEBUG 3460 if (ehcidebug > 5) { 3461 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3462 ehci_dump_sqh(sqh); 3463 ehci_dump_sqtds(data); 3464 } 3465 #endif 3466 3467 /* Set up interrupt info. */ 3468 exfer->sqtdstart = data; 3469 exfer->sqtdend = dataend; 3470 #ifdef DIAGNOSTIC 3471 if (!exfer->isdone) { 3472 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3473 } 3474 exfer->isdone = 0; 3475 #endif 3476 3477 s = splusb(); 3478 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3479 if (xfer->timeout && !sc->sc_bus.use_polling) { 3480 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3481 ehci_timeout, xfer); 3482 } 3483 mutex_enter(&sc->sc_intrhead_lock); 3484 ehci_add_intr_list(sc, exfer); 3485 mutex_exit(&sc->sc_intrhead_lock); 3486 xfer->status = USBD_IN_PROGRESS; 3487 splx(s); 3488 3489 #ifdef EHCI_DEBUG 3490 if (ehcidebug > 10) { 3491 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3492 delay(10000); 3493 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3494 ehci_dump_regs(sc); 3495 #if 0 3496 printf("async_head:\n"); 3497 ehci_dump_sqh(sc->sc_async_head); 3498 #endif 3499 printf("sqh:\n"); 3500 ehci_dump_sqh(sqh); 3501 ehci_dump_sqtds(data); 3502 } 3503 #endif 3504 3505 if (sc->sc_bus.use_polling) 3506 ehci_waitintr(sc, xfer); 3507 3508 return (USBD_IN_PROGRESS); 3509 #undef exfer 3510 } 3511 3512 Static void 3513 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3514 { 3515 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3516 ehci_abort_xfer(xfer, USBD_CANCELLED); 3517 } 3518 3519 /* 3520 * Close a device bulk pipe. 3521 */ 3522 Static void 3523 ehci_device_bulk_close(usbd_pipe_handle pipe) 3524 { 3525 ehci_softc_t *sc = pipe->device->bus->hci_private; 3526 3527 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3528 ehci_close_pipe(pipe, sc->sc_async_head); 3529 } 3530 3531 void 3532 ehci_device_bulk_done(usbd_xfer_handle xfer) 3533 { 3534 struct ehci_xfer *ex = EXFER(xfer); 3535 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3536 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3537 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3538 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3539 3540 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3541 xfer, xfer->actlen)); 3542 3543 mutex_enter(&sc->sc_intrhead_lock); 3544 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3545 ehci_del_intr_list(sc, ex); /* remove from active list */ 3546 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3547 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3548 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3549 } 3550 mutex_exit(&sc->sc_intrhead_lock); 3551 3552 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3553 } 3554 3555 /************************/ 3556 3557 Static usbd_status 3558 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3559 { 3560 struct ehci_soft_islot *isp; 3561 int islot, lev; 3562 3563 /* Find a poll rate that is large enough. */ 3564 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3565 if (EHCI_ILEV_IVAL(lev) <= ival) 3566 break; 3567 3568 /* Pick an interrupt slot at the right level. */ 3569 /* XXX could do better than picking at random */ 3570 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3571 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3572 3573 sqh->islot = islot; 3574 isp = &sc->sc_islots[islot]; 3575 ehci_add_qh(sqh, isp->sqh); 3576 3577 return (USBD_NORMAL_COMPLETION); 3578 } 3579 3580 Static usbd_status 3581 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3582 { 3583 usbd_status err; 3584 3585 /* Insert last in queue. */ 3586 err = usb_insert_transfer(xfer); 3587 if (err) 3588 return (err); 3589 3590 /* 3591 * Pipe isn't running (otherwise err would be USBD_INPROG), 3592 * so start it first. 3593 */ 3594 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3595 } 3596 3597 Static usbd_status 3598 ehci_device_intr_start(usbd_xfer_handle xfer) 3599 { 3600 #define exfer EXFER(xfer) 3601 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3602 usbd_device_handle dev = xfer->pipe->device; 3603 ehci_softc_t *sc = dev->bus->hci_private; 3604 ehci_soft_qtd_t *data, *dataend; 3605 ehci_soft_qh_t *sqh; 3606 usbd_status err; 3607 int len, isread, endpt; 3608 int s; 3609 3610 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3611 xfer, xfer->length, xfer->flags)); 3612 3613 if (sc->sc_dying) 3614 return (USBD_IOERROR); 3615 3616 #ifdef DIAGNOSTIC 3617 if (xfer->rqflags & URQ_REQUEST) 3618 panic("ehci_device_intr_start: a request"); 3619 #endif 3620 3621 len = xfer->length; 3622 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3623 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3624 sqh = epipe->sqh; 3625 3626 epipe->u.intr.length = len; 3627 3628 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3629 &dataend); 3630 if (err) { 3631 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3632 xfer->status = err; 3633 usb_transfer_complete(xfer); 3634 return (err); 3635 } 3636 3637 #ifdef EHCI_DEBUG 3638 if (ehcidebug > 5) { 3639 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3640 ehci_dump_sqh(sqh); 3641 ehci_dump_sqtds(data); 3642 } 3643 #endif 3644 3645 /* Set up interrupt info. */ 3646 exfer->sqtdstart = data; 3647 exfer->sqtdend = dataend; 3648 #ifdef DIAGNOSTIC 3649 if (!exfer->isdone) { 3650 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3651 } 3652 exfer->isdone = 0; 3653 #endif 3654 3655 s = splusb(); 3656 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3657 if (xfer->timeout && !sc->sc_bus.use_polling) { 3658 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout), 3659 ehci_timeout, xfer); 3660 } 3661 mutex_enter(&sc->sc_intrhead_lock); 3662 ehci_add_intr_list(sc, exfer); 3663 mutex_exit(&sc->sc_intrhead_lock); 3664 xfer->status = USBD_IN_PROGRESS; 3665 splx(s); 3666 3667 #ifdef EHCI_DEBUG 3668 if (ehcidebug > 10) { 3669 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3670 delay(10000); 3671 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3672 ehci_dump_regs(sc); 3673 printf("sqh:\n"); 3674 ehci_dump_sqh(sqh); 3675 ehci_dump_sqtds(data); 3676 } 3677 #endif 3678 3679 if (sc->sc_bus.use_polling) 3680 ehci_waitintr(sc, xfer); 3681 3682 return (USBD_IN_PROGRESS); 3683 #undef exfer 3684 } 3685 3686 Static void 3687 ehci_device_intr_abort(usbd_xfer_handle xfer) 3688 { 3689 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3690 if (xfer->pipe->intrxfer == xfer) { 3691 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3692 xfer->pipe->intrxfer = NULL; 3693 } 3694 /* 3695 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3696 * async doorbell. That's dependant on the async list, wheras 3697 * intr xfers are periodic, should not use this? 3698 */ 3699 ehci_abort_xfer(xfer, USBD_CANCELLED); 3700 } 3701 3702 Static void 3703 ehci_device_intr_close(usbd_pipe_handle pipe) 3704 { 3705 ehci_softc_t *sc = pipe->device->bus->hci_private; 3706 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3707 struct ehci_soft_islot *isp; 3708 3709 isp = &sc->sc_islots[epipe->sqh->islot]; 3710 ehci_close_pipe(pipe, isp->sqh); 3711 } 3712 3713 Static void 3714 ehci_device_intr_done(usbd_xfer_handle xfer) 3715 { 3716 #define exfer EXFER(xfer) 3717 struct ehci_xfer *ex = EXFER(xfer); 3718 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3719 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3720 ehci_soft_qtd_t *data, *dataend; 3721 ehci_soft_qh_t *sqh; 3722 usbd_status err; 3723 int len, isread, endpt, s; 3724 3725 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3726 xfer, xfer->actlen)); 3727 3728 mutex_enter(&sc->sc_intrhead_lock); 3729 if (xfer->pipe->repeat) { 3730 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3731 3732 len = epipe->u.intr.length; 3733 xfer->length = len; 3734 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3735 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3736 usb_syncmem(&xfer->dmabuf, 0, len, 3737 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3738 sqh = epipe->sqh; 3739 3740 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3741 &data, &dataend); 3742 if (err) { 3743 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3744 xfer->status = err; 3745 mutex_exit(&sc->sc_intrhead_lock); 3746 return; 3747 } 3748 3749 /* Set up interrupt info. */ 3750 exfer->sqtdstart = data; 3751 exfer->sqtdend = dataend; 3752 #ifdef DIAGNOSTIC 3753 if (!exfer->isdone) { 3754 printf("ehci_device_intr_done: not done, ex=%p\n", 3755 exfer); 3756 } 3757 exfer->isdone = 0; 3758 #endif 3759 3760 s = splusb(); 3761 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3762 if (xfer->timeout && !sc->sc_bus.use_polling) { 3763 usb_callout(xfer->timeout_handle, 3764 mstohz(xfer->timeout), ehci_timeout, xfer); 3765 } 3766 splx(s); 3767 3768 xfer->status = USBD_IN_PROGRESS; 3769 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3770 ehci_del_intr_list(sc, ex); /* remove from active list */ 3771 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3772 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3773 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3774 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3775 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3776 } 3777 mutex_exit(&sc->sc_intrhead_lock); 3778 #undef exfer 3779 } 3780 3781 /************************/ 3782 3783 Static usbd_status 3784 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3785 { 3786 usbd_status err; 3787 3788 err = usb_insert_transfer(xfer); 3789 if (err && err != USBD_IN_PROGRESS) 3790 return err; 3791 3792 return ehci_device_isoc_start(xfer); 3793 } 3794 3795 Static usbd_status 3796 ehci_device_isoc_start(usbd_xfer_handle xfer) 3797 { 3798 struct ehci_pipe *epipe; 3799 usbd_device_handle dev; 3800 ehci_softc_t *sc; 3801 struct ehci_xfer *exfer; 3802 ehci_soft_itd_t *itd, *prev, *start, *stop; 3803 usb_dma_t *dma_buf; 3804 int i, j, k, frames, uframes, ufrperframe; 3805 int s, trans_count, offs, total_length; 3806 int frindex; 3807 3808 start = NULL; 3809 prev = NULL; 3810 itd = NULL; 3811 trans_count = 0; 3812 total_length = 0; 3813 exfer = (struct ehci_xfer *) xfer; 3814 sc = xfer->pipe->device->bus->hci_private; 3815 dev = xfer->pipe->device; 3816 epipe = (struct ehci_pipe *)xfer->pipe; 3817 3818 /* 3819 * To allow continuous transfers, above we start all transfers 3820 * immediately. However, we're still going to get usbd_start_next call 3821 * this when another xfer completes. So, check if this is already 3822 * in progress or not 3823 */ 3824 3825 if (exfer->itdstart != NULL) 3826 return USBD_IN_PROGRESS; 3827 3828 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3829 xfer, xfer->length, xfer->flags)); 3830 3831 if (sc->sc_dying) 3832 return USBD_IOERROR; 3833 3834 /* 3835 * To avoid complication, don't allow a request right now that'll span 3836 * the entire frame table. To within 4 frames, to allow some leeway 3837 * on either side of where the hc currently is. 3838 */ 3839 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3840 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3841 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3842 return USBD_INVAL; 3843 } 3844 3845 #ifdef DIAGNOSTIC 3846 if (xfer->rqflags & URQ_REQUEST) 3847 panic("ehci_device_isoc_start: request\n"); 3848 3849 if (!exfer->isdone) 3850 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3851 exfer->isdone = 0; 3852 #endif 3853 3854 /* 3855 * Step 1: Allocate and initialize itds, how many do we need? 3856 * One per transfer if interval >= 8 microframes, fewer if we use 3857 * multiple microframes per frame. 3858 */ 3859 3860 i = epipe->pipe.endpoint->edesc->bInterval; 3861 if (i > 16 || i == 0) { 3862 /* Spec page 271 says intervals > 16 are invalid */ 3863 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3864 return USBD_INVAL; 3865 } 3866 3867 switch (i) { 3868 case 1: 3869 ufrperframe = 8; 3870 break; 3871 case 2: 3872 ufrperframe = 4; 3873 break; 3874 case 3: 3875 ufrperframe = 2; 3876 break; 3877 default: 3878 ufrperframe = 1; 3879 break; 3880 } 3881 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3882 uframes = 8 / ufrperframe; 3883 3884 if (frames == 0) { 3885 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3886 return USBD_INVAL; 3887 } 3888 3889 dma_buf = &xfer->dmabuf; 3890 offs = 0; 3891 3892 for (i = 0; i < frames; i++) { 3893 int froffs = offs; 3894 itd = ehci_alloc_itd(sc); 3895 3896 if (prev != NULL) { 3897 prev->itd.itd_next = 3898 htole32(itd->physaddr | EHCI_LINK_ITD); 3899 usb_syncmem(&itd->dma, 3900 itd->offs + offsetof(ehci_itd_t, itd_next), 3901 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 3902 3903 prev->xfer_next = itd; 3904 } else { 3905 start = itd; 3906 } 3907 3908 /* 3909 * Step 1.5, initialize uframes 3910 */ 3911 for (j = 0; j < 8; j += uframes) { 3912 /* Calculate which page in the list this starts in */ 3913 int addr = DMAADDR(dma_buf, froffs); 3914 addr = EHCI_PAGE_OFFSET(addr); 3915 addr += (offs - froffs); 3916 addr = EHCI_PAGE(addr); 3917 addr /= EHCI_PAGE_SIZE; 3918 3919 /* This gets the initial offset into the first page, 3920 * looks how far further along the current uframe 3921 * offset is. Works out how many pages that is. 3922 */ 3923 3924 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3925 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3926 EHCI_ITD_SET_PG(addr) | 3927 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 3928 3929 total_length += xfer->frlengths[trans_count]; 3930 offs += xfer->frlengths[trans_count]; 3931 trans_count++; 3932 3933 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3934 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3935 break; 3936 } 3937 } 3938 3939 /* Step 1.75, set buffer pointers. To simplify matters, all 3940 * pointers are filled out for the next 7 hardware pages in 3941 * the dma block, so no need to worry what pages to cover 3942 * and what to not. 3943 */ 3944 3945 for (j=0; j < 7; j++) { 3946 /* 3947 * Don't try to lookup a page that's past the end 3948 * of buffer 3949 */ 3950 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 3951 if (page_offs >= dma_buf->block->size) 3952 break; 3953 3954 long long page = DMAADDR(dma_buf, page_offs); 3955 page = EHCI_PAGE(page); 3956 itd->itd.itd_bufr[j] = 3957 htole32(EHCI_ITD_SET_BPTR(page)); 3958 itd->itd.itd_bufr_hi[j] = 3959 htole32(page >> 32); 3960 } 3961 3962 /* 3963 * Other special values 3964 */ 3965 3966 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3967 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3968 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3969 3970 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3971 ? 1 : 0; 3972 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3973 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3974 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3975 3976 /* FIXME: handle invalid trans */ 3977 itd->itd.itd_bufr[2] |= 3978 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3979 3980 usb_syncmem(&itd->dma, 3981 itd->offs + offsetof(ehci_itd_t, itd_next), 3982 sizeof(ehci_itd_t), 3983 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3984 3985 prev = itd; 3986 } /* End of frame */ 3987 3988 stop = itd; 3989 stop->xfer_next = NULL; 3990 exfer->isoc_len = total_length; 3991 3992 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 3993 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3994 3995 /* 3996 * Part 2: Transfer descriptors have now been set up, now they must 3997 * be scheduled into the period frame list. Erk. Not wanting to 3998 * complicate matters, transfer is denied if the transfer spans 3999 * more than the period frame list. 4000 */ 4001 4002 s = splusb(); 4003 4004 /* Start inserting frames */ 4005 if (epipe->u.isoc.cur_xfers > 0) { 4006 frindex = epipe->u.isoc.next_frame; 4007 } else { 4008 frindex = EOREAD4(sc, EHCI_FRINDEX); 4009 frindex = frindex >> 3; /* Erase microframe index */ 4010 frindex += 2; 4011 } 4012 4013 if (frindex >= sc->sc_flsize) 4014 frindex &= (sc->sc_flsize - 1); 4015 4016 /* Whats the frame interval? */ 4017 i = (1 << epipe->pipe.endpoint->edesc->bInterval); 4018 if (i / 8 == 0) 4019 i = 1; 4020 else 4021 i /= 8; 4022 4023 itd = start; 4024 for (j = 0; j < frames; j++) { 4025 if (itd == NULL) 4026 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4027 4028 itd->itd.itd_next = sc->sc_flist[frindex]; 4029 if (itd->itd.itd_next == 0) 4030 /* FIXME: frindex table gets initialized to NULL 4031 * or EHCI_NULL? */ 4032 itd->itd.itd_next = htole32(EHCI_NULL); 4033 4034 usb_syncmem(&itd->dma, 4035 itd->offs + offsetof(ehci_itd_t, itd_next), 4036 sizeof(itd->itd.itd_next), 4037 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4038 4039 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4040 4041 usb_syncmem(&sc->sc_fldma, 4042 sizeof(ehci_link_t) * frindex, 4043 sizeof(ehci_link_t), 4044 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4045 4046 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4047 sc->sc_softitds[frindex] = itd; 4048 if (itd->u.frame_list.next != NULL) 4049 itd->u.frame_list.next->u.frame_list.prev = itd; 4050 itd->slot = frindex; 4051 itd->u.frame_list.prev = NULL; 4052 4053 frindex += i; 4054 if (frindex >= sc->sc_flsize) 4055 frindex -= sc->sc_flsize; 4056 4057 itd = itd->xfer_next; 4058 } 4059 4060 epipe->u.isoc.cur_xfers++; 4061 epipe->u.isoc.next_frame = frindex; 4062 4063 exfer->itdstart = start; 4064 exfer->itdend = stop; 4065 exfer->sqtdstart = NULL; 4066 exfer->sqtdstart = NULL; 4067 4068 mutex_enter(&sc->sc_intrhead_lock); 4069 ehci_add_intr_list(sc, exfer); 4070 mutex_exit(&sc->sc_intrhead_lock); 4071 xfer->status = USBD_IN_PROGRESS; 4072 xfer->done = 0; 4073 splx(s); 4074 4075 if (sc->sc_bus.use_polling) { 4076 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4077 ehci_waitintr(sc, xfer); 4078 } 4079 4080 return USBD_IN_PROGRESS; 4081 } 4082 4083 Static void 4084 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4085 { 4086 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4087 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4088 } 4089 4090 Static void 4091 ehci_device_isoc_close(usbd_pipe_handle pipe) 4092 { 4093 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4094 } 4095 4096 Static void 4097 ehci_device_isoc_done(usbd_xfer_handle xfer) 4098 { 4099 struct ehci_xfer *exfer; 4100 ehci_softc_t *sc; 4101 struct ehci_pipe *epipe; 4102 int s; 4103 4104 exfer = EXFER(xfer); 4105 sc = xfer->pipe->device->bus->hci_private; 4106 epipe = (struct ehci_pipe *) xfer->pipe; 4107 4108 s = splusb(); 4109 epipe->u.isoc.cur_xfers--; 4110 mutex_enter(&sc->sc_intrhead_lock); 4111 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4112 ehci_del_intr_list(sc, exfer); 4113 ehci_rem_free_itd_chain(sc, exfer); 4114 } 4115 mutex_exit(&sc->sc_intrhead_lock); 4116 splx(s); 4117 4118 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4119 BUS_DMASYNC_POSTREAD); 4120 4121 } 4122
Indexes created Mon Sep 22 21:09:42 GMT 2025