ehci.c revision 1.167
1 /* $NetBSD: ehci.c,v 1.167 2010/05/29 16:52:33 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum and 9 * Jeremy Morse (jeremy.morse (at) gmail.com). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 35 * 36 * The EHCI 1.0 spec can be found at 37 * http://www.intel.com/technology/usb/spec.htm 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/ 40 * 41 */ 42 43 /* 44 * TODO: 45 * 1) hold off explorations by companion controllers until ehci has started. 46 * 47 * 2) The hub driver needs to handle and schedule the transaction translator, 48 * to assign place in frame where different devices get to go. See chapter 49 * on hubs in USB 2.0 for details. 50 * 51 * 3) Command failures are not recovered correctly. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.167 2010/05/29 16:52:33 jakllsch Exp $"); 56 57 #include "ohci.h" 58 #include "uhci.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/kernel.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/select.h> 66 #include <sys/proc.h> 67 #include <sys/queue.h> 68 #include <sys/mutex.h> 69 #include <sys/bus.h> 70 71 #include <machine/endian.h> 72 73 #include <dev/usb/usb.h> 74 #include <dev/usb/usbdi.h> 75 #include <dev/usb/usbdivar.h> 76 #include <dev/usb/usb_mem.h> 77 #include <dev/usb/usb_quirks.h> 78 79 #include <dev/usb/ehcireg.h> 80 #include <dev/usb/ehcivar.h> 81 #include <dev/usb/usbroothub_subr.h> 82 83 #ifdef EHCI_DEBUG 84 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 85 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 86 int ehcidebug = 0; 87 #else 88 #define DPRINTF(x) 89 #define DPRINTFN(n,x) 90 #endif 91 92 struct ehci_pipe { 93 struct usbd_pipe pipe; 94 int nexttoggle; 95 96 ehci_soft_qh_t *sqh; 97 union { 98 ehci_soft_qtd_t *qtd; 99 /* ehci_soft_itd_t *itd; */ 100 } tail; 101 union { 102 /* Control pipe */ 103 struct { 104 usb_dma_t reqdma; 105 u_int length; 106 } ctl; 107 /* Interrupt pipe */ 108 struct { 109 u_int length; 110 } intr; 111 /* Bulk pipe */ 112 struct { 113 u_int length; 114 } bulk; 115 /* Iso pipe */ 116 struct { 117 u_int next_frame; 118 u_int cur_xfers; 119 } isoc; 120 } u; 121 }; 122 123 Static usbd_status ehci_open(usbd_pipe_handle); 124 Static void ehci_poll(struct usbd_bus *); 125 Static void ehci_softintr(void *); 126 Static int ehci_intr1(ehci_softc_t *); 127 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 128 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 129 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 130 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 131 Static void ehci_idone(struct ehci_xfer *); 132 Static void ehci_timeout(void *); 133 Static void ehci_timeout_task(void *); 134 Static void ehci_intrlist_timeout(void *); 135 136 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 137 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 138 139 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 140 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 141 142 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 143 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 144 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 145 Static void ehci_root_ctrl_close(usbd_pipe_handle); 146 Static void ehci_root_ctrl_done(usbd_xfer_handle); 147 148 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 149 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 150 Static void ehci_root_intr_abort(usbd_xfer_handle); 151 Static void ehci_root_intr_close(usbd_pipe_handle); 152 Static void ehci_root_intr_done(usbd_xfer_handle); 153 154 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 155 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 156 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 157 Static void ehci_device_ctrl_close(usbd_pipe_handle); 158 Static void ehci_device_ctrl_done(usbd_xfer_handle); 159 160 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 161 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 162 Static void ehci_device_bulk_abort(usbd_xfer_handle); 163 Static void ehci_device_bulk_close(usbd_pipe_handle); 164 Static void ehci_device_bulk_done(usbd_xfer_handle); 165 166 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 167 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 168 Static void ehci_device_intr_abort(usbd_xfer_handle); 169 Static void ehci_device_intr_close(usbd_pipe_handle); 170 Static void ehci_device_intr_done(usbd_xfer_handle); 171 172 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 173 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 174 Static void ehci_device_isoc_abort(usbd_xfer_handle); 175 Static void ehci_device_isoc_close(usbd_pipe_handle); 176 Static void ehci_device_isoc_done(usbd_xfer_handle); 177 178 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 179 Static void ehci_noop(usbd_pipe_handle pipe); 180 181 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 182 Static void ehci_disown(ehci_softc_t *, int, int); 183 184 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 185 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 186 187 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 188 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 189 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 190 ehci_softc_t *, int, int, usbd_xfer_handle, 191 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 192 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 193 ehci_soft_qtd_t *); 194 195 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 196 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 197 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 198 struct ehci_xfer *exfer); 199 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 200 usbd_status status); 201 202 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 203 204 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 205 int ival); 206 207 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 208 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 209 ehci_soft_qh_t *); 210 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 211 Static void ehci_sync_hc(ehci_softc_t *); 212 213 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 214 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 215 216 #ifdef EHCI_DEBUG 217 Static void ehci_dump_regs(ehci_softc_t *); 218 void ehci_dump(void); 219 Static ehci_softc_t *theehci; 220 Static void ehci_dump_link(ehci_link_t, int); 221 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 222 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 223 Static void ehci_dump_qtd(ehci_qtd_t *); 224 Static void ehci_dump_sqh(ehci_soft_qh_t *); 225 #if notyet 226 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 227 Static void ehci_dump_itd(struct ehci_soft_itd *); 228 #endif 229 #ifdef DIAGNOSTIC 230 Static void ehci_dump_exfer(struct ehci_xfer *); 231 #endif 232 #endif 233 234 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 235 236 #define EHCI_INTR_ENDPT 1 237 238 #define ehci_add_intr_list(sc, ex) \ 239 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 240 #define ehci_del_intr_list(sc, ex) \ 241 do { \ 242 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 243 (ex)->inext.tqe_prev = NULL; \ 244 } while (0) 245 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 246 247 Static const struct usbd_bus_methods ehci_bus_methods = { 248 ehci_open, 249 ehci_softintr, 250 ehci_poll, 251 ehci_allocm, 252 ehci_freem, 253 ehci_allocx, 254 ehci_freex, 255 }; 256 257 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 258 ehci_root_ctrl_transfer, 259 ehci_root_ctrl_start, 260 ehci_root_ctrl_abort, 261 ehci_root_ctrl_close, 262 ehci_noop, 263 ehci_root_ctrl_done, 264 }; 265 266 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 267 ehci_root_intr_transfer, 268 ehci_root_intr_start, 269 ehci_root_intr_abort, 270 ehci_root_intr_close, 271 ehci_noop, 272 ehci_root_intr_done, 273 }; 274 275 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 276 ehci_device_ctrl_transfer, 277 ehci_device_ctrl_start, 278 ehci_device_ctrl_abort, 279 ehci_device_ctrl_close, 280 ehci_noop, 281 ehci_device_ctrl_done, 282 }; 283 284 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 285 ehci_device_intr_transfer, 286 ehci_device_intr_start, 287 ehci_device_intr_abort, 288 ehci_device_intr_close, 289 ehci_device_clear_toggle, 290 ehci_device_intr_done, 291 }; 292 293 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 294 ehci_device_bulk_transfer, 295 ehci_device_bulk_start, 296 ehci_device_bulk_abort, 297 ehci_device_bulk_close, 298 ehci_device_clear_toggle, 299 ehci_device_bulk_done, 300 }; 301 302 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 303 ehci_device_isoc_transfer, 304 ehci_device_isoc_start, 305 ehci_device_isoc_abort, 306 ehci_device_isoc_close, 307 ehci_noop, 308 ehci_device_isoc_done, 309 }; 310 311 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 312 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 313 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 314 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 315 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 316 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 317 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 318 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 319 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 320 }; 321 322 usbd_status 323 ehci_init(ehci_softc_t *sc) 324 { 325 u_int32_t vers, sparams, cparams, hcr; 326 u_int i; 327 usbd_status err; 328 ehci_soft_qh_t *sqh; 329 u_int ncomp; 330 331 DPRINTF(("ehci_init: start\n")); 332 #ifdef EHCI_DEBUG 333 theehci = sc; 334 #endif 335 336 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 337 338 vers = EREAD2(sc, EHCI_HCIVERSION); 339 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 340 vers >> 8, vers & 0xff); 341 342 sparams = EREAD4(sc, EHCI_HCSPARAMS); 343 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 344 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 345 ncomp = EHCI_HCS_N_CC(sparams); 346 if (ncomp != sc->sc_ncomp) { 347 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 348 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 349 #if NOHCI == 0 || NUHCI == 0 350 aprint_error("%s: ohci or uhci probably not configured\n", 351 device_xname(sc->sc_dev)); 352 #endif 353 if (ncomp < sc->sc_ncomp) 354 sc->sc_ncomp = ncomp; 355 } 356 if (sc->sc_ncomp > 0) { 357 aprint_normal("%s: companion controller%s, %d port%s each:", 358 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 359 EHCI_HCS_N_PCC(sparams), 360 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 361 for (i = 0; i < sc->sc_ncomp; i++) 362 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 363 aprint_normal("\n"); 364 } 365 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 366 cparams = EREAD4(sc, EHCI_HCCPARAMS); 367 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 368 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 369 370 if (EHCI_HCC_64BIT(cparams)) { 371 /* MUST clear segment register if 64 bit capable. */ 372 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 373 } 374 375 sc->sc_bus.usbrev = USBREV_2_0; 376 377 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 378 USB_MEM_RESERVE); 379 380 /* Reset the controller */ 381 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 382 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 383 usb_delay_ms(&sc->sc_bus, 1); 384 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 385 for (i = 0; i < 100; i++) { 386 usb_delay_ms(&sc->sc_bus, 1); 387 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 388 if (!hcr) 389 break; 390 } 391 if (hcr) { 392 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 393 return (USBD_IOERROR); 394 } 395 396 /* XXX need proper intr scheduling */ 397 sc->sc_rand = 96; 398 399 /* frame list size at default, read back what we got and use that */ 400 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 401 case 0: sc->sc_flsize = 1024; break; 402 case 1: sc->sc_flsize = 512; break; 403 case 2: sc->sc_flsize = 256; break; 404 case 3: return (USBD_IOERROR); 405 } 406 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 407 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 408 if (err) 409 return (err); 410 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 411 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 412 413 for (i = 0; i < sc->sc_flsize; i++) { 414 sc->sc_flist[i] = EHCI_NULL; 415 } 416 417 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 418 419 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 420 M_USB, M_NOWAIT | M_ZERO); 421 if (sc->sc_softitds == NULL) 422 return ENOMEM; 423 LIST_INIT(&sc->sc_freeitds); 424 TAILQ_INIT(&sc->sc_intrhead); 425 mutex_init(&sc->sc_intrhead_lock, MUTEX_DEFAULT, IPL_USB); 426 427 /* Set up the bus struct. */ 428 sc->sc_bus.methods = &ehci_bus_methods; 429 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 430 431 sc->sc_eintrs = EHCI_NORMAL_INTRS; 432 433 /* 434 * Allocate the interrupt dummy QHs. These are arranged to give poll 435 * intervals that are powers of 2 times 1ms. 436 */ 437 for (i = 0; i < EHCI_INTRQHS; i++) { 438 sqh = ehci_alloc_sqh(sc); 439 if (sqh == NULL) { 440 err = USBD_NOMEM; 441 goto bad1; 442 } 443 sc->sc_islots[i].sqh = sqh; 444 } 445 for (i = 0; i < EHCI_INTRQHS; i++) { 446 sqh = sc->sc_islots[i].sqh; 447 if (i == 0) { 448 /* The last (1ms) QH terminates. */ 449 sqh->qh.qh_link = EHCI_NULL; 450 sqh->next = NULL; 451 } else { 452 /* Otherwise the next QH has half the poll interval */ 453 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 454 sqh->qh.qh_link = htole32(sqh->next->physaddr | 455 EHCI_LINK_QH); 456 } 457 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 458 sqh->qh.qh_curqtd = EHCI_NULL; 459 sqh->next = NULL; 460 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 461 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 462 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 463 sqh->sqtd = NULL; 464 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 465 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 466 } 467 /* Point the frame list at the last level (128ms). */ 468 for (i = 0; i < sc->sc_flsize; i++) { 469 int j; 470 471 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 472 revbits[i & (EHCI_MAX_POLLRATE-1)]; 473 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 474 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 475 i)].sqh->physaddr); 476 } 477 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 478 BUS_DMASYNC_PREWRITE); 479 480 /* Allocate dummy QH that starts the async list. */ 481 sqh = ehci_alloc_sqh(sc); 482 if (sqh == NULL) { 483 err = USBD_NOMEM; 484 goto bad1; 485 } 486 /* Fill the QH */ 487 sqh->qh.qh_endp = 488 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 489 sqh->qh.qh_link = 490 htole32(sqh->physaddr | EHCI_LINK_QH); 491 sqh->qh.qh_curqtd = EHCI_NULL; 492 sqh->next = NULL; 493 /* Fill the overlay qTD */ 494 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 495 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 496 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 497 sqh->sqtd = NULL; 498 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 499 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 500 #ifdef EHCI_DEBUG 501 if (ehcidebug) { 502 ehci_dump_sqh(sqh); 503 } 504 #endif 505 506 /* Point to async list */ 507 sc->sc_async_head = sqh; 508 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 509 510 callout_init(&(sc->sc_tmo_intrlist), 0); 511 512 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE); 513 514 /* Turn on controller */ 515 EOWRITE4(sc, EHCI_USBCMD, 516 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 517 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 518 EHCI_CMD_ASE | 519 EHCI_CMD_PSE | 520 EHCI_CMD_RS); 521 522 /* Take over port ownership */ 523 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 524 525 for (i = 0; i < 100; i++) { 526 usb_delay_ms(&sc->sc_bus, 1); 527 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 528 if (!hcr) 529 break; 530 } 531 if (hcr) { 532 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 533 return (USBD_IOERROR); 534 } 535 536 /* Enable interrupts */ 537 DPRINTFN(1,("ehci_init: enabling\n")); 538 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 539 540 return (USBD_NORMAL_COMPLETION); 541 542 #if 0 543 bad2: 544 ehci_free_sqh(sc, sc->sc_async_head); 545 #endif 546 bad1: 547 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 548 return (err); 549 } 550 551 int 552 ehci_intr(void *v) 553 { 554 ehci_softc_t *sc = v; 555 556 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 557 return (0); 558 559 /* If we get an interrupt while polling, then just ignore it. */ 560 if (sc->sc_bus.use_polling) { 561 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 562 563 if (intrs) 564 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 565 #ifdef DIAGNOSTIC 566 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 567 #endif 568 return (0); 569 } 570 571 return (ehci_intr1(sc)); 572 } 573 574 Static int 575 ehci_intr1(ehci_softc_t *sc) 576 { 577 u_int32_t intrs, eintrs; 578 579 DPRINTFN(20,("ehci_intr1: enter\n")); 580 581 /* In case the interrupt occurs before initialization has completed. */ 582 if (sc == NULL) { 583 #ifdef DIAGNOSTIC 584 printf("ehci_intr1: sc == NULL\n"); 585 #endif 586 return (0); 587 } 588 589 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 590 if (!intrs) 591 return (0); 592 593 eintrs = intrs & sc->sc_eintrs; 594 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 595 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 596 (u_int)eintrs)); 597 if (!eintrs) 598 return (0); 599 600 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 601 sc->sc_bus.intr_context++; 602 sc->sc_bus.no_intrs++; 603 if (eintrs & EHCI_STS_IAA) { 604 DPRINTF(("ehci_intr1: door bell\n")); 605 wakeup(&sc->sc_async_head); 606 eintrs &= ~EHCI_STS_IAA; 607 } 608 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 609 DPRINTFN(5,("ehci_intr1: %s %s\n", 610 eintrs & EHCI_STS_INT ? "INT" : "", 611 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 612 usb_schedsoftintr(&sc->sc_bus); 613 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 614 } 615 if (eintrs & EHCI_STS_HSE) { 616 printf("%s: unrecoverable error, controller halted\n", 617 device_xname(sc->sc_dev)); 618 /* XXX what else */ 619 } 620 if (eintrs & EHCI_STS_PCD) { 621 ehci_pcd(sc, sc->sc_intrxfer); 622 eintrs &= ~EHCI_STS_PCD; 623 } 624 625 sc->sc_bus.intr_context--; 626 627 if (eintrs != 0) { 628 /* Block unprocessed interrupts. */ 629 sc->sc_eintrs &= ~eintrs; 630 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 631 printf("%s: blocking intrs 0x%x\n", 632 device_xname(sc->sc_dev), eintrs); 633 } 634 635 return (1); 636 } 637 638 639 Static void 640 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 641 { 642 usbd_pipe_handle pipe; 643 u_char *p; 644 int i, m; 645 646 if (xfer == NULL) { 647 /* Just ignore the change. */ 648 return; 649 } 650 651 pipe = xfer->pipe; 652 653 p = KERNADDR(&xfer->dmabuf, 0); 654 m = min(sc->sc_noport, xfer->length * 8 - 1); 655 memset(p, 0, xfer->length); 656 for (i = 1; i <= m; i++) { 657 /* Pick out CHANGE bits from the status reg. */ 658 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 659 p[i/8] |= 1 << (i%8); 660 } 661 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 662 xfer->actlen = xfer->length; 663 xfer->status = USBD_NORMAL_COMPLETION; 664 665 usb_transfer_complete(xfer); 666 } 667 668 Static void 669 ehci_softintr(void *v) 670 { 671 struct usbd_bus *bus = v; 672 ehci_softc_t *sc = bus->hci_private; 673 struct ehci_xfer *ex, *nextex; 674 675 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 676 sc->sc_bus.intr_context)); 677 678 sc->sc_bus.intr_context++; 679 680 /* 681 * The only explanation I can think of for why EHCI is as brain dead 682 * as UHCI interrupt-wise is that Intel was involved in both. 683 * An interrupt just tells us that something is done, we have no 684 * clue what, so we need to scan through all active transfers. :-( 685 */ 686 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 687 nextex = TAILQ_NEXT(ex, inext); 688 ehci_check_intr(sc, ex); 689 } 690 691 /* Schedule a callout to catch any dropped transactions. */ 692 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 693 !TAILQ_EMPTY(&sc->sc_intrhead)) 694 callout_reset(&(sc->sc_tmo_intrlist), 695 (hz), (ehci_intrlist_timeout), (sc)); 696 697 #ifdef USB_USE_SOFTINTR 698 if (sc->sc_softwake) { 699 sc->sc_softwake = 0; 700 wakeup(&sc->sc_softwake); 701 } 702 #endif /* USB_USE_SOFTINTR */ 703 704 sc->sc_bus.intr_context--; 705 } 706 707 /* Check for an interrupt. */ 708 Static void 709 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 710 { 711 int attr; 712 713 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 714 715 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 716 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 717 ehci_check_itd_intr(sc, ex); 718 else 719 ehci_check_qh_intr(sc, ex); 720 721 return; 722 } 723 724 Static void 725 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 726 { 727 ehci_soft_qtd_t *sqtd, *lsqtd; 728 __uint32_t status; 729 730 if (ex->sqtdstart == NULL) { 731 printf("ehci_check_qh_intr: not valid sqtd\n"); 732 return; 733 } 734 735 lsqtd = ex->sqtdend; 736 #ifdef DIAGNOSTIC 737 if (lsqtd == NULL) { 738 printf("ehci_check_qh_intr: lsqtd==0\n"); 739 return; 740 } 741 #endif 742 /* 743 * If the last TD is still active we need to check whether there 744 * is a an error somewhere in the middle, or whether there was a 745 * short packet (SPD and not ACTIVE). 746 */ 747 usb_syncmem(&lsqtd->dma, 748 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 749 sizeof(lsqtd->qtd.qtd_status), 750 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 751 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 752 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 753 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 754 usb_syncmem(&sqtd->dma, 755 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 756 sizeof(sqtd->qtd.qtd_status), 757 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 758 status = le32toh(sqtd->qtd.qtd_status); 759 usb_syncmem(&sqtd->dma, 760 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 761 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 762 /* If there's an active QTD the xfer isn't done. */ 763 if (status & EHCI_QTD_ACTIVE) 764 break; 765 /* Any kind of error makes the xfer done. */ 766 if (status & EHCI_QTD_HALTED) 767 goto done; 768 /* We want short packets, and it is short: it's done */ 769 if (EHCI_QTD_GET_BYTES(status) != 0) 770 goto done; 771 } 772 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 773 ex, ex->sqtdstart)); 774 usb_syncmem(&lsqtd->dma, 775 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 776 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 777 return; 778 } 779 done: 780 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 781 callout_stop(&(ex->xfer.timeout_handle)); 782 ehci_idone(ex); 783 } 784 785 Static void 786 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 787 ehci_soft_itd_t *itd; 788 int i; 789 790 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 791 return; 792 793 if (ex->itdstart == NULL) { 794 printf("ehci_check_itd_intr: not valid itd\n"); 795 return; 796 } 797 798 itd = ex->itdend; 799 #ifdef DIAGNOSTIC 800 if (itd == NULL) { 801 printf("ehci_check_itd_intr: itdend == 0\n"); 802 return; 803 } 804 #endif 805 806 /* 807 * check no active transfers in last itd, meaning we're finished 808 */ 809 810 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 811 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 812 BUS_DMASYNC_POSTREAD); 813 814 for (i = 0; i < 8; i++) { 815 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 816 break; 817 } 818 819 if (i == 8) { 820 goto done; /* All 8 descriptors inactive, it's done */ 821 } 822 823 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 824 ex->itdstart)); 825 return; 826 done: 827 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 828 callout_stop(&(ex->xfer.timeout_handle)); 829 ehci_idone(ex); 830 } 831 832 Static void 833 ehci_idone(struct ehci_xfer *ex) 834 { 835 usbd_xfer_handle xfer = &ex->xfer; 836 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 837 ehci_soft_qtd_t *sqtd, *lsqtd; 838 u_int32_t status = 0, nstatus = 0; 839 int actlen; 840 841 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 842 #ifdef DIAGNOSTIC 843 { 844 int s = splhigh(); 845 if (ex->isdone) { 846 splx(s); 847 #ifdef EHCI_DEBUG 848 printf("ehci_idone: ex is done!\n "); 849 ehci_dump_exfer(ex); 850 #else 851 printf("ehci_idone: ex=%p is done!\n", ex); 852 #endif 853 return; 854 } 855 ex->isdone = 1; 856 splx(s); 857 } 858 #endif 859 if (xfer->status == USBD_CANCELLED || 860 xfer->status == USBD_TIMEOUT) { 861 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 862 return; 863 } 864 865 #ifdef EHCI_DEBUG 866 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 867 if (ehcidebug > 10) 868 ehci_dump_sqtds(ex->sqtdstart); 869 #endif 870 871 /* The transfer is done, compute actual length and status. */ 872 873 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 874 == UE_ISOCHRONOUS) { 875 /* Isoc transfer */ 876 struct ehci_soft_itd *itd; 877 int i, nframes, len, uframes; 878 879 nframes = 0; 880 actlen = 0; 881 882 switch (xfer->pipe->endpoint->edesc->bInterval) { 883 case 0: 884 panic("ehci: isoc xfer suddenly has 0 bInterval, invalid\n"); 885 case 1: uframes = 1; break; 886 case 2: uframes = 2; break; 887 case 3: uframes = 4; break; 888 default: uframes = 8; break; 889 } 890 891 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 892 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 893 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 894 BUS_DMASYNC_POSTREAD); 895 896 for (i = 0; i < 8; i += uframes) { 897 /* XXX - driver didn't fill in the frame full 898 * of uframes. This leads to scheduling 899 * inefficiencies, but working around 900 * this doubles complexity of tracking 901 * an xfer. 902 */ 903 if (nframes >= xfer->nframes) 904 break; 905 906 status = le32toh(itd->itd.itd_ctl[i]); 907 len = EHCI_ITD_GET_LEN(status); 908 if (EHCI_ITD_GET_STATUS(status) != 0) 909 len = 0; /*No valid data on error*/ 910 911 xfer->frlengths[nframes++] = len; 912 actlen += len; 913 } 914 915 if (nframes >= xfer->nframes) 916 break; 917 } 918 919 xfer->actlen = actlen; 920 xfer->status = USBD_NORMAL_COMPLETION; 921 goto end; 922 } 923 924 /* Continue processing xfers using queue heads */ 925 926 lsqtd = ex->sqtdend; 927 actlen = 0; 928 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 929 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 930 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 931 nstatus = le32toh(sqtd->qtd.qtd_status); 932 if (nstatus & EHCI_QTD_ACTIVE) 933 break; 934 935 status = nstatus; 936 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 937 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 938 } 939 940 941 /* 942 * If there are left over TDs we need to update the toggle. 943 * The default pipe doesn't need it since control transfers 944 * start the toggle at 0 every time. 945 * For a short transfer we need to update the toggle for the missing 946 * packets within the qTD. 947 */ 948 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 949 xfer->pipe->device->default_pipe != xfer->pipe) { 950 DPRINTFN(2, ("ehci_idone: need toggle update " 951 "status=%08x nstatus=%08x\n", status, nstatus)); 952 #if 0 953 ehci_dump_sqh(epipe->sqh); 954 ehci_dump_sqtds(ex->sqtdstart); 955 #endif 956 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 957 } 958 959 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 960 xfer->length, actlen, status)); 961 xfer->actlen = actlen; 962 if (status & EHCI_QTD_HALTED) { 963 #ifdef EHCI_DEBUG 964 char sbuf[128]; 965 966 snprintb(sbuf, sizeof(sbuf), 967 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 968 (u_int32_t)status); 969 970 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 971 "status 0x%s\n", 972 xfer->pipe->device->address, 973 xfer->pipe->endpoint->edesc->bEndpointAddress, 974 sbuf)); 975 if (ehcidebug > 2) { 976 ehci_dump_sqh(epipe->sqh); 977 ehci_dump_sqtds(ex->sqtdstart); 978 } 979 #endif 980 /* low&full speed has an extra error flag */ 981 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 982 EHCI_QH_SPEED_HIGH) 983 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 984 else 985 status &= EHCI_QTD_STATERRS; 986 if (status == 0) /* no other errors means a stall */ { 987 xfer->status = USBD_STALLED; 988 } else { 989 xfer->status = USBD_IOERROR; /* more info XXX */ 990 } 991 /* XXX need to reset TT on missed microframe */ 992 if (status & EHCI_QTD_MISSEDMICRO) { 993 ehci_softc_t *sc = 994 xfer->pipe->device->bus->hci_private; 995 996 printf("%s: missed microframe, TT reset not " 997 "implemented, hub might be inoperational\n", 998 device_xname(sc->sc_dev)); 999 } 1000 } else { 1001 xfer->status = USBD_NORMAL_COMPLETION; 1002 } 1003 1004 end: 1005 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1006 * during this call, before methods->done is called: dma sync required 1007 * beforehand? */ 1008 usb_transfer_complete(xfer); 1009 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1010 } 1011 1012 /* 1013 * Wait here until controller claims to have an interrupt. 1014 * Then call ehci_intr and return. Use timeout to avoid waiting 1015 * too long. 1016 */ 1017 Static void 1018 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1019 { 1020 int timo; 1021 u_int32_t intrs; 1022 1023 xfer->status = USBD_IN_PROGRESS; 1024 for (timo = xfer->timeout; timo >= 0; timo--) { 1025 usb_delay_ms(&sc->sc_bus, 1); 1026 if (sc->sc_dying) 1027 break; 1028 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1029 sc->sc_eintrs; 1030 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1031 #ifdef EHCI_DEBUG 1032 if (ehcidebug > 15) 1033 ehci_dump_regs(sc); 1034 #endif 1035 if (intrs) { 1036 ehci_intr1(sc); 1037 if (xfer->status != USBD_IN_PROGRESS) 1038 return; 1039 } 1040 } 1041 1042 /* Timeout */ 1043 DPRINTF(("ehci_waitintr: timeout\n")); 1044 xfer->status = USBD_TIMEOUT; 1045 usb_transfer_complete(xfer); 1046 /* XXX should free TD */ 1047 } 1048 1049 Static void 1050 ehci_poll(struct usbd_bus *bus) 1051 { 1052 ehci_softc_t *sc = bus->hci_private; 1053 #ifdef EHCI_DEBUG 1054 static int last; 1055 int new; 1056 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1057 if (new != last) { 1058 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1059 last = new; 1060 } 1061 #endif 1062 1063 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1064 ehci_intr1(sc); 1065 } 1066 1067 void 1068 ehci_childdet(device_t self, device_t child) 1069 { 1070 struct ehci_softc *sc = device_private(self); 1071 1072 KASSERT(sc->sc_child == child); 1073 sc->sc_child = NULL; 1074 } 1075 1076 int 1077 ehci_detach(struct ehci_softc *sc, int flags) 1078 { 1079 int rv = 0; 1080 1081 if (sc->sc_child != NULL) 1082 rv = config_detach(sc->sc_child, flags); 1083 1084 if (rv != 0) 1085 return (rv); 1086 1087 callout_stop(&(sc->sc_tmo_intrlist)); 1088 1089 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1090 1091 /* XXX free other data structures XXX */ 1092 mutex_destroy(&sc->sc_doorbell_lock); 1093 mutex_destroy(&sc->sc_intrhead_lock); 1094 1095 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1096 1097 return (rv); 1098 } 1099 1100 1101 int 1102 ehci_activate(device_t self, enum devact act) 1103 { 1104 struct ehci_softc *sc = device_private(self); 1105 1106 switch (act) { 1107 case DVACT_DEACTIVATE: 1108 sc->sc_dying = 1; 1109 return 0; 1110 default: 1111 return EOPNOTSUPP; 1112 } 1113 } 1114 1115 /* 1116 * Handle suspend/resume. 1117 * 1118 * We need to switch to polling mode here, because this routine is 1119 * called from an interrupt context. This is all right since we 1120 * are almost suspended anyway. 1121 * 1122 * Note that this power handler isn't to be registered directly; the 1123 * bus glue needs to call out to it. 1124 */ 1125 bool 1126 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1127 { 1128 ehci_softc_t *sc = device_private(dv); 1129 int i, s; 1130 uint32_t cmd, hcr; 1131 1132 s = splhardusb(); 1133 1134 sc->sc_bus.use_polling++; 1135 1136 for (i = 1; i <= sc->sc_noport; i++) { 1137 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1138 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1139 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1140 } 1141 1142 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1143 1144 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1145 EOWRITE4(sc, EHCI_USBCMD, cmd); 1146 1147 for (i = 0; i < 100; i++) { 1148 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1149 if (hcr == 0) 1150 break; 1151 1152 usb_delay_ms(&sc->sc_bus, 1); 1153 } 1154 if (hcr != 0) 1155 printf("%s: reset timeout\n", device_xname(dv)); 1156 1157 cmd &= ~EHCI_CMD_RS; 1158 EOWRITE4(sc, EHCI_USBCMD, cmd); 1159 1160 for (i = 0; i < 100; i++) { 1161 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1162 if (hcr == EHCI_STS_HCH) 1163 break; 1164 1165 usb_delay_ms(&sc->sc_bus, 1); 1166 } 1167 if (hcr != EHCI_STS_HCH) 1168 printf("%s: config timeout\n", device_xname(dv)); 1169 1170 sc->sc_bus.use_polling--; 1171 splx(s); 1172 1173 return true; 1174 } 1175 1176 bool 1177 ehci_resume(device_t dv, const pmf_qual_t *qual) 1178 { 1179 ehci_softc_t *sc = device_private(dv); 1180 int i; 1181 uint32_t cmd, hcr; 1182 1183 /* restore things in case the bios sucks */ 1184 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1185 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1186 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1187 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1188 1189 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1190 1191 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1192 1193 hcr = 0; 1194 for (i = 1; i <= sc->sc_noport; i++) { 1195 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1196 if ((cmd & EHCI_PS_PO) == 0 && 1197 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1198 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1199 hcr = 1; 1200 } 1201 } 1202 1203 if (hcr) { 1204 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1205 1206 for (i = 1; i <= sc->sc_noport; i++) { 1207 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1208 if ((cmd & EHCI_PS_PO) == 0 && 1209 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1210 EOWRITE4(sc, EHCI_PORTSC(i), 1211 cmd & ~EHCI_PS_FPR); 1212 } 1213 } 1214 1215 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1216 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1217 1218 for (i = 0; i < 100; i++) { 1219 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1220 if (hcr != EHCI_STS_HCH) 1221 break; 1222 1223 usb_delay_ms(&sc->sc_bus, 1); 1224 } 1225 if (hcr == EHCI_STS_HCH) 1226 printf("%s: config timeout\n", device_xname(dv)); 1227 1228 return true; 1229 } 1230 1231 /* 1232 * Shut down the controller when the system is going down. 1233 */ 1234 bool 1235 ehci_shutdown(device_t self, int flags) 1236 { 1237 ehci_softc_t *sc = device_private(self); 1238 1239 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1240 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1241 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1242 return true; 1243 } 1244 1245 Static usbd_status 1246 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1247 { 1248 struct ehci_softc *sc = bus->hci_private; 1249 usbd_status err; 1250 1251 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1252 if (err == USBD_NOMEM) 1253 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1254 #ifdef EHCI_DEBUG 1255 if (err) 1256 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1257 #endif 1258 return (err); 1259 } 1260 1261 Static void 1262 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1263 { 1264 struct ehci_softc *sc = bus->hci_private; 1265 1266 if (dma->block->flags & USB_DMA_RESERVE) { 1267 usb_reserve_freem(&sc->sc_dma_reserve, 1268 dma); 1269 return; 1270 } 1271 usb_freemem(&sc->sc_bus, dma); 1272 } 1273 1274 Static usbd_xfer_handle 1275 ehci_allocx(struct usbd_bus *bus) 1276 { 1277 struct ehci_softc *sc = bus->hci_private; 1278 usbd_xfer_handle xfer; 1279 1280 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1281 if (xfer != NULL) { 1282 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1283 #ifdef DIAGNOSTIC 1284 if (xfer->busy_free != XFER_FREE) { 1285 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1286 xfer->busy_free); 1287 } 1288 #endif 1289 } else { 1290 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1291 } 1292 if (xfer != NULL) { 1293 memset(xfer, 0, sizeof(struct ehci_xfer)); 1294 #ifdef DIAGNOSTIC 1295 EXFER(xfer)->isdone = 1; 1296 xfer->busy_free = XFER_BUSY; 1297 #endif 1298 } 1299 return (xfer); 1300 } 1301 1302 Static void 1303 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1304 { 1305 struct ehci_softc *sc = bus->hci_private; 1306 1307 #ifdef DIAGNOSTIC 1308 if (xfer->busy_free != XFER_BUSY) { 1309 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1310 xfer->busy_free); 1311 } 1312 xfer->busy_free = XFER_FREE; 1313 if (!EXFER(xfer)->isdone) { 1314 printf("ehci_freex: !isdone\n"); 1315 } 1316 #endif 1317 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1318 } 1319 1320 Static void 1321 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1322 { 1323 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1324 1325 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1326 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1327 #ifdef EHCI_DEBUG 1328 if (ehcidebug) 1329 usbd_dump_pipe(pipe); 1330 #endif 1331 epipe->nexttoggle = 0; 1332 } 1333 1334 Static void 1335 ehci_noop(usbd_pipe_handle pipe) 1336 { 1337 } 1338 1339 #ifdef EHCI_DEBUG 1340 Static void 1341 ehci_dump_regs(ehci_softc_t *sc) 1342 { 1343 int i; 1344 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1345 EOREAD4(sc, EHCI_USBCMD), 1346 EOREAD4(sc, EHCI_USBSTS), 1347 EOREAD4(sc, EHCI_USBINTR)); 1348 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1349 EOREAD4(sc, EHCI_FRINDEX), 1350 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1351 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1352 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1353 for (i = 1; i <= sc->sc_noport; i++) 1354 printf("port %d status=0x%08x\n", i, 1355 EOREAD4(sc, EHCI_PORTSC(i))); 1356 } 1357 1358 /* 1359 * Unused function - this is meant to be called from a kernel 1360 * debugger. 1361 */ 1362 void 1363 ehci_dump(void) 1364 { 1365 ehci_dump_regs(theehci); 1366 } 1367 1368 Static void 1369 ehci_dump_link(ehci_link_t link, int type) 1370 { 1371 link = le32toh(link); 1372 printf("0x%08x", link); 1373 if (link & EHCI_LINK_TERMINATE) 1374 printf("<T>"); 1375 else { 1376 printf("<"); 1377 if (type) { 1378 switch (EHCI_LINK_TYPE(link)) { 1379 case EHCI_LINK_ITD: printf("ITD"); break; 1380 case EHCI_LINK_QH: printf("QH"); break; 1381 case EHCI_LINK_SITD: printf("SITD"); break; 1382 case EHCI_LINK_FSTN: printf("FSTN"); break; 1383 } 1384 } 1385 printf(">"); 1386 } 1387 } 1388 1389 Static void 1390 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1391 { 1392 int i; 1393 u_int32_t stop; 1394 1395 stop = 0; 1396 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1397 ehci_dump_sqtd(sqtd); 1398 usb_syncmem(&sqtd->dma, 1399 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1400 sizeof(sqtd->qtd), 1401 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1402 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1403 usb_syncmem(&sqtd->dma, 1404 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1405 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1406 } 1407 if (sqtd) 1408 printf("dump aborted, too many TDs\n"); 1409 } 1410 1411 Static void 1412 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1413 { 1414 usb_syncmem(&sqtd->dma, sqtd->offs, 1415 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1416 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1417 ehci_dump_qtd(&sqtd->qtd); 1418 usb_syncmem(&sqtd->dma, sqtd->offs, 1419 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1420 } 1421 1422 Static void 1423 ehci_dump_qtd(ehci_qtd_t *qtd) 1424 { 1425 u_int32_t s; 1426 char sbuf[128]; 1427 1428 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1429 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1430 printf("\n"); 1431 s = le32toh(qtd->qtd_status); 1432 snprintb(sbuf, sizeof(sbuf), 1433 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1434 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1435 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1436 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1437 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1438 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1439 EHCI_QTD_GET_PID(s), sbuf); 1440 for (s = 0; s < 5; s++) 1441 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1442 } 1443 1444 Static void 1445 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1446 { 1447 ehci_qh_t *qh = &sqh->qh; 1448 u_int32_t endp, endphub; 1449 1450 usb_syncmem(&sqh->dma, sqh->offs, 1451 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1452 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1453 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1454 endp = le32toh(qh->qh_endp); 1455 printf(" endp=0x%08x\n", endp); 1456 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1457 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1458 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1459 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1460 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1461 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1462 EHCI_QH_GET_NRL(endp)); 1463 endphub = le32toh(qh->qh_endphub); 1464 printf(" endphub=0x%08x\n", endphub); 1465 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1466 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1467 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1468 EHCI_QH_GET_MULT(endphub)); 1469 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1470 printf("Overlay qTD:\n"); 1471 ehci_dump_qtd(&qh->qh_qtd); 1472 usb_syncmem(&sqh->dma, sqh->offs, 1473 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1474 } 1475 1476 #if notyet 1477 Static void 1478 ehci_dump_itd(struct ehci_soft_itd *itd) 1479 { 1480 ehci_isoc_trans_t t; 1481 ehci_isoc_bufr_ptr_t b, b2, b3; 1482 int i; 1483 1484 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1485 1486 for (i = 0; i < 8;i++) { 1487 t = le32toh(itd->itd.itd_ctl[i]); 1488 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1489 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1490 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1491 EHCI_ITD_GET_OFFS(t)); 1492 } 1493 printf("ITDbufr: "); 1494 for (i = 0; i < 7; i++) 1495 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1496 1497 b = le32toh(itd->itd.itd_bufr[0]); 1498 b2 = le32toh(itd->itd.itd_bufr[1]); 1499 b3 = le32toh(itd->itd.itd_bufr[2]); 1500 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1501 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1502 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1503 } 1504 1505 Static void 1506 ehci_dump_sitd(struct ehci_soft_itd *itd) 1507 { 1508 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1509 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1510 itd->xfer_next, itd->physaddr, itd->slot); 1511 } 1512 #endif 1513 1514 #ifdef DIAGNOSTIC 1515 Static void 1516 ehci_dump_exfer(struct ehci_xfer *ex) 1517 { 1518 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1519 } 1520 #endif 1521 #endif 1522 1523 Static usbd_status 1524 ehci_open(usbd_pipe_handle pipe) 1525 { 1526 usbd_device_handle dev = pipe->device; 1527 ehci_softc_t *sc = dev->bus->hci_private; 1528 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1529 u_int8_t addr = dev->address; 1530 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1531 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1532 ehci_soft_qh_t *sqh; 1533 usbd_status err; 1534 int s; 1535 int ival, speed, naks; 1536 int hshubaddr, hshubport; 1537 1538 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1539 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1540 1541 if (dev->myhsport) { 1542 hshubaddr = dev->myhsport->parent->address; 1543 hshubport = dev->myhsport->portno; 1544 } else { 1545 hshubaddr = 0; 1546 hshubport = 0; 1547 } 1548 1549 if (sc->sc_dying) 1550 return (USBD_IOERROR); 1551 1552 epipe->nexttoggle = 0; 1553 1554 if (addr == sc->sc_addr) { 1555 switch (ed->bEndpointAddress) { 1556 case USB_CONTROL_ENDPOINT: 1557 pipe->methods = &ehci_root_ctrl_methods; 1558 break; 1559 case UE_DIR_IN | EHCI_INTR_ENDPT: 1560 pipe->methods = &ehci_root_intr_methods; 1561 break; 1562 default: 1563 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1564 ed->bEndpointAddress)); 1565 return (USBD_INVAL); 1566 } 1567 return (USBD_NORMAL_COMPLETION); 1568 } 1569 1570 /* XXX All this stuff is only valid for async. */ 1571 switch (dev->speed) { 1572 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1573 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1574 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1575 default: panic("ehci_open: bad device speed %d", dev->speed); 1576 } 1577 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1578 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1579 "isoc endpoint.\n"); 1580 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1581 "attached to a USB2 hub, and transaction translations are " 1582 "not yet supported.\n"); 1583 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1584 "root hub instead.\n"); 1585 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1586 hshubaddr, hshubport)); 1587 return USBD_INVAL; 1588 } 1589 1590 naks = 8; /* XXX */ 1591 1592 /* Allocate sqh for everything, save isoc xfers */ 1593 if (xfertype != UE_ISOCHRONOUS) { 1594 sqh = ehci_alloc_sqh(sc); 1595 if (sqh == NULL) 1596 return (USBD_NOMEM); 1597 /* qh_link filled when the QH is added */ 1598 sqh->qh.qh_endp = htole32( 1599 EHCI_QH_SET_ADDR(addr) | 1600 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1601 EHCI_QH_SET_EPS(speed) | 1602 EHCI_QH_DTC | 1603 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1604 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1605 EHCI_QH_CTL : 0) | 1606 EHCI_QH_SET_NRL(naks) 1607 ); 1608 sqh->qh.qh_endphub = htole32( 1609 EHCI_QH_SET_MULT(1) | 1610 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1611 ); 1612 if (speed != EHCI_QH_SPEED_HIGH) 1613 sqh->qh.qh_endphub |= htole32( 1614 EHCI_QH_SET_PORT(hshubport) | 1615 EHCI_QH_SET_HUBA(hshubaddr) | 1616 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1617 ); 1618 sqh->qh.qh_curqtd = EHCI_NULL; 1619 /* Fill the overlay qTD */ 1620 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1621 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1622 sqh->qh.qh_qtd.qtd_status = htole32(0); 1623 1624 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1625 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1626 epipe->sqh = sqh; 1627 } else { 1628 sqh = NULL; 1629 } /*xfertype == UE_ISOC*/ 1630 1631 switch (xfertype) { 1632 case UE_CONTROL: 1633 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1634 0, &epipe->u.ctl.reqdma); 1635 #ifdef EHCI_DEBUG 1636 if (err) 1637 printf("ehci_open: usb_allocmem()=%d\n", err); 1638 #endif 1639 if (err) 1640 goto bad; 1641 pipe->methods = &ehci_device_ctrl_methods; 1642 s = splusb(); 1643 ehci_add_qh(sqh, sc->sc_async_head); 1644 splx(s); 1645 break; 1646 case UE_BULK: 1647 pipe->methods = &ehci_device_bulk_methods; 1648 s = splusb(); 1649 ehci_add_qh(sqh, sc->sc_async_head); 1650 splx(s); 1651 break; 1652 case UE_INTERRUPT: 1653 pipe->methods = &ehci_device_intr_methods; 1654 ival = pipe->interval; 1655 if (ival == USBD_DEFAULT_INTERVAL) { 1656 if (speed == EHCI_QH_SPEED_HIGH) { 1657 if (ed->bInterval > 16) { 1658 /* 1659 * illegal with high-speed, but there 1660 * were documentation bugs in the spec, 1661 * so be generous 1662 */ 1663 ival = 256; 1664 } else 1665 ival = (1 << (ed->bInterval - 1)) / 8; 1666 } else 1667 ival = ed->bInterval; 1668 } 1669 err = ehci_device_setintr(sc, sqh, ival); 1670 if (err) 1671 goto bad; 1672 break; 1673 case UE_ISOCHRONOUS: 1674 pipe->methods = &ehci_device_isoc_methods; 1675 if (ed->bInterval == 0 || ed->bInterval > 16) { 1676 printf("ehci: opening pipe with invalid bInterval\n"); 1677 err = USBD_INVAL; 1678 goto bad; 1679 } 1680 if (UGETW(ed->wMaxPacketSize) == 0) { 1681 printf("ehci: zero length endpoint open request\n"); 1682 err = USBD_INVAL; 1683 goto bad; 1684 } 1685 epipe->u.isoc.next_frame = 0; 1686 epipe->u.isoc.cur_xfers = 0; 1687 break; 1688 default: 1689 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1690 err = USBD_INVAL; 1691 goto bad; 1692 } 1693 return (USBD_NORMAL_COMPLETION); 1694 1695 bad: 1696 if (sqh != NULL) 1697 ehci_free_sqh(sc, sqh); 1698 return (err); 1699 } 1700 1701 /* 1702 * Add an ED to the schedule. Called at splusb(). 1703 */ 1704 Static void 1705 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1706 { 1707 SPLUSBCHECK; 1708 1709 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1710 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1711 sqh->next = head->next; 1712 sqh->qh.qh_link = head->qh.qh_link; 1713 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1714 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1715 head->next = sqh; 1716 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1717 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1718 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1719 1720 #ifdef EHCI_DEBUG 1721 if (ehcidebug > 5) { 1722 printf("ehci_add_qh:\n"); 1723 ehci_dump_sqh(sqh); 1724 } 1725 #endif 1726 } 1727 1728 /* 1729 * Remove an ED from the schedule. Called at splusb(). 1730 */ 1731 Static void 1732 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1733 { 1734 ehci_soft_qh_t *p; 1735 1736 SPLUSBCHECK; 1737 /* XXX */ 1738 for (p = head; p != NULL && p->next != sqh; p = p->next) 1739 ; 1740 if (p == NULL) 1741 panic("ehci_rem_qh: ED not found"); 1742 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1743 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1744 p->next = sqh->next; 1745 p->qh.qh_link = sqh->qh.qh_link; 1746 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1747 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1748 1749 ehci_sync_hc(sc); 1750 } 1751 1752 Static void 1753 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1754 { 1755 int i; 1756 u_int32_t status; 1757 1758 /* Save toggle bit and ping status. */ 1759 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1760 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1761 status = sqh->qh.qh_qtd.qtd_status & 1762 htole32(EHCI_QTD_TOGGLE_MASK | 1763 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1764 /* Set HALTED to make hw leave it alone. */ 1765 sqh->qh.qh_qtd.qtd_status = 1766 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1767 usb_syncmem(&sqh->dma, 1768 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1769 sizeof(sqh->qh.qh_qtd.qtd_status), 1770 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1771 sqh->qh.qh_curqtd = 0; 1772 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1773 sqh->qh.qh_qtd.qtd_altnext = 0; 1774 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1775 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1776 sqh->sqtd = sqtd; 1777 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1778 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1779 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1780 sqh->qh.qh_qtd.qtd_status = status; 1781 usb_syncmem(&sqh->dma, 1782 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1783 sizeof(sqh->qh.qh_qtd.qtd_status), 1784 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1785 } 1786 1787 /* 1788 * Ensure that the HC has released all references to the QH. We do this 1789 * by asking for a Async Advance Doorbell interrupt and then we wait for 1790 * the interrupt. 1791 * To make this easier we first obtain exclusive use of the doorbell. 1792 */ 1793 Static void 1794 ehci_sync_hc(ehci_softc_t *sc) 1795 { 1796 int s, error; 1797 1798 if (sc->sc_dying) { 1799 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1800 return; 1801 } 1802 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1803 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */ 1804 s = splhardusb(); 1805 /* ask for doorbell */ 1806 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1807 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1808 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1809 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1810 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1811 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1812 splx(s); 1813 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */ 1814 #ifdef DIAGNOSTIC 1815 if (error) 1816 printf("ehci_sync_hc: tsleep() = %d\n", error); 1817 #endif 1818 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1819 } 1820 1821 /*Call at splusb*/ 1822 Static void 1823 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1824 { 1825 struct ehci_soft_itd *itd, *prev; 1826 1827 prev = NULL; 1828 1829 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1830 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1831 1832 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1833 prev = itd->u.frame_list.prev; 1834 /* Unlink itd from hardware chain, or frame array */ 1835 if (prev == NULL) { /* We're at the table head */ 1836 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1837 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1838 usb_syncmem(&sc->sc_fldma, 1839 sizeof(ehci_link_t) * itd->slot, 1840 sizeof(ehci_link_t), 1841 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1842 1843 if (itd->u.frame_list.next != NULL) 1844 itd->u.frame_list.next->u.frame_list.prev = NULL; 1845 } else { 1846 /* XXX this part is untested... */ 1847 prev->itd.itd_next = itd->itd.itd_next; 1848 usb_syncmem(&itd->dma, 1849 itd->offs + offsetof(ehci_itd_t, itd_next), 1850 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1851 1852 prev->u.frame_list.next = itd->u.frame_list.next; 1853 if (itd->u.frame_list.next != NULL) 1854 itd->u.frame_list.next->u.frame_list.prev = prev; 1855 } 1856 } 1857 1858 prev = NULL; 1859 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1860 if (prev != NULL) 1861 ehci_free_itd(sc, prev); 1862 prev = itd; 1863 } 1864 if (prev) 1865 ehci_free_itd(sc, prev); 1866 exfer->itdstart = NULL; 1867 exfer->itdend = NULL; 1868 } 1869 1870 /***********/ 1871 1872 /* 1873 * Data structures and routines to emulate the root hub. 1874 */ 1875 Static usb_device_descriptor_t ehci_devd = { 1876 USB_DEVICE_DESCRIPTOR_SIZE, 1877 UDESC_DEVICE, /* type */ 1878 {0x00, 0x02}, /* USB version */ 1879 UDCLASS_HUB, /* class */ 1880 UDSUBCLASS_HUB, /* subclass */ 1881 UDPROTO_HSHUBSTT, /* protocol */ 1882 64, /* max packet */ 1883 {0},{0},{0x00,0x01}, /* device id */ 1884 1,2,0, /* string indicies */ 1885 1 /* # of configurations */ 1886 }; 1887 1888 Static const usb_device_qualifier_t ehci_odevd = { 1889 USB_DEVICE_DESCRIPTOR_SIZE, 1890 UDESC_DEVICE_QUALIFIER, /* type */ 1891 {0x00, 0x02}, /* USB version */ 1892 UDCLASS_HUB, /* class */ 1893 UDSUBCLASS_HUB, /* subclass */ 1894 UDPROTO_FSHUB, /* protocol */ 1895 64, /* max packet */ 1896 1, /* # of configurations */ 1897 0 1898 }; 1899 1900 Static const usb_config_descriptor_t ehci_confd = { 1901 USB_CONFIG_DESCRIPTOR_SIZE, 1902 UDESC_CONFIG, 1903 {USB_CONFIG_DESCRIPTOR_SIZE + 1904 USB_INTERFACE_DESCRIPTOR_SIZE + 1905 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1906 1, 1907 1, 1908 0, 1909 UC_ATTR_MBO | UC_SELF_POWERED, 1910 0 /* max power */ 1911 }; 1912 1913 Static const usb_interface_descriptor_t ehci_ifcd = { 1914 USB_INTERFACE_DESCRIPTOR_SIZE, 1915 UDESC_INTERFACE, 1916 0, 1917 0, 1918 1, 1919 UICLASS_HUB, 1920 UISUBCLASS_HUB, 1921 UIPROTO_HSHUBSTT, 1922 0 1923 }; 1924 1925 Static const usb_endpoint_descriptor_t ehci_endpd = { 1926 USB_ENDPOINT_DESCRIPTOR_SIZE, 1927 UDESC_ENDPOINT, 1928 UE_DIR_IN | EHCI_INTR_ENDPT, 1929 UE_INTERRUPT, 1930 {8, 0}, /* max packet */ 1931 12 1932 }; 1933 1934 Static const usb_hub_descriptor_t ehci_hubd = { 1935 USB_HUB_DESCRIPTOR_SIZE, 1936 UDESC_HUB, 1937 0, 1938 {0,0}, 1939 0, 1940 0, 1941 {""}, 1942 {""}, 1943 }; 1944 1945 /* 1946 * Simulate a hardware hub by handling all the necessary requests. 1947 */ 1948 Static usbd_status 1949 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1950 { 1951 usbd_status err; 1952 1953 /* Insert last in queue. */ 1954 err = usb_insert_transfer(xfer); 1955 if (err) 1956 return (err); 1957 1958 /* Pipe isn't running, start first */ 1959 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1960 } 1961 1962 Static usbd_status 1963 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1964 { 1965 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1966 usb_device_request_t *req; 1967 void *buf = NULL; 1968 int port, i; 1969 int s, len, value, index, l, totlen = 0; 1970 usb_port_status_t ps; 1971 usb_hub_descriptor_t hubd; 1972 usbd_status err; 1973 u_int32_t v; 1974 1975 if (sc->sc_dying) 1976 return (USBD_IOERROR); 1977 1978 #ifdef DIAGNOSTIC 1979 if (!(xfer->rqflags & URQ_REQUEST)) 1980 /* XXX panic */ 1981 return (USBD_INVAL); 1982 #endif 1983 req = &xfer->request; 1984 1985 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1986 req->bmRequestType, req->bRequest)); 1987 1988 len = UGETW(req->wLength); 1989 value = UGETW(req->wValue); 1990 index = UGETW(req->wIndex); 1991 1992 if (len != 0) 1993 buf = KERNADDR(&xfer->dmabuf, 0); 1994 1995 #define C(x,y) ((x) | ((y) << 8)) 1996 switch(C(req->bRequest, req->bmRequestType)) { 1997 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1998 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1999 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2000 /* 2001 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2002 * for the integrated root hub. 2003 */ 2004 break; 2005 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2006 if (len > 0) { 2007 *(u_int8_t *)buf = sc->sc_conf; 2008 totlen = 1; 2009 } 2010 break; 2011 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2012 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2013 if (len == 0) 2014 break; 2015 switch(value >> 8) { 2016 case UDESC_DEVICE: 2017 if ((value & 0xff) != 0) { 2018 err = USBD_IOERROR; 2019 goto ret; 2020 } 2021 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2022 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2023 memcpy(buf, &ehci_devd, l); 2024 break; 2025 /* 2026 * We can't really operate at another speed, but the spec says 2027 * we need this descriptor. 2028 */ 2029 case UDESC_DEVICE_QUALIFIER: 2030 if ((value & 0xff) != 0) { 2031 err = USBD_IOERROR; 2032 goto ret; 2033 } 2034 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2035 memcpy(buf, &ehci_odevd, l); 2036 break; 2037 /* 2038 * We can't really operate at another speed, but the spec says 2039 * we need this descriptor. 2040 */ 2041 case UDESC_OTHER_SPEED_CONFIGURATION: 2042 case UDESC_CONFIG: 2043 if ((value & 0xff) != 0) { 2044 err = USBD_IOERROR; 2045 goto ret; 2046 } 2047 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2048 memcpy(buf, &ehci_confd, l); 2049 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2050 value >> 8; 2051 buf = (char *)buf + l; 2052 len -= l; 2053 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2054 totlen += l; 2055 memcpy(buf, &ehci_ifcd, l); 2056 buf = (char *)buf + l; 2057 len -= l; 2058 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2059 totlen += l; 2060 memcpy(buf, &ehci_endpd, l); 2061 break; 2062 case UDESC_STRING: 2063 #define sd ((usb_string_descriptor_t *)buf) 2064 switch (value & 0xff) { 2065 case 0: /* Language table */ 2066 totlen = usb_makelangtbl(sd, len); 2067 break; 2068 case 1: /* Vendor */ 2069 totlen = usb_makestrdesc(sd, len, 2070 sc->sc_vendor); 2071 break; 2072 case 2: /* Product */ 2073 totlen = usb_makestrdesc(sd, len, 2074 "EHCI root hub"); 2075 break; 2076 } 2077 #undef sd 2078 break; 2079 default: 2080 err = USBD_IOERROR; 2081 goto ret; 2082 } 2083 break; 2084 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2085 if (len > 0) { 2086 *(u_int8_t *)buf = 0; 2087 totlen = 1; 2088 } 2089 break; 2090 case C(UR_GET_STATUS, UT_READ_DEVICE): 2091 if (len > 1) { 2092 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2093 totlen = 2; 2094 } 2095 break; 2096 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2097 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2098 if (len > 1) { 2099 USETW(((usb_status_t *)buf)->wStatus, 0); 2100 totlen = 2; 2101 } 2102 break; 2103 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2104 if (value >= USB_MAX_DEVICES) { 2105 err = USBD_IOERROR; 2106 goto ret; 2107 } 2108 sc->sc_addr = value; 2109 break; 2110 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2111 if (value != 0 && value != 1) { 2112 err = USBD_IOERROR; 2113 goto ret; 2114 } 2115 sc->sc_conf = value; 2116 break; 2117 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2118 break; 2119 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2120 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2121 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2122 err = USBD_IOERROR; 2123 goto ret; 2124 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2125 break; 2126 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2127 break; 2128 /* Hub requests */ 2129 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2130 break; 2131 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2132 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2133 "port=%d feature=%d\n", 2134 index, value)); 2135 if (index < 1 || index > sc->sc_noport) { 2136 err = USBD_IOERROR; 2137 goto ret; 2138 } 2139 port = EHCI_PORTSC(index); 2140 v = EOREAD4(sc, port); 2141 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2142 v &= ~EHCI_PS_CLEAR; 2143 switch(value) { 2144 case UHF_PORT_ENABLE: 2145 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2146 break; 2147 case UHF_PORT_SUSPEND: 2148 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2149 break; 2150 v &= ~EHCI_PS_SUSP; 2151 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2152 /* see USB2 spec ch. 7.1.7.7 */ 2153 usb_delay_ms(&sc->sc_bus, 20); 2154 EOWRITE4(sc, port, v); 2155 usb_delay_ms(&sc->sc_bus, 2); 2156 #ifdef DEBUG 2157 v = EOREAD4(sc, port); 2158 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2159 printf("ehci: resume failed: %x\n", v); 2160 #endif 2161 break; 2162 case UHF_PORT_POWER: 2163 if (sc->sc_hasppc) 2164 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2165 break; 2166 case UHF_PORT_TEST: 2167 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2168 "%d\n", index)); 2169 break; 2170 case UHF_PORT_INDICATOR: 2171 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2172 "%d\n", index)); 2173 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2174 break; 2175 case UHF_C_PORT_CONNECTION: 2176 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2177 break; 2178 case UHF_C_PORT_ENABLE: 2179 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2180 break; 2181 case UHF_C_PORT_SUSPEND: 2182 /* how? */ 2183 break; 2184 case UHF_C_PORT_OVER_CURRENT: 2185 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2186 break; 2187 case UHF_C_PORT_RESET: 2188 sc->sc_isreset[index] = 0; 2189 break; 2190 default: 2191 err = USBD_IOERROR; 2192 goto ret; 2193 } 2194 #if 0 2195 switch(value) { 2196 case UHF_C_PORT_CONNECTION: 2197 case UHF_C_PORT_ENABLE: 2198 case UHF_C_PORT_SUSPEND: 2199 case UHF_C_PORT_OVER_CURRENT: 2200 case UHF_C_PORT_RESET: 2201 default: 2202 break; 2203 } 2204 #endif 2205 break; 2206 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2207 if (len == 0) 2208 break; 2209 if ((value & 0xff) != 0) { 2210 err = USBD_IOERROR; 2211 goto ret; 2212 } 2213 hubd = ehci_hubd; 2214 hubd.bNbrPorts = sc->sc_noport; 2215 v = EOREAD4(sc, EHCI_HCSPARAMS); 2216 USETW(hubd.wHubCharacteristics, 2217 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2218 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2219 ? UHD_PORT_IND : 0); 2220 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2221 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2222 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2223 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2224 l = min(len, hubd.bDescLength); 2225 totlen = l; 2226 memcpy(buf, &hubd, l); 2227 break; 2228 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2229 if (len != 4) { 2230 err = USBD_IOERROR; 2231 goto ret; 2232 } 2233 memset(buf, 0, len); /* ? XXX */ 2234 totlen = len; 2235 break; 2236 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2237 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2238 index)); 2239 if (index < 1 || index > sc->sc_noport) { 2240 err = USBD_IOERROR; 2241 goto ret; 2242 } 2243 if (len != 4) { 2244 err = USBD_IOERROR; 2245 goto ret; 2246 } 2247 v = EOREAD4(sc, EHCI_PORTSC(index)); 2248 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2249 v)); 2250 i = UPS_HIGH_SPEED; 2251 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2252 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2253 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2254 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2255 if (v & EHCI_PS_PR) i |= UPS_RESET; 2256 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2257 USETW(ps.wPortStatus, i); 2258 i = 0; 2259 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2260 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2261 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2262 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2263 USETW(ps.wPortChange, i); 2264 l = min(len, sizeof ps); 2265 memcpy(buf, &ps, l); 2266 totlen = l; 2267 break; 2268 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2269 err = USBD_IOERROR; 2270 goto ret; 2271 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2272 break; 2273 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2274 if (index < 1 || index > sc->sc_noport) { 2275 err = USBD_IOERROR; 2276 goto ret; 2277 } 2278 port = EHCI_PORTSC(index); 2279 v = EOREAD4(sc, port); 2280 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2281 v &= ~EHCI_PS_CLEAR; 2282 switch(value) { 2283 case UHF_PORT_ENABLE: 2284 EOWRITE4(sc, port, v | EHCI_PS_PE); 2285 break; 2286 case UHF_PORT_SUSPEND: 2287 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2288 break; 2289 case UHF_PORT_RESET: 2290 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2291 index)); 2292 if (EHCI_PS_IS_LOWSPEED(v)) { 2293 /* Low speed device, give up ownership. */ 2294 ehci_disown(sc, index, 1); 2295 break; 2296 } 2297 /* Start reset sequence. */ 2298 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2299 EOWRITE4(sc, port, v | EHCI_PS_PR); 2300 /* Wait for reset to complete. */ 2301 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2302 if (sc->sc_dying) { 2303 err = USBD_IOERROR; 2304 goto ret; 2305 } 2306 /* Terminate reset sequence. */ 2307 EOWRITE4(sc, port, v); 2308 /* Wait for HC to complete reset. */ 2309 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2310 if (sc->sc_dying) { 2311 err = USBD_IOERROR; 2312 goto ret; 2313 } 2314 v = EOREAD4(sc, port); 2315 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2316 if (v & EHCI_PS_PR) { 2317 printf("%s: port reset timeout\n", 2318 device_xname(sc->sc_dev)); 2319 return (USBD_TIMEOUT); 2320 } 2321 if (!(v & EHCI_PS_PE)) { 2322 /* Not a high speed device, give up ownership.*/ 2323 ehci_disown(sc, index, 0); 2324 break; 2325 } 2326 sc->sc_isreset[index] = 1; 2327 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2328 index, v)); 2329 break; 2330 case UHF_PORT_POWER: 2331 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2332 "%d (has PPC = %d)\n", index, 2333 sc->sc_hasppc)); 2334 if (sc->sc_hasppc) 2335 EOWRITE4(sc, port, v | EHCI_PS_PP); 2336 break; 2337 case UHF_PORT_TEST: 2338 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2339 "%d\n", index)); 2340 break; 2341 case UHF_PORT_INDICATOR: 2342 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2343 "%d\n", index)); 2344 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2345 break; 2346 default: 2347 err = USBD_IOERROR; 2348 goto ret; 2349 } 2350 break; 2351 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2352 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2353 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2354 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2355 break; 2356 default: 2357 err = USBD_IOERROR; 2358 goto ret; 2359 } 2360 xfer->actlen = totlen; 2361 err = USBD_NORMAL_COMPLETION; 2362 ret: 2363 xfer->status = err; 2364 s = splusb(); 2365 usb_transfer_complete(xfer); 2366 splx(s); 2367 return (USBD_IN_PROGRESS); 2368 } 2369 2370 Static void 2371 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2372 { 2373 int port; 2374 u_int32_t v; 2375 2376 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2377 #ifdef DIAGNOSTIC 2378 if (sc->sc_npcomp != 0) { 2379 int i = (index-1) / sc->sc_npcomp; 2380 if (i >= sc->sc_ncomp) 2381 printf("%s: strange port\n", 2382 device_xname(sc->sc_dev)); 2383 else 2384 printf("%s: handing over %s speed device on " 2385 "port %d to %s\n", 2386 device_xname(sc->sc_dev), 2387 lowspeed ? "low" : "full", 2388 index, device_xname(sc->sc_comps[i])); 2389 } else { 2390 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2391 } 2392 #endif 2393 port = EHCI_PORTSC(index); 2394 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2395 EOWRITE4(sc, port, v | EHCI_PS_PO); 2396 } 2397 2398 /* Abort a root control request. */ 2399 Static void 2400 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2401 { 2402 /* Nothing to do, all transfers are synchronous. */ 2403 } 2404 2405 /* Close the root pipe. */ 2406 Static void 2407 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2408 { 2409 DPRINTF(("ehci_root_ctrl_close\n")); 2410 /* Nothing to do. */ 2411 } 2412 2413 Static void 2414 ehci_root_intr_done(usbd_xfer_handle xfer) 2415 { 2416 xfer->hcpriv = NULL; 2417 } 2418 2419 Static usbd_status 2420 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2421 { 2422 usbd_status err; 2423 2424 /* Insert last in queue. */ 2425 err = usb_insert_transfer(xfer); 2426 if (err) 2427 return (err); 2428 2429 /* Pipe isn't running, start first */ 2430 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2431 } 2432 2433 Static usbd_status 2434 ehci_root_intr_start(usbd_xfer_handle xfer) 2435 { 2436 usbd_pipe_handle pipe = xfer->pipe; 2437 ehci_softc_t *sc = pipe->device->bus->hci_private; 2438 2439 if (sc->sc_dying) 2440 return (USBD_IOERROR); 2441 2442 sc->sc_intrxfer = xfer; 2443 2444 return (USBD_IN_PROGRESS); 2445 } 2446 2447 /* Abort a root interrupt request. */ 2448 Static void 2449 ehci_root_intr_abort(usbd_xfer_handle xfer) 2450 { 2451 int s; 2452 2453 if (xfer->pipe->intrxfer == xfer) { 2454 DPRINTF(("ehci_root_intr_abort: remove\n")); 2455 xfer->pipe->intrxfer = NULL; 2456 } 2457 xfer->status = USBD_CANCELLED; 2458 s = splusb(); 2459 usb_transfer_complete(xfer); 2460 splx(s); 2461 } 2462 2463 /* Close the root pipe. */ 2464 Static void 2465 ehci_root_intr_close(usbd_pipe_handle pipe) 2466 { 2467 ehci_softc_t *sc = pipe->device->bus->hci_private; 2468 2469 DPRINTF(("ehci_root_intr_close\n")); 2470 2471 sc->sc_intrxfer = NULL; 2472 } 2473 2474 Static void 2475 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2476 { 2477 xfer->hcpriv = NULL; 2478 } 2479 2480 /************************/ 2481 2482 Static ehci_soft_qh_t * 2483 ehci_alloc_sqh(ehci_softc_t *sc) 2484 { 2485 ehci_soft_qh_t *sqh; 2486 usbd_status err; 2487 int i, offs; 2488 usb_dma_t dma; 2489 2490 if (sc->sc_freeqhs == NULL) { 2491 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2492 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2493 EHCI_PAGE_SIZE, &dma); 2494 #ifdef EHCI_DEBUG 2495 if (err) 2496 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2497 #endif 2498 if (err) 2499 return (NULL); 2500 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2501 offs = i * EHCI_SQH_SIZE; 2502 sqh = KERNADDR(&dma, offs); 2503 sqh->physaddr = DMAADDR(&dma, offs); 2504 sqh->dma = dma; 2505 sqh->offs = offs; 2506 sqh->next = sc->sc_freeqhs; 2507 sc->sc_freeqhs = sqh; 2508 } 2509 } 2510 sqh = sc->sc_freeqhs; 2511 sc->sc_freeqhs = sqh->next; 2512 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2513 sqh->next = NULL; 2514 return (sqh); 2515 } 2516 2517 Static void 2518 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2519 { 2520 sqh->next = sc->sc_freeqhs; 2521 sc->sc_freeqhs = sqh; 2522 } 2523 2524 Static ehci_soft_qtd_t * 2525 ehci_alloc_sqtd(ehci_softc_t *sc) 2526 { 2527 ehci_soft_qtd_t *sqtd; 2528 usbd_status err; 2529 int i, offs; 2530 usb_dma_t dma; 2531 int s; 2532 2533 if (sc->sc_freeqtds == NULL) { 2534 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2535 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2536 EHCI_PAGE_SIZE, &dma); 2537 #ifdef EHCI_DEBUG 2538 if (err) 2539 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2540 #endif 2541 if (err) 2542 return (NULL); 2543 s = splusb(); 2544 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2545 offs = i * EHCI_SQTD_SIZE; 2546 sqtd = KERNADDR(&dma, offs); 2547 sqtd->physaddr = DMAADDR(&dma, offs); 2548 sqtd->dma = dma; 2549 sqtd->offs = offs; 2550 sqtd->nextqtd = sc->sc_freeqtds; 2551 sc->sc_freeqtds = sqtd; 2552 } 2553 splx(s); 2554 } 2555 2556 s = splusb(); 2557 sqtd = sc->sc_freeqtds; 2558 sc->sc_freeqtds = sqtd->nextqtd; 2559 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2560 sqtd->nextqtd = NULL; 2561 sqtd->xfer = NULL; 2562 splx(s); 2563 2564 return (sqtd); 2565 } 2566 2567 Static void 2568 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2569 { 2570 int s; 2571 2572 s = splusb(); 2573 sqtd->nextqtd = sc->sc_freeqtds; 2574 sc->sc_freeqtds = sqtd; 2575 splx(s); 2576 } 2577 2578 Static usbd_status 2579 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2580 int alen, int rd, usbd_xfer_handle xfer, 2581 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2582 { 2583 ehci_soft_qtd_t *next, *cur; 2584 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2585 u_int32_t qtdstatus; 2586 int len, curlen, mps; 2587 int i, tog; 2588 usb_dma_t *dma = &xfer->dmabuf; 2589 u_int16_t flags = xfer->flags; 2590 2591 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2592 2593 len = alen; 2594 dataphys = DMAADDR(dma, 0); 2595 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2596 qtdstatus = EHCI_QTD_ACTIVE | 2597 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2598 EHCI_QTD_SET_CERR(3) 2599 /* IOC set below */ 2600 /* BYTES set below */ 2601 ; 2602 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2603 tog = epipe->nexttoggle; 2604 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2605 2606 cur = ehci_alloc_sqtd(sc); 2607 *sp = cur; 2608 if (cur == NULL) 2609 goto nomem; 2610 2611 usb_syncmem(dma, 0, alen, 2612 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2613 for (;;) { 2614 dataphyspage = EHCI_PAGE(dataphys); 2615 /* The EHCI hardware can handle at most 5 pages. */ 2616 if (dataphyslastpage - dataphyspage < 2617 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2618 /* we can handle it in this QTD */ 2619 curlen = len; 2620 } else { 2621 /* must use multiple TDs, fill as much as possible. */ 2622 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2623 EHCI_PAGE_OFFSET(dataphys); 2624 #ifdef DIAGNOSTIC 2625 if (curlen > len) { 2626 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2627 "len=0x%x offs=0x%x\n", curlen, len, 2628 EHCI_PAGE_OFFSET(dataphys)); 2629 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2630 dataphyslastpage, dataphyspage, 2631 dataphys); 2632 curlen = len; 2633 } 2634 #endif 2635 /* the length must be a multiple of the max size */ 2636 curlen -= curlen % mps; 2637 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2638 "curlen=%d\n", curlen)); 2639 #ifdef DIAGNOSTIC 2640 if (curlen == 0) 2641 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2642 #endif 2643 } 2644 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2645 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2646 dataphys, dataphyslastpage, 2647 len, curlen)); 2648 len -= curlen; 2649 2650 /* 2651 * Allocate another transfer if there's more data left, 2652 * or if force last short transfer flag is set and we're 2653 * allocating a multiple of the max packet size. 2654 */ 2655 if (len != 0 || 2656 ((curlen % mps) == 0 && !rd && curlen != 0 && 2657 (flags & USBD_FORCE_SHORT_XFER))) { 2658 next = ehci_alloc_sqtd(sc); 2659 if (next == NULL) 2660 goto nomem; 2661 nextphys = htole32(next->physaddr); 2662 } else { 2663 next = NULL; 2664 nextphys = EHCI_NULL; 2665 } 2666 2667 for (i = 0; i * EHCI_PAGE_SIZE < 2668 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2669 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2670 if (i != 0) /* use offset only in first buffer */ 2671 a = EHCI_PAGE(a); 2672 cur->qtd.qtd_buffer[i] = htole32(a); 2673 cur->qtd.qtd_buffer_hi[i] = 0; 2674 #ifdef DIAGNOSTIC 2675 if (i >= EHCI_QTD_NBUFFERS) { 2676 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2677 goto nomem; 2678 } 2679 #endif 2680 } 2681 cur->nextqtd = next; 2682 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2683 cur->qtd.qtd_status = 2684 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2685 cur->xfer = xfer; 2686 cur->len = curlen; 2687 2688 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2689 dataphys, dataphys + curlen)); 2690 /* adjust the toggle based on the number of packets in this 2691 qtd */ 2692 if (((curlen + mps - 1) / mps) & 1) { 2693 tog ^= 1; 2694 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2695 } 2696 if (next == NULL) 2697 break; 2698 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2699 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2700 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2701 dataphys += curlen; 2702 cur = next; 2703 } 2704 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2705 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2706 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2707 *ep = cur; 2708 epipe->nexttoggle = tog; 2709 2710 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2711 *sp, *ep)); 2712 2713 return (USBD_NORMAL_COMPLETION); 2714 2715 nomem: 2716 /* XXX free chain */ 2717 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2718 return (USBD_NOMEM); 2719 } 2720 2721 Static void 2722 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2723 ehci_soft_qtd_t *sqtdend) 2724 { 2725 ehci_soft_qtd_t *p; 2726 int i; 2727 2728 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2729 sqtd, sqtdend)); 2730 2731 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2732 p = sqtd->nextqtd; 2733 ehci_free_sqtd(sc, sqtd); 2734 } 2735 } 2736 2737 Static ehci_soft_itd_t * 2738 ehci_alloc_itd(ehci_softc_t *sc) 2739 { 2740 struct ehci_soft_itd *itd, *freeitd; 2741 usbd_status err; 2742 int i, s, offs, frindex, previndex; 2743 usb_dma_t dma; 2744 2745 s = splusb(); 2746 2747 /* Find an itd that wasn't freed this frame or last frame. This can 2748 * discard itds that were freed before frindex wrapped around 2749 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2750 * interrupt and fiddling with list when that happens */ 2751 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2752 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2753 2754 freeitd = NULL; 2755 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2756 if (itd == NULL) 2757 break; 2758 if (itd->slot != frindex && itd->slot != previndex) { 2759 freeitd = itd; 2760 break; 2761 } 2762 } 2763 2764 if (freeitd == NULL) { 2765 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2766 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2767 EHCI_PAGE_SIZE, &dma); 2768 2769 if (err) { 2770 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2771 return NULL; 2772 } 2773 2774 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2775 offs = i * EHCI_ITD_SIZE; 2776 itd = KERNADDR(&dma, offs); 2777 itd->physaddr = DMAADDR(&dma, offs); 2778 itd->dma = dma; 2779 itd->offs = offs; 2780 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2781 } 2782 freeitd = LIST_FIRST(&sc->sc_freeitds); 2783 } 2784 2785 itd = freeitd; 2786 LIST_REMOVE(itd, u.free_list); 2787 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2788 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2789 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2790 BUS_DMASYNC_PREREAD); 2791 2792 itd->u.frame_list.next = NULL; 2793 itd->u.frame_list.prev = NULL; 2794 itd->xfer_next = NULL; 2795 itd->slot = 0; 2796 splx(s); 2797 2798 return itd; 2799 } 2800 2801 Static void 2802 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2803 { 2804 int s; 2805 2806 s = splusb(); 2807 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2808 splx(s); 2809 } 2810 2811 /****************/ 2812 2813 /* 2814 * Close a reqular pipe. 2815 * Assumes that there are no pending transactions. 2816 */ 2817 Static void 2818 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2819 { 2820 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2821 ehci_softc_t *sc = pipe->device->bus->hci_private; 2822 ehci_soft_qh_t *sqh = epipe->sqh; 2823 int s; 2824 2825 s = splusb(); 2826 ehci_rem_qh(sc, sqh, head); 2827 splx(s); 2828 ehci_free_sqh(sc, epipe->sqh); 2829 } 2830 2831 /* 2832 * Abort a device request. 2833 * If this routine is called at splusb() it guarantees that the request 2834 * will be removed from the hardware scheduling and that the callback 2835 * for it will be called with USBD_CANCELLED status. 2836 * It's impossible to guarantee that the requested transfer will not 2837 * have happened since the hardware runs concurrently. 2838 * If the transaction has already happened we rely on the ordinary 2839 * interrupt processing to process it. 2840 * XXX This is most probably wrong. 2841 */ 2842 Static void 2843 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2844 { 2845 #define exfer EXFER(xfer) 2846 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2847 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2848 ehci_soft_qh_t *sqh = epipe->sqh; 2849 ehci_soft_qtd_t *sqtd; 2850 ehci_physaddr_t cur; 2851 u_int32_t qhstatus; 2852 int s; 2853 int hit; 2854 int wake; 2855 2856 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2857 2858 if (sc->sc_dying) { 2859 /* If we're dying, just do the software part. */ 2860 s = splusb(); 2861 xfer->status = status; /* make software ignore it */ 2862 callout_stop(&(xfer->timeout_handle)); 2863 usb_transfer_complete(xfer); 2864 splx(s); 2865 return; 2866 } 2867 2868 if (xfer->device->bus->intr_context) 2869 panic("ehci_abort_xfer: not in process context"); 2870 2871 /* 2872 * If an abort is already in progress then just wait for it to 2873 * complete and return. 2874 */ 2875 if (xfer->hcflags & UXFER_ABORTING) { 2876 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2877 #ifdef DIAGNOSTIC 2878 if (status == USBD_TIMEOUT) 2879 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2880 #endif 2881 /* Override the status which might be USBD_TIMEOUT. */ 2882 xfer->status = status; 2883 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2884 xfer->hcflags |= UXFER_ABORTWAIT; 2885 while (xfer->hcflags & UXFER_ABORTING) 2886 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2887 return; 2888 } 2889 xfer->hcflags |= UXFER_ABORTING; 2890 2891 /* 2892 * Step 1: Make interrupt routine and hardware ignore xfer. 2893 */ 2894 s = splusb(); 2895 xfer->status = status; /* make software ignore it */ 2896 callout_stop(&(xfer->timeout_handle)); 2897 2898 usb_syncmem(&sqh->dma, 2899 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2900 sizeof(sqh->qh.qh_qtd.qtd_status), 2901 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2902 qhstatus = sqh->qh.qh_qtd.qtd_status; 2903 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2904 usb_syncmem(&sqh->dma, 2905 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2906 sizeof(sqh->qh.qh_qtd.qtd_status), 2907 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2908 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2909 usb_syncmem(&sqtd->dma, 2910 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2911 sizeof(sqtd->qtd.qtd_status), 2912 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2913 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2914 usb_syncmem(&sqtd->dma, 2915 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2916 sizeof(sqtd->qtd.qtd_status), 2917 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2918 if (sqtd == exfer->sqtdend) 2919 break; 2920 } 2921 splx(s); 2922 2923 /* 2924 * Step 2: Wait until we know hardware has finished any possible 2925 * use of the xfer. Also make sure the soft interrupt routine 2926 * has run. 2927 */ 2928 ehci_sync_hc(sc); 2929 s = splusb(); 2930 #ifdef USB_USE_SOFTINTR 2931 sc->sc_softwake = 1; 2932 #endif /* USB_USE_SOFTINTR */ 2933 usb_schedsoftintr(&sc->sc_bus); 2934 #ifdef USB_USE_SOFTINTR 2935 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2936 #endif /* USB_USE_SOFTINTR */ 2937 splx(s); 2938 2939 /* 2940 * Step 3: Remove any vestiges of the xfer from the hardware. 2941 * The complication here is that the hardware may have executed 2942 * beyond the xfer we're trying to abort. So as we're scanning 2943 * the TDs of this xfer we check if the hardware points to 2944 * any of them. 2945 */ 2946 s = splusb(); /* XXX why? */ 2947 2948 usb_syncmem(&sqh->dma, 2949 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2950 sizeof(sqh->qh.qh_curqtd), 2951 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2952 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2953 hit = 0; 2954 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2955 hit |= cur == sqtd->physaddr; 2956 if (sqtd == exfer->sqtdend) 2957 break; 2958 } 2959 sqtd = sqtd->nextqtd; 2960 /* Zap curqtd register if hardware pointed inside the xfer. */ 2961 if (hit && sqtd != NULL) { 2962 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 2963 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 2964 usb_syncmem(&sqh->dma, 2965 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2966 sizeof(sqh->qh.qh_curqtd), 2967 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2968 sqh->qh.qh_qtd.qtd_status = qhstatus; 2969 usb_syncmem(&sqh->dma, 2970 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2971 sizeof(sqh->qh.qh_qtd.qtd_status), 2972 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2973 } else { 2974 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2975 } 2976 2977 /* 2978 * Step 4: Execute callback. 2979 */ 2980 #ifdef DIAGNOSTIC 2981 exfer->isdone = 1; 2982 #endif 2983 wake = xfer->hcflags & UXFER_ABORTWAIT; 2984 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2985 usb_transfer_complete(xfer); 2986 if (wake) 2987 wakeup(&xfer->hcflags); 2988 2989 splx(s); 2990 #undef exfer 2991 } 2992 2993 Static void 2994 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 2995 { 2996 ehci_isoc_trans_t trans_status; 2997 struct ehci_pipe *epipe; 2998 struct ehci_xfer *exfer; 2999 ehci_softc_t *sc; 3000 struct ehci_soft_itd *itd; 3001 int s, i, wake; 3002 3003 epipe = (struct ehci_pipe *) xfer->pipe; 3004 exfer = EXFER(xfer); 3005 sc = epipe->pipe.device->bus->hci_private; 3006 3007 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3008 3009 if (sc->sc_dying) { 3010 s = splusb(); 3011 xfer->status = status; 3012 callout_stop(&(xfer->timeout_handle)); 3013 usb_transfer_complete(xfer); 3014 splx(s); 3015 return; 3016 } 3017 3018 if (xfer->hcflags & UXFER_ABORTING) { 3019 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3020 3021 #ifdef DIAGNOSTIC 3022 if (status == USBD_TIMEOUT) 3023 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3024 #endif 3025 3026 xfer->status = status; 3027 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3028 xfer->hcflags |= UXFER_ABORTWAIT; 3029 while (xfer->hcflags & UXFER_ABORTING) 3030 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0); 3031 return; 3032 } 3033 xfer->hcflags |= UXFER_ABORTING; 3034 3035 xfer->status = status; 3036 callout_stop(&(xfer->timeout_handle)); 3037 3038 s = splusb(); 3039 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3040 usb_syncmem(&itd->dma, 3041 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3042 sizeof(itd->itd.itd_ctl), 3043 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3044 3045 for (i = 0; i < 8; i++) { 3046 trans_status = le32toh(itd->itd.itd_ctl[i]); 3047 trans_status &= ~EHCI_ITD_ACTIVE; 3048 itd->itd.itd_ctl[i] = htole32(trans_status); 3049 } 3050 3051 usb_syncmem(&itd->dma, 3052 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3053 sizeof(itd->itd.itd_ctl), 3054 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3055 } 3056 splx(s); 3057 3058 s = splusb(); 3059 #ifdef USB_USE_SOFTINTR 3060 sc->sc_softwake = 1; 3061 #endif /* USB_USE_SOFTINTR */ 3062 usb_schedsoftintr(&sc->sc_bus); 3063 #ifdef USB_USE_SOFTINTR 3064 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3065 #endif /* USB_USE_SOFTINTR */ 3066 splx(s); 3067 3068 #ifdef DIAGNOSTIC 3069 exfer->isdone = 1; 3070 #endif 3071 wake = xfer->hcflags & UXFER_ABORTWAIT; 3072 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3073 usb_transfer_complete(xfer); 3074 if (wake) 3075 wakeup(&xfer->hcflags); 3076 3077 return; 3078 } 3079 3080 Static void 3081 ehci_timeout(void *addr) 3082 { 3083 struct ehci_xfer *exfer = addr; 3084 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3085 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3086 3087 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3088 #ifdef EHCI_DEBUG 3089 if (ehcidebug > 1) 3090 usbd_dump_pipe(exfer->xfer.pipe); 3091 #endif 3092 3093 if (sc->sc_dying) { 3094 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3095 return; 3096 } 3097 3098 /* Execute the abort in a process context. */ 3099 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3100 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3101 USB_TASKQ_HC); 3102 } 3103 3104 Static void 3105 ehci_timeout_task(void *addr) 3106 { 3107 usbd_xfer_handle xfer = addr; 3108 int s; 3109 3110 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3111 3112 s = splusb(); 3113 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3114 splx(s); 3115 } 3116 3117 /************************/ 3118 3119 Static usbd_status 3120 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3121 { 3122 usbd_status err; 3123 3124 /* Insert last in queue. */ 3125 err = usb_insert_transfer(xfer); 3126 if (err) 3127 return (err); 3128 3129 /* Pipe isn't running, start first */ 3130 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3131 } 3132 3133 Static usbd_status 3134 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3135 { 3136 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3137 usbd_status err; 3138 3139 if (sc->sc_dying) 3140 return (USBD_IOERROR); 3141 3142 #ifdef DIAGNOSTIC 3143 if (!(xfer->rqflags & URQ_REQUEST)) { 3144 /* XXX panic */ 3145 printf("ehci_device_ctrl_transfer: not a request\n"); 3146 return (USBD_INVAL); 3147 } 3148 #endif 3149 3150 err = ehci_device_request(xfer); 3151 if (err) 3152 return (err); 3153 3154 if (sc->sc_bus.use_polling) 3155 ehci_waitintr(sc, xfer); 3156 return (USBD_IN_PROGRESS); 3157 } 3158 3159 Static void 3160 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3161 { 3162 struct ehci_xfer *ex = EXFER(xfer); 3163 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3164 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3165 usb_device_request_t *req = &xfer->request; 3166 int len = UGETW(req->wLength); 3167 int rd = req->bmRequestType & UT_READ; 3168 3169 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3170 3171 #ifdef DIAGNOSTIC 3172 if (!(xfer->rqflags & URQ_REQUEST)) { 3173 panic("ehci_ctrl_done: not a request"); 3174 } 3175 #endif 3176 3177 mutex_enter(&sc->sc_intrhead_lock); 3178 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3179 ehci_del_intr_list(sc, ex); /* remove from active list */ 3180 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3181 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3182 BUS_DMASYNC_POSTWRITE); 3183 if (len) 3184 usb_syncmem(&xfer->dmabuf, 0, len, 3185 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3186 } 3187 mutex_exit(&sc->sc_intrhead_lock); 3188 3189 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3190 } 3191 3192 /* Abort a device control request. */ 3193 Static void 3194 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3195 { 3196 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3197 ehci_abort_xfer(xfer, USBD_CANCELLED); 3198 } 3199 3200 /* Close a device control pipe. */ 3201 Static void 3202 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3203 { 3204 ehci_softc_t *sc = pipe->device->bus->hci_private; 3205 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3206 3207 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3208 ehci_close_pipe(pipe, sc->sc_async_head); 3209 } 3210 3211 Static usbd_status 3212 ehci_device_request(usbd_xfer_handle xfer) 3213 { 3214 #define exfer EXFER(xfer) 3215 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3216 usb_device_request_t *req = &xfer->request; 3217 usbd_device_handle dev = epipe->pipe.device; 3218 ehci_softc_t *sc = dev->bus->hci_private; 3219 int addr = dev->address; 3220 ehci_soft_qtd_t *setup, *stat, *next; 3221 ehci_soft_qh_t *sqh; 3222 int isread; 3223 int len; 3224 usbd_status err; 3225 int s; 3226 3227 isread = req->bmRequestType & UT_READ; 3228 len = UGETW(req->wLength); 3229 3230 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3231 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3232 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3233 UGETW(req->wIndex), len, addr, 3234 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3235 3236 setup = ehci_alloc_sqtd(sc); 3237 if (setup == NULL) { 3238 err = USBD_NOMEM; 3239 goto bad1; 3240 } 3241 stat = ehci_alloc_sqtd(sc); 3242 if (stat == NULL) { 3243 err = USBD_NOMEM; 3244 goto bad2; 3245 } 3246 3247 sqh = epipe->sqh; 3248 epipe->u.ctl.length = len; 3249 3250 /* Update device address and length since they may have changed 3251 during the setup of the control pipe in usbd_new_device(). */ 3252 /* XXX This only needs to be done once, but it's too early in open. */ 3253 /* XXXX Should not touch ED here! */ 3254 sqh->qh.qh_endp = 3255 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3256 htole32( 3257 EHCI_QH_SET_ADDR(addr) | 3258 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3259 ); 3260 3261 /* Set up data transaction */ 3262 if (len != 0) { 3263 ehci_soft_qtd_t *end; 3264 3265 /* Start toggle at 1. */ 3266 epipe->nexttoggle = 1; 3267 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3268 &next, &end); 3269 if (err) 3270 goto bad3; 3271 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3272 end->nextqtd = stat; 3273 end->qtd.qtd_next = 3274 end->qtd.qtd_altnext = htole32(stat->physaddr); 3275 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3276 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3277 } else { 3278 next = stat; 3279 } 3280 3281 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3282 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3283 3284 /* Clear toggle */ 3285 setup->qtd.qtd_status = htole32( 3286 EHCI_QTD_ACTIVE | 3287 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3288 EHCI_QTD_SET_CERR(3) | 3289 EHCI_QTD_SET_TOGGLE(0) | 3290 EHCI_QTD_SET_BYTES(sizeof *req) 3291 ); 3292 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3293 setup->qtd.qtd_buffer_hi[0] = 0; 3294 setup->nextqtd = next; 3295 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3296 setup->xfer = xfer; 3297 setup->len = sizeof *req; 3298 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3299 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3300 3301 stat->qtd.qtd_status = htole32( 3302 EHCI_QTD_ACTIVE | 3303 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3304 EHCI_QTD_SET_CERR(3) | 3305 EHCI_QTD_SET_TOGGLE(1) | 3306 EHCI_QTD_IOC 3307 ); 3308 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3309 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3310 stat->nextqtd = NULL; 3311 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3312 stat->xfer = xfer; 3313 stat->len = 0; 3314 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3315 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3316 3317 #ifdef EHCI_DEBUG 3318 if (ehcidebug > 5) { 3319 DPRINTF(("ehci_device_request:\n")); 3320 ehci_dump_sqh(sqh); 3321 ehci_dump_sqtds(setup); 3322 } 3323 #endif 3324 3325 exfer->sqtdstart = setup; 3326 exfer->sqtdend = stat; 3327 #ifdef DIAGNOSTIC 3328 if (!exfer->isdone) { 3329 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3330 } 3331 exfer->isdone = 0; 3332 #endif 3333 3334 /* Insert qTD in QH list. */ 3335 s = splusb(); 3336 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3337 if (xfer->timeout && !sc->sc_bus.use_polling) { 3338 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3339 (ehci_timeout), (xfer)); 3340 } 3341 mutex_enter(&sc->sc_intrhead_lock); 3342 ehci_add_intr_list(sc, exfer); 3343 mutex_exit(&sc->sc_intrhead_lock); 3344 xfer->status = USBD_IN_PROGRESS; 3345 splx(s); 3346 3347 #ifdef EHCI_DEBUG 3348 if (ehcidebug > 10) { 3349 DPRINTF(("ehci_device_request: status=%x\n", 3350 EOREAD4(sc, EHCI_USBSTS))); 3351 delay(10000); 3352 ehci_dump_regs(sc); 3353 ehci_dump_sqh(sc->sc_async_head); 3354 ehci_dump_sqh(sqh); 3355 ehci_dump_sqtds(setup); 3356 } 3357 #endif 3358 3359 return (USBD_NORMAL_COMPLETION); 3360 3361 bad3: 3362 ehci_free_sqtd(sc, stat); 3363 bad2: 3364 ehci_free_sqtd(sc, setup); 3365 bad1: 3366 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3367 xfer->status = err; 3368 usb_transfer_complete(xfer); 3369 return (err); 3370 #undef exfer 3371 } 3372 3373 /* 3374 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3375 * qTD status, or miss signalling occasionally under heavy load. If the host 3376 * machine is too fast, we we can miss transaction completion - when we scan 3377 * the active list the transaction still seems to be active. This generally 3378 * exhibits itself as a umass stall that never recovers. 3379 * 3380 * We work around this behaviour by setting up this callback after any softintr 3381 * that completes with transactions still pending, giving us another chance to 3382 * check for completion after the writeback has taken place. 3383 */ 3384 Static void 3385 ehci_intrlist_timeout(void *arg) 3386 { 3387 ehci_softc_t *sc = arg; 3388 int s = splusb(); 3389 3390 DPRINTF(("ehci_intrlist_timeout\n")); 3391 usb_schedsoftintr(&sc->sc_bus); 3392 3393 splx(s); 3394 } 3395 3396 /************************/ 3397 3398 Static usbd_status 3399 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3400 { 3401 usbd_status err; 3402 3403 /* Insert last in queue. */ 3404 err = usb_insert_transfer(xfer); 3405 if (err) 3406 return (err); 3407 3408 /* Pipe isn't running, start first */ 3409 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3410 } 3411 3412 Static usbd_status 3413 ehci_device_bulk_start(usbd_xfer_handle xfer) 3414 { 3415 #define exfer EXFER(xfer) 3416 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3417 usbd_device_handle dev = epipe->pipe.device; 3418 ehci_softc_t *sc = dev->bus->hci_private; 3419 ehci_soft_qtd_t *data, *dataend; 3420 ehci_soft_qh_t *sqh; 3421 usbd_status err; 3422 int len, isread, endpt; 3423 int s; 3424 3425 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3426 xfer, xfer->length, xfer->flags)); 3427 3428 if (sc->sc_dying) 3429 return (USBD_IOERROR); 3430 3431 #ifdef DIAGNOSTIC 3432 if (xfer->rqflags & URQ_REQUEST) 3433 panic("ehci_device_bulk_start: a request"); 3434 #endif 3435 3436 len = xfer->length; 3437 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3438 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3439 sqh = epipe->sqh; 3440 3441 epipe->u.bulk.length = len; 3442 3443 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3444 &dataend); 3445 if (err) { 3446 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3447 xfer->status = err; 3448 usb_transfer_complete(xfer); 3449 return (err); 3450 } 3451 3452 #ifdef EHCI_DEBUG 3453 if (ehcidebug > 5) { 3454 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3455 ehci_dump_sqh(sqh); 3456 ehci_dump_sqtds(data); 3457 } 3458 #endif 3459 3460 /* Set up interrupt info. */ 3461 exfer->sqtdstart = data; 3462 exfer->sqtdend = dataend; 3463 #ifdef DIAGNOSTIC 3464 if (!exfer->isdone) { 3465 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3466 } 3467 exfer->isdone = 0; 3468 #endif 3469 3470 s = splusb(); 3471 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3472 if (xfer->timeout && !sc->sc_bus.use_polling) { 3473 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3474 (ehci_timeout), (xfer)); 3475 } 3476 mutex_enter(&sc->sc_intrhead_lock); 3477 ehci_add_intr_list(sc, exfer); 3478 mutex_exit(&sc->sc_intrhead_lock); 3479 xfer->status = USBD_IN_PROGRESS; 3480 splx(s); 3481 3482 #ifdef EHCI_DEBUG 3483 if (ehcidebug > 10) { 3484 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3485 delay(10000); 3486 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3487 ehci_dump_regs(sc); 3488 #if 0 3489 printf("async_head:\n"); 3490 ehci_dump_sqh(sc->sc_async_head); 3491 #endif 3492 printf("sqh:\n"); 3493 ehci_dump_sqh(sqh); 3494 ehci_dump_sqtds(data); 3495 } 3496 #endif 3497 3498 if (sc->sc_bus.use_polling) 3499 ehci_waitintr(sc, xfer); 3500 3501 return (USBD_IN_PROGRESS); 3502 #undef exfer 3503 } 3504 3505 Static void 3506 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3507 { 3508 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3509 ehci_abort_xfer(xfer, USBD_CANCELLED); 3510 } 3511 3512 /* 3513 * Close a device bulk pipe. 3514 */ 3515 Static void 3516 ehci_device_bulk_close(usbd_pipe_handle pipe) 3517 { 3518 ehci_softc_t *sc = pipe->device->bus->hci_private; 3519 3520 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3521 ehci_close_pipe(pipe, sc->sc_async_head); 3522 } 3523 3524 Static void 3525 ehci_device_bulk_done(usbd_xfer_handle xfer) 3526 { 3527 struct ehci_xfer *ex = EXFER(xfer); 3528 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3529 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3530 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3531 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3532 3533 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3534 xfer, xfer->actlen)); 3535 3536 mutex_enter(&sc->sc_intrhead_lock); 3537 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3538 ehci_del_intr_list(sc, ex); /* remove from active list */ 3539 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3540 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3541 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3542 } 3543 mutex_exit(&sc->sc_intrhead_lock); 3544 3545 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3546 } 3547 3548 /************************/ 3549 3550 Static usbd_status 3551 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3552 { 3553 struct ehci_soft_islot *isp; 3554 int islot, lev; 3555 3556 /* Find a poll rate that is large enough. */ 3557 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3558 if (EHCI_ILEV_IVAL(lev) <= ival) 3559 break; 3560 3561 /* Pick an interrupt slot at the right level. */ 3562 /* XXX could do better than picking at random */ 3563 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3564 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3565 3566 sqh->islot = islot; 3567 isp = &sc->sc_islots[islot]; 3568 ehci_add_qh(sqh, isp->sqh); 3569 3570 return (USBD_NORMAL_COMPLETION); 3571 } 3572 3573 Static usbd_status 3574 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3575 { 3576 usbd_status err; 3577 3578 /* Insert last in queue. */ 3579 err = usb_insert_transfer(xfer); 3580 if (err) 3581 return (err); 3582 3583 /* 3584 * Pipe isn't running (otherwise err would be USBD_INPROG), 3585 * so start it first. 3586 */ 3587 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3588 } 3589 3590 Static usbd_status 3591 ehci_device_intr_start(usbd_xfer_handle xfer) 3592 { 3593 #define exfer EXFER(xfer) 3594 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3595 usbd_device_handle dev = xfer->pipe->device; 3596 ehci_softc_t *sc = dev->bus->hci_private; 3597 ehci_soft_qtd_t *data, *dataend; 3598 ehci_soft_qh_t *sqh; 3599 usbd_status err; 3600 int len, isread, endpt; 3601 int s; 3602 3603 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3604 xfer, xfer->length, xfer->flags)); 3605 3606 if (sc->sc_dying) 3607 return (USBD_IOERROR); 3608 3609 #ifdef DIAGNOSTIC 3610 if (xfer->rqflags & URQ_REQUEST) 3611 panic("ehci_device_intr_start: a request"); 3612 #endif 3613 3614 len = xfer->length; 3615 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3616 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3617 sqh = epipe->sqh; 3618 3619 epipe->u.intr.length = len; 3620 3621 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3622 &dataend); 3623 if (err) { 3624 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3625 xfer->status = err; 3626 usb_transfer_complete(xfer); 3627 return (err); 3628 } 3629 3630 #ifdef EHCI_DEBUG 3631 if (ehcidebug > 5) { 3632 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3633 ehci_dump_sqh(sqh); 3634 ehci_dump_sqtds(data); 3635 } 3636 #endif 3637 3638 /* Set up interrupt info. */ 3639 exfer->sqtdstart = data; 3640 exfer->sqtdend = dataend; 3641 #ifdef DIAGNOSTIC 3642 if (!exfer->isdone) { 3643 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3644 } 3645 exfer->isdone = 0; 3646 #endif 3647 3648 s = splusb(); 3649 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3650 if (xfer->timeout && !sc->sc_bus.use_polling) { 3651 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3652 (ehci_timeout), (xfer)); 3653 } 3654 mutex_enter(&sc->sc_intrhead_lock); 3655 ehci_add_intr_list(sc, exfer); 3656 mutex_exit(&sc->sc_intrhead_lock); 3657 xfer->status = USBD_IN_PROGRESS; 3658 splx(s); 3659 3660 #ifdef EHCI_DEBUG 3661 if (ehcidebug > 10) { 3662 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3663 delay(10000); 3664 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3665 ehci_dump_regs(sc); 3666 printf("sqh:\n"); 3667 ehci_dump_sqh(sqh); 3668 ehci_dump_sqtds(data); 3669 } 3670 #endif 3671 3672 if (sc->sc_bus.use_polling) 3673 ehci_waitintr(sc, xfer); 3674 3675 return (USBD_IN_PROGRESS); 3676 #undef exfer 3677 } 3678 3679 Static void 3680 ehci_device_intr_abort(usbd_xfer_handle xfer) 3681 { 3682 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3683 if (xfer->pipe->intrxfer == xfer) { 3684 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3685 xfer->pipe->intrxfer = NULL; 3686 } 3687 /* 3688 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3689 * async doorbell. That's dependant on the async list, wheras 3690 * intr xfers are periodic, should not use this? 3691 */ 3692 ehci_abort_xfer(xfer, USBD_CANCELLED); 3693 } 3694 3695 Static void 3696 ehci_device_intr_close(usbd_pipe_handle pipe) 3697 { 3698 ehci_softc_t *sc = pipe->device->bus->hci_private; 3699 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3700 struct ehci_soft_islot *isp; 3701 3702 isp = &sc->sc_islots[epipe->sqh->islot]; 3703 ehci_close_pipe(pipe, isp->sqh); 3704 } 3705 3706 Static void 3707 ehci_device_intr_done(usbd_xfer_handle xfer) 3708 { 3709 #define exfer EXFER(xfer) 3710 struct ehci_xfer *ex = EXFER(xfer); 3711 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3712 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3713 ehci_soft_qtd_t *data, *dataend; 3714 ehci_soft_qh_t *sqh; 3715 usbd_status err; 3716 int len, isread, endpt, s; 3717 3718 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3719 xfer, xfer->actlen)); 3720 3721 mutex_enter(&sc->sc_intrhead_lock); 3722 if (xfer->pipe->repeat) { 3723 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3724 3725 len = epipe->u.intr.length; 3726 xfer->length = len; 3727 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3728 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3729 usb_syncmem(&xfer->dmabuf, 0, len, 3730 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3731 sqh = epipe->sqh; 3732 3733 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3734 &data, &dataend); 3735 if (err) { 3736 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3737 xfer->status = err; 3738 mutex_exit(&sc->sc_intrhead_lock); 3739 return; 3740 } 3741 3742 /* Set up interrupt info. */ 3743 exfer->sqtdstart = data; 3744 exfer->sqtdend = dataend; 3745 #ifdef DIAGNOSTIC 3746 if (!exfer->isdone) { 3747 printf("ehci_device_intr_done: not done, ex=%p\n", 3748 exfer); 3749 } 3750 exfer->isdone = 0; 3751 #endif 3752 3753 s = splusb(); 3754 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3755 if (xfer->timeout && !sc->sc_bus.use_polling) { 3756 callout_reset(&(xfer->timeout_handle), 3757 (mstohz(xfer->timeout)), (ehci_timeout), (xfer)); 3758 } 3759 splx(s); 3760 3761 xfer->status = USBD_IN_PROGRESS; 3762 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3763 ehci_del_intr_list(sc, ex); /* remove from active list */ 3764 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3765 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3766 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3767 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3768 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3769 } 3770 mutex_exit(&sc->sc_intrhead_lock); 3771 #undef exfer 3772 } 3773 3774 /************************/ 3775 3776 Static usbd_status 3777 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3778 { 3779 usbd_status err; 3780 3781 err = usb_insert_transfer(xfer); 3782 if (err && err != USBD_IN_PROGRESS) 3783 return err; 3784 3785 return ehci_device_isoc_start(xfer); 3786 } 3787 3788 Static usbd_status 3789 ehci_device_isoc_start(usbd_xfer_handle xfer) 3790 { 3791 struct ehci_pipe *epipe; 3792 usbd_device_handle dev; 3793 ehci_softc_t *sc; 3794 struct ehci_xfer *exfer; 3795 ehci_soft_itd_t *itd, *prev, *start, *stop; 3796 usb_dma_t *dma_buf; 3797 int i, j, k, frames, uframes, ufrperframe; 3798 int s, trans_count, offs, total_length; 3799 int frindex; 3800 3801 start = NULL; 3802 prev = NULL; 3803 itd = NULL; 3804 trans_count = 0; 3805 total_length = 0; 3806 exfer = (struct ehci_xfer *) xfer; 3807 sc = xfer->pipe->device->bus->hci_private; 3808 dev = xfer->pipe->device; 3809 epipe = (struct ehci_pipe *)xfer->pipe; 3810 3811 /* 3812 * To allow continuous transfers, above we start all transfers 3813 * immediately. However, we're still going to get usbd_start_next call 3814 * this when another xfer completes. So, check if this is already 3815 * in progress or not 3816 */ 3817 3818 if (exfer->itdstart != NULL) 3819 return USBD_IN_PROGRESS; 3820 3821 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3822 xfer, xfer->length, xfer->flags)); 3823 3824 if (sc->sc_dying) 3825 return USBD_IOERROR; 3826 3827 /* 3828 * To avoid complication, don't allow a request right now that'll span 3829 * the entire frame table. To within 4 frames, to allow some leeway 3830 * on either side of where the hc currently is. 3831 */ 3832 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3833 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3834 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3835 return USBD_INVAL; 3836 } 3837 3838 #ifdef DIAGNOSTIC 3839 if (xfer->rqflags & URQ_REQUEST) 3840 panic("ehci_device_isoc_start: request\n"); 3841 3842 if (!exfer->isdone) 3843 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3844 exfer->isdone = 0; 3845 #endif 3846 3847 /* 3848 * Step 1: Allocate and initialize itds, how many do we need? 3849 * One per transfer if interval >= 8 microframes, fewer if we use 3850 * multiple microframes per frame. 3851 */ 3852 3853 i = epipe->pipe.endpoint->edesc->bInterval; 3854 if (i > 16 || i == 0) { 3855 /* Spec page 271 says intervals > 16 are invalid */ 3856 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3857 return USBD_INVAL; 3858 } 3859 3860 switch (i) { 3861 case 1: 3862 ufrperframe = 8; 3863 break; 3864 case 2: 3865 ufrperframe = 4; 3866 break; 3867 case 3: 3868 ufrperframe = 2; 3869 break; 3870 default: 3871 ufrperframe = 1; 3872 break; 3873 } 3874 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3875 uframes = 8 / ufrperframe; 3876 3877 if (frames == 0) { 3878 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3879 return USBD_INVAL; 3880 } 3881 3882 dma_buf = &xfer->dmabuf; 3883 offs = 0; 3884 3885 for (i = 0; i < frames; i++) { 3886 int froffs = offs; 3887 itd = ehci_alloc_itd(sc); 3888 3889 if (prev != NULL) { 3890 prev->itd.itd_next = 3891 htole32(itd->physaddr | EHCI_LINK_ITD); 3892 usb_syncmem(&itd->dma, 3893 itd->offs + offsetof(ehci_itd_t, itd_next), 3894 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 3895 3896 prev->xfer_next = itd; 3897 } else { 3898 start = itd; 3899 } 3900 3901 /* 3902 * Step 1.5, initialize uframes 3903 */ 3904 for (j = 0; j < 8; j += uframes) { 3905 /* Calculate which page in the list this starts in */ 3906 int addr = DMAADDR(dma_buf, froffs); 3907 addr = EHCI_PAGE_OFFSET(addr); 3908 addr += (offs - froffs); 3909 addr = EHCI_PAGE(addr); 3910 addr /= EHCI_PAGE_SIZE; 3911 3912 /* This gets the initial offset into the first page, 3913 * looks how far further along the current uframe 3914 * offset is. Works out how many pages that is. 3915 */ 3916 3917 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3918 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3919 EHCI_ITD_SET_PG(addr) | 3920 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 3921 3922 total_length += xfer->frlengths[trans_count]; 3923 offs += xfer->frlengths[trans_count]; 3924 trans_count++; 3925 3926 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3927 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3928 break; 3929 } 3930 } 3931 3932 /* Step 1.75, set buffer pointers. To simplify matters, all 3933 * pointers are filled out for the next 7 hardware pages in 3934 * the dma block, so no need to worry what pages to cover 3935 * and what to not. 3936 */ 3937 3938 for (j=0; j < 7; j++) { 3939 /* 3940 * Don't try to lookup a page that's past the end 3941 * of buffer 3942 */ 3943 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 3944 if (page_offs >= dma_buf->block->size) 3945 break; 3946 3947 long long page = DMAADDR(dma_buf, page_offs); 3948 page = EHCI_PAGE(page); 3949 itd->itd.itd_bufr[j] = 3950 htole32(EHCI_ITD_SET_BPTR(page)); 3951 itd->itd.itd_bufr_hi[j] = 3952 htole32(page >> 32); 3953 } 3954 3955 /* 3956 * Other special values 3957 */ 3958 3959 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3960 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3961 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3962 3963 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3964 ? 1 : 0; 3965 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3966 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3967 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3968 3969 /* FIXME: handle invalid trans */ 3970 itd->itd.itd_bufr[2] |= 3971 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3972 3973 usb_syncmem(&itd->dma, 3974 itd->offs + offsetof(ehci_itd_t, itd_next), 3975 sizeof(ehci_itd_t), 3976 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3977 3978 prev = itd; 3979 } /* End of frame */ 3980 3981 stop = itd; 3982 stop->xfer_next = NULL; 3983 exfer->isoc_len = total_length; 3984 3985 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 3986 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3987 3988 /* 3989 * Part 2: Transfer descriptors have now been set up, now they must 3990 * be scheduled into the period frame list. Erk. Not wanting to 3991 * complicate matters, transfer is denied if the transfer spans 3992 * more than the period frame list. 3993 */ 3994 3995 s = splusb(); 3996 3997 /* Start inserting frames */ 3998 if (epipe->u.isoc.cur_xfers > 0) { 3999 frindex = epipe->u.isoc.next_frame; 4000 } else { 4001 frindex = EOREAD4(sc, EHCI_FRINDEX); 4002 frindex = frindex >> 3; /* Erase microframe index */ 4003 frindex += 2; 4004 } 4005 4006 if (frindex >= sc->sc_flsize) 4007 frindex &= (sc->sc_flsize - 1); 4008 4009 /* Whats the frame interval? */ 4010 i = (1 << epipe->pipe.endpoint->edesc->bInterval); 4011 if (i / 8 == 0) 4012 i = 1; 4013 else 4014 i /= 8; 4015 4016 itd = start; 4017 for (j = 0; j < frames; j++) { 4018 if (itd == NULL) 4019 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4020 4021 itd->itd.itd_next = sc->sc_flist[frindex]; 4022 if (itd->itd.itd_next == 0) 4023 /* FIXME: frindex table gets initialized to NULL 4024 * or EHCI_NULL? */ 4025 itd->itd.itd_next = EHCI_NULL; 4026 4027 usb_syncmem(&itd->dma, 4028 itd->offs + offsetof(ehci_itd_t, itd_next), 4029 sizeof(itd->itd.itd_next), 4030 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4031 4032 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4033 4034 usb_syncmem(&sc->sc_fldma, 4035 sizeof(ehci_link_t) * frindex, 4036 sizeof(ehci_link_t), 4037 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4038 4039 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4040 sc->sc_softitds[frindex] = itd; 4041 if (itd->u.frame_list.next != NULL) 4042 itd->u.frame_list.next->u.frame_list.prev = itd; 4043 itd->slot = frindex; 4044 itd->u.frame_list.prev = NULL; 4045 4046 frindex += i; 4047 if (frindex >= sc->sc_flsize) 4048 frindex -= sc->sc_flsize; 4049 4050 itd = itd->xfer_next; 4051 } 4052 4053 epipe->u.isoc.cur_xfers++; 4054 epipe->u.isoc.next_frame = frindex; 4055 4056 exfer->itdstart = start; 4057 exfer->itdend = stop; 4058 exfer->sqtdstart = NULL; 4059 exfer->sqtdstart = NULL; 4060 4061 mutex_enter(&sc->sc_intrhead_lock); 4062 ehci_add_intr_list(sc, exfer); 4063 mutex_exit(&sc->sc_intrhead_lock); 4064 xfer->status = USBD_IN_PROGRESS; 4065 xfer->done = 0; 4066 splx(s); 4067 4068 if (sc->sc_bus.use_polling) { 4069 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4070 ehci_waitintr(sc, xfer); 4071 } 4072 4073 return USBD_IN_PROGRESS; 4074 } 4075 4076 Static void 4077 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4078 { 4079 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4080 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4081 } 4082 4083 Static void 4084 ehci_device_isoc_close(usbd_pipe_handle pipe) 4085 { 4086 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4087 } 4088 4089 Static void 4090 ehci_device_isoc_done(usbd_xfer_handle xfer) 4091 { 4092 struct ehci_xfer *exfer; 4093 ehci_softc_t *sc; 4094 struct ehci_pipe *epipe; 4095 int s; 4096 4097 exfer = EXFER(xfer); 4098 sc = xfer->pipe->device->bus->hci_private; 4099 epipe = (struct ehci_pipe *) xfer->pipe; 4100 4101 s = splusb(); 4102 epipe->u.isoc.cur_xfers--; 4103 mutex_enter(&sc->sc_intrhead_lock); 4104 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4105 ehci_del_intr_list(sc, exfer); 4106 ehci_rem_free_itd_chain(sc, exfer); 4107 } 4108 mutex_exit(&sc->sc_intrhead_lock); 4109 splx(s); 4110 4111 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4112 BUS_DMASYNC_POSTREAD); 4113 4114 } 4115
Indexes created Mon Sep 22 13:09:51 GMT 2025