ehci.c revision 1.17
1 /* TODO 2 Add intrinfo. 3 */ 4 /* $NetBSD: ehci.c,v 1.17 2001/11/21 08:18:39 augustss Exp $ */ 5 6 /* 7 * Copyright (c) 2001 The NetBSD Foundation, Inc. 8 * All rights reserved. 9 * 10 * This code is derived from software contributed to The NetBSD Foundation 11 * by Lennart Augustsson (lennart (at) augustsson.net). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by the NetBSD 24 * Foundation, Inc. and its contributors. 25 * 4. Neither the name of The NetBSD Foundation nor the names of its 26 * contributors may be used to endorse or promote products derived 27 * from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 31 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 32 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 33 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 34 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 37 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 39 * POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42 /* 43 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 44 * 45 * The EHCI 0.96 spec can be found at 46 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf 47 * and the USB 2.0 spec at 48 * http://www.usb.org/developers/data/usb_20.zip 49 * 50 */ 51 52 #include <sys/cdefs.h> 53 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.17 2001/11/21 08:18:39 augustss Exp $"); 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/kernel.h> 58 #include <sys/malloc.h> 59 #include <sys/device.h> 60 #include <sys/select.h> 61 #include <sys/proc.h> 62 #include <sys/queue.h> 63 64 #include <machine/bus.h> 65 #include <machine/endian.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 #include <dev/usb/usbdivar.h> 70 #include <dev/usb/usb_mem.h> 71 #include <dev/usb/usb_quirks.h> 72 73 #include <dev/usb/ehcireg.h> 74 #include <dev/usb/ehcivar.h> 75 76 #ifdef EHCI_DEBUG 77 #define DPRINTF(x) if (ehcidebug) printf x 78 #define DPRINTFN(n,x) if (ehcidebug>(n)) printf x 79 int ehcidebug = 0; 80 #ifndef __NetBSD__ 81 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f)) 82 #endif 83 #else 84 #define DPRINTF(x) 85 #define DPRINTFN(n,x) 86 #endif 87 88 struct ehci_pipe { 89 struct usbd_pipe pipe; 90 ehci_soft_qh_t *sqh; 91 union { 92 ehci_soft_qtd_t *qtd; 93 /* ehci_soft_itd_t *itd; */ 94 } tail; 95 union { 96 /* Control pipe */ 97 struct { 98 usb_dma_t reqdma; 99 u_int length; 100 ehci_soft_qtd_t *setup, *data, *stat; 101 } ctl; 102 /* Interrupt pipe */ 103 /* XXX */ 104 /* Bulk pipe */ 105 struct { 106 u_int length; 107 int isread; 108 } bulk; 109 /* Iso pipe */ 110 /* XXX */ 111 } u; 112 }; 113 114 Static void ehci_shutdown(void *); 115 Static void ehci_power(int, void *); 116 117 Static usbd_status ehci_open(usbd_pipe_handle); 118 Static void ehci_poll(struct usbd_bus *); 119 Static void ehci_softintr(void *); 120 Static int ehci_intr1(ehci_softc_t *); 121 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 122 Static void ehci_timeout(void *); 123 Static void ehci_timeout_task(void *); 124 125 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 126 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 127 128 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 129 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 130 131 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 132 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 133 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 134 Static void ehci_root_ctrl_close(usbd_pipe_handle); 135 Static void ehci_root_ctrl_done(usbd_xfer_handle); 136 137 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 138 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 139 Static void ehci_root_intr_abort(usbd_xfer_handle); 140 Static void ehci_root_intr_close(usbd_pipe_handle); 141 Static void ehci_root_intr_done(usbd_xfer_handle); 142 143 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 144 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 145 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 146 Static void ehci_device_ctrl_close(usbd_pipe_handle); 147 Static void ehci_device_ctrl_done(usbd_xfer_handle); 148 149 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 150 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 151 Static void ehci_device_bulk_abort(usbd_xfer_handle); 152 Static void ehci_device_bulk_close(usbd_pipe_handle); 153 Static void ehci_device_bulk_done(usbd_xfer_handle); 154 155 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 156 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 157 Static void ehci_device_intr_abort(usbd_xfer_handle); 158 Static void ehci_device_intr_close(usbd_pipe_handle); 159 Static void ehci_device_intr_done(usbd_xfer_handle); 160 161 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 162 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 163 Static void ehci_device_isoc_abort(usbd_xfer_handle); 164 Static void ehci_device_isoc_close(usbd_pipe_handle); 165 Static void ehci_device_isoc_done(usbd_xfer_handle); 166 167 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 168 Static void ehci_noop(usbd_pipe_handle pipe); 169 170 Static int ehci_str(usb_string_descriptor_t *, int, char *); 171 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 172 Static void ehci_pcd_able(ehci_softc_t *, int); 173 Static void ehci_pcd_enable(void *); 174 Static void ehci_disown(ehci_softc_t *, int, int); 175 176 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 177 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 178 179 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 180 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 181 Static usbd_status ehci_alloc_std_chain(struct ehci_pipe *, 182 ehci_softc_t *, int, int, usbd_xfer_handle, 183 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 184 185 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 186 187 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 188 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 189 ehci_soft_qh_t *); 190 Static void ehci_sync_hc(ehci_softc_t *); 191 192 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 193 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 194 195 #ifdef EHCI_DEBUG 196 Static void ehci_dumpregs(ehci_softc_t *); 197 Static void ehci_dump(void); 198 Static ehci_softc_t *theehci; 199 Static void ehci_dump_link(ehci_link_t, int); 200 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 201 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 202 Static void ehci_dump_qtd(ehci_qtd_t *); 203 Static void ehci_dump_sqh(ehci_soft_qh_t *); 204 #endif 205 206 #define MS_TO_TICKS(ms) ((ms) * hz / 1000) 207 208 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 209 210 #define EHCI_INTR_ENDPT 1 211 212 Static struct usbd_bus_methods ehci_bus_methods = { 213 ehci_open, 214 ehci_softintr, 215 ehci_poll, 216 ehci_allocm, 217 ehci_freem, 218 ehci_allocx, 219 ehci_freex, 220 }; 221 222 Static struct usbd_pipe_methods ehci_root_ctrl_methods = { 223 ehci_root_ctrl_transfer, 224 ehci_root_ctrl_start, 225 ehci_root_ctrl_abort, 226 ehci_root_ctrl_close, 227 ehci_noop, 228 ehci_root_ctrl_done, 229 }; 230 231 Static struct usbd_pipe_methods ehci_root_intr_methods = { 232 ehci_root_intr_transfer, 233 ehci_root_intr_start, 234 ehci_root_intr_abort, 235 ehci_root_intr_close, 236 ehci_noop, 237 ehci_root_intr_done, 238 }; 239 240 Static struct usbd_pipe_methods ehci_device_ctrl_methods = { 241 ehci_device_ctrl_transfer, 242 ehci_device_ctrl_start, 243 ehci_device_ctrl_abort, 244 ehci_device_ctrl_close, 245 ehci_noop, 246 ehci_device_ctrl_done, 247 }; 248 249 Static struct usbd_pipe_methods ehci_device_intr_methods = { 250 ehci_device_intr_transfer, 251 ehci_device_intr_start, 252 ehci_device_intr_abort, 253 ehci_device_intr_close, 254 ehci_device_clear_toggle, 255 ehci_device_intr_done, 256 }; 257 258 Static struct usbd_pipe_methods ehci_device_bulk_methods = { 259 ehci_device_bulk_transfer, 260 ehci_device_bulk_start, 261 ehci_device_bulk_abort, 262 ehci_device_bulk_close, 263 ehci_device_clear_toggle, 264 ehci_device_bulk_done, 265 }; 266 267 Static struct usbd_pipe_methods ehci_device_isoc_methods = { 268 ehci_device_isoc_transfer, 269 ehci_device_isoc_start, 270 ehci_device_isoc_abort, 271 ehci_device_isoc_close, 272 ehci_noop, 273 ehci_device_isoc_done, 274 }; 275 276 usbd_status 277 ehci_init(ehci_softc_t *sc) 278 { 279 u_int32_t version, sparams, cparams, hcr; 280 u_int i; 281 usbd_status err; 282 ehci_soft_qh_t *sqh; 283 284 DPRINTF(("ehci_init: start\n")); 285 #ifdef EHCI_DEBUG 286 theehci = sc; 287 #endif 288 289 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 290 291 version = EREAD2(sc, EHCI_HCIVERSION); 292 printf("%s: EHCI version %x.%x\n", USBDEVNAME(sc->sc_bus.bdev), 293 version >> 8, version & 0xff); 294 295 sparams = EREAD4(sc, EHCI_HCSPARAMS); 296 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 297 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 298 if (EHCI_HCS_N_CC(sparams) != sc->sc_ncomp) { 299 printf("%s: wrong number of companions (%d != %d)\n", 300 USBDEVNAME(sc->sc_bus.bdev), 301 EHCI_HCS_N_CC(sparams), sc->sc_ncomp); 302 return (USBD_IOERROR); 303 } 304 if (sc->sc_ncomp > 0) { 305 printf("%s: companion controller%s, %d port%s each:", 306 USBDEVNAME(sc->sc_bus.bdev), sc->sc_ncomp!=1 ? "s" : "", 307 EHCI_HCS_N_PCC(sparams), 308 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 309 for (i = 0; i < sc->sc_ncomp; i++) 310 printf(" %s", USBDEVNAME(sc->sc_comps[i]->bdev)); 311 printf("\n"); 312 } 313 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 314 cparams = EREAD4(sc, EHCI_HCCPARAMS); 315 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 316 317 sc->sc_bus.usbrev = USBREV_2_0; 318 319 /* Reset the controller */ 320 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev))); 321 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 322 usb_delay_ms(&sc->sc_bus, 1); 323 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 324 for (i = 0; i < 100; i++) { 325 delay(10); 326 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 327 if (!hcr) 328 break; 329 } 330 if (hcr) { 331 printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 332 return (USBD_IOERROR); 333 } 334 335 /* frame list size at default, read back what we got and use that */ 336 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 337 case 0: sc->sc_flsize = 1024*4; break; 338 case 1: sc->sc_flsize = 512*4; break; 339 case 2: sc->sc_flsize = 256*4; break; 340 case 3: return (USBD_IOERROR); 341 } 342 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize, 343 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 344 if (err) 345 return (err); 346 DPRINTF(("%s: flsize=%d\n", USBDEVNAME(sc->sc_bus.bdev),sc->sc_flsize)); 347 348 /* Set up the bus struct. */ 349 sc->sc_bus.methods = &ehci_bus_methods; 350 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 351 352 sc->sc_powerhook = powerhook_establish(ehci_power, sc); 353 sc->sc_shutdownhook = shutdownhook_establish(ehci_shutdown, sc); 354 355 sc->sc_eintrs = EHCI_NORMAL_INTRS; 356 357 /* Allocate dummy QH that starts the async list. */ 358 sqh = ehci_alloc_sqh(sc); 359 if (sqh == NULL) { 360 err = USBD_NOMEM; 361 goto bad1; 362 } 363 /* Fill the QH */ 364 sqh->qh.qh_endp = 365 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 366 sqh->qh.qh_link = 367 htole32(sqh->physaddr | EHCI_LINK_QH); 368 sqh->qh.qh_curqtd = EHCI_NULL; 369 sqh->next = NULL; 370 /* Fill the overlay qTD */ 371 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 372 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 373 sqh->qh.qh_qtd.qtd_status = 374 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 375 sqh->sqtd = NULL; 376 #ifdef EHCI_DEBUG 377 if (ehcidebug) { 378 ehci_dump_sqh(sc->sc_async_head); 379 } 380 #endif 381 382 /* Point to async list */ 383 sc->sc_async_head = sqh; 384 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 385 386 usb_callout_init(sc->sc_tmo_pcd); 387 388 lockinit(&sc->sc_doorbell_lock, PZERO, "ehcidb", 0, 0); 389 390 /* Enable interrupts */ 391 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 392 393 /* Turn on controller */ 394 EOWRITE4(sc, EHCI_USBCMD, 395 EHCI_CMD_ITC_8 | /* 8 microframes */ 396 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 397 EHCI_CMD_ASE | 398 /* EHCI_CMD_PSE | */ 399 EHCI_CMD_RS); 400 401 /* Take over port ownership */ 402 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 403 404 for (i = 0; i < 100; i++) { 405 delay(10); 406 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 407 if (!hcr) 408 break; 409 } 410 if (hcr) { 411 printf("%s: run timeout\n", USBDEVNAME(sc->sc_bus.bdev)); 412 return (USBD_IOERROR); 413 } 414 415 return (USBD_NORMAL_COMPLETION); 416 417 #if 0 418 bad2: 419 ehci_free_sqh(sc, sc->sc_async_head); 420 #endif 421 bad1: 422 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 423 return (err); 424 } 425 426 int 427 ehci_intr(void *v) 428 { 429 ehci_softc_t *sc = v; 430 431 if (sc == NULL || sc->sc_dying) 432 return (0); 433 434 /* If we get an interrupt while polling, then just ignore it. */ 435 if (sc->sc_bus.use_polling) { 436 #ifdef DIAGNOSTIC 437 printf("ehci_intr: ignored interrupt while polling\n"); 438 #endif 439 return (0); 440 } 441 442 return (ehci_intr1(sc)); 443 } 444 445 Static int 446 ehci_intr1(ehci_softc_t *sc) 447 { 448 u_int32_t intrs, eintrs; 449 450 DPRINTFN(20,("ehci_intr1: enter\n")); 451 452 /* In case the interrupt occurs before initialization has completed. */ 453 if (sc == NULL) { 454 #ifdef DIAGNOSTIC 455 printf("ehci_intr: sc == NULL\n"); 456 #endif 457 return (0); 458 } 459 460 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 461 462 if (!intrs) 463 return (0); 464 465 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 466 eintrs = intrs & sc->sc_eintrs; 467 DPRINTFN(7, ("ehci_intr: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 468 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 469 (u_int)eintrs)); 470 if (!eintrs) 471 return (0); 472 473 sc->sc_bus.intr_context++; 474 sc->sc_bus.no_intrs++; 475 if (eintrs & EHCI_STS_IAA) { 476 DPRINTF(("ehci_intr1: door bell\n")); 477 wakeup(&sc->sc_async_head); 478 eintrs &= ~EHCI_STS_INT; 479 } 480 if (eintrs & EHCI_STS_INT) { 481 DPRINTF(("ehci_intr1: something is done\n")); 482 eintrs &= ~EHCI_STS_INT; 483 } 484 if (eintrs & EHCI_STS_ERRINT) { 485 DPRINTF(("ehci_intr1: some error\n")); 486 eintrs &= ~EHCI_STS_HSE; 487 } 488 if (eintrs & EHCI_STS_HSE) { 489 printf("%s: unrecoverable error, controller halted\n", 490 USBDEVNAME(sc->sc_bus.bdev)); 491 /* XXX what else */ 492 } 493 if (eintrs & EHCI_STS_PCD) { 494 ehci_pcd(sc, sc->sc_intrxfer); 495 /* 496 * Disable PCD interrupt for now, because it will be 497 * on until the port has been reset. 498 */ 499 ehci_pcd_able(sc, 0); 500 /* Do not allow RHSC interrupts > 1 per second */ 501 usb_callout(sc->sc_tmo_pcd, hz, ehci_pcd_enable, sc); 502 eintrs &= ~EHCI_STS_PCD; 503 } 504 505 sc->sc_bus.intr_context--; 506 507 if (eintrs != 0) { 508 /* Block unprocessed interrupts. */ 509 sc->sc_eintrs &= ~eintrs; 510 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 511 printf("%s: blocking intrs 0x%x\n", 512 USBDEVNAME(sc->sc_bus.bdev), eintrs); 513 } 514 515 return (1); 516 } 517 518 void 519 ehci_pcd_able(ehci_softc_t *sc, int on) 520 { 521 DPRINTFN(4, ("ehci_pcd_able: on=%d\n", on)); 522 if (on) 523 sc->sc_eintrs |= EHCI_STS_PCD; 524 else 525 sc->sc_eintrs &= ~EHCI_STS_PCD; 526 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 527 } 528 529 void 530 ehci_pcd_enable(void *v_sc) 531 { 532 ehci_softc_t *sc = v_sc; 533 534 ehci_pcd_able(sc, 1); 535 } 536 537 void 538 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 539 { 540 usbd_pipe_handle pipe; 541 struct ehci_pipe *epipe; 542 u_char *p; 543 int i, m; 544 545 if (xfer == NULL) { 546 /* Just ignore the change. */ 547 return; 548 } 549 550 pipe = xfer->pipe; 551 epipe = (struct ehci_pipe *)pipe; 552 553 p = KERNADDR(&xfer->dmabuf); 554 m = min(sc->sc_noport, xfer->length * 8 - 1); 555 memset(p, 0, xfer->length); 556 for (i = 1; i <= m; i++) { 557 /* Pick out CHANGE bits from the status reg. */ 558 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 559 p[i/8] |= 1 << (i%8); 560 } 561 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 562 xfer->actlen = xfer->length; 563 xfer->status = USBD_NORMAL_COMPLETION; 564 565 usb_transfer_complete(xfer); 566 } 567 568 void 569 ehci_softintr(void *v) 570 { 571 //ehci_softc_t *sc = v; 572 } 573 574 /* 575 * Wait here until controller claims to have an interrupt. 576 * Then call ohci_intr and return. Use timeout to avoid waiting 577 * too long. 578 */ 579 void 580 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 581 { 582 int timo = xfer->timeout; 583 int usecs; 584 u_int32_t intrs; 585 586 xfer->status = USBD_IN_PROGRESS; 587 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) { 588 usb_delay_ms(&sc->sc_bus, 1); 589 if (sc->sc_dying) 590 break; 591 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 592 sc->sc_eintrs; 593 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 594 #ifdef OHCI_DEBUG 595 if (ehcidebug > 15) 596 ehci_dumpregs(sc); 597 #endif 598 if (intrs) { 599 ehci_intr1(sc); 600 if (xfer->status != USBD_IN_PROGRESS) 601 return; 602 } 603 } 604 605 /* Timeout */ 606 DPRINTF(("ehci_waitintr: timeout\n")); 607 xfer->status = USBD_TIMEOUT; 608 usb_transfer_complete(xfer); 609 /* XXX should free TD */ 610 } 611 612 void 613 ehci_poll(struct usbd_bus *bus) 614 { 615 ehci_softc_t *sc = (ehci_softc_t *)bus; 616 #ifdef EHCI_DEBUG 617 static int last; 618 int new; 619 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 620 if (new != last) { 621 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 622 last = new; 623 } 624 #endif 625 626 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 627 ehci_intr1(sc); 628 } 629 630 int 631 ehci_detach(struct ehci_softc *sc, int flags) 632 { 633 int rv = 0; 634 635 if (sc->sc_child != NULL) 636 rv = config_detach(sc->sc_child, flags); 637 638 if (rv != 0) 639 return (rv); 640 641 usb_uncallout(sc->sc_tmo_pcd, ehci_pcd_enable, sc); 642 643 if (sc->sc_powerhook != NULL) 644 powerhook_disestablish(sc->sc_powerhook); 645 if (sc->sc_shutdownhook != NULL) 646 shutdownhook_disestablish(sc->sc_shutdownhook); 647 648 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 649 650 /* XXX free other data structures XXX */ 651 652 return (rv); 653 } 654 655 656 int 657 ehci_activate(device_ptr_t self, enum devact act) 658 { 659 struct ehci_softc *sc = (struct ehci_softc *)self; 660 int rv = 0; 661 662 switch (act) { 663 case DVACT_ACTIVATE: 664 return (EOPNOTSUPP); 665 break; 666 667 case DVACT_DEACTIVATE: 668 if (sc->sc_child != NULL) 669 rv = config_deactivate(sc->sc_child); 670 sc->sc_dying = 1; 671 break; 672 } 673 return (rv); 674 } 675 676 /* 677 * Handle suspend/resume. 678 * 679 * We need to switch to polling mode here, because this routine is 680 * called from an intterupt context. This is all right since we 681 * are almost suspended anyway. 682 */ 683 void 684 ehci_power(int why, void *v) 685 { 686 ehci_softc_t *sc = v; 687 //u_int32_t ctl; 688 int s; 689 690 #ifdef EHCI_DEBUG 691 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why)); 692 ehci_dumpregs(sc); 693 #endif 694 695 s = splhardusb(); 696 switch (why) { 697 case PWR_SUSPEND: 698 case PWR_STANDBY: 699 sc->sc_bus.use_polling++; 700 #if 0 701 OOO 702 ctl = OREAD4(sc, EHCI_CONTROL) & ~EHCI_HCFS_MASK; 703 if (sc->sc_control == 0) { 704 /* 705 * Preserve register values, in case that APM BIOS 706 * does not recover them. 707 */ 708 sc->sc_control = ctl; 709 sc->sc_intre = OREAD4(sc, EHCI_INTERRUPT_ENABLE); 710 } 711 ctl |= EHCI_HCFS_SUSPEND; 712 OWRITE4(sc, EHCI_CONTROL, ctl); 713 #endif 714 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 715 sc->sc_bus.use_polling--; 716 break; 717 case PWR_RESUME: 718 sc->sc_bus.use_polling++; 719 #if 0 720 OOO 721 /* Some broken BIOSes do not recover these values */ 722 OWRITE4(sc, EHCI_HCCA, DMAADDR(&sc->sc_hccadma)); 723 OWRITE4(sc, EHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr); 724 OWRITE4(sc, EHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr); 725 if (sc->sc_intre) 726 OWRITE4(sc, EHCI_INTERRUPT_ENABLE, 727 sc->sc_intre & (EHCI_ALL_INTRS | EHCI_MIE)); 728 if (sc->sc_control) 729 ctl = sc->sc_control; 730 else 731 ctl = OREAD4(sc, EHCI_CONTROL); 732 ctl |= EHCI_HCFS_RESUME; 733 OWRITE4(sc, EHCI_CONTROL, ctl); 734 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY); 735 ctl = (ctl & ~EHCI_HCFS_MASK) | EHCI_HCFS_OPERATIONAL; 736 OWRITE4(sc, EHCI_CONTROL, ctl); 737 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY); 738 sc->sc_control = sc->sc_intre = 0; 739 #endif 740 sc->sc_bus.use_polling--; 741 break; 742 case PWR_SOFTSUSPEND: 743 case PWR_SOFTSTANDBY: 744 case PWR_SOFTRESUME: 745 break; 746 } 747 splx(s); 748 } 749 750 /* 751 * Shut down the controller when the system is going down. 752 */ 753 void 754 ehci_shutdown(void *v) 755 { 756 ehci_softc_t *sc = v; 757 758 DPRINTF(("ehci_shutdown: stopping the HC\n")); 759 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 760 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 761 } 762 763 usbd_status 764 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 765 { 766 struct ehci_softc *sc = (struct ehci_softc *)bus; 767 768 return (usb_allocmem(&sc->sc_bus, size, 0, dma)); 769 } 770 771 void 772 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 773 { 774 struct ehci_softc *sc = (struct ehci_softc *)bus; 775 776 usb_freemem(&sc->sc_bus, dma); 777 } 778 779 usbd_xfer_handle 780 ehci_allocx(struct usbd_bus *bus) 781 { 782 struct ehci_softc *sc = (struct ehci_softc *)bus; 783 usbd_xfer_handle xfer; 784 785 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 786 if (xfer != NULL) 787 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, xfer, next); 788 else 789 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 790 if (xfer != NULL) 791 memset(xfer, 0, sizeof (struct ehci_xfer)); 792 return (xfer); 793 } 794 795 void 796 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 797 { 798 struct ehci_softc *sc = (struct ehci_softc *)bus; 799 800 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 801 } 802 803 Static void 804 ehci_device_clear_toggle(usbd_pipe_handle pipe) 805 { 806 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 807 808 printf("ehci_device_clear_toggle: epipe=%p\n", epipe); 809 #if 0 810 OOO 811 epipe->sed->ed.ed_headp &= htole32(~EHCI_TOGGLECARRY); 812 #endif 813 } 814 815 Static void 816 ehci_noop(usbd_pipe_handle pipe) 817 { 818 } 819 820 #ifdef EHCI_DEBUG 821 void 822 ehci_dumpregs(ehci_softc_t *sc) 823 { 824 int i; 825 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 826 EOREAD4(sc, EHCI_USBCMD), 827 EOREAD4(sc, EHCI_USBSTS), 828 EOREAD4(sc, EHCI_USBINTR)); 829 printf("frindex=0x08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 830 EOREAD4(sc, EHCI_FRINDEX), 831 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 832 EOREAD4(sc, EHCI_PERIODICLISTBASE), 833 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 834 for (i = 1; i <= sc->sc_noport; i++) 835 printf("port %d status=0x%08x\n", i, 836 EOREAD4(sc, EHCI_PORTSC(i))); 837 } 838 839 void 840 ehci_dump() 841 { 842 ehci_dumpregs(theehci); 843 } 844 845 void 846 ehci_dump_link(ehci_link_t link, int type) 847 { 848 link = le32toh(link); 849 printf("0x%08x", link); 850 if (link & EHCI_LINK_TERMINATE) 851 printf("<T>"); 852 else { 853 printf("<"); 854 if (type) { 855 switch (EHCI_LINK_TYPE(link)) { 856 case EHCI_LINK_ITD: printf("ITD"); break; 857 case EHCI_LINK_QH: printf("QH"); break; 858 case EHCI_LINK_SITD: printf("SITD"); break; 859 case EHCI_LINK_FSTN: printf("FSTN"); break; 860 } 861 } 862 printf(">"); 863 } 864 } 865 866 void 867 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 868 { 869 for (; sqtd; sqtd = sqtd->nextqtd) 870 ehci_dump_sqtd(sqtd); 871 } 872 873 void 874 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 875 { 876 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 877 ehci_dump_qtd(&sqtd->qtd); 878 } 879 880 void 881 ehci_dump_qtd(ehci_qtd_t *qtd) 882 { 883 u_int32_t s; 884 char sbuf[128]; 885 886 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 887 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 888 printf("\n"); 889 s = le32toh(qtd->qtd_status); 890 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), 891 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 892 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf)); 893 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 894 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 895 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 896 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 897 EHCI_QTD_GET_PID(s), sbuf); 898 for (s = 0; s < 5; s++) 899 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 900 } 901 902 void 903 ehci_dump_sqh(ehci_soft_qh_t *sqh) 904 { 905 ehci_qh_t *qh = &sqh->qh; 906 u_int32_t endp, endphub; 907 908 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 909 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 910 endp = le32toh(qh->qh_endp); 911 printf(" endp=0x%08x\n", endp); 912 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 913 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 914 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 915 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 916 printf(" mpl=0x%x ctl=%d nrl=%d\n", 917 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 918 EHCI_QH_GET_NRL(endp)); 919 endphub = le32toh(qh->qh_endphub); 920 printf(" endphub=0x%08x\n", endphub); 921 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 922 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 923 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 924 EHCI_QH_GET_MULT(endphub)); 925 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 926 printf("Overlay qTD:\n"); 927 ehci_dump_qtd(&qh->qh_qtd); 928 } 929 930 #endif 931 932 usbd_status 933 ehci_open(usbd_pipe_handle pipe) 934 { 935 usbd_device_handle dev = pipe->device; 936 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 937 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 938 u_int8_t addr = dev->address; 939 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 940 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 941 ehci_soft_qh_t *sqh; 942 usbd_status err; 943 #if 0 944 ehci_soft_itd_t *sitd; 945 ehci_physaddr_t tdphys; 946 u_int32_t fmt; 947 int ival; 948 #endif 949 int s; 950 int speed, naks; 951 952 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 953 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 954 955 if (sc->sc_dying) 956 return (USBD_IOERROR); 957 958 if (addr == sc->sc_addr) { 959 switch (ed->bEndpointAddress) { 960 case USB_CONTROL_ENDPOINT: 961 pipe->methods = &ehci_root_ctrl_methods; 962 break; 963 case UE_DIR_IN | EHCI_INTR_ENDPT: 964 pipe->methods = &ehci_root_intr_methods; 965 break; 966 default: 967 return (USBD_INVAL); 968 } 969 return (USBD_NORMAL_COMPLETION); 970 } 971 972 switch (dev->speed) { 973 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 974 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 975 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 976 default: panic("ehci_open: bad device speed %d\n", dev->speed); 977 } 978 naks = 8; /* XXX */ 979 sqh = ehci_alloc_sqh(sc); 980 if (sqh == NULL) 981 goto bad0; 982 /* qh_link filled when the QH is added */ 983 sqh->qh.qh_endp = htole32( 984 EHCI_QH_SET_ADDR(addr) | 985 EHCI_QH_SET_ENDPT(ed->bEndpointAddress) | 986 EHCI_QH_SET_EPS(speed) | /* XXX */ 987 /* XXX EHCI_QH_DTC ? */ 988 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 989 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 990 EHCI_QH_CTL : 0) | 991 EHCI_QH_SET_NRL(naks) 992 ); 993 sqh->qh.qh_endphub = htole32( 994 EHCI_QH_SET_MULT(1) 995 /* XXX TT stuff */ 996 /* XXX interrupt mask */ 997 ); 998 sqh->qh.qh_curqtd = EHCI_NULL; 999 /* Fill the overlay qTD */ 1000 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1001 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1002 sqh->qh.qh_qtd.qtd_status = htole32(0); 1003 1004 epipe->sqh = sqh; 1005 1006 switch (xfertype) { 1007 case UE_CONTROL: 1008 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1009 0, &epipe->u.ctl.reqdma); 1010 if (err) 1011 goto bad1; 1012 pipe->methods = &ehci_device_ctrl_methods; 1013 s = splusb(); 1014 ehci_add_qh(sqh, sc->sc_async_head); 1015 splx(s); 1016 break; 1017 case UE_BULK: 1018 pipe->methods = &ehci_device_bulk_methods; 1019 s = splusb(); 1020 ehci_add_qh(sqh, sc->sc_async_head); 1021 splx(s); 1022 break; 1023 default: 1024 return (USBD_INVAL); 1025 } 1026 return (USBD_NORMAL_COMPLETION); 1027 1028 bad1: 1029 ehci_free_sqh(sc, sqh); 1030 bad0: 1031 return (USBD_NOMEM); 1032 } 1033 1034 /* 1035 * Add an ED to the schedule. Called at splusb(). 1036 */ 1037 void 1038 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1039 { 1040 SPLUSBCHECK; 1041 1042 sqh->next = head->next; 1043 sqh->qh.qh_link = head->qh.qh_link; 1044 head->next = sqh; 1045 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1046 1047 #ifdef EHCI_DEBUG 1048 if (ehcidebug > 0) { 1049 printf("ehci_add_qh:\n"); 1050 ehci_dump_sqh(sqh); 1051 } 1052 #endif 1053 } 1054 1055 /* 1056 * Remove an ED from the schedule. Called at splusb(). 1057 */ 1058 void 1059 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1060 { 1061 ehci_soft_qh_t *p; 1062 1063 SPLUSBCHECK; 1064 /* XXX */ 1065 for (p = head; p == NULL && p->next != sqh; p = p->next) 1066 ; 1067 if (p == NULL) 1068 panic("ehci_rem_qh: ED not found\n"); 1069 p->next = sqh->next; 1070 p->qh.qh_link = sqh->qh.qh_link; 1071 1072 ehci_sync_hc(sc); 1073 } 1074 1075 /* 1076 * Ensure that the HC has released all references to the QH. We do this 1077 * by asking for a Async Advance Doorbell interrupt and then we wait for 1078 * the interrupt. 1079 * To make this easier we first obtain exclusive use of the doorbell. 1080 */ 1081 void 1082 ehci_sync_hc(ehci_softc_t *sc) 1083 { 1084 int s, error; 1085 1086 if (sc->sc_dying) { 1087 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1088 return; 1089 } 1090 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1091 lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE, NULL); /* get doorbell */ 1092 s = splhardusb(); 1093 /* ask for doorbell */ 1094 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1095 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1096 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1097 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1098 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1099 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1100 splx(s); 1101 lockmgr(&sc->sc_doorbell_lock, LK_RELEASE, NULL); /* release doorbell */ 1102 #ifdef DIAGNOSTIC 1103 if (error) 1104 printf("ehci_sync_hc: tsleep() = %d\n", error); 1105 #endif 1106 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1107 } 1108 1109 /***********/ 1110 1111 /* 1112 * Data structures and routines to emulate the root hub. 1113 */ 1114 Static usb_device_descriptor_t ehci_devd = { 1115 USB_DEVICE_DESCRIPTOR_SIZE, 1116 UDESC_DEVICE, /* type */ 1117 {0x00, 0x02}, /* USB version */ 1118 UDCLASS_HUB, /* class */ 1119 UDSUBCLASS_HUB, /* subclass */ 1120 UDPROTO_HSHUBSTT, /* protocol */ 1121 64, /* max packet */ 1122 {0},{0},{0x00,0x01}, /* device id */ 1123 1,2,0, /* string indicies */ 1124 1 /* # of configurations */ 1125 }; 1126 1127 Static usb_device_qualifier_t ehci_odevd = { 1128 USB_DEVICE_DESCRIPTOR_SIZE, 1129 UDESC_DEVICE_QUALIFIER, /* type */ 1130 {0x00, 0x02}, /* USB version */ 1131 UDCLASS_HUB, /* class */ 1132 UDSUBCLASS_HUB, /* subclass */ 1133 UDPROTO_FSHUB, /* protocol */ 1134 64, /* max packet */ 1135 1, /* # of configurations */ 1136 0 1137 }; 1138 1139 Static usb_config_descriptor_t ehci_confd = { 1140 USB_CONFIG_DESCRIPTOR_SIZE, 1141 UDESC_CONFIG, 1142 {USB_CONFIG_DESCRIPTOR_SIZE + 1143 USB_INTERFACE_DESCRIPTOR_SIZE + 1144 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1145 1, 1146 1, 1147 0, 1148 UC_SELF_POWERED, 1149 0 /* max power */ 1150 }; 1151 1152 Static usb_interface_descriptor_t ehci_ifcd = { 1153 USB_INTERFACE_DESCRIPTOR_SIZE, 1154 UDESC_INTERFACE, 1155 0, 1156 0, 1157 1, 1158 UICLASS_HUB, 1159 UISUBCLASS_HUB, 1160 UIPROTO_HSHUBSTT, 1161 0 1162 }; 1163 1164 Static usb_endpoint_descriptor_t ehci_endpd = { 1165 USB_ENDPOINT_DESCRIPTOR_SIZE, 1166 UDESC_ENDPOINT, 1167 UE_DIR_IN | EHCI_INTR_ENDPT, 1168 UE_INTERRUPT, 1169 {8, 0}, /* max packet */ 1170 255 1171 }; 1172 1173 Static usb_hub_descriptor_t ehci_hubd = { 1174 USB_HUB_DESCRIPTOR_SIZE, 1175 UDESC_HUB, 1176 0, 1177 {0,0}, 1178 0, 1179 0, 1180 {0}, 1181 }; 1182 1183 Static int 1184 ehci_str(p, l, s) 1185 usb_string_descriptor_t *p; 1186 int l; 1187 char *s; 1188 { 1189 int i; 1190 1191 if (l == 0) 1192 return (0); 1193 p->bLength = 2 * strlen(s) + 2; 1194 if (l == 1) 1195 return (1); 1196 p->bDescriptorType = UDESC_STRING; 1197 l -= 2; 1198 for (i = 0; s[i] && l > 1; i++, l -= 2) 1199 USETW2(p->bString[i], 0, s[i]); 1200 return (2*i+2); 1201 } 1202 1203 /* 1204 * Simulate a hardware hub by handling all the necessary requests. 1205 */ 1206 Static usbd_status 1207 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1208 { 1209 usbd_status err; 1210 1211 /* Insert last in queue. */ 1212 err = usb_insert_transfer(xfer); 1213 if (err) 1214 return (err); 1215 1216 /* Pipe isn't running, start first */ 1217 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1218 } 1219 1220 Static usbd_status 1221 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1222 { 1223 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 1224 usb_device_request_t *req; 1225 void *buf = NULL; 1226 int port, i; 1227 int s, len, value, index, l, totlen = 0; 1228 usb_port_status_t ps; 1229 usb_hub_descriptor_t hubd; 1230 usbd_status err; 1231 u_int32_t v; 1232 1233 if (sc->sc_dying) 1234 return (USBD_IOERROR); 1235 1236 #ifdef DIAGNOSTIC 1237 if (!(xfer->rqflags & URQ_REQUEST)) 1238 /* XXX panic */ 1239 return (USBD_INVAL); 1240 #endif 1241 req = &xfer->request; 1242 1243 DPRINTFN(4,("ehci_root_ctrl_control type=0x%02x request=%02x\n", 1244 req->bmRequestType, req->bRequest)); 1245 1246 len = UGETW(req->wLength); 1247 value = UGETW(req->wValue); 1248 index = UGETW(req->wIndex); 1249 1250 if (len != 0) 1251 buf = KERNADDR(&xfer->dmabuf); 1252 1253 #define C(x,y) ((x) | ((y) << 8)) 1254 switch(C(req->bRequest, req->bmRequestType)) { 1255 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 1256 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 1257 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 1258 /* 1259 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 1260 * for the integrated root hub. 1261 */ 1262 break; 1263 case C(UR_GET_CONFIG, UT_READ_DEVICE): 1264 if (len > 0) { 1265 *(u_int8_t *)buf = sc->sc_conf; 1266 totlen = 1; 1267 } 1268 break; 1269 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 1270 DPRINTFN(8,("ehci_root_ctrl_control wValue=0x%04x\n", value)); 1271 switch(value >> 8) { 1272 case UDESC_DEVICE: 1273 if ((value & 0xff) != 0) { 1274 err = USBD_IOERROR; 1275 goto ret; 1276 } 1277 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1278 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 1279 memcpy(buf, &ehci_devd, l); 1280 break; 1281 /* 1282 * We can't really operate at another speed, but the spec says 1283 * we need this descriptor. 1284 */ 1285 case UDESC_DEVICE_QUALIFIER: 1286 if ((value & 0xff) != 0) { 1287 err = USBD_IOERROR; 1288 goto ret; 1289 } 1290 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 1291 memcpy(buf, &ehci_odevd, l); 1292 break; 1293 /* 1294 * We can't really operate at another speed, but the spec says 1295 * we need this descriptor. 1296 */ 1297 case UDESC_OTHER_SPEED_CONFIGURATION: 1298 case UDESC_CONFIG: 1299 if ((value & 0xff) != 0) { 1300 err = USBD_IOERROR; 1301 goto ret; 1302 } 1303 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 1304 memcpy(buf, &ehci_confd, l); 1305 ((usb_config_descriptor_t *)buf)->bDescriptorType = 1306 value >> 8; 1307 buf = (char *)buf + l; 1308 len -= l; 1309 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 1310 totlen += l; 1311 memcpy(buf, &ehci_ifcd, l); 1312 buf = (char *)buf + l; 1313 len -= l; 1314 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 1315 totlen += l; 1316 memcpy(buf, &ehci_endpd, l); 1317 break; 1318 case UDESC_STRING: 1319 if (len == 0) 1320 break; 1321 *(u_int8_t *)buf = 0; 1322 totlen = 1; 1323 switch (value & 0xff) { 1324 case 1: /* Vendor */ 1325 totlen = ehci_str(buf, len, sc->sc_vendor); 1326 break; 1327 case 2: /* Product */ 1328 totlen = ehci_str(buf, len, "EHCI root hub"); 1329 break; 1330 } 1331 break; 1332 default: 1333 err = USBD_IOERROR; 1334 goto ret; 1335 } 1336 break; 1337 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 1338 if (len > 0) { 1339 *(u_int8_t *)buf = 0; 1340 totlen = 1; 1341 } 1342 break; 1343 case C(UR_GET_STATUS, UT_READ_DEVICE): 1344 if (len > 1) { 1345 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 1346 totlen = 2; 1347 } 1348 break; 1349 case C(UR_GET_STATUS, UT_READ_INTERFACE): 1350 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 1351 if (len > 1) { 1352 USETW(((usb_status_t *)buf)->wStatus, 0); 1353 totlen = 2; 1354 } 1355 break; 1356 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 1357 if (value >= USB_MAX_DEVICES) { 1358 err = USBD_IOERROR; 1359 goto ret; 1360 } 1361 sc->sc_addr = value; 1362 break; 1363 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 1364 if (value != 0 && value != 1) { 1365 err = USBD_IOERROR; 1366 goto ret; 1367 } 1368 sc->sc_conf = value; 1369 break; 1370 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 1371 break; 1372 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 1373 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 1374 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 1375 err = USBD_IOERROR; 1376 goto ret; 1377 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 1378 break; 1379 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 1380 break; 1381 /* Hub requests */ 1382 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 1383 break; 1384 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 1385 DPRINTFN(8, ("ehci_root_ctrl_control: UR_CLEAR_PORT_FEATURE " 1386 "port=%d feature=%d\n", 1387 index, value)); 1388 if (index < 1 || index > sc->sc_noport) { 1389 err = USBD_IOERROR; 1390 goto ret; 1391 } 1392 port = EHCI_PORTSC(index); 1393 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 1394 switch(value) { 1395 case UHF_PORT_ENABLE: 1396 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 1397 break; 1398 case UHF_PORT_SUSPEND: 1399 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP); 1400 break; 1401 case UHF_PORT_POWER: 1402 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 1403 break; 1404 case UHF_PORT_TEST: 1405 DPRINTFN(2,("ehci_root_ctrl_transfer: clear port test " 1406 "%d\n", index)); 1407 break; 1408 case UHF_PORT_INDICATOR: 1409 DPRINTFN(2,("ehci_root_ctrl_transfer: clear port ind " 1410 "%d\n", index)); 1411 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 1412 break; 1413 case UHF_C_PORT_CONNECTION: 1414 EOWRITE4(sc, port, v | EHCI_PS_CSC); 1415 break; 1416 case UHF_C_PORT_ENABLE: 1417 EOWRITE4(sc, port, v | EHCI_PS_PEC); 1418 break; 1419 case UHF_C_PORT_SUSPEND: 1420 /* how? */ 1421 break; 1422 case UHF_C_PORT_OVER_CURRENT: 1423 EOWRITE4(sc, port, v | EHCI_PS_OCC); 1424 break; 1425 case UHF_C_PORT_RESET: 1426 sc->sc_isreset = 0; 1427 break; 1428 default: 1429 err = USBD_IOERROR; 1430 goto ret; 1431 } 1432 #if 0 1433 switch(value) { 1434 case UHF_C_PORT_CONNECTION: 1435 case UHF_C_PORT_ENABLE: 1436 case UHF_C_PORT_SUSPEND: 1437 case UHF_C_PORT_OVER_CURRENT: 1438 case UHF_C_PORT_RESET: 1439 /* Enable RHSC interrupt if condition is cleared. */ 1440 if ((OREAD4(sc, port) >> 16) == 0) 1441 ehci_pcd_able(sc, 1); 1442 break; 1443 default: 1444 break; 1445 } 1446 #endif 1447 break; 1448 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 1449 if (value != 0) { 1450 err = USBD_IOERROR; 1451 goto ret; 1452 } 1453 hubd = ehci_hubd; 1454 hubd.bNbrPorts = sc->sc_noport; 1455 v = EOREAD4(sc, EHCI_HCSPARAMS); 1456 USETW(hubd.wHubCharacteristics, 1457 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 1458 EHCI_HCS_P_INCICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 1459 ? UHD_PORT_IND : 0); 1460 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 1461 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 1462 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 1463 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 1464 l = min(len, hubd.bDescLength); 1465 totlen = l; 1466 memcpy(buf, &hubd, l); 1467 break; 1468 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 1469 if (len != 4) { 1470 err = USBD_IOERROR; 1471 goto ret; 1472 } 1473 memset(buf, 0, len); /* ? XXX */ 1474 totlen = len; 1475 break; 1476 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 1477 DPRINTFN(8,("ehci_root_ctrl_transfer: get port status i=%d\n", 1478 index)); 1479 if (index < 1 || index > sc->sc_noport) { 1480 err = USBD_IOERROR; 1481 goto ret; 1482 } 1483 if (len != 4) { 1484 err = USBD_IOERROR; 1485 goto ret; 1486 } 1487 v = EOREAD4(sc, EHCI_PORTSC(index)); 1488 DPRINTFN(8,("ehci_root_ctrl_transfer: port status=0x%04x\n", 1489 v)); 1490 i = UPS_HIGH_SPEED; 1491 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 1492 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 1493 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 1494 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 1495 if (v & EHCI_PS_PR) i |= UPS_RESET; 1496 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 1497 USETW(ps.wPortStatus, i); 1498 i = 0; 1499 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 1500 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 1501 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 1502 if (sc->sc_isreset) i |= UPS_C_PORT_RESET; 1503 USETW(ps.wPortChange, i); 1504 l = min(len, sizeof ps); 1505 memcpy(buf, &ps, l); 1506 totlen = l; 1507 break; 1508 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 1509 err = USBD_IOERROR; 1510 goto ret; 1511 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 1512 break; 1513 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 1514 if (index < 1 || index > sc->sc_noport) { 1515 err = USBD_IOERROR; 1516 goto ret; 1517 } 1518 port = EHCI_PORTSC(index); 1519 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 1520 switch(value) { 1521 case UHF_PORT_ENABLE: 1522 EOWRITE4(sc, port, v | EHCI_PS_PE); 1523 break; 1524 case UHF_PORT_SUSPEND: 1525 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 1526 break; 1527 case UHF_PORT_RESET: 1528 DPRINTFN(5,("ehci_root_ctrl_transfer: reset port %d\n", 1529 index)); 1530 if (EHCI_PS_IS_LOWSPEED(v)) { 1531 /* Low speed device, give up ownership. */ 1532 ehci_disown(sc, index, 1); 1533 break; 1534 } 1535 /* Start reset sequence. */ 1536 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 1537 EOWRITE4(sc, port, v | EHCI_PS_PR); 1538 /* Wait for reset to complete. */ 1539 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 1540 if (sc->sc_dying) { 1541 err = USBD_IOERROR; 1542 goto ret; 1543 } 1544 /* Terminate reset sequence. */ 1545 EOWRITE4(sc, port, v); 1546 /* Wait for HC to complete reset. */ 1547 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 1548 if (sc->sc_dying) { 1549 err = USBD_IOERROR; 1550 goto ret; 1551 } 1552 v = EOREAD4(sc, port); 1553 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 1554 if (v & EHCI_PS_PR) { 1555 printf("%s: port reset timeout\n", 1556 USBDEVNAME(sc->sc_bus.bdev)); 1557 return (USBD_TIMEOUT); 1558 } 1559 if (!(v & EHCI_PS_PE)) { 1560 /* Not a high speed device, give up ownership.*/ 1561 ehci_disown(sc, index, 0); 1562 break; 1563 } 1564 sc->sc_isreset = 1; 1565 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 1566 index, v)); 1567 break; 1568 case UHF_PORT_POWER: 1569 DPRINTFN(2,("ehci_root_ctrl_transfer: set port power " 1570 "%d\n", index)); 1571 EOWRITE4(sc, port, v | EHCI_PS_PP); 1572 break; 1573 case UHF_PORT_TEST: 1574 DPRINTFN(2,("ehci_root_ctrl_transfer: set port test " 1575 "%d\n", index)); 1576 break; 1577 case UHF_PORT_INDICATOR: 1578 DPRINTFN(2,("ehci_root_ctrl_transfer: set port ind " 1579 "%d\n", index)); 1580 EOWRITE4(sc, port, v | EHCI_PS_PIC); 1581 break; 1582 default: 1583 err = USBD_IOERROR; 1584 goto ret; 1585 } 1586 break; 1587 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 1588 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 1589 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 1590 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 1591 break; 1592 default: 1593 err = USBD_IOERROR; 1594 goto ret; 1595 } 1596 xfer->actlen = totlen; 1597 err = USBD_NORMAL_COMPLETION; 1598 ret: 1599 xfer->status = err; 1600 s = splusb(); 1601 usb_transfer_complete(xfer); 1602 splx(s); 1603 return (USBD_IN_PROGRESS); 1604 } 1605 1606 void 1607 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 1608 { 1609 int i, port; 1610 u_int32_t v; 1611 1612 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 1613 #ifdef DIAGNOSTIC 1614 if (sc->sc_npcomp != 0) { 1615 i = (index-1) / sc->sc_npcomp; 1616 if (i >= sc->sc_ncomp) 1617 printf("%s: strange port\n", 1618 USBDEVNAME(sc->sc_bus.bdev)); 1619 else 1620 printf("%s: handing over %s speed device on " 1621 "port %d to %s\n", 1622 USBDEVNAME(sc->sc_bus.bdev), 1623 lowspeed ? "low" : "full", 1624 index, USBDEVNAME(sc->sc_comps[i]->bdev)); 1625 } else { 1626 printf("%s: npcomp == 0\n", USBDEVNAME(sc->sc_bus.bdev)); 1627 } 1628 #endif 1629 port = EHCI_PORTSC(index); 1630 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 1631 EOWRITE4(sc, port, v | EHCI_PS_PO); 1632 } 1633 1634 /* Abort a root control request. */ 1635 Static void 1636 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 1637 { 1638 /* Nothing to do, all transfers are synchronous. */ 1639 } 1640 1641 /* Close the root pipe. */ 1642 Static void 1643 ehci_root_ctrl_close(usbd_pipe_handle pipe) 1644 { 1645 DPRINTF(("ehci_root_ctrl_close\n")); 1646 /* Nothing to do. */ 1647 } 1648 1649 void 1650 ehci_root_intr_done(usbd_xfer_handle xfer) 1651 { 1652 xfer->hcpriv = NULL; 1653 } 1654 1655 Static usbd_status 1656 ehci_root_intr_transfer(usbd_xfer_handle xfer) 1657 { 1658 usbd_status err; 1659 1660 /* Insert last in queue. */ 1661 err = usb_insert_transfer(xfer); 1662 if (err) 1663 return (err); 1664 1665 /* Pipe isn't running, start first */ 1666 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1667 } 1668 1669 Static usbd_status 1670 ehci_root_intr_start(usbd_xfer_handle xfer) 1671 { 1672 usbd_pipe_handle pipe = xfer->pipe; 1673 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 1674 1675 if (sc->sc_dying) 1676 return (USBD_IOERROR); 1677 1678 sc->sc_intrxfer = xfer; 1679 1680 return (USBD_IN_PROGRESS); 1681 } 1682 1683 /* Abort a root interrupt request. */ 1684 Static void 1685 ehci_root_intr_abort(usbd_xfer_handle xfer) 1686 { 1687 int s; 1688 1689 if (xfer->pipe->intrxfer == xfer) { 1690 DPRINTF(("ehci_root_intr_abort: remove\n")); 1691 xfer->pipe->intrxfer = NULL; 1692 } 1693 xfer->status = USBD_CANCELLED; 1694 s = splusb(); 1695 usb_transfer_complete(xfer); 1696 splx(s); 1697 } 1698 1699 /* Close the root pipe. */ 1700 Static void 1701 ehci_root_intr_close(usbd_pipe_handle pipe) 1702 { 1703 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 1704 1705 DPRINTF(("ehci_root_intr_close\n")); 1706 1707 sc->sc_intrxfer = NULL; 1708 } 1709 1710 void 1711 ehci_root_ctrl_done(usbd_xfer_handle xfer) 1712 { 1713 xfer->hcpriv = NULL; 1714 } 1715 1716 /************************/ 1717 1718 ehci_soft_qh_t * 1719 ehci_alloc_sqh(ehci_softc_t *sc) 1720 { 1721 ehci_soft_qh_t *sqh; 1722 usbd_status err; 1723 int i, offs; 1724 usb_dma_t dma; 1725 1726 if (sc->sc_freeqhs == NULL) { 1727 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 1728 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 1729 EHCI_PAGE_SIZE, &dma); 1730 if (err) 1731 return (NULL); 1732 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 1733 offs = i * EHCI_SQH_SIZE; 1734 sqh = (ehci_soft_qh_t *)((char *)KERNADDR(&dma) + offs); 1735 sqh->physaddr = DMAADDR(&dma) + offs; 1736 sqh->next = sc->sc_freeqhs; 1737 sc->sc_freeqhs = sqh; 1738 } 1739 } 1740 sqh = sc->sc_freeqhs; 1741 sc->sc_freeqhs = sqh->next; 1742 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 1743 sqh->next = NULL; 1744 return (sqh); 1745 } 1746 1747 void 1748 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 1749 { 1750 sqh->next = sc->sc_freeqhs; 1751 sc->sc_freeqhs = sqh; 1752 } 1753 1754 ehci_soft_qtd_t * 1755 ehci_alloc_sqtd(ehci_softc_t *sc) 1756 { 1757 ehci_soft_qtd_t *sqtd; 1758 usbd_status err; 1759 int i, offs; 1760 usb_dma_t dma; 1761 int s; 1762 1763 if (sc->sc_freeqtds == NULL) { 1764 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 1765 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 1766 EHCI_PAGE_SIZE, &dma); 1767 if (err) 1768 return (NULL); 1769 s = splusb(); 1770 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 1771 offs = i * EHCI_SQTD_SIZE; 1772 sqtd = (ehci_soft_qtd_t *)((char *)KERNADDR(&dma)+offs); 1773 sqtd->physaddr = DMAADDR(&dma) + offs; 1774 sqtd->nextqtd = sc->sc_freeqtds; 1775 sc->sc_freeqtds = sqtd; 1776 } 1777 splx(s); 1778 } 1779 1780 s = splusb(); 1781 sqtd = sc->sc_freeqtds; 1782 sc->sc_freeqtds = sqtd->nextqtd; 1783 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 1784 sqtd->nextqtd = NULL; 1785 sqtd->xfer = NULL; 1786 splx(s); 1787 1788 return (sqtd); 1789 } 1790 1791 void 1792 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 1793 { 1794 int s; 1795 1796 s = splusb(); 1797 sqtd->nextqtd = sc->sc_freeqtds; 1798 sc->sc_freeqtds = sqtd; 1799 splx(s); 1800 } 1801 1802 usbd_status 1803 ehci_alloc_std_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 1804 int alen, int rd, usbd_xfer_handle xfer, 1805 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 1806 { 1807 ehci_soft_qtd_t *next, *cur; 1808 ehci_physaddr_t dataphys, dataphysend, nextphys; 1809 u_int32_t qtdstatus; 1810 int len, curlen; 1811 int i; 1812 usb_dma_t *dma = &xfer->dmabuf; 1813 1814 DPRINTFN(alen < 4096,("ehci_alloc_std_chain: start len=%d\n", alen)); 1815 1816 len = alen; 1817 dataphys = DMAADDR(dma); 1818 dataphysend = EHCI_PAGE(dataphys + len - 1); 1819 qtdstatus = htole32( 1820 EHCI_QTD_SET_STATUS(EHCI_QTD_ACTIVE) | 1821 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 1822 EHCI_QTD_SET_CERR(3) 1823 /* IOC set below */ 1824 /* BYTES set below */ 1825 /* XXX Data toggle */ 1826 ); 1827 1828 cur = ehci_alloc_sqtd(sc); 1829 if (cur == NULL) 1830 goto nomem; 1831 *sp = cur; 1832 for (;;) { 1833 /* The EHCI hardware can handle at most 4 page crossings. */ 1834 if (EHCI_PAGE(dataphys) == dataphysend || 1835 EHCI_PAGE(dataphys) + EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE 1836 == dataphysend) { 1837 /* we can handle it in this QTD */ 1838 curlen = len; 1839 } else { 1840 #if 0 1841 /* must use multiple TDs, fill as much as possible. */ 1842 curlen = 2 * EHCI_PAGE_SIZE - 1843 (dataphys & (EHCI_PAGE_SIZE-1)); 1844 /* the length must be a multiple of the max size */ 1845 curlen -= curlen % UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 1846 #ifdef DIAGNOSTIC 1847 if (curlen == 0) 1848 panic("ehci_alloc_std: curlen == 0\n"); 1849 #endif 1850 #else 1851 printf("ehci_alloc_std_chain: multiple QTDs\n"); 1852 return (USBD_NOMEM); 1853 #endif 1854 } 1855 DPRINTFN(4,("ehci_alloc_std_chain: dataphys=0x%08x " 1856 "dataphysend=0x%08x len=%d curlen=%d\n", 1857 dataphys, dataphysend, 1858 len, curlen)); 1859 len -= curlen; 1860 1861 if (len != 0) { 1862 next = ehci_alloc_sqtd(sc); 1863 if (next == NULL) 1864 goto nomem; 1865 nextphys = next->physaddr; 1866 } else { 1867 next = NULL; 1868 nextphys = EHCI_NULL; 1869 } 1870 1871 for (i = 0; i * EHCI_PAGE_SIZE < curlen; i++) { 1872 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 1873 if (i != 0) /* use offset only in first buffer */ 1874 a = EHCI_PAGE(a); 1875 cur->qtd.qtd_buffer[i] = htole32(a); 1876 } 1877 cur->nextqtd = next; 1878 cur->qtd.qtd_next = cur->qtd.qtd_altnext = htole32(nextphys); 1879 cur->qtd.qtd_status = 1880 qtdstatus | htole32(EHCI_QTD_SET_BYTES(curlen)); 1881 cur->xfer = xfer; 1882 DPRINTFN(10,("ehci_alloc_std_chain: cbp=0x%08x be=0x%08x\n", 1883 dataphys, dataphys + curlen - 1)); 1884 if (len == 0) 1885 break; 1886 DPRINTFN(10,("ehci_alloc_std_chain: extend chain\n")); 1887 dataphys += curlen; 1888 cur = next; 1889 } 1890 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 1891 *ep = cur; 1892 1893 return (USBD_NORMAL_COMPLETION); 1894 1895 nomem: 1896 /* XXX free chain */ 1897 return (USBD_NOMEM); 1898 } 1899 1900 /****************/ 1901 1902 /* 1903 * Close a reqular pipe. 1904 * Assumes that there are no pending transactions. 1905 */ 1906 void 1907 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 1908 { 1909 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1910 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 1911 ehci_soft_qh_t *sqh = epipe->sqh; 1912 int s; 1913 1914 s = splusb(); 1915 ehci_rem_qh(sc, sqh, head); 1916 splx(s); 1917 ehci_free_sqh(sc, epipe->sqh); 1918 } 1919 1920 /* 1921 * Abort a device request. 1922 * If this routine is called at splusb() it guarantees that the request 1923 * will be removed from the hardware scheduling and that the callback 1924 * for it will be called with USBD_CANCELLED status. 1925 * It's impossible to guarantee that the requested transfer will not 1926 * have happened since the hardware runs concurrently. 1927 * If the transaction has already happened we rely on the ordinary 1928 * interrupt processing to process it. 1929 */ 1930 void 1931 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 1932 { 1933 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 1934 ehci_soft_qh_t *sqh = epipe->sqh; 1935 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 1936 #if 0 1937 ehci_soft_td_t *p, *n; 1938 ehci_physaddr_t headp; 1939 int hit; 1940 #endif 1941 int s; 1942 1943 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p sqh=%p\n", xfer, epipe,sqh)); 1944 1945 if (sc->sc_dying) { 1946 /* If we're dying, just do the software part. */ 1947 s = splusb(); 1948 xfer->status = status; /* make software ignore it */ 1949 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 1950 usb_transfer_complete(xfer); 1951 splx(s); 1952 return; 1953 } 1954 1955 if (xfer->device->bus->intr_context || !curproc) 1956 panic("ehci_abort_xfer: not in process context\n"); 1957 1958 /* 1959 * Step 1: Make interrupt routine and hardware ignore xfer. 1960 */ 1961 s = splusb(); 1962 xfer->status = status; /* make software ignore it */ 1963 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer); 1964 splx(s); 1965 /* XXX */ 1966 1967 /* 1968 * Step 2: Wait until we know hardware has finished any possible 1969 * use of the xfer. Also make sure the soft interrupt routine 1970 * has run. 1971 */ 1972 usb_delay_ms(epipe->pipe.device->bus, 1); /* Hardware finishes in 1ms */ 1973 /* XXX should have some communication with softintr() to know 1974 when it's done */ 1975 usb_delay_ms(epipe->pipe.device->bus, 250); 1976 1977 /* 1978 * Step 3: Remove any vestiges of the xfer from the hardware. 1979 * The complication here is that the hardware may have executed 1980 * beyond the xfer we're trying to abort. So as we're scanning 1981 * the TDs of this xfer we check if the hardware points to 1982 * any of them. 1983 */ 1984 s = splusb(); /* XXX why? */ 1985 /* XXX */ 1986 1987 /* 1988 * Step 4: Turn on hardware again. 1989 */ 1990 /* XXX */ 1991 1992 /* 1993 * Step 5: Execute callback. 1994 */ 1995 usb_transfer_complete(xfer); 1996 1997 splx(s); 1998 } 1999 2000 void 2001 ehci_timeout(void *addr) 2002 { 2003 struct ehci_xfer *exfer = addr; 2004 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 2005 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus; 2006 2007 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 2008 2009 if (sc->sc_dying) { 2010 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 2011 return; 2012 } 2013 2014 /* Execute the abort in a process context. */ 2015 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 2016 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task); 2017 } 2018 2019 void 2020 ehci_timeout_task(void *addr) 2021 { 2022 usbd_xfer_handle xfer = addr; 2023 int s; 2024 2025 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 2026 2027 s = splusb(); 2028 ehci_abort_xfer(xfer, USBD_TIMEOUT); 2029 splx(s); 2030 } 2031 2032 /************************/ 2033 2034 Static usbd_status 2035 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 2036 { 2037 usbd_status err; 2038 2039 /* Insert last in queue. */ 2040 err = usb_insert_transfer(xfer); 2041 if (err) 2042 return (err); 2043 2044 /* Pipe isn't running, start first */ 2045 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2046 } 2047 2048 Static usbd_status 2049 ehci_device_ctrl_start(usbd_xfer_handle xfer) 2050 { 2051 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus; 2052 usbd_status err; 2053 2054 if (sc->sc_dying) 2055 return (USBD_IOERROR); 2056 2057 #ifdef DIAGNOSTIC 2058 if (!(xfer->rqflags & URQ_REQUEST)) { 2059 /* XXX panic */ 2060 printf("ehci_device_ctrl_transfer: not a request\n"); 2061 return (USBD_INVAL); 2062 } 2063 #endif 2064 2065 err = ehci_device_request(xfer); 2066 if (err) 2067 return (err); 2068 2069 if (sc->sc_bus.use_polling) 2070 ehci_waitintr(sc, xfer); 2071 return (USBD_IN_PROGRESS); 2072 } 2073 2074 void 2075 ehci_device_ctrl_done(usbd_xfer_handle xfer) 2076 { 2077 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 2078 2079 #ifdef DIAGNOSTIC 2080 if (!(xfer->rqflags & URQ_REQUEST)) { 2081 panic("ehci_ctrl_done: not a request\n"); 2082 } 2083 #endif 2084 xfer->hcpriv = NULL; 2085 } 2086 2087 /* Abort a device control request. */ 2088 Static void 2089 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 2090 { 2091 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 2092 ehci_abort_xfer(xfer, USBD_CANCELLED); 2093 } 2094 2095 /* Close a device control pipe. */ 2096 Static void 2097 ehci_device_ctrl_close(usbd_pipe_handle pipe) 2098 { 2099 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus; 2100 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 2101 2102 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 2103 ehci_close_pipe(pipe, sc->sc_async_head); 2104 /*ehci_free_std(sc, epipe->tail.td);*/ 2105 } 2106 2107 usbd_status 2108 ehci_device_request(usbd_xfer_handle xfer) 2109 { 2110 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2111 usb_device_request_t *req = &xfer->request; 2112 usbd_device_handle dev = epipe->pipe.device; 2113 ehci_softc_t *sc = (ehci_softc_t *)dev->bus; 2114 int addr = dev->address; 2115 ehci_soft_qtd_t *setup, *stat, *next; 2116 ehci_soft_qh_t *sqh; 2117 int isread; 2118 int len; 2119 usbd_status err; 2120 int s; 2121 2122 isread = req->bmRequestType & UT_READ; 2123 len = UGETW(req->wLength); 2124 2125 DPRINTFN(3,("ehci_device_control type=0x%02x, request=0x%02x, " 2126 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 2127 req->bmRequestType, req->bRequest, UGETW(req->wValue), 2128 UGETW(req->wIndex), len, addr, 2129 epipe->pipe.endpoint->edesc->bEndpointAddress)); 2130 2131 setup = ehci_alloc_sqtd(sc); 2132 if (setup == NULL) { 2133 err = USBD_NOMEM; 2134 goto bad1; 2135 } 2136 stat = ehci_alloc_sqtd(sc); 2137 if (stat == NULL) { 2138 err = USBD_NOMEM; 2139 goto bad2; 2140 } 2141 2142 sqh = epipe->sqh; 2143 epipe->u.ctl.length = len; 2144 2145 /* XXX 2146 * Since we're messing with the QH we must know the HC is in sync. 2147 * This needs to go away since it slows down control transfers. 2148 * Removing it entails: 2149 * - fill the QH only once with addr & wMaxPacketSize 2150 * - put the correct data toggles in the qtds and set DTC 2151 */ 2152 /* ehci_sync_hc(sc); */ 2153 /* Update device address and length since they may have changed. */ 2154 /* XXX This only needs to be done once, but it's too early in open. */ 2155 /* XXXX Should not touch ED here! */ 2156 sqh->qh.qh_endp = 2157 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QG_MPLMASK))) | 2158 htole32( 2159 EHCI_QH_SET_ADDR(addr) | 2160 /* EHCI_QH_DTC | */ 2161 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 2162 ); 2163 /* Clear toggle */ 2164 sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE); 2165 2166 /* Set up data transaction */ 2167 if (len != 0) { 2168 ehci_soft_qtd_t *end; 2169 2170 err = ehci_alloc_std_chain(epipe, sc, len, isread, xfer, 2171 &next, &end); 2172 if (err) 2173 goto bad3; 2174 end->nextqtd = stat; 2175 end->qtd.qtd_next = 2176 end->qtd.qtd_altnext = htole32(stat->physaddr); 2177 /* Start toggle at 1. */ 2178 /*next->qtd.td_flags |= htole32(EHCI_QTD_TOGGLE);*/ 2179 } else { 2180 next = stat; 2181 } 2182 2183 memcpy(KERNADDR(&epipe->u.ctl.reqdma), req, sizeof *req); 2184 2185 setup->qtd.qtd_status = htole32( 2186 EHCI_QTD_SET_STATUS(EHCI_QTD_ACTIVE) | 2187 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 2188 EHCI_QTD_SET_CERR(3) | 2189 EHCI_QTD_SET_BYTES(sizeof *req) 2190 ); 2191 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma)); 2192 setup->nextqtd = next; 2193 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 2194 setup->xfer = xfer; 2195 2196 stat->qtd.qtd_status = htole32( 2197 EHCI_QTD_SET_STATUS(EHCI_QTD_ACTIVE) | 2198 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 2199 EHCI_QTD_SET_CERR(3) | 2200 EHCI_QTD_IOC 2201 ); 2202 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 2203 stat->nextqtd = NULL; 2204 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 2205 stat->xfer = xfer; 2206 2207 #ifdef EHCI_DEBUG 2208 if (ehcidebug > 2) { 2209 DPRINTF(("ehci_device_request:\n")); 2210 ehci_dump_sqh(sqh); 2211 ehci_dump_sqtds(setup); 2212 } 2213 #endif 2214 2215 /* Insert qTD in QH list. */ 2216 s = splusb(); 2217 sqh->qh.qh_curqtd = 0; 2218 sqh->qh.qh_qtd.qtd_next = htole32(setup->physaddr); 2219 sqh->sqtd = setup; 2220 if (xfer->timeout && !sc->sc_bus.use_polling) { 2221 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout), 2222 ehci_timeout, xfer); 2223 } 2224 splx(s); 2225 2226 #ifdef EHCI_DEBUG 2227 if (ehcidebug > 10) { 2228 delay(10000); 2229 DPRINTF(("ehci_device_request: status=%x\n", 2230 EOREAD4(sc, EHCI_USBSTS))); 2231 ehci_dumpregs(sc); 2232 ehci_dump_sqh(sc->sc_async_head); 2233 ehci_dump_sqh(sqh); 2234 ehci_dump_sqtds(setup); 2235 } 2236 #endif 2237 2238 return (USBD_NORMAL_COMPLETION); 2239 2240 bad3: 2241 ehci_free_sqtd(sc, stat); 2242 bad2: 2243 ehci_free_sqtd(sc, setup); 2244 bad1: 2245 return (err); 2246 } 2247 2248 /************************/ 2249 2250 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle xfer) { return USBD_IOERROR; } 2251 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle xfer) { return USBD_IOERROR; } 2252 Static void ehci_device_bulk_abort(usbd_xfer_handle xfer) { } 2253 Static void ehci_device_bulk_close(usbd_pipe_handle pipe) { } 2254 Static void ehci_device_bulk_done(usbd_xfer_handle xfer) { } 2255 2256 /************************/ 2257 2258 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle xfer) { return USBD_IOERROR; } 2259 Static usbd_status ehci_device_intr_start(usbd_xfer_handle xfer) { return USBD_IOERROR; } 2260 Static void ehci_device_intr_abort(usbd_xfer_handle xfer) { } 2261 Static void ehci_device_intr_close(usbd_pipe_handle pipe) { } 2262 Static void ehci_device_intr_done(usbd_xfer_handle xfer) { } 2263 2264 /************************/ 2265 2266 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle xfer) { return USBD_IOERROR; } 2267 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle xfer) { return USBD_IOERROR; } 2268 Static void ehci_device_isoc_abort(usbd_xfer_handle xfer) { } 2269 Static void ehci_device_isoc_close(usbd_pipe_handle pipe) { } 2270 Static void ehci_device_isoc_done(usbd_xfer_handle xfer) { } 2271
Indexes created Mon Sep 22 10:09:38 GMT 2025