ehci.c revision 1.171
1 /* $NetBSD: ehci.c,v 1.171 2010/11/03 22:34:23 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum and 9 * Jeremy Morse (jeremy.morse (at) gmail.com). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 35 * 36 * The EHCI 1.0 spec can be found at 37 * http://www.intel.com/technology/usb/spec.htm 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/ 40 * 41 */ 42 43 /* 44 * TODO: 45 * 1) hold off explorations by companion controllers until ehci has started. 46 * 47 * 2) The hub driver needs to handle and schedule the transaction translator, 48 * to assign place in frame where different devices get to go. See chapter 49 * on hubs in USB 2.0 for details. 50 * 51 * 3) Command failures are not recovered correctly. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.171 2010/11/03 22:34:23 dyoung Exp $"); 56 57 #include "ohci.h" 58 #include "uhci.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/kernel.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/select.h> 66 #include <sys/proc.h> 67 #include <sys/queue.h> 68 #include <sys/mutex.h> 69 #include <sys/bus.h> 70 71 #include <machine/endian.h> 72 73 #include <dev/usb/usb.h> 74 #include <dev/usb/usbdi.h> 75 #include <dev/usb/usbdivar.h> 76 #include <dev/usb/usb_mem.h> 77 #include <dev/usb/usb_quirks.h> 78 79 #include <dev/usb/ehcireg.h> 80 #include <dev/usb/ehcivar.h> 81 #include <dev/usb/usbroothub_subr.h> 82 83 #ifdef EHCI_DEBUG 84 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 85 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 86 int ehcidebug = 0; 87 #else 88 #define DPRINTF(x) 89 #define DPRINTFN(n,x) 90 #endif 91 92 struct ehci_pipe { 93 struct usbd_pipe pipe; 94 int nexttoggle; 95 96 ehci_soft_qh_t *sqh; 97 union { 98 ehci_soft_qtd_t *qtd; 99 /* ehci_soft_itd_t *itd; */ 100 } tail; 101 union { 102 /* Control pipe */ 103 struct { 104 usb_dma_t reqdma; 105 u_int length; 106 } ctl; 107 /* Interrupt pipe */ 108 struct { 109 u_int length; 110 } intr; 111 /* Bulk pipe */ 112 struct { 113 u_int length; 114 } bulk; 115 /* Iso pipe */ 116 struct { 117 u_int next_frame; 118 u_int cur_xfers; 119 } isoc; 120 } u; 121 }; 122 123 Static usbd_status ehci_open(usbd_pipe_handle); 124 Static void ehci_poll(struct usbd_bus *); 125 Static void ehci_softintr(void *); 126 Static int ehci_intr1(ehci_softc_t *); 127 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 128 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 129 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 130 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 131 Static void ehci_idone(struct ehci_xfer *); 132 Static void ehci_timeout(void *); 133 Static void ehci_timeout_task(void *); 134 Static void ehci_intrlist_timeout(void *); 135 136 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 137 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 138 139 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 140 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 141 142 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 143 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 144 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 145 Static void ehci_root_ctrl_close(usbd_pipe_handle); 146 Static void ehci_root_ctrl_done(usbd_xfer_handle); 147 148 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 149 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 150 Static void ehci_root_intr_abort(usbd_xfer_handle); 151 Static void ehci_root_intr_close(usbd_pipe_handle); 152 Static void ehci_root_intr_done(usbd_xfer_handle); 153 154 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 155 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 156 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 157 Static void ehci_device_ctrl_close(usbd_pipe_handle); 158 Static void ehci_device_ctrl_done(usbd_xfer_handle); 159 160 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 161 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 162 Static void ehci_device_bulk_abort(usbd_xfer_handle); 163 Static void ehci_device_bulk_close(usbd_pipe_handle); 164 Static void ehci_device_bulk_done(usbd_xfer_handle); 165 166 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 167 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 168 Static void ehci_device_intr_abort(usbd_xfer_handle); 169 Static void ehci_device_intr_close(usbd_pipe_handle); 170 Static void ehci_device_intr_done(usbd_xfer_handle); 171 172 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 173 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 174 Static void ehci_device_isoc_abort(usbd_xfer_handle); 175 Static void ehci_device_isoc_close(usbd_pipe_handle); 176 Static void ehci_device_isoc_done(usbd_xfer_handle); 177 178 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 179 Static void ehci_noop(usbd_pipe_handle pipe); 180 181 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 182 Static void ehci_disown(ehci_softc_t *, int, int); 183 184 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 185 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 186 187 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 188 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 189 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 190 ehci_softc_t *, int, int, usbd_xfer_handle, 191 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 192 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 193 ehci_soft_qtd_t *); 194 195 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 196 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 197 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 198 struct ehci_xfer *exfer); 199 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 200 usbd_status status); 201 202 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 203 204 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 205 int ival); 206 207 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 208 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 209 ehci_soft_qh_t *); 210 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 211 Static void ehci_sync_hc(ehci_softc_t *); 212 213 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 214 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 215 216 #ifdef EHCI_DEBUG 217 Static void ehci_dump_regs(ehci_softc_t *); 218 void ehci_dump(void); 219 Static ehci_softc_t *theehci; 220 Static void ehci_dump_link(ehci_link_t, int); 221 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 222 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 223 Static void ehci_dump_qtd(ehci_qtd_t *); 224 Static void ehci_dump_sqh(ehci_soft_qh_t *); 225 #if notyet 226 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 227 Static void ehci_dump_itd(struct ehci_soft_itd *); 228 #endif 229 #ifdef DIAGNOSTIC 230 Static void ehci_dump_exfer(struct ehci_xfer *); 231 #endif 232 #endif 233 234 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 235 236 #define EHCI_INTR_ENDPT 1 237 238 #define ehci_add_intr_list(sc, ex) \ 239 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 240 #define ehci_del_intr_list(sc, ex) \ 241 do { \ 242 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 243 (ex)->inext.tqe_prev = NULL; \ 244 } while (0) 245 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 246 247 Static const struct usbd_bus_methods ehci_bus_methods = { 248 ehci_open, 249 ehci_softintr, 250 ehci_poll, 251 ehci_allocm, 252 ehci_freem, 253 ehci_allocx, 254 ehci_freex, 255 }; 256 257 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 258 ehci_root_ctrl_transfer, 259 ehci_root_ctrl_start, 260 ehci_root_ctrl_abort, 261 ehci_root_ctrl_close, 262 ehci_noop, 263 ehci_root_ctrl_done, 264 }; 265 266 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 267 ehci_root_intr_transfer, 268 ehci_root_intr_start, 269 ehci_root_intr_abort, 270 ehci_root_intr_close, 271 ehci_noop, 272 ehci_root_intr_done, 273 }; 274 275 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 276 ehci_device_ctrl_transfer, 277 ehci_device_ctrl_start, 278 ehci_device_ctrl_abort, 279 ehci_device_ctrl_close, 280 ehci_noop, 281 ehci_device_ctrl_done, 282 }; 283 284 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 285 ehci_device_intr_transfer, 286 ehci_device_intr_start, 287 ehci_device_intr_abort, 288 ehci_device_intr_close, 289 ehci_device_clear_toggle, 290 ehci_device_intr_done, 291 }; 292 293 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 294 ehci_device_bulk_transfer, 295 ehci_device_bulk_start, 296 ehci_device_bulk_abort, 297 ehci_device_bulk_close, 298 ehci_device_clear_toggle, 299 ehci_device_bulk_done, 300 }; 301 302 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 303 ehci_device_isoc_transfer, 304 ehci_device_isoc_start, 305 ehci_device_isoc_abort, 306 ehci_device_isoc_close, 307 ehci_noop, 308 ehci_device_isoc_done, 309 }; 310 311 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 312 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 313 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 314 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 315 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 316 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 317 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 318 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 319 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 320 }; 321 322 usbd_status 323 ehci_init(ehci_softc_t *sc) 324 { 325 u_int32_t vers, sparams, cparams, hcr; 326 u_int i; 327 usbd_status err; 328 ehci_soft_qh_t *sqh; 329 u_int ncomp; 330 331 DPRINTF(("ehci_init: start\n")); 332 #ifdef EHCI_DEBUG 333 theehci = sc; 334 #endif 335 336 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 337 338 vers = EREAD2(sc, EHCI_HCIVERSION); 339 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 340 vers >> 8, vers & 0xff); 341 342 sparams = EREAD4(sc, EHCI_HCSPARAMS); 343 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 344 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 345 ncomp = EHCI_HCS_N_CC(sparams); 346 if (ncomp != sc->sc_ncomp) { 347 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 348 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 349 #if NOHCI == 0 || NUHCI == 0 350 aprint_error("%s: ohci or uhci probably not configured\n", 351 device_xname(sc->sc_dev)); 352 #endif 353 if (ncomp < sc->sc_ncomp) 354 sc->sc_ncomp = ncomp; 355 } 356 if (sc->sc_ncomp > 0) { 357 aprint_normal("%s: companion controller%s, %d port%s each:", 358 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 359 EHCI_HCS_N_PCC(sparams), 360 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 361 for (i = 0; i < sc->sc_ncomp; i++) 362 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 363 aprint_normal("\n"); 364 } 365 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 366 cparams = EREAD4(sc, EHCI_HCCPARAMS); 367 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 368 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 369 370 if (EHCI_HCC_64BIT(cparams)) { 371 /* MUST clear segment register if 64 bit capable. */ 372 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 373 } 374 375 sc->sc_bus.usbrev = USBREV_2_0; 376 377 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 378 USB_MEM_RESERVE); 379 380 /* Reset the controller */ 381 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 382 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 383 usb_delay_ms(&sc->sc_bus, 1); 384 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 385 for (i = 0; i < 100; i++) { 386 usb_delay_ms(&sc->sc_bus, 1); 387 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 388 if (!hcr) 389 break; 390 } 391 if (hcr) { 392 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 393 return (USBD_IOERROR); 394 } 395 if (sc->sc_vendor_init) 396 sc->sc_vendor_init(sc); 397 398 /* XXX need proper intr scheduling */ 399 sc->sc_rand = 96; 400 401 /* frame list size at default, read back what we got and use that */ 402 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 403 case 0: sc->sc_flsize = 1024; break; 404 case 1: sc->sc_flsize = 512; break; 405 case 2: sc->sc_flsize = 256; break; 406 case 3: return (USBD_IOERROR); 407 } 408 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 409 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 410 if (err) 411 return (err); 412 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 413 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 414 415 for (i = 0; i < sc->sc_flsize; i++) { 416 sc->sc_flist[i] = EHCI_NULL; 417 } 418 419 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 420 421 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 422 M_USB, M_NOWAIT | M_ZERO); 423 if (sc->sc_softitds == NULL) 424 return ENOMEM; 425 LIST_INIT(&sc->sc_freeitds); 426 TAILQ_INIT(&sc->sc_intrhead); 427 mutex_init(&sc->sc_intrhead_lock, MUTEX_DEFAULT, IPL_USB); 428 429 /* Set up the bus struct. */ 430 sc->sc_bus.methods = &ehci_bus_methods; 431 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 432 433 sc->sc_eintrs = EHCI_NORMAL_INTRS; 434 435 /* 436 * Allocate the interrupt dummy QHs. These are arranged to give poll 437 * intervals that are powers of 2 times 1ms. 438 */ 439 for (i = 0; i < EHCI_INTRQHS; i++) { 440 sqh = ehci_alloc_sqh(sc); 441 if (sqh == NULL) { 442 err = USBD_NOMEM; 443 goto bad1; 444 } 445 sc->sc_islots[i].sqh = sqh; 446 } 447 for (i = 0; i < EHCI_INTRQHS; i++) { 448 sqh = sc->sc_islots[i].sqh; 449 if (i == 0) { 450 /* The last (1ms) QH terminates. */ 451 sqh->qh.qh_link = EHCI_NULL; 452 sqh->next = NULL; 453 } else { 454 /* Otherwise the next QH has half the poll interval */ 455 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 456 sqh->qh.qh_link = htole32(sqh->next->physaddr | 457 EHCI_LINK_QH); 458 } 459 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 460 sqh->qh.qh_curqtd = EHCI_NULL; 461 sqh->next = NULL; 462 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 463 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 464 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 465 sqh->sqtd = NULL; 466 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 467 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 468 } 469 /* Point the frame list at the last level (128ms). */ 470 for (i = 0; i < sc->sc_flsize; i++) { 471 int j; 472 473 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 474 revbits[i & (EHCI_MAX_POLLRATE-1)]; 475 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 476 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 477 i)].sqh->physaddr); 478 } 479 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 480 BUS_DMASYNC_PREWRITE); 481 482 /* Allocate dummy QH that starts the async list. */ 483 sqh = ehci_alloc_sqh(sc); 484 if (sqh == NULL) { 485 err = USBD_NOMEM; 486 goto bad1; 487 } 488 /* Fill the QH */ 489 sqh->qh.qh_endp = 490 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 491 sqh->qh.qh_link = 492 htole32(sqh->physaddr | EHCI_LINK_QH); 493 sqh->qh.qh_curqtd = EHCI_NULL; 494 sqh->next = NULL; 495 /* Fill the overlay qTD */ 496 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 497 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 498 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 499 sqh->sqtd = NULL; 500 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 501 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 502 #ifdef EHCI_DEBUG 503 if (ehcidebug) { 504 ehci_dump_sqh(sqh); 505 } 506 #endif 507 508 /* Point to async list */ 509 sc->sc_async_head = sqh; 510 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 511 512 callout_init(&(sc->sc_tmo_intrlist), 0); 513 514 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE); 515 516 /* Turn on controller */ 517 EOWRITE4(sc, EHCI_USBCMD, 518 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 519 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 520 EHCI_CMD_ASE | 521 EHCI_CMD_PSE | 522 EHCI_CMD_RS); 523 524 /* Take over port ownership */ 525 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 526 527 for (i = 0; i < 100; i++) { 528 usb_delay_ms(&sc->sc_bus, 1); 529 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 530 if (!hcr) 531 break; 532 } 533 if (hcr) { 534 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 535 return (USBD_IOERROR); 536 } 537 538 /* Enable interrupts */ 539 DPRINTFN(1,("ehci_init: enabling\n")); 540 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 541 542 return (USBD_NORMAL_COMPLETION); 543 544 #if 0 545 bad2: 546 ehci_free_sqh(sc, sc->sc_async_head); 547 #endif 548 bad1: 549 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 550 return (err); 551 } 552 553 int 554 ehci_intr(void *v) 555 { 556 ehci_softc_t *sc = v; 557 558 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 559 return (0); 560 561 /* If we get an interrupt while polling, then just ignore it. */ 562 if (sc->sc_bus.use_polling) { 563 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 564 565 if (intrs) 566 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 567 #ifdef DIAGNOSTIC 568 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 569 #endif 570 return (0); 571 } 572 573 return (ehci_intr1(sc)); 574 } 575 576 Static int 577 ehci_intr1(ehci_softc_t *sc) 578 { 579 u_int32_t intrs, eintrs; 580 581 DPRINTFN(20,("ehci_intr1: enter\n")); 582 583 /* In case the interrupt occurs before initialization has completed. */ 584 if (sc == NULL) { 585 #ifdef DIAGNOSTIC 586 printf("ehci_intr1: sc == NULL\n"); 587 #endif 588 return (0); 589 } 590 591 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 592 if (!intrs) 593 return (0); 594 595 eintrs = intrs & sc->sc_eintrs; 596 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 597 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 598 (u_int)eintrs)); 599 if (!eintrs) 600 return (0); 601 602 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 603 sc->sc_bus.intr_context++; 604 sc->sc_bus.no_intrs++; 605 if (eintrs & EHCI_STS_IAA) { 606 DPRINTF(("ehci_intr1: door bell\n")); 607 wakeup(&sc->sc_async_head); 608 eintrs &= ~EHCI_STS_IAA; 609 } 610 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 611 DPRINTFN(5,("ehci_intr1: %s %s\n", 612 eintrs & EHCI_STS_INT ? "INT" : "", 613 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 614 usb_schedsoftintr(&sc->sc_bus); 615 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 616 } 617 if (eintrs & EHCI_STS_HSE) { 618 printf("%s: unrecoverable error, controller halted\n", 619 device_xname(sc->sc_dev)); 620 /* XXX what else */ 621 } 622 if (eintrs & EHCI_STS_PCD) { 623 ehci_pcd(sc, sc->sc_intrxfer); 624 eintrs &= ~EHCI_STS_PCD; 625 } 626 627 sc->sc_bus.intr_context--; 628 629 if (eintrs != 0) { 630 /* Block unprocessed interrupts. */ 631 sc->sc_eintrs &= ~eintrs; 632 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 633 printf("%s: blocking intrs 0x%x\n", 634 device_xname(sc->sc_dev), eintrs); 635 } 636 637 return (1); 638 } 639 640 641 Static void 642 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 643 { 644 usbd_pipe_handle pipe; 645 u_char *p; 646 int i, m; 647 648 if (xfer == NULL) { 649 /* Just ignore the change. */ 650 return; 651 } 652 653 pipe = xfer->pipe; 654 655 p = KERNADDR(&xfer->dmabuf, 0); 656 m = min(sc->sc_noport, xfer->length * 8 - 1); 657 memset(p, 0, xfer->length); 658 for (i = 1; i <= m; i++) { 659 /* Pick out CHANGE bits from the status reg. */ 660 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 661 p[i/8] |= 1 << (i%8); 662 } 663 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 664 xfer->actlen = xfer->length; 665 xfer->status = USBD_NORMAL_COMPLETION; 666 667 usb_transfer_complete(xfer); 668 } 669 670 Static void 671 ehci_softintr(void *v) 672 { 673 struct usbd_bus *bus = v; 674 ehci_softc_t *sc = bus->hci_private; 675 struct ehci_xfer *ex, *nextex; 676 677 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 678 sc->sc_bus.intr_context)); 679 680 sc->sc_bus.intr_context++; 681 682 /* 683 * The only explanation I can think of for why EHCI is as brain dead 684 * as UHCI interrupt-wise is that Intel was involved in both. 685 * An interrupt just tells us that something is done, we have no 686 * clue what, so we need to scan through all active transfers. :-( 687 */ 688 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 689 nextex = TAILQ_NEXT(ex, inext); 690 ehci_check_intr(sc, ex); 691 } 692 693 /* Schedule a callout to catch any dropped transactions. */ 694 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 695 !TAILQ_EMPTY(&sc->sc_intrhead)) 696 callout_reset(&(sc->sc_tmo_intrlist), 697 (hz), (ehci_intrlist_timeout), (sc)); 698 699 #ifdef USB_USE_SOFTINTR 700 if (sc->sc_softwake) { 701 sc->sc_softwake = 0; 702 wakeup(&sc->sc_softwake); 703 } 704 #endif /* USB_USE_SOFTINTR */ 705 706 sc->sc_bus.intr_context--; 707 } 708 709 /* Check for an interrupt. */ 710 Static void 711 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 712 { 713 int attr; 714 715 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 716 717 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 718 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 719 ehci_check_itd_intr(sc, ex); 720 else 721 ehci_check_qh_intr(sc, ex); 722 723 return; 724 } 725 726 Static void 727 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 728 { 729 ehci_soft_qtd_t *sqtd, *lsqtd; 730 __uint32_t status; 731 732 if (ex->sqtdstart == NULL) { 733 printf("ehci_check_qh_intr: not valid sqtd\n"); 734 return; 735 } 736 737 lsqtd = ex->sqtdend; 738 #ifdef DIAGNOSTIC 739 if (lsqtd == NULL) { 740 printf("ehci_check_qh_intr: lsqtd==0\n"); 741 return; 742 } 743 #endif 744 /* 745 * If the last TD is still active we need to check whether there 746 * is a an error somewhere in the middle, or whether there was a 747 * short packet (SPD and not ACTIVE). 748 */ 749 usb_syncmem(&lsqtd->dma, 750 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 751 sizeof(lsqtd->qtd.qtd_status), 752 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 753 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 754 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 755 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 756 usb_syncmem(&sqtd->dma, 757 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 758 sizeof(sqtd->qtd.qtd_status), 759 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 760 status = le32toh(sqtd->qtd.qtd_status); 761 usb_syncmem(&sqtd->dma, 762 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 763 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 764 /* If there's an active QTD the xfer isn't done. */ 765 if (status & EHCI_QTD_ACTIVE) 766 break; 767 /* Any kind of error makes the xfer done. */ 768 if (status & EHCI_QTD_HALTED) 769 goto done; 770 /* We want short packets, and it is short: it's done */ 771 if (EHCI_QTD_GET_BYTES(status) != 0) 772 goto done; 773 } 774 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 775 ex, ex->sqtdstart)); 776 usb_syncmem(&lsqtd->dma, 777 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 778 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 779 return; 780 } 781 done: 782 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 783 callout_stop(&ex->xfer.timeout_handle); 784 ehci_idone(ex); 785 } 786 787 Static void 788 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 789 ehci_soft_itd_t *itd; 790 int i; 791 792 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 793 return; 794 795 if (ex->itdstart == NULL) { 796 printf("ehci_check_itd_intr: not valid itd\n"); 797 return; 798 } 799 800 itd = ex->itdend; 801 #ifdef DIAGNOSTIC 802 if (itd == NULL) { 803 printf("ehci_check_itd_intr: itdend == 0\n"); 804 return; 805 } 806 #endif 807 808 /* 809 * check no active transfers in last itd, meaning we're finished 810 */ 811 812 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 813 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 814 BUS_DMASYNC_POSTREAD); 815 816 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 817 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 818 break; 819 } 820 821 if (i == EHCI_ITD_NUFRAMES) { 822 goto done; /* All 8 descriptors inactive, it's done */ 823 } 824 825 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 826 ex->itdstart)); 827 return; 828 done: 829 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 830 callout_stop(&ex->xfer.timeout_handle); 831 ehci_idone(ex); 832 } 833 834 Static void 835 ehci_idone(struct ehci_xfer *ex) 836 { 837 usbd_xfer_handle xfer = &ex->xfer; 838 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 839 ehci_soft_qtd_t *sqtd, *lsqtd; 840 u_int32_t status = 0, nstatus = 0; 841 int actlen; 842 843 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 844 #ifdef DIAGNOSTIC 845 { 846 int s = splhigh(); 847 if (ex->isdone) { 848 splx(s); 849 #ifdef EHCI_DEBUG 850 printf("ehci_idone: ex is done!\n "); 851 ehci_dump_exfer(ex); 852 #else 853 printf("ehci_idone: ex=%p is done!\n", ex); 854 #endif 855 return; 856 } 857 ex->isdone = 1; 858 splx(s); 859 } 860 #endif 861 if (xfer->status == USBD_CANCELLED || 862 xfer->status == USBD_TIMEOUT) { 863 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 864 return; 865 } 866 867 #ifdef EHCI_DEBUG 868 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 869 if (ehcidebug > 10) 870 ehci_dump_sqtds(ex->sqtdstart); 871 #endif 872 873 /* The transfer is done, compute actual length and status. */ 874 875 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 876 == UE_ISOCHRONOUS) { 877 /* Isoc transfer */ 878 struct ehci_soft_itd *itd; 879 int i, nframes, len, uframes; 880 881 nframes = 0; 882 actlen = 0; 883 884 i = xfer->pipe->endpoint->edesc->bInterval; 885 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 886 887 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 888 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 889 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 890 BUS_DMASYNC_POSTREAD); 891 892 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 893 /* XXX - driver didn't fill in the frame full 894 * of uframes. This leads to scheduling 895 * inefficiencies, but working around 896 * this doubles complexity of tracking 897 * an xfer. 898 */ 899 if (nframes >= xfer->nframes) 900 break; 901 902 status = le32toh(itd->itd.itd_ctl[i]); 903 len = EHCI_ITD_GET_LEN(status); 904 if (EHCI_ITD_GET_STATUS(status) != 0) 905 len = 0; /*No valid data on error*/ 906 907 xfer->frlengths[nframes++] = len; 908 actlen += len; 909 } 910 911 if (nframes >= xfer->nframes) 912 break; 913 } 914 915 xfer->actlen = actlen; 916 xfer->status = USBD_NORMAL_COMPLETION; 917 goto end; 918 } 919 920 /* Continue processing xfers using queue heads */ 921 922 lsqtd = ex->sqtdend; 923 actlen = 0; 924 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 925 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 926 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 927 nstatus = le32toh(sqtd->qtd.qtd_status); 928 if (nstatus & EHCI_QTD_ACTIVE) 929 break; 930 931 status = nstatus; 932 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 933 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 934 } 935 936 937 /* 938 * If there are left over TDs we need to update the toggle. 939 * The default pipe doesn't need it since control transfers 940 * start the toggle at 0 every time. 941 * For a short transfer we need to update the toggle for the missing 942 * packets within the qTD. 943 */ 944 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 945 xfer->pipe->device->default_pipe != xfer->pipe) { 946 DPRINTFN(2, ("ehci_idone: need toggle update " 947 "status=%08x nstatus=%08x\n", status, nstatus)); 948 #if 0 949 ehci_dump_sqh(epipe->sqh); 950 ehci_dump_sqtds(ex->sqtdstart); 951 #endif 952 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 953 } 954 955 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 956 xfer->length, actlen, status)); 957 xfer->actlen = actlen; 958 if (status & EHCI_QTD_HALTED) { 959 #ifdef EHCI_DEBUG 960 char sbuf[128]; 961 962 snprintb(sbuf, sizeof(sbuf), 963 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 964 (u_int32_t)status); 965 966 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 967 "status 0x%s\n", 968 xfer->pipe->device->address, 969 xfer->pipe->endpoint->edesc->bEndpointAddress, 970 sbuf)); 971 if (ehcidebug > 2) { 972 ehci_dump_sqh(epipe->sqh); 973 ehci_dump_sqtds(ex->sqtdstart); 974 } 975 #endif 976 /* low&full speed has an extra error flag */ 977 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 978 EHCI_QH_SPEED_HIGH) 979 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 980 else 981 status &= EHCI_QTD_STATERRS; 982 if (status == 0) /* no other errors means a stall */ { 983 xfer->status = USBD_STALLED; 984 } else { 985 xfer->status = USBD_IOERROR; /* more info XXX */ 986 } 987 /* XXX need to reset TT on missed microframe */ 988 if (status & EHCI_QTD_MISSEDMICRO) { 989 ehci_softc_t *sc = 990 xfer->pipe->device->bus->hci_private; 991 992 printf("%s: missed microframe, TT reset not " 993 "implemented, hub might be inoperational\n", 994 device_xname(sc->sc_dev)); 995 } 996 } else { 997 xfer->status = USBD_NORMAL_COMPLETION; 998 } 999 1000 end: 1001 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1002 * during this call, before methods->done is called: dma sync required 1003 * beforehand? */ 1004 usb_transfer_complete(xfer); 1005 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1006 } 1007 1008 /* 1009 * Wait here until controller claims to have an interrupt. 1010 * Then call ehci_intr and return. Use timeout to avoid waiting 1011 * too long. 1012 */ 1013 Static void 1014 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1015 { 1016 int timo; 1017 u_int32_t intrs; 1018 1019 xfer->status = USBD_IN_PROGRESS; 1020 for (timo = xfer->timeout; timo >= 0; timo--) { 1021 usb_delay_ms(&sc->sc_bus, 1); 1022 if (sc->sc_dying) 1023 break; 1024 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1025 sc->sc_eintrs; 1026 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1027 #ifdef EHCI_DEBUG 1028 if (ehcidebug > 15) 1029 ehci_dump_regs(sc); 1030 #endif 1031 if (intrs) { 1032 ehci_intr1(sc); 1033 if (xfer->status != USBD_IN_PROGRESS) 1034 return; 1035 } 1036 } 1037 1038 /* Timeout */ 1039 DPRINTF(("ehci_waitintr: timeout\n")); 1040 xfer->status = USBD_TIMEOUT; 1041 usb_transfer_complete(xfer); 1042 /* XXX should free TD */ 1043 } 1044 1045 Static void 1046 ehci_poll(struct usbd_bus *bus) 1047 { 1048 ehci_softc_t *sc = bus->hci_private; 1049 #ifdef EHCI_DEBUG 1050 static int last; 1051 int new; 1052 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1053 if (new != last) { 1054 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1055 last = new; 1056 } 1057 #endif 1058 1059 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1060 ehci_intr1(sc); 1061 } 1062 1063 void 1064 ehci_childdet(device_t self, device_t child) 1065 { 1066 struct ehci_softc *sc = device_private(self); 1067 1068 KASSERT(sc->sc_child == child); 1069 sc->sc_child = NULL; 1070 } 1071 1072 int 1073 ehci_detach(struct ehci_softc *sc, int flags) 1074 { 1075 int rv = 0; 1076 1077 if (sc->sc_child != NULL) 1078 rv = config_detach(sc->sc_child, flags); 1079 1080 if (rv != 0) 1081 return (rv); 1082 1083 callout_stop(&sc->sc_tmo_intrlist); 1084 1085 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1086 1087 /* XXX free other data structures XXX */ 1088 mutex_destroy(&sc->sc_doorbell_lock); 1089 mutex_destroy(&sc->sc_intrhead_lock); 1090 1091 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1092 1093 return (rv); 1094 } 1095 1096 1097 int 1098 ehci_activate(device_t self, enum devact act) 1099 { 1100 struct ehci_softc *sc = device_private(self); 1101 1102 switch (act) { 1103 case DVACT_DEACTIVATE: 1104 sc->sc_dying = 1; 1105 return 0; 1106 default: 1107 return EOPNOTSUPP; 1108 } 1109 } 1110 1111 /* 1112 * Handle suspend/resume. 1113 * 1114 * We need to switch to polling mode here, because this routine is 1115 * called from an interrupt context. This is all right since we 1116 * are almost suspended anyway. 1117 * 1118 * Note that this power handler isn't to be registered directly; the 1119 * bus glue needs to call out to it. 1120 */ 1121 bool 1122 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1123 { 1124 ehci_softc_t *sc = device_private(dv); 1125 int i, s; 1126 uint32_t cmd, hcr; 1127 1128 s = splhardusb(); 1129 1130 sc->sc_bus.use_polling++; 1131 1132 for (i = 1; i <= sc->sc_noport; i++) { 1133 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1134 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1135 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1136 } 1137 1138 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1139 1140 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1141 EOWRITE4(sc, EHCI_USBCMD, cmd); 1142 1143 for (i = 0; i < 100; i++) { 1144 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1145 if (hcr == 0) 1146 break; 1147 1148 usb_delay_ms(&sc->sc_bus, 1); 1149 } 1150 if (hcr != 0) 1151 printf("%s: reset timeout\n", device_xname(dv)); 1152 1153 cmd &= ~EHCI_CMD_RS; 1154 EOWRITE4(sc, EHCI_USBCMD, cmd); 1155 1156 for (i = 0; i < 100; i++) { 1157 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1158 if (hcr == EHCI_STS_HCH) 1159 break; 1160 1161 usb_delay_ms(&sc->sc_bus, 1); 1162 } 1163 if (hcr != EHCI_STS_HCH) 1164 printf("%s: config timeout\n", device_xname(dv)); 1165 1166 sc->sc_bus.use_polling--; 1167 splx(s); 1168 1169 return true; 1170 } 1171 1172 bool 1173 ehci_resume(device_t dv, const pmf_qual_t *qual) 1174 { 1175 ehci_softc_t *sc = device_private(dv); 1176 int i; 1177 uint32_t cmd, hcr; 1178 1179 /* restore things in case the bios sucks */ 1180 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1181 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1182 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1183 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1184 1185 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1186 1187 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1188 1189 hcr = 0; 1190 for (i = 1; i <= sc->sc_noport; i++) { 1191 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1192 if ((cmd & EHCI_PS_PO) == 0 && 1193 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1194 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1195 hcr = 1; 1196 } 1197 } 1198 1199 if (hcr) { 1200 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1201 1202 for (i = 1; i <= sc->sc_noport; i++) { 1203 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1204 if ((cmd & EHCI_PS_PO) == 0 && 1205 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1206 EOWRITE4(sc, EHCI_PORTSC(i), 1207 cmd & ~EHCI_PS_FPR); 1208 } 1209 } 1210 1211 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1212 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1213 1214 for (i = 0; i < 100; i++) { 1215 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1216 if (hcr != EHCI_STS_HCH) 1217 break; 1218 1219 usb_delay_ms(&sc->sc_bus, 1); 1220 } 1221 if (hcr == EHCI_STS_HCH) 1222 printf("%s: config timeout\n", device_xname(dv)); 1223 1224 return true; 1225 } 1226 1227 /* 1228 * Shut down the controller when the system is going down. 1229 */ 1230 bool 1231 ehci_shutdown(device_t self, int flags) 1232 { 1233 ehci_softc_t *sc = device_private(self); 1234 1235 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1236 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1237 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1238 return true; 1239 } 1240 1241 Static usbd_status 1242 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1243 { 1244 struct ehci_softc *sc = bus->hci_private; 1245 usbd_status err; 1246 1247 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1248 if (err == USBD_NOMEM) 1249 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1250 #ifdef EHCI_DEBUG 1251 if (err) 1252 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1253 #endif 1254 return (err); 1255 } 1256 1257 Static void 1258 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1259 { 1260 struct ehci_softc *sc = bus->hci_private; 1261 1262 if (dma->block->flags & USB_DMA_RESERVE) { 1263 usb_reserve_freem(&sc->sc_dma_reserve, 1264 dma); 1265 return; 1266 } 1267 usb_freemem(&sc->sc_bus, dma); 1268 } 1269 1270 Static usbd_xfer_handle 1271 ehci_allocx(struct usbd_bus *bus) 1272 { 1273 struct ehci_softc *sc = bus->hci_private; 1274 usbd_xfer_handle xfer; 1275 1276 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1277 if (xfer != NULL) { 1278 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1279 #ifdef DIAGNOSTIC 1280 if (xfer->busy_free != XFER_FREE) { 1281 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1282 xfer->busy_free); 1283 } 1284 #endif 1285 } else { 1286 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1287 } 1288 if (xfer != NULL) { 1289 memset(xfer, 0, sizeof(struct ehci_xfer)); 1290 #ifdef DIAGNOSTIC 1291 EXFER(xfer)->isdone = 1; 1292 xfer->busy_free = XFER_BUSY; 1293 #endif 1294 } 1295 return (xfer); 1296 } 1297 1298 Static void 1299 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1300 { 1301 struct ehci_softc *sc = bus->hci_private; 1302 1303 #ifdef DIAGNOSTIC 1304 if (xfer->busy_free != XFER_BUSY) { 1305 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1306 xfer->busy_free); 1307 } 1308 xfer->busy_free = XFER_FREE; 1309 if (!EXFER(xfer)->isdone) { 1310 printf("ehci_freex: !isdone\n"); 1311 } 1312 #endif 1313 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1314 } 1315 1316 Static void 1317 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1318 { 1319 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1320 1321 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1322 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1323 #ifdef EHCI_DEBUG 1324 if (ehcidebug) 1325 usbd_dump_pipe(pipe); 1326 #endif 1327 epipe->nexttoggle = 0; 1328 } 1329 1330 Static void 1331 ehci_noop(usbd_pipe_handle pipe) 1332 { 1333 } 1334 1335 #ifdef EHCI_DEBUG 1336 Static void 1337 ehci_dump_regs(ehci_softc_t *sc) 1338 { 1339 int i; 1340 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1341 EOREAD4(sc, EHCI_USBCMD), 1342 EOREAD4(sc, EHCI_USBSTS), 1343 EOREAD4(sc, EHCI_USBINTR)); 1344 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1345 EOREAD4(sc, EHCI_FRINDEX), 1346 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1347 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1348 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1349 for (i = 1; i <= sc->sc_noport; i++) 1350 printf("port %d status=0x%08x\n", i, 1351 EOREAD4(sc, EHCI_PORTSC(i))); 1352 } 1353 1354 /* 1355 * Unused function - this is meant to be called from a kernel 1356 * debugger. 1357 */ 1358 void 1359 ehci_dump(void) 1360 { 1361 ehci_dump_regs(theehci); 1362 } 1363 1364 Static void 1365 ehci_dump_link(ehci_link_t link, int type) 1366 { 1367 link = le32toh(link); 1368 printf("0x%08x", link); 1369 if (link & EHCI_LINK_TERMINATE) 1370 printf("<T>"); 1371 else { 1372 printf("<"); 1373 if (type) { 1374 switch (EHCI_LINK_TYPE(link)) { 1375 case EHCI_LINK_ITD: printf("ITD"); break; 1376 case EHCI_LINK_QH: printf("QH"); break; 1377 case EHCI_LINK_SITD: printf("SITD"); break; 1378 case EHCI_LINK_FSTN: printf("FSTN"); break; 1379 } 1380 } 1381 printf(">"); 1382 } 1383 } 1384 1385 Static void 1386 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1387 { 1388 int i; 1389 u_int32_t stop; 1390 1391 stop = 0; 1392 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1393 ehci_dump_sqtd(sqtd); 1394 usb_syncmem(&sqtd->dma, 1395 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1396 sizeof(sqtd->qtd), 1397 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1398 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1399 usb_syncmem(&sqtd->dma, 1400 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1401 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1402 } 1403 if (sqtd) 1404 printf("dump aborted, too many TDs\n"); 1405 } 1406 1407 Static void 1408 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1409 { 1410 usb_syncmem(&sqtd->dma, sqtd->offs, 1411 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1412 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1413 ehci_dump_qtd(&sqtd->qtd); 1414 usb_syncmem(&sqtd->dma, sqtd->offs, 1415 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1416 } 1417 1418 Static void 1419 ehci_dump_qtd(ehci_qtd_t *qtd) 1420 { 1421 u_int32_t s; 1422 char sbuf[128]; 1423 1424 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1425 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1426 printf("\n"); 1427 s = le32toh(qtd->qtd_status); 1428 snprintb(sbuf, sizeof(sbuf), 1429 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1430 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1431 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1432 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1433 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1434 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1435 EHCI_QTD_GET_PID(s), sbuf); 1436 for (s = 0; s < 5; s++) 1437 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1438 } 1439 1440 Static void 1441 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1442 { 1443 ehci_qh_t *qh = &sqh->qh; 1444 u_int32_t endp, endphub; 1445 1446 usb_syncmem(&sqh->dma, sqh->offs, 1447 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1448 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1449 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1450 endp = le32toh(qh->qh_endp); 1451 printf(" endp=0x%08x\n", endp); 1452 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1453 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1454 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1455 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1456 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1457 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1458 EHCI_QH_GET_NRL(endp)); 1459 endphub = le32toh(qh->qh_endphub); 1460 printf(" endphub=0x%08x\n", endphub); 1461 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1462 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1463 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1464 EHCI_QH_GET_MULT(endphub)); 1465 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1466 printf("Overlay qTD:\n"); 1467 ehci_dump_qtd(&qh->qh_qtd); 1468 usb_syncmem(&sqh->dma, sqh->offs, 1469 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1470 } 1471 1472 #if notyet 1473 Static void 1474 ehci_dump_itd(struct ehci_soft_itd *itd) 1475 { 1476 ehci_isoc_trans_t t; 1477 ehci_isoc_bufr_ptr_t b, b2, b3; 1478 int i; 1479 1480 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1481 1482 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1483 t = le32toh(itd->itd.itd_ctl[i]); 1484 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1485 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1486 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1487 EHCI_ITD_GET_OFFS(t)); 1488 } 1489 printf("ITDbufr: "); 1490 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1491 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1492 1493 b = le32toh(itd->itd.itd_bufr[0]); 1494 b2 = le32toh(itd->itd.itd_bufr[1]); 1495 b3 = le32toh(itd->itd.itd_bufr[2]); 1496 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1497 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1498 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1499 } 1500 1501 Static void 1502 ehci_dump_sitd(struct ehci_soft_itd *itd) 1503 { 1504 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1505 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1506 itd->xfer_next, itd->physaddr, itd->slot); 1507 } 1508 #endif 1509 1510 #ifdef DIAGNOSTIC 1511 Static void 1512 ehci_dump_exfer(struct ehci_xfer *ex) 1513 { 1514 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1515 } 1516 #endif 1517 #endif 1518 1519 Static usbd_status 1520 ehci_open(usbd_pipe_handle pipe) 1521 { 1522 usbd_device_handle dev = pipe->device; 1523 ehci_softc_t *sc = dev->bus->hci_private; 1524 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1525 u_int8_t addr = dev->address; 1526 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1527 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1528 ehci_soft_qh_t *sqh; 1529 usbd_status err; 1530 int s; 1531 int ival, speed, naks; 1532 int hshubaddr, hshubport; 1533 1534 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1535 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1536 1537 if (dev->myhsport) { 1538 hshubaddr = dev->myhsport->parent->address; 1539 hshubport = dev->myhsport->portno; 1540 } else { 1541 hshubaddr = 0; 1542 hshubport = 0; 1543 } 1544 1545 if (sc->sc_dying) 1546 return (USBD_IOERROR); 1547 1548 epipe->nexttoggle = 0; 1549 1550 if (addr == sc->sc_addr) { 1551 switch (ed->bEndpointAddress) { 1552 case USB_CONTROL_ENDPOINT: 1553 pipe->methods = &ehci_root_ctrl_methods; 1554 break; 1555 case UE_DIR_IN | EHCI_INTR_ENDPT: 1556 pipe->methods = &ehci_root_intr_methods; 1557 break; 1558 default: 1559 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1560 ed->bEndpointAddress)); 1561 return (USBD_INVAL); 1562 } 1563 return (USBD_NORMAL_COMPLETION); 1564 } 1565 1566 /* XXX All this stuff is only valid for async. */ 1567 switch (dev->speed) { 1568 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1569 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1570 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1571 default: panic("ehci_open: bad device speed %d", dev->speed); 1572 } 1573 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1574 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1575 "isoc endpoint.\n"); 1576 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1577 "attached to a USB2 hub, and transaction translations are " 1578 "not yet supported.\n"); 1579 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1580 "root hub instead.\n"); 1581 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1582 hshubaddr, hshubport)); 1583 return USBD_INVAL; 1584 } 1585 1586 /* 1587 * For interrupt transfer, nak throttling must be disabled, but for 1588 * the other transfer type, nak throttling should be enabled from the 1589 * veiwpoint that avoids the memory thrashing. 1590 */ 1591 naks = (xfertype == UE_INTERRUPT) ? 0 1592 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1593 1594 /* Allocate sqh for everything, save isoc xfers */ 1595 if (xfertype != UE_ISOCHRONOUS) { 1596 sqh = ehci_alloc_sqh(sc); 1597 if (sqh == NULL) 1598 return (USBD_NOMEM); 1599 /* qh_link filled when the QH is added */ 1600 sqh->qh.qh_endp = htole32( 1601 EHCI_QH_SET_ADDR(addr) | 1602 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1603 EHCI_QH_SET_EPS(speed) | 1604 EHCI_QH_DTC | 1605 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1606 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1607 EHCI_QH_CTL : 0) | 1608 EHCI_QH_SET_NRL(naks) 1609 ); 1610 sqh->qh.qh_endphub = htole32( 1611 EHCI_QH_SET_MULT(1) | 1612 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1613 ); 1614 if (speed != EHCI_QH_SPEED_HIGH) 1615 sqh->qh.qh_endphub |= htole32( 1616 EHCI_QH_SET_PORT(hshubport) | 1617 EHCI_QH_SET_HUBA(hshubaddr) | 1618 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1619 ); 1620 sqh->qh.qh_curqtd = EHCI_NULL; 1621 /* Fill the overlay qTD */ 1622 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1623 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1624 sqh->qh.qh_qtd.qtd_status = htole32(0); 1625 1626 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1627 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1628 epipe->sqh = sqh; 1629 } else { 1630 sqh = NULL; 1631 } /*xfertype == UE_ISOC*/ 1632 1633 switch (xfertype) { 1634 case UE_CONTROL: 1635 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1636 0, &epipe->u.ctl.reqdma); 1637 #ifdef EHCI_DEBUG 1638 if (err) 1639 printf("ehci_open: usb_allocmem()=%d\n", err); 1640 #endif 1641 if (err) 1642 goto bad; 1643 pipe->methods = &ehci_device_ctrl_methods; 1644 s = splusb(); 1645 ehci_add_qh(sqh, sc->sc_async_head); 1646 splx(s); 1647 break; 1648 case UE_BULK: 1649 pipe->methods = &ehci_device_bulk_methods; 1650 s = splusb(); 1651 ehci_add_qh(sqh, sc->sc_async_head); 1652 splx(s); 1653 break; 1654 case UE_INTERRUPT: 1655 pipe->methods = &ehci_device_intr_methods; 1656 ival = pipe->interval; 1657 if (ival == USBD_DEFAULT_INTERVAL) { 1658 if (speed == EHCI_QH_SPEED_HIGH) { 1659 if (ed->bInterval > 16) { 1660 /* 1661 * illegal with high-speed, but there 1662 * were documentation bugs in the spec, 1663 * so be generous 1664 */ 1665 ival = 256; 1666 } else 1667 ival = (1 << (ed->bInterval - 1)) / 8; 1668 } else 1669 ival = ed->bInterval; 1670 } 1671 err = ehci_device_setintr(sc, sqh, ival); 1672 if (err) 1673 goto bad; 1674 break; 1675 case UE_ISOCHRONOUS: 1676 pipe->methods = &ehci_device_isoc_methods; 1677 if (ed->bInterval == 0 || ed->bInterval > 16) { 1678 printf("ehci: opening pipe with invalid bInterval\n"); 1679 err = USBD_INVAL; 1680 goto bad; 1681 } 1682 if (UGETW(ed->wMaxPacketSize) == 0) { 1683 printf("ehci: zero length endpoint open request\n"); 1684 err = USBD_INVAL; 1685 goto bad; 1686 } 1687 epipe->u.isoc.next_frame = 0; 1688 epipe->u.isoc.cur_xfers = 0; 1689 break; 1690 default: 1691 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1692 err = USBD_INVAL; 1693 goto bad; 1694 } 1695 return (USBD_NORMAL_COMPLETION); 1696 1697 bad: 1698 if (sqh != NULL) 1699 ehci_free_sqh(sc, sqh); 1700 return (err); 1701 } 1702 1703 /* 1704 * Add an ED to the schedule. Called at splusb(). 1705 */ 1706 Static void 1707 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1708 { 1709 SPLUSBCHECK; 1710 1711 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1712 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1713 sqh->next = head->next; 1714 sqh->qh.qh_link = head->qh.qh_link; 1715 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1716 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1717 head->next = sqh; 1718 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1719 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1720 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1721 1722 #ifdef EHCI_DEBUG 1723 if (ehcidebug > 5) { 1724 printf("ehci_add_qh:\n"); 1725 ehci_dump_sqh(sqh); 1726 } 1727 #endif 1728 } 1729 1730 /* 1731 * Remove an ED from the schedule. Called at splusb(). 1732 */ 1733 Static void 1734 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1735 { 1736 ehci_soft_qh_t *p; 1737 1738 SPLUSBCHECK; 1739 /* XXX */ 1740 for (p = head; p != NULL && p->next != sqh; p = p->next) 1741 ; 1742 if (p == NULL) 1743 panic("ehci_rem_qh: ED not found"); 1744 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1745 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1746 p->next = sqh->next; 1747 p->qh.qh_link = sqh->qh.qh_link; 1748 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1749 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1750 1751 ehci_sync_hc(sc); 1752 } 1753 1754 Static void 1755 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1756 { 1757 int i; 1758 u_int32_t status; 1759 1760 /* Save toggle bit and ping status. */ 1761 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1762 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1763 status = sqh->qh.qh_qtd.qtd_status & 1764 htole32(EHCI_QTD_TOGGLE_MASK | 1765 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1766 /* Set HALTED to make hw leave it alone. */ 1767 sqh->qh.qh_qtd.qtd_status = 1768 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1769 usb_syncmem(&sqh->dma, 1770 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1771 sizeof(sqh->qh.qh_qtd.qtd_status), 1772 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1773 sqh->qh.qh_curqtd = 0; 1774 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1775 sqh->qh.qh_qtd.qtd_altnext = 0; 1776 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1777 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1778 sqh->sqtd = sqtd; 1779 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1780 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1781 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1782 sqh->qh.qh_qtd.qtd_status = status; 1783 usb_syncmem(&sqh->dma, 1784 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1785 sizeof(sqh->qh.qh_qtd.qtd_status), 1786 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1787 } 1788 1789 /* 1790 * Ensure that the HC has released all references to the QH. We do this 1791 * by asking for a Async Advance Doorbell interrupt and then we wait for 1792 * the interrupt. 1793 * To make this easier we first obtain exclusive use of the doorbell. 1794 */ 1795 Static void 1796 ehci_sync_hc(ehci_softc_t *sc) 1797 { 1798 int s, error; 1799 1800 if (sc->sc_dying) { 1801 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1802 return; 1803 } 1804 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1805 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */ 1806 s = splhardusb(); 1807 /* ask for doorbell */ 1808 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1809 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1810 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1811 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1812 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1813 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1814 splx(s); 1815 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */ 1816 #ifdef DIAGNOSTIC 1817 if (error) 1818 printf("ehci_sync_hc: tsleep() = %d\n", error); 1819 #endif 1820 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1821 } 1822 1823 /*Call at splusb*/ 1824 Static void 1825 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1826 { 1827 struct ehci_soft_itd *itd, *prev; 1828 1829 prev = NULL; 1830 1831 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1832 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1833 1834 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1835 prev = itd->u.frame_list.prev; 1836 /* Unlink itd from hardware chain, or frame array */ 1837 if (prev == NULL) { /* We're at the table head */ 1838 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1839 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1840 usb_syncmem(&sc->sc_fldma, 1841 sizeof(ehci_link_t) * itd->slot, 1842 sizeof(ehci_link_t), 1843 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1844 1845 if (itd->u.frame_list.next != NULL) 1846 itd->u.frame_list.next->u.frame_list.prev = NULL; 1847 } else { 1848 /* XXX this part is untested... */ 1849 prev->itd.itd_next = itd->itd.itd_next; 1850 usb_syncmem(&itd->dma, 1851 itd->offs + offsetof(ehci_itd_t, itd_next), 1852 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1853 1854 prev->u.frame_list.next = itd->u.frame_list.next; 1855 if (itd->u.frame_list.next != NULL) 1856 itd->u.frame_list.next->u.frame_list.prev = prev; 1857 } 1858 } 1859 1860 prev = NULL; 1861 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1862 if (prev != NULL) 1863 ehci_free_itd(sc, prev); 1864 prev = itd; 1865 } 1866 if (prev) 1867 ehci_free_itd(sc, prev); 1868 exfer->itdstart = NULL; 1869 exfer->itdend = NULL; 1870 } 1871 1872 /***********/ 1873 1874 /* 1875 * Data structures and routines to emulate the root hub. 1876 */ 1877 Static usb_device_descriptor_t ehci_devd = { 1878 USB_DEVICE_DESCRIPTOR_SIZE, 1879 UDESC_DEVICE, /* type */ 1880 {0x00, 0x02}, /* USB version */ 1881 UDCLASS_HUB, /* class */ 1882 UDSUBCLASS_HUB, /* subclass */ 1883 UDPROTO_HSHUBSTT, /* protocol */ 1884 64, /* max packet */ 1885 {0},{0},{0x00,0x01}, /* device id */ 1886 1,2,0, /* string indicies */ 1887 1 /* # of configurations */ 1888 }; 1889 1890 Static const usb_device_qualifier_t ehci_odevd = { 1891 USB_DEVICE_DESCRIPTOR_SIZE, 1892 UDESC_DEVICE_QUALIFIER, /* type */ 1893 {0x00, 0x02}, /* USB version */ 1894 UDCLASS_HUB, /* class */ 1895 UDSUBCLASS_HUB, /* subclass */ 1896 UDPROTO_FSHUB, /* protocol */ 1897 64, /* max packet */ 1898 1, /* # of configurations */ 1899 0 1900 }; 1901 1902 Static const usb_config_descriptor_t ehci_confd = { 1903 USB_CONFIG_DESCRIPTOR_SIZE, 1904 UDESC_CONFIG, 1905 {USB_CONFIG_DESCRIPTOR_SIZE + 1906 USB_INTERFACE_DESCRIPTOR_SIZE + 1907 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1908 1, 1909 1, 1910 0, 1911 UC_ATTR_MBO | UC_SELF_POWERED, 1912 0 /* max power */ 1913 }; 1914 1915 Static const usb_interface_descriptor_t ehci_ifcd = { 1916 USB_INTERFACE_DESCRIPTOR_SIZE, 1917 UDESC_INTERFACE, 1918 0, 1919 0, 1920 1, 1921 UICLASS_HUB, 1922 UISUBCLASS_HUB, 1923 UIPROTO_HSHUBSTT, 1924 0 1925 }; 1926 1927 Static const usb_endpoint_descriptor_t ehci_endpd = { 1928 USB_ENDPOINT_DESCRIPTOR_SIZE, 1929 UDESC_ENDPOINT, 1930 UE_DIR_IN | EHCI_INTR_ENDPT, 1931 UE_INTERRUPT, 1932 {8, 0}, /* max packet */ 1933 12 1934 }; 1935 1936 Static const usb_hub_descriptor_t ehci_hubd = { 1937 USB_HUB_DESCRIPTOR_SIZE, 1938 UDESC_HUB, 1939 0, 1940 {0,0}, 1941 0, 1942 0, 1943 {""}, 1944 {""}, 1945 }; 1946 1947 /* 1948 * Simulate a hardware hub by handling all the necessary requests. 1949 */ 1950 Static usbd_status 1951 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1952 { 1953 usbd_status err; 1954 1955 /* Insert last in queue. */ 1956 err = usb_insert_transfer(xfer); 1957 if (err) 1958 return (err); 1959 1960 /* Pipe isn't running, start first */ 1961 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1962 } 1963 1964 Static usbd_status 1965 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1966 { 1967 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1968 usb_device_request_t *req; 1969 void *buf = NULL; 1970 int port, i; 1971 int s, len, value, index, l, totlen = 0; 1972 usb_port_status_t ps; 1973 usb_hub_descriptor_t hubd; 1974 usbd_status err; 1975 u_int32_t v; 1976 1977 if (sc->sc_dying) 1978 return (USBD_IOERROR); 1979 1980 #ifdef DIAGNOSTIC 1981 if (!(xfer->rqflags & URQ_REQUEST)) 1982 /* XXX panic */ 1983 return (USBD_INVAL); 1984 #endif 1985 req = &xfer->request; 1986 1987 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 1988 req->bmRequestType, req->bRequest)); 1989 1990 len = UGETW(req->wLength); 1991 value = UGETW(req->wValue); 1992 index = UGETW(req->wIndex); 1993 1994 if (len != 0) 1995 buf = KERNADDR(&xfer->dmabuf, 0); 1996 1997 #define C(x,y) ((x) | ((y) << 8)) 1998 switch(C(req->bRequest, req->bmRequestType)) { 1999 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2000 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2001 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2002 /* 2003 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2004 * for the integrated root hub. 2005 */ 2006 break; 2007 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2008 if (len > 0) { 2009 *(u_int8_t *)buf = sc->sc_conf; 2010 totlen = 1; 2011 } 2012 break; 2013 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2014 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2015 if (len == 0) 2016 break; 2017 switch(value >> 8) { 2018 case UDESC_DEVICE: 2019 if ((value & 0xff) != 0) { 2020 err = USBD_IOERROR; 2021 goto ret; 2022 } 2023 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2024 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2025 memcpy(buf, &ehci_devd, l); 2026 break; 2027 /* 2028 * We can't really operate at another speed, but the spec says 2029 * we need this descriptor. 2030 */ 2031 case UDESC_DEVICE_QUALIFIER: 2032 if ((value & 0xff) != 0) { 2033 err = USBD_IOERROR; 2034 goto ret; 2035 } 2036 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2037 memcpy(buf, &ehci_odevd, l); 2038 break; 2039 /* 2040 * We can't really operate at another speed, but the spec says 2041 * we need this descriptor. 2042 */ 2043 case UDESC_OTHER_SPEED_CONFIGURATION: 2044 case UDESC_CONFIG: 2045 if ((value & 0xff) != 0) { 2046 err = USBD_IOERROR; 2047 goto ret; 2048 } 2049 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2050 memcpy(buf, &ehci_confd, l); 2051 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2052 value >> 8; 2053 buf = (char *)buf + l; 2054 len -= l; 2055 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2056 totlen += l; 2057 memcpy(buf, &ehci_ifcd, l); 2058 buf = (char *)buf + l; 2059 len -= l; 2060 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2061 totlen += l; 2062 memcpy(buf, &ehci_endpd, l); 2063 break; 2064 case UDESC_STRING: 2065 #define sd ((usb_string_descriptor_t *)buf) 2066 switch (value & 0xff) { 2067 case 0: /* Language table */ 2068 totlen = usb_makelangtbl(sd, len); 2069 break; 2070 case 1: /* Vendor */ 2071 totlen = usb_makestrdesc(sd, len, 2072 sc->sc_vendor); 2073 break; 2074 case 2: /* Product */ 2075 totlen = usb_makestrdesc(sd, len, 2076 "EHCI root hub"); 2077 break; 2078 } 2079 #undef sd 2080 break; 2081 default: 2082 err = USBD_IOERROR; 2083 goto ret; 2084 } 2085 break; 2086 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2087 if (len > 0) { 2088 *(u_int8_t *)buf = 0; 2089 totlen = 1; 2090 } 2091 break; 2092 case C(UR_GET_STATUS, UT_READ_DEVICE): 2093 if (len > 1) { 2094 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2095 totlen = 2; 2096 } 2097 break; 2098 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2099 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2100 if (len > 1) { 2101 USETW(((usb_status_t *)buf)->wStatus, 0); 2102 totlen = 2; 2103 } 2104 break; 2105 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2106 if (value >= USB_MAX_DEVICES) { 2107 err = USBD_IOERROR; 2108 goto ret; 2109 } 2110 sc->sc_addr = value; 2111 break; 2112 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2113 if (value != 0 && value != 1) { 2114 err = USBD_IOERROR; 2115 goto ret; 2116 } 2117 sc->sc_conf = value; 2118 break; 2119 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2120 break; 2121 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2122 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2123 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2124 err = USBD_IOERROR; 2125 goto ret; 2126 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2127 break; 2128 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2129 break; 2130 /* Hub requests */ 2131 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2132 break; 2133 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2134 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2135 "port=%d feature=%d\n", 2136 index, value)); 2137 if (index < 1 || index > sc->sc_noport) { 2138 err = USBD_IOERROR; 2139 goto ret; 2140 } 2141 port = EHCI_PORTSC(index); 2142 v = EOREAD4(sc, port); 2143 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2144 v &= ~EHCI_PS_CLEAR; 2145 switch(value) { 2146 case UHF_PORT_ENABLE: 2147 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2148 break; 2149 case UHF_PORT_SUSPEND: 2150 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2151 break; 2152 v &= ~EHCI_PS_SUSP; 2153 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2154 /* see USB2 spec ch. 7.1.7.7 */ 2155 usb_delay_ms(&sc->sc_bus, 20); 2156 EOWRITE4(sc, port, v); 2157 usb_delay_ms(&sc->sc_bus, 2); 2158 #ifdef DEBUG 2159 v = EOREAD4(sc, port); 2160 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2161 printf("ehci: resume failed: %x\n", v); 2162 #endif 2163 break; 2164 case UHF_PORT_POWER: 2165 if (sc->sc_hasppc) 2166 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2167 break; 2168 case UHF_PORT_TEST: 2169 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2170 "%d\n", index)); 2171 break; 2172 case UHF_PORT_INDICATOR: 2173 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2174 "%d\n", index)); 2175 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2176 break; 2177 case UHF_C_PORT_CONNECTION: 2178 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2179 break; 2180 case UHF_C_PORT_ENABLE: 2181 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2182 break; 2183 case UHF_C_PORT_SUSPEND: 2184 /* how? */ 2185 break; 2186 case UHF_C_PORT_OVER_CURRENT: 2187 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2188 break; 2189 case UHF_C_PORT_RESET: 2190 sc->sc_isreset[index] = 0; 2191 break; 2192 default: 2193 err = USBD_IOERROR; 2194 goto ret; 2195 } 2196 #if 0 2197 switch(value) { 2198 case UHF_C_PORT_CONNECTION: 2199 case UHF_C_PORT_ENABLE: 2200 case UHF_C_PORT_SUSPEND: 2201 case UHF_C_PORT_OVER_CURRENT: 2202 case UHF_C_PORT_RESET: 2203 default: 2204 break; 2205 } 2206 #endif 2207 break; 2208 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2209 if (len == 0) 2210 break; 2211 if ((value & 0xff) != 0) { 2212 err = USBD_IOERROR; 2213 goto ret; 2214 } 2215 hubd = ehci_hubd; 2216 hubd.bNbrPorts = sc->sc_noport; 2217 v = EOREAD4(sc, EHCI_HCSPARAMS); 2218 USETW(hubd.wHubCharacteristics, 2219 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2220 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2221 ? UHD_PORT_IND : 0); 2222 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2223 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2224 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2225 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2226 l = min(len, hubd.bDescLength); 2227 totlen = l; 2228 memcpy(buf, &hubd, l); 2229 break; 2230 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2231 if (len != 4) { 2232 err = USBD_IOERROR; 2233 goto ret; 2234 } 2235 memset(buf, 0, len); /* ? XXX */ 2236 totlen = len; 2237 break; 2238 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2239 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2240 index)); 2241 if (index < 1 || index > sc->sc_noport) { 2242 err = USBD_IOERROR; 2243 goto ret; 2244 } 2245 if (len != 4) { 2246 err = USBD_IOERROR; 2247 goto ret; 2248 } 2249 v = EOREAD4(sc, EHCI_PORTSC(index)); 2250 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2251 v)); 2252 i = UPS_HIGH_SPEED; 2253 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2254 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2255 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2256 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2257 if (v & EHCI_PS_PR) i |= UPS_RESET; 2258 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2259 if (sc->sc_vendor_port_status) 2260 i = sc->sc_vendor_port_status(sc, v, i); 2261 USETW(ps.wPortStatus, i); 2262 i = 0; 2263 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2264 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2265 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2266 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2267 USETW(ps.wPortChange, i); 2268 l = min(len, sizeof ps); 2269 memcpy(buf, &ps, l); 2270 totlen = l; 2271 break; 2272 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2273 err = USBD_IOERROR; 2274 goto ret; 2275 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2276 break; 2277 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2278 if (index < 1 || index > sc->sc_noport) { 2279 err = USBD_IOERROR; 2280 goto ret; 2281 } 2282 port = EHCI_PORTSC(index); 2283 v = EOREAD4(sc, port); 2284 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2285 v &= ~EHCI_PS_CLEAR; 2286 switch(value) { 2287 case UHF_PORT_ENABLE: 2288 EOWRITE4(sc, port, v | EHCI_PS_PE); 2289 break; 2290 case UHF_PORT_SUSPEND: 2291 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2292 break; 2293 case UHF_PORT_RESET: 2294 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2295 index)); 2296 if (EHCI_PS_IS_LOWSPEED(v) && sc->sc_ncomp > 0) { 2297 /* Low speed device, give up ownership. */ 2298 ehci_disown(sc, index, 1); 2299 break; 2300 } 2301 /* Start reset sequence. */ 2302 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2303 EOWRITE4(sc, port, v | EHCI_PS_PR); 2304 /* Wait for reset to complete. */ 2305 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2306 if (sc->sc_dying) { 2307 err = USBD_IOERROR; 2308 goto ret; 2309 } 2310 /* Terminate reset sequence. */ 2311 v = EOREAD4(sc, port); 2312 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2313 /* Wait for HC to complete reset. */ 2314 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE); 2315 if (sc->sc_dying) { 2316 err = USBD_IOERROR; 2317 goto ret; 2318 } 2319 v = EOREAD4(sc, port); 2320 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2321 if (v & EHCI_PS_PR) { 2322 printf("%s: port reset timeout\n", 2323 device_xname(sc->sc_dev)); 2324 return (USBD_TIMEOUT); 2325 } 2326 if (!(v & EHCI_PS_PE)) { 2327 /* Not a high speed device, give up ownership.*/ 2328 ehci_disown(sc, index, 0); 2329 break; 2330 } 2331 sc->sc_isreset[index] = 1; 2332 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2333 index, v)); 2334 break; 2335 case UHF_PORT_POWER: 2336 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2337 "%d (has PPC = %d)\n", index, 2338 sc->sc_hasppc)); 2339 if (sc->sc_hasppc) 2340 EOWRITE4(sc, port, v | EHCI_PS_PP); 2341 break; 2342 case UHF_PORT_TEST: 2343 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2344 "%d\n", index)); 2345 break; 2346 case UHF_PORT_INDICATOR: 2347 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2348 "%d\n", index)); 2349 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2350 break; 2351 default: 2352 err = USBD_IOERROR; 2353 goto ret; 2354 } 2355 break; 2356 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2357 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2358 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2359 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2360 break; 2361 default: 2362 err = USBD_IOERROR; 2363 goto ret; 2364 } 2365 xfer->actlen = totlen; 2366 err = USBD_NORMAL_COMPLETION; 2367 ret: 2368 xfer->status = err; 2369 s = splusb(); 2370 usb_transfer_complete(xfer); 2371 splx(s); 2372 return (USBD_IN_PROGRESS); 2373 } 2374 2375 Static void 2376 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2377 { 2378 int port; 2379 u_int32_t v; 2380 2381 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2382 #ifdef DIAGNOSTIC 2383 if (sc->sc_npcomp != 0) { 2384 int i = (index-1) / sc->sc_npcomp; 2385 if (i >= sc->sc_ncomp) 2386 printf("%s: strange port\n", 2387 device_xname(sc->sc_dev)); 2388 else 2389 printf("%s: handing over %s speed device on " 2390 "port %d to %s\n", 2391 device_xname(sc->sc_dev), 2392 lowspeed ? "low" : "full", 2393 index, device_xname(sc->sc_comps[i])); 2394 } else { 2395 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2396 } 2397 #endif 2398 port = EHCI_PORTSC(index); 2399 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2400 EOWRITE4(sc, port, v | EHCI_PS_PO); 2401 } 2402 2403 /* Abort a root control request. */ 2404 Static void 2405 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2406 { 2407 /* Nothing to do, all transfers are synchronous. */ 2408 } 2409 2410 /* Close the root pipe. */ 2411 Static void 2412 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2413 { 2414 DPRINTF(("ehci_root_ctrl_close\n")); 2415 /* Nothing to do. */ 2416 } 2417 2418 Static void 2419 ehci_root_intr_done(usbd_xfer_handle xfer) 2420 { 2421 xfer->hcpriv = NULL; 2422 } 2423 2424 Static usbd_status 2425 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2426 { 2427 usbd_status err; 2428 2429 /* Insert last in queue. */ 2430 err = usb_insert_transfer(xfer); 2431 if (err) 2432 return (err); 2433 2434 /* Pipe isn't running, start first */ 2435 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2436 } 2437 2438 Static usbd_status 2439 ehci_root_intr_start(usbd_xfer_handle xfer) 2440 { 2441 usbd_pipe_handle pipe = xfer->pipe; 2442 ehci_softc_t *sc = pipe->device->bus->hci_private; 2443 2444 if (sc->sc_dying) 2445 return (USBD_IOERROR); 2446 2447 sc->sc_intrxfer = xfer; 2448 2449 return (USBD_IN_PROGRESS); 2450 } 2451 2452 /* Abort a root interrupt request. */ 2453 Static void 2454 ehci_root_intr_abort(usbd_xfer_handle xfer) 2455 { 2456 int s; 2457 2458 if (xfer->pipe->intrxfer == xfer) { 2459 DPRINTF(("ehci_root_intr_abort: remove\n")); 2460 xfer->pipe->intrxfer = NULL; 2461 } 2462 xfer->status = USBD_CANCELLED; 2463 s = splusb(); 2464 usb_transfer_complete(xfer); 2465 splx(s); 2466 } 2467 2468 /* Close the root pipe. */ 2469 Static void 2470 ehci_root_intr_close(usbd_pipe_handle pipe) 2471 { 2472 ehci_softc_t *sc = pipe->device->bus->hci_private; 2473 2474 DPRINTF(("ehci_root_intr_close\n")); 2475 2476 sc->sc_intrxfer = NULL; 2477 } 2478 2479 Static void 2480 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2481 { 2482 xfer->hcpriv = NULL; 2483 } 2484 2485 /************************/ 2486 2487 Static ehci_soft_qh_t * 2488 ehci_alloc_sqh(ehci_softc_t *sc) 2489 { 2490 ehci_soft_qh_t *sqh; 2491 usbd_status err; 2492 int i, offs; 2493 usb_dma_t dma; 2494 2495 if (sc->sc_freeqhs == NULL) { 2496 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2497 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2498 EHCI_PAGE_SIZE, &dma); 2499 #ifdef EHCI_DEBUG 2500 if (err) 2501 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2502 #endif 2503 if (err) 2504 return (NULL); 2505 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2506 offs = i * EHCI_SQH_SIZE; 2507 sqh = KERNADDR(&dma, offs); 2508 sqh->physaddr = DMAADDR(&dma, offs); 2509 sqh->dma = dma; 2510 sqh->offs = offs; 2511 sqh->next = sc->sc_freeqhs; 2512 sc->sc_freeqhs = sqh; 2513 } 2514 } 2515 sqh = sc->sc_freeqhs; 2516 sc->sc_freeqhs = sqh->next; 2517 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2518 sqh->next = NULL; 2519 return (sqh); 2520 } 2521 2522 Static void 2523 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2524 { 2525 sqh->next = sc->sc_freeqhs; 2526 sc->sc_freeqhs = sqh; 2527 } 2528 2529 Static ehci_soft_qtd_t * 2530 ehci_alloc_sqtd(ehci_softc_t *sc) 2531 { 2532 ehci_soft_qtd_t *sqtd; 2533 usbd_status err; 2534 int i, offs; 2535 usb_dma_t dma; 2536 int s; 2537 2538 if (sc->sc_freeqtds == NULL) { 2539 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2540 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2541 EHCI_PAGE_SIZE, &dma); 2542 #ifdef EHCI_DEBUG 2543 if (err) 2544 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2545 #endif 2546 if (err) 2547 return (NULL); 2548 s = splusb(); 2549 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2550 offs = i * EHCI_SQTD_SIZE; 2551 sqtd = KERNADDR(&dma, offs); 2552 sqtd->physaddr = DMAADDR(&dma, offs); 2553 sqtd->dma = dma; 2554 sqtd->offs = offs; 2555 sqtd->nextqtd = sc->sc_freeqtds; 2556 sc->sc_freeqtds = sqtd; 2557 } 2558 splx(s); 2559 } 2560 2561 s = splusb(); 2562 sqtd = sc->sc_freeqtds; 2563 sc->sc_freeqtds = sqtd->nextqtd; 2564 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2565 sqtd->nextqtd = NULL; 2566 sqtd->xfer = NULL; 2567 splx(s); 2568 2569 return (sqtd); 2570 } 2571 2572 Static void 2573 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2574 { 2575 int s; 2576 2577 s = splusb(); 2578 sqtd->nextqtd = sc->sc_freeqtds; 2579 sc->sc_freeqtds = sqtd; 2580 splx(s); 2581 } 2582 2583 Static usbd_status 2584 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2585 int alen, int rd, usbd_xfer_handle xfer, 2586 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2587 { 2588 ehci_soft_qtd_t *next, *cur; 2589 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2590 u_int32_t qtdstatus; 2591 int len, curlen, mps; 2592 int i, tog; 2593 usb_dma_t *dma = &xfer->dmabuf; 2594 u_int16_t flags = xfer->flags; 2595 2596 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2597 2598 len = alen; 2599 dataphys = DMAADDR(dma, 0); 2600 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2601 qtdstatus = EHCI_QTD_ACTIVE | 2602 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2603 EHCI_QTD_SET_CERR(3) 2604 /* IOC set below */ 2605 /* BYTES set below */ 2606 ; 2607 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2608 tog = epipe->nexttoggle; 2609 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2610 2611 cur = ehci_alloc_sqtd(sc); 2612 *sp = cur; 2613 if (cur == NULL) 2614 goto nomem; 2615 2616 usb_syncmem(dma, 0, alen, 2617 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2618 for (;;) { 2619 dataphyspage = EHCI_PAGE(dataphys); 2620 /* The EHCI hardware can handle at most 5 pages. */ 2621 if (dataphyslastpage - dataphyspage < 2622 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2623 /* we can handle it in this QTD */ 2624 curlen = len; 2625 } else { 2626 /* must use multiple TDs, fill as much as possible. */ 2627 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2628 EHCI_PAGE_OFFSET(dataphys); 2629 #ifdef DIAGNOSTIC 2630 if (curlen > len) { 2631 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2632 "len=0x%x offs=0x%x\n", curlen, len, 2633 EHCI_PAGE_OFFSET(dataphys)); 2634 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2635 dataphyslastpage, dataphyspage, 2636 dataphys); 2637 curlen = len; 2638 } 2639 #endif 2640 /* the length must be a multiple of the max size */ 2641 curlen -= curlen % mps; 2642 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2643 "curlen=%d\n", curlen)); 2644 #ifdef DIAGNOSTIC 2645 if (curlen == 0) 2646 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2647 #endif 2648 } 2649 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2650 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2651 dataphys, dataphyslastpage, 2652 len, curlen)); 2653 len -= curlen; 2654 2655 /* 2656 * Allocate another transfer if there's more data left, 2657 * or if force last short transfer flag is set and we're 2658 * allocating a multiple of the max packet size. 2659 */ 2660 if (len != 0 || 2661 ((curlen % mps) == 0 && !rd && curlen != 0 && 2662 (flags & USBD_FORCE_SHORT_XFER))) { 2663 next = ehci_alloc_sqtd(sc); 2664 if (next == NULL) 2665 goto nomem; 2666 nextphys = htole32(next->physaddr); 2667 } else { 2668 next = NULL; 2669 nextphys = EHCI_NULL; 2670 } 2671 2672 for (i = 0; i * EHCI_PAGE_SIZE < 2673 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2674 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2675 if (i != 0) /* use offset only in first buffer */ 2676 a = EHCI_PAGE(a); 2677 cur->qtd.qtd_buffer[i] = htole32(a); 2678 cur->qtd.qtd_buffer_hi[i] = 0; 2679 #ifdef DIAGNOSTIC 2680 if (i >= EHCI_QTD_NBUFFERS) { 2681 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2682 goto nomem; 2683 } 2684 #endif 2685 } 2686 cur->nextqtd = next; 2687 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2688 cur->qtd.qtd_status = 2689 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2690 cur->xfer = xfer; 2691 cur->len = curlen; 2692 2693 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2694 dataphys, dataphys + curlen)); 2695 /* adjust the toggle based on the number of packets in this 2696 qtd */ 2697 if (((curlen + mps - 1) / mps) & 1) { 2698 tog ^= 1; 2699 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2700 } 2701 if (next == NULL) 2702 break; 2703 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2704 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2705 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2706 dataphys += curlen; 2707 cur = next; 2708 } 2709 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2710 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2711 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2712 *ep = cur; 2713 epipe->nexttoggle = tog; 2714 2715 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2716 *sp, *ep)); 2717 2718 return (USBD_NORMAL_COMPLETION); 2719 2720 nomem: 2721 /* XXX free chain */ 2722 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2723 return (USBD_NOMEM); 2724 } 2725 2726 Static void 2727 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2728 ehci_soft_qtd_t *sqtdend) 2729 { 2730 ehci_soft_qtd_t *p; 2731 int i; 2732 2733 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2734 sqtd, sqtdend)); 2735 2736 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2737 p = sqtd->nextqtd; 2738 ehci_free_sqtd(sc, sqtd); 2739 } 2740 } 2741 2742 Static ehci_soft_itd_t * 2743 ehci_alloc_itd(ehci_softc_t *sc) 2744 { 2745 struct ehci_soft_itd *itd, *freeitd; 2746 usbd_status err; 2747 int i, s, offs, frindex, previndex; 2748 usb_dma_t dma; 2749 2750 s = splusb(); 2751 2752 /* Find an itd that wasn't freed this frame or last frame. This can 2753 * discard itds that were freed before frindex wrapped around 2754 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2755 * interrupt and fiddling with list when that happens */ 2756 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2757 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2758 2759 freeitd = NULL; 2760 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2761 if (itd == NULL) 2762 break; 2763 if (itd->slot != frindex && itd->slot != previndex) { 2764 freeitd = itd; 2765 break; 2766 } 2767 } 2768 2769 if (freeitd == NULL) { 2770 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2771 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2772 EHCI_PAGE_SIZE, &dma); 2773 2774 if (err) { 2775 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2776 return NULL; 2777 } 2778 2779 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2780 offs = i * EHCI_ITD_SIZE; 2781 itd = KERNADDR(&dma, offs); 2782 itd->physaddr = DMAADDR(&dma, offs); 2783 itd->dma = dma; 2784 itd->offs = offs; 2785 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2786 } 2787 freeitd = LIST_FIRST(&sc->sc_freeitds); 2788 } 2789 2790 itd = freeitd; 2791 LIST_REMOVE(itd, u.free_list); 2792 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2793 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2794 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2795 BUS_DMASYNC_PREREAD); 2796 2797 itd->u.frame_list.next = NULL; 2798 itd->u.frame_list.prev = NULL; 2799 itd->xfer_next = NULL; 2800 itd->slot = 0; 2801 splx(s); 2802 2803 return itd; 2804 } 2805 2806 Static void 2807 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2808 { 2809 int s; 2810 2811 s = splusb(); 2812 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2813 splx(s); 2814 } 2815 2816 /****************/ 2817 2818 /* 2819 * Close a reqular pipe. 2820 * Assumes that there are no pending transactions. 2821 */ 2822 Static void 2823 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2824 { 2825 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2826 ehci_softc_t *sc = pipe->device->bus->hci_private; 2827 ehci_soft_qh_t *sqh = epipe->sqh; 2828 int s; 2829 2830 s = splusb(); 2831 ehci_rem_qh(sc, sqh, head); 2832 splx(s); 2833 ehci_free_sqh(sc, epipe->sqh); 2834 } 2835 2836 /* 2837 * Abort a device request. 2838 * If this routine is called at splusb() it guarantees that the request 2839 * will be removed from the hardware scheduling and that the callback 2840 * for it will be called with USBD_CANCELLED status. 2841 * It's impossible to guarantee that the requested transfer will not 2842 * have happened since the hardware runs concurrently. 2843 * If the transaction has already happened we rely on the ordinary 2844 * interrupt processing to process it. 2845 * XXX This is most probably wrong. 2846 */ 2847 Static void 2848 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2849 { 2850 #define exfer EXFER(xfer) 2851 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2852 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2853 ehci_soft_qh_t *sqh = epipe->sqh; 2854 ehci_soft_qtd_t *sqtd; 2855 ehci_physaddr_t cur; 2856 u_int32_t qhstatus; 2857 int s; 2858 int hit; 2859 int wake; 2860 2861 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2862 2863 if (sc->sc_dying) { 2864 /* If we're dying, just do the software part. */ 2865 s = splusb(); 2866 xfer->status = status; /* make software ignore it */ 2867 callout_stop(&xfer->timeout_handle); 2868 usb_transfer_complete(xfer); 2869 splx(s); 2870 return; 2871 } 2872 2873 if (xfer->device->bus->intr_context) 2874 panic("ehci_abort_xfer: not in process context"); 2875 2876 /* 2877 * If an abort is already in progress then just wait for it to 2878 * complete and return. 2879 */ 2880 if (xfer->hcflags & UXFER_ABORTING) { 2881 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2882 #ifdef DIAGNOSTIC 2883 if (status == USBD_TIMEOUT) 2884 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2885 #endif 2886 /* Override the status which might be USBD_TIMEOUT. */ 2887 xfer->status = status; 2888 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2889 xfer->hcflags |= UXFER_ABORTWAIT; 2890 while (xfer->hcflags & UXFER_ABORTING) 2891 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2892 return; 2893 } 2894 xfer->hcflags |= UXFER_ABORTING; 2895 2896 /* 2897 * Step 1: Make interrupt routine and hardware ignore xfer. 2898 */ 2899 s = splusb(); 2900 xfer->status = status; /* make software ignore it */ 2901 callout_stop(&xfer->timeout_handle); 2902 2903 usb_syncmem(&sqh->dma, 2904 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2905 sizeof(sqh->qh.qh_qtd.qtd_status), 2906 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2907 qhstatus = sqh->qh.qh_qtd.qtd_status; 2908 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2909 usb_syncmem(&sqh->dma, 2910 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2911 sizeof(sqh->qh.qh_qtd.qtd_status), 2912 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2913 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2914 usb_syncmem(&sqtd->dma, 2915 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2916 sizeof(sqtd->qtd.qtd_status), 2917 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2918 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2919 usb_syncmem(&sqtd->dma, 2920 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2921 sizeof(sqtd->qtd.qtd_status), 2922 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2923 if (sqtd == exfer->sqtdend) 2924 break; 2925 } 2926 splx(s); 2927 2928 /* 2929 * Step 2: Wait until we know hardware has finished any possible 2930 * use of the xfer. Also make sure the soft interrupt routine 2931 * has run. 2932 */ 2933 ehci_sync_hc(sc); 2934 s = splusb(); 2935 #ifdef USB_USE_SOFTINTR 2936 sc->sc_softwake = 1; 2937 #endif /* USB_USE_SOFTINTR */ 2938 usb_schedsoftintr(&sc->sc_bus); 2939 #ifdef USB_USE_SOFTINTR 2940 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2941 #endif /* USB_USE_SOFTINTR */ 2942 splx(s); 2943 2944 /* 2945 * Step 3: Remove any vestiges of the xfer from the hardware. 2946 * The complication here is that the hardware may have executed 2947 * beyond the xfer we're trying to abort. So as we're scanning 2948 * the TDs of this xfer we check if the hardware points to 2949 * any of them. 2950 */ 2951 s = splusb(); /* XXX why? */ 2952 2953 usb_syncmem(&sqh->dma, 2954 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2955 sizeof(sqh->qh.qh_curqtd), 2956 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2957 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 2958 hit = 0; 2959 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2960 hit |= cur == sqtd->physaddr; 2961 if (sqtd == exfer->sqtdend) 2962 break; 2963 } 2964 sqtd = sqtd->nextqtd; 2965 /* Zap curqtd register if hardware pointed inside the xfer. */ 2966 if (hit && sqtd != NULL) { 2967 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 2968 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 2969 usb_syncmem(&sqh->dma, 2970 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2971 sizeof(sqh->qh.qh_curqtd), 2972 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2973 sqh->qh.qh_qtd.qtd_status = qhstatus; 2974 usb_syncmem(&sqh->dma, 2975 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2976 sizeof(sqh->qh.qh_qtd.qtd_status), 2977 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2978 } else { 2979 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 2980 } 2981 2982 /* 2983 * Step 4: Execute callback. 2984 */ 2985 #ifdef DIAGNOSTIC 2986 exfer->isdone = 1; 2987 #endif 2988 wake = xfer->hcflags & UXFER_ABORTWAIT; 2989 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 2990 usb_transfer_complete(xfer); 2991 if (wake) 2992 wakeup(&xfer->hcflags); 2993 2994 splx(s); 2995 #undef exfer 2996 } 2997 2998 Static void 2999 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3000 { 3001 ehci_isoc_trans_t trans_status; 3002 struct ehci_pipe *epipe; 3003 struct ehci_xfer *exfer; 3004 ehci_softc_t *sc; 3005 struct ehci_soft_itd *itd; 3006 int s, i, wake; 3007 3008 epipe = (struct ehci_pipe *) xfer->pipe; 3009 exfer = EXFER(xfer); 3010 sc = epipe->pipe.device->bus->hci_private; 3011 3012 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3013 3014 if (sc->sc_dying) { 3015 s = splusb(); 3016 xfer->status = status; 3017 callout_stop(&xfer->timeout_handle); 3018 usb_transfer_complete(xfer); 3019 splx(s); 3020 return; 3021 } 3022 3023 if (xfer->hcflags & UXFER_ABORTING) { 3024 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3025 3026 #ifdef DIAGNOSTIC 3027 if (status == USBD_TIMEOUT) 3028 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3029 #endif 3030 3031 xfer->status = status; 3032 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3033 xfer->hcflags |= UXFER_ABORTWAIT; 3034 while (xfer->hcflags & UXFER_ABORTING) 3035 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0); 3036 return; 3037 } 3038 xfer->hcflags |= UXFER_ABORTING; 3039 3040 xfer->status = status; 3041 callout_stop(&xfer->timeout_handle); 3042 3043 s = splusb(); 3044 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3045 usb_syncmem(&itd->dma, 3046 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3047 sizeof(itd->itd.itd_ctl), 3048 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3049 3050 for (i = 0; i < 8; i++) { 3051 trans_status = le32toh(itd->itd.itd_ctl[i]); 3052 trans_status &= ~EHCI_ITD_ACTIVE; 3053 itd->itd.itd_ctl[i] = htole32(trans_status); 3054 } 3055 3056 usb_syncmem(&itd->dma, 3057 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3058 sizeof(itd->itd.itd_ctl), 3059 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3060 } 3061 splx(s); 3062 3063 s = splusb(); 3064 #ifdef USB_USE_SOFTINTR 3065 sc->sc_softwake = 1; 3066 #endif /* USB_USE_SOFTINTR */ 3067 usb_schedsoftintr(&sc->sc_bus); 3068 #ifdef USB_USE_SOFTINTR 3069 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3070 #endif /* USB_USE_SOFTINTR */ 3071 splx(s); 3072 3073 #ifdef DIAGNOSTIC 3074 exfer->isdone = 1; 3075 #endif 3076 wake = xfer->hcflags & UXFER_ABORTWAIT; 3077 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3078 usb_transfer_complete(xfer); 3079 if (wake) 3080 wakeup(&xfer->hcflags); 3081 3082 return; 3083 } 3084 3085 Static void 3086 ehci_timeout(void *addr) 3087 { 3088 struct ehci_xfer *exfer = addr; 3089 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3090 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3091 3092 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3093 #ifdef EHCI_DEBUG 3094 if (ehcidebug > 1) 3095 usbd_dump_pipe(exfer->xfer.pipe); 3096 #endif 3097 3098 if (sc->sc_dying) { 3099 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3100 return; 3101 } 3102 3103 /* Execute the abort in a process context. */ 3104 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3105 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3106 USB_TASKQ_HC); 3107 } 3108 3109 Static void 3110 ehci_timeout_task(void *addr) 3111 { 3112 usbd_xfer_handle xfer = addr; 3113 int s; 3114 3115 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3116 3117 s = splusb(); 3118 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3119 splx(s); 3120 } 3121 3122 /************************/ 3123 3124 Static usbd_status 3125 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3126 { 3127 usbd_status err; 3128 3129 /* Insert last in queue. */ 3130 err = usb_insert_transfer(xfer); 3131 if (err) 3132 return (err); 3133 3134 /* Pipe isn't running, start first */ 3135 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3136 } 3137 3138 Static usbd_status 3139 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3140 { 3141 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3142 usbd_status err; 3143 3144 if (sc->sc_dying) 3145 return (USBD_IOERROR); 3146 3147 #ifdef DIAGNOSTIC 3148 if (!(xfer->rqflags & URQ_REQUEST)) { 3149 /* XXX panic */ 3150 printf("ehci_device_ctrl_transfer: not a request\n"); 3151 return (USBD_INVAL); 3152 } 3153 #endif 3154 3155 err = ehci_device_request(xfer); 3156 if (err) 3157 return (err); 3158 3159 if (sc->sc_bus.use_polling) 3160 ehci_waitintr(sc, xfer); 3161 return (USBD_IN_PROGRESS); 3162 } 3163 3164 Static void 3165 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3166 { 3167 struct ehci_xfer *ex = EXFER(xfer); 3168 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3169 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3170 usb_device_request_t *req = &xfer->request; 3171 int len = UGETW(req->wLength); 3172 int rd = req->bmRequestType & UT_READ; 3173 3174 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3175 3176 #ifdef DIAGNOSTIC 3177 if (!(xfer->rqflags & URQ_REQUEST)) { 3178 panic("ehci_ctrl_done: not a request"); 3179 } 3180 #endif 3181 3182 mutex_enter(&sc->sc_intrhead_lock); 3183 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3184 ehci_del_intr_list(sc, ex); /* remove from active list */ 3185 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3186 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3187 BUS_DMASYNC_POSTWRITE); 3188 if (len) 3189 usb_syncmem(&xfer->dmabuf, 0, len, 3190 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3191 } 3192 mutex_exit(&sc->sc_intrhead_lock); 3193 3194 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3195 } 3196 3197 /* Abort a device control request. */ 3198 Static void 3199 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3200 { 3201 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3202 ehci_abort_xfer(xfer, USBD_CANCELLED); 3203 } 3204 3205 /* Close a device control pipe. */ 3206 Static void 3207 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3208 { 3209 ehci_softc_t *sc = pipe->device->bus->hci_private; 3210 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3211 3212 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3213 ehci_close_pipe(pipe, sc->sc_async_head); 3214 } 3215 3216 Static usbd_status 3217 ehci_device_request(usbd_xfer_handle xfer) 3218 { 3219 #define exfer EXFER(xfer) 3220 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3221 usb_device_request_t *req = &xfer->request; 3222 usbd_device_handle dev = epipe->pipe.device; 3223 ehci_softc_t *sc = dev->bus->hci_private; 3224 int addr = dev->address; 3225 ehci_soft_qtd_t *setup, *stat, *next; 3226 ehci_soft_qh_t *sqh; 3227 int isread; 3228 int len; 3229 usbd_status err; 3230 int s; 3231 3232 isread = req->bmRequestType & UT_READ; 3233 len = UGETW(req->wLength); 3234 3235 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3236 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3237 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3238 UGETW(req->wIndex), len, addr, 3239 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3240 3241 setup = ehci_alloc_sqtd(sc); 3242 if (setup == NULL) { 3243 err = USBD_NOMEM; 3244 goto bad1; 3245 } 3246 stat = ehci_alloc_sqtd(sc); 3247 if (stat == NULL) { 3248 err = USBD_NOMEM; 3249 goto bad2; 3250 } 3251 3252 sqh = epipe->sqh; 3253 epipe->u.ctl.length = len; 3254 3255 /* Update device address and length since they may have changed 3256 during the setup of the control pipe in usbd_new_device(). */ 3257 /* XXX This only needs to be done once, but it's too early in open. */ 3258 /* XXXX Should not touch ED here! */ 3259 sqh->qh.qh_endp = 3260 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3261 htole32( 3262 EHCI_QH_SET_ADDR(addr) | 3263 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3264 ); 3265 3266 /* Set up data transaction */ 3267 if (len != 0) { 3268 ehci_soft_qtd_t *end; 3269 3270 /* Start toggle at 1. */ 3271 epipe->nexttoggle = 1; 3272 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3273 &next, &end); 3274 if (err) 3275 goto bad3; 3276 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3277 end->nextqtd = stat; 3278 end->qtd.qtd_next = 3279 end->qtd.qtd_altnext = htole32(stat->physaddr); 3280 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3281 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3282 } else { 3283 next = stat; 3284 } 3285 3286 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3287 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3288 3289 /* Clear toggle */ 3290 setup->qtd.qtd_status = htole32( 3291 EHCI_QTD_ACTIVE | 3292 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3293 EHCI_QTD_SET_CERR(3) | 3294 EHCI_QTD_SET_TOGGLE(0) | 3295 EHCI_QTD_SET_BYTES(sizeof *req) 3296 ); 3297 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3298 setup->qtd.qtd_buffer_hi[0] = 0; 3299 setup->nextqtd = next; 3300 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3301 setup->xfer = xfer; 3302 setup->len = sizeof *req; 3303 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3304 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3305 3306 stat->qtd.qtd_status = htole32( 3307 EHCI_QTD_ACTIVE | 3308 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3309 EHCI_QTD_SET_CERR(3) | 3310 EHCI_QTD_SET_TOGGLE(1) | 3311 EHCI_QTD_IOC 3312 ); 3313 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3314 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3315 stat->nextqtd = NULL; 3316 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3317 stat->xfer = xfer; 3318 stat->len = 0; 3319 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3320 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3321 3322 #ifdef EHCI_DEBUG 3323 if (ehcidebug > 5) { 3324 DPRINTF(("ehci_device_request:\n")); 3325 ehci_dump_sqh(sqh); 3326 ehci_dump_sqtds(setup); 3327 } 3328 #endif 3329 3330 exfer->sqtdstart = setup; 3331 exfer->sqtdend = stat; 3332 #ifdef DIAGNOSTIC 3333 if (!exfer->isdone) { 3334 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3335 } 3336 exfer->isdone = 0; 3337 #endif 3338 3339 /* Insert qTD in QH list. */ 3340 s = splusb(); 3341 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3342 if (xfer->timeout && !sc->sc_bus.use_polling) { 3343 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3344 (ehci_timeout), (xfer)); 3345 } 3346 mutex_enter(&sc->sc_intrhead_lock); 3347 ehci_add_intr_list(sc, exfer); 3348 mutex_exit(&sc->sc_intrhead_lock); 3349 xfer->status = USBD_IN_PROGRESS; 3350 splx(s); 3351 3352 #ifdef EHCI_DEBUG 3353 if (ehcidebug > 10) { 3354 DPRINTF(("ehci_device_request: status=%x\n", 3355 EOREAD4(sc, EHCI_USBSTS))); 3356 delay(10000); 3357 ehci_dump_regs(sc); 3358 ehci_dump_sqh(sc->sc_async_head); 3359 ehci_dump_sqh(sqh); 3360 ehci_dump_sqtds(setup); 3361 } 3362 #endif 3363 3364 return (USBD_NORMAL_COMPLETION); 3365 3366 bad3: 3367 ehci_free_sqtd(sc, stat); 3368 bad2: 3369 ehci_free_sqtd(sc, setup); 3370 bad1: 3371 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3372 xfer->status = err; 3373 usb_transfer_complete(xfer); 3374 return (err); 3375 #undef exfer 3376 } 3377 3378 /* 3379 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3380 * qTD status, or miss signalling occasionally under heavy load. If the host 3381 * machine is too fast, we we can miss transaction completion - when we scan 3382 * the active list the transaction still seems to be active. This generally 3383 * exhibits itself as a umass stall that never recovers. 3384 * 3385 * We work around this behaviour by setting up this callback after any softintr 3386 * that completes with transactions still pending, giving us another chance to 3387 * check for completion after the writeback has taken place. 3388 */ 3389 Static void 3390 ehci_intrlist_timeout(void *arg) 3391 { 3392 ehci_softc_t *sc = arg; 3393 int s = splusb(); 3394 3395 DPRINTF(("ehci_intrlist_timeout\n")); 3396 usb_schedsoftintr(&sc->sc_bus); 3397 3398 splx(s); 3399 } 3400 3401 /************************/ 3402 3403 Static usbd_status 3404 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3405 { 3406 usbd_status err; 3407 3408 /* Insert last in queue. */ 3409 err = usb_insert_transfer(xfer); 3410 if (err) 3411 return (err); 3412 3413 /* Pipe isn't running, start first */ 3414 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3415 } 3416 3417 Static usbd_status 3418 ehci_device_bulk_start(usbd_xfer_handle xfer) 3419 { 3420 #define exfer EXFER(xfer) 3421 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3422 usbd_device_handle dev = epipe->pipe.device; 3423 ehci_softc_t *sc = dev->bus->hci_private; 3424 ehci_soft_qtd_t *data, *dataend; 3425 ehci_soft_qh_t *sqh; 3426 usbd_status err; 3427 int len, isread, endpt; 3428 int s; 3429 3430 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3431 xfer, xfer->length, xfer->flags)); 3432 3433 if (sc->sc_dying) 3434 return (USBD_IOERROR); 3435 3436 #ifdef DIAGNOSTIC 3437 if (xfer->rqflags & URQ_REQUEST) 3438 panic("ehci_device_bulk_start: a request"); 3439 #endif 3440 3441 len = xfer->length; 3442 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3443 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3444 sqh = epipe->sqh; 3445 3446 epipe->u.bulk.length = len; 3447 3448 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3449 &dataend); 3450 if (err) { 3451 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3452 xfer->status = err; 3453 usb_transfer_complete(xfer); 3454 return (err); 3455 } 3456 3457 #ifdef EHCI_DEBUG 3458 if (ehcidebug > 5) { 3459 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3460 ehci_dump_sqh(sqh); 3461 ehci_dump_sqtds(data); 3462 } 3463 #endif 3464 3465 /* Set up interrupt info. */ 3466 exfer->sqtdstart = data; 3467 exfer->sqtdend = dataend; 3468 #ifdef DIAGNOSTIC 3469 if (!exfer->isdone) { 3470 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3471 } 3472 exfer->isdone = 0; 3473 #endif 3474 3475 s = splusb(); 3476 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3477 if (xfer->timeout && !sc->sc_bus.use_polling) { 3478 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3479 (ehci_timeout), (xfer)); 3480 } 3481 mutex_enter(&sc->sc_intrhead_lock); 3482 ehci_add_intr_list(sc, exfer); 3483 mutex_exit(&sc->sc_intrhead_lock); 3484 xfer->status = USBD_IN_PROGRESS; 3485 splx(s); 3486 3487 #ifdef EHCI_DEBUG 3488 if (ehcidebug > 10) { 3489 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3490 delay(10000); 3491 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3492 ehci_dump_regs(sc); 3493 #if 0 3494 printf("async_head:\n"); 3495 ehci_dump_sqh(sc->sc_async_head); 3496 #endif 3497 printf("sqh:\n"); 3498 ehci_dump_sqh(sqh); 3499 ehci_dump_sqtds(data); 3500 } 3501 #endif 3502 3503 if (sc->sc_bus.use_polling) 3504 ehci_waitintr(sc, xfer); 3505 3506 return (USBD_IN_PROGRESS); 3507 #undef exfer 3508 } 3509 3510 Static void 3511 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3512 { 3513 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3514 ehci_abort_xfer(xfer, USBD_CANCELLED); 3515 } 3516 3517 /* 3518 * Close a device bulk pipe. 3519 */ 3520 Static void 3521 ehci_device_bulk_close(usbd_pipe_handle pipe) 3522 { 3523 ehci_softc_t *sc = pipe->device->bus->hci_private; 3524 3525 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3526 ehci_close_pipe(pipe, sc->sc_async_head); 3527 } 3528 3529 Static void 3530 ehci_device_bulk_done(usbd_xfer_handle xfer) 3531 { 3532 struct ehci_xfer *ex = EXFER(xfer); 3533 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3534 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3535 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3536 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3537 3538 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3539 xfer, xfer->actlen)); 3540 3541 mutex_enter(&sc->sc_intrhead_lock); 3542 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3543 ehci_del_intr_list(sc, ex); /* remove from active list */ 3544 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3545 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3546 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3547 } 3548 mutex_exit(&sc->sc_intrhead_lock); 3549 3550 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3551 } 3552 3553 /************************/ 3554 3555 Static usbd_status 3556 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3557 { 3558 struct ehci_soft_islot *isp; 3559 int islot, lev; 3560 3561 /* Find a poll rate that is large enough. */ 3562 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3563 if (EHCI_ILEV_IVAL(lev) <= ival) 3564 break; 3565 3566 /* Pick an interrupt slot at the right level. */ 3567 /* XXX could do better than picking at random */ 3568 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3569 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3570 3571 sqh->islot = islot; 3572 isp = &sc->sc_islots[islot]; 3573 ehci_add_qh(sqh, isp->sqh); 3574 3575 return (USBD_NORMAL_COMPLETION); 3576 } 3577 3578 Static usbd_status 3579 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3580 { 3581 usbd_status err; 3582 3583 /* Insert last in queue. */ 3584 err = usb_insert_transfer(xfer); 3585 if (err) 3586 return (err); 3587 3588 /* 3589 * Pipe isn't running (otherwise err would be USBD_INPROG), 3590 * so start it first. 3591 */ 3592 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3593 } 3594 3595 Static usbd_status 3596 ehci_device_intr_start(usbd_xfer_handle xfer) 3597 { 3598 #define exfer EXFER(xfer) 3599 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3600 usbd_device_handle dev = xfer->pipe->device; 3601 ehci_softc_t *sc = dev->bus->hci_private; 3602 ehci_soft_qtd_t *data, *dataend; 3603 ehci_soft_qh_t *sqh; 3604 usbd_status err; 3605 int len, isread, endpt; 3606 int s; 3607 3608 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3609 xfer, xfer->length, xfer->flags)); 3610 3611 if (sc->sc_dying) 3612 return (USBD_IOERROR); 3613 3614 #ifdef DIAGNOSTIC 3615 if (xfer->rqflags & URQ_REQUEST) 3616 panic("ehci_device_intr_start: a request"); 3617 #endif 3618 3619 len = xfer->length; 3620 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3621 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3622 sqh = epipe->sqh; 3623 3624 epipe->u.intr.length = len; 3625 3626 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3627 &dataend); 3628 if (err) { 3629 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3630 xfer->status = err; 3631 usb_transfer_complete(xfer); 3632 return (err); 3633 } 3634 3635 #ifdef EHCI_DEBUG 3636 if (ehcidebug > 5) { 3637 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3638 ehci_dump_sqh(sqh); 3639 ehci_dump_sqtds(data); 3640 } 3641 #endif 3642 3643 /* Set up interrupt info. */ 3644 exfer->sqtdstart = data; 3645 exfer->sqtdend = dataend; 3646 #ifdef DIAGNOSTIC 3647 if (!exfer->isdone) { 3648 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3649 } 3650 exfer->isdone = 0; 3651 #endif 3652 3653 s = splusb(); 3654 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3655 if (xfer->timeout && !sc->sc_bus.use_polling) { 3656 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3657 (ehci_timeout), (xfer)); 3658 } 3659 mutex_enter(&sc->sc_intrhead_lock); 3660 ehci_add_intr_list(sc, exfer); 3661 mutex_exit(&sc->sc_intrhead_lock); 3662 xfer->status = USBD_IN_PROGRESS; 3663 splx(s); 3664 3665 #ifdef EHCI_DEBUG 3666 if (ehcidebug > 10) { 3667 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3668 delay(10000); 3669 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3670 ehci_dump_regs(sc); 3671 printf("sqh:\n"); 3672 ehci_dump_sqh(sqh); 3673 ehci_dump_sqtds(data); 3674 } 3675 #endif 3676 3677 if (sc->sc_bus.use_polling) 3678 ehci_waitintr(sc, xfer); 3679 3680 return (USBD_IN_PROGRESS); 3681 #undef exfer 3682 } 3683 3684 Static void 3685 ehci_device_intr_abort(usbd_xfer_handle xfer) 3686 { 3687 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3688 if (xfer->pipe->intrxfer == xfer) { 3689 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3690 xfer->pipe->intrxfer = NULL; 3691 } 3692 /* 3693 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3694 * async doorbell. That's dependant on the async list, wheras 3695 * intr xfers are periodic, should not use this? 3696 */ 3697 ehci_abort_xfer(xfer, USBD_CANCELLED); 3698 } 3699 3700 Static void 3701 ehci_device_intr_close(usbd_pipe_handle pipe) 3702 { 3703 ehci_softc_t *sc = pipe->device->bus->hci_private; 3704 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3705 struct ehci_soft_islot *isp; 3706 3707 isp = &sc->sc_islots[epipe->sqh->islot]; 3708 ehci_close_pipe(pipe, isp->sqh); 3709 } 3710 3711 Static void 3712 ehci_device_intr_done(usbd_xfer_handle xfer) 3713 { 3714 #define exfer EXFER(xfer) 3715 struct ehci_xfer *ex = EXFER(xfer); 3716 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3717 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3718 ehci_soft_qtd_t *data, *dataend; 3719 ehci_soft_qh_t *sqh; 3720 usbd_status err; 3721 int len, isread, endpt, s; 3722 3723 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3724 xfer, xfer->actlen)); 3725 3726 mutex_enter(&sc->sc_intrhead_lock); 3727 if (xfer->pipe->repeat) { 3728 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3729 3730 len = epipe->u.intr.length; 3731 xfer->length = len; 3732 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3733 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3734 usb_syncmem(&xfer->dmabuf, 0, len, 3735 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3736 sqh = epipe->sqh; 3737 3738 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3739 &data, &dataend); 3740 if (err) { 3741 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3742 xfer->status = err; 3743 mutex_exit(&sc->sc_intrhead_lock); 3744 return; 3745 } 3746 3747 /* Set up interrupt info. */ 3748 exfer->sqtdstart = data; 3749 exfer->sqtdend = dataend; 3750 #ifdef DIAGNOSTIC 3751 if (!exfer->isdone) { 3752 printf("ehci_device_intr_done: not done, ex=%p\n", 3753 exfer); 3754 } 3755 exfer->isdone = 0; 3756 #endif 3757 3758 s = splusb(); 3759 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3760 if (xfer->timeout && !sc->sc_bus.use_polling) { 3761 callout_reset(&(xfer->timeout_handle), 3762 (mstohz(xfer->timeout)), (ehci_timeout), (xfer)); 3763 } 3764 splx(s); 3765 3766 xfer->status = USBD_IN_PROGRESS; 3767 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3768 ehci_del_intr_list(sc, ex); /* remove from active list */ 3769 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3770 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3771 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3772 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3773 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3774 } 3775 mutex_exit(&sc->sc_intrhead_lock); 3776 #undef exfer 3777 } 3778 3779 /************************/ 3780 3781 Static usbd_status 3782 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3783 { 3784 usbd_status err; 3785 3786 err = usb_insert_transfer(xfer); 3787 if (err && err != USBD_IN_PROGRESS) 3788 return err; 3789 3790 return ehci_device_isoc_start(xfer); 3791 } 3792 3793 Static usbd_status 3794 ehci_device_isoc_start(usbd_xfer_handle xfer) 3795 { 3796 struct ehci_pipe *epipe; 3797 usbd_device_handle dev; 3798 ehci_softc_t *sc; 3799 struct ehci_xfer *exfer; 3800 ehci_soft_itd_t *itd, *prev, *start, *stop; 3801 usb_dma_t *dma_buf; 3802 int i, j, k, frames, uframes, ufrperframe; 3803 int s, trans_count, offs, total_length; 3804 int frindex; 3805 3806 start = NULL; 3807 prev = NULL; 3808 itd = NULL; 3809 trans_count = 0; 3810 total_length = 0; 3811 exfer = (struct ehci_xfer *) xfer; 3812 sc = xfer->pipe->device->bus->hci_private; 3813 dev = xfer->pipe->device; 3814 epipe = (struct ehci_pipe *)xfer->pipe; 3815 3816 /* 3817 * To allow continuous transfers, above we start all transfers 3818 * immediately. However, we're still going to get usbd_start_next call 3819 * this when another xfer completes. So, check if this is already 3820 * in progress or not 3821 */ 3822 3823 if (exfer->itdstart != NULL) 3824 return USBD_IN_PROGRESS; 3825 3826 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3827 xfer, xfer->length, xfer->flags)); 3828 3829 if (sc->sc_dying) 3830 return USBD_IOERROR; 3831 3832 /* 3833 * To avoid complication, don't allow a request right now that'll span 3834 * the entire frame table. To within 4 frames, to allow some leeway 3835 * on either side of where the hc currently is. 3836 */ 3837 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3838 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3839 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3840 return USBD_INVAL; 3841 } 3842 3843 #ifdef DIAGNOSTIC 3844 if (xfer->rqflags & URQ_REQUEST) 3845 panic("ehci_device_isoc_start: request\n"); 3846 3847 if (!exfer->isdone) 3848 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3849 exfer->isdone = 0; 3850 #endif 3851 3852 /* 3853 * Step 1: Allocate and initialize itds, how many do we need? 3854 * One per transfer if interval >= 8 microframes, fewer if we use 3855 * multiple microframes per frame. 3856 */ 3857 3858 i = epipe->pipe.endpoint->edesc->bInterval; 3859 if (i > 16 || i == 0) { 3860 /* Spec page 271 says intervals > 16 are invalid */ 3861 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3862 return USBD_INVAL; 3863 } 3864 3865 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 3866 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3867 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 3868 3869 if (frames == 0) { 3870 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3871 return USBD_INVAL; 3872 } 3873 3874 dma_buf = &xfer->dmabuf; 3875 offs = 0; 3876 3877 for (i = 0; i < frames; i++) { 3878 int froffs = offs; 3879 itd = ehci_alloc_itd(sc); 3880 3881 if (prev != NULL) { 3882 prev->itd.itd_next = 3883 htole32(itd->physaddr | EHCI_LINK_ITD); 3884 usb_syncmem(&itd->dma, 3885 itd->offs + offsetof(ehci_itd_t, itd_next), 3886 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 3887 3888 prev->xfer_next = itd; 3889 } else { 3890 start = itd; 3891 } 3892 3893 /* 3894 * Step 1.5, initialize uframes 3895 */ 3896 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 3897 /* Calculate which page in the list this starts in */ 3898 int addr = DMAADDR(dma_buf, froffs); 3899 addr = EHCI_PAGE_OFFSET(addr); 3900 addr += (offs - froffs); 3901 addr = EHCI_PAGE(addr); 3902 addr /= EHCI_PAGE_SIZE; 3903 3904 /* This gets the initial offset into the first page, 3905 * looks how far further along the current uframe 3906 * offset is. Works out how many pages that is. 3907 */ 3908 3909 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3910 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3911 EHCI_ITD_SET_PG(addr) | 3912 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 3913 3914 total_length += xfer->frlengths[trans_count]; 3915 offs += xfer->frlengths[trans_count]; 3916 trans_count++; 3917 3918 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3919 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3920 break; 3921 } 3922 } 3923 3924 /* Step 1.75, set buffer pointers. To simplify matters, all 3925 * pointers are filled out for the next 7 hardware pages in 3926 * the dma block, so no need to worry what pages to cover 3927 * and what to not. 3928 */ 3929 3930 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 3931 /* 3932 * Don't try to lookup a page that's past the end 3933 * of buffer 3934 */ 3935 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 3936 if (page_offs >= dma_buf->block->size) 3937 break; 3938 3939 long long page = DMAADDR(dma_buf, page_offs); 3940 page = EHCI_PAGE(page); 3941 itd->itd.itd_bufr[j] = 3942 htole32(EHCI_ITD_SET_BPTR(page)); 3943 itd->itd.itd_bufr_hi[j] = 3944 htole32(page >> 32); 3945 } 3946 3947 /* 3948 * Other special values 3949 */ 3950 3951 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3952 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3953 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3954 3955 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3956 ? 1 : 0; 3957 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3958 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3959 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 3960 3961 /* FIXME: handle invalid trans */ 3962 itd->itd.itd_bufr[2] |= 3963 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 3964 3965 usb_syncmem(&itd->dma, 3966 itd->offs + offsetof(ehci_itd_t, itd_next), 3967 sizeof(ehci_itd_t), 3968 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3969 3970 prev = itd; 3971 } /* End of frame */ 3972 3973 stop = itd; 3974 stop->xfer_next = NULL; 3975 exfer->isoc_len = total_length; 3976 3977 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 3978 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3979 3980 /* 3981 * Part 2: Transfer descriptors have now been set up, now they must 3982 * be scheduled into the period frame list. Erk. Not wanting to 3983 * complicate matters, transfer is denied if the transfer spans 3984 * more than the period frame list. 3985 */ 3986 3987 s = splusb(); 3988 3989 /* Start inserting frames */ 3990 if (epipe->u.isoc.cur_xfers > 0) { 3991 frindex = epipe->u.isoc.next_frame; 3992 } else { 3993 frindex = EOREAD4(sc, EHCI_FRINDEX); 3994 frindex = frindex >> 3; /* Erase microframe index */ 3995 frindex += 2; 3996 } 3997 3998 if (frindex >= sc->sc_flsize) 3999 frindex &= (sc->sc_flsize - 1); 4000 4001 /* What's the frame interval? */ 4002 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4003 if (i / USB_UFRAMES_PER_FRAME == 0) 4004 i = 1; 4005 else 4006 i /= USB_UFRAMES_PER_FRAME; 4007 4008 itd = start; 4009 for (j = 0; j < frames; j++) { 4010 if (itd == NULL) 4011 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4012 4013 itd->itd.itd_next = sc->sc_flist[frindex]; 4014 if (itd->itd.itd_next == 0) 4015 /* FIXME: frindex table gets initialized to NULL 4016 * or EHCI_NULL? */ 4017 itd->itd.itd_next = EHCI_NULL; 4018 4019 usb_syncmem(&itd->dma, 4020 itd->offs + offsetof(ehci_itd_t, itd_next), 4021 sizeof(itd->itd.itd_next), 4022 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4023 4024 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4025 4026 usb_syncmem(&sc->sc_fldma, 4027 sizeof(ehci_link_t) * frindex, 4028 sizeof(ehci_link_t), 4029 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4030 4031 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4032 sc->sc_softitds[frindex] = itd; 4033 if (itd->u.frame_list.next != NULL) 4034 itd->u.frame_list.next->u.frame_list.prev = itd; 4035 itd->slot = frindex; 4036 itd->u.frame_list.prev = NULL; 4037 4038 frindex += i; 4039 if (frindex >= sc->sc_flsize) 4040 frindex -= sc->sc_flsize; 4041 4042 itd = itd->xfer_next; 4043 } 4044 4045 epipe->u.isoc.cur_xfers++; 4046 epipe->u.isoc.next_frame = frindex; 4047 4048 exfer->itdstart = start; 4049 exfer->itdend = stop; 4050 exfer->sqtdstart = NULL; 4051 exfer->sqtdstart = NULL; 4052 4053 mutex_enter(&sc->sc_intrhead_lock); 4054 ehci_add_intr_list(sc, exfer); 4055 mutex_exit(&sc->sc_intrhead_lock); 4056 xfer->status = USBD_IN_PROGRESS; 4057 xfer->done = 0; 4058 splx(s); 4059 4060 if (sc->sc_bus.use_polling) { 4061 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4062 ehci_waitintr(sc, xfer); 4063 } 4064 4065 return USBD_IN_PROGRESS; 4066 } 4067 4068 Static void 4069 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4070 { 4071 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4072 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4073 } 4074 4075 Static void 4076 ehci_device_isoc_close(usbd_pipe_handle pipe) 4077 { 4078 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4079 } 4080 4081 Static void 4082 ehci_device_isoc_done(usbd_xfer_handle xfer) 4083 { 4084 struct ehci_xfer *exfer; 4085 ehci_softc_t *sc; 4086 struct ehci_pipe *epipe; 4087 int s; 4088 4089 exfer = EXFER(xfer); 4090 sc = xfer->pipe->device->bus->hci_private; 4091 epipe = (struct ehci_pipe *) xfer->pipe; 4092 4093 s = splusb(); 4094 epipe->u.isoc.cur_xfers--; 4095 mutex_enter(&sc->sc_intrhead_lock); 4096 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4097 ehci_del_intr_list(sc, exfer); 4098 ehci_rem_free_itd_chain(sc, exfer); 4099 } 4100 mutex_exit(&sc->sc_intrhead_lock); 4101 splx(s); 4102 4103 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4104 BUS_DMASYNC_POSTREAD); 4105 4106 } 4107
Indexes created Tue Sep 23 22:09:46 GMT 2025