ehci.c revision 1.175
1 /* $NetBSD: ehci.c,v 1.175 2011/05/27 17:19:18 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum and 9 * Jeremy Morse (jeremy.morse (at) gmail.com). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 35 * 36 * The EHCI 1.0 spec can be found at 37 * http://www.intel.com/technology/usb/spec.htm 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/ 40 * 41 */ 42 43 /* 44 * TODO: 45 * 1) hold off explorations by companion controllers until ehci has started. 46 * 47 * 2) The hub driver needs to handle and schedule the transaction translator, 48 * to assign place in frame where different devices get to go. See chapter 49 * on hubs in USB 2.0 for details. 50 * 51 * 3) Command failures are not recovered correctly. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.175 2011/05/27 17:19:18 drochner Exp $"); 56 57 #include "ohci.h" 58 #include "uhci.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/kernel.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/select.h> 66 #include <sys/proc.h> 67 #include <sys/queue.h> 68 #include <sys/mutex.h> 69 #include <sys/bus.h> 70 71 #include <machine/endian.h> 72 73 #include <dev/usb/usb.h> 74 #include <dev/usb/usbdi.h> 75 #include <dev/usb/usbdivar.h> 76 #include <dev/usb/usb_mem.h> 77 #include <dev/usb/usb_quirks.h> 78 79 #include <dev/usb/ehcireg.h> 80 #include <dev/usb/ehcivar.h> 81 #include <dev/usb/usbroothub_subr.h> 82 83 #ifdef EHCI_DEBUG 84 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 85 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 86 int ehcidebug = 0; 87 #else 88 #define DPRINTF(x) 89 #define DPRINTFN(n,x) 90 #endif 91 92 struct ehci_pipe { 93 struct usbd_pipe pipe; 94 int nexttoggle; 95 96 ehci_soft_qh_t *sqh; 97 union { 98 ehci_soft_qtd_t *qtd; 99 /* ehci_soft_itd_t *itd; */ 100 } tail; 101 union { 102 /* Control pipe */ 103 struct { 104 usb_dma_t reqdma; 105 u_int length; 106 } ctl; 107 /* Interrupt pipe */ 108 struct { 109 u_int length; 110 } intr; 111 /* Bulk pipe */ 112 struct { 113 u_int length; 114 } bulk; 115 /* Iso pipe */ 116 struct { 117 u_int next_frame; 118 u_int cur_xfers; 119 } isoc; 120 } u; 121 }; 122 123 Static usbd_status ehci_open(usbd_pipe_handle); 124 Static void ehci_poll(struct usbd_bus *); 125 Static void ehci_softintr(void *); 126 Static int ehci_intr1(ehci_softc_t *); 127 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 128 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 129 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 130 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 131 Static void ehci_idone(struct ehci_xfer *); 132 Static void ehci_timeout(void *); 133 Static void ehci_timeout_task(void *); 134 Static void ehci_intrlist_timeout(void *); 135 136 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 137 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 138 139 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 140 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 141 142 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 143 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 144 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 145 Static void ehci_root_ctrl_close(usbd_pipe_handle); 146 Static void ehci_root_ctrl_done(usbd_xfer_handle); 147 148 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 149 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 150 Static void ehci_root_intr_abort(usbd_xfer_handle); 151 Static void ehci_root_intr_close(usbd_pipe_handle); 152 Static void ehci_root_intr_done(usbd_xfer_handle); 153 154 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 155 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 156 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 157 Static void ehci_device_ctrl_close(usbd_pipe_handle); 158 Static void ehci_device_ctrl_done(usbd_xfer_handle); 159 160 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 161 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 162 Static void ehci_device_bulk_abort(usbd_xfer_handle); 163 Static void ehci_device_bulk_close(usbd_pipe_handle); 164 Static void ehci_device_bulk_done(usbd_xfer_handle); 165 166 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 167 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 168 Static void ehci_device_intr_abort(usbd_xfer_handle); 169 Static void ehci_device_intr_close(usbd_pipe_handle); 170 Static void ehci_device_intr_done(usbd_xfer_handle); 171 172 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 173 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 174 Static void ehci_device_isoc_abort(usbd_xfer_handle); 175 Static void ehci_device_isoc_close(usbd_pipe_handle); 176 Static void ehci_device_isoc_done(usbd_xfer_handle); 177 178 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 179 Static void ehci_noop(usbd_pipe_handle pipe); 180 181 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 182 Static void ehci_disown(ehci_softc_t *, int, int); 183 184 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 185 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 186 187 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 188 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 189 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 190 ehci_softc_t *, int, int, usbd_xfer_handle, 191 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 192 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 193 ehci_soft_qtd_t *); 194 195 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 196 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 197 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 198 struct ehci_xfer *exfer); 199 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 200 usbd_status status); 201 202 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 203 204 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 205 int ival); 206 207 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 208 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 209 ehci_soft_qh_t *); 210 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 211 Static void ehci_sync_hc(ehci_softc_t *); 212 213 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 214 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 215 216 #ifdef EHCI_DEBUG 217 Static void ehci_dump_regs(ehci_softc_t *); 218 void ehci_dump(void); 219 Static ehci_softc_t *theehci; 220 Static void ehci_dump_link(ehci_link_t, int); 221 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 222 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 223 Static void ehci_dump_qtd(ehci_qtd_t *); 224 Static void ehci_dump_sqh(ehci_soft_qh_t *); 225 #if notyet 226 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 227 Static void ehci_dump_itd(struct ehci_soft_itd *); 228 #endif 229 #ifdef DIAGNOSTIC 230 Static void ehci_dump_exfer(struct ehci_xfer *); 231 #endif 232 #endif 233 234 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 235 236 #define EHCI_INTR_ENDPT 1 237 238 #define ehci_add_intr_list(sc, ex) \ 239 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 240 #define ehci_del_intr_list(sc, ex) \ 241 do { \ 242 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 243 (ex)->inext.tqe_prev = NULL; \ 244 } while (0) 245 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 246 247 Static const struct usbd_bus_methods ehci_bus_methods = { 248 ehci_open, 249 ehci_softintr, 250 ehci_poll, 251 ehci_allocm, 252 ehci_freem, 253 ehci_allocx, 254 ehci_freex, 255 }; 256 257 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 258 ehci_root_ctrl_transfer, 259 ehci_root_ctrl_start, 260 ehci_root_ctrl_abort, 261 ehci_root_ctrl_close, 262 ehci_noop, 263 ehci_root_ctrl_done, 264 }; 265 266 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 267 ehci_root_intr_transfer, 268 ehci_root_intr_start, 269 ehci_root_intr_abort, 270 ehci_root_intr_close, 271 ehci_noop, 272 ehci_root_intr_done, 273 }; 274 275 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 276 ehci_device_ctrl_transfer, 277 ehci_device_ctrl_start, 278 ehci_device_ctrl_abort, 279 ehci_device_ctrl_close, 280 ehci_noop, 281 ehci_device_ctrl_done, 282 }; 283 284 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 285 ehci_device_intr_transfer, 286 ehci_device_intr_start, 287 ehci_device_intr_abort, 288 ehci_device_intr_close, 289 ehci_device_clear_toggle, 290 ehci_device_intr_done, 291 }; 292 293 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 294 ehci_device_bulk_transfer, 295 ehci_device_bulk_start, 296 ehci_device_bulk_abort, 297 ehci_device_bulk_close, 298 ehci_device_clear_toggle, 299 ehci_device_bulk_done, 300 }; 301 302 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 303 ehci_device_isoc_transfer, 304 ehci_device_isoc_start, 305 ehci_device_isoc_abort, 306 ehci_device_isoc_close, 307 ehci_noop, 308 ehci_device_isoc_done, 309 }; 310 311 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 312 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 313 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 314 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 315 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 316 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 317 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 318 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 319 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 320 }; 321 322 usbd_status 323 ehci_init(ehci_softc_t *sc) 324 { 325 u_int32_t vers, sparams, cparams, hcr; 326 u_int i; 327 usbd_status err; 328 ehci_soft_qh_t *sqh; 329 u_int ncomp; 330 331 DPRINTF(("ehci_init: start\n")); 332 #ifdef EHCI_DEBUG 333 theehci = sc; 334 #endif 335 336 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 337 338 vers = EREAD2(sc, EHCI_HCIVERSION); 339 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 340 vers >> 8, vers & 0xff); 341 342 sparams = EREAD4(sc, EHCI_HCSPARAMS); 343 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 344 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 345 ncomp = EHCI_HCS_N_CC(sparams); 346 if (ncomp != sc->sc_ncomp) { 347 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 348 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 349 #if NOHCI == 0 || NUHCI == 0 350 aprint_error("%s: ohci or uhci probably not configured\n", 351 device_xname(sc->sc_dev)); 352 #endif 353 if (ncomp < sc->sc_ncomp) 354 sc->sc_ncomp = ncomp; 355 } 356 if (sc->sc_ncomp > 0) { 357 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 358 aprint_normal("%s: companion controller%s, %d port%s each:", 359 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 360 EHCI_HCS_N_PCC(sparams), 361 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 362 for (i = 0; i < sc->sc_ncomp; i++) 363 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 364 aprint_normal("\n"); 365 } 366 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 367 cparams = EREAD4(sc, EHCI_HCCPARAMS); 368 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 369 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 370 371 if (EHCI_HCC_64BIT(cparams)) { 372 /* MUST clear segment register if 64 bit capable. */ 373 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 374 } 375 376 sc->sc_bus.usbrev = USBREV_2_0; 377 378 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 379 USB_MEM_RESERVE); 380 381 /* Reset the controller */ 382 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 383 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 384 usb_delay_ms(&sc->sc_bus, 1); 385 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 386 for (i = 0; i < 100; i++) { 387 usb_delay_ms(&sc->sc_bus, 1); 388 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 389 if (!hcr) 390 break; 391 } 392 if (hcr) { 393 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 394 return (USBD_IOERROR); 395 } 396 if (sc->sc_vendor_init) 397 sc->sc_vendor_init(sc); 398 399 /* 400 * If we are doing embedded transaction translation function, force 401 * the controller to host mode. 402 */ 403 if (sc->sc_flags & EHCIF_ETTF) { 404 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 405 usbmode &= ~EHCI_USBMODE_CM; 406 usbmode |= EHCI_USBMODE_CM_HOST; 407 EWRITE4(sc, EHCI_USBMODE, usbmode); 408 } 409 410 /* XXX need proper intr scheduling */ 411 sc->sc_rand = 96; 412 413 /* frame list size at default, read back what we got and use that */ 414 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 415 case 0: sc->sc_flsize = 1024; break; 416 case 1: sc->sc_flsize = 512; break; 417 case 2: sc->sc_flsize = 256; break; 418 case 3: return (USBD_IOERROR); 419 } 420 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 421 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 422 if (err) 423 return (err); 424 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 425 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 426 427 for (i = 0; i < sc->sc_flsize; i++) { 428 sc->sc_flist[i] = EHCI_NULL; 429 } 430 431 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 432 433 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 434 M_USB, M_NOWAIT | M_ZERO); 435 if (sc->sc_softitds == NULL) 436 return ENOMEM; 437 LIST_INIT(&sc->sc_freeitds); 438 TAILQ_INIT(&sc->sc_intrhead); 439 mutex_init(&sc->sc_intrhead_lock, MUTEX_DEFAULT, IPL_USB); 440 441 /* Set up the bus struct. */ 442 sc->sc_bus.methods = &ehci_bus_methods; 443 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 444 445 sc->sc_eintrs = EHCI_NORMAL_INTRS; 446 447 /* 448 * Allocate the interrupt dummy QHs. These are arranged to give poll 449 * intervals that are powers of 2 times 1ms. 450 */ 451 for (i = 0; i < EHCI_INTRQHS; i++) { 452 sqh = ehci_alloc_sqh(sc); 453 if (sqh == NULL) { 454 err = USBD_NOMEM; 455 goto bad1; 456 } 457 sc->sc_islots[i].sqh = sqh; 458 } 459 for (i = 0; i < EHCI_INTRQHS; i++) { 460 sqh = sc->sc_islots[i].sqh; 461 if (i == 0) { 462 /* The last (1ms) QH terminates. */ 463 sqh->qh.qh_link = EHCI_NULL; 464 sqh->next = NULL; 465 } else { 466 /* Otherwise the next QH has half the poll interval */ 467 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 468 sqh->qh.qh_link = htole32(sqh->next->physaddr | 469 EHCI_LINK_QH); 470 } 471 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 472 sqh->qh.qh_curqtd = EHCI_NULL; 473 sqh->next = NULL; 474 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 475 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 476 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 477 sqh->sqtd = NULL; 478 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 479 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 480 } 481 /* Point the frame list at the last level (128ms). */ 482 for (i = 0; i < sc->sc_flsize; i++) { 483 int j; 484 485 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 486 revbits[i & (EHCI_MAX_POLLRATE-1)]; 487 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 488 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 489 i)].sqh->physaddr); 490 } 491 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 492 BUS_DMASYNC_PREWRITE); 493 494 /* Allocate dummy QH that starts the async list. */ 495 sqh = ehci_alloc_sqh(sc); 496 if (sqh == NULL) { 497 err = USBD_NOMEM; 498 goto bad1; 499 } 500 /* Fill the QH */ 501 sqh->qh.qh_endp = 502 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 503 sqh->qh.qh_link = 504 htole32(sqh->physaddr | EHCI_LINK_QH); 505 sqh->qh.qh_curqtd = EHCI_NULL; 506 sqh->next = NULL; 507 /* Fill the overlay qTD */ 508 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 509 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 510 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 511 sqh->sqtd = NULL; 512 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 513 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 514 #ifdef EHCI_DEBUG 515 if (ehcidebug) { 516 ehci_dump_sqh(sqh); 517 } 518 #endif 519 520 /* Point to async list */ 521 sc->sc_async_head = sqh; 522 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 523 524 callout_init(&(sc->sc_tmo_intrlist), 0); 525 526 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE); 527 528 /* Turn on controller */ 529 EOWRITE4(sc, EHCI_USBCMD, 530 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 531 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 532 EHCI_CMD_ASE | 533 EHCI_CMD_PSE | 534 EHCI_CMD_RS); 535 536 /* Take over port ownership */ 537 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 538 539 for (i = 0; i < 100; i++) { 540 usb_delay_ms(&sc->sc_bus, 1); 541 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 542 if (!hcr) 543 break; 544 } 545 if (hcr) { 546 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 547 return (USBD_IOERROR); 548 } 549 550 /* Enable interrupts */ 551 DPRINTFN(1,("ehci_init: enabling\n")); 552 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 553 554 return (USBD_NORMAL_COMPLETION); 555 556 #if 0 557 bad2: 558 ehci_free_sqh(sc, sc->sc_async_head); 559 #endif 560 bad1: 561 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 562 return (err); 563 } 564 565 int 566 ehci_intr(void *v) 567 { 568 ehci_softc_t *sc = v; 569 570 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 571 return (0); 572 573 /* If we get an interrupt while polling, then just ignore it. */ 574 if (sc->sc_bus.use_polling) { 575 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 576 577 if (intrs) 578 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 579 #ifdef DIAGNOSTIC 580 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 581 #endif 582 return (0); 583 } 584 585 return (ehci_intr1(sc)); 586 } 587 588 Static int 589 ehci_intr1(ehci_softc_t *sc) 590 { 591 u_int32_t intrs, eintrs; 592 593 DPRINTFN(20,("ehci_intr1: enter\n")); 594 595 /* In case the interrupt occurs before initialization has completed. */ 596 if (sc == NULL) { 597 #ifdef DIAGNOSTIC 598 printf("ehci_intr1: sc == NULL\n"); 599 #endif 600 return (0); 601 } 602 603 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 604 if (!intrs) 605 return (0); 606 607 eintrs = intrs & sc->sc_eintrs; 608 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 609 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 610 (u_int)eintrs)); 611 if (!eintrs) 612 return (0); 613 614 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 615 sc->sc_bus.intr_context++; 616 sc->sc_bus.no_intrs++; 617 if (eintrs & EHCI_STS_IAA) { 618 DPRINTF(("ehci_intr1: door bell\n")); 619 wakeup(&sc->sc_async_head); 620 eintrs &= ~EHCI_STS_IAA; 621 } 622 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 623 DPRINTFN(5,("ehci_intr1: %s %s\n", 624 eintrs & EHCI_STS_INT ? "INT" : "", 625 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 626 usb_schedsoftintr(&sc->sc_bus); 627 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 628 } 629 if (eintrs & EHCI_STS_HSE) { 630 printf("%s: unrecoverable error, controller halted\n", 631 device_xname(sc->sc_dev)); 632 /* XXX what else */ 633 } 634 if (eintrs & EHCI_STS_PCD) { 635 ehci_pcd(sc, sc->sc_intrxfer); 636 eintrs &= ~EHCI_STS_PCD; 637 } 638 639 sc->sc_bus.intr_context--; 640 641 if (eintrs != 0) { 642 /* Block unprocessed interrupts. */ 643 sc->sc_eintrs &= ~eintrs; 644 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 645 printf("%s: blocking intrs 0x%x\n", 646 device_xname(sc->sc_dev), eintrs); 647 } 648 649 return (1); 650 } 651 652 653 Static void 654 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 655 { 656 usbd_pipe_handle pipe; 657 u_char *p; 658 int i, m; 659 660 if (xfer == NULL) { 661 /* Just ignore the change. */ 662 return; 663 } 664 665 pipe = xfer->pipe; 666 667 p = KERNADDR(&xfer->dmabuf, 0); 668 m = min(sc->sc_noport, xfer->length * 8 - 1); 669 memset(p, 0, xfer->length); 670 for (i = 1; i <= m; i++) { 671 /* Pick out CHANGE bits from the status reg. */ 672 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 673 p[i/8] |= 1 << (i%8); 674 } 675 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 676 xfer->actlen = xfer->length; 677 xfer->status = USBD_NORMAL_COMPLETION; 678 679 usb_transfer_complete(xfer); 680 } 681 682 Static void 683 ehci_softintr(void *v) 684 { 685 struct usbd_bus *bus = v; 686 ehci_softc_t *sc = bus->hci_private; 687 struct ehci_xfer *ex, *nextex; 688 689 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 690 sc->sc_bus.intr_context)); 691 692 sc->sc_bus.intr_context++; 693 694 /* 695 * The only explanation I can think of for why EHCI is as brain dead 696 * as UHCI interrupt-wise is that Intel was involved in both. 697 * An interrupt just tells us that something is done, we have no 698 * clue what, so we need to scan through all active transfers. :-( 699 */ 700 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 701 nextex = TAILQ_NEXT(ex, inext); 702 ehci_check_intr(sc, ex); 703 } 704 705 /* Schedule a callout to catch any dropped transactions. */ 706 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 707 !TAILQ_EMPTY(&sc->sc_intrhead)) 708 callout_reset(&(sc->sc_tmo_intrlist), 709 (hz), (ehci_intrlist_timeout), (sc)); 710 711 #ifdef USB_USE_SOFTINTR 712 if (sc->sc_softwake) { 713 sc->sc_softwake = 0; 714 wakeup(&sc->sc_softwake); 715 } 716 #endif /* USB_USE_SOFTINTR */ 717 718 sc->sc_bus.intr_context--; 719 } 720 721 /* Check for an interrupt. */ 722 Static void 723 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 724 { 725 int attr; 726 727 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 728 729 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 730 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 731 ehci_check_itd_intr(sc, ex); 732 else 733 ehci_check_qh_intr(sc, ex); 734 735 return; 736 } 737 738 Static void 739 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 740 { 741 ehci_soft_qtd_t *sqtd, *lsqtd; 742 __uint32_t status; 743 744 if (ex->sqtdstart == NULL) { 745 printf("ehci_check_qh_intr: not valid sqtd\n"); 746 return; 747 } 748 749 lsqtd = ex->sqtdend; 750 #ifdef DIAGNOSTIC 751 if (lsqtd == NULL) { 752 printf("ehci_check_qh_intr: lsqtd==0\n"); 753 return; 754 } 755 #endif 756 /* 757 * If the last TD is still active we need to check whether there 758 * is a an error somewhere in the middle, or whether there was a 759 * short packet (SPD and not ACTIVE). 760 */ 761 usb_syncmem(&lsqtd->dma, 762 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 763 sizeof(lsqtd->qtd.qtd_status), 764 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 765 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 766 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 767 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 768 usb_syncmem(&sqtd->dma, 769 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 770 sizeof(sqtd->qtd.qtd_status), 771 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 772 status = le32toh(sqtd->qtd.qtd_status); 773 usb_syncmem(&sqtd->dma, 774 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 775 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 776 /* If there's an active QTD the xfer isn't done. */ 777 if (status & EHCI_QTD_ACTIVE) 778 break; 779 /* Any kind of error makes the xfer done. */ 780 if (status & EHCI_QTD_HALTED) 781 goto done; 782 /* We want short packets, and it is short: it's done */ 783 if (EHCI_QTD_GET_BYTES(status) != 0) 784 goto done; 785 } 786 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 787 ex, ex->sqtdstart)); 788 usb_syncmem(&lsqtd->dma, 789 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 790 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 791 return; 792 } 793 done: 794 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 795 callout_stop(&ex->xfer.timeout_handle); 796 ehci_idone(ex); 797 } 798 799 Static void 800 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 801 ehci_soft_itd_t *itd; 802 int i; 803 804 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 805 return; 806 807 if (ex->itdstart == NULL) { 808 printf("ehci_check_itd_intr: not valid itd\n"); 809 return; 810 } 811 812 itd = ex->itdend; 813 #ifdef DIAGNOSTIC 814 if (itd == NULL) { 815 printf("ehci_check_itd_intr: itdend == 0\n"); 816 return; 817 } 818 #endif 819 820 /* 821 * check no active transfers in last itd, meaning we're finished 822 */ 823 824 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 825 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 826 BUS_DMASYNC_POSTREAD); 827 828 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 829 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 830 break; 831 } 832 833 if (i == EHCI_ITD_NUFRAMES) { 834 goto done; /* All 8 descriptors inactive, it's done */ 835 } 836 837 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 838 ex->itdstart)); 839 return; 840 done: 841 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 842 callout_stop(&ex->xfer.timeout_handle); 843 ehci_idone(ex); 844 } 845 846 Static void 847 ehci_idone(struct ehci_xfer *ex) 848 { 849 usbd_xfer_handle xfer = &ex->xfer; 850 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 851 ehci_soft_qtd_t *sqtd, *lsqtd; 852 u_int32_t status = 0, nstatus = 0; 853 int actlen; 854 855 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 856 #ifdef DIAGNOSTIC 857 { 858 int s = splhigh(); 859 if (ex->isdone) { 860 splx(s); 861 #ifdef EHCI_DEBUG 862 printf("ehci_idone: ex is done!\n "); 863 ehci_dump_exfer(ex); 864 #else 865 printf("ehci_idone: ex=%p is done!\n", ex); 866 #endif 867 return; 868 } 869 ex->isdone = 1; 870 splx(s); 871 } 872 #endif 873 if (xfer->status == USBD_CANCELLED || 874 xfer->status == USBD_TIMEOUT) { 875 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 876 return; 877 } 878 879 #ifdef EHCI_DEBUG 880 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 881 if (ehcidebug > 10) 882 ehci_dump_sqtds(ex->sqtdstart); 883 #endif 884 885 /* The transfer is done, compute actual length and status. */ 886 887 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 888 == UE_ISOCHRONOUS) { 889 /* Isoc transfer */ 890 struct ehci_soft_itd *itd; 891 int i, nframes, len, uframes; 892 893 nframes = 0; 894 actlen = 0; 895 896 i = xfer->pipe->endpoint->edesc->bInterval; 897 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 898 899 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 900 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 901 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 902 BUS_DMASYNC_POSTREAD); 903 904 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 905 /* XXX - driver didn't fill in the frame full 906 * of uframes. This leads to scheduling 907 * inefficiencies, but working around 908 * this doubles complexity of tracking 909 * an xfer. 910 */ 911 if (nframes >= xfer->nframes) 912 break; 913 914 status = le32toh(itd->itd.itd_ctl[i]); 915 len = EHCI_ITD_GET_LEN(status); 916 if (EHCI_ITD_GET_STATUS(status) != 0) 917 len = 0; /*No valid data on error*/ 918 919 xfer->frlengths[nframes++] = len; 920 actlen += len; 921 } 922 923 if (nframes >= xfer->nframes) 924 break; 925 } 926 927 xfer->actlen = actlen; 928 xfer->status = USBD_NORMAL_COMPLETION; 929 goto end; 930 } 931 932 /* Continue processing xfers using queue heads */ 933 934 lsqtd = ex->sqtdend; 935 actlen = 0; 936 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 937 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 938 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 939 nstatus = le32toh(sqtd->qtd.qtd_status); 940 if (nstatus & EHCI_QTD_ACTIVE) 941 break; 942 943 status = nstatus; 944 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 945 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 946 } 947 948 949 /* 950 * If there are left over TDs we need to update the toggle. 951 * The default pipe doesn't need it since control transfers 952 * start the toggle at 0 every time. 953 * For a short transfer we need to update the toggle for the missing 954 * packets within the qTD. 955 */ 956 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 957 xfer->pipe->device->default_pipe != xfer->pipe) { 958 DPRINTFN(2, ("ehci_idone: need toggle update " 959 "status=%08x nstatus=%08x\n", status, nstatus)); 960 #if 0 961 ehci_dump_sqh(epipe->sqh); 962 ehci_dump_sqtds(ex->sqtdstart); 963 #endif 964 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 965 } 966 967 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 968 xfer->length, actlen, status)); 969 xfer->actlen = actlen; 970 if (status & EHCI_QTD_HALTED) { 971 #ifdef EHCI_DEBUG 972 char sbuf[128]; 973 974 snprintb(sbuf, sizeof(sbuf), 975 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 976 (u_int32_t)status); 977 978 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 979 "status 0x%s\n", 980 xfer->pipe->device->address, 981 xfer->pipe->endpoint->edesc->bEndpointAddress, 982 sbuf)); 983 if (ehcidebug > 2) { 984 ehci_dump_sqh(epipe->sqh); 985 ehci_dump_sqtds(ex->sqtdstart); 986 } 987 #endif 988 /* low&full speed has an extra error flag */ 989 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 990 EHCI_QH_SPEED_HIGH) 991 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 992 else 993 status &= EHCI_QTD_STATERRS; 994 if (status == 0) /* no other errors means a stall */ { 995 xfer->status = USBD_STALLED; 996 } else { 997 xfer->status = USBD_IOERROR; /* more info XXX */ 998 } 999 /* XXX need to reset TT on missed microframe */ 1000 if (status & EHCI_QTD_MISSEDMICRO) { 1001 ehci_softc_t *sc = 1002 xfer->pipe->device->bus->hci_private; 1003 1004 printf("%s: missed microframe, TT reset not " 1005 "implemented, hub might be inoperational\n", 1006 device_xname(sc->sc_dev)); 1007 } 1008 } else { 1009 xfer->status = USBD_NORMAL_COMPLETION; 1010 } 1011 1012 end: 1013 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1014 * during this call, before methods->done is called: dma sync required 1015 * beforehand? */ 1016 usb_transfer_complete(xfer); 1017 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1018 } 1019 1020 /* 1021 * Wait here until controller claims to have an interrupt. 1022 * Then call ehci_intr and return. Use timeout to avoid waiting 1023 * too long. 1024 */ 1025 Static void 1026 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1027 { 1028 int timo; 1029 u_int32_t intrs; 1030 1031 xfer->status = USBD_IN_PROGRESS; 1032 for (timo = xfer->timeout; timo >= 0; timo--) { 1033 usb_delay_ms(&sc->sc_bus, 1); 1034 if (sc->sc_dying) 1035 break; 1036 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1037 sc->sc_eintrs; 1038 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1039 #ifdef EHCI_DEBUG 1040 if (ehcidebug > 15) 1041 ehci_dump_regs(sc); 1042 #endif 1043 if (intrs) { 1044 ehci_intr1(sc); 1045 if (xfer->status != USBD_IN_PROGRESS) 1046 return; 1047 } 1048 } 1049 1050 /* Timeout */ 1051 DPRINTF(("ehci_waitintr: timeout\n")); 1052 xfer->status = USBD_TIMEOUT; 1053 usb_transfer_complete(xfer); 1054 /* XXX should free TD */ 1055 } 1056 1057 Static void 1058 ehci_poll(struct usbd_bus *bus) 1059 { 1060 ehci_softc_t *sc = bus->hci_private; 1061 #ifdef EHCI_DEBUG 1062 static int last; 1063 int new; 1064 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1065 if (new != last) { 1066 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1067 last = new; 1068 } 1069 #endif 1070 1071 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1072 ehci_intr1(sc); 1073 } 1074 1075 void 1076 ehci_childdet(device_t self, device_t child) 1077 { 1078 struct ehci_softc *sc = device_private(self); 1079 1080 KASSERT(sc->sc_child == child); 1081 sc->sc_child = NULL; 1082 } 1083 1084 int 1085 ehci_detach(struct ehci_softc *sc, int flags) 1086 { 1087 int rv = 0; 1088 1089 if (sc->sc_child != NULL) 1090 rv = config_detach(sc->sc_child, flags); 1091 1092 if (rv != 0) 1093 return (rv); 1094 1095 callout_stop(&sc->sc_tmo_intrlist); 1096 1097 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1098 1099 /* XXX free other data structures XXX */ 1100 mutex_destroy(&sc->sc_doorbell_lock); 1101 mutex_destroy(&sc->sc_intrhead_lock); 1102 1103 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1104 1105 return (rv); 1106 } 1107 1108 1109 int 1110 ehci_activate(device_t self, enum devact act) 1111 { 1112 struct ehci_softc *sc = device_private(self); 1113 1114 switch (act) { 1115 case DVACT_DEACTIVATE: 1116 sc->sc_dying = 1; 1117 return 0; 1118 default: 1119 return EOPNOTSUPP; 1120 } 1121 } 1122 1123 /* 1124 * Handle suspend/resume. 1125 * 1126 * We need to switch to polling mode here, because this routine is 1127 * called from an interrupt context. This is all right since we 1128 * are almost suspended anyway. 1129 * 1130 * Note that this power handler isn't to be registered directly; the 1131 * bus glue needs to call out to it. 1132 */ 1133 bool 1134 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1135 { 1136 ehci_softc_t *sc = device_private(dv); 1137 int i, s; 1138 uint32_t cmd, hcr; 1139 1140 s = splhardusb(); 1141 1142 sc->sc_bus.use_polling++; 1143 1144 for (i = 1; i <= sc->sc_noport; i++) { 1145 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1146 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1147 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1148 } 1149 1150 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1151 1152 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1153 EOWRITE4(sc, EHCI_USBCMD, cmd); 1154 1155 for (i = 0; i < 100; i++) { 1156 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1157 if (hcr == 0) 1158 break; 1159 1160 usb_delay_ms(&sc->sc_bus, 1); 1161 } 1162 if (hcr != 0) 1163 printf("%s: reset timeout\n", device_xname(dv)); 1164 1165 cmd &= ~EHCI_CMD_RS; 1166 EOWRITE4(sc, EHCI_USBCMD, cmd); 1167 1168 for (i = 0; i < 100; i++) { 1169 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1170 if (hcr == EHCI_STS_HCH) 1171 break; 1172 1173 usb_delay_ms(&sc->sc_bus, 1); 1174 } 1175 if (hcr != EHCI_STS_HCH) 1176 printf("%s: config timeout\n", device_xname(dv)); 1177 1178 sc->sc_bus.use_polling--; 1179 splx(s); 1180 1181 return true; 1182 } 1183 1184 bool 1185 ehci_resume(device_t dv, const pmf_qual_t *qual) 1186 { 1187 ehci_softc_t *sc = device_private(dv); 1188 int i; 1189 uint32_t cmd, hcr; 1190 1191 /* restore things in case the bios sucks */ 1192 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1193 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1194 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1195 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1196 1197 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1198 1199 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1200 1201 hcr = 0; 1202 for (i = 1; i <= sc->sc_noport; i++) { 1203 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1204 if ((cmd & EHCI_PS_PO) == 0 && 1205 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1206 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1207 hcr = 1; 1208 } 1209 } 1210 1211 if (hcr) { 1212 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1213 1214 for (i = 1; i <= sc->sc_noport; i++) { 1215 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1216 if ((cmd & EHCI_PS_PO) == 0 && 1217 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1218 EOWRITE4(sc, EHCI_PORTSC(i), 1219 cmd & ~EHCI_PS_FPR); 1220 } 1221 } 1222 1223 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1224 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1225 1226 for (i = 0; i < 100; i++) { 1227 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1228 if (hcr != EHCI_STS_HCH) 1229 break; 1230 1231 usb_delay_ms(&sc->sc_bus, 1); 1232 } 1233 if (hcr == EHCI_STS_HCH) 1234 printf("%s: config timeout\n", device_xname(dv)); 1235 1236 return true; 1237 } 1238 1239 /* 1240 * Shut down the controller when the system is going down. 1241 */ 1242 bool 1243 ehci_shutdown(device_t self, int flags) 1244 { 1245 ehci_softc_t *sc = device_private(self); 1246 1247 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1248 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1249 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1250 return true; 1251 } 1252 1253 Static usbd_status 1254 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1255 { 1256 struct ehci_softc *sc = bus->hci_private; 1257 usbd_status err; 1258 1259 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1260 if (err == USBD_NOMEM) 1261 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1262 #ifdef EHCI_DEBUG 1263 if (err) 1264 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1265 #endif 1266 return (err); 1267 } 1268 1269 Static void 1270 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1271 { 1272 struct ehci_softc *sc = bus->hci_private; 1273 1274 if (dma->block->flags & USB_DMA_RESERVE) { 1275 usb_reserve_freem(&sc->sc_dma_reserve, 1276 dma); 1277 return; 1278 } 1279 usb_freemem(&sc->sc_bus, dma); 1280 } 1281 1282 Static usbd_xfer_handle 1283 ehci_allocx(struct usbd_bus *bus) 1284 { 1285 struct ehci_softc *sc = bus->hci_private; 1286 usbd_xfer_handle xfer; 1287 1288 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1289 if (xfer != NULL) { 1290 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1291 #ifdef DIAGNOSTIC 1292 if (xfer->busy_free != XFER_FREE) { 1293 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1294 xfer->busy_free); 1295 } 1296 #endif 1297 } else { 1298 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1299 } 1300 if (xfer != NULL) { 1301 memset(xfer, 0, sizeof(struct ehci_xfer)); 1302 #ifdef DIAGNOSTIC 1303 EXFER(xfer)->isdone = 1; 1304 xfer->busy_free = XFER_BUSY; 1305 #endif 1306 } 1307 return (xfer); 1308 } 1309 1310 Static void 1311 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1312 { 1313 struct ehci_softc *sc = bus->hci_private; 1314 1315 #ifdef DIAGNOSTIC 1316 if (xfer->busy_free != XFER_BUSY) { 1317 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1318 xfer->busy_free); 1319 } 1320 xfer->busy_free = XFER_FREE; 1321 if (!EXFER(xfer)->isdone) { 1322 printf("ehci_freex: !isdone\n"); 1323 } 1324 #endif 1325 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1326 } 1327 1328 Static void 1329 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1330 { 1331 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1332 1333 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1334 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1335 #ifdef EHCI_DEBUG 1336 if (ehcidebug) 1337 usbd_dump_pipe(pipe); 1338 #endif 1339 epipe->nexttoggle = 0; 1340 } 1341 1342 Static void 1343 ehci_noop(usbd_pipe_handle pipe) 1344 { 1345 } 1346 1347 #ifdef EHCI_DEBUG 1348 Static void 1349 ehci_dump_regs(ehci_softc_t *sc) 1350 { 1351 int i; 1352 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1353 EOREAD4(sc, EHCI_USBCMD), 1354 EOREAD4(sc, EHCI_USBSTS), 1355 EOREAD4(sc, EHCI_USBINTR)); 1356 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1357 EOREAD4(sc, EHCI_FRINDEX), 1358 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1359 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1360 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1361 for (i = 1; i <= sc->sc_noport; i++) 1362 printf("port %d status=0x%08x\n", i, 1363 EOREAD4(sc, EHCI_PORTSC(i))); 1364 } 1365 1366 /* 1367 * Unused function - this is meant to be called from a kernel 1368 * debugger. 1369 */ 1370 void 1371 ehci_dump(void) 1372 { 1373 ehci_dump_regs(theehci); 1374 } 1375 1376 Static void 1377 ehci_dump_link(ehci_link_t link, int type) 1378 { 1379 link = le32toh(link); 1380 printf("0x%08x", link); 1381 if (link & EHCI_LINK_TERMINATE) 1382 printf("<T>"); 1383 else { 1384 printf("<"); 1385 if (type) { 1386 switch (EHCI_LINK_TYPE(link)) { 1387 case EHCI_LINK_ITD: printf("ITD"); break; 1388 case EHCI_LINK_QH: printf("QH"); break; 1389 case EHCI_LINK_SITD: printf("SITD"); break; 1390 case EHCI_LINK_FSTN: printf("FSTN"); break; 1391 } 1392 } 1393 printf(">"); 1394 } 1395 } 1396 1397 Static void 1398 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1399 { 1400 int i; 1401 u_int32_t stop; 1402 1403 stop = 0; 1404 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1405 ehci_dump_sqtd(sqtd); 1406 usb_syncmem(&sqtd->dma, 1407 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1408 sizeof(sqtd->qtd), 1409 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1410 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1411 usb_syncmem(&sqtd->dma, 1412 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1413 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1414 } 1415 if (sqtd) 1416 printf("dump aborted, too many TDs\n"); 1417 } 1418 1419 Static void 1420 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1421 { 1422 usb_syncmem(&sqtd->dma, sqtd->offs, 1423 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1424 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1425 ehci_dump_qtd(&sqtd->qtd); 1426 usb_syncmem(&sqtd->dma, sqtd->offs, 1427 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1428 } 1429 1430 Static void 1431 ehci_dump_qtd(ehci_qtd_t *qtd) 1432 { 1433 u_int32_t s; 1434 char sbuf[128]; 1435 1436 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1437 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1438 printf("\n"); 1439 s = le32toh(qtd->qtd_status); 1440 snprintb(sbuf, sizeof(sbuf), 1441 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1442 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1443 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1444 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1445 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1446 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1447 EHCI_QTD_GET_PID(s), sbuf); 1448 for (s = 0; s < 5; s++) 1449 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1450 } 1451 1452 Static void 1453 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1454 { 1455 ehci_qh_t *qh = &sqh->qh; 1456 u_int32_t endp, endphub; 1457 1458 usb_syncmem(&sqh->dma, sqh->offs, 1459 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1460 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1461 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1462 endp = le32toh(qh->qh_endp); 1463 printf(" endp=0x%08x\n", endp); 1464 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1465 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1466 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1467 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1468 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1469 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1470 EHCI_QH_GET_NRL(endp)); 1471 endphub = le32toh(qh->qh_endphub); 1472 printf(" endphub=0x%08x\n", endphub); 1473 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1474 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1475 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1476 EHCI_QH_GET_MULT(endphub)); 1477 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1478 printf("Overlay qTD:\n"); 1479 ehci_dump_qtd(&qh->qh_qtd); 1480 usb_syncmem(&sqh->dma, sqh->offs, 1481 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1482 } 1483 1484 #if notyet 1485 Static void 1486 ehci_dump_itd(struct ehci_soft_itd *itd) 1487 { 1488 ehci_isoc_trans_t t; 1489 ehci_isoc_bufr_ptr_t b, b2, b3; 1490 int i; 1491 1492 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1493 1494 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1495 t = le32toh(itd->itd.itd_ctl[i]); 1496 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1497 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1498 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1499 EHCI_ITD_GET_OFFS(t)); 1500 } 1501 printf("ITDbufr: "); 1502 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1503 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1504 1505 b = le32toh(itd->itd.itd_bufr[0]); 1506 b2 = le32toh(itd->itd.itd_bufr[1]); 1507 b3 = le32toh(itd->itd.itd_bufr[2]); 1508 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1509 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1510 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1511 } 1512 1513 Static void 1514 ehci_dump_sitd(struct ehci_soft_itd *itd) 1515 { 1516 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1517 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1518 itd->xfer_next, itd->physaddr, itd->slot); 1519 } 1520 #endif 1521 1522 #ifdef DIAGNOSTIC 1523 Static void 1524 ehci_dump_exfer(struct ehci_xfer *ex) 1525 { 1526 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1527 } 1528 #endif 1529 #endif 1530 1531 Static usbd_status 1532 ehci_open(usbd_pipe_handle pipe) 1533 { 1534 usbd_device_handle dev = pipe->device; 1535 ehci_softc_t *sc = dev->bus->hci_private; 1536 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1537 u_int8_t addr = dev->address; 1538 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1539 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1540 ehci_soft_qh_t *sqh; 1541 usbd_status err; 1542 int s; 1543 int ival, speed, naks; 1544 int hshubaddr, hshubport; 1545 1546 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1547 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1548 1549 if (dev->myhsport) { 1550 /* 1551 * When directly attached FS/LS device while doing embedded 1552 * transaction translations and we are the hub, set the hub 1553 * adddress to 0 (us). 1554 */ 1555 if (!(sc->sc_flags & EHCIF_ETTF) 1556 || (dev->myhsport->parent->address != sc->sc_addr)) { 1557 hshubaddr = dev->myhsport->parent->address; 1558 } else { 1559 hshubaddr = 0; 1560 } 1561 hshubport = dev->myhsport->portno; 1562 } else { 1563 hshubaddr = 0; 1564 hshubport = 0; 1565 } 1566 1567 if (sc->sc_dying) 1568 return (USBD_IOERROR); 1569 1570 /* toggle state needed for bulk endpoints */ 1571 epipe->nexttoggle = pipe->endpoint->datatoggle; 1572 1573 if (addr == sc->sc_addr) { 1574 switch (ed->bEndpointAddress) { 1575 case USB_CONTROL_ENDPOINT: 1576 pipe->methods = &ehci_root_ctrl_methods; 1577 break; 1578 case UE_DIR_IN | EHCI_INTR_ENDPT: 1579 pipe->methods = &ehci_root_intr_methods; 1580 break; 1581 default: 1582 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1583 ed->bEndpointAddress)); 1584 return (USBD_INVAL); 1585 } 1586 return (USBD_NORMAL_COMPLETION); 1587 } 1588 1589 /* XXX All this stuff is only valid for async. */ 1590 switch (dev->speed) { 1591 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1592 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1593 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1594 default: panic("ehci_open: bad device speed %d", dev->speed); 1595 } 1596 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1597 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1598 "isoc endpoint.\n"); 1599 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1600 "attached to a USB2 hub, and transaction translations are " 1601 "not yet supported.\n"); 1602 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1603 "root hub instead.\n"); 1604 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1605 hshubaddr, hshubport)); 1606 return USBD_INVAL; 1607 } 1608 1609 /* 1610 * For interrupt transfer, nak throttling must be disabled, but for 1611 * the other transfer type, nak throttling should be enabled from the 1612 * veiwpoint that avoids the memory thrashing. 1613 */ 1614 naks = (xfertype == UE_INTERRUPT) ? 0 1615 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1616 1617 /* Allocate sqh for everything, save isoc xfers */ 1618 if (xfertype != UE_ISOCHRONOUS) { 1619 sqh = ehci_alloc_sqh(sc); 1620 if (sqh == NULL) 1621 return (USBD_NOMEM); 1622 /* qh_link filled when the QH is added */ 1623 sqh->qh.qh_endp = htole32( 1624 EHCI_QH_SET_ADDR(addr) | 1625 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1626 EHCI_QH_SET_EPS(speed) | 1627 EHCI_QH_DTC | 1628 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1629 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1630 EHCI_QH_CTL : 0) | 1631 EHCI_QH_SET_NRL(naks) 1632 ); 1633 sqh->qh.qh_endphub = htole32( 1634 EHCI_QH_SET_MULT(1) | 1635 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1636 ); 1637 if (speed != EHCI_QH_SPEED_HIGH) 1638 sqh->qh.qh_endphub |= htole32( 1639 EHCI_QH_SET_PORT(hshubport) | 1640 EHCI_QH_SET_HUBA(hshubaddr) | 1641 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1642 ); 1643 sqh->qh.qh_curqtd = EHCI_NULL; 1644 /* Fill the overlay qTD */ 1645 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1646 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1647 sqh->qh.qh_qtd.qtd_status = htole32(0); 1648 1649 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1650 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1651 epipe->sqh = sqh; 1652 } else { 1653 sqh = NULL; 1654 } /*xfertype == UE_ISOC*/ 1655 1656 switch (xfertype) { 1657 case UE_CONTROL: 1658 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1659 0, &epipe->u.ctl.reqdma); 1660 #ifdef EHCI_DEBUG 1661 if (err) 1662 printf("ehci_open: usb_allocmem()=%d\n", err); 1663 #endif 1664 if (err) 1665 goto bad; 1666 pipe->methods = &ehci_device_ctrl_methods; 1667 s = splusb(); 1668 ehci_add_qh(sqh, sc->sc_async_head); 1669 splx(s); 1670 break; 1671 case UE_BULK: 1672 pipe->methods = &ehci_device_bulk_methods; 1673 s = splusb(); 1674 ehci_add_qh(sqh, sc->sc_async_head); 1675 splx(s); 1676 break; 1677 case UE_INTERRUPT: 1678 pipe->methods = &ehci_device_intr_methods; 1679 ival = pipe->interval; 1680 if (ival == USBD_DEFAULT_INTERVAL) { 1681 if (speed == EHCI_QH_SPEED_HIGH) { 1682 if (ed->bInterval > 16) { 1683 /* 1684 * illegal with high-speed, but there 1685 * were documentation bugs in the spec, 1686 * so be generous 1687 */ 1688 ival = 256; 1689 } else 1690 ival = (1 << (ed->bInterval - 1)) / 8; 1691 } else 1692 ival = ed->bInterval; 1693 } 1694 err = ehci_device_setintr(sc, sqh, ival); 1695 if (err) 1696 goto bad; 1697 break; 1698 case UE_ISOCHRONOUS: 1699 pipe->methods = &ehci_device_isoc_methods; 1700 if (ed->bInterval == 0 || ed->bInterval > 16) { 1701 printf("ehci: opening pipe with invalid bInterval\n"); 1702 err = USBD_INVAL; 1703 goto bad; 1704 } 1705 if (UGETW(ed->wMaxPacketSize) == 0) { 1706 printf("ehci: zero length endpoint open request\n"); 1707 err = USBD_INVAL; 1708 goto bad; 1709 } 1710 epipe->u.isoc.next_frame = 0; 1711 epipe->u.isoc.cur_xfers = 0; 1712 break; 1713 default: 1714 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1715 err = USBD_INVAL; 1716 goto bad; 1717 } 1718 return (USBD_NORMAL_COMPLETION); 1719 1720 bad: 1721 if (sqh != NULL) 1722 ehci_free_sqh(sc, sqh); 1723 return (err); 1724 } 1725 1726 /* 1727 * Add an ED to the schedule. Called at splusb(). 1728 */ 1729 Static void 1730 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1731 { 1732 SPLUSBCHECK; 1733 1734 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1735 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1736 sqh->next = head->next; 1737 sqh->qh.qh_link = head->qh.qh_link; 1738 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1739 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1740 head->next = sqh; 1741 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1742 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1743 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1744 1745 #ifdef EHCI_DEBUG 1746 if (ehcidebug > 5) { 1747 printf("ehci_add_qh:\n"); 1748 ehci_dump_sqh(sqh); 1749 } 1750 #endif 1751 } 1752 1753 /* 1754 * Remove an ED from the schedule. Called at splusb(). 1755 */ 1756 Static void 1757 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1758 { 1759 ehci_soft_qh_t *p; 1760 1761 SPLUSBCHECK; 1762 /* XXX */ 1763 for (p = head; p != NULL && p->next != sqh; p = p->next) 1764 ; 1765 if (p == NULL) 1766 panic("ehci_rem_qh: ED not found"); 1767 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1768 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1769 p->next = sqh->next; 1770 p->qh.qh_link = sqh->qh.qh_link; 1771 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1772 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1773 1774 ehci_sync_hc(sc); 1775 } 1776 1777 Static void 1778 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1779 { 1780 int i; 1781 u_int32_t status; 1782 1783 /* Save toggle bit and ping status. */ 1784 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1785 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1786 status = sqh->qh.qh_qtd.qtd_status & 1787 htole32(EHCI_QTD_TOGGLE_MASK | 1788 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1789 /* Set HALTED to make hw leave it alone. */ 1790 sqh->qh.qh_qtd.qtd_status = 1791 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1792 usb_syncmem(&sqh->dma, 1793 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1794 sizeof(sqh->qh.qh_qtd.qtd_status), 1795 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1796 sqh->qh.qh_curqtd = 0; 1797 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1798 sqh->qh.qh_qtd.qtd_altnext = 0; 1799 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1800 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1801 sqh->sqtd = sqtd; 1802 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1803 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1804 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1805 sqh->qh.qh_qtd.qtd_status = status; 1806 usb_syncmem(&sqh->dma, 1807 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1808 sizeof(sqh->qh.qh_qtd.qtd_status), 1809 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1810 } 1811 1812 /* 1813 * Ensure that the HC has released all references to the QH. We do this 1814 * by asking for a Async Advance Doorbell interrupt and then we wait for 1815 * the interrupt. 1816 * To make this easier we first obtain exclusive use of the doorbell. 1817 */ 1818 Static void 1819 ehci_sync_hc(ehci_softc_t *sc) 1820 { 1821 int s, error; 1822 1823 if (sc->sc_dying) { 1824 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1825 return; 1826 } 1827 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1828 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */ 1829 s = splhardusb(); 1830 /* ask for doorbell */ 1831 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1832 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1833 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1834 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1835 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1836 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1837 splx(s); 1838 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */ 1839 #ifdef DIAGNOSTIC 1840 if (error) 1841 printf("ehci_sync_hc: tsleep() = %d\n", error); 1842 #endif 1843 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1844 } 1845 1846 /*Call at splusb*/ 1847 Static void 1848 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1849 { 1850 struct ehci_soft_itd *itd, *prev; 1851 1852 prev = NULL; 1853 1854 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1855 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1856 1857 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1858 prev = itd->u.frame_list.prev; 1859 /* Unlink itd from hardware chain, or frame array */ 1860 if (prev == NULL) { /* We're at the table head */ 1861 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1862 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1863 usb_syncmem(&sc->sc_fldma, 1864 sizeof(ehci_link_t) * itd->slot, 1865 sizeof(ehci_link_t), 1866 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1867 1868 if (itd->u.frame_list.next != NULL) 1869 itd->u.frame_list.next->u.frame_list.prev = NULL; 1870 } else { 1871 /* XXX this part is untested... */ 1872 prev->itd.itd_next = itd->itd.itd_next; 1873 usb_syncmem(&itd->dma, 1874 itd->offs + offsetof(ehci_itd_t, itd_next), 1875 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1876 1877 prev->u.frame_list.next = itd->u.frame_list.next; 1878 if (itd->u.frame_list.next != NULL) 1879 itd->u.frame_list.next->u.frame_list.prev = prev; 1880 } 1881 } 1882 1883 prev = NULL; 1884 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1885 if (prev != NULL) 1886 ehci_free_itd(sc, prev); 1887 prev = itd; 1888 } 1889 if (prev) 1890 ehci_free_itd(sc, prev); 1891 exfer->itdstart = NULL; 1892 exfer->itdend = NULL; 1893 } 1894 1895 /***********/ 1896 1897 /* 1898 * Data structures and routines to emulate the root hub. 1899 */ 1900 Static usb_device_descriptor_t ehci_devd = { 1901 USB_DEVICE_DESCRIPTOR_SIZE, 1902 UDESC_DEVICE, /* type */ 1903 {0x00, 0x02}, /* USB version */ 1904 UDCLASS_HUB, /* class */ 1905 UDSUBCLASS_HUB, /* subclass */ 1906 UDPROTO_HSHUBSTT, /* protocol */ 1907 64, /* max packet */ 1908 {0},{0},{0x00,0x01}, /* device id */ 1909 1,2,0, /* string indicies */ 1910 1 /* # of configurations */ 1911 }; 1912 1913 Static const usb_device_qualifier_t ehci_odevd = { 1914 USB_DEVICE_DESCRIPTOR_SIZE, 1915 UDESC_DEVICE_QUALIFIER, /* type */ 1916 {0x00, 0x02}, /* USB version */ 1917 UDCLASS_HUB, /* class */ 1918 UDSUBCLASS_HUB, /* subclass */ 1919 UDPROTO_FSHUB, /* protocol */ 1920 64, /* max packet */ 1921 1, /* # of configurations */ 1922 0 1923 }; 1924 1925 Static const usb_config_descriptor_t ehci_confd = { 1926 USB_CONFIG_DESCRIPTOR_SIZE, 1927 UDESC_CONFIG, 1928 {USB_CONFIG_DESCRIPTOR_SIZE + 1929 USB_INTERFACE_DESCRIPTOR_SIZE + 1930 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1931 1, 1932 1, 1933 0, 1934 UC_ATTR_MBO | UC_SELF_POWERED, 1935 0 /* max power */ 1936 }; 1937 1938 Static const usb_interface_descriptor_t ehci_ifcd = { 1939 USB_INTERFACE_DESCRIPTOR_SIZE, 1940 UDESC_INTERFACE, 1941 0, 1942 0, 1943 1, 1944 UICLASS_HUB, 1945 UISUBCLASS_HUB, 1946 UIPROTO_HSHUBSTT, 1947 0 1948 }; 1949 1950 Static const usb_endpoint_descriptor_t ehci_endpd = { 1951 USB_ENDPOINT_DESCRIPTOR_SIZE, 1952 UDESC_ENDPOINT, 1953 UE_DIR_IN | EHCI_INTR_ENDPT, 1954 UE_INTERRUPT, 1955 {8, 0}, /* max packet */ 1956 12 1957 }; 1958 1959 Static const usb_hub_descriptor_t ehci_hubd = { 1960 USB_HUB_DESCRIPTOR_SIZE, 1961 UDESC_HUB, 1962 0, 1963 {0,0}, 1964 0, 1965 0, 1966 {""}, 1967 {""}, 1968 }; 1969 1970 /* 1971 * Simulate a hardware hub by handling all the necessary requests. 1972 */ 1973 Static usbd_status 1974 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1975 { 1976 usbd_status err; 1977 1978 /* Insert last in queue. */ 1979 err = usb_insert_transfer(xfer); 1980 if (err) 1981 return (err); 1982 1983 /* Pipe isn't running, start first */ 1984 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1985 } 1986 1987 Static usbd_status 1988 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1989 { 1990 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1991 usb_device_request_t *req; 1992 void *buf = NULL; 1993 int port, i; 1994 int s, len, value, index, l, totlen = 0; 1995 usb_port_status_t ps; 1996 usb_hub_descriptor_t hubd; 1997 usbd_status err; 1998 u_int32_t v; 1999 2000 if (sc->sc_dying) 2001 return (USBD_IOERROR); 2002 2003 #ifdef DIAGNOSTIC 2004 if (!(xfer->rqflags & URQ_REQUEST)) 2005 /* XXX panic */ 2006 return (USBD_INVAL); 2007 #endif 2008 req = &xfer->request; 2009 2010 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2011 req->bmRequestType, req->bRequest)); 2012 2013 len = UGETW(req->wLength); 2014 value = UGETW(req->wValue); 2015 index = UGETW(req->wIndex); 2016 2017 if (len != 0) 2018 buf = KERNADDR(&xfer->dmabuf, 0); 2019 2020 #define C(x,y) ((x) | ((y) << 8)) 2021 switch(C(req->bRequest, req->bmRequestType)) { 2022 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2023 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2024 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2025 /* 2026 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2027 * for the integrated root hub. 2028 */ 2029 break; 2030 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2031 if (len > 0) { 2032 *(u_int8_t *)buf = sc->sc_conf; 2033 totlen = 1; 2034 } 2035 break; 2036 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2037 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2038 if (len == 0) 2039 break; 2040 switch(value >> 8) { 2041 case UDESC_DEVICE: 2042 if ((value & 0xff) != 0) { 2043 err = USBD_IOERROR; 2044 goto ret; 2045 } 2046 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2047 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2048 memcpy(buf, &ehci_devd, l); 2049 break; 2050 /* 2051 * We can't really operate at another speed, but the spec says 2052 * we need this descriptor. 2053 */ 2054 case UDESC_DEVICE_QUALIFIER: 2055 if ((value & 0xff) != 0) { 2056 err = USBD_IOERROR; 2057 goto ret; 2058 } 2059 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2060 memcpy(buf, &ehci_odevd, l); 2061 break; 2062 /* 2063 * We can't really operate at another speed, but the spec says 2064 * we need this descriptor. 2065 */ 2066 case UDESC_OTHER_SPEED_CONFIGURATION: 2067 case UDESC_CONFIG: 2068 if ((value & 0xff) != 0) { 2069 err = USBD_IOERROR; 2070 goto ret; 2071 } 2072 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2073 memcpy(buf, &ehci_confd, l); 2074 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2075 value >> 8; 2076 buf = (char *)buf + l; 2077 len -= l; 2078 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2079 totlen += l; 2080 memcpy(buf, &ehci_ifcd, l); 2081 buf = (char *)buf + l; 2082 len -= l; 2083 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2084 totlen += l; 2085 memcpy(buf, &ehci_endpd, l); 2086 break; 2087 case UDESC_STRING: 2088 #define sd ((usb_string_descriptor_t *)buf) 2089 switch (value & 0xff) { 2090 case 0: /* Language table */ 2091 totlen = usb_makelangtbl(sd, len); 2092 break; 2093 case 1: /* Vendor */ 2094 totlen = usb_makestrdesc(sd, len, 2095 sc->sc_vendor); 2096 break; 2097 case 2: /* Product */ 2098 totlen = usb_makestrdesc(sd, len, 2099 "EHCI root hub"); 2100 break; 2101 } 2102 #undef sd 2103 break; 2104 default: 2105 err = USBD_IOERROR; 2106 goto ret; 2107 } 2108 break; 2109 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2110 if (len > 0) { 2111 *(u_int8_t *)buf = 0; 2112 totlen = 1; 2113 } 2114 break; 2115 case C(UR_GET_STATUS, UT_READ_DEVICE): 2116 if (len > 1) { 2117 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2118 totlen = 2; 2119 } 2120 break; 2121 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2122 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2123 if (len > 1) { 2124 USETW(((usb_status_t *)buf)->wStatus, 0); 2125 totlen = 2; 2126 } 2127 break; 2128 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2129 if (value >= USB_MAX_DEVICES) { 2130 err = USBD_IOERROR; 2131 goto ret; 2132 } 2133 sc->sc_addr = value; 2134 break; 2135 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2136 if (value != 0 && value != 1) { 2137 err = USBD_IOERROR; 2138 goto ret; 2139 } 2140 sc->sc_conf = value; 2141 break; 2142 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2143 break; 2144 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2145 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2146 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2147 err = USBD_IOERROR; 2148 goto ret; 2149 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2150 break; 2151 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2152 break; 2153 /* Hub requests */ 2154 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2155 break; 2156 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2157 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2158 "port=%d feature=%d\n", 2159 index, value)); 2160 if (index < 1 || index > sc->sc_noport) { 2161 err = USBD_IOERROR; 2162 goto ret; 2163 } 2164 port = EHCI_PORTSC(index); 2165 v = EOREAD4(sc, port); 2166 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2167 v &= ~EHCI_PS_CLEAR; 2168 switch(value) { 2169 case UHF_PORT_ENABLE: 2170 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2171 break; 2172 case UHF_PORT_SUSPEND: 2173 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2174 break; 2175 v &= ~EHCI_PS_SUSP; 2176 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2177 /* see USB2 spec ch. 7.1.7.7 */ 2178 usb_delay_ms(&sc->sc_bus, 20); 2179 EOWRITE4(sc, port, v); 2180 usb_delay_ms(&sc->sc_bus, 2); 2181 #ifdef DEBUG 2182 v = EOREAD4(sc, port); 2183 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2184 printf("ehci: resume failed: %x\n", v); 2185 #endif 2186 break; 2187 case UHF_PORT_POWER: 2188 if (sc->sc_hasppc) 2189 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2190 break; 2191 case UHF_PORT_TEST: 2192 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2193 "%d\n", index)); 2194 break; 2195 case UHF_PORT_INDICATOR: 2196 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2197 "%d\n", index)); 2198 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2199 break; 2200 case UHF_C_PORT_CONNECTION: 2201 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2202 break; 2203 case UHF_C_PORT_ENABLE: 2204 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2205 break; 2206 case UHF_C_PORT_SUSPEND: 2207 /* how? */ 2208 break; 2209 case UHF_C_PORT_OVER_CURRENT: 2210 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2211 break; 2212 case UHF_C_PORT_RESET: 2213 sc->sc_isreset[index] = 0; 2214 break; 2215 default: 2216 err = USBD_IOERROR; 2217 goto ret; 2218 } 2219 #if 0 2220 switch(value) { 2221 case UHF_C_PORT_CONNECTION: 2222 case UHF_C_PORT_ENABLE: 2223 case UHF_C_PORT_SUSPEND: 2224 case UHF_C_PORT_OVER_CURRENT: 2225 case UHF_C_PORT_RESET: 2226 default: 2227 break; 2228 } 2229 #endif 2230 break; 2231 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2232 if (len == 0) 2233 break; 2234 if ((value & 0xff) != 0) { 2235 err = USBD_IOERROR; 2236 goto ret; 2237 } 2238 hubd = ehci_hubd; 2239 hubd.bNbrPorts = sc->sc_noport; 2240 v = EOREAD4(sc, EHCI_HCSPARAMS); 2241 USETW(hubd.wHubCharacteristics, 2242 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2243 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2244 ? UHD_PORT_IND : 0); 2245 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2246 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2247 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2248 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2249 l = min(len, hubd.bDescLength); 2250 totlen = l; 2251 memcpy(buf, &hubd, l); 2252 break; 2253 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2254 if (len != 4) { 2255 err = USBD_IOERROR; 2256 goto ret; 2257 } 2258 memset(buf, 0, len); /* ? XXX */ 2259 totlen = len; 2260 break; 2261 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2262 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2263 index)); 2264 if (index < 1 || index > sc->sc_noport) { 2265 err = USBD_IOERROR; 2266 goto ret; 2267 } 2268 if (len != 4) { 2269 err = USBD_IOERROR; 2270 goto ret; 2271 } 2272 v = EOREAD4(sc, EHCI_PORTSC(index)); 2273 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2274 v)); 2275 2276 if (sc->sc_flags & EHCIF_ETTF) { 2277 /* 2278 * If we are doing embedded transaction translation, 2279 * then directly attached LS/FS devices are reset by 2280 * the EHCI controller itself. PSPD is encoded 2281 * the same way as in USBSTATUS. 2282 */ 2283 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2284 } else { 2285 i = UPS_HIGH_SPEED; 2286 } 2287 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2288 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2289 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2290 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2291 if (v & EHCI_PS_PR) i |= UPS_RESET; 2292 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2293 if (sc->sc_vendor_port_status) 2294 i = sc->sc_vendor_port_status(sc, v, i); 2295 USETW(ps.wPortStatus, i); 2296 i = 0; 2297 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2298 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2299 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2300 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2301 USETW(ps.wPortChange, i); 2302 l = min(len, sizeof ps); 2303 memcpy(buf, &ps, l); 2304 totlen = l; 2305 break; 2306 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2307 err = USBD_IOERROR; 2308 goto ret; 2309 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2310 break; 2311 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2312 if (index < 1 || index > sc->sc_noport) { 2313 err = USBD_IOERROR; 2314 goto ret; 2315 } 2316 port = EHCI_PORTSC(index); 2317 v = EOREAD4(sc, port); 2318 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2319 v &= ~EHCI_PS_CLEAR; 2320 switch(value) { 2321 case UHF_PORT_ENABLE: 2322 EOWRITE4(sc, port, v | EHCI_PS_PE); 2323 break; 2324 case UHF_PORT_SUSPEND: 2325 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2326 break; 2327 case UHF_PORT_RESET: 2328 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2329 index)); 2330 if (EHCI_PS_IS_LOWSPEED(v) 2331 && sc->sc_ncomp > 0 2332 && !(sc->sc_flags & EHCIF_ETTF)) { 2333 /* 2334 * Low speed device on non-ETTF controller or 2335 * unaccompanied controller, give up ownership. 2336 */ 2337 ehci_disown(sc, index, 1); 2338 break; 2339 } 2340 /* Start reset sequence. */ 2341 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2342 EOWRITE4(sc, port, v | EHCI_PS_PR); 2343 /* Wait for reset to complete. */ 2344 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2345 if (sc->sc_dying) { 2346 err = USBD_IOERROR; 2347 goto ret; 2348 } 2349 /* 2350 * An embedded transaction translater will automatically 2351 * terminate the reset sequence so there's no need to 2352 * it. 2353 */ 2354 if (!(sc->sc_flags & EHCIF_ETTF)) { 2355 /* Terminate reset sequence. */ 2356 v = EOREAD4(sc, port); 2357 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2358 /* Wait for HC to complete reset. */ 2359 usb_delay_ms(&sc->sc_bus, 2360 EHCI_PORT_RESET_COMPLETE); 2361 if (sc->sc_dying) { 2362 err = USBD_IOERROR; 2363 goto ret; 2364 } 2365 } 2366 2367 v = EOREAD4(sc, port); 2368 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2369 if (v & EHCI_PS_PR) { 2370 printf("%s: port reset timeout\n", 2371 device_xname(sc->sc_dev)); 2372 return (USBD_TIMEOUT); 2373 } 2374 if (!(v & EHCI_PS_PE)) { 2375 /* Not a high speed device, give up ownership.*/ 2376 ehci_disown(sc, index, 0); 2377 break; 2378 } 2379 sc->sc_isreset[index] = 1; 2380 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2381 index, v)); 2382 break; 2383 case UHF_PORT_POWER: 2384 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2385 "%d (has PPC = %d)\n", index, 2386 sc->sc_hasppc)); 2387 if (sc->sc_hasppc) 2388 EOWRITE4(sc, port, v | EHCI_PS_PP); 2389 break; 2390 case UHF_PORT_TEST: 2391 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2392 "%d\n", index)); 2393 break; 2394 case UHF_PORT_INDICATOR: 2395 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2396 "%d\n", index)); 2397 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2398 break; 2399 default: 2400 err = USBD_IOERROR; 2401 goto ret; 2402 } 2403 break; 2404 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2405 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2406 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2407 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2408 break; 2409 default: 2410 err = USBD_IOERROR; 2411 goto ret; 2412 } 2413 xfer->actlen = totlen; 2414 err = USBD_NORMAL_COMPLETION; 2415 ret: 2416 xfer->status = err; 2417 s = splusb(); 2418 usb_transfer_complete(xfer); 2419 splx(s); 2420 return (USBD_IN_PROGRESS); 2421 } 2422 2423 Static void 2424 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2425 { 2426 int port; 2427 u_int32_t v; 2428 2429 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2430 #ifdef DIAGNOSTIC 2431 if (sc->sc_npcomp != 0) { 2432 int i = (index-1) / sc->sc_npcomp; 2433 if (i >= sc->sc_ncomp) 2434 printf("%s: strange port\n", 2435 device_xname(sc->sc_dev)); 2436 else 2437 printf("%s: handing over %s speed device on " 2438 "port %d to %s\n", 2439 device_xname(sc->sc_dev), 2440 lowspeed ? "low" : "full", 2441 index, device_xname(sc->sc_comps[i])); 2442 } else { 2443 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2444 } 2445 #endif 2446 port = EHCI_PORTSC(index); 2447 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2448 EOWRITE4(sc, port, v | EHCI_PS_PO); 2449 } 2450 2451 /* Abort a root control request. */ 2452 Static void 2453 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2454 { 2455 /* Nothing to do, all transfers are synchronous. */ 2456 } 2457 2458 /* Close the root pipe. */ 2459 Static void 2460 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2461 { 2462 DPRINTF(("ehci_root_ctrl_close\n")); 2463 /* Nothing to do. */ 2464 } 2465 2466 Static void 2467 ehci_root_intr_done(usbd_xfer_handle xfer) 2468 { 2469 xfer->hcpriv = NULL; 2470 } 2471 2472 Static usbd_status 2473 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2474 { 2475 usbd_status err; 2476 2477 /* Insert last in queue. */ 2478 err = usb_insert_transfer(xfer); 2479 if (err) 2480 return (err); 2481 2482 /* Pipe isn't running, start first */ 2483 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2484 } 2485 2486 Static usbd_status 2487 ehci_root_intr_start(usbd_xfer_handle xfer) 2488 { 2489 usbd_pipe_handle pipe = xfer->pipe; 2490 ehci_softc_t *sc = pipe->device->bus->hci_private; 2491 2492 if (sc->sc_dying) 2493 return (USBD_IOERROR); 2494 2495 sc->sc_intrxfer = xfer; 2496 2497 return (USBD_IN_PROGRESS); 2498 } 2499 2500 /* Abort a root interrupt request. */ 2501 Static void 2502 ehci_root_intr_abort(usbd_xfer_handle xfer) 2503 { 2504 int s; 2505 2506 if (xfer->pipe->intrxfer == xfer) { 2507 DPRINTF(("ehci_root_intr_abort: remove\n")); 2508 xfer->pipe->intrxfer = NULL; 2509 } 2510 xfer->status = USBD_CANCELLED; 2511 s = splusb(); 2512 usb_transfer_complete(xfer); 2513 splx(s); 2514 } 2515 2516 /* Close the root pipe. */ 2517 Static void 2518 ehci_root_intr_close(usbd_pipe_handle pipe) 2519 { 2520 ehci_softc_t *sc = pipe->device->bus->hci_private; 2521 2522 DPRINTF(("ehci_root_intr_close\n")); 2523 2524 sc->sc_intrxfer = NULL; 2525 } 2526 2527 Static void 2528 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2529 { 2530 xfer->hcpriv = NULL; 2531 } 2532 2533 /************************/ 2534 2535 Static ehci_soft_qh_t * 2536 ehci_alloc_sqh(ehci_softc_t *sc) 2537 { 2538 ehci_soft_qh_t *sqh; 2539 usbd_status err; 2540 int i, offs; 2541 usb_dma_t dma; 2542 2543 if (sc->sc_freeqhs == NULL) { 2544 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2545 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2546 EHCI_PAGE_SIZE, &dma); 2547 #ifdef EHCI_DEBUG 2548 if (err) 2549 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2550 #endif 2551 if (err) 2552 return (NULL); 2553 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2554 offs = i * EHCI_SQH_SIZE; 2555 sqh = KERNADDR(&dma, offs); 2556 sqh->physaddr = DMAADDR(&dma, offs); 2557 sqh->dma = dma; 2558 sqh->offs = offs; 2559 sqh->next = sc->sc_freeqhs; 2560 sc->sc_freeqhs = sqh; 2561 } 2562 } 2563 sqh = sc->sc_freeqhs; 2564 sc->sc_freeqhs = sqh->next; 2565 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2566 sqh->next = NULL; 2567 return (sqh); 2568 } 2569 2570 Static void 2571 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2572 { 2573 sqh->next = sc->sc_freeqhs; 2574 sc->sc_freeqhs = sqh; 2575 } 2576 2577 Static ehci_soft_qtd_t * 2578 ehci_alloc_sqtd(ehci_softc_t *sc) 2579 { 2580 ehci_soft_qtd_t *sqtd; 2581 usbd_status err; 2582 int i, offs; 2583 usb_dma_t dma; 2584 int s; 2585 2586 if (sc->sc_freeqtds == NULL) { 2587 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2588 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2589 EHCI_PAGE_SIZE, &dma); 2590 #ifdef EHCI_DEBUG 2591 if (err) 2592 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2593 #endif 2594 if (err) 2595 return (NULL); 2596 s = splusb(); 2597 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2598 offs = i * EHCI_SQTD_SIZE; 2599 sqtd = KERNADDR(&dma, offs); 2600 sqtd->physaddr = DMAADDR(&dma, offs); 2601 sqtd->dma = dma; 2602 sqtd->offs = offs; 2603 sqtd->nextqtd = sc->sc_freeqtds; 2604 sc->sc_freeqtds = sqtd; 2605 } 2606 splx(s); 2607 } 2608 2609 s = splusb(); 2610 sqtd = sc->sc_freeqtds; 2611 sc->sc_freeqtds = sqtd->nextqtd; 2612 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2613 sqtd->nextqtd = NULL; 2614 sqtd->xfer = NULL; 2615 splx(s); 2616 2617 return (sqtd); 2618 } 2619 2620 Static void 2621 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2622 { 2623 int s; 2624 2625 s = splusb(); 2626 sqtd->nextqtd = sc->sc_freeqtds; 2627 sc->sc_freeqtds = sqtd; 2628 splx(s); 2629 } 2630 2631 Static usbd_status 2632 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2633 int alen, int rd, usbd_xfer_handle xfer, 2634 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2635 { 2636 ehci_soft_qtd_t *next, *cur; 2637 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2638 u_int32_t qtdstatus; 2639 int len, curlen, mps; 2640 int i, tog; 2641 usb_dma_t *dma = &xfer->dmabuf; 2642 u_int16_t flags = xfer->flags; 2643 2644 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2645 2646 len = alen; 2647 dataphys = DMAADDR(dma, 0); 2648 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2649 qtdstatus = EHCI_QTD_ACTIVE | 2650 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2651 EHCI_QTD_SET_CERR(3) 2652 /* IOC set below */ 2653 /* BYTES set below */ 2654 ; 2655 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2656 tog = epipe->nexttoggle; 2657 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2658 2659 cur = ehci_alloc_sqtd(sc); 2660 *sp = cur; 2661 if (cur == NULL) 2662 goto nomem; 2663 2664 usb_syncmem(dma, 0, alen, 2665 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2666 for (;;) { 2667 dataphyspage = EHCI_PAGE(dataphys); 2668 /* The EHCI hardware can handle at most 5 pages. */ 2669 if (dataphyslastpage - dataphyspage < 2670 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2671 /* we can handle it in this QTD */ 2672 curlen = len; 2673 } else { 2674 /* must use multiple TDs, fill as much as possible. */ 2675 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2676 EHCI_PAGE_OFFSET(dataphys); 2677 #ifdef DIAGNOSTIC 2678 if (curlen > len) { 2679 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2680 "len=0x%x offs=0x%x\n", curlen, len, 2681 EHCI_PAGE_OFFSET(dataphys)); 2682 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2683 dataphyslastpage, dataphyspage, 2684 dataphys); 2685 curlen = len; 2686 } 2687 #endif 2688 /* the length must be a multiple of the max size */ 2689 curlen -= curlen % mps; 2690 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2691 "curlen=%d\n", curlen)); 2692 #ifdef DIAGNOSTIC 2693 if (curlen == 0) 2694 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2695 #endif 2696 } 2697 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2698 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2699 dataphys, dataphyslastpage, 2700 len, curlen)); 2701 len -= curlen; 2702 2703 /* 2704 * Allocate another transfer if there's more data left, 2705 * or if force last short transfer flag is set and we're 2706 * allocating a multiple of the max packet size. 2707 */ 2708 if (len != 0 || 2709 ((curlen % mps) == 0 && !rd && curlen != 0 && 2710 (flags & USBD_FORCE_SHORT_XFER))) { 2711 next = ehci_alloc_sqtd(sc); 2712 if (next == NULL) 2713 goto nomem; 2714 nextphys = htole32(next->physaddr); 2715 } else { 2716 next = NULL; 2717 nextphys = EHCI_NULL; 2718 } 2719 2720 for (i = 0; i * EHCI_PAGE_SIZE < 2721 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2722 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2723 if (i != 0) /* use offset only in first buffer */ 2724 a = EHCI_PAGE(a); 2725 cur->qtd.qtd_buffer[i] = htole32(a); 2726 cur->qtd.qtd_buffer_hi[i] = 0; 2727 #ifdef DIAGNOSTIC 2728 if (i >= EHCI_QTD_NBUFFERS) { 2729 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2730 goto nomem; 2731 } 2732 #endif 2733 } 2734 cur->nextqtd = next; 2735 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2736 cur->qtd.qtd_status = 2737 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2738 cur->xfer = xfer; 2739 cur->len = curlen; 2740 2741 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2742 dataphys, dataphys + curlen)); 2743 /* adjust the toggle based on the number of packets in this 2744 qtd */ 2745 if (((curlen + mps - 1) / mps) & 1) { 2746 tog ^= 1; 2747 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2748 } 2749 if (next == NULL) 2750 break; 2751 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2752 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2753 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2754 if (len) 2755 dataphys += curlen; 2756 cur = next; 2757 } 2758 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2759 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2760 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2761 *ep = cur; 2762 epipe->nexttoggle = tog; 2763 2764 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2765 *sp, *ep)); 2766 2767 return (USBD_NORMAL_COMPLETION); 2768 2769 nomem: 2770 /* XXX free chain */ 2771 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2772 return (USBD_NOMEM); 2773 } 2774 2775 Static void 2776 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2777 ehci_soft_qtd_t *sqtdend) 2778 { 2779 ehci_soft_qtd_t *p; 2780 int i; 2781 2782 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2783 sqtd, sqtdend)); 2784 2785 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2786 p = sqtd->nextqtd; 2787 ehci_free_sqtd(sc, sqtd); 2788 } 2789 } 2790 2791 Static ehci_soft_itd_t * 2792 ehci_alloc_itd(ehci_softc_t *sc) 2793 { 2794 struct ehci_soft_itd *itd, *freeitd; 2795 usbd_status err; 2796 int i, s, offs, frindex, previndex; 2797 usb_dma_t dma; 2798 2799 s = splusb(); 2800 2801 /* Find an itd that wasn't freed this frame or last frame. This can 2802 * discard itds that were freed before frindex wrapped around 2803 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2804 * interrupt and fiddling with list when that happens */ 2805 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2806 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2807 2808 freeitd = NULL; 2809 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2810 if (itd == NULL) 2811 break; 2812 if (itd->slot != frindex && itd->slot != previndex) { 2813 freeitd = itd; 2814 break; 2815 } 2816 } 2817 2818 if (freeitd == NULL) { 2819 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2820 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2821 EHCI_PAGE_SIZE, &dma); 2822 2823 if (err) { 2824 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2825 return NULL; 2826 } 2827 2828 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2829 offs = i * EHCI_ITD_SIZE; 2830 itd = KERNADDR(&dma, offs); 2831 itd->physaddr = DMAADDR(&dma, offs); 2832 itd->dma = dma; 2833 itd->offs = offs; 2834 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2835 } 2836 freeitd = LIST_FIRST(&sc->sc_freeitds); 2837 } 2838 2839 itd = freeitd; 2840 LIST_REMOVE(itd, u.free_list); 2841 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2842 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2843 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2844 BUS_DMASYNC_PREREAD); 2845 2846 itd->u.frame_list.next = NULL; 2847 itd->u.frame_list.prev = NULL; 2848 itd->xfer_next = NULL; 2849 itd->slot = 0; 2850 splx(s); 2851 2852 return itd; 2853 } 2854 2855 Static void 2856 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2857 { 2858 int s; 2859 2860 s = splusb(); 2861 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2862 splx(s); 2863 } 2864 2865 /****************/ 2866 2867 /* 2868 * Close a reqular pipe. 2869 * Assumes that there are no pending transactions. 2870 */ 2871 Static void 2872 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2873 { 2874 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2875 ehci_softc_t *sc = pipe->device->bus->hci_private; 2876 ehci_soft_qh_t *sqh = epipe->sqh; 2877 int s; 2878 2879 s = splusb(); 2880 ehci_rem_qh(sc, sqh, head); 2881 splx(s); 2882 ehci_free_sqh(sc, epipe->sqh); 2883 } 2884 2885 /* 2886 * Abort a device request. 2887 * If this routine is called at splusb() it guarantees that the request 2888 * will be removed from the hardware scheduling and that the callback 2889 * for it will be called with USBD_CANCELLED status. 2890 * It's impossible to guarantee that the requested transfer will not 2891 * have happened since the hardware runs concurrently. 2892 * If the transaction has already happened we rely on the ordinary 2893 * interrupt processing to process it. 2894 * XXX This is most probably wrong. 2895 */ 2896 Static void 2897 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2898 { 2899 #define exfer EXFER(xfer) 2900 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2901 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2902 ehci_soft_qh_t *sqh = epipe->sqh; 2903 ehci_soft_qtd_t *sqtd; 2904 ehci_physaddr_t cur; 2905 u_int32_t qhstatus; 2906 int s; 2907 int hit; 2908 int wake; 2909 2910 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2911 2912 if (sc->sc_dying) { 2913 /* If we're dying, just do the software part. */ 2914 s = splusb(); 2915 xfer->status = status; /* make software ignore it */ 2916 callout_stop(&xfer->timeout_handle); 2917 usb_transfer_complete(xfer); 2918 splx(s); 2919 return; 2920 } 2921 2922 if (xfer->device->bus->intr_context) 2923 panic("ehci_abort_xfer: not in process context"); 2924 2925 /* 2926 * If an abort is already in progress then just wait for it to 2927 * complete and return. 2928 */ 2929 if (xfer->hcflags & UXFER_ABORTING) { 2930 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2931 #ifdef DIAGNOSTIC 2932 if (status == USBD_TIMEOUT) 2933 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2934 #endif 2935 /* Override the status which might be USBD_TIMEOUT. */ 2936 xfer->status = status; 2937 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2938 xfer->hcflags |= UXFER_ABORTWAIT; 2939 while (xfer->hcflags & UXFER_ABORTING) 2940 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2941 return; 2942 } 2943 xfer->hcflags |= UXFER_ABORTING; 2944 2945 /* 2946 * Step 1: Make interrupt routine and hardware ignore xfer. 2947 */ 2948 s = splusb(); 2949 xfer->status = status; /* make software ignore it */ 2950 callout_stop(&xfer->timeout_handle); 2951 2952 usb_syncmem(&sqh->dma, 2953 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2954 sizeof(sqh->qh.qh_qtd.qtd_status), 2955 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2956 qhstatus = sqh->qh.qh_qtd.qtd_status; 2957 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2958 usb_syncmem(&sqh->dma, 2959 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2960 sizeof(sqh->qh.qh_qtd.qtd_status), 2961 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2962 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2963 usb_syncmem(&sqtd->dma, 2964 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2965 sizeof(sqtd->qtd.qtd_status), 2966 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2967 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2968 usb_syncmem(&sqtd->dma, 2969 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2970 sizeof(sqtd->qtd.qtd_status), 2971 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2972 if (sqtd == exfer->sqtdend) 2973 break; 2974 } 2975 splx(s); 2976 2977 /* 2978 * Step 2: Wait until we know hardware has finished any possible 2979 * use of the xfer. Also make sure the soft interrupt routine 2980 * has run. 2981 */ 2982 ehci_sync_hc(sc); 2983 s = splusb(); 2984 #ifdef USB_USE_SOFTINTR 2985 sc->sc_softwake = 1; 2986 #endif /* USB_USE_SOFTINTR */ 2987 usb_schedsoftintr(&sc->sc_bus); 2988 #ifdef USB_USE_SOFTINTR 2989 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2990 #endif /* USB_USE_SOFTINTR */ 2991 splx(s); 2992 2993 /* 2994 * Step 3: Remove any vestiges of the xfer from the hardware. 2995 * The complication here is that the hardware may have executed 2996 * beyond the xfer we're trying to abort. So as we're scanning 2997 * the TDs of this xfer we check if the hardware points to 2998 * any of them. 2999 */ 3000 s = splusb(); /* XXX why? */ 3001 3002 usb_syncmem(&sqh->dma, 3003 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3004 sizeof(sqh->qh.qh_curqtd), 3005 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3006 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3007 hit = 0; 3008 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3009 hit |= cur == sqtd->physaddr; 3010 if (sqtd == exfer->sqtdend) 3011 break; 3012 } 3013 sqtd = sqtd->nextqtd; 3014 /* Zap curqtd register if hardware pointed inside the xfer. */ 3015 if (hit && sqtd != NULL) { 3016 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3017 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3018 usb_syncmem(&sqh->dma, 3019 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3020 sizeof(sqh->qh.qh_curqtd), 3021 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3022 sqh->qh.qh_qtd.qtd_status = qhstatus; 3023 usb_syncmem(&sqh->dma, 3024 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3025 sizeof(sqh->qh.qh_qtd.qtd_status), 3026 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3027 } else { 3028 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3029 } 3030 3031 /* 3032 * Step 4: Execute callback. 3033 */ 3034 #ifdef DIAGNOSTIC 3035 exfer->isdone = 1; 3036 #endif 3037 wake = xfer->hcflags & UXFER_ABORTWAIT; 3038 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3039 usb_transfer_complete(xfer); 3040 if (wake) 3041 wakeup(&xfer->hcflags); 3042 3043 splx(s); 3044 #undef exfer 3045 } 3046 3047 Static void 3048 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3049 { 3050 ehci_isoc_trans_t trans_status; 3051 struct ehci_pipe *epipe; 3052 struct ehci_xfer *exfer; 3053 ehci_softc_t *sc; 3054 struct ehci_soft_itd *itd; 3055 int s, i, wake; 3056 3057 epipe = (struct ehci_pipe *) xfer->pipe; 3058 exfer = EXFER(xfer); 3059 sc = epipe->pipe.device->bus->hci_private; 3060 3061 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3062 3063 if (sc->sc_dying) { 3064 s = splusb(); 3065 xfer->status = status; 3066 callout_stop(&xfer->timeout_handle); 3067 usb_transfer_complete(xfer); 3068 splx(s); 3069 return; 3070 } 3071 3072 if (xfer->hcflags & UXFER_ABORTING) { 3073 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3074 3075 #ifdef DIAGNOSTIC 3076 if (status == USBD_TIMEOUT) 3077 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3078 #endif 3079 3080 xfer->status = status; 3081 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3082 xfer->hcflags |= UXFER_ABORTWAIT; 3083 while (xfer->hcflags & UXFER_ABORTING) 3084 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0); 3085 return; 3086 } 3087 xfer->hcflags |= UXFER_ABORTING; 3088 3089 xfer->status = status; 3090 callout_stop(&xfer->timeout_handle); 3091 3092 s = splusb(); 3093 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3094 usb_syncmem(&itd->dma, 3095 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3096 sizeof(itd->itd.itd_ctl), 3097 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3098 3099 for (i = 0; i < 8; i++) { 3100 trans_status = le32toh(itd->itd.itd_ctl[i]); 3101 trans_status &= ~EHCI_ITD_ACTIVE; 3102 itd->itd.itd_ctl[i] = htole32(trans_status); 3103 } 3104 3105 usb_syncmem(&itd->dma, 3106 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3107 sizeof(itd->itd.itd_ctl), 3108 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3109 } 3110 splx(s); 3111 3112 s = splusb(); 3113 #ifdef USB_USE_SOFTINTR 3114 sc->sc_softwake = 1; 3115 #endif /* USB_USE_SOFTINTR */ 3116 usb_schedsoftintr(&sc->sc_bus); 3117 #ifdef USB_USE_SOFTINTR 3118 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3119 #endif /* USB_USE_SOFTINTR */ 3120 splx(s); 3121 3122 #ifdef DIAGNOSTIC 3123 exfer->isdone = 1; 3124 #endif 3125 wake = xfer->hcflags & UXFER_ABORTWAIT; 3126 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3127 usb_transfer_complete(xfer); 3128 if (wake) 3129 wakeup(&xfer->hcflags); 3130 3131 return; 3132 } 3133 3134 Static void 3135 ehci_timeout(void *addr) 3136 { 3137 struct ehci_xfer *exfer = addr; 3138 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3139 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3140 3141 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3142 #ifdef EHCI_DEBUG 3143 if (ehcidebug > 1) 3144 usbd_dump_pipe(exfer->xfer.pipe); 3145 #endif 3146 3147 if (sc->sc_dying) { 3148 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3149 return; 3150 } 3151 3152 /* Execute the abort in a process context. */ 3153 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3154 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3155 USB_TASKQ_HC); 3156 } 3157 3158 Static void 3159 ehci_timeout_task(void *addr) 3160 { 3161 usbd_xfer_handle xfer = addr; 3162 int s; 3163 3164 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3165 3166 s = splusb(); 3167 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3168 splx(s); 3169 } 3170 3171 /************************/ 3172 3173 Static usbd_status 3174 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3175 { 3176 usbd_status err; 3177 3178 /* Insert last in queue. */ 3179 err = usb_insert_transfer(xfer); 3180 if (err) 3181 return (err); 3182 3183 /* Pipe isn't running, start first */ 3184 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3185 } 3186 3187 Static usbd_status 3188 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3189 { 3190 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3191 usbd_status err; 3192 3193 if (sc->sc_dying) 3194 return (USBD_IOERROR); 3195 3196 #ifdef DIAGNOSTIC 3197 if (!(xfer->rqflags & URQ_REQUEST)) { 3198 /* XXX panic */ 3199 printf("ehci_device_ctrl_transfer: not a request\n"); 3200 return (USBD_INVAL); 3201 } 3202 #endif 3203 3204 err = ehci_device_request(xfer); 3205 if (err) 3206 return (err); 3207 3208 if (sc->sc_bus.use_polling) 3209 ehci_waitintr(sc, xfer); 3210 return (USBD_IN_PROGRESS); 3211 } 3212 3213 Static void 3214 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3215 { 3216 struct ehci_xfer *ex = EXFER(xfer); 3217 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3218 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3219 usb_device_request_t *req = &xfer->request; 3220 int len = UGETW(req->wLength); 3221 int rd = req->bmRequestType & UT_READ; 3222 3223 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3224 3225 #ifdef DIAGNOSTIC 3226 if (!(xfer->rqflags & URQ_REQUEST)) { 3227 panic("ehci_ctrl_done: not a request"); 3228 } 3229 #endif 3230 3231 mutex_enter(&sc->sc_intrhead_lock); 3232 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3233 ehci_del_intr_list(sc, ex); /* remove from active list */ 3234 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3235 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3236 BUS_DMASYNC_POSTWRITE); 3237 if (len) 3238 usb_syncmem(&xfer->dmabuf, 0, len, 3239 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3240 } 3241 mutex_exit(&sc->sc_intrhead_lock); 3242 3243 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3244 } 3245 3246 /* Abort a device control request. */ 3247 Static void 3248 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3249 { 3250 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3251 ehci_abort_xfer(xfer, USBD_CANCELLED); 3252 } 3253 3254 /* Close a device control pipe. */ 3255 Static void 3256 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3257 { 3258 ehci_softc_t *sc = pipe->device->bus->hci_private; 3259 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3260 3261 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3262 ehci_close_pipe(pipe, sc->sc_async_head); 3263 } 3264 3265 Static usbd_status 3266 ehci_device_request(usbd_xfer_handle xfer) 3267 { 3268 #define exfer EXFER(xfer) 3269 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3270 usb_device_request_t *req = &xfer->request; 3271 usbd_device_handle dev = epipe->pipe.device; 3272 ehci_softc_t *sc = dev->bus->hci_private; 3273 int addr = dev->address; 3274 ehci_soft_qtd_t *setup, *stat, *next; 3275 ehci_soft_qh_t *sqh; 3276 int isread; 3277 int len; 3278 usbd_status err; 3279 int s; 3280 3281 isread = req->bmRequestType & UT_READ; 3282 len = UGETW(req->wLength); 3283 3284 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3285 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3286 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3287 UGETW(req->wIndex), len, addr, 3288 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3289 3290 setup = ehci_alloc_sqtd(sc); 3291 if (setup == NULL) { 3292 err = USBD_NOMEM; 3293 goto bad1; 3294 } 3295 stat = ehci_alloc_sqtd(sc); 3296 if (stat == NULL) { 3297 err = USBD_NOMEM; 3298 goto bad2; 3299 } 3300 3301 sqh = epipe->sqh; 3302 epipe->u.ctl.length = len; 3303 3304 /* Update device address and length since they may have changed 3305 during the setup of the control pipe in usbd_new_device(). */ 3306 /* XXX This only needs to be done once, but it's too early in open. */ 3307 /* XXXX Should not touch ED here! */ 3308 sqh->qh.qh_endp = 3309 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3310 htole32( 3311 EHCI_QH_SET_ADDR(addr) | 3312 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3313 ); 3314 3315 /* Set up data transaction */ 3316 if (len != 0) { 3317 ehci_soft_qtd_t *end; 3318 3319 /* Start toggle at 1. */ 3320 epipe->nexttoggle = 1; 3321 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3322 &next, &end); 3323 if (err) 3324 goto bad3; 3325 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3326 end->nextqtd = stat; 3327 end->qtd.qtd_next = 3328 end->qtd.qtd_altnext = htole32(stat->physaddr); 3329 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3330 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3331 } else { 3332 next = stat; 3333 } 3334 3335 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3336 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3337 3338 /* Clear toggle */ 3339 setup->qtd.qtd_status = htole32( 3340 EHCI_QTD_ACTIVE | 3341 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3342 EHCI_QTD_SET_CERR(3) | 3343 EHCI_QTD_SET_TOGGLE(0) | 3344 EHCI_QTD_SET_BYTES(sizeof *req) 3345 ); 3346 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3347 setup->qtd.qtd_buffer_hi[0] = 0; 3348 setup->nextqtd = next; 3349 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3350 setup->xfer = xfer; 3351 setup->len = sizeof *req; 3352 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3353 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3354 3355 stat->qtd.qtd_status = htole32( 3356 EHCI_QTD_ACTIVE | 3357 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3358 EHCI_QTD_SET_CERR(3) | 3359 EHCI_QTD_SET_TOGGLE(1) | 3360 EHCI_QTD_IOC 3361 ); 3362 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3363 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3364 stat->nextqtd = NULL; 3365 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3366 stat->xfer = xfer; 3367 stat->len = 0; 3368 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3369 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3370 3371 #ifdef EHCI_DEBUG 3372 if (ehcidebug > 5) { 3373 DPRINTF(("ehci_device_request:\n")); 3374 ehci_dump_sqh(sqh); 3375 ehci_dump_sqtds(setup); 3376 } 3377 #endif 3378 3379 exfer->sqtdstart = setup; 3380 exfer->sqtdend = stat; 3381 #ifdef DIAGNOSTIC 3382 if (!exfer->isdone) { 3383 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3384 } 3385 exfer->isdone = 0; 3386 #endif 3387 3388 /* Insert qTD in QH list. */ 3389 s = splusb(); 3390 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3391 if (xfer->timeout && !sc->sc_bus.use_polling) { 3392 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3393 (ehci_timeout), (xfer)); 3394 } 3395 mutex_enter(&sc->sc_intrhead_lock); 3396 ehci_add_intr_list(sc, exfer); 3397 mutex_exit(&sc->sc_intrhead_lock); 3398 xfer->status = USBD_IN_PROGRESS; 3399 splx(s); 3400 3401 #ifdef EHCI_DEBUG 3402 if (ehcidebug > 10) { 3403 DPRINTF(("ehci_device_request: status=%x\n", 3404 EOREAD4(sc, EHCI_USBSTS))); 3405 delay(10000); 3406 ehci_dump_regs(sc); 3407 ehci_dump_sqh(sc->sc_async_head); 3408 ehci_dump_sqh(sqh); 3409 ehci_dump_sqtds(setup); 3410 } 3411 #endif 3412 3413 return (USBD_NORMAL_COMPLETION); 3414 3415 bad3: 3416 ehci_free_sqtd(sc, stat); 3417 bad2: 3418 ehci_free_sqtd(sc, setup); 3419 bad1: 3420 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3421 xfer->status = err; 3422 usb_transfer_complete(xfer); 3423 return (err); 3424 #undef exfer 3425 } 3426 3427 /* 3428 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3429 * qTD status, or miss signalling occasionally under heavy load. If the host 3430 * machine is too fast, we we can miss transaction completion - when we scan 3431 * the active list the transaction still seems to be active. This generally 3432 * exhibits itself as a umass stall that never recovers. 3433 * 3434 * We work around this behaviour by setting up this callback after any softintr 3435 * that completes with transactions still pending, giving us another chance to 3436 * check for completion after the writeback has taken place. 3437 */ 3438 Static void 3439 ehci_intrlist_timeout(void *arg) 3440 { 3441 ehci_softc_t *sc = arg; 3442 int s = splusb(); 3443 3444 DPRINTF(("ehci_intrlist_timeout\n")); 3445 usb_schedsoftintr(&sc->sc_bus); 3446 3447 splx(s); 3448 } 3449 3450 /************************/ 3451 3452 Static usbd_status 3453 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3454 { 3455 usbd_status err; 3456 3457 /* Insert last in queue. */ 3458 err = usb_insert_transfer(xfer); 3459 if (err) 3460 return (err); 3461 3462 /* Pipe isn't running, start first */ 3463 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3464 } 3465 3466 Static usbd_status 3467 ehci_device_bulk_start(usbd_xfer_handle xfer) 3468 { 3469 #define exfer EXFER(xfer) 3470 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3471 usbd_device_handle dev = epipe->pipe.device; 3472 ehci_softc_t *sc = dev->bus->hci_private; 3473 ehci_soft_qtd_t *data, *dataend; 3474 ehci_soft_qh_t *sqh; 3475 usbd_status err; 3476 int len, isread, endpt; 3477 int s; 3478 3479 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3480 xfer, xfer->length, xfer->flags)); 3481 3482 if (sc->sc_dying) 3483 return (USBD_IOERROR); 3484 3485 #ifdef DIAGNOSTIC 3486 if (xfer->rqflags & URQ_REQUEST) 3487 panic("ehci_device_bulk_start: a request"); 3488 #endif 3489 3490 len = xfer->length; 3491 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3492 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3493 sqh = epipe->sqh; 3494 3495 epipe->u.bulk.length = len; 3496 3497 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3498 &dataend); 3499 if (err) { 3500 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3501 xfer->status = err; 3502 usb_transfer_complete(xfer); 3503 return (err); 3504 } 3505 3506 #ifdef EHCI_DEBUG 3507 if (ehcidebug > 5) { 3508 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3509 ehci_dump_sqh(sqh); 3510 ehci_dump_sqtds(data); 3511 } 3512 #endif 3513 3514 /* Set up interrupt info. */ 3515 exfer->sqtdstart = data; 3516 exfer->sqtdend = dataend; 3517 #ifdef DIAGNOSTIC 3518 if (!exfer->isdone) { 3519 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3520 } 3521 exfer->isdone = 0; 3522 #endif 3523 3524 s = splusb(); 3525 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3526 if (xfer->timeout && !sc->sc_bus.use_polling) { 3527 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3528 (ehci_timeout), (xfer)); 3529 } 3530 mutex_enter(&sc->sc_intrhead_lock); 3531 ehci_add_intr_list(sc, exfer); 3532 mutex_exit(&sc->sc_intrhead_lock); 3533 xfer->status = USBD_IN_PROGRESS; 3534 splx(s); 3535 3536 #ifdef EHCI_DEBUG 3537 if (ehcidebug > 10) { 3538 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3539 delay(10000); 3540 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3541 ehci_dump_regs(sc); 3542 #if 0 3543 printf("async_head:\n"); 3544 ehci_dump_sqh(sc->sc_async_head); 3545 #endif 3546 printf("sqh:\n"); 3547 ehci_dump_sqh(sqh); 3548 ehci_dump_sqtds(data); 3549 } 3550 #endif 3551 3552 if (sc->sc_bus.use_polling) 3553 ehci_waitintr(sc, xfer); 3554 3555 return (USBD_IN_PROGRESS); 3556 #undef exfer 3557 } 3558 3559 Static void 3560 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3561 { 3562 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3563 ehci_abort_xfer(xfer, USBD_CANCELLED); 3564 } 3565 3566 /* 3567 * Close a device bulk pipe. 3568 */ 3569 Static void 3570 ehci_device_bulk_close(usbd_pipe_handle pipe) 3571 { 3572 ehci_softc_t *sc = pipe->device->bus->hci_private; 3573 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3574 3575 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3576 pipe->endpoint->datatoggle = epipe->nexttoggle; 3577 ehci_close_pipe(pipe, sc->sc_async_head); 3578 } 3579 3580 Static void 3581 ehci_device_bulk_done(usbd_xfer_handle xfer) 3582 { 3583 struct ehci_xfer *ex = EXFER(xfer); 3584 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3585 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3586 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3587 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3588 3589 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3590 xfer, xfer->actlen)); 3591 3592 mutex_enter(&sc->sc_intrhead_lock); 3593 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3594 ehci_del_intr_list(sc, ex); /* remove from active list */ 3595 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3596 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3597 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3598 } 3599 mutex_exit(&sc->sc_intrhead_lock); 3600 3601 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3602 } 3603 3604 /************************/ 3605 3606 Static usbd_status 3607 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3608 { 3609 struct ehci_soft_islot *isp; 3610 int islot, lev; 3611 3612 /* Find a poll rate that is large enough. */ 3613 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3614 if (EHCI_ILEV_IVAL(lev) <= ival) 3615 break; 3616 3617 /* Pick an interrupt slot at the right level. */ 3618 /* XXX could do better than picking at random */ 3619 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3620 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3621 3622 sqh->islot = islot; 3623 isp = &sc->sc_islots[islot]; 3624 ehci_add_qh(sqh, isp->sqh); 3625 3626 return (USBD_NORMAL_COMPLETION); 3627 } 3628 3629 Static usbd_status 3630 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3631 { 3632 usbd_status err; 3633 3634 /* Insert last in queue. */ 3635 err = usb_insert_transfer(xfer); 3636 if (err) 3637 return (err); 3638 3639 /* 3640 * Pipe isn't running (otherwise err would be USBD_INPROG), 3641 * so start it first. 3642 */ 3643 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3644 } 3645 3646 Static usbd_status 3647 ehci_device_intr_start(usbd_xfer_handle xfer) 3648 { 3649 #define exfer EXFER(xfer) 3650 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3651 usbd_device_handle dev = xfer->pipe->device; 3652 ehci_softc_t *sc = dev->bus->hci_private; 3653 ehci_soft_qtd_t *data, *dataend; 3654 ehci_soft_qh_t *sqh; 3655 usbd_status err; 3656 int len, isread, endpt; 3657 int s; 3658 3659 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3660 xfer, xfer->length, xfer->flags)); 3661 3662 if (sc->sc_dying) 3663 return (USBD_IOERROR); 3664 3665 #ifdef DIAGNOSTIC 3666 if (xfer->rqflags & URQ_REQUEST) 3667 panic("ehci_device_intr_start: a request"); 3668 #endif 3669 3670 len = xfer->length; 3671 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3672 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3673 sqh = epipe->sqh; 3674 3675 epipe->u.intr.length = len; 3676 3677 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3678 &dataend); 3679 if (err) { 3680 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3681 xfer->status = err; 3682 usb_transfer_complete(xfer); 3683 return (err); 3684 } 3685 3686 #ifdef EHCI_DEBUG 3687 if (ehcidebug > 5) { 3688 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3689 ehci_dump_sqh(sqh); 3690 ehci_dump_sqtds(data); 3691 } 3692 #endif 3693 3694 /* Set up interrupt info. */ 3695 exfer->sqtdstart = data; 3696 exfer->sqtdend = dataend; 3697 #ifdef DIAGNOSTIC 3698 if (!exfer->isdone) { 3699 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3700 } 3701 exfer->isdone = 0; 3702 #endif 3703 3704 s = splusb(); 3705 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3706 if (xfer->timeout && !sc->sc_bus.use_polling) { 3707 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3708 (ehci_timeout), (xfer)); 3709 } 3710 mutex_enter(&sc->sc_intrhead_lock); 3711 ehci_add_intr_list(sc, exfer); 3712 mutex_exit(&sc->sc_intrhead_lock); 3713 xfer->status = USBD_IN_PROGRESS; 3714 splx(s); 3715 3716 #ifdef EHCI_DEBUG 3717 if (ehcidebug > 10) { 3718 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3719 delay(10000); 3720 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3721 ehci_dump_regs(sc); 3722 printf("sqh:\n"); 3723 ehci_dump_sqh(sqh); 3724 ehci_dump_sqtds(data); 3725 } 3726 #endif 3727 3728 if (sc->sc_bus.use_polling) 3729 ehci_waitintr(sc, xfer); 3730 3731 return (USBD_IN_PROGRESS); 3732 #undef exfer 3733 } 3734 3735 Static void 3736 ehci_device_intr_abort(usbd_xfer_handle xfer) 3737 { 3738 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3739 if (xfer->pipe->intrxfer == xfer) { 3740 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3741 xfer->pipe->intrxfer = NULL; 3742 } 3743 /* 3744 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3745 * async doorbell. That's dependant on the async list, wheras 3746 * intr xfers are periodic, should not use this? 3747 */ 3748 ehci_abort_xfer(xfer, USBD_CANCELLED); 3749 } 3750 3751 Static void 3752 ehci_device_intr_close(usbd_pipe_handle pipe) 3753 { 3754 ehci_softc_t *sc = pipe->device->bus->hci_private; 3755 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3756 struct ehci_soft_islot *isp; 3757 3758 isp = &sc->sc_islots[epipe->sqh->islot]; 3759 ehci_close_pipe(pipe, isp->sqh); 3760 } 3761 3762 Static void 3763 ehci_device_intr_done(usbd_xfer_handle xfer) 3764 { 3765 #define exfer EXFER(xfer) 3766 struct ehci_xfer *ex = EXFER(xfer); 3767 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3768 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3769 ehci_soft_qtd_t *data, *dataend; 3770 ehci_soft_qh_t *sqh; 3771 usbd_status err; 3772 int len, isread, endpt, s; 3773 3774 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3775 xfer, xfer->actlen)); 3776 3777 mutex_enter(&sc->sc_intrhead_lock); 3778 if (xfer->pipe->repeat) { 3779 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3780 3781 len = epipe->u.intr.length; 3782 xfer->length = len; 3783 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3784 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3785 usb_syncmem(&xfer->dmabuf, 0, len, 3786 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3787 sqh = epipe->sqh; 3788 3789 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3790 &data, &dataend); 3791 if (err) { 3792 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3793 xfer->status = err; 3794 mutex_exit(&sc->sc_intrhead_lock); 3795 return; 3796 } 3797 3798 /* Set up interrupt info. */ 3799 exfer->sqtdstart = data; 3800 exfer->sqtdend = dataend; 3801 #ifdef DIAGNOSTIC 3802 if (!exfer->isdone) { 3803 printf("ehci_device_intr_done: not done, ex=%p\n", 3804 exfer); 3805 } 3806 exfer->isdone = 0; 3807 #endif 3808 3809 s = splusb(); 3810 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3811 if (xfer->timeout && !sc->sc_bus.use_polling) { 3812 callout_reset(&(xfer->timeout_handle), 3813 (mstohz(xfer->timeout)), (ehci_timeout), (xfer)); 3814 } 3815 splx(s); 3816 3817 xfer->status = USBD_IN_PROGRESS; 3818 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3819 ehci_del_intr_list(sc, ex); /* remove from active list */ 3820 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3821 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3822 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3823 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3824 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3825 } 3826 mutex_exit(&sc->sc_intrhead_lock); 3827 #undef exfer 3828 } 3829 3830 /************************/ 3831 3832 Static usbd_status 3833 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3834 { 3835 usbd_status err; 3836 3837 err = usb_insert_transfer(xfer); 3838 if (err && err != USBD_IN_PROGRESS) 3839 return err; 3840 3841 return ehci_device_isoc_start(xfer); 3842 } 3843 3844 Static usbd_status 3845 ehci_device_isoc_start(usbd_xfer_handle xfer) 3846 { 3847 struct ehci_pipe *epipe; 3848 usbd_device_handle dev; 3849 ehci_softc_t *sc; 3850 struct ehci_xfer *exfer; 3851 ehci_soft_itd_t *itd, *prev, *start, *stop; 3852 usb_dma_t *dma_buf; 3853 int i, j, k, frames, uframes, ufrperframe; 3854 int s, trans_count, offs, total_length; 3855 int frindex; 3856 3857 start = NULL; 3858 prev = NULL; 3859 itd = NULL; 3860 trans_count = 0; 3861 total_length = 0; 3862 exfer = (struct ehci_xfer *) xfer; 3863 sc = xfer->pipe->device->bus->hci_private; 3864 dev = xfer->pipe->device; 3865 epipe = (struct ehci_pipe *)xfer->pipe; 3866 3867 /* 3868 * To allow continuous transfers, above we start all transfers 3869 * immediately. However, we're still going to get usbd_start_next call 3870 * this when another xfer completes. So, check if this is already 3871 * in progress or not 3872 */ 3873 3874 if (exfer->itdstart != NULL) 3875 return USBD_IN_PROGRESS; 3876 3877 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3878 xfer, xfer->length, xfer->flags)); 3879 3880 if (sc->sc_dying) 3881 return USBD_IOERROR; 3882 3883 /* 3884 * To avoid complication, don't allow a request right now that'll span 3885 * the entire frame table. To within 4 frames, to allow some leeway 3886 * on either side of where the hc currently is. 3887 */ 3888 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3889 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3890 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3891 return USBD_INVAL; 3892 } 3893 3894 #ifdef DIAGNOSTIC 3895 if (xfer->rqflags & URQ_REQUEST) 3896 panic("ehci_device_isoc_start: request\n"); 3897 3898 if (!exfer->isdone) 3899 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3900 exfer->isdone = 0; 3901 #endif 3902 3903 /* 3904 * Step 1: Allocate and initialize itds, how many do we need? 3905 * One per transfer if interval >= 8 microframes, fewer if we use 3906 * multiple microframes per frame. 3907 */ 3908 3909 i = epipe->pipe.endpoint->edesc->bInterval; 3910 if (i > 16 || i == 0) { 3911 /* Spec page 271 says intervals > 16 are invalid */ 3912 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3913 return USBD_INVAL; 3914 } 3915 3916 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 3917 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3918 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 3919 3920 if (frames == 0) { 3921 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3922 return USBD_INVAL; 3923 } 3924 3925 dma_buf = &xfer->dmabuf; 3926 offs = 0; 3927 3928 for (i = 0; i < frames; i++) { 3929 int froffs = offs; 3930 itd = ehci_alloc_itd(sc); 3931 3932 if (prev != NULL) { 3933 prev->itd.itd_next = 3934 htole32(itd->physaddr | EHCI_LINK_ITD); 3935 usb_syncmem(&itd->dma, 3936 itd->offs + offsetof(ehci_itd_t, itd_next), 3937 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 3938 3939 prev->xfer_next = itd; 3940 } else { 3941 start = itd; 3942 } 3943 3944 /* 3945 * Step 1.5, initialize uframes 3946 */ 3947 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 3948 /* Calculate which page in the list this starts in */ 3949 int addr = DMAADDR(dma_buf, froffs); 3950 addr = EHCI_PAGE_OFFSET(addr); 3951 addr += (offs - froffs); 3952 addr = EHCI_PAGE(addr); 3953 addr /= EHCI_PAGE_SIZE; 3954 3955 /* This gets the initial offset into the first page, 3956 * looks how far further along the current uframe 3957 * offset is. Works out how many pages that is. 3958 */ 3959 3960 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3961 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3962 EHCI_ITD_SET_PG(addr) | 3963 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 3964 3965 total_length += xfer->frlengths[trans_count]; 3966 offs += xfer->frlengths[trans_count]; 3967 trans_count++; 3968 3969 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3970 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3971 break; 3972 } 3973 } 3974 3975 /* Step 1.75, set buffer pointers. To simplify matters, all 3976 * pointers are filled out for the next 7 hardware pages in 3977 * the dma block, so no need to worry what pages to cover 3978 * and what to not. 3979 */ 3980 3981 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 3982 /* 3983 * Don't try to lookup a page that's past the end 3984 * of buffer 3985 */ 3986 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 3987 if (page_offs >= dma_buf->block->size) 3988 break; 3989 3990 long long page = DMAADDR(dma_buf, page_offs); 3991 page = EHCI_PAGE(page); 3992 itd->itd.itd_bufr[j] = 3993 htole32(EHCI_ITD_SET_BPTR(page)); 3994 itd->itd.itd_bufr_hi[j] = 3995 htole32(page >> 32); 3996 } 3997 3998 /* 3999 * Other special values 4000 */ 4001 4002 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4003 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4004 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4005 4006 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4007 ? 1 : 0; 4008 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4009 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4010 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4011 4012 /* FIXME: handle invalid trans */ 4013 itd->itd.itd_bufr[2] |= 4014 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4015 4016 usb_syncmem(&itd->dma, 4017 itd->offs + offsetof(ehci_itd_t, itd_next), 4018 sizeof(ehci_itd_t), 4019 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4020 4021 prev = itd; 4022 } /* End of frame */ 4023 4024 stop = itd; 4025 stop->xfer_next = NULL; 4026 exfer->isoc_len = total_length; 4027 4028 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4029 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4030 4031 /* 4032 * Part 2: Transfer descriptors have now been set up, now they must 4033 * be scheduled into the period frame list. Erk. Not wanting to 4034 * complicate matters, transfer is denied if the transfer spans 4035 * more than the period frame list. 4036 */ 4037 4038 s = splusb(); 4039 4040 /* Start inserting frames */ 4041 if (epipe->u.isoc.cur_xfers > 0) { 4042 frindex = epipe->u.isoc.next_frame; 4043 } else { 4044 frindex = EOREAD4(sc, EHCI_FRINDEX); 4045 frindex = frindex >> 3; /* Erase microframe index */ 4046 frindex += 2; 4047 } 4048 4049 if (frindex >= sc->sc_flsize) 4050 frindex &= (sc->sc_flsize - 1); 4051 4052 /* What's the frame interval? */ 4053 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4054 if (i / USB_UFRAMES_PER_FRAME == 0) 4055 i = 1; 4056 else 4057 i /= USB_UFRAMES_PER_FRAME; 4058 4059 itd = start; 4060 for (j = 0; j < frames; j++) { 4061 if (itd == NULL) 4062 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4063 4064 itd->itd.itd_next = sc->sc_flist[frindex]; 4065 if (itd->itd.itd_next == 0) 4066 /* FIXME: frindex table gets initialized to NULL 4067 * or EHCI_NULL? */ 4068 itd->itd.itd_next = EHCI_NULL; 4069 4070 usb_syncmem(&itd->dma, 4071 itd->offs + offsetof(ehci_itd_t, itd_next), 4072 sizeof(itd->itd.itd_next), 4073 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4074 4075 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4076 4077 usb_syncmem(&sc->sc_fldma, 4078 sizeof(ehci_link_t) * frindex, 4079 sizeof(ehci_link_t), 4080 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4081 4082 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4083 sc->sc_softitds[frindex] = itd; 4084 if (itd->u.frame_list.next != NULL) 4085 itd->u.frame_list.next->u.frame_list.prev = itd; 4086 itd->slot = frindex; 4087 itd->u.frame_list.prev = NULL; 4088 4089 frindex += i; 4090 if (frindex >= sc->sc_flsize) 4091 frindex -= sc->sc_flsize; 4092 4093 itd = itd->xfer_next; 4094 } 4095 4096 epipe->u.isoc.cur_xfers++; 4097 epipe->u.isoc.next_frame = frindex; 4098 4099 exfer->itdstart = start; 4100 exfer->itdend = stop; 4101 exfer->sqtdstart = NULL; 4102 exfer->sqtdstart = NULL; 4103 4104 mutex_enter(&sc->sc_intrhead_lock); 4105 ehci_add_intr_list(sc, exfer); 4106 mutex_exit(&sc->sc_intrhead_lock); 4107 xfer->status = USBD_IN_PROGRESS; 4108 xfer->done = 0; 4109 splx(s); 4110 4111 if (sc->sc_bus.use_polling) { 4112 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4113 ehci_waitintr(sc, xfer); 4114 } 4115 4116 return USBD_IN_PROGRESS; 4117 } 4118 4119 Static void 4120 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4121 { 4122 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4123 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4124 } 4125 4126 Static void 4127 ehci_device_isoc_close(usbd_pipe_handle pipe) 4128 { 4129 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4130 } 4131 4132 Static void 4133 ehci_device_isoc_done(usbd_xfer_handle xfer) 4134 { 4135 struct ehci_xfer *exfer; 4136 ehci_softc_t *sc; 4137 struct ehci_pipe *epipe; 4138 int s; 4139 4140 exfer = EXFER(xfer); 4141 sc = xfer->pipe->device->bus->hci_private; 4142 epipe = (struct ehci_pipe *) xfer->pipe; 4143 4144 s = splusb(); 4145 epipe->u.isoc.cur_xfers--; 4146 mutex_enter(&sc->sc_intrhead_lock); 4147 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4148 ehci_del_intr_list(sc, exfer); 4149 ehci_rem_free_itd_chain(sc, exfer); 4150 } 4151 mutex_exit(&sc->sc_intrhead_lock); 4152 splx(s); 4153 4154 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4155 BUS_DMASYNC_POSTREAD); 4156 4157 } 4158
Indexes created Mon Sep 22 21:09:42 GMT 2025