ehci.c revision 1.176
1 /* $NetBSD: ehci.c,v 1.176 2011/05/27 19:04:24 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum and 9 * Jeremy Morse (jeremy.morse (at) gmail.com). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 35 * 36 * The EHCI 1.0 spec can be found at 37 * http://www.intel.com/technology/usb/spec.htm 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/ 40 * 41 */ 42 43 /* 44 * TODO: 45 * 1) hold off explorations by companion controllers until ehci has started. 46 * 47 * 2) The hub driver needs to handle and schedule the transaction translator, 48 * to assign place in frame where different devices get to go. See chapter 49 * on hubs in USB 2.0 for details. 50 * 51 * 3) Command failures are not recovered correctly. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.176 2011/05/27 19:04:24 tsutsui Exp $"); 56 57 #include "ohci.h" 58 #include "uhci.h" 59 60 #include <sys/param.h> 61 #include <sys/systm.h> 62 #include <sys/kernel.h> 63 #include <sys/malloc.h> 64 #include <sys/device.h> 65 #include <sys/select.h> 66 #include <sys/proc.h> 67 #include <sys/queue.h> 68 #include <sys/mutex.h> 69 #include <sys/bus.h> 70 71 #include <machine/endian.h> 72 73 #include <dev/usb/usb.h> 74 #include <dev/usb/usbdi.h> 75 #include <dev/usb/usbdivar.h> 76 #include <dev/usb/usb_mem.h> 77 #include <dev/usb/usb_quirks.h> 78 79 #include <dev/usb/ehcireg.h> 80 #include <dev/usb/ehcivar.h> 81 #include <dev/usb/usbroothub_subr.h> 82 83 #ifdef EHCI_DEBUG 84 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 85 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 86 int ehcidebug = 0; 87 #else 88 #define DPRINTF(x) 89 #define DPRINTFN(n,x) 90 #endif 91 92 struct ehci_pipe { 93 struct usbd_pipe pipe; 94 int nexttoggle; 95 96 ehci_soft_qh_t *sqh; 97 union { 98 ehci_soft_qtd_t *qtd; 99 /* ehci_soft_itd_t *itd; */ 100 } tail; 101 union { 102 /* Control pipe */ 103 struct { 104 usb_dma_t reqdma; 105 u_int length; 106 } ctl; 107 /* Interrupt pipe */ 108 struct { 109 u_int length; 110 } intr; 111 /* Bulk pipe */ 112 struct { 113 u_int length; 114 } bulk; 115 /* Iso pipe */ 116 struct { 117 u_int next_frame; 118 u_int cur_xfers; 119 } isoc; 120 } u; 121 }; 122 123 Static usbd_status ehci_open(usbd_pipe_handle); 124 Static void ehci_poll(struct usbd_bus *); 125 Static void ehci_softintr(void *); 126 Static int ehci_intr1(ehci_softc_t *); 127 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 128 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 129 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 130 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 131 Static void ehci_idone(struct ehci_xfer *); 132 Static void ehci_timeout(void *); 133 Static void ehci_timeout_task(void *); 134 Static void ehci_intrlist_timeout(void *); 135 136 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 137 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 138 139 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 140 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 141 142 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 143 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 144 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 145 Static void ehci_root_ctrl_close(usbd_pipe_handle); 146 Static void ehci_root_ctrl_done(usbd_xfer_handle); 147 148 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 149 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 150 Static void ehci_root_intr_abort(usbd_xfer_handle); 151 Static void ehci_root_intr_close(usbd_pipe_handle); 152 Static void ehci_root_intr_done(usbd_xfer_handle); 153 154 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 155 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 156 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 157 Static void ehci_device_ctrl_close(usbd_pipe_handle); 158 Static void ehci_device_ctrl_done(usbd_xfer_handle); 159 160 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 161 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 162 Static void ehci_device_bulk_abort(usbd_xfer_handle); 163 Static void ehci_device_bulk_close(usbd_pipe_handle); 164 Static void ehci_device_bulk_done(usbd_xfer_handle); 165 166 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 167 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 168 Static void ehci_device_intr_abort(usbd_xfer_handle); 169 Static void ehci_device_intr_close(usbd_pipe_handle); 170 Static void ehci_device_intr_done(usbd_xfer_handle); 171 172 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 173 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 174 Static void ehci_device_isoc_abort(usbd_xfer_handle); 175 Static void ehci_device_isoc_close(usbd_pipe_handle); 176 Static void ehci_device_isoc_done(usbd_xfer_handle); 177 178 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 179 Static void ehci_noop(usbd_pipe_handle pipe); 180 181 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 182 Static void ehci_disown(ehci_softc_t *, int, int); 183 184 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 185 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 186 187 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 188 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 189 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 190 ehci_softc_t *, int, int, usbd_xfer_handle, 191 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 192 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 193 ehci_soft_qtd_t *); 194 195 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 196 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 197 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 198 struct ehci_xfer *exfer); 199 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 200 usbd_status status); 201 202 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 203 204 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 205 int ival); 206 207 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 208 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 209 ehci_soft_qh_t *); 210 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 211 Static void ehci_sync_hc(ehci_softc_t *); 212 213 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 214 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 215 216 #ifdef EHCI_DEBUG 217 Static void ehci_dump_regs(ehci_softc_t *); 218 void ehci_dump(void); 219 Static ehci_softc_t *theehci; 220 Static void ehci_dump_link(ehci_link_t, int); 221 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 222 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 223 Static void ehci_dump_qtd(ehci_qtd_t *); 224 Static void ehci_dump_sqh(ehci_soft_qh_t *); 225 #if notyet 226 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 227 Static void ehci_dump_itd(struct ehci_soft_itd *); 228 #endif 229 #ifdef DIAGNOSTIC 230 Static void ehci_dump_exfer(struct ehci_xfer *); 231 #endif 232 #endif 233 234 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 235 236 #define EHCI_INTR_ENDPT 1 237 238 #define ehci_add_intr_list(sc, ex) \ 239 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 240 #define ehci_del_intr_list(sc, ex) \ 241 do { \ 242 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 243 (ex)->inext.tqe_prev = NULL; \ 244 } while (0) 245 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 246 247 Static const struct usbd_bus_methods ehci_bus_methods = { 248 ehci_open, 249 ehci_softintr, 250 ehci_poll, 251 ehci_allocm, 252 ehci_freem, 253 ehci_allocx, 254 ehci_freex, 255 }; 256 257 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 258 ehci_root_ctrl_transfer, 259 ehci_root_ctrl_start, 260 ehci_root_ctrl_abort, 261 ehci_root_ctrl_close, 262 ehci_noop, 263 ehci_root_ctrl_done, 264 }; 265 266 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 267 ehci_root_intr_transfer, 268 ehci_root_intr_start, 269 ehci_root_intr_abort, 270 ehci_root_intr_close, 271 ehci_noop, 272 ehci_root_intr_done, 273 }; 274 275 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 276 ehci_device_ctrl_transfer, 277 ehci_device_ctrl_start, 278 ehci_device_ctrl_abort, 279 ehci_device_ctrl_close, 280 ehci_noop, 281 ehci_device_ctrl_done, 282 }; 283 284 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 285 ehci_device_intr_transfer, 286 ehci_device_intr_start, 287 ehci_device_intr_abort, 288 ehci_device_intr_close, 289 ehci_device_clear_toggle, 290 ehci_device_intr_done, 291 }; 292 293 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 294 ehci_device_bulk_transfer, 295 ehci_device_bulk_start, 296 ehci_device_bulk_abort, 297 ehci_device_bulk_close, 298 ehci_device_clear_toggle, 299 ehci_device_bulk_done, 300 }; 301 302 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 303 ehci_device_isoc_transfer, 304 ehci_device_isoc_start, 305 ehci_device_isoc_abort, 306 ehci_device_isoc_close, 307 ehci_noop, 308 ehci_device_isoc_done, 309 }; 310 311 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 312 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 313 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 314 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 315 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 316 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 317 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 318 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 319 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 320 }; 321 322 usbd_status 323 ehci_init(ehci_softc_t *sc) 324 { 325 u_int32_t vers, sparams, cparams, hcr; 326 u_int i; 327 usbd_status err; 328 ehci_soft_qh_t *sqh; 329 u_int ncomp; 330 331 DPRINTF(("ehci_init: start\n")); 332 #ifdef EHCI_DEBUG 333 theehci = sc; 334 #endif 335 336 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 337 338 vers = EREAD2(sc, EHCI_HCIVERSION); 339 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 340 vers >> 8, vers & 0xff); 341 342 sparams = EREAD4(sc, EHCI_HCSPARAMS); 343 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 344 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 345 ncomp = EHCI_HCS_N_CC(sparams); 346 if (ncomp != sc->sc_ncomp) { 347 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 348 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 349 #if NOHCI == 0 || NUHCI == 0 350 aprint_error("%s: ohci or uhci probably not configured\n", 351 device_xname(sc->sc_dev)); 352 #endif 353 if (ncomp < sc->sc_ncomp) 354 sc->sc_ncomp = ncomp; 355 } 356 if (sc->sc_ncomp > 0) { 357 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 358 aprint_normal("%s: companion controller%s, %d port%s each:", 359 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 360 EHCI_HCS_N_PCC(sparams), 361 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 362 for (i = 0; i < sc->sc_ncomp; i++) 363 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 364 aprint_normal("\n"); 365 } 366 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 367 cparams = EREAD4(sc, EHCI_HCCPARAMS); 368 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 369 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 370 371 if (EHCI_HCC_64BIT(cparams)) { 372 /* MUST clear segment register if 64 bit capable. */ 373 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 374 } 375 376 sc->sc_bus.usbrev = USBREV_2_0; 377 378 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 379 USB_MEM_RESERVE); 380 381 /* Reset the controller */ 382 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 383 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 384 usb_delay_ms(&sc->sc_bus, 1); 385 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 386 for (i = 0; i < 100; i++) { 387 usb_delay_ms(&sc->sc_bus, 1); 388 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 389 if (!hcr) 390 break; 391 } 392 if (hcr) { 393 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 394 return (USBD_IOERROR); 395 } 396 if (sc->sc_vendor_init) 397 sc->sc_vendor_init(sc); 398 399 /* 400 * If we are doing embedded transaction translation function, force 401 * the controller to host mode. 402 */ 403 if (sc->sc_flags & EHCIF_ETTF) { 404 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 405 usbmode &= ~EHCI_USBMODE_CM; 406 usbmode |= EHCI_USBMODE_CM_HOST; 407 EWRITE4(sc, EHCI_USBMODE, usbmode); 408 } 409 410 /* XXX need proper intr scheduling */ 411 sc->sc_rand = 96; 412 413 /* frame list size at default, read back what we got and use that */ 414 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 415 case 0: sc->sc_flsize = 1024; break; 416 case 1: sc->sc_flsize = 512; break; 417 case 2: sc->sc_flsize = 256; break; 418 case 3: return (USBD_IOERROR); 419 } 420 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 421 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 422 if (err) 423 return (err); 424 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 425 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 426 427 for (i = 0; i < sc->sc_flsize; i++) { 428 sc->sc_flist[i] = EHCI_NULL; 429 } 430 431 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 432 433 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 434 M_USB, M_NOWAIT | M_ZERO); 435 if (sc->sc_softitds == NULL) 436 return ENOMEM; 437 LIST_INIT(&sc->sc_freeitds); 438 TAILQ_INIT(&sc->sc_intrhead); 439 mutex_init(&sc->sc_intrhead_lock, MUTEX_DEFAULT, IPL_USB); 440 441 /* Set up the bus struct. */ 442 sc->sc_bus.methods = &ehci_bus_methods; 443 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 444 445 sc->sc_eintrs = EHCI_NORMAL_INTRS; 446 447 /* 448 * Allocate the interrupt dummy QHs. These are arranged to give poll 449 * intervals that are powers of 2 times 1ms. 450 */ 451 for (i = 0; i < EHCI_INTRQHS; i++) { 452 sqh = ehci_alloc_sqh(sc); 453 if (sqh == NULL) { 454 err = USBD_NOMEM; 455 goto bad1; 456 } 457 sc->sc_islots[i].sqh = sqh; 458 } 459 for (i = 0; i < EHCI_INTRQHS; i++) { 460 sqh = sc->sc_islots[i].sqh; 461 if (i == 0) { 462 /* The last (1ms) QH terminates. */ 463 sqh->qh.qh_link = EHCI_NULL; 464 sqh->next = NULL; 465 } else { 466 /* Otherwise the next QH has half the poll interval */ 467 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 468 sqh->qh.qh_link = htole32(sqh->next->physaddr | 469 EHCI_LINK_QH); 470 } 471 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 472 sqh->qh.qh_curqtd = EHCI_NULL; 473 sqh->next = NULL; 474 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 475 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 476 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 477 sqh->sqtd = NULL; 478 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 479 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 480 } 481 /* Point the frame list at the last level (128ms). */ 482 for (i = 0; i < sc->sc_flsize; i++) { 483 int j; 484 485 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 486 revbits[i & (EHCI_MAX_POLLRATE-1)]; 487 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 488 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 489 i)].sqh->physaddr); 490 } 491 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 492 BUS_DMASYNC_PREWRITE); 493 494 /* Allocate dummy QH that starts the async list. */ 495 sqh = ehci_alloc_sqh(sc); 496 if (sqh == NULL) { 497 err = USBD_NOMEM; 498 goto bad1; 499 } 500 /* Fill the QH */ 501 sqh->qh.qh_endp = 502 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 503 sqh->qh.qh_link = 504 htole32(sqh->physaddr | EHCI_LINK_QH); 505 sqh->qh.qh_curqtd = EHCI_NULL; 506 sqh->next = NULL; 507 /* Fill the overlay qTD */ 508 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 509 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 510 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 511 sqh->sqtd = NULL; 512 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 513 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 514 #ifdef EHCI_DEBUG 515 if (ehcidebug) { 516 ehci_dump_sqh(sqh); 517 } 518 #endif 519 520 /* Point to async list */ 521 sc->sc_async_head = sqh; 522 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 523 524 callout_init(&(sc->sc_tmo_intrlist), 0); 525 526 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE); 527 528 /* Turn on controller */ 529 EOWRITE4(sc, EHCI_USBCMD, 530 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 531 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 532 EHCI_CMD_ASE | 533 EHCI_CMD_PSE | 534 EHCI_CMD_RS); 535 536 /* Take over port ownership */ 537 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 538 539 for (i = 0; i < 100; i++) { 540 usb_delay_ms(&sc->sc_bus, 1); 541 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 542 if (!hcr) 543 break; 544 } 545 if (hcr) { 546 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 547 return (USBD_IOERROR); 548 } 549 550 /* Enable interrupts */ 551 DPRINTFN(1,("ehci_init: enabling\n")); 552 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 553 554 return (USBD_NORMAL_COMPLETION); 555 556 #if 0 557 bad2: 558 ehci_free_sqh(sc, sc->sc_async_head); 559 #endif 560 bad1: 561 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 562 return (err); 563 } 564 565 int 566 ehci_intr(void *v) 567 { 568 ehci_softc_t *sc = v; 569 570 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 571 return (0); 572 573 /* If we get an interrupt while polling, then just ignore it. */ 574 if (sc->sc_bus.use_polling) { 575 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 576 577 if (intrs) 578 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 579 #ifdef DIAGNOSTIC 580 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 581 #endif 582 return (0); 583 } 584 585 return (ehci_intr1(sc)); 586 } 587 588 Static int 589 ehci_intr1(ehci_softc_t *sc) 590 { 591 u_int32_t intrs, eintrs; 592 593 DPRINTFN(20,("ehci_intr1: enter\n")); 594 595 /* In case the interrupt occurs before initialization has completed. */ 596 if (sc == NULL) { 597 #ifdef DIAGNOSTIC 598 printf("ehci_intr1: sc == NULL\n"); 599 #endif 600 return (0); 601 } 602 603 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 604 if (!intrs) 605 return (0); 606 607 eintrs = intrs & sc->sc_eintrs; 608 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 609 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 610 (u_int)eintrs)); 611 if (!eintrs) 612 return (0); 613 614 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 615 sc->sc_bus.intr_context++; 616 sc->sc_bus.no_intrs++; 617 if (eintrs & EHCI_STS_IAA) { 618 DPRINTF(("ehci_intr1: door bell\n")); 619 wakeup(&sc->sc_async_head); 620 eintrs &= ~EHCI_STS_IAA; 621 } 622 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 623 DPRINTFN(5,("ehci_intr1: %s %s\n", 624 eintrs & EHCI_STS_INT ? "INT" : "", 625 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 626 usb_schedsoftintr(&sc->sc_bus); 627 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 628 } 629 if (eintrs & EHCI_STS_HSE) { 630 printf("%s: unrecoverable error, controller halted\n", 631 device_xname(sc->sc_dev)); 632 /* XXX what else */ 633 } 634 if (eintrs & EHCI_STS_PCD) { 635 ehci_pcd(sc, sc->sc_intrxfer); 636 eintrs &= ~EHCI_STS_PCD; 637 } 638 639 sc->sc_bus.intr_context--; 640 641 if (eintrs != 0) { 642 /* Block unprocessed interrupts. */ 643 sc->sc_eintrs &= ~eintrs; 644 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 645 printf("%s: blocking intrs 0x%x\n", 646 device_xname(sc->sc_dev), eintrs); 647 } 648 649 return (1); 650 } 651 652 653 Static void 654 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 655 { 656 usbd_pipe_handle pipe; 657 u_char *p; 658 int i, m; 659 660 if (xfer == NULL) { 661 /* Just ignore the change. */ 662 return; 663 } 664 665 pipe = xfer->pipe; 666 667 p = KERNADDR(&xfer->dmabuf, 0); 668 m = min(sc->sc_noport, xfer->length * 8 - 1); 669 memset(p, 0, xfer->length); 670 for (i = 1; i <= m; i++) { 671 /* Pick out CHANGE bits from the status reg. */ 672 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 673 p[i/8] |= 1 << (i%8); 674 } 675 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 676 xfer->actlen = xfer->length; 677 xfer->status = USBD_NORMAL_COMPLETION; 678 679 usb_transfer_complete(xfer); 680 } 681 682 Static void 683 ehci_softintr(void *v) 684 { 685 struct usbd_bus *bus = v; 686 ehci_softc_t *sc = bus->hci_private; 687 struct ehci_xfer *ex, *nextex; 688 689 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 690 sc->sc_bus.intr_context)); 691 692 sc->sc_bus.intr_context++; 693 694 /* 695 * The only explanation I can think of for why EHCI is as brain dead 696 * as UHCI interrupt-wise is that Intel was involved in both. 697 * An interrupt just tells us that something is done, we have no 698 * clue what, so we need to scan through all active transfers. :-( 699 */ 700 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 701 nextex = TAILQ_NEXT(ex, inext); 702 ehci_check_intr(sc, ex); 703 } 704 705 /* Schedule a callout to catch any dropped transactions. */ 706 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 707 !TAILQ_EMPTY(&sc->sc_intrhead)) 708 callout_reset(&(sc->sc_tmo_intrlist), 709 (hz), (ehci_intrlist_timeout), (sc)); 710 711 #ifdef USB_USE_SOFTINTR 712 if (sc->sc_softwake) { 713 sc->sc_softwake = 0; 714 wakeup(&sc->sc_softwake); 715 } 716 #endif /* USB_USE_SOFTINTR */ 717 718 sc->sc_bus.intr_context--; 719 } 720 721 /* Check for an interrupt. */ 722 Static void 723 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 724 { 725 int attr; 726 727 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 728 729 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 730 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 731 ehci_check_itd_intr(sc, ex); 732 else 733 ehci_check_qh_intr(sc, ex); 734 735 return; 736 } 737 738 Static void 739 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 740 { 741 ehci_soft_qtd_t *sqtd, *lsqtd; 742 __uint32_t status; 743 744 if (ex->sqtdstart == NULL) { 745 printf("ehci_check_qh_intr: not valid sqtd\n"); 746 return; 747 } 748 749 lsqtd = ex->sqtdend; 750 #ifdef DIAGNOSTIC 751 if (lsqtd == NULL) { 752 printf("ehci_check_qh_intr: lsqtd==0\n"); 753 return; 754 } 755 #endif 756 /* 757 * If the last TD is still active we need to check whether there 758 * is a an error somewhere in the middle, or whether there was a 759 * short packet (SPD and not ACTIVE). 760 */ 761 usb_syncmem(&lsqtd->dma, 762 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 763 sizeof(lsqtd->qtd.qtd_status), 764 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 765 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 766 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 767 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 768 usb_syncmem(&sqtd->dma, 769 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 770 sizeof(sqtd->qtd.qtd_status), 771 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 772 status = le32toh(sqtd->qtd.qtd_status); 773 usb_syncmem(&sqtd->dma, 774 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 775 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 776 /* If there's an active QTD the xfer isn't done. */ 777 if (status & EHCI_QTD_ACTIVE) 778 break; 779 /* Any kind of error makes the xfer done. */ 780 if (status & EHCI_QTD_HALTED) 781 goto done; 782 /* We want short packets, and it is short: it's done */ 783 if (EHCI_QTD_GET_BYTES(status) != 0) 784 goto done; 785 } 786 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 787 ex, ex->sqtdstart)); 788 usb_syncmem(&lsqtd->dma, 789 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 790 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 791 return; 792 } 793 done: 794 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 795 callout_stop(&ex->xfer.timeout_handle); 796 ehci_idone(ex); 797 } 798 799 Static void 800 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 801 ehci_soft_itd_t *itd; 802 int i; 803 804 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 805 return; 806 807 if (ex->itdstart == NULL) { 808 printf("ehci_check_itd_intr: not valid itd\n"); 809 return; 810 } 811 812 itd = ex->itdend; 813 #ifdef DIAGNOSTIC 814 if (itd == NULL) { 815 printf("ehci_check_itd_intr: itdend == 0\n"); 816 return; 817 } 818 #endif 819 820 /* 821 * check no active transfers in last itd, meaning we're finished 822 */ 823 824 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 825 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 826 BUS_DMASYNC_POSTREAD); 827 828 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 829 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 830 break; 831 } 832 833 if (i == EHCI_ITD_NUFRAMES) { 834 goto done; /* All 8 descriptors inactive, it's done */ 835 } 836 837 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 838 ex->itdstart)); 839 return; 840 done: 841 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 842 callout_stop(&ex->xfer.timeout_handle); 843 ehci_idone(ex); 844 } 845 846 Static void 847 ehci_idone(struct ehci_xfer *ex) 848 { 849 usbd_xfer_handle xfer = &ex->xfer; 850 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 851 ehci_soft_qtd_t *sqtd, *lsqtd; 852 u_int32_t status = 0, nstatus = 0; 853 int actlen; 854 855 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 856 #ifdef DIAGNOSTIC 857 { 858 int s = splhigh(); 859 if (ex->isdone) { 860 splx(s); 861 #ifdef EHCI_DEBUG 862 printf("ehci_idone: ex is done!\n "); 863 ehci_dump_exfer(ex); 864 #else 865 printf("ehci_idone: ex=%p is done!\n", ex); 866 #endif 867 return; 868 } 869 ex->isdone = 1; 870 splx(s); 871 } 872 #endif 873 if (xfer->status == USBD_CANCELLED || 874 xfer->status == USBD_TIMEOUT) { 875 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 876 return; 877 } 878 879 #ifdef EHCI_DEBUG 880 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 881 if (ehcidebug > 10) 882 ehci_dump_sqtds(ex->sqtdstart); 883 #endif 884 885 /* The transfer is done, compute actual length and status. */ 886 887 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 888 == UE_ISOCHRONOUS) { 889 /* Isoc transfer */ 890 struct ehci_soft_itd *itd; 891 int i, nframes, len, uframes; 892 893 nframes = 0; 894 actlen = 0; 895 896 i = xfer->pipe->endpoint->edesc->bInterval; 897 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 898 899 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 900 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 901 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 902 BUS_DMASYNC_POSTREAD); 903 904 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 905 /* XXX - driver didn't fill in the frame full 906 * of uframes. This leads to scheduling 907 * inefficiencies, but working around 908 * this doubles complexity of tracking 909 * an xfer. 910 */ 911 if (nframes >= xfer->nframes) 912 break; 913 914 status = le32toh(itd->itd.itd_ctl[i]); 915 len = EHCI_ITD_GET_LEN(status); 916 if (EHCI_ITD_GET_STATUS(status) != 0) 917 len = 0; /*No valid data on error*/ 918 919 xfer->frlengths[nframes++] = len; 920 actlen += len; 921 } 922 923 if (nframes >= xfer->nframes) 924 break; 925 } 926 927 xfer->actlen = actlen; 928 xfer->status = USBD_NORMAL_COMPLETION; 929 goto end; 930 } 931 932 /* Continue processing xfers using queue heads */ 933 934 lsqtd = ex->sqtdend; 935 actlen = 0; 936 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 937 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 938 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 939 nstatus = le32toh(sqtd->qtd.qtd_status); 940 if (nstatus & EHCI_QTD_ACTIVE) 941 break; 942 943 status = nstatus; 944 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 945 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 946 } 947 948 949 /* 950 * If there are left over TDs we need to update the toggle. 951 * The default pipe doesn't need it since control transfers 952 * start the toggle at 0 every time. 953 * For a short transfer we need to update the toggle for the missing 954 * packets within the qTD. 955 */ 956 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 957 xfer->pipe->device->default_pipe != xfer->pipe) { 958 DPRINTFN(2, ("ehci_idone: need toggle update " 959 "status=%08x nstatus=%08x\n", status, nstatus)); 960 #if 0 961 ehci_dump_sqh(epipe->sqh); 962 ehci_dump_sqtds(ex->sqtdstart); 963 #endif 964 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 965 } 966 967 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 968 xfer->length, actlen, status)); 969 xfer->actlen = actlen; 970 if (status & EHCI_QTD_HALTED) { 971 #ifdef EHCI_DEBUG 972 char sbuf[128]; 973 974 snprintb(sbuf, sizeof(sbuf), 975 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 976 (u_int32_t)status); 977 978 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 979 "status 0x%s\n", 980 xfer->pipe->device->address, 981 xfer->pipe->endpoint->edesc->bEndpointAddress, 982 sbuf)); 983 if (ehcidebug > 2) { 984 ehci_dump_sqh(epipe->sqh); 985 ehci_dump_sqtds(ex->sqtdstart); 986 } 987 #endif 988 /* low&full speed has an extra error flag */ 989 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 990 EHCI_QH_SPEED_HIGH) 991 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 992 else 993 status &= EHCI_QTD_STATERRS; 994 if (status == 0) /* no other errors means a stall */ { 995 xfer->status = USBD_STALLED; 996 } else { 997 xfer->status = USBD_IOERROR; /* more info XXX */ 998 } 999 /* XXX need to reset TT on missed microframe */ 1000 if (status & EHCI_QTD_MISSEDMICRO) { 1001 ehci_softc_t *sc = 1002 xfer->pipe->device->bus->hci_private; 1003 1004 printf("%s: missed microframe, TT reset not " 1005 "implemented, hub might be inoperational\n", 1006 device_xname(sc->sc_dev)); 1007 } 1008 } else { 1009 xfer->status = USBD_NORMAL_COMPLETION; 1010 } 1011 1012 end: 1013 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1014 * during this call, before methods->done is called: dma sync required 1015 * beforehand? */ 1016 usb_transfer_complete(xfer); 1017 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1018 } 1019 1020 /* 1021 * Wait here until controller claims to have an interrupt. 1022 * Then call ehci_intr and return. Use timeout to avoid waiting 1023 * too long. 1024 */ 1025 Static void 1026 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1027 { 1028 int timo; 1029 u_int32_t intrs; 1030 1031 xfer->status = USBD_IN_PROGRESS; 1032 for (timo = xfer->timeout; timo >= 0; timo--) { 1033 usb_delay_ms(&sc->sc_bus, 1); 1034 if (sc->sc_dying) 1035 break; 1036 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1037 sc->sc_eintrs; 1038 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1039 #ifdef EHCI_DEBUG 1040 if (ehcidebug > 15) 1041 ehci_dump_regs(sc); 1042 #endif 1043 if (intrs) { 1044 ehci_intr1(sc); 1045 if (xfer->status != USBD_IN_PROGRESS) 1046 return; 1047 } 1048 } 1049 1050 /* Timeout */ 1051 DPRINTF(("ehci_waitintr: timeout\n")); 1052 xfer->status = USBD_TIMEOUT; 1053 usb_transfer_complete(xfer); 1054 /* XXX should free TD */ 1055 } 1056 1057 Static void 1058 ehci_poll(struct usbd_bus *bus) 1059 { 1060 ehci_softc_t *sc = bus->hci_private; 1061 #ifdef EHCI_DEBUG 1062 static int last; 1063 int new; 1064 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1065 if (new != last) { 1066 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1067 last = new; 1068 } 1069 #endif 1070 1071 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1072 ehci_intr1(sc); 1073 } 1074 1075 void 1076 ehci_childdet(device_t self, device_t child) 1077 { 1078 struct ehci_softc *sc = device_private(self); 1079 1080 KASSERT(sc->sc_child == child); 1081 sc->sc_child = NULL; 1082 } 1083 1084 int 1085 ehci_detach(struct ehci_softc *sc, int flags) 1086 { 1087 int rv = 0; 1088 1089 if (sc->sc_child != NULL) 1090 rv = config_detach(sc->sc_child, flags); 1091 1092 if (rv != 0) 1093 return (rv); 1094 1095 callout_stop(&sc->sc_tmo_intrlist); 1096 1097 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1098 1099 /* XXX free other data structures XXX */ 1100 mutex_destroy(&sc->sc_doorbell_lock); 1101 mutex_destroy(&sc->sc_intrhead_lock); 1102 1103 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1104 1105 return (rv); 1106 } 1107 1108 1109 int 1110 ehci_activate(device_t self, enum devact act) 1111 { 1112 struct ehci_softc *sc = device_private(self); 1113 1114 switch (act) { 1115 case DVACT_DEACTIVATE: 1116 sc->sc_dying = 1; 1117 return 0; 1118 default: 1119 return EOPNOTSUPP; 1120 } 1121 } 1122 1123 /* 1124 * Handle suspend/resume. 1125 * 1126 * We need to switch to polling mode here, because this routine is 1127 * called from an interrupt context. This is all right since we 1128 * are almost suspended anyway. 1129 * 1130 * Note that this power handler isn't to be registered directly; the 1131 * bus glue needs to call out to it. 1132 */ 1133 bool 1134 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1135 { 1136 ehci_softc_t *sc = device_private(dv); 1137 int i, s; 1138 uint32_t cmd, hcr; 1139 1140 s = splhardusb(); 1141 1142 sc->sc_bus.use_polling++; 1143 1144 for (i = 1; i <= sc->sc_noport; i++) { 1145 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1146 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1147 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1148 } 1149 1150 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1151 1152 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1153 EOWRITE4(sc, EHCI_USBCMD, cmd); 1154 1155 for (i = 0; i < 100; i++) { 1156 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1157 if (hcr == 0) 1158 break; 1159 1160 usb_delay_ms(&sc->sc_bus, 1); 1161 } 1162 if (hcr != 0) 1163 printf("%s: reset timeout\n", device_xname(dv)); 1164 1165 cmd &= ~EHCI_CMD_RS; 1166 EOWRITE4(sc, EHCI_USBCMD, cmd); 1167 1168 for (i = 0; i < 100; i++) { 1169 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1170 if (hcr == EHCI_STS_HCH) 1171 break; 1172 1173 usb_delay_ms(&sc->sc_bus, 1); 1174 } 1175 if (hcr != EHCI_STS_HCH) 1176 printf("%s: config timeout\n", device_xname(dv)); 1177 1178 sc->sc_bus.use_polling--; 1179 splx(s); 1180 1181 return true; 1182 } 1183 1184 bool 1185 ehci_resume(device_t dv, const pmf_qual_t *qual) 1186 { 1187 ehci_softc_t *sc = device_private(dv); 1188 int i; 1189 uint32_t cmd, hcr; 1190 1191 /* restore things in case the bios sucks */ 1192 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1193 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1194 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1195 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1196 1197 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1198 1199 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1200 1201 hcr = 0; 1202 for (i = 1; i <= sc->sc_noport; i++) { 1203 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1204 if ((cmd & EHCI_PS_PO) == 0 && 1205 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1206 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1207 hcr = 1; 1208 } 1209 } 1210 1211 if (hcr) { 1212 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1213 1214 for (i = 1; i <= sc->sc_noport; i++) { 1215 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1216 if ((cmd & EHCI_PS_PO) == 0 && 1217 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1218 EOWRITE4(sc, EHCI_PORTSC(i), 1219 cmd & ~EHCI_PS_FPR); 1220 } 1221 } 1222 1223 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1224 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1225 1226 for (i = 0; i < 100; i++) { 1227 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1228 if (hcr != EHCI_STS_HCH) 1229 break; 1230 1231 usb_delay_ms(&sc->sc_bus, 1); 1232 } 1233 if (hcr == EHCI_STS_HCH) 1234 printf("%s: config timeout\n", device_xname(dv)); 1235 1236 return true; 1237 } 1238 1239 /* 1240 * Shut down the controller when the system is going down. 1241 */ 1242 bool 1243 ehci_shutdown(device_t self, int flags) 1244 { 1245 ehci_softc_t *sc = device_private(self); 1246 1247 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1248 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1249 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1250 return true; 1251 } 1252 1253 Static usbd_status 1254 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1255 { 1256 struct ehci_softc *sc = bus->hci_private; 1257 usbd_status err; 1258 1259 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1260 if (err == USBD_NOMEM) 1261 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1262 #ifdef EHCI_DEBUG 1263 if (err) 1264 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1265 #endif 1266 return (err); 1267 } 1268 1269 Static void 1270 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1271 { 1272 struct ehci_softc *sc = bus->hci_private; 1273 1274 if (dma->block->flags & USB_DMA_RESERVE) { 1275 usb_reserve_freem(&sc->sc_dma_reserve, 1276 dma); 1277 return; 1278 } 1279 usb_freemem(&sc->sc_bus, dma); 1280 } 1281 1282 Static usbd_xfer_handle 1283 ehci_allocx(struct usbd_bus *bus) 1284 { 1285 struct ehci_softc *sc = bus->hci_private; 1286 usbd_xfer_handle xfer; 1287 struct ehci_xfer *exfer; 1288 1289 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1290 if (xfer != NULL) { 1291 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1292 #ifdef DIAGNOSTIC 1293 if (xfer->busy_free != XFER_FREE) { 1294 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1295 xfer->busy_free); 1296 } 1297 #endif 1298 } else { 1299 xfer = malloc(sizeof(*exfer), M_USB, M_NOWAIT); 1300 } 1301 if (xfer != NULL) { 1302 exfer = EXFER(xfer); 1303 memset(exfer, 0, sizeof(*exfer)); 1304 usb_init_task(&exfer->abort_task, ehci_timeout_task, exfer); 1305 #ifdef DIAGNOSTIC 1306 exfer->isdone = 1; 1307 xfer->busy_free = XFER_BUSY; 1308 #endif 1309 } 1310 return (xfer); 1311 } 1312 1313 Static void 1314 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1315 { 1316 struct ehci_softc *sc = bus->hci_private; 1317 struct ehci_xfer *exfer = EXFER(xfer); 1318 1319 #ifdef DIAGNOSTIC 1320 if (xfer->busy_free != XFER_BUSY) { 1321 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1322 xfer->busy_free); 1323 } 1324 xfer->busy_free = XFER_FREE; 1325 if (!exfer->isdone) { 1326 printf("ehci_freex: !isdone\n"); 1327 } 1328 #endif 1329 usb_rem_task(xfer->pipe->device, &exfer->abort_task); 1330 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1331 } 1332 1333 Static void 1334 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1335 { 1336 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1337 1338 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1339 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1340 #ifdef EHCI_DEBUG 1341 if (ehcidebug) 1342 usbd_dump_pipe(pipe); 1343 #endif 1344 epipe->nexttoggle = 0; 1345 } 1346 1347 Static void 1348 ehci_noop(usbd_pipe_handle pipe) 1349 { 1350 } 1351 1352 #ifdef EHCI_DEBUG 1353 Static void 1354 ehci_dump_regs(ehci_softc_t *sc) 1355 { 1356 int i; 1357 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1358 EOREAD4(sc, EHCI_USBCMD), 1359 EOREAD4(sc, EHCI_USBSTS), 1360 EOREAD4(sc, EHCI_USBINTR)); 1361 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1362 EOREAD4(sc, EHCI_FRINDEX), 1363 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1364 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1365 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1366 for (i = 1; i <= sc->sc_noport; i++) 1367 printf("port %d status=0x%08x\n", i, 1368 EOREAD4(sc, EHCI_PORTSC(i))); 1369 } 1370 1371 /* 1372 * Unused function - this is meant to be called from a kernel 1373 * debugger. 1374 */ 1375 void 1376 ehci_dump(void) 1377 { 1378 ehci_dump_regs(theehci); 1379 } 1380 1381 Static void 1382 ehci_dump_link(ehci_link_t link, int type) 1383 { 1384 link = le32toh(link); 1385 printf("0x%08x", link); 1386 if (link & EHCI_LINK_TERMINATE) 1387 printf("<T>"); 1388 else { 1389 printf("<"); 1390 if (type) { 1391 switch (EHCI_LINK_TYPE(link)) { 1392 case EHCI_LINK_ITD: printf("ITD"); break; 1393 case EHCI_LINK_QH: printf("QH"); break; 1394 case EHCI_LINK_SITD: printf("SITD"); break; 1395 case EHCI_LINK_FSTN: printf("FSTN"); break; 1396 } 1397 } 1398 printf(">"); 1399 } 1400 } 1401 1402 Static void 1403 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1404 { 1405 int i; 1406 u_int32_t stop; 1407 1408 stop = 0; 1409 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1410 ehci_dump_sqtd(sqtd); 1411 usb_syncmem(&sqtd->dma, 1412 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1413 sizeof(sqtd->qtd), 1414 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1415 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1416 usb_syncmem(&sqtd->dma, 1417 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1418 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1419 } 1420 if (sqtd) 1421 printf("dump aborted, too many TDs\n"); 1422 } 1423 1424 Static void 1425 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1426 { 1427 usb_syncmem(&sqtd->dma, sqtd->offs, 1428 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1429 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1430 ehci_dump_qtd(&sqtd->qtd); 1431 usb_syncmem(&sqtd->dma, sqtd->offs, 1432 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1433 } 1434 1435 Static void 1436 ehci_dump_qtd(ehci_qtd_t *qtd) 1437 { 1438 u_int32_t s; 1439 char sbuf[128]; 1440 1441 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1442 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1443 printf("\n"); 1444 s = le32toh(qtd->qtd_status); 1445 snprintb(sbuf, sizeof(sbuf), 1446 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1447 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1448 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1449 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1450 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1451 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1452 EHCI_QTD_GET_PID(s), sbuf); 1453 for (s = 0; s < 5; s++) 1454 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1455 } 1456 1457 Static void 1458 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1459 { 1460 ehci_qh_t *qh = &sqh->qh; 1461 u_int32_t endp, endphub; 1462 1463 usb_syncmem(&sqh->dma, sqh->offs, 1464 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1465 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1466 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1467 endp = le32toh(qh->qh_endp); 1468 printf(" endp=0x%08x\n", endp); 1469 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1470 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1471 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1472 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1473 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1474 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1475 EHCI_QH_GET_NRL(endp)); 1476 endphub = le32toh(qh->qh_endphub); 1477 printf(" endphub=0x%08x\n", endphub); 1478 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1479 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1480 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1481 EHCI_QH_GET_MULT(endphub)); 1482 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1483 printf("Overlay qTD:\n"); 1484 ehci_dump_qtd(&qh->qh_qtd); 1485 usb_syncmem(&sqh->dma, sqh->offs, 1486 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1487 } 1488 1489 #if notyet 1490 Static void 1491 ehci_dump_itd(struct ehci_soft_itd *itd) 1492 { 1493 ehci_isoc_trans_t t; 1494 ehci_isoc_bufr_ptr_t b, b2, b3; 1495 int i; 1496 1497 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1498 1499 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1500 t = le32toh(itd->itd.itd_ctl[i]); 1501 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1502 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1503 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1504 EHCI_ITD_GET_OFFS(t)); 1505 } 1506 printf("ITDbufr: "); 1507 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1508 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1509 1510 b = le32toh(itd->itd.itd_bufr[0]); 1511 b2 = le32toh(itd->itd.itd_bufr[1]); 1512 b3 = le32toh(itd->itd.itd_bufr[2]); 1513 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1514 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1515 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1516 } 1517 1518 Static void 1519 ehci_dump_sitd(struct ehci_soft_itd *itd) 1520 { 1521 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1522 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1523 itd->xfer_next, itd->physaddr, itd->slot); 1524 } 1525 #endif 1526 1527 #ifdef DIAGNOSTIC 1528 Static void 1529 ehci_dump_exfer(struct ehci_xfer *ex) 1530 { 1531 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1532 } 1533 #endif 1534 #endif 1535 1536 Static usbd_status 1537 ehci_open(usbd_pipe_handle pipe) 1538 { 1539 usbd_device_handle dev = pipe->device; 1540 ehci_softc_t *sc = dev->bus->hci_private; 1541 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1542 u_int8_t addr = dev->address; 1543 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1544 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1545 ehci_soft_qh_t *sqh; 1546 usbd_status err; 1547 int s; 1548 int ival, speed, naks; 1549 int hshubaddr, hshubport; 1550 1551 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1552 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1553 1554 if (dev->myhsport) { 1555 /* 1556 * When directly attached FS/LS device while doing embedded 1557 * transaction translations and we are the hub, set the hub 1558 * adddress to 0 (us). 1559 */ 1560 if (!(sc->sc_flags & EHCIF_ETTF) 1561 || (dev->myhsport->parent->address != sc->sc_addr)) { 1562 hshubaddr = dev->myhsport->parent->address; 1563 } else { 1564 hshubaddr = 0; 1565 } 1566 hshubport = dev->myhsport->portno; 1567 } else { 1568 hshubaddr = 0; 1569 hshubport = 0; 1570 } 1571 1572 if (sc->sc_dying) 1573 return (USBD_IOERROR); 1574 1575 /* toggle state needed for bulk endpoints */ 1576 epipe->nexttoggle = pipe->endpoint->datatoggle; 1577 1578 if (addr == sc->sc_addr) { 1579 switch (ed->bEndpointAddress) { 1580 case USB_CONTROL_ENDPOINT: 1581 pipe->methods = &ehci_root_ctrl_methods; 1582 break; 1583 case UE_DIR_IN | EHCI_INTR_ENDPT: 1584 pipe->methods = &ehci_root_intr_methods; 1585 break; 1586 default: 1587 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1588 ed->bEndpointAddress)); 1589 return (USBD_INVAL); 1590 } 1591 return (USBD_NORMAL_COMPLETION); 1592 } 1593 1594 /* XXX All this stuff is only valid for async. */ 1595 switch (dev->speed) { 1596 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1597 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1598 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1599 default: panic("ehci_open: bad device speed %d", dev->speed); 1600 } 1601 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1602 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1603 "isoc endpoint.\n"); 1604 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1605 "attached to a USB2 hub, and transaction translations are " 1606 "not yet supported.\n"); 1607 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1608 "root hub instead.\n"); 1609 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1610 hshubaddr, hshubport)); 1611 return USBD_INVAL; 1612 } 1613 1614 /* 1615 * For interrupt transfer, nak throttling must be disabled, but for 1616 * the other transfer type, nak throttling should be enabled from the 1617 * veiwpoint that avoids the memory thrashing. 1618 */ 1619 naks = (xfertype == UE_INTERRUPT) ? 0 1620 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1621 1622 /* Allocate sqh for everything, save isoc xfers */ 1623 if (xfertype != UE_ISOCHRONOUS) { 1624 sqh = ehci_alloc_sqh(sc); 1625 if (sqh == NULL) 1626 return (USBD_NOMEM); 1627 /* qh_link filled when the QH is added */ 1628 sqh->qh.qh_endp = htole32( 1629 EHCI_QH_SET_ADDR(addr) | 1630 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1631 EHCI_QH_SET_EPS(speed) | 1632 EHCI_QH_DTC | 1633 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1634 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1635 EHCI_QH_CTL : 0) | 1636 EHCI_QH_SET_NRL(naks) 1637 ); 1638 sqh->qh.qh_endphub = htole32( 1639 EHCI_QH_SET_MULT(1) | 1640 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1641 ); 1642 if (speed != EHCI_QH_SPEED_HIGH) 1643 sqh->qh.qh_endphub |= htole32( 1644 EHCI_QH_SET_PORT(hshubport) | 1645 EHCI_QH_SET_HUBA(hshubaddr) | 1646 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1647 ); 1648 sqh->qh.qh_curqtd = EHCI_NULL; 1649 /* Fill the overlay qTD */ 1650 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1651 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1652 sqh->qh.qh_qtd.qtd_status = htole32(0); 1653 1654 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1655 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1656 epipe->sqh = sqh; 1657 } else { 1658 sqh = NULL; 1659 } /*xfertype == UE_ISOC*/ 1660 1661 switch (xfertype) { 1662 case UE_CONTROL: 1663 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1664 0, &epipe->u.ctl.reqdma); 1665 #ifdef EHCI_DEBUG 1666 if (err) 1667 printf("ehci_open: usb_allocmem()=%d\n", err); 1668 #endif 1669 if (err) 1670 goto bad; 1671 pipe->methods = &ehci_device_ctrl_methods; 1672 s = splusb(); 1673 ehci_add_qh(sqh, sc->sc_async_head); 1674 splx(s); 1675 break; 1676 case UE_BULK: 1677 pipe->methods = &ehci_device_bulk_methods; 1678 s = splusb(); 1679 ehci_add_qh(sqh, sc->sc_async_head); 1680 splx(s); 1681 break; 1682 case UE_INTERRUPT: 1683 pipe->methods = &ehci_device_intr_methods; 1684 ival = pipe->interval; 1685 if (ival == USBD_DEFAULT_INTERVAL) { 1686 if (speed == EHCI_QH_SPEED_HIGH) { 1687 if (ed->bInterval > 16) { 1688 /* 1689 * illegal with high-speed, but there 1690 * were documentation bugs in the spec, 1691 * so be generous 1692 */ 1693 ival = 256; 1694 } else 1695 ival = (1 << (ed->bInterval - 1)) / 8; 1696 } else 1697 ival = ed->bInterval; 1698 } 1699 err = ehci_device_setintr(sc, sqh, ival); 1700 if (err) 1701 goto bad; 1702 break; 1703 case UE_ISOCHRONOUS: 1704 pipe->methods = &ehci_device_isoc_methods; 1705 if (ed->bInterval == 0 || ed->bInterval > 16) { 1706 printf("ehci: opening pipe with invalid bInterval\n"); 1707 err = USBD_INVAL; 1708 goto bad; 1709 } 1710 if (UGETW(ed->wMaxPacketSize) == 0) { 1711 printf("ehci: zero length endpoint open request\n"); 1712 err = USBD_INVAL; 1713 goto bad; 1714 } 1715 epipe->u.isoc.next_frame = 0; 1716 epipe->u.isoc.cur_xfers = 0; 1717 break; 1718 default: 1719 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1720 err = USBD_INVAL; 1721 goto bad; 1722 } 1723 return (USBD_NORMAL_COMPLETION); 1724 1725 bad: 1726 if (sqh != NULL) 1727 ehci_free_sqh(sc, sqh); 1728 return (err); 1729 } 1730 1731 /* 1732 * Add an ED to the schedule. Called at splusb(). 1733 */ 1734 Static void 1735 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1736 { 1737 SPLUSBCHECK; 1738 1739 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1740 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1741 sqh->next = head->next; 1742 sqh->qh.qh_link = head->qh.qh_link; 1743 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1744 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1745 head->next = sqh; 1746 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1747 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1748 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1749 1750 #ifdef EHCI_DEBUG 1751 if (ehcidebug > 5) { 1752 printf("ehci_add_qh:\n"); 1753 ehci_dump_sqh(sqh); 1754 } 1755 #endif 1756 } 1757 1758 /* 1759 * Remove an ED from the schedule. Called at splusb(). 1760 */ 1761 Static void 1762 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1763 { 1764 ehci_soft_qh_t *p; 1765 1766 SPLUSBCHECK; 1767 /* XXX */ 1768 for (p = head; p != NULL && p->next != sqh; p = p->next) 1769 ; 1770 if (p == NULL) 1771 panic("ehci_rem_qh: ED not found"); 1772 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1773 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1774 p->next = sqh->next; 1775 p->qh.qh_link = sqh->qh.qh_link; 1776 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1777 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1778 1779 ehci_sync_hc(sc); 1780 } 1781 1782 Static void 1783 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1784 { 1785 int i; 1786 u_int32_t status; 1787 1788 /* Save toggle bit and ping status. */ 1789 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1790 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1791 status = sqh->qh.qh_qtd.qtd_status & 1792 htole32(EHCI_QTD_TOGGLE_MASK | 1793 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1794 /* Set HALTED to make hw leave it alone. */ 1795 sqh->qh.qh_qtd.qtd_status = 1796 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1797 usb_syncmem(&sqh->dma, 1798 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1799 sizeof(sqh->qh.qh_qtd.qtd_status), 1800 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1801 sqh->qh.qh_curqtd = 0; 1802 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1803 sqh->qh.qh_qtd.qtd_altnext = 0; 1804 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1805 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1806 sqh->sqtd = sqtd; 1807 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1808 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1809 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1810 sqh->qh.qh_qtd.qtd_status = status; 1811 usb_syncmem(&sqh->dma, 1812 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1813 sizeof(sqh->qh.qh_qtd.qtd_status), 1814 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1815 } 1816 1817 /* 1818 * Ensure that the HC has released all references to the QH. We do this 1819 * by asking for a Async Advance Doorbell interrupt and then we wait for 1820 * the interrupt. 1821 * To make this easier we first obtain exclusive use of the doorbell. 1822 */ 1823 Static void 1824 ehci_sync_hc(ehci_softc_t *sc) 1825 { 1826 int s, error; 1827 1828 if (sc->sc_dying) { 1829 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1830 return; 1831 } 1832 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1833 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */ 1834 s = splhardusb(); 1835 /* ask for doorbell */ 1836 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1837 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1838 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1839 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1840 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1841 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1842 splx(s); 1843 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */ 1844 #ifdef DIAGNOSTIC 1845 if (error) 1846 printf("ehci_sync_hc: tsleep() = %d\n", error); 1847 #endif 1848 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1849 } 1850 1851 /*Call at splusb*/ 1852 Static void 1853 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1854 { 1855 struct ehci_soft_itd *itd, *prev; 1856 1857 prev = NULL; 1858 1859 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1860 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1861 1862 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1863 prev = itd->u.frame_list.prev; 1864 /* Unlink itd from hardware chain, or frame array */ 1865 if (prev == NULL) { /* We're at the table head */ 1866 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1867 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1868 usb_syncmem(&sc->sc_fldma, 1869 sizeof(ehci_link_t) * itd->slot, 1870 sizeof(ehci_link_t), 1871 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1872 1873 if (itd->u.frame_list.next != NULL) 1874 itd->u.frame_list.next->u.frame_list.prev = NULL; 1875 } else { 1876 /* XXX this part is untested... */ 1877 prev->itd.itd_next = itd->itd.itd_next; 1878 usb_syncmem(&itd->dma, 1879 itd->offs + offsetof(ehci_itd_t, itd_next), 1880 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1881 1882 prev->u.frame_list.next = itd->u.frame_list.next; 1883 if (itd->u.frame_list.next != NULL) 1884 itd->u.frame_list.next->u.frame_list.prev = prev; 1885 } 1886 } 1887 1888 prev = NULL; 1889 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1890 if (prev != NULL) 1891 ehci_free_itd(sc, prev); 1892 prev = itd; 1893 } 1894 if (prev) 1895 ehci_free_itd(sc, prev); 1896 exfer->itdstart = NULL; 1897 exfer->itdend = NULL; 1898 } 1899 1900 /***********/ 1901 1902 /* 1903 * Data structures and routines to emulate the root hub. 1904 */ 1905 Static usb_device_descriptor_t ehci_devd = { 1906 USB_DEVICE_DESCRIPTOR_SIZE, 1907 UDESC_DEVICE, /* type */ 1908 {0x00, 0x02}, /* USB version */ 1909 UDCLASS_HUB, /* class */ 1910 UDSUBCLASS_HUB, /* subclass */ 1911 UDPROTO_HSHUBSTT, /* protocol */ 1912 64, /* max packet */ 1913 {0},{0},{0x00,0x01}, /* device id */ 1914 1,2,0, /* string indicies */ 1915 1 /* # of configurations */ 1916 }; 1917 1918 Static const usb_device_qualifier_t ehci_odevd = { 1919 USB_DEVICE_DESCRIPTOR_SIZE, 1920 UDESC_DEVICE_QUALIFIER, /* type */ 1921 {0x00, 0x02}, /* USB version */ 1922 UDCLASS_HUB, /* class */ 1923 UDSUBCLASS_HUB, /* subclass */ 1924 UDPROTO_FSHUB, /* protocol */ 1925 64, /* max packet */ 1926 1, /* # of configurations */ 1927 0 1928 }; 1929 1930 Static const usb_config_descriptor_t ehci_confd = { 1931 USB_CONFIG_DESCRIPTOR_SIZE, 1932 UDESC_CONFIG, 1933 {USB_CONFIG_DESCRIPTOR_SIZE + 1934 USB_INTERFACE_DESCRIPTOR_SIZE + 1935 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1936 1, 1937 1, 1938 0, 1939 UC_ATTR_MBO | UC_SELF_POWERED, 1940 0 /* max power */ 1941 }; 1942 1943 Static const usb_interface_descriptor_t ehci_ifcd = { 1944 USB_INTERFACE_DESCRIPTOR_SIZE, 1945 UDESC_INTERFACE, 1946 0, 1947 0, 1948 1, 1949 UICLASS_HUB, 1950 UISUBCLASS_HUB, 1951 UIPROTO_HSHUBSTT, 1952 0 1953 }; 1954 1955 Static const usb_endpoint_descriptor_t ehci_endpd = { 1956 USB_ENDPOINT_DESCRIPTOR_SIZE, 1957 UDESC_ENDPOINT, 1958 UE_DIR_IN | EHCI_INTR_ENDPT, 1959 UE_INTERRUPT, 1960 {8, 0}, /* max packet */ 1961 12 1962 }; 1963 1964 Static const usb_hub_descriptor_t ehci_hubd = { 1965 USB_HUB_DESCRIPTOR_SIZE, 1966 UDESC_HUB, 1967 0, 1968 {0,0}, 1969 0, 1970 0, 1971 {""}, 1972 {""}, 1973 }; 1974 1975 /* 1976 * Simulate a hardware hub by handling all the necessary requests. 1977 */ 1978 Static usbd_status 1979 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1980 { 1981 usbd_status err; 1982 1983 /* Insert last in queue. */ 1984 err = usb_insert_transfer(xfer); 1985 if (err) 1986 return (err); 1987 1988 /* Pipe isn't running, start first */ 1989 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1990 } 1991 1992 Static usbd_status 1993 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1994 { 1995 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1996 usb_device_request_t *req; 1997 void *buf = NULL; 1998 int port, i; 1999 int s, len, value, index, l, totlen = 0; 2000 usb_port_status_t ps; 2001 usb_hub_descriptor_t hubd; 2002 usbd_status err; 2003 u_int32_t v; 2004 2005 if (sc->sc_dying) 2006 return (USBD_IOERROR); 2007 2008 #ifdef DIAGNOSTIC 2009 if (!(xfer->rqflags & URQ_REQUEST)) 2010 /* XXX panic */ 2011 return (USBD_INVAL); 2012 #endif 2013 req = &xfer->request; 2014 2015 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2016 req->bmRequestType, req->bRequest)); 2017 2018 len = UGETW(req->wLength); 2019 value = UGETW(req->wValue); 2020 index = UGETW(req->wIndex); 2021 2022 if (len != 0) 2023 buf = KERNADDR(&xfer->dmabuf, 0); 2024 2025 #define C(x,y) ((x) | ((y) << 8)) 2026 switch(C(req->bRequest, req->bmRequestType)) { 2027 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2028 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2029 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2030 /* 2031 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2032 * for the integrated root hub. 2033 */ 2034 break; 2035 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2036 if (len > 0) { 2037 *(u_int8_t *)buf = sc->sc_conf; 2038 totlen = 1; 2039 } 2040 break; 2041 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2042 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2043 if (len == 0) 2044 break; 2045 switch(value >> 8) { 2046 case UDESC_DEVICE: 2047 if ((value & 0xff) != 0) { 2048 err = USBD_IOERROR; 2049 goto ret; 2050 } 2051 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2052 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2053 memcpy(buf, &ehci_devd, l); 2054 break; 2055 /* 2056 * We can't really operate at another speed, but the spec says 2057 * we need this descriptor. 2058 */ 2059 case UDESC_DEVICE_QUALIFIER: 2060 if ((value & 0xff) != 0) { 2061 err = USBD_IOERROR; 2062 goto ret; 2063 } 2064 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2065 memcpy(buf, &ehci_odevd, l); 2066 break; 2067 /* 2068 * We can't really operate at another speed, but the spec says 2069 * we need this descriptor. 2070 */ 2071 case UDESC_OTHER_SPEED_CONFIGURATION: 2072 case UDESC_CONFIG: 2073 if ((value & 0xff) != 0) { 2074 err = USBD_IOERROR; 2075 goto ret; 2076 } 2077 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2078 memcpy(buf, &ehci_confd, l); 2079 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2080 value >> 8; 2081 buf = (char *)buf + l; 2082 len -= l; 2083 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2084 totlen += l; 2085 memcpy(buf, &ehci_ifcd, l); 2086 buf = (char *)buf + l; 2087 len -= l; 2088 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2089 totlen += l; 2090 memcpy(buf, &ehci_endpd, l); 2091 break; 2092 case UDESC_STRING: 2093 #define sd ((usb_string_descriptor_t *)buf) 2094 switch (value & 0xff) { 2095 case 0: /* Language table */ 2096 totlen = usb_makelangtbl(sd, len); 2097 break; 2098 case 1: /* Vendor */ 2099 totlen = usb_makestrdesc(sd, len, 2100 sc->sc_vendor); 2101 break; 2102 case 2: /* Product */ 2103 totlen = usb_makestrdesc(sd, len, 2104 "EHCI root hub"); 2105 break; 2106 } 2107 #undef sd 2108 break; 2109 default: 2110 err = USBD_IOERROR; 2111 goto ret; 2112 } 2113 break; 2114 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2115 if (len > 0) { 2116 *(u_int8_t *)buf = 0; 2117 totlen = 1; 2118 } 2119 break; 2120 case C(UR_GET_STATUS, UT_READ_DEVICE): 2121 if (len > 1) { 2122 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2123 totlen = 2; 2124 } 2125 break; 2126 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2127 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2128 if (len > 1) { 2129 USETW(((usb_status_t *)buf)->wStatus, 0); 2130 totlen = 2; 2131 } 2132 break; 2133 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2134 if (value >= USB_MAX_DEVICES) { 2135 err = USBD_IOERROR; 2136 goto ret; 2137 } 2138 sc->sc_addr = value; 2139 break; 2140 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2141 if (value != 0 && value != 1) { 2142 err = USBD_IOERROR; 2143 goto ret; 2144 } 2145 sc->sc_conf = value; 2146 break; 2147 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2148 break; 2149 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2150 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2151 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2152 err = USBD_IOERROR; 2153 goto ret; 2154 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2155 break; 2156 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2157 break; 2158 /* Hub requests */ 2159 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2160 break; 2161 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2162 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2163 "port=%d feature=%d\n", 2164 index, value)); 2165 if (index < 1 || index > sc->sc_noport) { 2166 err = USBD_IOERROR; 2167 goto ret; 2168 } 2169 port = EHCI_PORTSC(index); 2170 v = EOREAD4(sc, port); 2171 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2172 v &= ~EHCI_PS_CLEAR; 2173 switch(value) { 2174 case UHF_PORT_ENABLE: 2175 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2176 break; 2177 case UHF_PORT_SUSPEND: 2178 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2179 break; 2180 v &= ~EHCI_PS_SUSP; 2181 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2182 /* see USB2 spec ch. 7.1.7.7 */ 2183 usb_delay_ms(&sc->sc_bus, 20); 2184 EOWRITE4(sc, port, v); 2185 usb_delay_ms(&sc->sc_bus, 2); 2186 #ifdef DEBUG 2187 v = EOREAD4(sc, port); 2188 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2189 printf("ehci: resume failed: %x\n", v); 2190 #endif 2191 break; 2192 case UHF_PORT_POWER: 2193 if (sc->sc_hasppc) 2194 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2195 break; 2196 case UHF_PORT_TEST: 2197 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2198 "%d\n", index)); 2199 break; 2200 case UHF_PORT_INDICATOR: 2201 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2202 "%d\n", index)); 2203 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2204 break; 2205 case UHF_C_PORT_CONNECTION: 2206 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2207 break; 2208 case UHF_C_PORT_ENABLE: 2209 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2210 break; 2211 case UHF_C_PORT_SUSPEND: 2212 /* how? */ 2213 break; 2214 case UHF_C_PORT_OVER_CURRENT: 2215 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2216 break; 2217 case UHF_C_PORT_RESET: 2218 sc->sc_isreset[index] = 0; 2219 break; 2220 default: 2221 err = USBD_IOERROR; 2222 goto ret; 2223 } 2224 #if 0 2225 switch(value) { 2226 case UHF_C_PORT_CONNECTION: 2227 case UHF_C_PORT_ENABLE: 2228 case UHF_C_PORT_SUSPEND: 2229 case UHF_C_PORT_OVER_CURRENT: 2230 case UHF_C_PORT_RESET: 2231 default: 2232 break; 2233 } 2234 #endif 2235 break; 2236 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2237 if (len == 0) 2238 break; 2239 if ((value & 0xff) != 0) { 2240 err = USBD_IOERROR; 2241 goto ret; 2242 } 2243 hubd = ehci_hubd; 2244 hubd.bNbrPorts = sc->sc_noport; 2245 v = EOREAD4(sc, EHCI_HCSPARAMS); 2246 USETW(hubd.wHubCharacteristics, 2247 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2248 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2249 ? UHD_PORT_IND : 0); 2250 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2251 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2252 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2253 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2254 l = min(len, hubd.bDescLength); 2255 totlen = l; 2256 memcpy(buf, &hubd, l); 2257 break; 2258 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2259 if (len != 4) { 2260 err = USBD_IOERROR; 2261 goto ret; 2262 } 2263 memset(buf, 0, len); /* ? XXX */ 2264 totlen = len; 2265 break; 2266 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2267 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2268 index)); 2269 if (index < 1 || index > sc->sc_noport) { 2270 err = USBD_IOERROR; 2271 goto ret; 2272 } 2273 if (len != 4) { 2274 err = USBD_IOERROR; 2275 goto ret; 2276 } 2277 v = EOREAD4(sc, EHCI_PORTSC(index)); 2278 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", 2279 v)); 2280 2281 if (sc->sc_flags & EHCIF_ETTF) { 2282 /* 2283 * If we are doing embedded transaction translation, 2284 * then directly attached LS/FS devices are reset by 2285 * the EHCI controller itself. PSPD is encoded 2286 * the same way as in USBSTATUS. 2287 */ 2288 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2289 } else { 2290 i = UPS_HIGH_SPEED; 2291 } 2292 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2293 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2294 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2295 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2296 if (v & EHCI_PS_PR) i |= UPS_RESET; 2297 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2298 if (sc->sc_vendor_port_status) 2299 i = sc->sc_vendor_port_status(sc, v, i); 2300 USETW(ps.wPortStatus, i); 2301 i = 0; 2302 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2303 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2304 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2305 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2306 USETW(ps.wPortChange, i); 2307 l = min(len, sizeof ps); 2308 memcpy(buf, &ps, l); 2309 totlen = l; 2310 break; 2311 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2312 err = USBD_IOERROR; 2313 goto ret; 2314 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2315 break; 2316 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2317 if (index < 1 || index > sc->sc_noport) { 2318 err = USBD_IOERROR; 2319 goto ret; 2320 } 2321 port = EHCI_PORTSC(index); 2322 v = EOREAD4(sc, port); 2323 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2324 v &= ~EHCI_PS_CLEAR; 2325 switch(value) { 2326 case UHF_PORT_ENABLE: 2327 EOWRITE4(sc, port, v | EHCI_PS_PE); 2328 break; 2329 case UHF_PORT_SUSPEND: 2330 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2331 break; 2332 case UHF_PORT_RESET: 2333 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2334 index)); 2335 if (EHCI_PS_IS_LOWSPEED(v) 2336 && sc->sc_ncomp > 0 2337 && !(sc->sc_flags & EHCIF_ETTF)) { 2338 /* 2339 * Low speed device on non-ETTF controller or 2340 * unaccompanied controller, give up ownership. 2341 */ 2342 ehci_disown(sc, index, 1); 2343 break; 2344 } 2345 /* Start reset sequence. */ 2346 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2347 EOWRITE4(sc, port, v | EHCI_PS_PR); 2348 /* Wait for reset to complete. */ 2349 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2350 if (sc->sc_dying) { 2351 err = USBD_IOERROR; 2352 goto ret; 2353 } 2354 /* 2355 * An embedded transaction translater will automatically 2356 * terminate the reset sequence so there's no need to 2357 * it. 2358 */ 2359 if (!(sc->sc_flags & EHCIF_ETTF)) { 2360 /* Terminate reset sequence. */ 2361 v = EOREAD4(sc, port); 2362 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2363 /* Wait for HC to complete reset. */ 2364 usb_delay_ms(&sc->sc_bus, 2365 EHCI_PORT_RESET_COMPLETE); 2366 if (sc->sc_dying) { 2367 err = USBD_IOERROR; 2368 goto ret; 2369 } 2370 } 2371 2372 v = EOREAD4(sc, port); 2373 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2374 if (v & EHCI_PS_PR) { 2375 printf("%s: port reset timeout\n", 2376 device_xname(sc->sc_dev)); 2377 return (USBD_TIMEOUT); 2378 } 2379 if (!(v & EHCI_PS_PE)) { 2380 /* Not a high speed device, give up ownership.*/ 2381 ehci_disown(sc, index, 0); 2382 break; 2383 } 2384 sc->sc_isreset[index] = 1; 2385 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2386 index, v)); 2387 break; 2388 case UHF_PORT_POWER: 2389 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2390 "%d (has PPC = %d)\n", index, 2391 sc->sc_hasppc)); 2392 if (sc->sc_hasppc) 2393 EOWRITE4(sc, port, v | EHCI_PS_PP); 2394 break; 2395 case UHF_PORT_TEST: 2396 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2397 "%d\n", index)); 2398 break; 2399 case UHF_PORT_INDICATOR: 2400 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2401 "%d\n", index)); 2402 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2403 break; 2404 default: 2405 err = USBD_IOERROR; 2406 goto ret; 2407 } 2408 break; 2409 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2410 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2411 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2412 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2413 break; 2414 default: 2415 err = USBD_IOERROR; 2416 goto ret; 2417 } 2418 xfer->actlen = totlen; 2419 err = USBD_NORMAL_COMPLETION; 2420 ret: 2421 xfer->status = err; 2422 s = splusb(); 2423 usb_transfer_complete(xfer); 2424 splx(s); 2425 return (USBD_IN_PROGRESS); 2426 } 2427 2428 Static void 2429 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2430 { 2431 int port; 2432 u_int32_t v; 2433 2434 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2435 #ifdef DIAGNOSTIC 2436 if (sc->sc_npcomp != 0) { 2437 int i = (index-1) / sc->sc_npcomp; 2438 if (i >= sc->sc_ncomp) 2439 printf("%s: strange port\n", 2440 device_xname(sc->sc_dev)); 2441 else 2442 printf("%s: handing over %s speed device on " 2443 "port %d to %s\n", 2444 device_xname(sc->sc_dev), 2445 lowspeed ? "low" : "full", 2446 index, device_xname(sc->sc_comps[i])); 2447 } else { 2448 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2449 } 2450 #endif 2451 port = EHCI_PORTSC(index); 2452 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2453 EOWRITE4(sc, port, v | EHCI_PS_PO); 2454 } 2455 2456 /* Abort a root control request. */ 2457 Static void 2458 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2459 { 2460 /* Nothing to do, all transfers are synchronous. */ 2461 } 2462 2463 /* Close the root pipe. */ 2464 Static void 2465 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2466 { 2467 DPRINTF(("ehci_root_ctrl_close\n")); 2468 /* Nothing to do. */ 2469 } 2470 2471 Static void 2472 ehci_root_intr_done(usbd_xfer_handle xfer) 2473 { 2474 xfer->hcpriv = NULL; 2475 } 2476 2477 Static usbd_status 2478 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2479 { 2480 usbd_status err; 2481 2482 /* Insert last in queue. */ 2483 err = usb_insert_transfer(xfer); 2484 if (err) 2485 return (err); 2486 2487 /* Pipe isn't running, start first */ 2488 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2489 } 2490 2491 Static usbd_status 2492 ehci_root_intr_start(usbd_xfer_handle xfer) 2493 { 2494 usbd_pipe_handle pipe = xfer->pipe; 2495 ehci_softc_t *sc = pipe->device->bus->hci_private; 2496 2497 if (sc->sc_dying) 2498 return (USBD_IOERROR); 2499 2500 sc->sc_intrxfer = xfer; 2501 2502 return (USBD_IN_PROGRESS); 2503 } 2504 2505 /* Abort a root interrupt request. */ 2506 Static void 2507 ehci_root_intr_abort(usbd_xfer_handle xfer) 2508 { 2509 int s; 2510 2511 if (xfer->pipe->intrxfer == xfer) { 2512 DPRINTF(("ehci_root_intr_abort: remove\n")); 2513 xfer->pipe->intrxfer = NULL; 2514 } 2515 xfer->status = USBD_CANCELLED; 2516 s = splusb(); 2517 usb_transfer_complete(xfer); 2518 splx(s); 2519 } 2520 2521 /* Close the root pipe. */ 2522 Static void 2523 ehci_root_intr_close(usbd_pipe_handle pipe) 2524 { 2525 ehci_softc_t *sc = pipe->device->bus->hci_private; 2526 2527 DPRINTF(("ehci_root_intr_close\n")); 2528 2529 sc->sc_intrxfer = NULL; 2530 } 2531 2532 Static void 2533 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2534 { 2535 xfer->hcpriv = NULL; 2536 } 2537 2538 /************************/ 2539 2540 Static ehci_soft_qh_t * 2541 ehci_alloc_sqh(ehci_softc_t *sc) 2542 { 2543 ehci_soft_qh_t *sqh; 2544 usbd_status err; 2545 int i, offs; 2546 usb_dma_t dma; 2547 2548 if (sc->sc_freeqhs == NULL) { 2549 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2550 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2551 EHCI_PAGE_SIZE, &dma); 2552 #ifdef EHCI_DEBUG 2553 if (err) 2554 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2555 #endif 2556 if (err) 2557 return (NULL); 2558 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2559 offs = i * EHCI_SQH_SIZE; 2560 sqh = KERNADDR(&dma, offs); 2561 sqh->physaddr = DMAADDR(&dma, offs); 2562 sqh->dma = dma; 2563 sqh->offs = offs; 2564 sqh->next = sc->sc_freeqhs; 2565 sc->sc_freeqhs = sqh; 2566 } 2567 } 2568 sqh = sc->sc_freeqhs; 2569 sc->sc_freeqhs = sqh->next; 2570 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2571 sqh->next = NULL; 2572 return (sqh); 2573 } 2574 2575 Static void 2576 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2577 { 2578 sqh->next = sc->sc_freeqhs; 2579 sc->sc_freeqhs = sqh; 2580 } 2581 2582 Static ehci_soft_qtd_t * 2583 ehci_alloc_sqtd(ehci_softc_t *sc) 2584 { 2585 ehci_soft_qtd_t *sqtd; 2586 usbd_status err; 2587 int i, offs; 2588 usb_dma_t dma; 2589 int s; 2590 2591 if (sc->sc_freeqtds == NULL) { 2592 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2593 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2594 EHCI_PAGE_SIZE, &dma); 2595 #ifdef EHCI_DEBUG 2596 if (err) 2597 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2598 #endif 2599 if (err) 2600 return (NULL); 2601 s = splusb(); 2602 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2603 offs = i * EHCI_SQTD_SIZE; 2604 sqtd = KERNADDR(&dma, offs); 2605 sqtd->physaddr = DMAADDR(&dma, offs); 2606 sqtd->dma = dma; 2607 sqtd->offs = offs; 2608 sqtd->nextqtd = sc->sc_freeqtds; 2609 sc->sc_freeqtds = sqtd; 2610 } 2611 splx(s); 2612 } 2613 2614 s = splusb(); 2615 sqtd = sc->sc_freeqtds; 2616 sc->sc_freeqtds = sqtd->nextqtd; 2617 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2618 sqtd->nextqtd = NULL; 2619 sqtd->xfer = NULL; 2620 splx(s); 2621 2622 return (sqtd); 2623 } 2624 2625 Static void 2626 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2627 { 2628 int s; 2629 2630 s = splusb(); 2631 sqtd->nextqtd = sc->sc_freeqtds; 2632 sc->sc_freeqtds = sqtd; 2633 splx(s); 2634 } 2635 2636 Static usbd_status 2637 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2638 int alen, int rd, usbd_xfer_handle xfer, 2639 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2640 { 2641 ehci_soft_qtd_t *next, *cur; 2642 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2643 u_int32_t qtdstatus; 2644 int len, curlen, mps; 2645 int i, tog; 2646 usb_dma_t *dma = &xfer->dmabuf; 2647 u_int16_t flags = xfer->flags; 2648 2649 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2650 2651 len = alen; 2652 dataphys = DMAADDR(dma, 0); 2653 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2654 qtdstatus = EHCI_QTD_ACTIVE | 2655 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2656 EHCI_QTD_SET_CERR(3) 2657 /* IOC set below */ 2658 /* BYTES set below */ 2659 ; 2660 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2661 tog = epipe->nexttoggle; 2662 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2663 2664 cur = ehci_alloc_sqtd(sc); 2665 *sp = cur; 2666 if (cur == NULL) 2667 goto nomem; 2668 2669 usb_syncmem(dma, 0, alen, 2670 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2671 for (;;) { 2672 dataphyspage = EHCI_PAGE(dataphys); 2673 /* The EHCI hardware can handle at most 5 pages. */ 2674 if (dataphyslastpage - dataphyspage < 2675 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2676 /* we can handle it in this QTD */ 2677 curlen = len; 2678 } else { 2679 /* must use multiple TDs, fill as much as possible. */ 2680 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2681 EHCI_PAGE_OFFSET(dataphys); 2682 #ifdef DIAGNOSTIC 2683 if (curlen > len) { 2684 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2685 "len=0x%x offs=0x%x\n", curlen, len, 2686 EHCI_PAGE_OFFSET(dataphys)); 2687 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2688 dataphyslastpage, dataphyspage, 2689 dataphys); 2690 curlen = len; 2691 } 2692 #endif 2693 /* the length must be a multiple of the max size */ 2694 curlen -= curlen % mps; 2695 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2696 "curlen=%d\n", curlen)); 2697 #ifdef DIAGNOSTIC 2698 if (curlen == 0) 2699 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2700 #endif 2701 } 2702 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2703 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2704 dataphys, dataphyslastpage, 2705 len, curlen)); 2706 len -= curlen; 2707 2708 /* 2709 * Allocate another transfer if there's more data left, 2710 * or if force last short transfer flag is set and we're 2711 * allocating a multiple of the max packet size. 2712 */ 2713 if (len != 0 || 2714 ((curlen % mps) == 0 && !rd && curlen != 0 && 2715 (flags & USBD_FORCE_SHORT_XFER))) { 2716 next = ehci_alloc_sqtd(sc); 2717 if (next == NULL) 2718 goto nomem; 2719 nextphys = htole32(next->physaddr); 2720 } else { 2721 next = NULL; 2722 nextphys = EHCI_NULL; 2723 } 2724 2725 for (i = 0; i * EHCI_PAGE_SIZE < 2726 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2727 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2728 if (i != 0) /* use offset only in first buffer */ 2729 a = EHCI_PAGE(a); 2730 cur->qtd.qtd_buffer[i] = htole32(a); 2731 cur->qtd.qtd_buffer_hi[i] = 0; 2732 #ifdef DIAGNOSTIC 2733 if (i >= EHCI_QTD_NBUFFERS) { 2734 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2735 goto nomem; 2736 } 2737 #endif 2738 } 2739 cur->nextqtd = next; 2740 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2741 cur->qtd.qtd_status = 2742 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2743 cur->xfer = xfer; 2744 cur->len = curlen; 2745 2746 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2747 dataphys, dataphys + curlen)); 2748 /* adjust the toggle based on the number of packets in this 2749 qtd */ 2750 if (((curlen + mps - 1) / mps) & 1) { 2751 tog ^= 1; 2752 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2753 } 2754 if (next == NULL) 2755 break; 2756 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2757 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2758 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2759 if (len) 2760 dataphys += curlen; 2761 cur = next; 2762 } 2763 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2764 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2765 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2766 *ep = cur; 2767 epipe->nexttoggle = tog; 2768 2769 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2770 *sp, *ep)); 2771 2772 return (USBD_NORMAL_COMPLETION); 2773 2774 nomem: 2775 /* XXX free chain */ 2776 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2777 return (USBD_NOMEM); 2778 } 2779 2780 Static void 2781 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2782 ehci_soft_qtd_t *sqtdend) 2783 { 2784 ehci_soft_qtd_t *p; 2785 int i; 2786 2787 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2788 sqtd, sqtdend)); 2789 2790 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2791 p = sqtd->nextqtd; 2792 ehci_free_sqtd(sc, sqtd); 2793 } 2794 } 2795 2796 Static ehci_soft_itd_t * 2797 ehci_alloc_itd(ehci_softc_t *sc) 2798 { 2799 struct ehci_soft_itd *itd, *freeitd; 2800 usbd_status err; 2801 int i, s, offs, frindex, previndex; 2802 usb_dma_t dma; 2803 2804 s = splusb(); 2805 2806 /* Find an itd that wasn't freed this frame or last frame. This can 2807 * discard itds that were freed before frindex wrapped around 2808 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2809 * interrupt and fiddling with list when that happens */ 2810 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2811 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2812 2813 freeitd = NULL; 2814 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2815 if (itd == NULL) 2816 break; 2817 if (itd->slot != frindex && itd->slot != previndex) { 2818 freeitd = itd; 2819 break; 2820 } 2821 } 2822 2823 if (freeitd == NULL) { 2824 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2825 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2826 EHCI_PAGE_SIZE, &dma); 2827 2828 if (err) { 2829 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2830 return NULL; 2831 } 2832 2833 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2834 offs = i * EHCI_ITD_SIZE; 2835 itd = KERNADDR(&dma, offs); 2836 itd->physaddr = DMAADDR(&dma, offs); 2837 itd->dma = dma; 2838 itd->offs = offs; 2839 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2840 } 2841 freeitd = LIST_FIRST(&sc->sc_freeitds); 2842 } 2843 2844 itd = freeitd; 2845 LIST_REMOVE(itd, u.free_list); 2846 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2847 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2848 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2849 BUS_DMASYNC_PREREAD); 2850 2851 itd->u.frame_list.next = NULL; 2852 itd->u.frame_list.prev = NULL; 2853 itd->xfer_next = NULL; 2854 itd->slot = 0; 2855 splx(s); 2856 2857 return itd; 2858 } 2859 2860 Static void 2861 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2862 { 2863 int s; 2864 2865 s = splusb(); 2866 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2867 splx(s); 2868 } 2869 2870 /****************/ 2871 2872 /* 2873 * Close a reqular pipe. 2874 * Assumes that there are no pending transactions. 2875 */ 2876 Static void 2877 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2878 { 2879 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2880 ehci_softc_t *sc = pipe->device->bus->hci_private; 2881 ehci_soft_qh_t *sqh = epipe->sqh; 2882 int s; 2883 2884 s = splusb(); 2885 ehci_rem_qh(sc, sqh, head); 2886 splx(s); 2887 ehci_free_sqh(sc, epipe->sqh); 2888 } 2889 2890 /* 2891 * Abort a device request. 2892 * If this routine is called at splusb() it guarantees that the request 2893 * will be removed from the hardware scheduling and that the callback 2894 * for it will be called with USBD_CANCELLED status. 2895 * It's impossible to guarantee that the requested transfer will not 2896 * have happened since the hardware runs concurrently. 2897 * If the transaction has already happened we rely on the ordinary 2898 * interrupt processing to process it. 2899 * XXX This is most probably wrong. 2900 */ 2901 Static void 2902 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2903 { 2904 #define exfer EXFER(xfer) 2905 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2906 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2907 ehci_soft_qh_t *sqh = epipe->sqh; 2908 ehci_soft_qtd_t *sqtd; 2909 ehci_physaddr_t cur; 2910 u_int32_t qhstatus; 2911 int s; 2912 int hit; 2913 int wake; 2914 2915 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2916 2917 if (sc->sc_dying) { 2918 /* If we're dying, just do the software part. */ 2919 s = splusb(); 2920 xfer->status = status; /* make software ignore it */ 2921 callout_stop(&xfer->timeout_handle); 2922 usb_transfer_complete(xfer); 2923 splx(s); 2924 return; 2925 } 2926 2927 if (xfer->device->bus->intr_context) 2928 panic("ehci_abort_xfer: not in process context"); 2929 2930 /* 2931 * If an abort is already in progress then just wait for it to 2932 * complete and return. 2933 */ 2934 if (xfer->hcflags & UXFER_ABORTING) { 2935 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2936 #ifdef DIAGNOSTIC 2937 if (status == USBD_TIMEOUT) 2938 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2939 #endif 2940 /* Override the status which might be USBD_TIMEOUT. */ 2941 xfer->status = status; 2942 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2943 xfer->hcflags |= UXFER_ABORTWAIT; 2944 while (xfer->hcflags & UXFER_ABORTING) 2945 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2946 return; 2947 } 2948 xfer->hcflags |= UXFER_ABORTING; 2949 2950 /* 2951 * Step 1: Make interrupt routine and hardware ignore xfer. 2952 */ 2953 s = splusb(); 2954 xfer->status = status; /* make software ignore it */ 2955 callout_stop(&xfer->timeout_handle); 2956 2957 usb_syncmem(&sqh->dma, 2958 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2959 sizeof(sqh->qh.qh_qtd.qtd_status), 2960 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2961 qhstatus = sqh->qh.qh_qtd.qtd_status; 2962 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2963 usb_syncmem(&sqh->dma, 2964 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2965 sizeof(sqh->qh.qh_qtd.qtd_status), 2966 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2967 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2968 usb_syncmem(&sqtd->dma, 2969 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2970 sizeof(sqtd->qtd.qtd_status), 2971 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2972 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2973 usb_syncmem(&sqtd->dma, 2974 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2975 sizeof(sqtd->qtd.qtd_status), 2976 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2977 if (sqtd == exfer->sqtdend) 2978 break; 2979 } 2980 splx(s); 2981 2982 /* 2983 * Step 2: Wait until we know hardware has finished any possible 2984 * use of the xfer. Also make sure the soft interrupt routine 2985 * has run. 2986 */ 2987 ehci_sync_hc(sc); 2988 s = splusb(); 2989 #ifdef USB_USE_SOFTINTR 2990 sc->sc_softwake = 1; 2991 #endif /* USB_USE_SOFTINTR */ 2992 usb_schedsoftintr(&sc->sc_bus); 2993 #ifdef USB_USE_SOFTINTR 2994 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2995 #endif /* USB_USE_SOFTINTR */ 2996 splx(s); 2997 2998 /* 2999 * Step 3: Remove any vestiges of the xfer from the hardware. 3000 * The complication here is that the hardware may have executed 3001 * beyond the xfer we're trying to abort. So as we're scanning 3002 * the TDs of this xfer we check if the hardware points to 3003 * any of them. 3004 */ 3005 s = splusb(); /* XXX why? */ 3006 3007 usb_syncmem(&sqh->dma, 3008 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3009 sizeof(sqh->qh.qh_curqtd), 3010 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3011 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3012 hit = 0; 3013 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3014 hit |= cur == sqtd->physaddr; 3015 if (sqtd == exfer->sqtdend) 3016 break; 3017 } 3018 sqtd = sqtd->nextqtd; 3019 /* Zap curqtd register if hardware pointed inside the xfer. */ 3020 if (hit && sqtd != NULL) { 3021 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3022 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3023 usb_syncmem(&sqh->dma, 3024 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3025 sizeof(sqh->qh.qh_curqtd), 3026 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3027 sqh->qh.qh_qtd.qtd_status = qhstatus; 3028 usb_syncmem(&sqh->dma, 3029 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3030 sizeof(sqh->qh.qh_qtd.qtd_status), 3031 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3032 } else { 3033 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3034 } 3035 3036 /* 3037 * Step 4: Execute callback. 3038 */ 3039 #ifdef DIAGNOSTIC 3040 exfer->isdone = 1; 3041 #endif 3042 wake = xfer->hcflags & UXFER_ABORTWAIT; 3043 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3044 usb_transfer_complete(xfer); 3045 if (wake) 3046 wakeup(&xfer->hcflags); 3047 3048 splx(s); 3049 #undef exfer 3050 } 3051 3052 Static void 3053 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3054 { 3055 ehci_isoc_trans_t trans_status; 3056 struct ehci_pipe *epipe; 3057 struct ehci_xfer *exfer; 3058 ehci_softc_t *sc; 3059 struct ehci_soft_itd *itd; 3060 int s, i, wake; 3061 3062 epipe = (struct ehci_pipe *) xfer->pipe; 3063 exfer = EXFER(xfer); 3064 sc = epipe->pipe.device->bus->hci_private; 3065 3066 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3067 3068 if (sc->sc_dying) { 3069 s = splusb(); 3070 xfer->status = status; 3071 callout_stop(&xfer->timeout_handle); 3072 usb_transfer_complete(xfer); 3073 splx(s); 3074 return; 3075 } 3076 3077 if (xfer->hcflags & UXFER_ABORTING) { 3078 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3079 3080 #ifdef DIAGNOSTIC 3081 if (status == USBD_TIMEOUT) 3082 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3083 #endif 3084 3085 xfer->status = status; 3086 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3087 xfer->hcflags |= UXFER_ABORTWAIT; 3088 while (xfer->hcflags & UXFER_ABORTING) 3089 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0); 3090 return; 3091 } 3092 xfer->hcflags |= UXFER_ABORTING; 3093 3094 xfer->status = status; 3095 callout_stop(&xfer->timeout_handle); 3096 3097 s = splusb(); 3098 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3099 usb_syncmem(&itd->dma, 3100 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3101 sizeof(itd->itd.itd_ctl), 3102 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3103 3104 for (i = 0; i < 8; i++) { 3105 trans_status = le32toh(itd->itd.itd_ctl[i]); 3106 trans_status &= ~EHCI_ITD_ACTIVE; 3107 itd->itd.itd_ctl[i] = htole32(trans_status); 3108 } 3109 3110 usb_syncmem(&itd->dma, 3111 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3112 sizeof(itd->itd.itd_ctl), 3113 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3114 } 3115 splx(s); 3116 3117 s = splusb(); 3118 #ifdef USB_USE_SOFTINTR 3119 sc->sc_softwake = 1; 3120 #endif /* USB_USE_SOFTINTR */ 3121 usb_schedsoftintr(&sc->sc_bus); 3122 #ifdef USB_USE_SOFTINTR 3123 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3124 #endif /* USB_USE_SOFTINTR */ 3125 splx(s); 3126 3127 #ifdef DIAGNOSTIC 3128 exfer->isdone = 1; 3129 #endif 3130 wake = xfer->hcflags & UXFER_ABORTWAIT; 3131 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3132 usb_transfer_complete(xfer); 3133 if (wake) 3134 wakeup(&xfer->hcflags); 3135 3136 return; 3137 } 3138 3139 Static void 3140 ehci_timeout(void *addr) 3141 { 3142 struct ehci_xfer *exfer = addr; 3143 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3144 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3145 3146 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3147 #ifdef EHCI_DEBUG 3148 if (ehcidebug > 1) 3149 usbd_dump_pipe(exfer->xfer.pipe); 3150 #endif 3151 3152 if (sc->sc_dying) { 3153 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3154 return; 3155 } 3156 3157 /* Execute the abort in a process context. */ 3158 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3159 USB_TASKQ_HC); 3160 } 3161 3162 Static void 3163 ehci_timeout_task(void *addr) 3164 { 3165 usbd_xfer_handle xfer = addr; 3166 int s; 3167 3168 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3169 3170 s = splusb(); 3171 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3172 splx(s); 3173 } 3174 3175 /************************/ 3176 3177 Static usbd_status 3178 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3179 { 3180 usbd_status err; 3181 3182 /* Insert last in queue. */ 3183 err = usb_insert_transfer(xfer); 3184 if (err) 3185 return (err); 3186 3187 /* Pipe isn't running, start first */ 3188 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3189 } 3190 3191 Static usbd_status 3192 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3193 { 3194 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3195 usbd_status err; 3196 3197 if (sc->sc_dying) 3198 return (USBD_IOERROR); 3199 3200 #ifdef DIAGNOSTIC 3201 if (!(xfer->rqflags & URQ_REQUEST)) { 3202 /* XXX panic */ 3203 printf("ehci_device_ctrl_transfer: not a request\n"); 3204 return (USBD_INVAL); 3205 } 3206 #endif 3207 3208 err = ehci_device_request(xfer); 3209 if (err) 3210 return (err); 3211 3212 if (sc->sc_bus.use_polling) 3213 ehci_waitintr(sc, xfer); 3214 return (USBD_IN_PROGRESS); 3215 } 3216 3217 Static void 3218 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3219 { 3220 struct ehci_xfer *ex = EXFER(xfer); 3221 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3222 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3223 usb_device_request_t *req = &xfer->request; 3224 int len = UGETW(req->wLength); 3225 int rd = req->bmRequestType & UT_READ; 3226 3227 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3228 3229 #ifdef DIAGNOSTIC 3230 if (!(xfer->rqflags & URQ_REQUEST)) { 3231 panic("ehci_ctrl_done: not a request"); 3232 } 3233 #endif 3234 3235 mutex_enter(&sc->sc_intrhead_lock); 3236 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3237 ehci_del_intr_list(sc, ex); /* remove from active list */ 3238 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3239 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3240 BUS_DMASYNC_POSTWRITE); 3241 if (len) 3242 usb_syncmem(&xfer->dmabuf, 0, len, 3243 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3244 } 3245 mutex_exit(&sc->sc_intrhead_lock); 3246 3247 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3248 } 3249 3250 /* Abort a device control request. */ 3251 Static void 3252 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3253 { 3254 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3255 ehci_abort_xfer(xfer, USBD_CANCELLED); 3256 } 3257 3258 /* Close a device control pipe. */ 3259 Static void 3260 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3261 { 3262 ehci_softc_t *sc = pipe->device->bus->hci_private; 3263 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3264 3265 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3266 ehci_close_pipe(pipe, sc->sc_async_head); 3267 } 3268 3269 Static usbd_status 3270 ehci_device_request(usbd_xfer_handle xfer) 3271 { 3272 #define exfer EXFER(xfer) 3273 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3274 usb_device_request_t *req = &xfer->request; 3275 usbd_device_handle dev = epipe->pipe.device; 3276 ehci_softc_t *sc = dev->bus->hci_private; 3277 int addr = dev->address; 3278 ehci_soft_qtd_t *setup, *stat, *next; 3279 ehci_soft_qh_t *sqh; 3280 int isread; 3281 int len; 3282 usbd_status err; 3283 int s; 3284 3285 isread = req->bmRequestType & UT_READ; 3286 len = UGETW(req->wLength); 3287 3288 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3289 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3290 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3291 UGETW(req->wIndex), len, addr, 3292 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3293 3294 setup = ehci_alloc_sqtd(sc); 3295 if (setup == NULL) { 3296 err = USBD_NOMEM; 3297 goto bad1; 3298 } 3299 stat = ehci_alloc_sqtd(sc); 3300 if (stat == NULL) { 3301 err = USBD_NOMEM; 3302 goto bad2; 3303 } 3304 3305 sqh = epipe->sqh; 3306 epipe->u.ctl.length = len; 3307 3308 /* Update device address and length since they may have changed 3309 during the setup of the control pipe in usbd_new_device(). */ 3310 /* XXX This only needs to be done once, but it's too early in open. */ 3311 /* XXXX Should not touch ED here! */ 3312 sqh->qh.qh_endp = 3313 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3314 htole32( 3315 EHCI_QH_SET_ADDR(addr) | 3316 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3317 ); 3318 3319 /* Set up data transaction */ 3320 if (len != 0) { 3321 ehci_soft_qtd_t *end; 3322 3323 /* Start toggle at 1. */ 3324 epipe->nexttoggle = 1; 3325 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3326 &next, &end); 3327 if (err) 3328 goto bad3; 3329 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3330 end->nextqtd = stat; 3331 end->qtd.qtd_next = 3332 end->qtd.qtd_altnext = htole32(stat->physaddr); 3333 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3334 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3335 } else { 3336 next = stat; 3337 } 3338 3339 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3340 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3341 3342 /* Clear toggle */ 3343 setup->qtd.qtd_status = htole32( 3344 EHCI_QTD_ACTIVE | 3345 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3346 EHCI_QTD_SET_CERR(3) | 3347 EHCI_QTD_SET_TOGGLE(0) | 3348 EHCI_QTD_SET_BYTES(sizeof *req) 3349 ); 3350 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3351 setup->qtd.qtd_buffer_hi[0] = 0; 3352 setup->nextqtd = next; 3353 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3354 setup->xfer = xfer; 3355 setup->len = sizeof *req; 3356 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3357 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3358 3359 stat->qtd.qtd_status = htole32( 3360 EHCI_QTD_ACTIVE | 3361 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3362 EHCI_QTD_SET_CERR(3) | 3363 EHCI_QTD_SET_TOGGLE(1) | 3364 EHCI_QTD_IOC 3365 ); 3366 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3367 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3368 stat->nextqtd = NULL; 3369 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3370 stat->xfer = xfer; 3371 stat->len = 0; 3372 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3373 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3374 3375 #ifdef EHCI_DEBUG 3376 if (ehcidebug > 5) { 3377 DPRINTF(("ehci_device_request:\n")); 3378 ehci_dump_sqh(sqh); 3379 ehci_dump_sqtds(setup); 3380 } 3381 #endif 3382 3383 exfer->sqtdstart = setup; 3384 exfer->sqtdend = stat; 3385 #ifdef DIAGNOSTIC 3386 if (!exfer->isdone) { 3387 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3388 } 3389 exfer->isdone = 0; 3390 #endif 3391 3392 /* Insert qTD in QH list. */ 3393 s = splusb(); 3394 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3395 if (xfer->timeout && !sc->sc_bus.use_polling) { 3396 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3397 (ehci_timeout), (xfer)); 3398 } 3399 mutex_enter(&sc->sc_intrhead_lock); 3400 ehci_add_intr_list(sc, exfer); 3401 mutex_exit(&sc->sc_intrhead_lock); 3402 xfer->status = USBD_IN_PROGRESS; 3403 splx(s); 3404 3405 #ifdef EHCI_DEBUG 3406 if (ehcidebug > 10) { 3407 DPRINTF(("ehci_device_request: status=%x\n", 3408 EOREAD4(sc, EHCI_USBSTS))); 3409 delay(10000); 3410 ehci_dump_regs(sc); 3411 ehci_dump_sqh(sc->sc_async_head); 3412 ehci_dump_sqh(sqh); 3413 ehci_dump_sqtds(setup); 3414 } 3415 #endif 3416 3417 return (USBD_NORMAL_COMPLETION); 3418 3419 bad3: 3420 ehci_free_sqtd(sc, stat); 3421 bad2: 3422 ehci_free_sqtd(sc, setup); 3423 bad1: 3424 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3425 xfer->status = err; 3426 usb_transfer_complete(xfer); 3427 return (err); 3428 #undef exfer 3429 } 3430 3431 /* 3432 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3433 * qTD status, or miss signalling occasionally under heavy load. If the host 3434 * machine is too fast, we we can miss transaction completion - when we scan 3435 * the active list the transaction still seems to be active. This generally 3436 * exhibits itself as a umass stall that never recovers. 3437 * 3438 * We work around this behaviour by setting up this callback after any softintr 3439 * that completes with transactions still pending, giving us another chance to 3440 * check for completion after the writeback has taken place. 3441 */ 3442 Static void 3443 ehci_intrlist_timeout(void *arg) 3444 { 3445 ehci_softc_t *sc = arg; 3446 int s = splusb(); 3447 3448 DPRINTF(("ehci_intrlist_timeout\n")); 3449 usb_schedsoftintr(&sc->sc_bus); 3450 3451 splx(s); 3452 } 3453 3454 /************************/ 3455 3456 Static usbd_status 3457 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3458 { 3459 usbd_status err; 3460 3461 /* Insert last in queue. */ 3462 err = usb_insert_transfer(xfer); 3463 if (err) 3464 return (err); 3465 3466 /* Pipe isn't running, start first */ 3467 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3468 } 3469 3470 Static usbd_status 3471 ehci_device_bulk_start(usbd_xfer_handle xfer) 3472 { 3473 #define exfer EXFER(xfer) 3474 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3475 usbd_device_handle dev = epipe->pipe.device; 3476 ehci_softc_t *sc = dev->bus->hci_private; 3477 ehci_soft_qtd_t *data, *dataend; 3478 ehci_soft_qh_t *sqh; 3479 usbd_status err; 3480 int len, isread, endpt; 3481 int s; 3482 3483 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3484 xfer, xfer->length, xfer->flags)); 3485 3486 if (sc->sc_dying) 3487 return (USBD_IOERROR); 3488 3489 #ifdef DIAGNOSTIC 3490 if (xfer->rqflags & URQ_REQUEST) 3491 panic("ehci_device_bulk_start: a request"); 3492 #endif 3493 3494 len = xfer->length; 3495 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3496 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3497 sqh = epipe->sqh; 3498 3499 epipe->u.bulk.length = len; 3500 3501 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3502 &dataend); 3503 if (err) { 3504 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3505 xfer->status = err; 3506 usb_transfer_complete(xfer); 3507 return (err); 3508 } 3509 3510 #ifdef EHCI_DEBUG 3511 if (ehcidebug > 5) { 3512 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3513 ehci_dump_sqh(sqh); 3514 ehci_dump_sqtds(data); 3515 } 3516 #endif 3517 3518 /* Set up interrupt info. */ 3519 exfer->sqtdstart = data; 3520 exfer->sqtdend = dataend; 3521 #ifdef DIAGNOSTIC 3522 if (!exfer->isdone) { 3523 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3524 } 3525 exfer->isdone = 0; 3526 #endif 3527 3528 s = splusb(); 3529 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3530 if (xfer->timeout && !sc->sc_bus.use_polling) { 3531 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3532 (ehci_timeout), (xfer)); 3533 } 3534 mutex_enter(&sc->sc_intrhead_lock); 3535 ehci_add_intr_list(sc, exfer); 3536 mutex_exit(&sc->sc_intrhead_lock); 3537 xfer->status = USBD_IN_PROGRESS; 3538 splx(s); 3539 3540 #ifdef EHCI_DEBUG 3541 if (ehcidebug > 10) { 3542 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3543 delay(10000); 3544 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3545 ehci_dump_regs(sc); 3546 #if 0 3547 printf("async_head:\n"); 3548 ehci_dump_sqh(sc->sc_async_head); 3549 #endif 3550 printf("sqh:\n"); 3551 ehci_dump_sqh(sqh); 3552 ehci_dump_sqtds(data); 3553 } 3554 #endif 3555 3556 if (sc->sc_bus.use_polling) 3557 ehci_waitintr(sc, xfer); 3558 3559 return (USBD_IN_PROGRESS); 3560 #undef exfer 3561 } 3562 3563 Static void 3564 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3565 { 3566 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3567 ehci_abort_xfer(xfer, USBD_CANCELLED); 3568 } 3569 3570 /* 3571 * Close a device bulk pipe. 3572 */ 3573 Static void 3574 ehci_device_bulk_close(usbd_pipe_handle pipe) 3575 { 3576 ehci_softc_t *sc = pipe->device->bus->hci_private; 3577 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3578 3579 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3580 pipe->endpoint->datatoggle = epipe->nexttoggle; 3581 ehci_close_pipe(pipe, sc->sc_async_head); 3582 } 3583 3584 Static void 3585 ehci_device_bulk_done(usbd_xfer_handle xfer) 3586 { 3587 struct ehci_xfer *ex = EXFER(xfer); 3588 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3589 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3590 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3591 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3592 3593 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3594 xfer, xfer->actlen)); 3595 3596 mutex_enter(&sc->sc_intrhead_lock); 3597 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3598 ehci_del_intr_list(sc, ex); /* remove from active list */ 3599 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3600 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3601 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3602 } 3603 mutex_exit(&sc->sc_intrhead_lock); 3604 3605 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3606 } 3607 3608 /************************/ 3609 3610 Static usbd_status 3611 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3612 { 3613 struct ehci_soft_islot *isp; 3614 int islot, lev; 3615 3616 /* Find a poll rate that is large enough. */ 3617 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3618 if (EHCI_ILEV_IVAL(lev) <= ival) 3619 break; 3620 3621 /* Pick an interrupt slot at the right level. */ 3622 /* XXX could do better than picking at random */ 3623 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3624 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3625 3626 sqh->islot = islot; 3627 isp = &sc->sc_islots[islot]; 3628 ehci_add_qh(sqh, isp->sqh); 3629 3630 return (USBD_NORMAL_COMPLETION); 3631 } 3632 3633 Static usbd_status 3634 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3635 { 3636 usbd_status err; 3637 3638 /* Insert last in queue. */ 3639 err = usb_insert_transfer(xfer); 3640 if (err) 3641 return (err); 3642 3643 /* 3644 * Pipe isn't running (otherwise err would be USBD_INPROG), 3645 * so start it first. 3646 */ 3647 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3648 } 3649 3650 Static usbd_status 3651 ehci_device_intr_start(usbd_xfer_handle xfer) 3652 { 3653 #define exfer EXFER(xfer) 3654 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3655 usbd_device_handle dev = xfer->pipe->device; 3656 ehci_softc_t *sc = dev->bus->hci_private; 3657 ehci_soft_qtd_t *data, *dataend; 3658 ehci_soft_qh_t *sqh; 3659 usbd_status err; 3660 int len, isread, endpt; 3661 int s; 3662 3663 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3664 xfer, xfer->length, xfer->flags)); 3665 3666 if (sc->sc_dying) 3667 return (USBD_IOERROR); 3668 3669 #ifdef DIAGNOSTIC 3670 if (xfer->rqflags & URQ_REQUEST) 3671 panic("ehci_device_intr_start: a request"); 3672 #endif 3673 3674 len = xfer->length; 3675 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3676 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3677 sqh = epipe->sqh; 3678 3679 epipe->u.intr.length = len; 3680 3681 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3682 &dataend); 3683 if (err) { 3684 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3685 xfer->status = err; 3686 usb_transfer_complete(xfer); 3687 return (err); 3688 } 3689 3690 #ifdef EHCI_DEBUG 3691 if (ehcidebug > 5) { 3692 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3693 ehci_dump_sqh(sqh); 3694 ehci_dump_sqtds(data); 3695 } 3696 #endif 3697 3698 /* Set up interrupt info. */ 3699 exfer->sqtdstart = data; 3700 exfer->sqtdend = dataend; 3701 #ifdef DIAGNOSTIC 3702 if (!exfer->isdone) { 3703 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3704 } 3705 exfer->isdone = 0; 3706 #endif 3707 3708 s = splusb(); 3709 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3710 if (xfer->timeout && !sc->sc_bus.use_polling) { 3711 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3712 (ehci_timeout), (xfer)); 3713 } 3714 mutex_enter(&sc->sc_intrhead_lock); 3715 ehci_add_intr_list(sc, exfer); 3716 mutex_exit(&sc->sc_intrhead_lock); 3717 xfer->status = USBD_IN_PROGRESS; 3718 splx(s); 3719 3720 #ifdef EHCI_DEBUG 3721 if (ehcidebug > 10) { 3722 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3723 delay(10000); 3724 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3725 ehci_dump_regs(sc); 3726 printf("sqh:\n"); 3727 ehci_dump_sqh(sqh); 3728 ehci_dump_sqtds(data); 3729 } 3730 #endif 3731 3732 if (sc->sc_bus.use_polling) 3733 ehci_waitintr(sc, xfer); 3734 3735 return (USBD_IN_PROGRESS); 3736 #undef exfer 3737 } 3738 3739 Static void 3740 ehci_device_intr_abort(usbd_xfer_handle xfer) 3741 { 3742 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3743 if (xfer->pipe->intrxfer == xfer) { 3744 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3745 xfer->pipe->intrxfer = NULL; 3746 } 3747 /* 3748 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3749 * async doorbell. That's dependant on the async list, wheras 3750 * intr xfers are periodic, should not use this? 3751 */ 3752 ehci_abort_xfer(xfer, USBD_CANCELLED); 3753 } 3754 3755 Static void 3756 ehci_device_intr_close(usbd_pipe_handle pipe) 3757 { 3758 ehci_softc_t *sc = pipe->device->bus->hci_private; 3759 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3760 struct ehci_soft_islot *isp; 3761 3762 isp = &sc->sc_islots[epipe->sqh->islot]; 3763 ehci_close_pipe(pipe, isp->sqh); 3764 } 3765 3766 Static void 3767 ehci_device_intr_done(usbd_xfer_handle xfer) 3768 { 3769 #define exfer EXFER(xfer) 3770 struct ehci_xfer *ex = EXFER(xfer); 3771 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3772 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3773 ehci_soft_qtd_t *data, *dataend; 3774 ehci_soft_qh_t *sqh; 3775 usbd_status err; 3776 int len, isread, endpt, s; 3777 3778 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3779 xfer, xfer->actlen)); 3780 3781 mutex_enter(&sc->sc_intrhead_lock); 3782 if (xfer->pipe->repeat) { 3783 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3784 3785 len = epipe->u.intr.length; 3786 xfer->length = len; 3787 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3788 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3789 usb_syncmem(&xfer->dmabuf, 0, len, 3790 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3791 sqh = epipe->sqh; 3792 3793 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3794 &data, &dataend); 3795 if (err) { 3796 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3797 xfer->status = err; 3798 mutex_exit(&sc->sc_intrhead_lock); 3799 return; 3800 } 3801 3802 /* Set up interrupt info. */ 3803 exfer->sqtdstart = data; 3804 exfer->sqtdend = dataend; 3805 #ifdef DIAGNOSTIC 3806 if (!exfer->isdone) { 3807 printf("ehci_device_intr_done: not done, ex=%p\n", 3808 exfer); 3809 } 3810 exfer->isdone = 0; 3811 #endif 3812 3813 s = splusb(); 3814 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3815 if (xfer->timeout && !sc->sc_bus.use_polling) { 3816 callout_reset(&(xfer->timeout_handle), 3817 (mstohz(xfer->timeout)), (ehci_timeout), (xfer)); 3818 } 3819 splx(s); 3820 3821 xfer->status = USBD_IN_PROGRESS; 3822 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3823 ehci_del_intr_list(sc, ex); /* remove from active list */ 3824 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3825 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3826 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3827 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3828 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3829 } 3830 mutex_exit(&sc->sc_intrhead_lock); 3831 #undef exfer 3832 } 3833 3834 /************************/ 3835 3836 Static usbd_status 3837 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3838 { 3839 usbd_status err; 3840 3841 err = usb_insert_transfer(xfer); 3842 if (err && err != USBD_IN_PROGRESS) 3843 return err; 3844 3845 return ehci_device_isoc_start(xfer); 3846 } 3847 3848 Static usbd_status 3849 ehci_device_isoc_start(usbd_xfer_handle xfer) 3850 { 3851 struct ehci_pipe *epipe; 3852 usbd_device_handle dev; 3853 ehci_softc_t *sc; 3854 struct ehci_xfer *exfer; 3855 ehci_soft_itd_t *itd, *prev, *start, *stop; 3856 usb_dma_t *dma_buf; 3857 int i, j, k, frames, uframes, ufrperframe; 3858 int s, trans_count, offs, total_length; 3859 int frindex; 3860 3861 start = NULL; 3862 prev = NULL; 3863 itd = NULL; 3864 trans_count = 0; 3865 total_length = 0; 3866 exfer = (struct ehci_xfer *) xfer; 3867 sc = xfer->pipe->device->bus->hci_private; 3868 dev = xfer->pipe->device; 3869 epipe = (struct ehci_pipe *)xfer->pipe; 3870 3871 /* 3872 * To allow continuous transfers, above we start all transfers 3873 * immediately. However, we're still going to get usbd_start_next call 3874 * this when another xfer completes. So, check if this is already 3875 * in progress or not 3876 */ 3877 3878 if (exfer->itdstart != NULL) 3879 return USBD_IN_PROGRESS; 3880 3881 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3882 xfer, xfer->length, xfer->flags)); 3883 3884 if (sc->sc_dying) 3885 return USBD_IOERROR; 3886 3887 /* 3888 * To avoid complication, don't allow a request right now that'll span 3889 * the entire frame table. To within 4 frames, to allow some leeway 3890 * on either side of where the hc currently is. 3891 */ 3892 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3893 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3894 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3895 return USBD_INVAL; 3896 } 3897 3898 #ifdef DIAGNOSTIC 3899 if (xfer->rqflags & URQ_REQUEST) 3900 panic("ehci_device_isoc_start: request\n"); 3901 3902 if (!exfer->isdone) 3903 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3904 exfer->isdone = 0; 3905 #endif 3906 3907 /* 3908 * Step 1: Allocate and initialize itds, how many do we need? 3909 * One per transfer if interval >= 8 microframes, fewer if we use 3910 * multiple microframes per frame. 3911 */ 3912 3913 i = epipe->pipe.endpoint->edesc->bInterval; 3914 if (i > 16 || i == 0) { 3915 /* Spec page 271 says intervals > 16 are invalid */ 3916 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3917 return USBD_INVAL; 3918 } 3919 3920 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 3921 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3922 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 3923 3924 if (frames == 0) { 3925 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3926 return USBD_INVAL; 3927 } 3928 3929 dma_buf = &xfer->dmabuf; 3930 offs = 0; 3931 3932 for (i = 0; i < frames; i++) { 3933 int froffs = offs; 3934 itd = ehci_alloc_itd(sc); 3935 3936 if (prev != NULL) { 3937 prev->itd.itd_next = 3938 htole32(itd->physaddr | EHCI_LINK_ITD); 3939 usb_syncmem(&itd->dma, 3940 itd->offs + offsetof(ehci_itd_t, itd_next), 3941 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 3942 3943 prev->xfer_next = itd; 3944 } else { 3945 start = itd; 3946 } 3947 3948 /* 3949 * Step 1.5, initialize uframes 3950 */ 3951 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 3952 /* Calculate which page in the list this starts in */ 3953 int addr = DMAADDR(dma_buf, froffs); 3954 addr = EHCI_PAGE_OFFSET(addr); 3955 addr += (offs - froffs); 3956 addr = EHCI_PAGE(addr); 3957 addr /= EHCI_PAGE_SIZE; 3958 3959 /* This gets the initial offset into the first page, 3960 * looks how far further along the current uframe 3961 * offset is. Works out how many pages that is. 3962 */ 3963 3964 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3965 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3966 EHCI_ITD_SET_PG(addr) | 3967 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 3968 3969 total_length += xfer->frlengths[trans_count]; 3970 offs += xfer->frlengths[trans_count]; 3971 trans_count++; 3972 3973 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3974 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3975 break; 3976 } 3977 } 3978 3979 /* Step 1.75, set buffer pointers. To simplify matters, all 3980 * pointers are filled out for the next 7 hardware pages in 3981 * the dma block, so no need to worry what pages to cover 3982 * and what to not. 3983 */ 3984 3985 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 3986 /* 3987 * Don't try to lookup a page that's past the end 3988 * of buffer 3989 */ 3990 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 3991 if (page_offs >= dma_buf->block->size) 3992 break; 3993 3994 long long page = DMAADDR(dma_buf, page_offs); 3995 page = EHCI_PAGE(page); 3996 itd->itd.itd_bufr[j] = 3997 htole32(EHCI_ITD_SET_BPTR(page)); 3998 itd->itd.itd_bufr_hi[j] = 3999 htole32(page >> 32); 4000 } 4001 4002 /* 4003 * Other special values 4004 */ 4005 4006 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4007 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4008 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4009 4010 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4011 ? 1 : 0; 4012 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4013 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4014 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4015 4016 /* FIXME: handle invalid trans */ 4017 itd->itd.itd_bufr[2] |= 4018 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4019 4020 usb_syncmem(&itd->dma, 4021 itd->offs + offsetof(ehci_itd_t, itd_next), 4022 sizeof(ehci_itd_t), 4023 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4024 4025 prev = itd; 4026 } /* End of frame */ 4027 4028 stop = itd; 4029 stop->xfer_next = NULL; 4030 exfer->isoc_len = total_length; 4031 4032 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4033 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4034 4035 /* 4036 * Part 2: Transfer descriptors have now been set up, now they must 4037 * be scheduled into the period frame list. Erk. Not wanting to 4038 * complicate matters, transfer is denied if the transfer spans 4039 * more than the period frame list. 4040 */ 4041 4042 s = splusb(); 4043 4044 /* Start inserting frames */ 4045 if (epipe->u.isoc.cur_xfers > 0) { 4046 frindex = epipe->u.isoc.next_frame; 4047 } else { 4048 frindex = EOREAD4(sc, EHCI_FRINDEX); 4049 frindex = frindex >> 3; /* Erase microframe index */ 4050 frindex += 2; 4051 } 4052 4053 if (frindex >= sc->sc_flsize) 4054 frindex &= (sc->sc_flsize - 1); 4055 4056 /* What's the frame interval? */ 4057 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4058 if (i / USB_UFRAMES_PER_FRAME == 0) 4059 i = 1; 4060 else 4061 i /= USB_UFRAMES_PER_FRAME; 4062 4063 itd = start; 4064 for (j = 0; j < frames; j++) { 4065 if (itd == NULL) 4066 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4067 4068 itd->itd.itd_next = sc->sc_flist[frindex]; 4069 if (itd->itd.itd_next == 0) 4070 /* FIXME: frindex table gets initialized to NULL 4071 * or EHCI_NULL? */ 4072 itd->itd.itd_next = EHCI_NULL; 4073 4074 usb_syncmem(&itd->dma, 4075 itd->offs + offsetof(ehci_itd_t, itd_next), 4076 sizeof(itd->itd.itd_next), 4077 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4078 4079 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4080 4081 usb_syncmem(&sc->sc_fldma, 4082 sizeof(ehci_link_t) * frindex, 4083 sizeof(ehci_link_t), 4084 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4085 4086 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4087 sc->sc_softitds[frindex] = itd; 4088 if (itd->u.frame_list.next != NULL) 4089 itd->u.frame_list.next->u.frame_list.prev = itd; 4090 itd->slot = frindex; 4091 itd->u.frame_list.prev = NULL; 4092 4093 frindex += i; 4094 if (frindex >= sc->sc_flsize) 4095 frindex -= sc->sc_flsize; 4096 4097 itd = itd->xfer_next; 4098 } 4099 4100 epipe->u.isoc.cur_xfers++; 4101 epipe->u.isoc.next_frame = frindex; 4102 4103 exfer->itdstart = start; 4104 exfer->itdend = stop; 4105 exfer->sqtdstart = NULL; 4106 exfer->sqtdstart = NULL; 4107 4108 mutex_enter(&sc->sc_intrhead_lock); 4109 ehci_add_intr_list(sc, exfer); 4110 mutex_exit(&sc->sc_intrhead_lock); 4111 xfer->status = USBD_IN_PROGRESS; 4112 xfer->done = 0; 4113 splx(s); 4114 4115 if (sc->sc_bus.use_polling) { 4116 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4117 ehci_waitintr(sc, xfer); 4118 } 4119 4120 return USBD_IN_PROGRESS; 4121 } 4122 4123 Static void 4124 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4125 { 4126 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4127 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4128 } 4129 4130 Static void 4131 ehci_device_isoc_close(usbd_pipe_handle pipe) 4132 { 4133 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4134 } 4135 4136 Static void 4137 ehci_device_isoc_done(usbd_xfer_handle xfer) 4138 { 4139 struct ehci_xfer *exfer; 4140 ehci_softc_t *sc; 4141 struct ehci_pipe *epipe; 4142 int s; 4143 4144 exfer = EXFER(xfer); 4145 sc = xfer->pipe->device->bus->hci_private; 4146 epipe = (struct ehci_pipe *) xfer->pipe; 4147 4148 s = splusb(); 4149 epipe->u.isoc.cur_xfers--; 4150 mutex_enter(&sc->sc_intrhead_lock); 4151 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4152 ehci_del_intr_list(sc, exfer); 4153 ehci_rem_free_itd_chain(sc, exfer); 4154 } 4155 mutex_exit(&sc->sc_intrhead_lock); 4156 splx(s); 4157 4158 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4159 BUS_DMASYNC_POSTREAD); 4160 4161 } 4162
Indexes created Thu Oct 02 01:09:59 GMT 2025