ehci.c revision 1.181.6.1
1 /* $NetBSD: ehci.c,v 1.181.6.1 2011/12/04 13:23:16 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2011 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), and Jared D. McNeill 10 * (jmcneill (at) invisible.ca). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.181.6.1 2011/12/04 13:23:16 jmcneill Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/kmem.h> 66 #include <sys/device.h> 67 #include <sys/select.h> 68 #include <sys/proc.h> 69 #include <sys/queue.h> 70 #include <sys/mutex.h> 71 #include <sys/bus.h> 72 73 #include <machine/endian.h> 74 75 #include <dev/usb/usb.h> 76 #include <dev/usb/usbdi.h> 77 #include <dev/usb/usbdivar.h> 78 #include <dev/usb/usb_mem.h> 79 #include <dev/usb/usb_quirks.h> 80 81 #include <dev/usb/ehcireg.h> 82 #include <dev/usb/ehcivar.h> 83 #include <dev/usb/usbroothub_subr.h> 84 85 #ifdef EHCI_DEBUG 86 #include <sys/kprintf.h> 87 static void 88 ehciprintf(const char *fmt, ...) 89 { 90 va_list ap; 91 92 va_start(ap, fmt); 93 kprintf(fmt, TOLOG|TOCONS, NULL, NULL, ap); 94 va_end(ap); 95 } 96 97 #define DPRINTF(x) do { if (ehcidebug) ehciprintf x; } while(0) 98 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) ehciprintf x; } while (0) 99 int ehcidebug = 0; 100 #else 101 #define DPRINTF(x) 102 #define DPRINTFN(n,x) 103 #endif 104 105 struct ehci_pipe { 106 struct usbd_pipe pipe; 107 int nexttoggle; 108 109 ehci_soft_qh_t *sqh; 110 union { 111 ehci_soft_qtd_t *qtd; 112 /* ehci_soft_itd_t *itd; */ 113 } tail; 114 union { 115 /* Control pipe */ 116 struct { 117 usb_dma_t reqdma; 118 u_int length; 119 } ctl; 120 /* Interrupt pipe */ 121 struct { 122 u_int length; 123 } intr; 124 /* Bulk pipe */ 125 struct { 126 u_int length; 127 } bulk; 128 /* Iso pipe */ 129 struct { 130 u_int next_frame; 131 u_int cur_xfers; 132 } isoc; 133 } u; 134 }; 135 136 Static usbd_status ehci_open(usbd_pipe_handle); 137 Static void ehci_poll(struct usbd_bus *); 138 Static void ehci_softintr(void *); 139 Static int ehci_intr1(ehci_softc_t *); 140 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 141 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 142 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 143 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 144 Static void ehci_idone(struct ehci_xfer *); 145 Static void ehci_timeout(void *); 146 Static void ehci_timeout_task(void *); 147 Static void ehci_intrlist_timeout(void *); 148 Static void ehci_doorbell(void *); 149 Static void ehci_pcd(void *); 150 151 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 152 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 153 154 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 155 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 156 Static void ehci_get_locks(struct usbd_bus *, kmutex_t **, 157 kmutex_t **); 158 159 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 160 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 161 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 162 Static void ehci_root_ctrl_close(usbd_pipe_handle); 163 Static void ehci_root_ctrl_done(usbd_xfer_handle); 164 165 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 166 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 167 Static void ehci_root_intr_abort(usbd_xfer_handle); 168 Static void ehci_root_intr_close(usbd_pipe_handle); 169 Static void ehci_root_intr_done(usbd_xfer_handle); 170 171 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 172 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 173 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 174 Static void ehci_device_ctrl_close(usbd_pipe_handle); 175 Static void ehci_device_ctrl_done(usbd_xfer_handle); 176 177 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 178 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 179 Static void ehci_device_bulk_abort(usbd_xfer_handle); 180 Static void ehci_device_bulk_close(usbd_pipe_handle); 181 Static void ehci_device_bulk_done(usbd_xfer_handle); 182 183 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 184 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 185 Static void ehci_device_intr_abort(usbd_xfer_handle); 186 Static void ehci_device_intr_close(usbd_pipe_handle); 187 Static void ehci_device_intr_done(usbd_xfer_handle); 188 189 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 190 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 191 Static void ehci_device_isoc_abort(usbd_xfer_handle); 192 Static void ehci_device_isoc_close(usbd_pipe_handle); 193 Static void ehci_device_isoc_done(usbd_xfer_handle); 194 195 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 196 Static void ehci_noop(usbd_pipe_handle pipe); 197 198 Static void ehci_disown(ehci_softc_t *, int, int); 199 200 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 201 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 202 203 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 204 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 205 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 206 ehci_softc_t *, int, int, usbd_xfer_handle, 207 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 208 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 209 ehci_soft_qtd_t *); 210 211 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 212 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 213 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 214 struct ehci_xfer *exfer); 215 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 216 usbd_status status); 217 218 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 219 220 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 221 int ival); 222 223 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 224 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 225 ehci_soft_qh_t *); 226 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 227 Static void ehci_sync_hc(ehci_softc_t *); 228 229 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 230 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 231 232 #ifdef EHCI_DEBUG 233 Static void ehci_dump_regs(ehci_softc_t *); 234 void ehci_dump(void); 235 Static ehci_softc_t *theehci; 236 Static void ehci_dump_link(ehci_link_t, int); 237 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 238 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 239 Static void ehci_dump_qtd(ehci_qtd_t *); 240 Static void ehci_dump_sqh(ehci_soft_qh_t *); 241 #if notyet 242 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 243 Static void ehci_dump_itd(struct ehci_soft_itd *); 244 #endif 245 #ifdef DIAGNOSTIC 246 Static void ehci_dump_exfer(struct ehci_xfer *); 247 #endif 248 #endif 249 250 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 251 252 #define EHCI_INTR_ENDPT 1 253 254 #define ehci_add_intr_list(sc, ex) \ 255 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 256 #define ehci_del_intr_list(sc, ex) \ 257 do { \ 258 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 259 (ex)->inext.tqe_prev = NULL; \ 260 } while (0) 261 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 262 263 Static const struct usbd_bus_methods ehci_bus_methods = { 264 ehci_open, 265 ehci_softintr, 266 ehci_poll, 267 ehci_allocm, 268 ehci_freem, 269 ehci_allocx, 270 ehci_freex, 271 ehci_get_locks, 272 }; 273 274 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 275 ehci_root_ctrl_transfer, 276 ehci_root_ctrl_start, 277 ehci_root_ctrl_abort, 278 ehci_root_ctrl_close, 279 ehci_noop, 280 ehci_root_ctrl_done, 281 }; 282 283 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 284 ehci_root_intr_transfer, 285 ehci_root_intr_start, 286 ehci_root_intr_abort, 287 ehci_root_intr_close, 288 ehci_noop, 289 ehci_root_intr_done, 290 }; 291 292 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 293 ehci_device_ctrl_transfer, 294 ehci_device_ctrl_start, 295 ehci_device_ctrl_abort, 296 ehci_device_ctrl_close, 297 ehci_noop, 298 ehci_device_ctrl_done, 299 }; 300 301 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 302 ehci_device_intr_transfer, 303 ehci_device_intr_start, 304 ehci_device_intr_abort, 305 ehci_device_intr_close, 306 ehci_device_clear_toggle, 307 ehci_device_intr_done, 308 }; 309 310 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 311 ehci_device_bulk_transfer, 312 ehci_device_bulk_start, 313 ehci_device_bulk_abort, 314 ehci_device_bulk_close, 315 ehci_device_clear_toggle, 316 ehci_device_bulk_done, 317 }; 318 319 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 320 ehci_device_isoc_transfer, 321 ehci_device_isoc_start, 322 ehci_device_isoc_abort, 323 ehci_device_isoc_close, 324 ehci_noop, 325 ehci_device_isoc_done, 326 }; 327 328 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 329 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 330 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 331 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 332 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 333 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 334 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 335 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 336 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 337 }; 338 339 usbd_status 340 ehci_init(ehci_softc_t *sc) 341 { 342 u_int32_t vers, sparams, cparams, hcr; 343 u_int i; 344 usbd_status err; 345 ehci_soft_qh_t *sqh; 346 u_int ncomp; 347 348 DPRINTF(("ehci_init: start\n")); 349 #ifdef EHCI_DEBUG 350 theehci = sc; 351 #endif 352 353 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 354 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 355 cv_init(&sc->sc_softwake_cv, "ehciab"); 356 cv_init(&sc->sc_doorbell, "ehcidi"); 357 358 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 359 ehci_doorbell, sc); 360 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 361 ehci_pcd, sc); 362 363 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 364 365 vers = EREAD2(sc, EHCI_HCIVERSION); 366 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 367 vers >> 8, vers & 0xff); 368 369 sparams = EREAD4(sc, EHCI_HCSPARAMS); 370 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 371 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 372 ncomp = EHCI_HCS_N_CC(sparams); 373 if (ncomp != sc->sc_ncomp) { 374 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 375 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 376 #if NOHCI == 0 || NUHCI == 0 377 aprint_error("%s: ohci or uhci probably not configured\n", 378 device_xname(sc->sc_dev)); 379 #endif 380 if (ncomp < sc->sc_ncomp) 381 sc->sc_ncomp = ncomp; 382 } 383 if (sc->sc_ncomp > 0) { 384 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 385 aprint_normal("%s: companion controller%s, %d port%s each:", 386 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 387 EHCI_HCS_N_PCC(sparams), 388 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 389 for (i = 0; i < sc->sc_ncomp; i++) 390 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 391 aprint_normal("\n"); 392 } 393 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 394 cparams = EREAD4(sc, EHCI_HCCPARAMS); 395 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 396 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 397 398 if (EHCI_HCC_64BIT(cparams)) { 399 /* MUST clear segment register if 64 bit capable. */ 400 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 401 } 402 403 sc->sc_bus.usbrev = USBREV_2_0; 404 405 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 406 USB_MEM_RESERVE); 407 408 /* Reset the controller */ 409 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 410 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 411 usb_delay_ms(&sc->sc_bus, 1); 412 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 413 for (i = 0; i < 100; i++) { 414 usb_delay_ms(&sc->sc_bus, 1); 415 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 416 if (!hcr) 417 break; 418 } 419 if (hcr) { 420 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 421 return (USBD_IOERROR); 422 } 423 if (sc->sc_vendor_init) 424 sc->sc_vendor_init(sc); 425 426 /* 427 * If we are doing embedded transaction translation function, force 428 * the controller to host mode. 429 */ 430 if (sc->sc_flags & EHCIF_ETTF) { 431 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 432 usbmode &= ~EHCI_USBMODE_CM; 433 usbmode |= EHCI_USBMODE_CM_HOST; 434 EWRITE4(sc, EHCI_USBMODE, usbmode); 435 } 436 437 /* XXX need proper intr scheduling */ 438 sc->sc_rand = 96; 439 440 /* frame list size at default, read back what we got and use that */ 441 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 442 case 0: sc->sc_flsize = 1024; break; 443 case 1: sc->sc_flsize = 512; break; 444 case 2: sc->sc_flsize = 256; break; 445 case 3: return (USBD_IOERROR); 446 } 447 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 448 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 449 if (err) 450 return (err); 451 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 452 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 453 454 for (i = 0; i < sc->sc_flsize; i++) { 455 sc->sc_flist[i] = EHCI_NULL; 456 } 457 458 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 459 460 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 461 KM_SLEEP); 462 if (sc->sc_softitds == NULL) 463 return ENOMEM; 464 LIST_INIT(&sc->sc_freeitds); 465 TAILQ_INIT(&sc->sc_intrhead); 466 467 /* Set up the bus struct. */ 468 sc->sc_bus.methods = &ehci_bus_methods; 469 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 470 471 sc->sc_eintrs = EHCI_NORMAL_INTRS; 472 473 /* 474 * Allocate the interrupt dummy QHs. These are arranged to give poll 475 * intervals that are powers of 2 times 1ms. 476 */ 477 for (i = 0; i < EHCI_INTRQHS; i++) { 478 sqh = ehci_alloc_sqh(sc); 479 if (sqh == NULL) { 480 err = USBD_NOMEM; 481 goto bad1; 482 } 483 sc->sc_islots[i].sqh = sqh; 484 } 485 for (i = 0; i < EHCI_INTRQHS; i++) { 486 sqh = sc->sc_islots[i].sqh; 487 if (i == 0) { 488 /* The last (1ms) QH terminates. */ 489 sqh->qh.qh_link = EHCI_NULL; 490 sqh->next = NULL; 491 } else { 492 /* Otherwise the next QH has half the poll interval */ 493 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 494 sqh->qh.qh_link = htole32(sqh->next->physaddr | 495 EHCI_LINK_QH); 496 } 497 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 498 sqh->qh.qh_curqtd = EHCI_NULL; 499 sqh->next = NULL; 500 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 501 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 502 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 503 sqh->sqtd = NULL; 504 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 505 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 506 } 507 /* Point the frame list at the last level (128ms). */ 508 for (i = 0; i < sc->sc_flsize; i++) { 509 int j; 510 511 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 512 revbits[i & (EHCI_MAX_POLLRATE-1)]; 513 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 514 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 515 i)].sqh->physaddr); 516 } 517 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 518 BUS_DMASYNC_PREWRITE); 519 520 /* Allocate dummy QH that starts the async list. */ 521 sqh = ehci_alloc_sqh(sc); 522 if (sqh == NULL) { 523 err = USBD_NOMEM; 524 goto bad1; 525 } 526 /* Fill the QH */ 527 sqh->qh.qh_endp = 528 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 529 sqh->qh.qh_link = 530 htole32(sqh->physaddr | EHCI_LINK_QH); 531 sqh->qh.qh_curqtd = EHCI_NULL; 532 sqh->next = NULL; 533 /* Fill the overlay qTD */ 534 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 535 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 536 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 537 sqh->sqtd = NULL; 538 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 539 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 540 #ifdef EHCI_DEBUG 541 if (ehcidebug) { 542 ehci_dump_sqh(sqh); 543 } 544 #endif 545 546 /* Point to async list */ 547 sc->sc_async_head = sqh; 548 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 549 550 callout_init(&(sc->sc_tmo_intrlist), CALLOUT_MPSAFE); 551 552 /* Turn on controller */ 553 EOWRITE4(sc, EHCI_USBCMD, 554 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 555 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 556 EHCI_CMD_ASE | 557 EHCI_CMD_PSE | 558 EHCI_CMD_RS); 559 560 /* Take over port ownership */ 561 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 562 563 for (i = 0; i < 100; i++) { 564 usb_delay_ms(&sc->sc_bus, 1); 565 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 566 if (!hcr) 567 break; 568 } 569 if (hcr) { 570 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 571 return (USBD_IOERROR); 572 } 573 574 /* Enable interrupts */ 575 DPRINTFN(1,("ehci_init: enabling\n")); 576 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 577 578 return (USBD_NORMAL_COMPLETION); 579 580 #if 0 581 bad2: 582 ehci_free_sqh(sc, sc->sc_async_head); 583 #endif 584 bad1: 585 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 586 return (err); 587 } 588 589 int 590 ehci_intr(void *v) 591 { 592 ehci_softc_t *sc = v; 593 int ret = 0; 594 595 if (sc == NULL) 596 return 0; 597 598 mutex_spin_enter(&sc->sc_intr_lock); 599 600 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 601 goto done; 602 603 /* If we get an interrupt while polling, then just ignore it. */ 604 if (sc->sc_bus.use_polling) { 605 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 606 607 if (intrs) 608 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 609 #ifdef DIAGNOSTIC 610 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 611 #endif 612 goto done; 613 } 614 615 ret = ehci_intr1(sc); 616 617 done: 618 mutex_spin_exit(&sc->sc_intr_lock); 619 return ret; 620 } 621 622 Static int 623 ehci_intr1(ehci_softc_t *sc) 624 { 625 u_int32_t intrs, eintrs; 626 627 DPRINTFN(20,("ehci_intr1: enter\n")); 628 629 /* In case the interrupt occurs before initialization has completed. */ 630 if (sc == NULL) { 631 #ifdef DIAGNOSTIC 632 printf("ehci_intr1: sc == NULL\n"); 633 #endif 634 return (0); 635 } 636 637 KASSERT(mutex_owned(&sc->sc_intr_lock)); 638 639 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 640 if (!intrs) 641 return (0); 642 643 eintrs = intrs & sc->sc_eintrs; 644 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 645 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 646 (u_int)eintrs)); 647 if (!eintrs) 648 return (0); 649 650 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 651 sc->sc_bus.intr_context++; 652 sc->sc_bus.no_intrs++; 653 if (eintrs & EHCI_STS_IAA) { 654 DPRINTF(("ehci_intr1: door bell\n")); 655 softint_schedule(sc->sc_doorbell_si); 656 eintrs &= ~EHCI_STS_IAA; 657 } 658 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 659 DPRINTFN(5,("ehci_intr1: %s %s\n", 660 eintrs & EHCI_STS_INT ? "INT" : "", 661 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 662 usb_schedsoftintr(&sc->sc_bus); 663 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 664 } 665 if (eintrs & EHCI_STS_HSE) { 666 printf("%s: unrecoverable error, controller halted\n", 667 device_xname(sc->sc_dev)); 668 /* XXX what else */ 669 } 670 if (eintrs & EHCI_STS_PCD) { 671 softint_schedule(sc->sc_pcd_si); 672 eintrs &= ~EHCI_STS_PCD; 673 } 674 675 sc->sc_bus.intr_context--; 676 677 if (eintrs != 0) { 678 /* Block unprocessed interrupts. */ 679 sc->sc_eintrs &= ~eintrs; 680 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 681 printf("%s: blocking intrs 0x%x\n", 682 device_xname(sc->sc_dev), eintrs); 683 } 684 685 return (1); 686 } 687 688 Static void 689 ehci_doorbell(void *addr) 690 { 691 ehci_softc_t *sc = addr; 692 693 mutex_enter(&sc->sc_lock); 694 cv_broadcast(&sc->sc_doorbell); 695 mutex_exit(&sc->sc_lock); 696 } 697 698 Static void 699 ehci_pcd(void *addr) 700 { 701 ehci_softc_t *sc = addr; 702 usbd_xfer_handle xfer; 703 usbd_pipe_handle pipe; 704 u_char *p; 705 int i, m; 706 707 mutex_enter(&sc->sc_lock); 708 xfer = sc->sc_intrxfer; 709 710 if (xfer == NULL) { 711 /* Just ignore the change. */ 712 goto done; 713 } 714 715 pipe = xfer->pipe; 716 717 p = KERNADDR(&xfer->dmabuf, 0); 718 m = min(sc->sc_noport, xfer->length * 8 - 1); 719 memset(p, 0, xfer->length); 720 for (i = 1; i <= m; i++) { 721 /* Pick out CHANGE bits from the status reg. */ 722 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 723 p[i/8] |= 1 << (i%8); 724 } 725 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 726 xfer->actlen = xfer->length; 727 xfer->status = USBD_NORMAL_COMPLETION; 728 729 usb_transfer_complete(xfer); 730 731 done: 732 mutex_exit(&sc->sc_lock); 733 } 734 735 Static void 736 ehci_softintr(void *v) 737 { 738 struct usbd_bus *bus = v; 739 ehci_softc_t *sc = bus->hci_private; 740 struct ehci_xfer *ex, *nextex; 741 742 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 743 sc->sc_bus.intr_context)); 744 745 mutex_enter(&sc->sc_lock); 746 747 sc->sc_bus.intr_context++; 748 749 /* 750 * The only explanation I can think of for why EHCI is as brain dead 751 * as UHCI interrupt-wise is that Intel was involved in both. 752 * An interrupt just tells us that something is done, we have no 753 * clue what, so we need to scan through all active transfers. :-( 754 */ 755 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 756 nextex = TAILQ_NEXT(ex, inext); 757 ehci_check_intr(sc, ex); 758 } 759 760 /* Schedule a callout to catch any dropped transactions. */ 761 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 762 !TAILQ_EMPTY(&sc->sc_intrhead)) 763 callout_reset(&(sc->sc_tmo_intrlist), 764 (hz), (ehci_intrlist_timeout), (sc)); 765 766 if (sc->sc_softwake) { 767 sc->sc_softwake = 0; 768 cv_broadcast(&sc->sc_softwake_cv); 769 } 770 771 sc->sc_bus.intr_context--; 772 773 mutex_exit(&sc->sc_lock); 774 } 775 776 /* Check for an interrupt. */ 777 Static void 778 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 779 { 780 int attr; 781 782 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 783 784 KASSERT(mutex_owned(&sc->sc_lock)); 785 786 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 787 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 788 ehci_check_itd_intr(sc, ex); 789 else 790 ehci_check_qh_intr(sc, ex); 791 792 return; 793 } 794 795 Static void 796 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 797 { 798 ehci_soft_qtd_t *sqtd, *lsqtd; 799 __uint32_t status; 800 801 KASSERT(mutex_owned(&sc->sc_lock)); 802 803 if (ex->sqtdstart == NULL) { 804 printf("ehci_check_qh_intr: not valid sqtd\n"); 805 return; 806 } 807 808 lsqtd = ex->sqtdend; 809 #ifdef DIAGNOSTIC 810 if (lsqtd == NULL) { 811 printf("ehci_check_qh_intr: lsqtd==0\n"); 812 return; 813 } 814 #endif 815 /* 816 * If the last TD is still active we need to check whether there 817 * is a an error somewhere in the middle, or whether there was a 818 * short packet (SPD and not ACTIVE). 819 */ 820 usb_syncmem(&lsqtd->dma, 821 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 822 sizeof(lsqtd->qtd.qtd_status), 823 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 824 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 825 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 826 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 827 usb_syncmem(&sqtd->dma, 828 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 829 sizeof(sqtd->qtd.qtd_status), 830 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 831 status = le32toh(sqtd->qtd.qtd_status); 832 usb_syncmem(&sqtd->dma, 833 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 834 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 835 /* If there's an active QTD the xfer isn't done. */ 836 if (status & EHCI_QTD_ACTIVE) 837 break; 838 /* Any kind of error makes the xfer done. */ 839 if (status & EHCI_QTD_HALTED) 840 goto done; 841 /* We want short packets, and it is short: it's done */ 842 if (EHCI_QTD_GET_BYTES(status) != 0) 843 goto done; 844 } 845 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 846 ex, ex->sqtdstart)); 847 usb_syncmem(&lsqtd->dma, 848 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 849 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 850 return; 851 } 852 done: 853 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 854 callout_stop(&ex->xfer.timeout_handle); 855 ehci_idone(ex); 856 } 857 858 Static void 859 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 860 ehci_soft_itd_t *itd; 861 int i; 862 863 KASSERT(mutex_owned(&sc->sc_lock)); 864 865 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 866 return; 867 868 if (ex->itdstart == NULL) { 869 printf("ehci_check_itd_intr: not valid itd\n"); 870 return; 871 } 872 873 itd = ex->itdend; 874 #ifdef DIAGNOSTIC 875 if (itd == NULL) { 876 printf("ehci_check_itd_intr: itdend == 0\n"); 877 return; 878 } 879 #endif 880 881 /* 882 * check no active transfers in last itd, meaning we're finished 883 */ 884 885 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 886 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 887 BUS_DMASYNC_POSTREAD); 888 889 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 890 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 891 break; 892 } 893 894 if (i == EHCI_ITD_NUFRAMES) { 895 goto done; /* All 8 descriptors inactive, it's done */ 896 } 897 898 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 899 ex->itdstart)); 900 return; 901 done: 902 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 903 callout_stop(&ex->xfer.timeout_handle); 904 ehci_idone(ex); 905 } 906 907 Static void 908 ehci_idone(struct ehci_xfer *ex) 909 { 910 usbd_xfer_handle xfer = &ex->xfer; 911 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 912 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 913 ehci_soft_qtd_t *sqtd, *lsqtd; 914 u_int32_t status = 0, nstatus = 0; 915 int actlen; 916 917 KASSERT(mutex_owned(&sc->sc_lock)); 918 919 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 920 921 #ifdef DIAGNOSTIC 922 { 923 if (ex->isdone) { 924 #ifdef EHCI_DEBUG 925 printf("ehci_idone: ex is done!\n "); 926 ehci_dump_exfer(ex); 927 #else 928 printf("ehci_idone: ex=%p is done!\n", ex); 929 #endif 930 return; 931 } 932 ex->isdone = 1; 933 } 934 #endif 935 if (xfer->status == USBD_CANCELLED || 936 xfer->status == USBD_TIMEOUT) { 937 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 938 return; 939 } 940 941 #ifdef EHCI_DEBUG 942 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 943 if (ehcidebug > 10) 944 ehci_dump_sqtds(ex->sqtdstart); 945 #endif 946 947 /* The transfer is done, compute actual length and status. */ 948 949 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 950 == UE_ISOCHRONOUS) { 951 /* Isoc transfer */ 952 struct ehci_soft_itd *itd; 953 int i, nframes, len, uframes; 954 955 nframes = 0; 956 actlen = 0; 957 958 i = xfer->pipe->endpoint->edesc->bInterval; 959 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 960 961 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 962 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 963 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 964 BUS_DMASYNC_POSTREAD); 965 966 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 967 /* XXX - driver didn't fill in the frame full 968 * of uframes. This leads to scheduling 969 * inefficiencies, but working around 970 * this doubles complexity of tracking 971 * an xfer. 972 */ 973 if (nframes >= xfer->nframes) 974 break; 975 976 status = le32toh(itd->itd.itd_ctl[i]); 977 len = EHCI_ITD_GET_LEN(status); 978 if (EHCI_ITD_GET_STATUS(status) != 0) 979 len = 0; /*No valid data on error*/ 980 981 xfer->frlengths[nframes++] = len; 982 actlen += len; 983 } 984 985 if (nframes >= xfer->nframes) 986 break; 987 } 988 989 xfer->actlen = actlen; 990 xfer->status = USBD_NORMAL_COMPLETION; 991 goto end; 992 } 993 994 /* Continue processing xfers using queue heads */ 995 996 lsqtd = ex->sqtdend; 997 actlen = 0; 998 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 999 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1000 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1001 nstatus = le32toh(sqtd->qtd.qtd_status); 1002 if (nstatus & EHCI_QTD_ACTIVE) 1003 break; 1004 1005 status = nstatus; 1006 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1007 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1008 } 1009 1010 1011 /* 1012 * If there are left over TDs we need to update the toggle. 1013 * The default pipe doesn't need it since control transfers 1014 * start the toggle at 0 every time. 1015 * For a short transfer we need to update the toggle for the missing 1016 * packets within the qTD. 1017 */ 1018 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1019 xfer->pipe->device->default_pipe != xfer->pipe) { 1020 DPRINTFN(2, ("ehci_idone: need toggle update " 1021 "status=%08x nstatus=%08x\n", status, nstatus)); 1022 #if 0 1023 ehci_dump_sqh(epipe->sqh); 1024 ehci_dump_sqtds(ex->sqtdstart); 1025 #endif 1026 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1027 } 1028 1029 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 1030 xfer->length, actlen, status)); 1031 xfer->actlen = actlen; 1032 if (status & EHCI_QTD_HALTED) { 1033 #ifdef EHCI_DEBUG 1034 char sbuf[128]; 1035 1036 snprintb(sbuf, sizeof(sbuf), 1037 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 1038 (u_int32_t)status); 1039 1040 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 1041 "status 0x%s\n", 1042 xfer->pipe->device->address, 1043 xfer->pipe->endpoint->edesc->bEndpointAddress, 1044 sbuf)); 1045 if (ehcidebug > 2) { 1046 ehci_dump_sqh(epipe->sqh); 1047 ehci_dump_sqtds(ex->sqtdstart); 1048 } 1049 #endif 1050 /* low&full speed has an extra error flag */ 1051 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1052 EHCI_QH_SPEED_HIGH) 1053 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1054 else 1055 status &= EHCI_QTD_STATERRS; 1056 if (status == 0) /* no other errors means a stall */ { 1057 xfer->status = USBD_STALLED; 1058 } else { 1059 xfer->status = USBD_IOERROR; /* more info XXX */ 1060 } 1061 /* XXX need to reset TT on missed microframe */ 1062 if (status & EHCI_QTD_MISSEDMICRO) { 1063 printf("%s: missed microframe, TT reset not " 1064 "implemented, hub might be inoperational\n", 1065 device_xname(sc->sc_dev)); 1066 } 1067 } else { 1068 xfer->status = USBD_NORMAL_COMPLETION; 1069 } 1070 1071 end: 1072 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1073 * during this call, before methods->done is called: dma sync required 1074 * beforehand? */ 1075 usb_transfer_complete(xfer); 1076 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1077 } 1078 1079 /* 1080 * Wait here until controller claims to have an interrupt. 1081 * Then call ehci_intr and return. Use timeout to avoid waiting 1082 * too long. 1083 */ 1084 Static void 1085 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1086 { 1087 int timo; 1088 u_int32_t intrs; 1089 1090 xfer->status = USBD_IN_PROGRESS; 1091 for (timo = xfer->timeout; timo >= 0; timo--) { 1092 usb_delay_ms(&sc->sc_bus, 1); 1093 if (sc->sc_dying) 1094 break; 1095 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1096 sc->sc_eintrs; 1097 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1098 #ifdef EHCI_DEBUG 1099 if (ehcidebug > 15) 1100 ehci_dump_regs(sc); 1101 #endif 1102 if (intrs) { 1103 mutex_spin_enter(&sc->sc_intr_lock); 1104 ehci_intr1(sc); 1105 mutex_spin_exit(&sc->sc_intr_lock); 1106 if (xfer->status != USBD_IN_PROGRESS) 1107 return; 1108 } 1109 } 1110 1111 /* Timeout */ 1112 DPRINTF(("ehci_waitintr: timeout\n")); 1113 xfer->status = USBD_TIMEOUT; 1114 usb_transfer_complete(xfer); 1115 /* XXX should free TD */ 1116 } 1117 1118 Static void 1119 ehci_poll(struct usbd_bus *bus) 1120 { 1121 ehci_softc_t *sc = bus->hci_private; 1122 #ifdef EHCI_DEBUG 1123 static int last; 1124 int new; 1125 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1126 if (new != last) { 1127 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1128 last = new; 1129 } 1130 #endif 1131 1132 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1133 mutex_spin_enter(&sc->sc_intr_lock); 1134 ehci_intr1(sc); 1135 mutex_spin_exit(&sc->sc_intr_lock); 1136 } 1137 } 1138 1139 void 1140 ehci_childdet(device_t self, device_t child) 1141 { 1142 struct ehci_softc *sc = device_private(self); 1143 1144 KASSERT(sc->sc_child == child); 1145 sc->sc_child = NULL; 1146 } 1147 1148 int 1149 ehci_detach(struct ehci_softc *sc, int flags) 1150 { 1151 usbd_xfer_handle xfer; 1152 int rv = 0; 1153 1154 if (sc->sc_child != NULL) 1155 rv = config_detach(sc->sc_child, flags); 1156 1157 if (rv != 0) 1158 return (rv); 1159 1160 callout_stop(&sc->sc_tmo_intrlist); 1161 1162 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1163 1164 /* XXX free other data structures XXX */ 1165 if (sc->sc_softitds) 1166 kmem_free(sc->sc_softitds, 1167 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1168 cv_destroy(&sc->sc_doorbell); 1169 cv_destroy(&sc->sc_softwake_cv); 1170 1171 softint_disestablish(sc->sc_doorbell_si); 1172 softint_disestablish(sc->sc_pcd_si); 1173 1174 while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 1175 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1176 kmem_free(xfer, sizeof(struct ehci_xfer)); 1177 } 1178 1179 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1180 1181 return (rv); 1182 } 1183 1184 1185 int 1186 ehci_activate(device_t self, enum devact act) 1187 { 1188 struct ehci_softc *sc = device_private(self); 1189 1190 switch (act) { 1191 case DVACT_DEACTIVATE: 1192 sc->sc_dying = 1; 1193 return 0; 1194 default: 1195 return EOPNOTSUPP; 1196 } 1197 } 1198 1199 /* 1200 * Handle suspend/resume. 1201 * 1202 * We need to switch to polling mode here, because this routine is 1203 * called from an interrupt context. This is all right since we 1204 * are almost suspended anyway. 1205 * 1206 * Note that this power handler isn't to be registered directly; the 1207 * bus glue needs to call out to it. 1208 */ 1209 bool 1210 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1211 { 1212 ehci_softc_t *sc = device_private(dv); 1213 int i; 1214 uint32_t cmd, hcr; 1215 1216 mutex_spin_enter(&sc->sc_intr_lock); 1217 sc->sc_bus.use_polling++; 1218 mutex_spin_exit(&sc->sc_intr_lock); 1219 1220 for (i = 1; i <= sc->sc_noport; i++) { 1221 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1222 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1223 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1224 } 1225 1226 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1227 1228 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1229 EOWRITE4(sc, EHCI_USBCMD, cmd); 1230 1231 for (i = 0; i < 100; i++) { 1232 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1233 if (hcr == 0) 1234 break; 1235 1236 usb_delay_ms(&sc->sc_bus, 1); 1237 } 1238 if (hcr != 0) 1239 printf("%s: reset timeout\n", device_xname(dv)); 1240 1241 cmd &= ~EHCI_CMD_RS; 1242 EOWRITE4(sc, EHCI_USBCMD, cmd); 1243 1244 for (i = 0; i < 100; i++) { 1245 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1246 if (hcr == EHCI_STS_HCH) 1247 break; 1248 1249 usb_delay_ms(&sc->sc_bus, 1); 1250 } 1251 if (hcr != EHCI_STS_HCH) 1252 printf("%s: config timeout\n", device_xname(dv)); 1253 1254 mutex_spin_enter(&sc->sc_intr_lock); 1255 sc->sc_bus.use_polling--; 1256 mutex_spin_exit(&sc->sc_intr_lock); 1257 1258 return true; 1259 } 1260 1261 bool 1262 ehci_resume(device_t dv, const pmf_qual_t *qual) 1263 { 1264 ehci_softc_t *sc = device_private(dv); 1265 int i; 1266 uint32_t cmd, hcr; 1267 1268 /* restore things in case the bios sucks */ 1269 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1270 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1271 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1272 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1273 1274 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1275 1276 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1277 1278 hcr = 0; 1279 for (i = 1; i <= sc->sc_noport; i++) { 1280 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1281 if ((cmd & EHCI_PS_PO) == 0 && 1282 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1283 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1284 hcr = 1; 1285 } 1286 } 1287 1288 if (hcr) { 1289 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1290 1291 for (i = 1; i <= sc->sc_noport; i++) { 1292 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1293 if ((cmd & EHCI_PS_PO) == 0 && 1294 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1295 EOWRITE4(sc, EHCI_PORTSC(i), 1296 cmd & ~EHCI_PS_FPR); 1297 } 1298 } 1299 1300 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1301 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1302 1303 for (i = 0; i < 100; i++) { 1304 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1305 if (hcr != EHCI_STS_HCH) 1306 break; 1307 1308 usb_delay_ms(&sc->sc_bus, 1); 1309 } 1310 if (hcr == EHCI_STS_HCH) 1311 printf("%s: config timeout\n", device_xname(dv)); 1312 1313 return true; 1314 } 1315 1316 /* 1317 * Shut down the controller when the system is going down. 1318 */ 1319 bool 1320 ehci_shutdown(device_t self, int flags) 1321 { 1322 ehci_softc_t *sc = device_private(self); 1323 1324 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1325 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1326 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1327 return true; 1328 } 1329 1330 Static usbd_status 1331 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1332 { 1333 struct ehci_softc *sc = bus->hci_private; 1334 usbd_status err; 1335 1336 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1337 if (err == USBD_NOMEM) 1338 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1339 #ifdef EHCI_DEBUG 1340 if (err) 1341 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1342 #endif 1343 return (err); 1344 } 1345 1346 Static void 1347 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1348 { 1349 struct ehci_softc *sc = bus->hci_private; 1350 1351 if (dma->block->flags & USB_DMA_RESERVE) { 1352 usb_reserve_freem(&sc->sc_dma_reserve, 1353 dma); 1354 return; 1355 } 1356 usb_freemem(&sc->sc_bus, dma); 1357 } 1358 1359 Static usbd_xfer_handle 1360 ehci_allocx(struct usbd_bus *bus) 1361 { 1362 struct ehci_softc *sc = bus->hci_private; 1363 usbd_xfer_handle xfer; 1364 1365 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1366 if (xfer != NULL) { 1367 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1368 #ifdef DIAGNOSTIC 1369 if (xfer->busy_free != XFER_FREE) { 1370 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1371 xfer->busy_free); 1372 } 1373 #endif 1374 } else { 1375 xfer = kmem_alloc(sizeof(struct ehci_xfer), KM_SLEEP); 1376 } 1377 if (xfer != NULL) { 1378 memset(xfer, 0, sizeof(struct ehci_xfer)); 1379 #ifdef DIAGNOSTIC 1380 EXFER(xfer)->isdone = 1; 1381 xfer->busy_free = XFER_BUSY; 1382 #endif 1383 } 1384 return (xfer); 1385 } 1386 1387 Static void 1388 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1389 { 1390 struct ehci_softc *sc = bus->hci_private; 1391 1392 #ifdef DIAGNOSTIC 1393 if (xfer->busy_free != XFER_BUSY) { 1394 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1395 xfer->busy_free); 1396 } 1397 xfer->busy_free = XFER_FREE; 1398 if (!EXFER(xfer)->isdone) { 1399 printf("ehci_freex: !isdone\n"); 1400 } 1401 #endif 1402 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1403 } 1404 1405 Static void 1406 ehci_get_locks(struct usbd_bus *bus, kmutex_t **intr, kmutex_t **thread) 1407 { 1408 struct ehci_softc *sc = bus->hci_private; 1409 1410 *intr = &sc->sc_intr_lock; 1411 *thread = &sc->sc_lock; 1412 } 1413 1414 Static void 1415 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1416 { 1417 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1418 1419 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1420 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1421 #ifdef EHCI_DEBUG 1422 if (ehcidebug) 1423 usbd_dump_pipe(pipe); 1424 #endif 1425 epipe->nexttoggle = 0; 1426 } 1427 1428 Static void 1429 ehci_noop(usbd_pipe_handle pipe) 1430 { 1431 } 1432 1433 #ifdef EHCI_DEBUG 1434 Static void 1435 ehci_dump_regs(ehci_softc_t *sc) 1436 { 1437 int i; 1438 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1439 EOREAD4(sc, EHCI_USBCMD), 1440 EOREAD4(sc, EHCI_USBSTS), 1441 EOREAD4(sc, EHCI_USBINTR)); 1442 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1443 EOREAD4(sc, EHCI_FRINDEX), 1444 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1445 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1446 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1447 for (i = 1; i <= sc->sc_noport; i++) 1448 printf("port %d status=0x%08x\n", i, 1449 EOREAD4(sc, EHCI_PORTSC(i))); 1450 } 1451 1452 /* 1453 * Unused function - this is meant to be called from a kernel 1454 * debugger. 1455 */ 1456 void 1457 ehci_dump(void) 1458 { 1459 ehci_dump_regs(theehci); 1460 } 1461 1462 Static void 1463 ehci_dump_link(ehci_link_t link, int type) 1464 { 1465 link = le32toh(link); 1466 printf("0x%08x", link); 1467 if (link & EHCI_LINK_TERMINATE) 1468 printf("<T>"); 1469 else { 1470 printf("<"); 1471 if (type) { 1472 switch (EHCI_LINK_TYPE(link)) { 1473 case EHCI_LINK_ITD: printf("ITD"); break; 1474 case EHCI_LINK_QH: printf("QH"); break; 1475 case EHCI_LINK_SITD: printf("SITD"); break; 1476 case EHCI_LINK_FSTN: printf("FSTN"); break; 1477 } 1478 } 1479 printf(">"); 1480 } 1481 } 1482 1483 Static void 1484 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1485 { 1486 int i; 1487 u_int32_t stop; 1488 1489 stop = 0; 1490 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1491 ehci_dump_sqtd(sqtd); 1492 usb_syncmem(&sqtd->dma, 1493 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1494 sizeof(sqtd->qtd), 1495 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1496 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1497 usb_syncmem(&sqtd->dma, 1498 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1499 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1500 } 1501 if (sqtd) 1502 printf("dump aborted, too many TDs\n"); 1503 } 1504 1505 Static void 1506 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1507 { 1508 usb_syncmem(&sqtd->dma, sqtd->offs, 1509 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1510 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1511 ehci_dump_qtd(&sqtd->qtd); 1512 usb_syncmem(&sqtd->dma, sqtd->offs, 1513 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1514 } 1515 1516 Static void 1517 ehci_dump_qtd(ehci_qtd_t *qtd) 1518 { 1519 u_int32_t s; 1520 char sbuf[128]; 1521 1522 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1523 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1524 printf("\n"); 1525 s = le32toh(qtd->qtd_status); 1526 snprintb(sbuf, sizeof(sbuf), 1527 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1528 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1529 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1530 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1531 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1532 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1533 EHCI_QTD_GET_PID(s), sbuf); 1534 for (s = 0; s < 5; s++) 1535 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1536 } 1537 1538 Static void 1539 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1540 { 1541 ehci_qh_t *qh = &sqh->qh; 1542 u_int32_t endp, endphub; 1543 1544 usb_syncmem(&sqh->dma, sqh->offs, 1545 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1546 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1547 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1548 endp = le32toh(qh->qh_endp); 1549 printf(" endp=0x%08x\n", endp); 1550 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1551 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1552 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1553 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1554 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1555 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1556 EHCI_QH_GET_NRL(endp)); 1557 endphub = le32toh(qh->qh_endphub); 1558 printf(" endphub=0x%08x\n", endphub); 1559 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1560 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1561 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1562 EHCI_QH_GET_MULT(endphub)); 1563 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1564 printf("Overlay qTD:\n"); 1565 ehci_dump_qtd(&qh->qh_qtd); 1566 usb_syncmem(&sqh->dma, sqh->offs, 1567 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1568 } 1569 1570 #if notyet 1571 Static void 1572 ehci_dump_itd(struct ehci_soft_itd *itd) 1573 { 1574 ehci_isoc_trans_t t; 1575 ehci_isoc_bufr_ptr_t b, b2, b3; 1576 int i; 1577 1578 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1579 1580 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1581 t = le32toh(itd->itd.itd_ctl[i]); 1582 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1583 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1584 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1585 EHCI_ITD_GET_OFFS(t)); 1586 } 1587 printf("ITDbufr: "); 1588 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1589 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1590 1591 b = le32toh(itd->itd.itd_bufr[0]); 1592 b2 = le32toh(itd->itd.itd_bufr[1]); 1593 b3 = le32toh(itd->itd.itd_bufr[2]); 1594 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1595 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1596 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1597 } 1598 1599 Static void 1600 ehci_dump_sitd(struct ehci_soft_itd *itd) 1601 { 1602 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1603 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1604 itd->xfer_next, itd->physaddr, itd->slot); 1605 } 1606 #endif 1607 1608 #ifdef DIAGNOSTIC 1609 Static void 1610 ehci_dump_exfer(struct ehci_xfer *ex) 1611 { 1612 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1613 } 1614 #endif 1615 #endif 1616 1617 Static usbd_status 1618 ehci_open(usbd_pipe_handle pipe) 1619 { 1620 usbd_device_handle dev = pipe->device; 1621 ehci_softc_t *sc = dev->bus->hci_private; 1622 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1623 u_int8_t addr = dev->address; 1624 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1625 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1626 ehci_soft_qh_t *sqh; 1627 usbd_status err; 1628 int ival, speed, naks; 1629 int hshubaddr, hshubport; 1630 1631 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1632 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1633 1634 if (dev->myhsport) { 1635 /* 1636 * When directly attached FS/LS device while doing embedded 1637 * transaction translations and we are the hub, set the hub 1638 * adddress to 0 (us). 1639 */ 1640 if (!(sc->sc_flags & EHCIF_ETTF) 1641 || (dev->myhsport->parent->address != sc->sc_addr)) { 1642 hshubaddr = dev->myhsport->parent->address; 1643 } else { 1644 hshubaddr = 0; 1645 } 1646 hshubport = dev->myhsport->portno; 1647 } else { 1648 hshubaddr = 0; 1649 hshubport = 0; 1650 } 1651 1652 if (sc->sc_dying) 1653 return (USBD_IOERROR); 1654 1655 /* toggle state needed for bulk endpoints */ 1656 epipe->nexttoggle = pipe->endpoint->datatoggle; 1657 1658 if (addr == sc->sc_addr) { 1659 switch (ed->bEndpointAddress) { 1660 case USB_CONTROL_ENDPOINT: 1661 pipe->methods = &ehci_root_ctrl_methods; 1662 break; 1663 case UE_DIR_IN | EHCI_INTR_ENDPT: 1664 pipe->methods = &ehci_root_intr_methods; 1665 break; 1666 default: 1667 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1668 ed->bEndpointAddress)); 1669 return (USBD_INVAL); 1670 } 1671 return (USBD_NORMAL_COMPLETION); 1672 } 1673 1674 /* XXX All this stuff is only valid for async. */ 1675 switch (dev->speed) { 1676 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1677 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1678 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1679 default: panic("ehci_open: bad device speed %d", dev->speed); 1680 } 1681 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1682 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1683 "isoc endpoint.\n"); 1684 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1685 "attached to a USB2 hub, and transaction translations are " 1686 "not yet supported.\n"); 1687 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1688 "root hub instead.\n"); 1689 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1690 hshubaddr, hshubport)); 1691 return USBD_INVAL; 1692 } 1693 1694 /* 1695 * For interrupt transfer, nak throttling must be disabled, but for 1696 * the other transfer type, nak throttling should be enabled from the 1697 * veiwpoint that avoids the memory thrashing. 1698 */ 1699 naks = (xfertype == UE_INTERRUPT) ? 0 1700 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1701 1702 /* Allocate sqh for everything, save isoc xfers */ 1703 if (xfertype != UE_ISOCHRONOUS) { 1704 sqh = ehci_alloc_sqh(sc); 1705 if (sqh == NULL) 1706 return (USBD_NOMEM); 1707 /* qh_link filled when the QH is added */ 1708 sqh->qh.qh_endp = htole32( 1709 EHCI_QH_SET_ADDR(addr) | 1710 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1711 EHCI_QH_SET_EPS(speed) | 1712 EHCI_QH_DTC | 1713 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1714 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1715 EHCI_QH_CTL : 0) | 1716 EHCI_QH_SET_NRL(naks) 1717 ); 1718 sqh->qh.qh_endphub = htole32( 1719 EHCI_QH_SET_MULT(1) | 1720 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1721 ); 1722 if (speed != EHCI_QH_SPEED_HIGH) 1723 sqh->qh.qh_endphub |= htole32( 1724 EHCI_QH_SET_PORT(hshubport) | 1725 EHCI_QH_SET_HUBA(hshubaddr) | 1726 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1727 ); 1728 sqh->qh.qh_curqtd = EHCI_NULL; 1729 /* Fill the overlay qTD */ 1730 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1731 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1732 sqh->qh.qh_qtd.qtd_status = htole32(0); 1733 1734 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1735 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1736 epipe->sqh = sqh; 1737 } else { 1738 sqh = NULL; 1739 } /*xfertype == UE_ISOC*/ 1740 1741 switch (xfertype) { 1742 case UE_CONTROL: 1743 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1744 0, &epipe->u.ctl.reqdma); 1745 #ifdef EHCI_DEBUG 1746 if (err) 1747 printf("ehci_open: usb_allocmem()=%d\n", err); 1748 #endif 1749 if (err) 1750 goto bad; 1751 pipe->methods = &ehci_device_ctrl_methods; 1752 mutex_enter(&sc->sc_lock); 1753 ehci_add_qh(sqh, sc->sc_async_head); 1754 mutex_exit(&sc->sc_lock); 1755 break; 1756 case UE_BULK: 1757 pipe->methods = &ehci_device_bulk_methods; 1758 mutex_enter(&sc->sc_lock); 1759 ehci_add_qh(sqh, sc->sc_async_head); 1760 mutex_exit(&sc->sc_lock); 1761 break; 1762 case UE_INTERRUPT: 1763 pipe->methods = &ehci_device_intr_methods; 1764 ival = pipe->interval; 1765 if (ival == USBD_DEFAULT_INTERVAL) { 1766 if (speed == EHCI_QH_SPEED_HIGH) { 1767 if (ed->bInterval > 16) { 1768 /* 1769 * illegal with high-speed, but there 1770 * were documentation bugs in the spec, 1771 * so be generous 1772 */ 1773 ival = 256; 1774 } else 1775 ival = (1 << (ed->bInterval - 1)) / 8; 1776 } else 1777 ival = ed->bInterval; 1778 } 1779 err = ehci_device_setintr(sc, sqh, ival); 1780 if (err) 1781 goto bad; 1782 break; 1783 case UE_ISOCHRONOUS: 1784 pipe->methods = &ehci_device_isoc_methods; 1785 if (ed->bInterval == 0 || ed->bInterval > 16) { 1786 printf("ehci: opening pipe with invalid bInterval\n"); 1787 err = USBD_INVAL; 1788 goto bad; 1789 } 1790 if (UGETW(ed->wMaxPacketSize) == 0) { 1791 printf("ehci: zero length endpoint open request\n"); 1792 err = USBD_INVAL; 1793 goto bad; 1794 } 1795 epipe->u.isoc.next_frame = 0; 1796 epipe->u.isoc.cur_xfers = 0; 1797 break; 1798 default: 1799 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1800 err = USBD_INVAL; 1801 goto bad; 1802 } 1803 return (USBD_NORMAL_COMPLETION); 1804 1805 bad: 1806 if (sqh != NULL) 1807 ehci_free_sqh(sc, sqh); 1808 return (err); 1809 } 1810 1811 /* 1812 * Add an ED to the schedule. Called at splusb(). 1813 */ 1814 Static void 1815 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1816 { 1817 SPLUSBCHECK; 1818 1819 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1820 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1821 sqh->next = head->next; 1822 sqh->qh.qh_link = head->qh.qh_link; 1823 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1824 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1825 head->next = sqh; 1826 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1827 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1828 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1829 1830 #ifdef EHCI_DEBUG 1831 if (ehcidebug > 5) { 1832 printf("ehci_add_qh:\n"); 1833 ehci_dump_sqh(sqh); 1834 } 1835 #endif 1836 } 1837 1838 /* 1839 * Remove an ED from the schedule. Called at splusb(). 1840 */ 1841 Static void 1842 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1843 { 1844 ehci_soft_qh_t *p; 1845 1846 SPLUSBCHECK; 1847 /* XXX */ 1848 for (p = head; p != NULL && p->next != sqh; p = p->next) 1849 ; 1850 if (p == NULL) 1851 panic("ehci_rem_qh: ED not found"); 1852 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1853 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1854 p->next = sqh->next; 1855 p->qh.qh_link = sqh->qh.qh_link; 1856 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1857 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1858 1859 ehci_sync_hc(sc); 1860 } 1861 1862 Static void 1863 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1864 { 1865 int i; 1866 u_int32_t status; 1867 1868 /* Save toggle bit and ping status. */ 1869 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1870 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1871 status = sqh->qh.qh_qtd.qtd_status & 1872 htole32(EHCI_QTD_TOGGLE_MASK | 1873 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1874 /* Set HALTED to make hw leave it alone. */ 1875 sqh->qh.qh_qtd.qtd_status = 1876 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1877 usb_syncmem(&sqh->dma, 1878 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1879 sizeof(sqh->qh.qh_qtd.qtd_status), 1880 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1881 sqh->qh.qh_curqtd = 0; 1882 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1883 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1884 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1885 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1886 sqh->sqtd = sqtd; 1887 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1888 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1889 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1890 sqh->qh.qh_qtd.qtd_status = status; 1891 usb_syncmem(&sqh->dma, 1892 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1893 sizeof(sqh->qh.qh_qtd.qtd_status), 1894 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1895 } 1896 1897 /* 1898 * Ensure that the HC has released all references to the QH. We do this 1899 * by asking for a Async Advance Doorbell interrupt and then we wait for 1900 * the interrupt. 1901 * To make this easier we first obtain exclusive use of the doorbell. 1902 */ 1903 Static void 1904 ehci_sync_hc(ehci_softc_t *sc) 1905 { 1906 int error; 1907 1908 KASSERT(mutex_owned(&sc->sc_lock)); 1909 1910 if (sc->sc_dying) { 1911 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1912 return; 1913 } 1914 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1915 /* ask for doorbell */ 1916 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1917 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1918 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1919 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 1920 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1921 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1922 #ifdef DIAGNOSTIC 1923 if (error) 1924 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 1925 #endif 1926 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1927 } 1928 1929 /*Call at splusb*/ 1930 Static void 1931 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1932 { 1933 struct ehci_soft_itd *itd, *prev; 1934 1935 prev = NULL; 1936 1937 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1938 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1939 1940 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1941 prev = itd->u.frame_list.prev; 1942 /* Unlink itd from hardware chain, or frame array */ 1943 if (prev == NULL) { /* We're at the table head */ 1944 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1945 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1946 usb_syncmem(&sc->sc_fldma, 1947 sizeof(ehci_link_t) * itd->slot, 1948 sizeof(ehci_link_t), 1949 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1950 1951 if (itd->u.frame_list.next != NULL) 1952 itd->u.frame_list.next->u.frame_list.prev = NULL; 1953 } else { 1954 /* XXX this part is untested... */ 1955 prev->itd.itd_next = itd->itd.itd_next; 1956 usb_syncmem(&itd->dma, 1957 itd->offs + offsetof(ehci_itd_t, itd_next), 1958 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1959 1960 prev->u.frame_list.next = itd->u.frame_list.next; 1961 if (itd->u.frame_list.next != NULL) 1962 itd->u.frame_list.next->u.frame_list.prev = prev; 1963 } 1964 } 1965 1966 prev = NULL; 1967 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1968 if (prev != NULL) 1969 ehci_free_itd(sc, prev); 1970 prev = itd; 1971 } 1972 if (prev) 1973 ehci_free_itd(sc, prev); 1974 exfer->itdstart = NULL; 1975 exfer->itdend = NULL; 1976 } 1977 1978 /***********/ 1979 1980 /* 1981 * Data structures and routines to emulate the root hub. 1982 */ 1983 Static usb_device_descriptor_t ehci_devd = { 1984 USB_DEVICE_DESCRIPTOR_SIZE, 1985 UDESC_DEVICE, /* type */ 1986 {0x00, 0x02}, /* USB version */ 1987 UDCLASS_HUB, /* class */ 1988 UDSUBCLASS_HUB, /* subclass */ 1989 UDPROTO_HSHUBSTT, /* protocol */ 1990 64, /* max packet */ 1991 {0},{0},{0x00,0x01}, /* device id */ 1992 1,2,0, /* string indicies */ 1993 1 /* # of configurations */ 1994 }; 1995 1996 Static const usb_device_qualifier_t ehci_odevd = { 1997 USB_DEVICE_DESCRIPTOR_SIZE, 1998 UDESC_DEVICE_QUALIFIER, /* type */ 1999 {0x00, 0x02}, /* USB version */ 2000 UDCLASS_HUB, /* class */ 2001 UDSUBCLASS_HUB, /* subclass */ 2002 UDPROTO_FSHUB, /* protocol */ 2003 64, /* max packet */ 2004 1, /* # of configurations */ 2005 0 2006 }; 2007 2008 Static const usb_config_descriptor_t ehci_confd = { 2009 USB_CONFIG_DESCRIPTOR_SIZE, 2010 UDESC_CONFIG, 2011 {USB_CONFIG_DESCRIPTOR_SIZE + 2012 USB_INTERFACE_DESCRIPTOR_SIZE + 2013 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2014 1, 2015 1, 2016 0, 2017 UC_ATTR_MBO | UC_SELF_POWERED, 2018 0 /* max power */ 2019 }; 2020 2021 Static const usb_interface_descriptor_t ehci_ifcd = { 2022 USB_INTERFACE_DESCRIPTOR_SIZE, 2023 UDESC_INTERFACE, 2024 0, 2025 0, 2026 1, 2027 UICLASS_HUB, 2028 UISUBCLASS_HUB, 2029 UIPROTO_HSHUBSTT, 2030 0 2031 }; 2032 2033 Static const usb_endpoint_descriptor_t ehci_endpd = { 2034 USB_ENDPOINT_DESCRIPTOR_SIZE, 2035 UDESC_ENDPOINT, 2036 UE_DIR_IN | EHCI_INTR_ENDPT, 2037 UE_INTERRUPT, 2038 {8, 0}, /* max packet */ 2039 12 2040 }; 2041 2042 Static const usb_hub_descriptor_t ehci_hubd = { 2043 USB_HUB_DESCRIPTOR_SIZE, 2044 UDESC_HUB, 2045 0, 2046 {0,0}, 2047 0, 2048 0, 2049 {""}, 2050 {""}, 2051 }; 2052 2053 /* 2054 * Simulate a hardware hub by handling all the necessary requests. 2055 */ 2056 Static usbd_status 2057 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2058 { 2059 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2060 usbd_status err; 2061 2062 /* Insert last in queue. */ 2063 mutex_enter(&sc->sc_lock); 2064 err = usb_insert_transfer(xfer); 2065 mutex_exit(&sc->sc_lock); 2066 if (err) 2067 return (err); 2068 2069 /* Pipe isn't running, start first */ 2070 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2071 } 2072 2073 Static usbd_status 2074 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2075 { 2076 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2077 usb_device_request_t *req; 2078 void *buf = NULL; 2079 int port, i; 2080 int len, value, index, l, totlen = 0; 2081 usb_port_status_t ps; 2082 usb_hub_descriptor_t hubd; 2083 usbd_status err; 2084 u_int32_t v; 2085 2086 if (sc->sc_dying) 2087 return (USBD_IOERROR); 2088 2089 #ifdef DIAGNOSTIC 2090 if (!(xfer->rqflags & URQ_REQUEST)) 2091 /* XXX panic */ 2092 return (USBD_INVAL); 2093 #endif 2094 req = &xfer->request; 2095 2096 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2097 req->bmRequestType, req->bRequest)); 2098 2099 len = UGETW(req->wLength); 2100 value = UGETW(req->wValue); 2101 index = UGETW(req->wIndex); 2102 2103 if (len != 0) 2104 buf = KERNADDR(&xfer->dmabuf, 0); 2105 2106 #define C(x,y) ((x) | ((y) << 8)) 2107 switch(C(req->bRequest, req->bmRequestType)) { 2108 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2109 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2110 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2111 /* 2112 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2113 * for the integrated root hub. 2114 */ 2115 break; 2116 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2117 if (len > 0) { 2118 *(u_int8_t *)buf = sc->sc_conf; 2119 totlen = 1; 2120 } 2121 break; 2122 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2123 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2124 if (len == 0) 2125 break; 2126 switch(value >> 8) { 2127 case UDESC_DEVICE: 2128 if ((value & 0xff) != 0) { 2129 err = USBD_IOERROR; 2130 goto ret; 2131 } 2132 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2133 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2134 memcpy(buf, &ehci_devd, l); 2135 break; 2136 /* 2137 * We can't really operate at another speed, but the spec says 2138 * we need this descriptor. 2139 */ 2140 case UDESC_DEVICE_QUALIFIER: 2141 if ((value & 0xff) != 0) { 2142 err = USBD_IOERROR; 2143 goto ret; 2144 } 2145 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2146 memcpy(buf, &ehci_odevd, l); 2147 break; 2148 /* 2149 * We can't really operate at another speed, but the spec says 2150 * we need this descriptor. 2151 */ 2152 case UDESC_OTHER_SPEED_CONFIGURATION: 2153 case UDESC_CONFIG: 2154 if ((value & 0xff) != 0) { 2155 err = USBD_IOERROR; 2156 goto ret; 2157 } 2158 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2159 memcpy(buf, &ehci_confd, l); 2160 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2161 value >> 8; 2162 buf = (char *)buf + l; 2163 len -= l; 2164 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2165 totlen += l; 2166 memcpy(buf, &ehci_ifcd, l); 2167 buf = (char *)buf + l; 2168 len -= l; 2169 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2170 totlen += l; 2171 memcpy(buf, &ehci_endpd, l); 2172 break; 2173 case UDESC_STRING: 2174 #define sd ((usb_string_descriptor_t *)buf) 2175 switch (value & 0xff) { 2176 case 0: /* Language table */ 2177 totlen = usb_makelangtbl(sd, len); 2178 break; 2179 case 1: /* Vendor */ 2180 totlen = usb_makestrdesc(sd, len, 2181 sc->sc_vendor); 2182 break; 2183 case 2: /* Product */ 2184 totlen = usb_makestrdesc(sd, len, 2185 "EHCI root hub"); 2186 break; 2187 } 2188 #undef sd 2189 break; 2190 default: 2191 err = USBD_IOERROR; 2192 goto ret; 2193 } 2194 break; 2195 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2196 if (len > 0) { 2197 *(u_int8_t *)buf = 0; 2198 totlen = 1; 2199 } 2200 break; 2201 case C(UR_GET_STATUS, UT_READ_DEVICE): 2202 if (len > 1) { 2203 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2204 totlen = 2; 2205 } 2206 break; 2207 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2208 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2209 if (len > 1) { 2210 USETW(((usb_status_t *)buf)->wStatus, 0); 2211 totlen = 2; 2212 } 2213 break; 2214 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2215 if (value >= USB_MAX_DEVICES) { 2216 err = USBD_IOERROR; 2217 goto ret; 2218 } 2219 sc->sc_addr = value; 2220 break; 2221 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2222 if (value != 0 && value != 1) { 2223 err = USBD_IOERROR; 2224 goto ret; 2225 } 2226 sc->sc_conf = value; 2227 break; 2228 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2229 break; 2230 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2231 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2232 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2233 err = USBD_IOERROR; 2234 goto ret; 2235 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2236 break; 2237 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2238 break; 2239 /* Hub requests */ 2240 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2241 break; 2242 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2243 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2244 "port=%d feature=%d\n", 2245 index, value)); 2246 if (index < 1 || index > sc->sc_noport) { 2247 err = USBD_IOERROR; 2248 goto ret; 2249 } 2250 port = EHCI_PORTSC(index); 2251 v = EOREAD4(sc, port); 2252 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2253 v &= ~EHCI_PS_CLEAR; 2254 switch(value) { 2255 case UHF_PORT_ENABLE: 2256 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2257 break; 2258 case UHF_PORT_SUSPEND: 2259 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2260 break; 2261 v &= ~EHCI_PS_SUSP; 2262 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2263 /* see USB2 spec ch. 7.1.7.7 */ 2264 usb_delay_ms(&sc->sc_bus, 20); 2265 EOWRITE4(sc, port, v); 2266 usb_delay_ms(&sc->sc_bus, 2); 2267 #ifdef DEBUG 2268 v = EOREAD4(sc, port); 2269 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2270 printf("ehci: resume failed: %x\n", v); 2271 #endif 2272 break; 2273 case UHF_PORT_POWER: 2274 if (sc->sc_hasppc) 2275 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2276 break; 2277 case UHF_PORT_TEST: 2278 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2279 "%d\n", index)); 2280 break; 2281 case UHF_PORT_INDICATOR: 2282 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2283 "%d\n", index)); 2284 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2285 break; 2286 case UHF_C_PORT_CONNECTION: 2287 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2288 break; 2289 case UHF_C_PORT_ENABLE: 2290 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2291 break; 2292 case UHF_C_PORT_SUSPEND: 2293 /* how? */ 2294 break; 2295 case UHF_C_PORT_OVER_CURRENT: 2296 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2297 break; 2298 case UHF_C_PORT_RESET: 2299 sc->sc_isreset[index] = 0; 2300 break; 2301 default: 2302 err = USBD_IOERROR; 2303 goto ret; 2304 } 2305 #if 0 2306 switch(value) { 2307 case UHF_C_PORT_CONNECTION: 2308 case UHF_C_PORT_ENABLE: 2309 case UHF_C_PORT_SUSPEND: 2310 case UHF_C_PORT_OVER_CURRENT: 2311 case UHF_C_PORT_RESET: 2312 default: 2313 break; 2314 } 2315 #endif 2316 break; 2317 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2318 if (len == 0) 2319 break; 2320 if ((value & 0xff) != 0) { 2321 err = USBD_IOERROR; 2322 goto ret; 2323 } 2324 hubd = ehci_hubd; 2325 hubd.bNbrPorts = sc->sc_noport; 2326 v = EOREAD4(sc, EHCI_HCSPARAMS); 2327 USETW(hubd.wHubCharacteristics, 2328 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2329 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2330 ? UHD_PORT_IND : 0); 2331 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2332 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2333 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2334 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2335 l = min(len, hubd.bDescLength); 2336 totlen = l; 2337 memcpy(buf, &hubd, l); 2338 break; 2339 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2340 if (len != 4) { 2341 err = USBD_IOERROR; 2342 goto ret; 2343 } 2344 memset(buf, 0, len); /* ? XXX */ 2345 totlen = len; 2346 break; 2347 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2348 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2349 index)); 2350 if (index < 1 || index > sc->sc_noport) { 2351 err = USBD_IOERROR; 2352 goto ret; 2353 } 2354 if (len != 4) { 2355 err = USBD_IOERROR; 2356 goto ret; 2357 } 2358 v = EOREAD4(sc, EHCI_PORTSC(index)); 2359 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2360 2361 i = UPS_HIGH_SPEED; 2362 #if 0 2363 if (sc->sc_flags & EHCIF_ETTF) { 2364 /* 2365 * If we are doing embedded transaction translation, 2366 * then directly attached LS/FS devices are reset by 2367 * the EHCI controller itself. PSPD is encoded 2368 * the same way as in USBSTATUS. 2369 */ 2370 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2371 } 2372 #endif 2373 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2374 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2375 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2376 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2377 if (v & EHCI_PS_PR) i |= UPS_RESET; 2378 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2379 if (sc->sc_vendor_port_status) 2380 i = sc->sc_vendor_port_status(sc, v, i); 2381 USETW(ps.wPortStatus, i); 2382 i = 0; 2383 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2384 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2385 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2386 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2387 USETW(ps.wPortChange, i); 2388 l = min(len, sizeof ps); 2389 memcpy(buf, &ps, l); 2390 totlen = l; 2391 break; 2392 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2393 err = USBD_IOERROR; 2394 goto ret; 2395 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2396 break; 2397 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2398 if (index < 1 || index > sc->sc_noport) { 2399 err = USBD_IOERROR; 2400 goto ret; 2401 } 2402 port = EHCI_PORTSC(index); 2403 v = EOREAD4(sc, port); 2404 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2405 v &= ~EHCI_PS_CLEAR; 2406 switch(value) { 2407 case UHF_PORT_ENABLE: 2408 EOWRITE4(sc, port, v | EHCI_PS_PE); 2409 break; 2410 case UHF_PORT_SUSPEND: 2411 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2412 break; 2413 case UHF_PORT_RESET: 2414 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2415 index)); 2416 if (EHCI_PS_IS_LOWSPEED(v) 2417 && sc->sc_ncomp > 0 2418 && !(sc->sc_flags & EHCIF_ETTF)) { 2419 /* 2420 * Low speed device on non-ETTF controller or 2421 * unaccompanied controller, give up ownership. 2422 */ 2423 ehci_disown(sc, index, 1); 2424 break; 2425 } 2426 /* Start reset sequence. */ 2427 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2428 EOWRITE4(sc, port, v | EHCI_PS_PR); 2429 /* Wait for reset to complete. */ 2430 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2431 if (sc->sc_dying) { 2432 err = USBD_IOERROR; 2433 goto ret; 2434 } 2435 /* 2436 * An embedded transaction translater will automatically 2437 * terminate the reset sequence so there's no need to 2438 * it. 2439 */ 2440 v = EOREAD4(sc, port); 2441 if (v & EHCI_PS_PR) { 2442 /* Terminate reset sequence. */ 2443 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2444 /* Wait for HC to complete reset. */ 2445 usb_delay_ms(&sc->sc_bus, 2446 EHCI_PORT_RESET_COMPLETE); 2447 if (sc->sc_dying) { 2448 err = USBD_IOERROR; 2449 goto ret; 2450 } 2451 } 2452 2453 v = EOREAD4(sc, port); 2454 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2455 if (v & EHCI_PS_PR) { 2456 printf("%s: port reset timeout\n", 2457 device_xname(sc->sc_dev)); 2458 return (USBD_TIMEOUT); 2459 } 2460 if (!(v & EHCI_PS_PE)) { 2461 /* Not a high speed device, give up ownership.*/ 2462 ehci_disown(sc, index, 0); 2463 break; 2464 } 2465 sc->sc_isreset[index] = 1; 2466 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2467 index, v)); 2468 break; 2469 case UHF_PORT_POWER: 2470 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2471 "%d (has PPC = %d)\n", index, 2472 sc->sc_hasppc)); 2473 if (sc->sc_hasppc) 2474 EOWRITE4(sc, port, v | EHCI_PS_PP); 2475 break; 2476 case UHF_PORT_TEST: 2477 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2478 "%d\n", index)); 2479 break; 2480 case UHF_PORT_INDICATOR: 2481 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2482 "%d\n", index)); 2483 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2484 break; 2485 default: 2486 err = USBD_IOERROR; 2487 goto ret; 2488 } 2489 break; 2490 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2491 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2492 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2493 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2494 break; 2495 default: 2496 err = USBD_IOERROR; 2497 goto ret; 2498 } 2499 xfer->actlen = totlen; 2500 err = USBD_NORMAL_COMPLETION; 2501 ret: 2502 mutex_enter(&sc->sc_lock); 2503 xfer->status = err; 2504 usb_transfer_complete(xfer); 2505 mutex_exit(&sc->sc_lock); 2506 return (USBD_IN_PROGRESS); 2507 } 2508 2509 Static void 2510 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2511 { 2512 int port; 2513 u_int32_t v; 2514 2515 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2516 #ifdef DIAGNOSTIC 2517 if (sc->sc_npcomp != 0) { 2518 int i = (index-1) / sc->sc_npcomp; 2519 if (i >= sc->sc_ncomp) 2520 printf("%s: strange port\n", 2521 device_xname(sc->sc_dev)); 2522 else 2523 printf("%s: handing over %s speed device on " 2524 "port %d to %s\n", 2525 device_xname(sc->sc_dev), 2526 lowspeed ? "low" : "full", 2527 index, device_xname(sc->sc_comps[i])); 2528 } else { 2529 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2530 } 2531 #endif 2532 port = EHCI_PORTSC(index); 2533 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2534 EOWRITE4(sc, port, v | EHCI_PS_PO); 2535 } 2536 2537 /* Abort a root control request. */ 2538 Static void 2539 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2540 { 2541 /* Nothing to do, all transfers are synchronous. */ 2542 } 2543 2544 /* Close the root pipe. */ 2545 Static void 2546 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2547 { 2548 DPRINTF(("ehci_root_ctrl_close\n")); 2549 /* Nothing to do. */ 2550 } 2551 2552 Static void 2553 ehci_root_intr_done(usbd_xfer_handle xfer) 2554 { 2555 xfer->hcpriv = NULL; 2556 } 2557 2558 Static usbd_status 2559 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2560 { 2561 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2562 usbd_status err; 2563 2564 /* Insert last in queue. */ 2565 mutex_enter(&sc->sc_lock); 2566 err = usb_insert_transfer(xfer); 2567 mutex_exit(&sc->sc_lock); 2568 if (err) 2569 return (err); 2570 2571 /* Pipe isn't running, start first */ 2572 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2573 } 2574 2575 Static usbd_status 2576 ehci_root_intr_start(usbd_xfer_handle xfer) 2577 { 2578 usbd_pipe_handle pipe = xfer->pipe; 2579 ehci_softc_t *sc = pipe->device->bus->hci_private; 2580 2581 if (sc->sc_dying) 2582 return (USBD_IOERROR); 2583 2584 mutex_enter(&sc->sc_lock); 2585 sc->sc_intrxfer = xfer; 2586 mutex_exit(&sc->sc_lock); 2587 2588 return (USBD_IN_PROGRESS); 2589 } 2590 2591 /* Abort a root interrupt request. */ 2592 Static void 2593 ehci_root_intr_abort(usbd_xfer_handle xfer) 2594 { 2595 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2596 2597 mutex_enter(&sc->sc_lock); 2598 if (xfer->pipe->intrxfer == xfer) { 2599 DPRINTF(("ehci_root_intr_abort: remove\n")); 2600 xfer->pipe->intrxfer = NULL; 2601 } 2602 xfer->status = USBD_CANCELLED; 2603 usb_transfer_complete(xfer); 2604 mutex_exit(&sc->sc_lock); 2605 } 2606 2607 /* Close the root pipe. */ 2608 Static void 2609 ehci_root_intr_close(usbd_pipe_handle pipe) 2610 { 2611 ehci_softc_t *sc = pipe->device->bus->hci_private; 2612 2613 DPRINTF(("ehci_root_intr_close\n")); 2614 2615 mutex_enter(&sc->sc_lock); 2616 sc->sc_intrxfer = NULL; 2617 mutex_exit(&sc->sc_lock); 2618 } 2619 2620 Static void 2621 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2622 { 2623 xfer->hcpriv = NULL; 2624 } 2625 2626 /************************/ 2627 2628 Static ehci_soft_qh_t * 2629 ehci_alloc_sqh(ehci_softc_t *sc) 2630 { 2631 ehci_soft_qh_t *sqh; 2632 usbd_status err; 2633 int i, offs; 2634 usb_dma_t dma; 2635 2636 if (sc->sc_freeqhs == NULL) { 2637 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2638 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2639 EHCI_PAGE_SIZE, &dma); 2640 #ifdef EHCI_DEBUG 2641 if (err) 2642 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2643 #endif 2644 if (err) 2645 return (NULL); 2646 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2647 offs = i * EHCI_SQH_SIZE; 2648 sqh = KERNADDR(&dma, offs); 2649 sqh->physaddr = DMAADDR(&dma, offs); 2650 sqh->dma = dma; 2651 sqh->offs = offs; 2652 sqh->next = sc->sc_freeqhs; 2653 sc->sc_freeqhs = sqh; 2654 } 2655 } 2656 sqh = sc->sc_freeqhs; 2657 sc->sc_freeqhs = sqh->next; 2658 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2659 sqh->next = NULL; 2660 return (sqh); 2661 } 2662 2663 Static void 2664 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2665 { 2666 sqh->next = sc->sc_freeqhs; 2667 sc->sc_freeqhs = sqh; 2668 } 2669 2670 Static ehci_soft_qtd_t * 2671 ehci_alloc_sqtd(ehci_softc_t *sc) 2672 { 2673 ehci_soft_qtd_t *sqtd = NULL; 2674 usbd_status err; 2675 int i, offs; 2676 usb_dma_t dma; 2677 2678 if (sc->sc_freeqtds == NULL) { 2679 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2680 2681 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2682 EHCI_PAGE_SIZE, &dma); 2683 #ifdef EHCI_DEBUG 2684 if (err) 2685 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2686 #endif 2687 if (err) 2688 goto done; 2689 2690 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2691 offs = i * EHCI_SQTD_SIZE; 2692 sqtd = KERNADDR(&dma, offs); 2693 sqtd->physaddr = DMAADDR(&dma, offs); 2694 sqtd->dma = dma; 2695 sqtd->offs = offs; 2696 2697 sqtd->nextqtd = sc->sc_freeqtds; 2698 sc->sc_freeqtds = sqtd; 2699 } 2700 } 2701 2702 sqtd = sc->sc_freeqtds; 2703 sc->sc_freeqtds = sqtd->nextqtd; 2704 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2705 sqtd->nextqtd = NULL; 2706 sqtd->xfer = NULL; 2707 2708 done: 2709 return (sqtd); 2710 } 2711 2712 Static void 2713 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2714 { 2715 2716 KASSERT(mutex_owned(&sc->sc_lock)); 2717 2718 sqtd->nextqtd = sc->sc_freeqtds; 2719 sc->sc_freeqtds = sqtd; 2720 } 2721 2722 Static usbd_status 2723 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2724 int alen, int rd, usbd_xfer_handle xfer, 2725 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2726 { 2727 ehci_soft_qtd_t *next, *cur; 2728 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2729 u_int32_t qtdstatus; 2730 int len, curlen, mps; 2731 int i, tog; 2732 usb_dma_t *dma = &xfer->dmabuf; 2733 u_int16_t flags = xfer->flags; 2734 2735 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2736 2737 len = alen; 2738 dataphys = DMAADDR(dma, 0); 2739 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2740 qtdstatus = EHCI_QTD_ACTIVE | 2741 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2742 EHCI_QTD_SET_CERR(3) 2743 /* IOC set below */ 2744 /* BYTES set below */ 2745 ; 2746 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2747 tog = epipe->nexttoggle; 2748 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2749 2750 cur = ehci_alloc_sqtd(sc); 2751 *sp = cur; 2752 if (cur == NULL) 2753 goto nomem; 2754 2755 usb_syncmem(dma, 0, alen, 2756 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2757 for (;;) { 2758 dataphyspage = EHCI_PAGE(dataphys); 2759 /* The EHCI hardware can handle at most 5 pages. */ 2760 if (dataphyslastpage - dataphyspage < 2761 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2762 /* we can handle it in this QTD */ 2763 curlen = len; 2764 } else { 2765 /* must use multiple TDs, fill as much as possible. */ 2766 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2767 EHCI_PAGE_OFFSET(dataphys); 2768 #ifdef DIAGNOSTIC 2769 if (curlen > len) { 2770 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2771 "len=0x%x offs=0x%x\n", curlen, len, 2772 EHCI_PAGE_OFFSET(dataphys)); 2773 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2774 dataphyslastpage, dataphyspage, 2775 dataphys); 2776 curlen = len; 2777 } 2778 #endif 2779 /* the length must be a multiple of the max size */ 2780 curlen -= curlen % mps; 2781 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2782 "curlen=%d\n", curlen)); 2783 #ifdef DIAGNOSTIC 2784 if (curlen == 0) 2785 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2786 #endif 2787 } 2788 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2789 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2790 dataphys, dataphyslastpage, 2791 len, curlen)); 2792 len -= curlen; 2793 2794 /* 2795 * Allocate another transfer if there's more data left, 2796 * or if force last short transfer flag is set and we're 2797 * allocating a multiple of the max packet size. 2798 */ 2799 if (len != 0 || 2800 ((curlen % mps) == 0 && !rd && curlen != 0 && 2801 (flags & USBD_FORCE_SHORT_XFER))) { 2802 next = ehci_alloc_sqtd(sc); 2803 if (next == NULL) 2804 goto nomem; 2805 nextphys = htole32(next->physaddr); 2806 } else { 2807 next = NULL; 2808 nextphys = EHCI_NULL; 2809 } 2810 2811 for (i = 0; i * EHCI_PAGE_SIZE < 2812 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2813 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2814 if (i != 0) /* use offset only in first buffer */ 2815 a = EHCI_PAGE(a); 2816 cur->qtd.qtd_buffer[i] = htole32(a); 2817 cur->qtd.qtd_buffer_hi[i] = 0; 2818 #ifdef DIAGNOSTIC 2819 if (i >= EHCI_QTD_NBUFFERS) { 2820 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2821 goto nomem; 2822 } 2823 #endif 2824 } 2825 cur->nextqtd = next; 2826 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2827 cur->qtd.qtd_status = 2828 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2829 cur->xfer = xfer; 2830 cur->len = curlen; 2831 2832 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2833 dataphys, dataphys + curlen)); 2834 /* adjust the toggle based on the number of packets in this 2835 qtd */ 2836 if (((curlen + mps - 1) / mps) & 1) { 2837 tog ^= 1; 2838 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2839 } 2840 if (next == NULL) 2841 break; 2842 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2843 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2844 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2845 if (len) 2846 dataphys += curlen; 2847 cur = next; 2848 } 2849 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2850 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2851 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2852 *ep = cur; 2853 epipe->nexttoggle = tog; 2854 2855 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2856 *sp, *ep)); 2857 2858 return (USBD_NORMAL_COMPLETION); 2859 2860 nomem: 2861 /* XXX free chain */ 2862 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2863 return (USBD_NOMEM); 2864 } 2865 2866 Static void 2867 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2868 ehci_soft_qtd_t *sqtdend) 2869 { 2870 ehci_soft_qtd_t *p; 2871 int i; 2872 2873 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2874 sqtd, sqtdend)); 2875 2876 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2877 p = sqtd->nextqtd; 2878 ehci_free_sqtd(sc, sqtd); 2879 } 2880 } 2881 2882 Static ehci_soft_itd_t * 2883 ehci_alloc_itd(ehci_softc_t *sc) 2884 { 2885 struct ehci_soft_itd *itd, *freeitd; 2886 usbd_status err; 2887 int i, s, offs, frindex, previndex; 2888 usb_dma_t dma; 2889 2890 KASSERT(mutex_owned(&sc->sc_lock)); 2891 2892 /* Find an itd that wasn't freed this frame or last frame. This can 2893 * discard itds that were freed before frindex wrapped around 2894 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2895 * interrupt and fiddling with list when that happens */ 2896 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2897 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2898 2899 freeitd = NULL; 2900 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2901 if (itd == NULL) 2902 break; 2903 if (itd->slot != frindex && itd->slot != previndex) { 2904 freeitd = itd; 2905 break; 2906 } 2907 } 2908 2909 if (freeitd == NULL) { 2910 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2911 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2912 EHCI_PAGE_SIZE, &dma); 2913 2914 if (err) { 2915 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2916 return NULL; 2917 } 2918 2919 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2920 offs = i * EHCI_ITD_SIZE; 2921 itd = KERNADDR(&dma, offs); 2922 itd->physaddr = DMAADDR(&dma, offs); 2923 itd->dma = dma; 2924 itd->offs = offs; 2925 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2926 } 2927 freeitd = LIST_FIRST(&sc->sc_freeitds); 2928 } 2929 2930 itd = freeitd; 2931 LIST_REMOVE(itd, u.free_list); 2932 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2933 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2934 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2935 BUS_DMASYNC_PREREAD); 2936 2937 itd->u.frame_list.next = NULL; 2938 itd->u.frame_list.prev = NULL; 2939 itd->xfer_next = NULL; 2940 itd->slot = 0; 2941 splx(s); 2942 2943 return itd; 2944 } 2945 2946 Static void 2947 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2948 { 2949 2950 KASSERT(mutex_owned(&sc->sc_lock)); 2951 2952 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2953 } 2954 2955 /****************/ 2956 2957 /* 2958 * Close a reqular pipe. 2959 * Assumes that there are no pending transactions. 2960 */ 2961 Static void 2962 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2963 { 2964 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2965 ehci_softc_t *sc = pipe->device->bus->hci_private; 2966 ehci_soft_qh_t *sqh = epipe->sqh; 2967 2968 KASSERT(mutex_owned(&sc->sc_lock)); 2969 2970 ehci_rem_qh(sc, sqh, head); 2971 ehci_free_sqh(sc, epipe->sqh); 2972 } 2973 2974 /* 2975 * Abort a device request. 2976 * If this routine is called at splusb() it guarantees that the request 2977 * will be removed from the hardware scheduling and that the callback 2978 * for it will be called with USBD_CANCELLED status. 2979 * It's impossible to guarantee that the requested transfer will not 2980 * have happened since the hardware runs concurrently. 2981 * If the transaction has already happened we rely on the ordinary 2982 * interrupt processing to process it. 2983 * XXX This is most probably wrong. 2984 */ 2985 Static void 2986 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2987 { 2988 #define exfer EXFER(xfer) 2989 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2990 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2991 ehci_soft_qh_t *sqh = epipe->sqh; 2992 ehci_soft_qtd_t *sqtd; 2993 ehci_physaddr_t cur; 2994 u_int32_t qhstatus; 2995 int hit; 2996 int wake; 2997 2998 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2999 3000 if (sc->sc_dying) { 3001 /* If we're dying, just do the software part. */ 3002 mutex_enter(&sc->sc_lock); 3003 xfer->status = status; /* make software ignore it */ 3004 callout_stop(&xfer->timeout_handle); 3005 usb_transfer_complete(xfer); 3006 mutex_exit(&sc->sc_lock); 3007 return; 3008 } 3009 3010 if (xfer->device->bus->intr_context) 3011 panic("ehci_abort_xfer: not in process context"); 3012 3013 mutex_enter(&sc->sc_lock); 3014 3015 /* 3016 * If an abort is already in progress then just wait for it to 3017 * complete and return. 3018 */ 3019 if (xfer->hcflags & UXFER_ABORTING) { 3020 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3021 #ifdef DIAGNOSTIC 3022 if (status == USBD_TIMEOUT) 3023 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3024 #endif 3025 /* Override the status which might be USBD_TIMEOUT. */ 3026 xfer->status = status; 3027 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3028 xfer->hcflags |= UXFER_ABORTWAIT; 3029 while (xfer->hcflags & UXFER_ABORTING) 3030 cv_wait(&xfer->hccv, &sc->sc_lock); 3031 mutex_exit(&sc->sc_lock); 3032 return; 3033 } 3034 xfer->hcflags |= UXFER_ABORTING; 3035 3036 /* 3037 * Step 1: Make interrupt routine and hardware ignore xfer. 3038 */ 3039 xfer->status = status; /* make software ignore it */ 3040 callout_stop(&xfer->timeout_handle); 3041 3042 usb_syncmem(&sqh->dma, 3043 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3044 sizeof(sqh->qh.qh_qtd.qtd_status), 3045 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3046 qhstatus = sqh->qh.qh_qtd.qtd_status; 3047 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3048 usb_syncmem(&sqh->dma, 3049 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3050 sizeof(sqh->qh.qh_qtd.qtd_status), 3051 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3052 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3053 usb_syncmem(&sqtd->dma, 3054 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3055 sizeof(sqtd->qtd.qtd_status), 3056 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3057 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3058 usb_syncmem(&sqtd->dma, 3059 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3060 sizeof(sqtd->qtd.qtd_status), 3061 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3062 if (sqtd == exfer->sqtdend) 3063 break; 3064 } 3065 3066 /* 3067 * Step 2: Wait until we know hardware has finished any possible 3068 * use of the xfer. Also make sure the soft interrupt routine 3069 * has run. 3070 */ 3071 ehci_sync_hc(sc); 3072 sc->sc_softwake = 1; 3073 usb_schedsoftintr(&sc->sc_bus); 3074 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3075 3076 /* 3077 * Step 3: Remove any vestiges of the xfer from the hardware. 3078 * The complication here is that the hardware may have executed 3079 * beyond the xfer we're trying to abort. So as we're scanning 3080 * the TDs of this xfer we check if the hardware points to 3081 * any of them. 3082 */ 3083 3084 usb_syncmem(&sqh->dma, 3085 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3086 sizeof(sqh->qh.qh_curqtd), 3087 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3088 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3089 hit = 0; 3090 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3091 hit |= cur == sqtd->physaddr; 3092 if (sqtd == exfer->sqtdend) 3093 break; 3094 } 3095 sqtd = sqtd->nextqtd; 3096 /* Zap curqtd register if hardware pointed inside the xfer. */ 3097 if (hit && sqtd != NULL) { 3098 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3099 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3100 usb_syncmem(&sqh->dma, 3101 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3102 sizeof(sqh->qh.qh_curqtd), 3103 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3104 sqh->qh.qh_qtd.qtd_status = qhstatus; 3105 usb_syncmem(&sqh->dma, 3106 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3107 sizeof(sqh->qh.qh_qtd.qtd_status), 3108 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3109 } else { 3110 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3111 } 3112 3113 /* 3114 * Step 4: Execute callback. 3115 */ 3116 #ifdef DIAGNOSTIC 3117 exfer->isdone = 1; 3118 #endif 3119 wake = xfer->hcflags & UXFER_ABORTWAIT; 3120 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3121 usb_transfer_complete(xfer); 3122 if (wake) { 3123 cv_broadcast(&xfer->hccv); 3124 } 3125 3126 mutex_exit(&sc->sc_lock); 3127 #undef exfer 3128 } 3129 3130 Static void 3131 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3132 { 3133 ehci_isoc_trans_t trans_status; 3134 struct ehci_pipe *epipe; 3135 struct ehci_xfer *exfer; 3136 ehci_softc_t *sc; 3137 struct ehci_soft_itd *itd; 3138 int i, wake; 3139 3140 epipe = (struct ehci_pipe *) xfer->pipe; 3141 exfer = EXFER(xfer); 3142 sc = epipe->pipe.device->bus->hci_private; 3143 3144 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3145 3146 if (sc->sc_dying) { 3147 mutex_enter(&sc->sc_lock); 3148 xfer->status = status; 3149 callout_stop(&xfer->timeout_handle); 3150 usb_transfer_complete(xfer); 3151 mutex_exit(&sc->sc_lock); 3152 return; 3153 } 3154 3155 mutex_enter(&sc->sc_lock); 3156 3157 if (xfer->hcflags & UXFER_ABORTING) { 3158 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3159 3160 #ifdef DIAGNOSTIC 3161 if (status == USBD_TIMEOUT) 3162 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3163 #endif 3164 3165 xfer->status = status; 3166 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3167 xfer->hcflags |= UXFER_ABORTWAIT; 3168 while (xfer->hcflags & UXFER_ABORTING) 3169 cv_wait(&xfer->hccv, &sc->sc_intr_lock); 3170 goto done; 3171 } 3172 xfer->hcflags |= UXFER_ABORTING; 3173 3174 xfer->status = status; 3175 callout_stop(&xfer->timeout_handle); 3176 3177 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3178 usb_syncmem(&itd->dma, 3179 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3180 sizeof(itd->itd.itd_ctl), 3181 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3182 3183 for (i = 0; i < 8; i++) { 3184 trans_status = le32toh(itd->itd.itd_ctl[i]); 3185 trans_status &= ~EHCI_ITD_ACTIVE; 3186 itd->itd.itd_ctl[i] = htole32(trans_status); 3187 } 3188 3189 usb_syncmem(&itd->dma, 3190 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3191 sizeof(itd->itd.itd_ctl), 3192 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3193 } 3194 3195 sc->sc_softwake = 1; 3196 usb_schedsoftintr(&sc->sc_bus); 3197 cv_wait(&sc->sc_softwake_cv, &sc->sc_intr_lock); 3198 3199 #ifdef DIAGNOSTIC 3200 exfer->isdone = 1; 3201 #endif 3202 wake = xfer->hcflags & UXFER_ABORTWAIT; 3203 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3204 usb_transfer_complete(xfer); 3205 if (wake) { 3206 cv_broadcast(&xfer->hccv); 3207 } 3208 3209 done: 3210 mutex_exit(&sc->sc_lock); 3211 return; 3212 } 3213 3214 Static void 3215 ehci_timeout(void *addr) 3216 { 3217 struct ehci_xfer *exfer = addr; 3218 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3219 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3220 3221 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3222 #ifdef EHCI_DEBUG 3223 if (ehcidebug > 1) 3224 usbd_dump_pipe(exfer->xfer.pipe); 3225 #endif 3226 3227 if (sc->sc_dying) { 3228 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3229 return; 3230 } 3231 3232 /* Execute the abort in a process context. */ 3233 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3234 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3235 USB_TASKQ_HC); 3236 } 3237 3238 Static void 3239 ehci_timeout_task(void *addr) 3240 { 3241 usbd_xfer_handle xfer = addr; 3242 3243 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3244 3245 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3246 } 3247 3248 /************************/ 3249 3250 Static usbd_status 3251 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3252 { 3253 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3254 usbd_status err; 3255 3256 /* Insert last in queue. */ 3257 mutex_enter(&sc->sc_lock); 3258 err = usb_insert_transfer(xfer); 3259 mutex_exit(&sc->sc_lock); 3260 if (err) 3261 return (err); 3262 3263 /* Pipe isn't running, start first */ 3264 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3265 } 3266 3267 Static usbd_status 3268 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3269 { 3270 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3271 usbd_status err; 3272 3273 if (sc->sc_dying) 3274 return (USBD_IOERROR); 3275 3276 #ifdef DIAGNOSTIC 3277 if (!(xfer->rqflags & URQ_REQUEST)) { 3278 /* XXX panic */ 3279 printf("ehci_device_ctrl_transfer: not a request\n"); 3280 return (USBD_INVAL); 3281 } 3282 #endif 3283 3284 err = ehci_device_request(xfer); 3285 if (err) { 3286 return (err); 3287 } 3288 3289 if (sc->sc_bus.use_polling) 3290 ehci_waitintr(sc, xfer); 3291 3292 return (USBD_IN_PROGRESS); 3293 } 3294 3295 Static void 3296 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3297 { 3298 struct ehci_xfer *ex = EXFER(xfer); 3299 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3300 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3301 usb_device_request_t *req = &xfer->request; 3302 int len = UGETW(req->wLength); 3303 int rd = req->bmRequestType & UT_READ; 3304 3305 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3306 3307 KASSERT(mutex_owned(&sc->sc_lock)); 3308 3309 #ifdef DIAGNOSTIC 3310 if (!(xfer->rqflags & URQ_REQUEST)) { 3311 panic("ehci_ctrl_done: not a request"); 3312 } 3313 #endif 3314 3315 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3316 ehci_del_intr_list(sc, ex); /* remove from active list */ 3317 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3318 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3319 BUS_DMASYNC_POSTWRITE); 3320 if (len) 3321 usb_syncmem(&xfer->dmabuf, 0, len, 3322 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3323 } 3324 3325 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3326 } 3327 3328 /* Abort a device control request. */ 3329 Static void 3330 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3331 { 3332 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3333 ehci_abort_xfer(xfer, USBD_CANCELLED); 3334 } 3335 3336 /* Close a device control pipe. */ 3337 Static void 3338 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3339 { 3340 ehci_softc_t *sc = pipe->device->bus->hci_private; 3341 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3342 3343 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3344 3345 mutex_enter(&sc->sc_lock); 3346 ehci_close_pipe(pipe, sc->sc_async_head); 3347 mutex_exit(&sc->sc_lock); 3348 } 3349 3350 Static usbd_status 3351 ehci_device_request(usbd_xfer_handle xfer) 3352 { 3353 #define exfer EXFER(xfer) 3354 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3355 usb_device_request_t *req = &xfer->request; 3356 usbd_device_handle dev = epipe->pipe.device; 3357 ehci_softc_t *sc = dev->bus->hci_private; 3358 int addr = dev->address; 3359 ehci_soft_qtd_t *setup, *stat, *next; 3360 ehci_soft_qh_t *sqh; 3361 int isread; 3362 int len; 3363 usbd_status err; 3364 3365 isread = req->bmRequestType & UT_READ; 3366 len = UGETW(req->wLength); 3367 3368 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3369 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3370 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3371 UGETW(req->wIndex), len, addr, 3372 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3373 3374 setup = ehci_alloc_sqtd(sc); 3375 if (setup == NULL) { 3376 err = USBD_NOMEM; 3377 goto bad1; 3378 } 3379 stat = ehci_alloc_sqtd(sc); 3380 if (stat == NULL) { 3381 err = USBD_NOMEM; 3382 goto bad2; 3383 } 3384 3385 mutex_enter(&sc->sc_lock); 3386 3387 sqh = epipe->sqh; 3388 epipe->u.ctl.length = len; 3389 3390 /* Update device address and length since they may have changed 3391 during the setup of the control pipe in usbd_new_device(). */ 3392 /* XXX This only needs to be done once, but it's too early in open. */ 3393 /* XXXX Should not touch ED here! */ 3394 sqh->qh.qh_endp = 3395 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3396 htole32( 3397 EHCI_QH_SET_ADDR(addr) | 3398 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3399 ); 3400 3401 /* Set up data transaction */ 3402 if (len != 0) { 3403 ehci_soft_qtd_t *end; 3404 3405 /* Start toggle at 1. */ 3406 epipe->nexttoggle = 1; 3407 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3408 &next, &end); 3409 if (err) 3410 goto bad3; 3411 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3412 end->nextqtd = stat; 3413 end->qtd.qtd_next = 3414 end->qtd.qtd_altnext = htole32(stat->physaddr); 3415 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3416 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3417 } else { 3418 next = stat; 3419 } 3420 3421 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3422 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3423 3424 /* Clear toggle */ 3425 setup->qtd.qtd_status = htole32( 3426 EHCI_QTD_ACTIVE | 3427 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3428 EHCI_QTD_SET_CERR(3) | 3429 EHCI_QTD_SET_TOGGLE(0) | 3430 EHCI_QTD_SET_BYTES(sizeof *req) 3431 ); 3432 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3433 setup->qtd.qtd_buffer_hi[0] = 0; 3434 setup->nextqtd = next; 3435 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3436 setup->xfer = xfer; 3437 setup->len = sizeof *req; 3438 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3439 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3440 3441 stat->qtd.qtd_status = htole32( 3442 EHCI_QTD_ACTIVE | 3443 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3444 EHCI_QTD_SET_CERR(3) | 3445 EHCI_QTD_SET_TOGGLE(1) | 3446 EHCI_QTD_IOC 3447 ); 3448 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3449 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3450 stat->nextqtd = NULL; 3451 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3452 stat->xfer = xfer; 3453 stat->len = 0; 3454 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3455 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3456 3457 #ifdef EHCI_DEBUG 3458 if (ehcidebug > 5) { 3459 DPRINTF(("ehci_device_request:\n")); 3460 ehci_dump_sqh(sqh); 3461 ehci_dump_sqtds(setup); 3462 } 3463 #endif 3464 3465 exfer->sqtdstart = setup; 3466 exfer->sqtdend = stat; 3467 #ifdef DIAGNOSTIC 3468 if (!exfer->isdone) { 3469 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3470 } 3471 exfer->isdone = 0; 3472 #endif 3473 3474 /* Insert qTD in QH list. */ 3475 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3476 if (xfer->timeout && !sc->sc_bus.use_polling) { 3477 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3478 (ehci_timeout), (xfer)); 3479 } 3480 ehci_add_intr_list(sc, exfer); 3481 xfer->status = USBD_IN_PROGRESS; 3482 mutex_exit(&sc->sc_lock); 3483 3484 #ifdef EHCI_DEBUG 3485 if (ehcidebug > 10) { 3486 DPRINTF(("ehci_device_request: status=%x\n", 3487 EOREAD4(sc, EHCI_USBSTS))); 3488 delay(10000); 3489 ehci_dump_regs(sc); 3490 ehci_dump_sqh(sc->sc_async_head); 3491 ehci_dump_sqh(sqh); 3492 ehci_dump_sqtds(setup); 3493 } 3494 #endif 3495 3496 return (USBD_NORMAL_COMPLETION); 3497 3498 bad3: 3499 mutex_exit(&sc->sc_lock); 3500 ehci_free_sqtd(sc, stat); 3501 bad2: 3502 ehci_free_sqtd(sc, setup); 3503 bad1: 3504 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3505 mutex_enter(&sc->sc_lock); 3506 xfer->status = err; 3507 usb_transfer_complete(xfer); 3508 mutex_exit(&sc->sc_lock); 3509 return (err); 3510 #undef exfer 3511 } 3512 3513 /* 3514 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3515 * qTD status, or miss signalling occasionally under heavy load. If the host 3516 * machine is too fast, we we can miss transaction completion - when we scan 3517 * the active list the transaction still seems to be active. This generally 3518 * exhibits itself as a umass stall that never recovers. 3519 * 3520 * We work around this behaviour by setting up this callback after any softintr 3521 * that completes with transactions still pending, giving us another chance to 3522 * check for completion after the writeback has taken place. 3523 */ 3524 Static void 3525 ehci_intrlist_timeout(void *arg) 3526 { 3527 ehci_softc_t *sc = arg; 3528 3529 DPRINTF(("ehci_intrlist_timeout\n")); 3530 mutex_spin_enter(&sc->sc_intr_lock); 3531 usb_schedsoftintr(&sc->sc_bus); 3532 mutex_spin_exit(&sc->sc_intr_lock); 3533 } 3534 3535 /************************/ 3536 3537 Static usbd_status 3538 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3539 { 3540 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3541 usbd_status err; 3542 3543 /* Insert last in queue. */ 3544 mutex_enter(&sc->sc_lock); 3545 err = usb_insert_transfer(xfer); 3546 mutex_exit(&sc->sc_lock); 3547 if (err) 3548 return (err); 3549 3550 /* Pipe isn't running, start first */ 3551 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3552 } 3553 3554 Static usbd_status 3555 ehci_device_bulk_start(usbd_xfer_handle xfer) 3556 { 3557 #define exfer EXFER(xfer) 3558 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3559 usbd_device_handle dev = epipe->pipe.device; 3560 ehci_softc_t *sc = dev->bus->hci_private; 3561 ehci_soft_qtd_t *data, *dataend; 3562 ehci_soft_qh_t *sqh; 3563 usbd_status err; 3564 int len, isread, endpt; 3565 3566 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3567 xfer, xfer->length, xfer->flags)); 3568 3569 if (sc->sc_dying) 3570 return (USBD_IOERROR); 3571 3572 #ifdef DIAGNOSTIC 3573 if (xfer->rqflags & URQ_REQUEST) 3574 panic("ehci_device_bulk_start: a request"); 3575 #endif 3576 3577 len = xfer->length; 3578 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3579 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3580 sqh = epipe->sqh; 3581 3582 epipe->u.bulk.length = len; 3583 3584 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3585 &dataend); 3586 if (err) { 3587 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3588 xfer->status = err; 3589 usb_transfer_complete(xfer); 3590 return (err); 3591 } 3592 3593 #ifdef EHCI_DEBUG 3594 if (ehcidebug > 5) { 3595 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3596 ehci_dump_sqh(sqh); 3597 ehci_dump_sqtds(data); 3598 } 3599 #endif 3600 3601 /* Set up interrupt info. */ 3602 exfer->sqtdstart = data; 3603 exfer->sqtdend = dataend; 3604 #ifdef DIAGNOSTIC 3605 if (!exfer->isdone) { 3606 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3607 } 3608 exfer->isdone = 0; 3609 #endif 3610 3611 mutex_enter(&sc->sc_lock); 3612 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3613 if (xfer->timeout && !sc->sc_bus.use_polling) { 3614 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3615 (ehci_timeout), (xfer)); 3616 } 3617 ehci_add_intr_list(sc, exfer); 3618 xfer->status = USBD_IN_PROGRESS; 3619 mutex_exit(&sc->sc_lock); 3620 3621 #ifdef EHCI_DEBUG 3622 if (ehcidebug > 10) { 3623 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3624 delay(10000); 3625 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3626 ehci_dump_regs(sc); 3627 #if 0 3628 printf("async_head:\n"); 3629 ehci_dump_sqh(sc->sc_async_head); 3630 #endif 3631 printf("sqh:\n"); 3632 ehci_dump_sqh(sqh); 3633 ehci_dump_sqtds(data); 3634 } 3635 #endif 3636 3637 if (sc->sc_bus.use_polling) 3638 ehci_waitintr(sc, xfer); 3639 3640 return (USBD_IN_PROGRESS); 3641 #undef exfer 3642 } 3643 3644 Static void 3645 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3646 { 3647 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3648 ehci_abort_xfer(xfer, USBD_CANCELLED); 3649 } 3650 3651 /* 3652 * Close a device bulk pipe. 3653 */ 3654 Static void 3655 ehci_device_bulk_close(usbd_pipe_handle pipe) 3656 { 3657 ehci_softc_t *sc = pipe->device->bus->hci_private; 3658 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3659 3660 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3661 mutex_enter(&sc->sc_lock); 3662 pipe->endpoint->datatoggle = epipe->nexttoggle; 3663 ehci_close_pipe(pipe, sc->sc_async_head); 3664 mutex_exit(&sc->sc_lock); 3665 } 3666 3667 Static void 3668 ehci_device_bulk_done(usbd_xfer_handle xfer) 3669 { 3670 struct ehci_xfer *ex = EXFER(xfer); 3671 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3672 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3673 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3674 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3675 3676 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3677 xfer, xfer->actlen)); 3678 3679 KASSERT(mutex_owned(&sc->sc_lock)); 3680 3681 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3682 ehci_del_intr_list(sc, ex); /* remove from active list */ 3683 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3684 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3685 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3686 } 3687 3688 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3689 } 3690 3691 /************************/ 3692 3693 Static usbd_status 3694 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3695 { 3696 struct ehci_soft_islot *isp; 3697 int islot, lev; 3698 3699 /* Find a poll rate that is large enough. */ 3700 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3701 if (EHCI_ILEV_IVAL(lev) <= ival) 3702 break; 3703 3704 /* Pick an interrupt slot at the right level. */ 3705 /* XXX could do better than picking at random */ 3706 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3707 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3708 3709 sqh->islot = islot; 3710 isp = &sc->sc_islots[islot]; 3711 ehci_add_qh(sqh, isp->sqh); 3712 3713 return (USBD_NORMAL_COMPLETION); 3714 } 3715 3716 Static usbd_status 3717 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3718 { 3719 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3720 usbd_status err; 3721 3722 /* Insert last in queue. */ 3723 mutex_enter(&sc->sc_lock); 3724 err = usb_insert_transfer(xfer); 3725 mutex_exit(&sc->sc_lock); 3726 if (err) 3727 return (err); 3728 3729 /* 3730 * Pipe isn't running (otherwise err would be USBD_INPROG), 3731 * so start it first. 3732 */ 3733 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3734 } 3735 3736 Static usbd_status 3737 ehci_device_intr_start(usbd_xfer_handle xfer) 3738 { 3739 #define exfer EXFER(xfer) 3740 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3741 usbd_device_handle dev = xfer->pipe->device; 3742 ehci_softc_t *sc = dev->bus->hci_private; 3743 ehci_soft_qtd_t *data, *dataend; 3744 ehci_soft_qh_t *sqh; 3745 usbd_status err; 3746 int len, isread, endpt; 3747 3748 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3749 xfer, xfer->length, xfer->flags)); 3750 3751 if (sc->sc_dying) 3752 return (USBD_IOERROR); 3753 3754 #ifdef DIAGNOSTIC 3755 if (xfer->rqflags & URQ_REQUEST) 3756 panic("ehci_device_intr_start: a request"); 3757 #endif 3758 3759 len = xfer->length; 3760 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3761 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3762 sqh = epipe->sqh; 3763 3764 epipe->u.intr.length = len; 3765 3766 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3767 &dataend); 3768 if (err) { 3769 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3770 xfer->status = err; 3771 usb_transfer_complete(xfer); 3772 return (err); 3773 } 3774 3775 #ifdef EHCI_DEBUG 3776 if (ehcidebug > 5) { 3777 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3778 ehci_dump_sqh(sqh); 3779 ehci_dump_sqtds(data); 3780 } 3781 #endif 3782 3783 /* Set up interrupt info. */ 3784 exfer->sqtdstart = data; 3785 exfer->sqtdend = dataend; 3786 #ifdef DIAGNOSTIC 3787 if (!exfer->isdone) { 3788 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3789 } 3790 exfer->isdone = 0; 3791 #endif 3792 3793 mutex_enter(&sc->sc_lock); 3794 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3795 if (xfer->timeout && !sc->sc_bus.use_polling) { 3796 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3797 (ehci_timeout), (xfer)); 3798 } 3799 ehci_add_intr_list(sc, exfer); 3800 xfer->status = USBD_IN_PROGRESS; 3801 mutex_exit(&sc->sc_lock); 3802 3803 #ifdef EHCI_DEBUG 3804 if (ehcidebug > 10) { 3805 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3806 delay(10000); 3807 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3808 ehci_dump_regs(sc); 3809 printf("sqh:\n"); 3810 ehci_dump_sqh(sqh); 3811 ehci_dump_sqtds(data); 3812 } 3813 #endif 3814 3815 if (sc->sc_bus.use_polling) 3816 ehci_waitintr(sc, xfer); 3817 3818 return (USBD_IN_PROGRESS); 3819 #undef exfer 3820 } 3821 3822 Static void 3823 ehci_device_intr_abort(usbd_xfer_handle xfer) 3824 { 3825 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3826 if (xfer->pipe->intrxfer == xfer) { 3827 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3828 xfer->pipe->intrxfer = NULL; 3829 } 3830 /* 3831 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3832 * async doorbell. That's dependent on the async list, wheras 3833 * intr xfers are periodic, should not use this? 3834 */ 3835 ehci_abort_xfer(xfer, USBD_CANCELLED); 3836 } 3837 3838 Static void 3839 ehci_device_intr_close(usbd_pipe_handle pipe) 3840 { 3841 ehci_softc_t *sc = pipe->device->bus->hci_private; 3842 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3843 struct ehci_soft_islot *isp; 3844 3845 isp = &sc->sc_islots[epipe->sqh->islot]; 3846 ehci_close_pipe(pipe, isp->sqh); 3847 } 3848 3849 Static void 3850 ehci_device_intr_done(usbd_xfer_handle xfer) 3851 { 3852 #define exfer EXFER(xfer) 3853 struct ehci_xfer *ex = EXFER(xfer); 3854 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3855 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3856 ehci_soft_qtd_t *data, *dataend; 3857 ehci_soft_qh_t *sqh; 3858 usbd_status err; 3859 int len, isread, endpt; 3860 3861 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3862 xfer, xfer->actlen)); 3863 3864 KASSERT(mutex_owned(&sc->sc_lock)); 3865 3866 if (xfer->pipe->repeat) { 3867 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3868 3869 len = epipe->u.intr.length; 3870 xfer->length = len; 3871 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3872 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3873 usb_syncmem(&xfer->dmabuf, 0, len, 3874 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3875 sqh = epipe->sqh; 3876 3877 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3878 &data, &dataend); 3879 if (err) { 3880 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3881 xfer->status = err; 3882 return; 3883 } 3884 3885 /* Set up interrupt info. */ 3886 exfer->sqtdstart = data; 3887 exfer->sqtdend = dataend; 3888 #ifdef DIAGNOSTIC 3889 if (!exfer->isdone) { 3890 printf("ehci_device_intr_done: not done, ex=%p\n", 3891 exfer); 3892 } 3893 exfer->isdone = 0; 3894 #endif 3895 3896 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3897 if (xfer->timeout && !sc->sc_bus.use_polling) { 3898 callout_reset(&(xfer->timeout_handle), 3899 (mstohz(xfer->timeout)), (ehci_timeout), (xfer)); 3900 } 3901 3902 xfer->status = USBD_IN_PROGRESS; 3903 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3904 ehci_del_intr_list(sc, ex); /* remove from active list */ 3905 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3906 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3907 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3908 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3909 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3910 } 3911 #undef exfer 3912 } 3913 3914 /************************/ 3915 3916 Static usbd_status 3917 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3918 { 3919 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3920 usbd_status err; 3921 3922 mutex_enter(&sc->sc_lock); 3923 err = usb_insert_transfer(xfer); 3924 mutex_exit(&sc->sc_lock); 3925 if (err && err != USBD_IN_PROGRESS) 3926 return err; 3927 3928 return ehci_device_isoc_start(xfer); 3929 } 3930 3931 Static usbd_status 3932 ehci_device_isoc_start(usbd_xfer_handle xfer) 3933 { 3934 struct ehci_pipe *epipe; 3935 usbd_device_handle dev; 3936 ehci_softc_t *sc; 3937 struct ehci_xfer *exfer; 3938 ehci_soft_itd_t *itd, *prev, *start, *stop; 3939 usb_dma_t *dma_buf; 3940 int i, j, k, frames, uframes, ufrperframe; 3941 int trans_count, offs, total_length; 3942 int frindex; 3943 3944 start = NULL; 3945 prev = NULL; 3946 itd = NULL; 3947 trans_count = 0; 3948 total_length = 0; 3949 exfer = (struct ehci_xfer *) xfer; 3950 sc = xfer->pipe->device->bus->hci_private; 3951 dev = xfer->pipe->device; 3952 epipe = (struct ehci_pipe *)xfer->pipe; 3953 3954 /* 3955 * To allow continuous transfers, above we start all transfers 3956 * immediately. However, we're still going to get usbd_start_next call 3957 * this when another xfer completes. So, check if this is already 3958 * in progress or not 3959 */ 3960 3961 if (exfer->itdstart != NULL) 3962 return USBD_IN_PROGRESS; 3963 3964 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3965 xfer, xfer->length, xfer->flags)); 3966 3967 if (sc->sc_dying) 3968 return USBD_IOERROR; 3969 3970 /* 3971 * To avoid complication, don't allow a request right now that'll span 3972 * the entire frame table. To within 4 frames, to allow some leeway 3973 * on either side of where the hc currently is. 3974 */ 3975 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3976 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3977 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3978 return USBD_INVAL; 3979 } 3980 3981 #ifdef DIAGNOSTIC 3982 if (xfer->rqflags & URQ_REQUEST) 3983 panic("ehci_device_isoc_start: request\n"); 3984 3985 if (!exfer->isdone) 3986 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3987 exfer->isdone = 0; 3988 #endif 3989 3990 /* 3991 * Step 1: Allocate and initialize itds, how many do we need? 3992 * One per transfer if interval >= 8 microframes, fewer if we use 3993 * multiple microframes per frame. 3994 */ 3995 3996 i = epipe->pipe.endpoint->edesc->bInterval; 3997 if (i > 16 || i == 0) { 3998 /* Spec page 271 says intervals > 16 are invalid */ 3999 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 4000 return USBD_INVAL; 4001 } 4002 4003 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4004 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4005 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4006 4007 if (frames == 0) { 4008 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 4009 return USBD_INVAL; 4010 } 4011 4012 dma_buf = &xfer->dmabuf; 4013 offs = 0; 4014 4015 for (i = 0; i < frames; i++) { 4016 int froffs = offs; 4017 itd = ehci_alloc_itd(sc); 4018 4019 if (prev != NULL) { 4020 prev->itd.itd_next = 4021 htole32(itd->physaddr | EHCI_LINK_ITD); 4022 usb_syncmem(&itd->dma, 4023 itd->offs + offsetof(ehci_itd_t, itd_next), 4024 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4025 4026 prev->xfer_next = itd; 4027 } else { 4028 start = itd; 4029 } 4030 4031 /* 4032 * Step 1.5, initialize uframes 4033 */ 4034 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4035 /* Calculate which page in the list this starts in */ 4036 int addr = DMAADDR(dma_buf, froffs); 4037 addr = EHCI_PAGE_OFFSET(addr); 4038 addr += (offs - froffs); 4039 addr = EHCI_PAGE(addr); 4040 addr /= EHCI_PAGE_SIZE; 4041 4042 /* This gets the initial offset into the first page, 4043 * looks how far further along the current uframe 4044 * offset is. Works out how many pages that is. 4045 */ 4046 4047 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4048 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4049 EHCI_ITD_SET_PG(addr) | 4050 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4051 4052 total_length += xfer->frlengths[trans_count]; 4053 offs += xfer->frlengths[trans_count]; 4054 trans_count++; 4055 4056 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4057 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4058 break; 4059 } 4060 } 4061 4062 /* Step 1.75, set buffer pointers. To simplify matters, all 4063 * pointers are filled out for the next 7 hardware pages in 4064 * the dma block, so no need to worry what pages to cover 4065 * and what to not. 4066 */ 4067 4068 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4069 /* 4070 * Don't try to lookup a page that's past the end 4071 * of buffer 4072 */ 4073 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4074 if (page_offs >= dma_buf->block->size) 4075 break; 4076 4077 unsigned long long page = DMAADDR(dma_buf, page_offs); 4078 page = EHCI_PAGE(page); 4079 itd->itd.itd_bufr[j] = 4080 htole32(EHCI_ITD_SET_BPTR(page)); 4081 itd->itd.itd_bufr_hi[j] = 4082 htole32(page >> 32); 4083 } 4084 4085 /* 4086 * Other special values 4087 */ 4088 4089 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4090 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4091 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4092 4093 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4094 ? 1 : 0; 4095 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4096 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4097 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4098 4099 /* FIXME: handle invalid trans */ 4100 itd->itd.itd_bufr[2] |= 4101 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4102 4103 usb_syncmem(&itd->dma, 4104 itd->offs + offsetof(ehci_itd_t, itd_next), 4105 sizeof(ehci_itd_t), 4106 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4107 4108 prev = itd; 4109 } /* End of frame */ 4110 4111 stop = itd; 4112 stop->xfer_next = NULL; 4113 exfer->isoc_len = total_length; 4114 4115 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4116 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4117 4118 /* 4119 * Part 2: Transfer descriptors have now been set up, now they must 4120 * be scheduled into the period frame list. Erk. Not wanting to 4121 * complicate matters, transfer is denied if the transfer spans 4122 * more than the period frame list. 4123 */ 4124 4125 mutex_enter(&sc->sc_lock); 4126 4127 /* Start inserting frames */ 4128 if (epipe->u.isoc.cur_xfers > 0) { 4129 frindex = epipe->u.isoc.next_frame; 4130 } else { 4131 frindex = EOREAD4(sc, EHCI_FRINDEX); 4132 frindex = frindex >> 3; /* Erase microframe index */ 4133 frindex += 2; 4134 } 4135 4136 if (frindex >= sc->sc_flsize) 4137 frindex &= (sc->sc_flsize - 1); 4138 4139 /* What's the frame interval? */ 4140 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4141 if (i / USB_UFRAMES_PER_FRAME == 0) 4142 i = 1; 4143 else 4144 i /= USB_UFRAMES_PER_FRAME; 4145 4146 itd = start; 4147 for (j = 0; j < frames; j++) { 4148 if (itd == NULL) 4149 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4150 4151 itd->itd.itd_next = sc->sc_flist[frindex]; 4152 if (itd->itd.itd_next == 0) 4153 /* FIXME: frindex table gets initialized to NULL 4154 * or EHCI_NULL? */ 4155 itd->itd.itd_next = EHCI_NULL; 4156 4157 usb_syncmem(&itd->dma, 4158 itd->offs + offsetof(ehci_itd_t, itd_next), 4159 sizeof(itd->itd.itd_next), 4160 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4161 4162 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4163 4164 usb_syncmem(&sc->sc_fldma, 4165 sizeof(ehci_link_t) * frindex, 4166 sizeof(ehci_link_t), 4167 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4168 4169 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4170 sc->sc_softitds[frindex] = itd; 4171 if (itd->u.frame_list.next != NULL) 4172 itd->u.frame_list.next->u.frame_list.prev = itd; 4173 itd->slot = frindex; 4174 itd->u.frame_list.prev = NULL; 4175 4176 frindex += i; 4177 if (frindex >= sc->sc_flsize) 4178 frindex -= sc->sc_flsize; 4179 4180 itd = itd->xfer_next; 4181 } 4182 4183 epipe->u.isoc.cur_xfers++; 4184 epipe->u.isoc.next_frame = frindex; 4185 4186 exfer->itdstart = start; 4187 exfer->itdend = stop; 4188 exfer->sqtdstart = NULL; 4189 exfer->sqtdstart = NULL; 4190 4191 ehci_add_intr_list(sc, exfer); 4192 xfer->status = USBD_IN_PROGRESS; 4193 xfer->done = 0; 4194 mutex_exit(&sc->sc_lock); 4195 4196 if (sc->sc_bus.use_polling) { 4197 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4198 ehci_waitintr(sc, xfer); 4199 } 4200 4201 return USBD_IN_PROGRESS; 4202 } 4203 4204 Static void 4205 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4206 { 4207 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4208 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4209 } 4210 4211 Static void 4212 ehci_device_isoc_close(usbd_pipe_handle pipe) 4213 { 4214 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4215 } 4216 4217 Static void 4218 ehci_device_isoc_done(usbd_xfer_handle xfer) 4219 { 4220 struct ehci_xfer *exfer; 4221 ehci_softc_t *sc; 4222 struct ehci_pipe *epipe; 4223 4224 exfer = EXFER(xfer); 4225 sc = xfer->pipe->device->bus->hci_private; 4226 epipe = (struct ehci_pipe *) xfer->pipe; 4227 4228 KASSERT(mutex_owned(&sc->sc_lock)); 4229 4230 epipe->u.isoc.cur_xfers--; 4231 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4232 ehci_del_intr_list(sc, exfer); 4233 ehci_rem_free_itd_chain(sc, exfer); 4234 } 4235 4236 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4237 BUS_DMASYNC_POSTREAD); 4238 4239 } 4240
Indexes created Thu Oct 02 01:09:59 GMT 2025