ehci.c revision 1.181.6.10
1 /* $NetBSD: ehci.c,v 1.181.6.10 2012/02/20 22:42:24 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2011 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), and Jared D. McNeill 10 * (jmcneill (at) invisible.ca). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.181.6.10 2012/02/20 22:42:24 mrg Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/kmem.h> 66 #include <sys/device.h> 67 #include <sys/select.h> 68 #include <sys/proc.h> 69 #include <sys/queue.h> 70 #include <sys/mutex.h> 71 #include <sys/bus.h> 72 73 #include <machine/endian.h> 74 75 #include <dev/usb/usb.h> 76 #include <dev/usb/usbdi.h> 77 #include <dev/usb/usbdivar.h> 78 #include <dev/usb/usb_mem.h> 79 #include <dev/usb/usb_quirks.h> 80 81 #include <dev/usb/ehcireg.h> 82 #include <dev/usb/ehcivar.h> 83 #include <dev/usb/usbroothub_subr.h> 84 85 #ifdef EHCI_DEBUG 86 #include <sys/kprintf.h> 87 static void 88 ehciprintf(const char *fmt, ...) 89 { 90 va_list ap; 91 92 va_start(ap, fmt); 93 kprintf(fmt, TOLOG|TOCONS, NULL, NULL, ap); 94 va_end(ap); 95 } 96 97 #define DPRINTF(x) do { if (ehcidebug) ehciprintf x; } while(0) 98 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) ehciprintf x; } while (0) 99 int ehcidebug = 0; 100 #else 101 #define DPRINTF(x) 102 #define DPRINTFN(n,x) 103 #endif 104 105 struct ehci_pipe { 106 struct usbd_pipe pipe; 107 int nexttoggle; 108 109 ehci_soft_qh_t *sqh; 110 union { 111 ehci_soft_qtd_t *qtd; 112 /* ehci_soft_itd_t *itd; */ 113 } tail; 114 union { 115 /* Control pipe */ 116 struct { 117 usb_dma_t reqdma; 118 u_int length; 119 } ctl; 120 /* Interrupt pipe */ 121 struct { 122 u_int length; 123 } intr; 124 /* Bulk pipe */ 125 struct { 126 u_int length; 127 } bulk; 128 /* Iso pipe */ 129 struct { 130 u_int next_frame; 131 u_int cur_xfers; 132 } isoc; 133 } u; 134 }; 135 136 Static usbd_status ehci_open(usbd_pipe_handle); 137 Static void ehci_poll(struct usbd_bus *); 138 Static void ehci_softintr(void *); 139 Static int ehci_intr1(ehci_softc_t *); 140 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 141 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 142 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 143 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 144 Static void ehci_idone(struct ehci_xfer *); 145 Static void ehci_timeout(void *); 146 Static void ehci_timeout_task(void *); 147 Static void ehci_intrlist_timeout(void *); 148 Static void ehci_doorbell(void *); 149 Static void ehci_pcd(void *); 150 151 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 152 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 153 154 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 155 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 156 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 157 158 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 159 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 160 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 161 Static void ehci_root_ctrl_close(usbd_pipe_handle); 162 Static void ehci_root_ctrl_done(usbd_xfer_handle); 163 164 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 165 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 166 Static void ehci_root_intr_abort(usbd_xfer_handle); 167 Static void ehci_root_intr_close(usbd_pipe_handle); 168 Static void ehci_root_intr_done(usbd_xfer_handle); 169 170 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 171 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 172 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 173 Static void ehci_device_ctrl_close(usbd_pipe_handle); 174 Static void ehci_device_ctrl_done(usbd_xfer_handle); 175 176 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 177 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 178 Static void ehci_device_bulk_abort(usbd_xfer_handle); 179 Static void ehci_device_bulk_close(usbd_pipe_handle); 180 Static void ehci_device_bulk_done(usbd_xfer_handle); 181 182 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 183 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 184 Static void ehci_device_intr_abort(usbd_xfer_handle); 185 Static void ehci_device_intr_close(usbd_pipe_handle); 186 Static void ehci_device_intr_done(usbd_xfer_handle); 187 188 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 189 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 190 Static void ehci_device_isoc_abort(usbd_xfer_handle); 191 Static void ehci_device_isoc_close(usbd_pipe_handle); 192 Static void ehci_device_isoc_done(usbd_xfer_handle); 193 194 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 195 Static void ehci_noop(usbd_pipe_handle pipe); 196 197 Static void ehci_disown(ehci_softc_t *, int, int); 198 199 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 200 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 201 202 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 203 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 204 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 205 ehci_softc_t *, int, int, usbd_xfer_handle, 206 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 207 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 208 ehci_soft_qtd_t *); 209 210 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 211 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 212 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 213 struct ehci_xfer *exfer); 214 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 215 usbd_status status); 216 217 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 218 219 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 220 int ival); 221 222 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 223 ehci_soft_qh_t *); 224 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 225 ehci_soft_qh_t *); 226 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 227 Static void ehci_sync_hc(ehci_softc_t *); 228 229 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 230 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 231 232 #ifdef EHCI_DEBUG 233 Static void ehci_dump_regs(ehci_softc_t *); 234 void ehci_dump(void); 235 Static ehci_softc_t *theehci; 236 Static void ehci_dump_link(ehci_link_t, int); 237 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 238 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 239 Static void ehci_dump_qtd(ehci_qtd_t *); 240 Static void ehci_dump_sqh(ehci_soft_qh_t *); 241 #if notyet 242 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 243 Static void ehci_dump_itd(struct ehci_soft_itd *); 244 #endif 245 #ifdef DIAGNOSTIC 246 Static void ehci_dump_exfer(struct ehci_xfer *); 247 #endif 248 #endif 249 250 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 251 252 #define EHCI_INTR_ENDPT 1 253 254 #define ehci_add_intr_list(sc, ex) \ 255 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 256 #define ehci_del_intr_list(sc, ex) \ 257 do { \ 258 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 259 (ex)->inext.tqe_prev = NULL; \ 260 } while (0) 261 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 262 263 Static const struct usbd_bus_methods ehci_bus_methods = { 264 .open_pipe = ehci_open, 265 .soft_intr = ehci_softintr, 266 .do_poll = ehci_poll, 267 .allocm = ehci_allocm, 268 .freem = ehci_freem, 269 .allocx = ehci_allocx, 270 .freex = ehci_freex, 271 .get_lock = ehci_get_lock, 272 }; 273 274 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 275 .transfer = ehci_root_ctrl_transfer, 276 .start = ehci_root_ctrl_start, 277 .abort = ehci_root_ctrl_abort, 278 .close = ehci_root_ctrl_close, 279 .cleartoggle = ehci_noop, 280 .done = ehci_root_ctrl_done, 281 }; 282 283 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 284 .transfer = ehci_root_intr_transfer, 285 .start = ehci_root_intr_start, 286 .abort = ehci_root_intr_abort, 287 .close = ehci_root_intr_close, 288 .cleartoggle = ehci_noop, 289 .done = ehci_root_intr_done, 290 }; 291 292 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 293 .transfer = ehci_device_ctrl_transfer, 294 .start = ehci_device_ctrl_start, 295 .abort = ehci_device_ctrl_abort, 296 .close = ehci_device_ctrl_close, 297 .cleartoggle = ehci_noop, 298 .done = ehci_device_ctrl_done, 299 }; 300 301 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 302 .transfer = ehci_device_intr_transfer, 303 .start = ehci_device_intr_start, 304 .abort = ehci_device_intr_abort, 305 .close = ehci_device_intr_close, 306 .cleartoggle = ehci_device_clear_toggle, 307 .done = ehci_device_intr_done, 308 }; 309 310 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 311 .transfer = ehci_device_bulk_transfer, 312 .start = ehci_device_bulk_start, 313 .abort = ehci_device_bulk_abort, 314 .close = ehci_device_bulk_close, 315 .cleartoggle = ehci_device_clear_toggle, 316 .done = ehci_device_bulk_done, 317 }; 318 319 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 320 .transfer = ehci_device_isoc_transfer, 321 .start = ehci_device_isoc_start, 322 .abort = ehci_device_isoc_abort, 323 .close = ehci_device_isoc_close, 324 .cleartoggle = ehci_noop, 325 .done = ehci_device_isoc_done, 326 }; 327 328 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 329 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 330 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 331 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 332 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 333 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 334 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 335 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 336 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 337 }; 338 339 usbd_status 340 ehci_init(ehci_softc_t *sc) 341 { 342 u_int32_t vers, sparams, cparams, hcr; 343 u_int i; 344 usbd_status err; 345 ehci_soft_qh_t *sqh; 346 u_int ncomp; 347 348 DPRINTF(("ehci_init: start\n")); 349 #ifdef EHCI_DEBUG 350 theehci = sc; 351 #endif 352 353 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 354 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 355 cv_init(&sc->sc_softwake_cv, "ehciab"); 356 cv_init(&sc->sc_doorbell, "ehcidi"); 357 358 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 359 ehci_doorbell, sc); 360 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 361 ehci_pcd, sc); 362 363 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 364 365 vers = EREAD2(sc, EHCI_HCIVERSION); 366 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 367 vers >> 8, vers & 0xff); 368 369 sparams = EREAD4(sc, EHCI_HCSPARAMS); 370 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 371 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 372 ncomp = EHCI_HCS_N_CC(sparams); 373 if (ncomp != sc->sc_ncomp) { 374 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 375 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 376 #if NOHCI == 0 || NUHCI == 0 377 aprint_error("%s: ohci or uhci probably not configured\n", 378 device_xname(sc->sc_dev)); 379 #endif 380 if (ncomp < sc->sc_ncomp) 381 sc->sc_ncomp = ncomp; 382 } 383 if (sc->sc_ncomp > 0) { 384 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 385 aprint_normal("%s: companion controller%s, %d port%s each:", 386 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 387 EHCI_HCS_N_PCC(sparams), 388 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 389 for (i = 0; i < sc->sc_ncomp; i++) 390 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 391 aprint_normal("\n"); 392 } 393 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 394 cparams = EREAD4(sc, EHCI_HCCPARAMS); 395 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 396 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 397 398 if (EHCI_HCC_64BIT(cparams)) { 399 /* MUST clear segment register if 64 bit capable. */ 400 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 401 } 402 403 sc->sc_bus.usbrev = USBREV_2_0; 404 405 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 406 USB_MEM_RESERVE); 407 408 /* Reset the controller */ 409 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 410 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 411 usb_delay_ms(&sc->sc_bus, 1); 412 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 413 for (i = 0; i < 100; i++) { 414 usb_delay_ms(&sc->sc_bus, 1); 415 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 416 if (!hcr) 417 break; 418 } 419 if (hcr) { 420 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 421 return (USBD_IOERROR); 422 } 423 if (sc->sc_vendor_init) 424 sc->sc_vendor_init(sc); 425 426 /* 427 * If we are doing embedded transaction translation function, force 428 * the controller to host mode. 429 */ 430 if (sc->sc_flags & EHCIF_ETTF) { 431 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 432 usbmode &= ~EHCI_USBMODE_CM; 433 usbmode |= EHCI_USBMODE_CM_HOST; 434 EWRITE4(sc, EHCI_USBMODE, usbmode); 435 } 436 437 /* XXX need proper intr scheduling */ 438 sc->sc_rand = 96; 439 440 /* frame list size at default, read back what we got and use that */ 441 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 442 case 0: sc->sc_flsize = 1024; break; 443 case 1: sc->sc_flsize = 512; break; 444 case 2: sc->sc_flsize = 256; break; 445 case 3: return (USBD_IOERROR); 446 } 447 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 448 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 449 if (err) 450 return (err); 451 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 452 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 453 454 for (i = 0; i < sc->sc_flsize; i++) { 455 sc->sc_flist[i] = EHCI_NULL; 456 } 457 458 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 459 460 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 461 KM_SLEEP); 462 if (sc->sc_softitds == NULL) 463 return ENOMEM; 464 LIST_INIT(&sc->sc_freeitds); 465 TAILQ_INIT(&sc->sc_intrhead); 466 467 /* Set up the bus struct. */ 468 sc->sc_bus.methods = &ehci_bus_methods; 469 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 470 471 sc->sc_eintrs = EHCI_NORMAL_INTRS; 472 473 /* 474 * Allocate the interrupt dummy QHs. These are arranged to give poll 475 * intervals that are powers of 2 times 1ms. 476 */ 477 for (i = 0; i < EHCI_INTRQHS; i++) { 478 sqh = ehci_alloc_sqh(sc); 479 if (sqh == NULL) { 480 err = USBD_NOMEM; 481 goto bad1; 482 } 483 sc->sc_islots[i].sqh = sqh; 484 } 485 for (i = 0; i < EHCI_INTRQHS; i++) { 486 sqh = sc->sc_islots[i].sqh; 487 if (i == 0) { 488 /* The last (1ms) QH terminates. */ 489 sqh->qh.qh_link = EHCI_NULL; 490 sqh->next = NULL; 491 } else { 492 /* Otherwise the next QH has half the poll interval */ 493 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 494 sqh->qh.qh_link = htole32(sqh->next->physaddr | 495 EHCI_LINK_QH); 496 } 497 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 498 sqh->qh.qh_curqtd = EHCI_NULL; 499 sqh->next = NULL; 500 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 501 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 502 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 503 sqh->sqtd = NULL; 504 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 505 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 506 } 507 /* Point the frame list at the last level (128ms). */ 508 for (i = 0; i < sc->sc_flsize; i++) { 509 int j; 510 511 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 512 revbits[i & (EHCI_MAX_POLLRATE-1)]; 513 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 514 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 515 i)].sqh->physaddr); 516 } 517 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 518 BUS_DMASYNC_PREWRITE); 519 520 /* Allocate dummy QH that starts the async list. */ 521 sqh = ehci_alloc_sqh(sc); 522 if (sqh == NULL) { 523 err = USBD_NOMEM; 524 goto bad1; 525 } 526 /* Fill the QH */ 527 sqh->qh.qh_endp = 528 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 529 sqh->qh.qh_link = 530 htole32(sqh->physaddr | EHCI_LINK_QH); 531 sqh->qh.qh_curqtd = EHCI_NULL; 532 sqh->next = NULL; 533 /* Fill the overlay qTD */ 534 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 535 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 536 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 537 sqh->sqtd = NULL; 538 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 539 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 540 #ifdef EHCI_DEBUG 541 if (ehcidebug) { 542 ehci_dump_sqh(sqh); 543 } 544 #endif 545 546 /* Point to async list */ 547 sc->sc_async_head = sqh; 548 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 549 550 callout_init(&(sc->sc_tmo_intrlist), CALLOUT_MPSAFE); 551 552 /* Turn on controller */ 553 EOWRITE4(sc, EHCI_USBCMD, 554 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 555 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 556 EHCI_CMD_ASE | 557 EHCI_CMD_PSE | 558 EHCI_CMD_RS); 559 560 /* Take over port ownership */ 561 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 562 563 for (i = 0; i < 100; i++) { 564 usb_delay_ms(&sc->sc_bus, 1); 565 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 566 if (!hcr) 567 break; 568 } 569 if (hcr) { 570 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 571 return (USBD_IOERROR); 572 } 573 574 /* Enable interrupts */ 575 DPRINTFN(1,("ehci_init: enabling\n")); 576 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 577 578 return (USBD_NORMAL_COMPLETION); 579 580 #if 0 581 bad2: 582 ehci_free_sqh(sc, sc->sc_async_head); 583 #endif 584 bad1: 585 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 586 return (err); 587 } 588 589 int 590 ehci_intr(void *v) 591 { 592 ehci_softc_t *sc = v; 593 int ret = 0; 594 595 if (sc == NULL) 596 return 0; 597 598 mutex_spin_enter(&sc->sc_intr_lock); 599 600 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 601 goto done; 602 603 /* If we get an interrupt while polling, then just ignore it. */ 604 if (sc->sc_bus.use_polling) { 605 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 606 607 if (intrs) 608 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 609 #ifdef DIAGNOSTIC 610 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 611 #endif 612 goto done; 613 } 614 615 ret = ehci_intr1(sc); 616 617 done: 618 mutex_spin_exit(&sc->sc_intr_lock); 619 return ret; 620 } 621 622 Static int 623 ehci_intr1(ehci_softc_t *sc) 624 { 625 u_int32_t intrs, eintrs; 626 627 DPRINTFN(20,("ehci_intr1: enter\n")); 628 629 /* In case the interrupt occurs before initialization has completed. */ 630 if (sc == NULL) { 631 #ifdef DIAGNOSTIC 632 printf("ehci_intr1: sc == NULL\n"); 633 #endif 634 return (0); 635 } 636 637 KASSERT(mutex_owned(&sc->sc_intr_lock)); 638 639 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 640 if (!intrs) 641 return (0); 642 643 eintrs = intrs & sc->sc_eintrs; 644 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 645 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 646 (u_int)eintrs)); 647 if (!eintrs) 648 return (0); 649 650 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 651 sc->sc_bus.intr_context++; 652 sc->sc_bus.no_intrs++; 653 if (eintrs & EHCI_STS_IAA) { 654 DPRINTF(("ehci_intr1: door bell\n")); 655 kpreempt_disable(); 656 softint_schedule(sc->sc_doorbell_si); 657 kpreempt_enable(); 658 eintrs &= ~EHCI_STS_IAA; 659 } 660 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 661 DPRINTFN(5,("ehci_intr1: %s %s\n", 662 eintrs & EHCI_STS_INT ? "INT" : "", 663 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 664 usb_schedsoftintr(&sc->sc_bus); 665 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 666 } 667 if (eintrs & EHCI_STS_HSE) { 668 printf("%s: unrecoverable error, controller halted\n", 669 device_xname(sc->sc_dev)); 670 /* XXX what else */ 671 } 672 if (eintrs & EHCI_STS_PCD) { 673 kpreempt_disable(); 674 softint_schedule(sc->sc_pcd_si); 675 kpreempt_enable(); 676 eintrs &= ~EHCI_STS_PCD; 677 } 678 679 sc->sc_bus.intr_context--; 680 681 if (eintrs != 0) { 682 /* Block unprocessed interrupts. */ 683 sc->sc_eintrs &= ~eintrs; 684 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 685 printf("%s: blocking intrs 0x%x\n", 686 device_xname(sc->sc_dev), eintrs); 687 } 688 689 return (1); 690 } 691 692 Static void 693 ehci_doorbell(void *addr) 694 { 695 ehci_softc_t *sc = addr; 696 697 mutex_enter(&sc->sc_lock); 698 cv_broadcast(&sc->sc_doorbell); 699 mutex_exit(&sc->sc_lock); 700 } 701 702 Static void 703 ehci_pcd(void *addr) 704 { 705 ehci_softc_t *sc = addr; 706 usbd_xfer_handle xfer; 707 usbd_pipe_handle pipe; 708 u_char *p; 709 int i, m; 710 711 mutex_enter(&sc->sc_lock); 712 xfer = sc->sc_intrxfer; 713 714 if (xfer == NULL) { 715 /* Just ignore the change. */ 716 goto done; 717 } 718 719 pipe = xfer->pipe; 720 721 p = KERNADDR(&xfer->dmabuf, 0); 722 m = min(sc->sc_noport, xfer->length * 8 - 1); 723 memset(p, 0, xfer->length); 724 for (i = 1; i <= m; i++) { 725 /* Pick out CHANGE bits from the status reg. */ 726 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 727 p[i/8] |= 1 << (i%8); 728 } 729 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 730 xfer->actlen = xfer->length; 731 xfer->status = USBD_NORMAL_COMPLETION; 732 733 usb_transfer_complete(xfer); 734 735 done: 736 mutex_exit(&sc->sc_lock); 737 } 738 739 Static void 740 ehci_softintr(void *v) 741 { 742 struct usbd_bus *bus = v; 743 ehci_softc_t *sc = bus->hci_private; 744 struct ehci_xfer *ex, *nextex; 745 746 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 747 748 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 749 sc->sc_bus.intr_context)); 750 751 sc->sc_bus.intr_context++; 752 753 /* 754 * The only explanation I can think of for why EHCI is as brain dead 755 * as UHCI interrupt-wise is that Intel was involved in both. 756 * An interrupt just tells us that something is done, we have no 757 * clue what, so we need to scan through all active transfers. :-( 758 */ 759 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 760 nextex = TAILQ_NEXT(ex, inext); 761 ehci_check_intr(sc, ex); 762 } 763 764 /* Schedule a callout to catch any dropped transactions. */ 765 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 766 !TAILQ_EMPTY(&sc->sc_intrhead)) 767 callout_reset(&sc->sc_tmo_intrlist, 768 hz, ehci_intrlist_timeout, sc); 769 770 if (sc->sc_softwake) { 771 sc->sc_softwake = 0; 772 cv_broadcast(&sc->sc_softwake_cv); 773 } 774 775 sc->sc_bus.intr_context--; 776 } 777 778 /* Check for an interrupt. */ 779 Static void 780 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 781 { 782 int attr; 783 784 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 785 786 KASSERT(mutex_owned(&sc->sc_lock)); 787 788 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 789 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 790 ehci_check_itd_intr(sc, ex); 791 else 792 ehci_check_qh_intr(sc, ex); 793 794 return; 795 } 796 797 Static void 798 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 799 { 800 ehci_soft_qtd_t *sqtd, *lsqtd; 801 __uint32_t status; 802 803 KASSERT(mutex_owned(&sc->sc_lock)); 804 805 if (ex->sqtdstart == NULL) { 806 printf("ehci_check_qh_intr: not valid sqtd\n"); 807 return; 808 } 809 810 lsqtd = ex->sqtdend; 811 #ifdef DIAGNOSTIC 812 if (lsqtd == NULL) { 813 printf("ehci_check_qh_intr: lsqtd==0\n"); 814 return; 815 } 816 #endif 817 /* 818 * If the last TD is still active we need to check whether there 819 * is a an error somewhere in the middle, or whether there was a 820 * short packet (SPD and not ACTIVE). 821 */ 822 usb_syncmem(&lsqtd->dma, 823 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 824 sizeof(lsqtd->qtd.qtd_status), 825 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 826 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 827 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 828 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 829 usb_syncmem(&sqtd->dma, 830 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 831 sizeof(sqtd->qtd.qtd_status), 832 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 833 status = le32toh(sqtd->qtd.qtd_status); 834 usb_syncmem(&sqtd->dma, 835 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 836 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 837 /* If there's an active QTD the xfer isn't done. */ 838 if (status & EHCI_QTD_ACTIVE) 839 break; 840 /* Any kind of error makes the xfer done. */ 841 if (status & EHCI_QTD_HALTED) 842 goto done; 843 /* We want short packets, and it is short: it's done */ 844 if (EHCI_QTD_GET_BYTES(status) != 0) 845 goto done; 846 } 847 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 848 ex, ex->sqtdstart)); 849 usb_syncmem(&lsqtd->dma, 850 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 851 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 852 return; 853 } 854 done: 855 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 856 callout_stop(&ex->xfer.timeout_handle); 857 ehci_idone(ex); 858 } 859 860 Static void 861 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 862 ehci_soft_itd_t *itd; 863 int i; 864 865 KASSERT(mutex_owned(&sc->sc_lock)); 866 867 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 868 return; 869 870 if (ex->itdstart == NULL) { 871 printf("ehci_check_itd_intr: not valid itd\n"); 872 return; 873 } 874 875 itd = ex->itdend; 876 #ifdef DIAGNOSTIC 877 if (itd == NULL) { 878 printf("ehci_check_itd_intr: itdend == 0\n"); 879 return; 880 } 881 #endif 882 883 /* 884 * check no active transfers in last itd, meaning we're finished 885 */ 886 887 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 888 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 889 BUS_DMASYNC_POSTREAD); 890 891 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 892 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 893 break; 894 } 895 896 if (i == EHCI_ITD_NUFRAMES) { 897 goto done; /* All 8 descriptors inactive, it's done */ 898 } 899 900 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 901 ex->itdstart)); 902 return; 903 done: 904 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 905 callout_stop(&ex->xfer.timeout_handle); 906 ehci_idone(ex); 907 } 908 909 Static void 910 ehci_idone(struct ehci_xfer *ex) 911 { 912 usbd_xfer_handle xfer = &ex->xfer; 913 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 914 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 915 ehci_soft_qtd_t *sqtd, *lsqtd; 916 u_int32_t status = 0, nstatus = 0; 917 int actlen; 918 919 KASSERT(mutex_owned(&sc->sc_lock)); 920 921 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 922 923 #ifdef DIAGNOSTIC 924 { 925 if (ex->isdone) { 926 #ifdef EHCI_DEBUG 927 printf("ehci_idone: ex is done!\n "); 928 ehci_dump_exfer(ex); 929 #else 930 printf("ehci_idone: ex=%p is done!\n", ex); 931 #endif 932 return; 933 } 934 ex->isdone = 1; 935 } 936 #endif 937 if (xfer->status == USBD_CANCELLED || 938 xfer->status == USBD_TIMEOUT) { 939 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 940 return; 941 } 942 943 #ifdef EHCI_DEBUG 944 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 945 if (ehcidebug > 10) 946 ehci_dump_sqtds(ex->sqtdstart); 947 #endif 948 949 /* The transfer is done, compute actual length and status. */ 950 951 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 952 == UE_ISOCHRONOUS) { 953 /* Isoc transfer */ 954 struct ehci_soft_itd *itd; 955 int i, nframes, len, uframes; 956 957 nframes = 0; 958 actlen = 0; 959 960 i = xfer->pipe->endpoint->edesc->bInterval; 961 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 962 963 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 964 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 965 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 966 BUS_DMASYNC_POSTREAD); 967 968 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 969 /* XXX - driver didn't fill in the frame full 970 * of uframes. This leads to scheduling 971 * inefficiencies, but working around 972 * this doubles complexity of tracking 973 * an xfer. 974 */ 975 if (nframes >= xfer->nframes) 976 break; 977 978 status = le32toh(itd->itd.itd_ctl[i]); 979 len = EHCI_ITD_GET_LEN(status); 980 if (EHCI_ITD_GET_STATUS(status) != 0) 981 len = 0; /*No valid data on error*/ 982 983 xfer->frlengths[nframes++] = len; 984 actlen += len; 985 } 986 987 if (nframes >= xfer->nframes) 988 break; 989 } 990 991 xfer->actlen = actlen; 992 xfer->status = USBD_NORMAL_COMPLETION; 993 goto end; 994 } 995 996 /* Continue processing xfers using queue heads */ 997 998 lsqtd = ex->sqtdend; 999 actlen = 0; 1000 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1001 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1002 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1003 nstatus = le32toh(sqtd->qtd.qtd_status); 1004 if (nstatus & EHCI_QTD_ACTIVE) 1005 break; 1006 1007 status = nstatus; 1008 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1009 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1010 } 1011 1012 1013 /* 1014 * If there are left over TDs we need to update the toggle. 1015 * The default pipe doesn't need it since control transfers 1016 * start the toggle at 0 every time. 1017 * For a short transfer we need to update the toggle for the missing 1018 * packets within the qTD. 1019 */ 1020 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1021 xfer->pipe->device->default_pipe != xfer->pipe) { 1022 DPRINTFN(2, ("ehci_idone: need toggle update " 1023 "status=%08x nstatus=%08x\n", status, nstatus)); 1024 #if 0 1025 ehci_dump_sqh(epipe->sqh); 1026 ehci_dump_sqtds(ex->sqtdstart); 1027 #endif 1028 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1029 } 1030 1031 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 1032 xfer->length, actlen, status)); 1033 xfer->actlen = actlen; 1034 if (status & EHCI_QTD_HALTED) { 1035 #ifdef EHCI_DEBUG 1036 char sbuf[128]; 1037 1038 snprintb(sbuf, sizeof(sbuf), 1039 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 1040 (u_int32_t)status); 1041 1042 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 1043 "status 0x%s\n", 1044 xfer->pipe->device->address, 1045 xfer->pipe->endpoint->edesc->bEndpointAddress, 1046 sbuf)); 1047 if (ehcidebug > 2) { 1048 ehci_dump_sqh(epipe->sqh); 1049 ehci_dump_sqtds(ex->sqtdstart); 1050 } 1051 #endif 1052 /* low&full speed has an extra error flag */ 1053 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1054 EHCI_QH_SPEED_HIGH) 1055 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1056 else 1057 status &= EHCI_QTD_STATERRS; 1058 if (status == 0) /* no other errors means a stall */ { 1059 xfer->status = USBD_STALLED; 1060 } else { 1061 xfer->status = USBD_IOERROR; /* more info XXX */ 1062 } 1063 /* XXX need to reset TT on missed microframe */ 1064 if (status & EHCI_QTD_MISSEDMICRO) { 1065 printf("%s: missed microframe, TT reset not " 1066 "implemented, hub might be inoperational\n", 1067 device_xname(sc->sc_dev)); 1068 } 1069 } else { 1070 xfer->status = USBD_NORMAL_COMPLETION; 1071 } 1072 1073 end: 1074 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1075 * during this call, before methods->done is called: dma sync required 1076 * beforehand? */ 1077 usb_transfer_complete(xfer); 1078 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1079 } 1080 1081 /* 1082 * Wait here until controller claims to have an interrupt. 1083 * Then call ehci_intr and return. Use timeout to avoid waiting 1084 * too long. 1085 */ 1086 Static void 1087 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1088 { 1089 int timo; 1090 u_int32_t intrs; 1091 1092 xfer->status = USBD_IN_PROGRESS; 1093 for (timo = xfer->timeout; timo >= 0; timo--) { 1094 usb_delay_ms(&sc->sc_bus, 1); 1095 if (sc->sc_dying) 1096 break; 1097 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1098 sc->sc_eintrs; 1099 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1100 #ifdef EHCI_DEBUG 1101 if (ehcidebug > 15) 1102 ehci_dump_regs(sc); 1103 #endif 1104 if (intrs) { 1105 mutex_spin_enter(&sc->sc_intr_lock); 1106 ehci_intr1(sc); 1107 mutex_spin_exit(&sc->sc_intr_lock); 1108 if (xfer->status != USBD_IN_PROGRESS) 1109 return; 1110 } 1111 } 1112 1113 /* Timeout */ 1114 DPRINTF(("ehci_waitintr: timeout\n")); 1115 xfer->status = USBD_TIMEOUT; 1116 mutex_enter(&sc->sc_lock); 1117 usb_transfer_complete(xfer); 1118 mutex_exit(&sc->sc_lock); 1119 /* XXX should free TD */ 1120 } 1121 1122 Static void 1123 ehci_poll(struct usbd_bus *bus) 1124 { 1125 ehci_softc_t *sc = bus->hci_private; 1126 #ifdef EHCI_DEBUG 1127 static int last; 1128 int new; 1129 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1130 if (new != last) { 1131 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1132 last = new; 1133 } 1134 #endif 1135 1136 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1137 mutex_spin_enter(&sc->sc_intr_lock); 1138 ehci_intr1(sc); 1139 mutex_spin_exit(&sc->sc_intr_lock); 1140 } 1141 } 1142 1143 void 1144 ehci_childdet(device_t self, device_t child) 1145 { 1146 struct ehci_softc *sc = device_private(self); 1147 1148 KASSERT(sc->sc_child == child); 1149 sc->sc_child = NULL; 1150 } 1151 1152 int 1153 ehci_detach(struct ehci_softc *sc, int flags) 1154 { 1155 usbd_xfer_handle xfer; 1156 int rv = 0; 1157 1158 if (sc->sc_child != NULL) 1159 rv = config_detach(sc->sc_child, flags); 1160 1161 if (rv != 0) 1162 return (rv); 1163 1164 callout_halt(&sc->sc_tmo_intrlist, NULL); 1165 callout_destroy(&sc->sc_tmo_intrlist); 1166 1167 /* XXX free other data structures XXX */ 1168 if (sc->sc_softitds) 1169 kmem_free(sc->sc_softitds, 1170 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1171 cv_destroy(&sc->sc_doorbell); 1172 cv_destroy(&sc->sc_softwake_cv); 1173 1174 softint_disestablish(sc->sc_doorbell_si); 1175 softint_disestablish(sc->sc_pcd_si); 1176 1177 while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 1178 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1179 kmem_free(xfer, sizeof(struct ehci_xfer)); 1180 } 1181 1182 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1183 1184 return (rv); 1185 } 1186 1187 1188 int 1189 ehci_activate(device_t self, enum devact act) 1190 { 1191 struct ehci_softc *sc = device_private(self); 1192 1193 switch (act) { 1194 case DVACT_DEACTIVATE: 1195 sc->sc_dying = 1; 1196 return 0; 1197 default: 1198 return EOPNOTSUPP; 1199 } 1200 } 1201 1202 /* 1203 * Handle suspend/resume. 1204 * 1205 * We need to switch to polling mode here, because this routine is 1206 * called from an interrupt context. This is all right since we 1207 * are almost suspended anyway. 1208 * 1209 * Note that this power handler isn't to be registered directly; the 1210 * bus glue needs to call out to it. 1211 */ 1212 bool 1213 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1214 { 1215 ehci_softc_t *sc = device_private(dv); 1216 int i; 1217 uint32_t cmd, hcr; 1218 1219 mutex_spin_enter(&sc->sc_intr_lock); 1220 sc->sc_bus.use_polling++; 1221 mutex_spin_exit(&sc->sc_intr_lock); 1222 1223 for (i = 1; i <= sc->sc_noport; i++) { 1224 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1225 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1226 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1227 } 1228 1229 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1230 1231 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1232 EOWRITE4(sc, EHCI_USBCMD, cmd); 1233 1234 for (i = 0; i < 100; i++) { 1235 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1236 if (hcr == 0) 1237 break; 1238 1239 usb_delay_ms(&sc->sc_bus, 1); 1240 } 1241 if (hcr != 0) 1242 printf("%s: reset timeout\n", device_xname(dv)); 1243 1244 cmd &= ~EHCI_CMD_RS; 1245 EOWRITE4(sc, EHCI_USBCMD, cmd); 1246 1247 for (i = 0; i < 100; i++) { 1248 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1249 if (hcr == EHCI_STS_HCH) 1250 break; 1251 1252 usb_delay_ms(&sc->sc_bus, 1); 1253 } 1254 if (hcr != EHCI_STS_HCH) 1255 printf("%s: config timeout\n", device_xname(dv)); 1256 1257 mutex_spin_enter(&sc->sc_intr_lock); 1258 sc->sc_bus.use_polling--; 1259 mutex_spin_exit(&sc->sc_intr_lock); 1260 1261 return true; 1262 } 1263 1264 bool 1265 ehci_resume(device_t dv, const pmf_qual_t *qual) 1266 { 1267 ehci_softc_t *sc = device_private(dv); 1268 int i; 1269 uint32_t cmd, hcr; 1270 1271 /* restore things in case the bios sucks */ 1272 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1273 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1274 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1275 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1276 1277 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1278 1279 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1280 1281 hcr = 0; 1282 for (i = 1; i <= sc->sc_noport; i++) { 1283 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1284 if ((cmd & EHCI_PS_PO) == 0 && 1285 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1286 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1287 hcr = 1; 1288 } 1289 } 1290 1291 if (hcr) { 1292 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1293 1294 for (i = 1; i <= sc->sc_noport; i++) { 1295 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1296 if ((cmd & EHCI_PS_PO) == 0 && 1297 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1298 EOWRITE4(sc, EHCI_PORTSC(i), 1299 cmd & ~EHCI_PS_FPR); 1300 } 1301 } 1302 1303 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1304 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1305 1306 for (i = 0; i < 100; i++) { 1307 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1308 if (hcr != EHCI_STS_HCH) 1309 break; 1310 1311 usb_delay_ms(&sc->sc_bus, 1); 1312 } 1313 if (hcr == EHCI_STS_HCH) 1314 printf("%s: config timeout\n", device_xname(dv)); 1315 1316 return true; 1317 } 1318 1319 /* 1320 * Shut down the controller when the system is going down. 1321 */ 1322 bool 1323 ehci_shutdown(device_t self, int flags) 1324 { 1325 ehci_softc_t *sc = device_private(self); 1326 1327 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1328 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1329 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1330 return true; 1331 } 1332 1333 Static usbd_status 1334 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1335 { 1336 struct ehci_softc *sc = bus->hci_private; 1337 usbd_status err; 1338 1339 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1340 if (err == USBD_NOMEM) 1341 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1342 #ifdef EHCI_DEBUG 1343 if (err) 1344 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1345 #endif 1346 return (err); 1347 } 1348 1349 Static void 1350 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1351 { 1352 struct ehci_softc *sc = bus->hci_private; 1353 1354 if (dma->block->flags & USB_DMA_RESERVE) { 1355 usb_reserve_freem(&sc->sc_dma_reserve, 1356 dma); 1357 return; 1358 } 1359 usb_freemem(&sc->sc_bus, dma); 1360 } 1361 1362 Static usbd_xfer_handle 1363 ehci_allocx(struct usbd_bus *bus) 1364 { 1365 struct ehci_softc *sc = bus->hci_private; 1366 usbd_xfer_handle xfer; 1367 1368 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1369 if (xfer != NULL) { 1370 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1371 #ifdef DIAGNOSTIC 1372 if (xfer->busy_free != XFER_FREE) { 1373 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1374 xfer->busy_free); 1375 } 1376 #endif 1377 } else { 1378 xfer = kmem_alloc(sizeof(struct ehci_xfer), KM_SLEEP); 1379 } 1380 if (xfer != NULL) { 1381 memset(xfer, 0, sizeof(struct ehci_xfer)); 1382 #ifdef DIAGNOSTIC 1383 EXFER(xfer)->isdone = 1; 1384 xfer->busy_free = XFER_BUSY; 1385 #endif 1386 } 1387 return (xfer); 1388 } 1389 1390 Static void 1391 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1392 { 1393 struct ehci_softc *sc = bus->hci_private; 1394 1395 #ifdef DIAGNOSTIC 1396 if (xfer->busy_free != XFER_BUSY) { 1397 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1398 xfer->busy_free); 1399 } 1400 xfer->busy_free = XFER_FREE; 1401 if (!EXFER(xfer)->isdone) { 1402 printf("ehci_freex: !isdone\n"); 1403 } 1404 #endif 1405 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1406 } 1407 1408 Static void 1409 ehci_get_lock(struct usbd_bus *bus, kmutex_t **thread) 1410 { 1411 struct ehci_softc *sc = bus->hci_private; 1412 1413 *thread = &sc->sc_lock; 1414 } 1415 1416 Static void 1417 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1418 { 1419 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1420 1421 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1422 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1423 #ifdef EHCI_DEBUG 1424 if (ehcidebug) 1425 usbd_dump_pipe(pipe); 1426 #endif 1427 epipe->nexttoggle = 0; 1428 } 1429 1430 Static void 1431 ehci_noop(usbd_pipe_handle pipe) 1432 { 1433 } 1434 1435 #ifdef EHCI_DEBUG 1436 Static void 1437 ehci_dump_regs(ehci_softc_t *sc) 1438 { 1439 int i; 1440 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1441 EOREAD4(sc, EHCI_USBCMD), 1442 EOREAD4(sc, EHCI_USBSTS), 1443 EOREAD4(sc, EHCI_USBINTR)); 1444 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1445 EOREAD4(sc, EHCI_FRINDEX), 1446 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1447 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1448 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1449 for (i = 1; i <= sc->sc_noport; i++) 1450 printf("port %d status=0x%08x\n", i, 1451 EOREAD4(sc, EHCI_PORTSC(i))); 1452 } 1453 1454 /* 1455 * Unused function - this is meant to be called from a kernel 1456 * debugger. 1457 */ 1458 void 1459 ehci_dump(void) 1460 { 1461 ehci_dump_regs(theehci); 1462 } 1463 1464 Static void 1465 ehci_dump_link(ehci_link_t link, int type) 1466 { 1467 link = le32toh(link); 1468 printf("0x%08x", link); 1469 if (link & EHCI_LINK_TERMINATE) 1470 printf("<T>"); 1471 else { 1472 printf("<"); 1473 if (type) { 1474 switch (EHCI_LINK_TYPE(link)) { 1475 case EHCI_LINK_ITD: printf("ITD"); break; 1476 case EHCI_LINK_QH: printf("QH"); break; 1477 case EHCI_LINK_SITD: printf("SITD"); break; 1478 case EHCI_LINK_FSTN: printf("FSTN"); break; 1479 } 1480 } 1481 printf(">"); 1482 } 1483 } 1484 1485 Static void 1486 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1487 { 1488 int i; 1489 u_int32_t stop; 1490 1491 stop = 0; 1492 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1493 ehci_dump_sqtd(sqtd); 1494 usb_syncmem(&sqtd->dma, 1495 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1496 sizeof(sqtd->qtd), 1497 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1498 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1499 usb_syncmem(&sqtd->dma, 1500 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1501 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1502 } 1503 if (sqtd) 1504 printf("dump aborted, too many TDs\n"); 1505 } 1506 1507 Static void 1508 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1509 { 1510 usb_syncmem(&sqtd->dma, sqtd->offs, 1511 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1512 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1513 ehci_dump_qtd(&sqtd->qtd); 1514 usb_syncmem(&sqtd->dma, sqtd->offs, 1515 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1516 } 1517 1518 Static void 1519 ehci_dump_qtd(ehci_qtd_t *qtd) 1520 { 1521 u_int32_t s; 1522 char sbuf[128]; 1523 1524 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1525 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1526 printf("\n"); 1527 s = le32toh(qtd->qtd_status); 1528 snprintb(sbuf, sizeof(sbuf), 1529 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1530 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1531 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1532 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1533 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1534 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1535 EHCI_QTD_GET_PID(s), sbuf); 1536 for (s = 0; s < 5; s++) 1537 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1538 } 1539 1540 Static void 1541 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1542 { 1543 ehci_qh_t *qh = &sqh->qh; 1544 u_int32_t endp, endphub; 1545 1546 usb_syncmem(&sqh->dma, sqh->offs, 1547 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1548 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1549 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1550 endp = le32toh(qh->qh_endp); 1551 printf(" endp=0x%08x\n", endp); 1552 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1553 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1554 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1555 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1556 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1557 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1558 EHCI_QH_GET_NRL(endp)); 1559 endphub = le32toh(qh->qh_endphub); 1560 printf(" endphub=0x%08x\n", endphub); 1561 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1562 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1563 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1564 EHCI_QH_GET_MULT(endphub)); 1565 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1566 printf("Overlay qTD:\n"); 1567 ehci_dump_qtd(&qh->qh_qtd); 1568 usb_syncmem(&sqh->dma, sqh->offs, 1569 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1570 } 1571 1572 #if notyet 1573 Static void 1574 ehci_dump_itd(struct ehci_soft_itd *itd) 1575 { 1576 ehci_isoc_trans_t t; 1577 ehci_isoc_bufr_ptr_t b, b2, b3; 1578 int i; 1579 1580 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1581 1582 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1583 t = le32toh(itd->itd.itd_ctl[i]); 1584 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1585 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1586 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1587 EHCI_ITD_GET_OFFS(t)); 1588 } 1589 printf("ITDbufr: "); 1590 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1591 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1592 1593 b = le32toh(itd->itd.itd_bufr[0]); 1594 b2 = le32toh(itd->itd.itd_bufr[1]); 1595 b3 = le32toh(itd->itd.itd_bufr[2]); 1596 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1597 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1598 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1599 } 1600 1601 Static void 1602 ehci_dump_sitd(struct ehci_soft_itd *itd) 1603 { 1604 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1605 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1606 itd->xfer_next, itd->physaddr, itd->slot); 1607 } 1608 #endif 1609 1610 #ifdef DIAGNOSTIC 1611 Static void 1612 ehci_dump_exfer(struct ehci_xfer *ex) 1613 { 1614 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1615 } 1616 #endif 1617 #endif 1618 1619 Static usbd_status 1620 ehci_open(usbd_pipe_handle pipe) 1621 { 1622 usbd_device_handle dev = pipe->device; 1623 ehci_softc_t *sc = dev->bus->hci_private; 1624 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1625 u_int8_t addr = dev->address; 1626 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1627 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1628 ehci_soft_qh_t *sqh; 1629 usbd_status err; 1630 int ival, speed, naks; 1631 int hshubaddr, hshubport; 1632 1633 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1634 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1635 1636 if (dev->myhsport) { 1637 /* 1638 * When directly attached FS/LS device while doing embedded 1639 * transaction translations and we are the hub, set the hub 1640 * adddress to 0 (us). 1641 */ 1642 if (!(sc->sc_flags & EHCIF_ETTF) 1643 || (dev->myhsport->parent->address != sc->sc_addr)) { 1644 hshubaddr = dev->myhsport->parent->address; 1645 } else { 1646 hshubaddr = 0; 1647 } 1648 hshubport = dev->myhsport->portno; 1649 } else { 1650 hshubaddr = 0; 1651 hshubport = 0; 1652 } 1653 1654 if (sc->sc_dying) 1655 return (USBD_IOERROR); 1656 1657 /* toggle state needed for bulk endpoints */ 1658 epipe->nexttoggle = pipe->endpoint->datatoggle; 1659 1660 if (addr == sc->sc_addr) { 1661 switch (ed->bEndpointAddress) { 1662 case USB_CONTROL_ENDPOINT: 1663 pipe->methods = &ehci_root_ctrl_methods; 1664 break; 1665 case UE_DIR_IN | EHCI_INTR_ENDPT: 1666 pipe->methods = &ehci_root_intr_methods; 1667 break; 1668 default: 1669 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1670 ed->bEndpointAddress)); 1671 return (USBD_INVAL); 1672 } 1673 return (USBD_NORMAL_COMPLETION); 1674 } 1675 1676 /* XXX All this stuff is only valid for async. */ 1677 switch (dev->speed) { 1678 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1679 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1680 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1681 default: panic("ehci_open: bad device speed %d", dev->speed); 1682 } 1683 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1684 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1685 "isoc endpoint.\n"); 1686 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1687 "attached to a USB2 hub, and transaction translations are " 1688 "not yet supported.\n"); 1689 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1690 "root hub instead.\n"); 1691 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1692 hshubaddr, hshubport)); 1693 return USBD_INVAL; 1694 } 1695 1696 /* 1697 * For interrupt transfer, nak throttling must be disabled, but for 1698 * the other transfer type, nak throttling should be enabled from the 1699 * veiwpoint that avoids the memory thrashing. 1700 */ 1701 naks = (xfertype == UE_INTERRUPT) ? 0 1702 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1703 1704 /* Allocate sqh for everything, save isoc xfers */ 1705 if (xfertype != UE_ISOCHRONOUS) { 1706 sqh = ehci_alloc_sqh(sc); 1707 if (sqh == NULL) 1708 return (USBD_NOMEM); 1709 /* qh_link filled when the QH is added */ 1710 sqh->qh.qh_endp = htole32( 1711 EHCI_QH_SET_ADDR(addr) | 1712 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1713 EHCI_QH_SET_EPS(speed) | 1714 EHCI_QH_DTC | 1715 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1716 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1717 EHCI_QH_CTL : 0) | 1718 EHCI_QH_SET_NRL(naks) 1719 ); 1720 sqh->qh.qh_endphub = htole32( 1721 EHCI_QH_SET_MULT(1) | 1722 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1723 ); 1724 if (speed != EHCI_QH_SPEED_HIGH) 1725 sqh->qh.qh_endphub |= htole32( 1726 EHCI_QH_SET_PORT(hshubport) | 1727 EHCI_QH_SET_HUBA(hshubaddr) | 1728 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1729 ); 1730 sqh->qh.qh_curqtd = EHCI_NULL; 1731 /* Fill the overlay qTD */ 1732 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1733 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1734 sqh->qh.qh_qtd.qtd_status = htole32(0); 1735 1736 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1737 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1738 epipe->sqh = sqh; 1739 } else { 1740 sqh = NULL; 1741 } /*xfertype == UE_ISOC*/ 1742 1743 switch (xfertype) { 1744 case UE_CONTROL: 1745 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1746 0, &epipe->u.ctl.reqdma); 1747 #ifdef EHCI_DEBUG 1748 if (err) 1749 printf("ehci_open: usb_allocmem()=%d\n", err); 1750 #endif 1751 if (err) 1752 goto bad; 1753 pipe->methods = &ehci_device_ctrl_methods; 1754 mutex_enter(&sc->sc_lock); 1755 ehci_add_qh(sc, sqh, sc->sc_async_head); 1756 mutex_exit(&sc->sc_lock); 1757 break; 1758 case UE_BULK: 1759 pipe->methods = &ehci_device_bulk_methods; 1760 mutex_enter(&sc->sc_lock); 1761 ehci_add_qh(sc, sqh, sc->sc_async_head); 1762 mutex_exit(&sc->sc_lock); 1763 break; 1764 case UE_INTERRUPT: 1765 pipe->methods = &ehci_device_intr_methods; 1766 ival = pipe->interval; 1767 if (ival == USBD_DEFAULT_INTERVAL) { 1768 if (speed == EHCI_QH_SPEED_HIGH) { 1769 if (ed->bInterval > 16) { 1770 /* 1771 * illegal with high-speed, but there 1772 * were documentation bugs in the spec, 1773 * so be generous 1774 */ 1775 ival = 256; 1776 } else 1777 ival = (1 << (ed->bInterval - 1)) / 8; 1778 } else 1779 ival = ed->bInterval; 1780 } 1781 err = ehci_device_setintr(sc, sqh, ival); 1782 if (err) 1783 goto bad; 1784 break; 1785 case UE_ISOCHRONOUS: 1786 pipe->methods = &ehci_device_isoc_methods; 1787 if (ed->bInterval == 0 || ed->bInterval > 16) { 1788 printf("ehci: opening pipe with invalid bInterval\n"); 1789 err = USBD_INVAL; 1790 goto bad; 1791 } 1792 if (UGETW(ed->wMaxPacketSize) == 0) { 1793 printf("ehci: zero length endpoint open request\n"); 1794 err = USBD_INVAL; 1795 goto bad; 1796 } 1797 epipe->u.isoc.next_frame = 0; 1798 epipe->u.isoc.cur_xfers = 0; 1799 break; 1800 default: 1801 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1802 err = USBD_INVAL; 1803 goto bad; 1804 } 1805 return (USBD_NORMAL_COMPLETION); 1806 1807 bad: 1808 if (sqh != NULL) 1809 ehci_free_sqh(sc, sqh); 1810 return (err); 1811 } 1812 1813 /* 1814 * Add an ED to the schedule. Called with USB thread lock held. 1815 */ 1816 Static void 1817 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1818 { 1819 1820 KASSERT(mutex_owned(&sc->sc_lock)); 1821 1822 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1823 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1824 sqh->next = head->next; 1825 sqh->qh.qh_link = head->qh.qh_link; 1826 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1827 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1828 head->next = sqh; 1829 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1830 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1831 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1832 1833 #ifdef EHCI_DEBUG 1834 if (ehcidebug > 5) { 1835 printf("ehci_add_qh:\n"); 1836 ehci_dump_sqh(sqh); 1837 } 1838 #endif 1839 } 1840 1841 /* 1842 * Remove an ED from the schedule. Called with USB thread lock held. 1843 */ 1844 Static void 1845 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1846 { 1847 ehci_soft_qh_t *p; 1848 1849 KASSERT(mutex_owned(&sc->sc_lock)); 1850 1851 /* XXX */ 1852 for (p = head; p != NULL && p->next != sqh; p = p->next) 1853 ; 1854 if (p == NULL) 1855 panic("ehci_rem_qh: ED not found"); 1856 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1857 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1858 p->next = sqh->next; 1859 p->qh.qh_link = sqh->qh.qh_link; 1860 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1861 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1862 1863 ehci_sync_hc(sc); 1864 } 1865 1866 Static void 1867 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1868 { 1869 int i; 1870 u_int32_t status; 1871 1872 /* Save toggle bit and ping status. */ 1873 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1874 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1875 status = sqh->qh.qh_qtd.qtd_status & 1876 htole32(EHCI_QTD_TOGGLE_MASK | 1877 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1878 /* Set HALTED to make hw leave it alone. */ 1879 sqh->qh.qh_qtd.qtd_status = 1880 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1881 usb_syncmem(&sqh->dma, 1882 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1883 sizeof(sqh->qh.qh_qtd.qtd_status), 1884 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1885 sqh->qh.qh_curqtd = 0; 1886 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1887 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1888 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1889 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1890 sqh->sqtd = sqtd; 1891 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1892 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1893 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1894 sqh->qh.qh_qtd.qtd_status = status; 1895 usb_syncmem(&sqh->dma, 1896 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1897 sizeof(sqh->qh.qh_qtd.qtd_status), 1898 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1899 } 1900 1901 /* 1902 * Ensure that the HC has released all references to the QH. We do this 1903 * by asking for a Async Advance Doorbell interrupt and then we wait for 1904 * the interrupt. 1905 * To make this easier we first obtain exclusive use of the doorbell. 1906 */ 1907 Static void 1908 ehci_sync_hc(ehci_softc_t *sc) 1909 { 1910 int error; 1911 1912 KASSERT(mutex_owned(&sc->sc_lock)); 1913 1914 if (sc->sc_dying) { 1915 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1916 return; 1917 } 1918 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1919 /* ask for doorbell */ 1920 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1921 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1922 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1923 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 1924 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1925 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1926 #ifdef DIAGNOSTIC 1927 if (error) 1928 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 1929 #endif 1930 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1931 } 1932 1933 Static void 1934 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1935 { 1936 struct ehci_soft_itd *itd, *prev; 1937 1938 prev = NULL; 1939 1940 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1941 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1942 1943 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1944 prev = itd->u.frame_list.prev; 1945 /* Unlink itd from hardware chain, or frame array */ 1946 if (prev == NULL) { /* We're at the table head */ 1947 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1948 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1949 usb_syncmem(&sc->sc_fldma, 1950 sizeof(ehci_link_t) * itd->slot, 1951 sizeof(ehci_link_t), 1952 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1953 1954 if (itd->u.frame_list.next != NULL) 1955 itd->u.frame_list.next->u.frame_list.prev = NULL; 1956 } else { 1957 /* XXX this part is untested... */ 1958 prev->itd.itd_next = itd->itd.itd_next; 1959 usb_syncmem(&itd->dma, 1960 itd->offs + offsetof(ehci_itd_t, itd_next), 1961 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1962 1963 prev->u.frame_list.next = itd->u.frame_list.next; 1964 if (itd->u.frame_list.next != NULL) 1965 itd->u.frame_list.next->u.frame_list.prev = prev; 1966 } 1967 } 1968 1969 prev = NULL; 1970 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1971 if (prev != NULL) 1972 ehci_free_itd(sc, prev); 1973 prev = itd; 1974 } 1975 if (prev) 1976 ehci_free_itd(sc, prev); 1977 exfer->itdstart = NULL; 1978 exfer->itdend = NULL; 1979 } 1980 1981 /***********/ 1982 1983 /* 1984 * Data structures and routines to emulate the root hub. 1985 */ 1986 Static usb_device_descriptor_t ehci_devd = { 1987 USB_DEVICE_DESCRIPTOR_SIZE, 1988 UDESC_DEVICE, /* type */ 1989 {0x00, 0x02}, /* USB version */ 1990 UDCLASS_HUB, /* class */ 1991 UDSUBCLASS_HUB, /* subclass */ 1992 UDPROTO_HSHUBSTT, /* protocol */ 1993 64, /* max packet */ 1994 {0},{0},{0x00,0x01}, /* device id */ 1995 1,2,0, /* string indicies */ 1996 1 /* # of configurations */ 1997 }; 1998 1999 Static const usb_device_qualifier_t ehci_odevd = { 2000 USB_DEVICE_DESCRIPTOR_SIZE, 2001 UDESC_DEVICE_QUALIFIER, /* type */ 2002 {0x00, 0x02}, /* USB version */ 2003 UDCLASS_HUB, /* class */ 2004 UDSUBCLASS_HUB, /* subclass */ 2005 UDPROTO_FSHUB, /* protocol */ 2006 64, /* max packet */ 2007 1, /* # of configurations */ 2008 0 2009 }; 2010 2011 Static const usb_config_descriptor_t ehci_confd = { 2012 USB_CONFIG_DESCRIPTOR_SIZE, 2013 UDESC_CONFIG, 2014 {USB_CONFIG_DESCRIPTOR_SIZE + 2015 USB_INTERFACE_DESCRIPTOR_SIZE + 2016 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2017 1, 2018 1, 2019 0, 2020 UC_ATTR_MBO | UC_SELF_POWERED, 2021 0 /* max power */ 2022 }; 2023 2024 Static const usb_interface_descriptor_t ehci_ifcd = { 2025 USB_INTERFACE_DESCRIPTOR_SIZE, 2026 UDESC_INTERFACE, 2027 0, 2028 0, 2029 1, 2030 UICLASS_HUB, 2031 UISUBCLASS_HUB, 2032 UIPROTO_HSHUBSTT, 2033 0 2034 }; 2035 2036 Static const usb_endpoint_descriptor_t ehci_endpd = { 2037 USB_ENDPOINT_DESCRIPTOR_SIZE, 2038 UDESC_ENDPOINT, 2039 UE_DIR_IN | EHCI_INTR_ENDPT, 2040 UE_INTERRUPT, 2041 {8, 0}, /* max packet */ 2042 12 2043 }; 2044 2045 Static const usb_hub_descriptor_t ehci_hubd = { 2046 USB_HUB_DESCRIPTOR_SIZE, 2047 UDESC_HUB, 2048 0, 2049 {0,0}, 2050 0, 2051 0, 2052 {""}, 2053 {""}, 2054 }; 2055 2056 /* 2057 * Simulate a hardware hub by handling all the necessary requests. 2058 */ 2059 Static usbd_status 2060 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2061 { 2062 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2063 usbd_status err; 2064 2065 /* Insert last in queue. */ 2066 mutex_enter(&sc->sc_lock); 2067 err = usb_insert_transfer(xfer); 2068 mutex_exit(&sc->sc_lock); 2069 if (err) 2070 return (err); 2071 2072 /* Pipe isn't running, start first */ 2073 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2074 } 2075 2076 Static usbd_status 2077 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2078 { 2079 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2080 usb_device_request_t *req; 2081 void *buf = NULL; 2082 int port, i; 2083 int len, value, index, l, totlen = 0; 2084 usb_port_status_t ps; 2085 usb_hub_descriptor_t hubd; 2086 usbd_status err; 2087 u_int32_t v; 2088 2089 if (sc->sc_dying) 2090 return (USBD_IOERROR); 2091 2092 #ifdef DIAGNOSTIC 2093 if (!(xfer->rqflags & URQ_REQUEST)) 2094 /* XXX panic */ 2095 return (USBD_INVAL); 2096 #endif 2097 req = &xfer->request; 2098 2099 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2100 req->bmRequestType, req->bRequest)); 2101 2102 len = UGETW(req->wLength); 2103 value = UGETW(req->wValue); 2104 index = UGETW(req->wIndex); 2105 2106 if (len != 0) 2107 buf = KERNADDR(&xfer->dmabuf, 0); 2108 2109 #define C(x,y) ((x) | ((y) << 8)) 2110 switch(C(req->bRequest, req->bmRequestType)) { 2111 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2112 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2113 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2114 /* 2115 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2116 * for the integrated root hub. 2117 */ 2118 break; 2119 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2120 if (len > 0) { 2121 *(u_int8_t *)buf = sc->sc_conf; 2122 totlen = 1; 2123 } 2124 break; 2125 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2126 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2127 if (len == 0) 2128 break; 2129 switch(value >> 8) { 2130 case UDESC_DEVICE: 2131 if ((value & 0xff) != 0) { 2132 err = USBD_IOERROR; 2133 goto ret; 2134 } 2135 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2136 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2137 memcpy(buf, &ehci_devd, l); 2138 break; 2139 /* 2140 * We can't really operate at another speed, but the spec says 2141 * we need this descriptor. 2142 */ 2143 case UDESC_DEVICE_QUALIFIER: 2144 if ((value & 0xff) != 0) { 2145 err = USBD_IOERROR; 2146 goto ret; 2147 } 2148 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2149 memcpy(buf, &ehci_odevd, l); 2150 break; 2151 /* 2152 * We can't really operate at another speed, but the spec says 2153 * we need this descriptor. 2154 */ 2155 case UDESC_OTHER_SPEED_CONFIGURATION: 2156 case UDESC_CONFIG: 2157 if ((value & 0xff) != 0) { 2158 err = USBD_IOERROR; 2159 goto ret; 2160 } 2161 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2162 memcpy(buf, &ehci_confd, l); 2163 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2164 value >> 8; 2165 buf = (char *)buf + l; 2166 len -= l; 2167 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2168 totlen += l; 2169 memcpy(buf, &ehci_ifcd, l); 2170 buf = (char *)buf + l; 2171 len -= l; 2172 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2173 totlen += l; 2174 memcpy(buf, &ehci_endpd, l); 2175 break; 2176 case UDESC_STRING: 2177 #define sd ((usb_string_descriptor_t *)buf) 2178 switch (value & 0xff) { 2179 case 0: /* Language table */ 2180 totlen = usb_makelangtbl(sd, len); 2181 break; 2182 case 1: /* Vendor */ 2183 totlen = usb_makestrdesc(sd, len, 2184 sc->sc_vendor); 2185 break; 2186 case 2: /* Product */ 2187 totlen = usb_makestrdesc(sd, len, 2188 "EHCI root hub"); 2189 break; 2190 } 2191 #undef sd 2192 break; 2193 default: 2194 err = USBD_IOERROR; 2195 goto ret; 2196 } 2197 break; 2198 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2199 if (len > 0) { 2200 *(u_int8_t *)buf = 0; 2201 totlen = 1; 2202 } 2203 break; 2204 case C(UR_GET_STATUS, UT_READ_DEVICE): 2205 if (len > 1) { 2206 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2207 totlen = 2; 2208 } 2209 break; 2210 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2211 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2212 if (len > 1) { 2213 USETW(((usb_status_t *)buf)->wStatus, 0); 2214 totlen = 2; 2215 } 2216 break; 2217 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2218 if (value >= USB_MAX_DEVICES) { 2219 err = USBD_IOERROR; 2220 goto ret; 2221 } 2222 sc->sc_addr = value; 2223 break; 2224 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2225 if (value != 0 && value != 1) { 2226 err = USBD_IOERROR; 2227 goto ret; 2228 } 2229 sc->sc_conf = value; 2230 break; 2231 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2232 break; 2233 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2234 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2235 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2236 err = USBD_IOERROR; 2237 goto ret; 2238 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2239 break; 2240 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2241 break; 2242 /* Hub requests */ 2243 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2244 break; 2245 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2246 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2247 "port=%d feature=%d\n", 2248 index, value)); 2249 if (index < 1 || index > sc->sc_noport) { 2250 err = USBD_IOERROR; 2251 goto ret; 2252 } 2253 port = EHCI_PORTSC(index); 2254 v = EOREAD4(sc, port); 2255 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2256 v &= ~EHCI_PS_CLEAR; 2257 switch(value) { 2258 case UHF_PORT_ENABLE: 2259 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2260 break; 2261 case UHF_PORT_SUSPEND: 2262 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2263 break; 2264 v &= ~EHCI_PS_SUSP; 2265 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2266 /* see USB2 spec ch. 7.1.7.7 */ 2267 usb_delay_ms(&sc->sc_bus, 20); 2268 EOWRITE4(sc, port, v); 2269 usb_delay_ms(&sc->sc_bus, 2); 2270 #ifdef DEBUG 2271 v = EOREAD4(sc, port); 2272 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2273 printf("ehci: resume failed: %x\n", v); 2274 #endif 2275 break; 2276 case UHF_PORT_POWER: 2277 if (sc->sc_hasppc) 2278 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2279 break; 2280 case UHF_PORT_TEST: 2281 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2282 "%d\n", index)); 2283 break; 2284 case UHF_PORT_INDICATOR: 2285 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2286 "%d\n", index)); 2287 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2288 break; 2289 case UHF_C_PORT_CONNECTION: 2290 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2291 break; 2292 case UHF_C_PORT_ENABLE: 2293 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2294 break; 2295 case UHF_C_PORT_SUSPEND: 2296 /* how? */ 2297 break; 2298 case UHF_C_PORT_OVER_CURRENT: 2299 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2300 break; 2301 case UHF_C_PORT_RESET: 2302 sc->sc_isreset[index] = 0; 2303 break; 2304 default: 2305 err = USBD_IOERROR; 2306 goto ret; 2307 } 2308 #if 0 2309 switch(value) { 2310 case UHF_C_PORT_CONNECTION: 2311 case UHF_C_PORT_ENABLE: 2312 case UHF_C_PORT_SUSPEND: 2313 case UHF_C_PORT_OVER_CURRENT: 2314 case UHF_C_PORT_RESET: 2315 default: 2316 break; 2317 } 2318 #endif 2319 break; 2320 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2321 if (len == 0) 2322 break; 2323 if ((value & 0xff) != 0) { 2324 err = USBD_IOERROR; 2325 goto ret; 2326 } 2327 hubd = ehci_hubd; 2328 hubd.bNbrPorts = sc->sc_noport; 2329 v = EOREAD4(sc, EHCI_HCSPARAMS); 2330 USETW(hubd.wHubCharacteristics, 2331 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2332 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2333 ? UHD_PORT_IND : 0); 2334 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2335 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2336 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2337 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2338 l = min(len, hubd.bDescLength); 2339 totlen = l; 2340 memcpy(buf, &hubd, l); 2341 break; 2342 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2343 if (len != 4) { 2344 err = USBD_IOERROR; 2345 goto ret; 2346 } 2347 memset(buf, 0, len); /* ? XXX */ 2348 totlen = len; 2349 break; 2350 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2351 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2352 index)); 2353 if (index < 1 || index > sc->sc_noport) { 2354 err = USBD_IOERROR; 2355 goto ret; 2356 } 2357 if (len != 4) { 2358 err = USBD_IOERROR; 2359 goto ret; 2360 } 2361 v = EOREAD4(sc, EHCI_PORTSC(index)); 2362 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2363 2364 i = UPS_HIGH_SPEED; 2365 #if 0 2366 if (sc->sc_flags & EHCIF_ETTF) { 2367 /* 2368 * If we are doing embedded transaction translation, 2369 * then directly attached LS/FS devices are reset by 2370 * the EHCI controller itself. PSPD is encoded 2371 * the same way as in USBSTATUS. 2372 */ 2373 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2374 } 2375 #endif 2376 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2377 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2378 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2379 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2380 if (v & EHCI_PS_PR) i |= UPS_RESET; 2381 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2382 if (sc->sc_vendor_port_status) 2383 i = sc->sc_vendor_port_status(sc, v, i); 2384 USETW(ps.wPortStatus, i); 2385 i = 0; 2386 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2387 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2388 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2389 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2390 USETW(ps.wPortChange, i); 2391 l = min(len, sizeof ps); 2392 memcpy(buf, &ps, l); 2393 totlen = l; 2394 break; 2395 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2396 err = USBD_IOERROR; 2397 goto ret; 2398 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2399 break; 2400 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2401 if (index < 1 || index > sc->sc_noport) { 2402 err = USBD_IOERROR; 2403 goto ret; 2404 } 2405 port = EHCI_PORTSC(index); 2406 v = EOREAD4(sc, port); 2407 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2408 v &= ~EHCI_PS_CLEAR; 2409 switch(value) { 2410 case UHF_PORT_ENABLE: 2411 EOWRITE4(sc, port, v | EHCI_PS_PE); 2412 break; 2413 case UHF_PORT_SUSPEND: 2414 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2415 break; 2416 case UHF_PORT_RESET: 2417 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2418 index)); 2419 if (EHCI_PS_IS_LOWSPEED(v) 2420 && sc->sc_ncomp > 0 2421 && !(sc->sc_flags & EHCIF_ETTF)) { 2422 /* 2423 * Low speed device on non-ETTF controller or 2424 * unaccompanied controller, give up ownership. 2425 */ 2426 ehci_disown(sc, index, 1); 2427 break; 2428 } 2429 /* Start reset sequence. */ 2430 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2431 EOWRITE4(sc, port, v | EHCI_PS_PR); 2432 /* Wait for reset to complete. */ 2433 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2434 if (sc->sc_dying) { 2435 err = USBD_IOERROR; 2436 goto ret; 2437 } 2438 /* 2439 * An embedded transaction translater will automatically 2440 * terminate the reset sequence so there's no need to 2441 * it. 2442 */ 2443 v = EOREAD4(sc, port); 2444 if (v & EHCI_PS_PR) { 2445 /* Terminate reset sequence. */ 2446 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2447 /* Wait for HC to complete reset. */ 2448 usb_delay_ms(&sc->sc_bus, 2449 EHCI_PORT_RESET_COMPLETE); 2450 if (sc->sc_dying) { 2451 err = USBD_IOERROR; 2452 goto ret; 2453 } 2454 } 2455 2456 v = EOREAD4(sc, port); 2457 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2458 if (v & EHCI_PS_PR) { 2459 printf("%s: port reset timeout\n", 2460 device_xname(sc->sc_dev)); 2461 return (USBD_TIMEOUT); 2462 } 2463 if (!(v & EHCI_PS_PE)) { 2464 /* Not a high speed device, give up ownership.*/ 2465 ehci_disown(sc, index, 0); 2466 break; 2467 } 2468 sc->sc_isreset[index] = 1; 2469 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2470 index, v)); 2471 break; 2472 case UHF_PORT_POWER: 2473 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2474 "%d (has PPC = %d)\n", index, 2475 sc->sc_hasppc)); 2476 if (sc->sc_hasppc) 2477 EOWRITE4(sc, port, v | EHCI_PS_PP); 2478 break; 2479 case UHF_PORT_TEST: 2480 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2481 "%d\n", index)); 2482 break; 2483 case UHF_PORT_INDICATOR: 2484 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2485 "%d\n", index)); 2486 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2487 break; 2488 default: 2489 err = USBD_IOERROR; 2490 goto ret; 2491 } 2492 break; 2493 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2494 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2495 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2496 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2497 break; 2498 default: 2499 err = USBD_IOERROR; 2500 goto ret; 2501 } 2502 xfer->actlen = totlen; 2503 err = USBD_NORMAL_COMPLETION; 2504 ret: 2505 mutex_enter(&sc->sc_lock); 2506 xfer->status = err; 2507 usb_transfer_complete(xfer); 2508 mutex_exit(&sc->sc_lock); 2509 return (USBD_IN_PROGRESS); 2510 } 2511 2512 Static void 2513 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2514 { 2515 int port; 2516 u_int32_t v; 2517 2518 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2519 #ifdef DIAGNOSTIC 2520 if (sc->sc_npcomp != 0) { 2521 int i = (index-1) / sc->sc_npcomp; 2522 if (i >= sc->sc_ncomp) 2523 printf("%s: strange port\n", 2524 device_xname(sc->sc_dev)); 2525 else 2526 printf("%s: handing over %s speed device on " 2527 "port %d to %s\n", 2528 device_xname(sc->sc_dev), 2529 lowspeed ? "low" : "full", 2530 index, device_xname(sc->sc_comps[i])); 2531 } else { 2532 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2533 } 2534 #endif 2535 port = EHCI_PORTSC(index); 2536 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2537 EOWRITE4(sc, port, v | EHCI_PS_PO); 2538 } 2539 2540 /* Abort a root control request. */ 2541 Static void 2542 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2543 { 2544 /* Nothing to do, all transfers are synchronous. */ 2545 } 2546 2547 /* Close the root pipe. */ 2548 Static void 2549 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2550 { 2551 DPRINTF(("ehci_root_ctrl_close\n")); 2552 /* Nothing to do. */ 2553 } 2554 2555 Static void 2556 ehci_root_intr_done(usbd_xfer_handle xfer) 2557 { 2558 xfer->hcpriv = NULL; 2559 } 2560 2561 Static usbd_status 2562 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2563 { 2564 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2565 usbd_status err; 2566 2567 /* Insert last in queue. */ 2568 mutex_enter(&sc->sc_lock); 2569 err = usb_insert_transfer(xfer); 2570 mutex_exit(&sc->sc_lock); 2571 if (err) 2572 return (err); 2573 2574 /* Pipe isn't running, start first */ 2575 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2576 } 2577 2578 Static usbd_status 2579 ehci_root_intr_start(usbd_xfer_handle xfer) 2580 { 2581 usbd_pipe_handle pipe = xfer->pipe; 2582 ehci_softc_t *sc = pipe->device->bus->hci_private; 2583 2584 if (sc->sc_dying) 2585 return (USBD_IOERROR); 2586 2587 mutex_enter(&sc->sc_lock); 2588 sc->sc_intrxfer = xfer; 2589 mutex_exit(&sc->sc_lock); 2590 2591 return (USBD_IN_PROGRESS); 2592 } 2593 2594 /* Abort a root interrupt request. */ 2595 Static void 2596 ehci_root_intr_abort(usbd_xfer_handle xfer) 2597 { 2598 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2599 2600 KASSERT(mutex_owned(&sc->sc_lock)); 2601 if (xfer->pipe->intrxfer == xfer) { 2602 DPRINTF(("ehci_root_intr_abort: remove\n")); 2603 xfer->pipe->intrxfer = NULL; 2604 } 2605 xfer->status = USBD_CANCELLED; 2606 usb_transfer_complete(xfer); 2607 } 2608 2609 /* Close the root pipe. */ 2610 Static void 2611 ehci_root_intr_close(usbd_pipe_handle pipe) 2612 { 2613 ehci_softc_t *sc = pipe->device->bus->hci_private; 2614 2615 KASSERT(mutex_owned(&sc->sc_lock)); 2616 2617 DPRINTF(("ehci_root_intr_close\n")); 2618 2619 sc->sc_intrxfer = NULL; 2620 } 2621 2622 Static void 2623 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2624 { 2625 xfer->hcpriv = NULL; 2626 } 2627 2628 /************************/ 2629 2630 Static ehci_soft_qh_t * 2631 ehci_alloc_sqh(ehci_softc_t *sc) 2632 { 2633 ehci_soft_qh_t *sqh; 2634 usbd_status err; 2635 int i, offs; 2636 usb_dma_t dma; 2637 2638 if (sc->sc_freeqhs == NULL) { 2639 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2640 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2641 EHCI_PAGE_SIZE, &dma); 2642 #ifdef EHCI_DEBUG 2643 if (err) 2644 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2645 #endif 2646 if (err) 2647 return (NULL); 2648 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2649 offs = i * EHCI_SQH_SIZE; 2650 sqh = KERNADDR(&dma, offs); 2651 sqh->physaddr = DMAADDR(&dma, offs); 2652 sqh->dma = dma; 2653 sqh->offs = offs; 2654 sqh->next = sc->sc_freeqhs; 2655 sc->sc_freeqhs = sqh; 2656 } 2657 } 2658 sqh = sc->sc_freeqhs; 2659 sc->sc_freeqhs = sqh->next; 2660 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2661 sqh->next = NULL; 2662 return (sqh); 2663 } 2664 2665 Static void 2666 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2667 { 2668 sqh->next = sc->sc_freeqhs; 2669 sc->sc_freeqhs = sqh; 2670 } 2671 2672 Static ehci_soft_qtd_t * 2673 ehci_alloc_sqtd(ehci_softc_t *sc) 2674 { 2675 ehci_soft_qtd_t *sqtd = NULL; 2676 usbd_status err; 2677 int i, offs; 2678 usb_dma_t dma; 2679 2680 if (sc->sc_freeqtds == NULL) { 2681 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2682 2683 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2684 EHCI_PAGE_SIZE, &dma); 2685 #ifdef EHCI_DEBUG 2686 if (err) 2687 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2688 #endif 2689 if (err) 2690 goto done; 2691 2692 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2693 offs = i * EHCI_SQTD_SIZE; 2694 sqtd = KERNADDR(&dma, offs); 2695 sqtd->physaddr = DMAADDR(&dma, offs); 2696 sqtd->dma = dma; 2697 sqtd->offs = offs; 2698 2699 sqtd->nextqtd = sc->sc_freeqtds; 2700 sc->sc_freeqtds = sqtd; 2701 } 2702 } 2703 2704 sqtd = sc->sc_freeqtds; 2705 sc->sc_freeqtds = sqtd->nextqtd; 2706 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2707 sqtd->nextqtd = NULL; 2708 sqtd->xfer = NULL; 2709 2710 done: 2711 return (sqtd); 2712 } 2713 2714 Static void 2715 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2716 { 2717 2718 KASSERT(mutex_owned(&sc->sc_lock)); 2719 2720 sqtd->nextqtd = sc->sc_freeqtds; 2721 sc->sc_freeqtds = sqtd; 2722 } 2723 2724 Static usbd_status 2725 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2726 int alen, int rd, usbd_xfer_handle xfer, 2727 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2728 { 2729 ehci_soft_qtd_t *next, *cur; 2730 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2731 u_int32_t qtdstatus; 2732 int len, curlen, mps; 2733 int i, tog; 2734 usb_dma_t *dma = &xfer->dmabuf; 2735 u_int16_t flags = xfer->flags; 2736 2737 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2738 2739 len = alen; 2740 dataphys = DMAADDR(dma, 0); 2741 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2742 qtdstatus = EHCI_QTD_ACTIVE | 2743 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2744 EHCI_QTD_SET_CERR(3) 2745 /* IOC set below */ 2746 /* BYTES set below */ 2747 ; 2748 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2749 tog = epipe->nexttoggle; 2750 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2751 2752 cur = ehci_alloc_sqtd(sc); 2753 *sp = cur; 2754 if (cur == NULL) 2755 goto nomem; 2756 2757 usb_syncmem(dma, 0, alen, 2758 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2759 for (;;) { 2760 dataphyspage = EHCI_PAGE(dataphys); 2761 /* The EHCI hardware can handle at most 5 pages. */ 2762 if (dataphyslastpage - dataphyspage < 2763 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2764 /* we can handle it in this QTD */ 2765 curlen = len; 2766 } else { 2767 /* must use multiple TDs, fill as much as possible. */ 2768 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2769 EHCI_PAGE_OFFSET(dataphys); 2770 #ifdef DIAGNOSTIC 2771 if (curlen > len) { 2772 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2773 "len=0x%x offs=0x%x\n", curlen, len, 2774 EHCI_PAGE_OFFSET(dataphys)); 2775 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2776 dataphyslastpage, dataphyspage, 2777 dataphys); 2778 curlen = len; 2779 } 2780 #endif 2781 /* the length must be a multiple of the max size */ 2782 curlen -= curlen % mps; 2783 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2784 "curlen=%d\n", curlen)); 2785 #ifdef DIAGNOSTIC 2786 if (curlen == 0) 2787 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2788 #endif 2789 } 2790 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2791 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2792 dataphys, dataphyslastpage, 2793 len, curlen)); 2794 len -= curlen; 2795 2796 /* 2797 * Allocate another transfer if there's more data left, 2798 * or if force last short transfer flag is set and we're 2799 * allocating a multiple of the max packet size. 2800 */ 2801 if (len != 0 || 2802 ((curlen % mps) == 0 && !rd && curlen != 0 && 2803 (flags & USBD_FORCE_SHORT_XFER))) { 2804 next = ehci_alloc_sqtd(sc); 2805 if (next == NULL) 2806 goto nomem; 2807 nextphys = htole32(next->physaddr); 2808 } else { 2809 next = NULL; 2810 nextphys = EHCI_NULL; 2811 } 2812 2813 for (i = 0; i * EHCI_PAGE_SIZE < 2814 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2815 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2816 if (i != 0) /* use offset only in first buffer */ 2817 a = EHCI_PAGE(a); 2818 cur->qtd.qtd_buffer[i] = htole32(a); 2819 cur->qtd.qtd_buffer_hi[i] = 0; 2820 #ifdef DIAGNOSTIC 2821 if (i >= EHCI_QTD_NBUFFERS) { 2822 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2823 goto nomem; 2824 } 2825 #endif 2826 } 2827 cur->nextqtd = next; 2828 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2829 cur->qtd.qtd_status = 2830 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2831 cur->xfer = xfer; 2832 cur->len = curlen; 2833 2834 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2835 dataphys, dataphys + curlen)); 2836 /* adjust the toggle based on the number of packets in this 2837 qtd */ 2838 if (((curlen + mps - 1) / mps) & 1) { 2839 tog ^= 1; 2840 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2841 } 2842 if (next == NULL) 2843 break; 2844 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2845 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2846 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2847 if (len) 2848 dataphys += curlen; 2849 cur = next; 2850 } 2851 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2852 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2853 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2854 *ep = cur; 2855 epipe->nexttoggle = tog; 2856 2857 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2858 *sp, *ep)); 2859 2860 return (USBD_NORMAL_COMPLETION); 2861 2862 nomem: 2863 /* XXX free chain */ 2864 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2865 return (USBD_NOMEM); 2866 } 2867 2868 Static void 2869 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2870 ehci_soft_qtd_t *sqtdend) 2871 { 2872 ehci_soft_qtd_t *p; 2873 int i; 2874 2875 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2876 sqtd, sqtdend)); 2877 2878 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2879 p = sqtd->nextqtd; 2880 ehci_free_sqtd(sc, sqtd); 2881 } 2882 } 2883 2884 Static ehci_soft_itd_t * 2885 ehci_alloc_itd(ehci_softc_t *sc) 2886 { 2887 struct ehci_soft_itd *itd, *freeitd; 2888 usbd_status err; 2889 int i, s, offs, frindex, previndex; 2890 usb_dma_t dma; 2891 2892 KASSERT(mutex_owned(&sc->sc_lock)); 2893 2894 /* Find an itd that wasn't freed this frame or last frame. This can 2895 * discard itds that were freed before frindex wrapped around 2896 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2897 * interrupt and fiddling with list when that happens */ 2898 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2899 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2900 2901 freeitd = NULL; 2902 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2903 if (itd == NULL) 2904 break; 2905 if (itd->slot != frindex && itd->slot != previndex) { 2906 freeitd = itd; 2907 break; 2908 } 2909 } 2910 2911 if (freeitd == NULL) { 2912 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2913 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2914 EHCI_PAGE_SIZE, &dma); 2915 2916 if (err) { 2917 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2918 return NULL; 2919 } 2920 2921 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2922 offs = i * EHCI_ITD_SIZE; 2923 itd = KERNADDR(&dma, offs); 2924 itd->physaddr = DMAADDR(&dma, offs); 2925 itd->dma = dma; 2926 itd->offs = offs; 2927 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2928 } 2929 freeitd = LIST_FIRST(&sc->sc_freeitds); 2930 } 2931 2932 itd = freeitd; 2933 LIST_REMOVE(itd, u.free_list); 2934 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2935 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2936 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2937 BUS_DMASYNC_PREREAD); 2938 2939 itd->u.frame_list.next = NULL; 2940 itd->u.frame_list.prev = NULL; 2941 itd->xfer_next = NULL; 2942 itd->slot = 0; 2943 splx(s); 2944 2945 return itd; 2946 } 2947 2948 Static void 2949 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2950 { 2951 2952 KASSERT(mutex_owned(&sc->sc_lock)); 2953 2954 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2955 } 2956 2957 /****************/ 2958 2959 /* 2960 * Close a reqular pipe. 2961 * Assumes that there are no pending transactions. 2962 */ 2963 Static void 2964 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2965 { 2966 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2967 ehci_softc_t *sc = pipe->device->bus->hci_private; 2968 ehci_soft_qh_t *sqh = epipe->sqh; 2969 2970 KASSERT(mutex_owned(&sc->sc_lock)); 2971 2972 ehci_rem_qh(sc, sqh, head); 2973 ehci_free_sqh(sc, epipe->sqh); 2974 } 2975 2976 /* 2977 * Abort a device request. 2978 * If this routine is called at splusb() it guarantees that the request 2979 * will be removed from the hardware scheduling and that the callback 2980 * for it will be called with USBD_CANCELLED status. 2981 * It's impossible to guarantee that the requested transfer will not 2982 * have happened since the hardware runs concurrently. 2983 * If the transaction has already happened we rely on the ordinary 2984 * interrupt processing to process it. 2985 * XXX This is most probably wrong. 2986 * XXXMRG this doesn't make sense anymore. 2987 */ 2988 Static void 2989 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2990 { 2991 #define exfer EXFER(xfer) 2992 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2993 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2994 ehci_soft_qh_t *sqh = epipe->sqh; 2995 ehci_soft_qtd_t *sqtd; 2996 ehci_physaddr_t cur; 2997 u_int32_t qhstatus; 2998 int hit; 2999 int wake; 3000 3001 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 3002 3003 KASSERT(mutex_owned(&sc->sc_lock)); 3004 3005 if (sc->sc_dying) { 3006 /* If we're dying, just do the software part. */ 3007 xfer->status = status; /* make software ignore it */ 3008 callout_stop(&xfer->timeout_handle); 3009 usb_transfer_complete(xfer); 3010 return; 3011 } 3012 3013 if (xfer->device->bus->intr_context) 3014 panic("ehci_abort_xfer: not in process context"); 3015 3016 /* 3017 * If an abort is already in progress then just wait for it to 3018 * complete and return. 3019 */ 3020 if (xfer->hcflags & UXFER_ABORTING) { 3021 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3022 #ifdef DIAGNOSTIC 3023 if (status == USBD_TIMEOUT) 3024 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3025 #endif 3026 /* Override the status which might be USBD_TIMEOUT. */ 3027 xfer->status = status; 3028 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3029 xfer->hcflags |= UXFER_ABORTWAIT; 3030 while (xfer->hcflags & UXFER_ABORTING) 3031 cv_wait(&xfer->hccv, &sc->sc_lock); 3032 return; 3033 } 3034 xfer->hcflags |= UXFER_ABORTING; 3035 3036 /* 3037 * Step 1: Make interrupt routine and hardware ignore xfer. 3038 */ 3039 xfer->status = status; /* make software ignore it */ 3040 callout_stop(&xfer->timeout_handle); 3041 3042 usb_syncmem(&sqh->dma, 3043 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3044 sizeof(sqh->qh.qh_qtd.qtd_status), 3045 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3046 qhstatus = sqh->qh.qh_qtd.qtd_status; 3047 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3048 usb_syncmem(&sqh->dma, 3049 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3050 sizeof(sqh->qh.qh_qtd.qtd_status), 3051 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3052 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3053 usb_syncmem(&sqtd->dma, 3054 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3055 sizeof(sqtd->qtd.qtd_status), 3056 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3057 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3058 usb_syncmem(&sqtd->dma, 3059 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3060 sizeof(sqtd->qtd.qtd_status), 3061 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3062 if (sqtd == exfer->sqtdend) 3063 break; 3064 } 3065 3066 /* 3067 * Step 2: Wait until we know hardware has finished any possible 3068 * use of the xfer. Also make sure the soft interrupt routine 3069 * has run. 3070 */ 3071 ehci_sync_hc(sc); 3072 sc->sc_softwake = 1; 3073 usb_schedsoftintr(&sc->sc_bus); 3074 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3075 3076 /* 3077 * Step 3: Remove any vestiges of the xfer from the hardware. 3078 * The complication here is that the hardware may have executed 3079 * beyond the xfer we're trying to abort. So as we're scanning 3080 * the TDs of this xfer we check if the hardware points to 3081 * any of them. 3082 */ 3083 3084 usb_syncmem(&sqh->dma, 3085 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3086 sizeof(sqh->qh.qh_curqtd), 3087 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3088 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3089 hit = 0; 3090 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3091 hit |= cur == sqtd->physaddr; 3092 if (sqtd == exfer->sqtdend) 3093 break; 3094 } 3095 sqtd = sqtd->nextqtd; 3096 /* Zap curqtd register if hardware pointed inside the xfer. */ 3097 if (hit && sqtd != NULL) { 3098 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3099 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3100 usb_syncmem(&sqh->dma, 3101 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3102 sizeof(sqh->qh.qh_curqtd), 3103 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3104 sqh->qh.qh_qtd.qtd_status = qhstatus; 3105 usb_syncmem(&sqh->dma, 3106 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3107 sizeof(sqh->qh.qh_qtd.qtd_status), 3108 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3109 } else { 3110 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3111 } 3112 3113 /* 3114 * Step 4: Execute callback. 3115 */ 3116 #ifdef DIAGNOSTIC 3117 exfer->isdone = 1; 3118 #endif 3119 wake = xfer->hcflags & UXFER_ABORTWAIT; 3120 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3121 usb_transfer_complete(xfer); 3122 if (wake) { 3123 cv_broadcast(&xfer->hccv); 3124 } 3125 3126 KASSERT(mutex_owned(&sc->sc_lock)); 3127 #undef exfer 3128 } 3129 3130 Static void 3131 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3132 { 3133 ehci_isoc_trans_t trans_status; 3134 struct ehci_pipe *epipe; 3135 struct ehci_xfer *exfer; 3136 ehci_softc_t *sc; 3137 struct ehci_soft_itd *itd; 3138 int i, wake; 3139 3140 epipe = (struct ehci_pipe *) xfer->pipe; 3141 exfer = EXFER(xfer); 3142 sc = epipe->pipe.device->bus->hci_private; 3143 3144 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3145 3146 KASSERT(mutex_owned(&sc->sc_lock)); 3147 3148 if (sc->sc_dying) { 3149 xfer->status = status; 3150 callout_stop(&xfer->timeout_handle); 3151 usb_transfer_complete(xfer); 3152 return; 3153 } 3154 3155 if (xfer->hcflags & UXFER_ABORTING) { 3156 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3157 3158 #ifdef DIAGNOSTIC 3159 if (status == USBD_TIMEOUT) 3160 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3161 #endif 3162 3163 xfer->status = status; 3164 DPRINTFN(2, ("ehci_abort_isoc_xfer: waiting for abort to finish\n")); 3165 xfer->hcflags |= UXFER_ABORTWAIT; 3166 while (xfer->hcflags & UXFER_ABORTING) 3167 cv_wait(&xfer->hccv, &sc->sc_lock); 3168 goto done; 3169 } 3170 xfer->hcflags |= UXFER_ABORTING; 3171 3172 xfer->status = status; 3173 callout_stop(&xfer->timeout_handle); 3174 3175 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3176 usb_syncmem(&itd->dma, 3177 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3178 sizeof(itd->itd.itd_ctl), 3179 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3180 3181 for (i = 0; i < 8; i++) { 3182 trans_status = le32toh(itd->itd.itd_ctl[i]); 3183 trans_status &= ~EHCI_ITD_ACTIVE; 3184 itd->itd.itd_ctl[i] = htole32(trans_status); 3185 } 3186 3187 usb_syncmem(&itd->dma, 3188 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3189 sizeof(itd->itd.itd_ctl), 3190 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3191 } 3192 3193 sc->sc_softwake = 1; 3194 usb_schedsoftintr(&sc->sc_bus); 3195 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3196 3197 #ifdef DIAGNOSTIC 3198 exfer->isdone = 1; 3199 #endif 3200 wake = xfer->hcflags & UXFER_ABORTWAIT; 3201 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3202 usb_transfer_complete(xfer); 3203 if (wake) { 3204 cv_broadcast(&xfer->hccv); 3205 } 3206 3207 done: 3208 KASSERT(mutex_owned(&sc->sc_lock)); 3209 return; 3210 } 3211 3212 Static void 3213 ehci_timeout(void *addr) 3214 { 3215 struct ehci_xfer *exfer = addr; 3216 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3217 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3218 3219 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3220 #ifdef EHCI_DEBUG 3221 if (ehcidebug > 1) 3222 usbd_dump_pipe(exfer->xfer.pipe); 3223 #endif 3224 3225 if (sc->sc_dying) { 3226 mutex_enter(&sc->sc_lock); 3227 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3228 mutex_exit(&sc->sc_lock); 3229 return; 3230 } 3231 3232 /* Execute the abort in a process context. */ 3233 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3234 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3235 USB_TASKQ_HC); 3236 } 3237 3238 Static void 3239 ehci_timeout_task(void *addr) 3240 { 3241 usbd_xfer_handle xfer = addr; 3242 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3243 3244 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3245 3246 mutex_enter(&sc->sc_lock); 3247 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3248 mutex_exit(&sc->sc_lock); 3249 } 3250 3251 /************************/ 3252 3253 Static usbd_status 3254 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3255 { 3256 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3257 usbd_status err; 3258 3259 /* Insert last in queue. */ 3260 mutex_enter(&sc->sc_lock); 3261 err = usb_insert_transfer(xfer); 3262 mutex_exit(&sc->sc_lock); 3263 if (err) 3264 return (err); 3265 3266 /* Pipe isn't running, start first */ 3267 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3268 } 3269 3270 Static usbd_status 3271 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3272 { 3273 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3274 usbd_status err; 3275 3276 if (sc->sc_dying) 3277 return (USBD_IOERROR); 3278 3279 #ifdef DIAGNOSTIC 3280 if (!(xfer->rqflags & URQ_REQUEST)) { 3281 /* XXX panic */ 3282 printf("ehci_device_ctrl_transfer: not a request\n"); 3283 return (USBD_INVAL); 3284 } 3285 #endif 3286 3287 err = ehci_device_request(xfer); 3288 if (err) { 3289 return (err); 3290 } 3291 3292 if (sc->sc_bus.use_polling) 3293 ehci_waitintr(sc, xfer); 3294 3295 return (USBD_IN_PROGRESS); 3296 } 3297 3298 Static void 3299 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3300 { 3301 struct ehci_xfer *ex = EXFER(xfer); 3302 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3303 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3304 usb_device_request_t *req = &xfer->request; 3305 int len = UGETW(req->wLength); 3306 int rd = req->bmRequestType & UT_READ; 3307 3308 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3309 3310 KASSERT(mutex_owned(&sc->sc_lock)); 3311 3312 #ifdef DIAGNOSTIC 3313 if (!(xfer->rqflags & URQ_REQUEST)) { 3314 panic("ehci_ctrl_done: not a request"); 3315 } 3316 #endif 3317 3318 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3319 ehci_del_intr_list(sc, ex); /* remove from active list */ 3320 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3321 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3322 BUS_DMASYNC_POSTWRITE); 3323 if (len) 3324 usb_syncmem(&xfer->dmabuf, 0, len, 3325 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3326 } 3327 3328 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3329 } 3330 3331 /* Abort a device control request. */ 3332 Static void 3333 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3334 { 3335 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3336 ehci_abort_xfer(xfer, USBD_CANCELLED); 3337 } 3338 3339 /* Close a device control pipe. */ 3340 Static void 3341 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3342 { 3343 ehci_softc_t *sc = pipe->device->bus->hci_private; 3344 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3345 3346 KASSERT(mutex_owned(&sc->sc_lock)); 3347 3348 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3349 3350 ehci_close_pipe(pipe, sc->sc_async_head); 3351 } 3352 3353 Static usbd_status 3354 ehci_device_request(usbd_xfer_handle xfer) 3355 { 3356 #define exfer EXFER(xfer) 3357 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3358 usb_device_request_t *req = &xfer->request; 3359 usbd_device_handle dev = epipe->pipe.device; 3360 ehci_softc_t *sc = dev->bus->hci_private; 3361 int addr = dev->address; 3362 ehci_soft_qtd_t *setup, *stat, *next; 3363 ehci_soft_qh_t *sqh; 3364 int isread; 3365 int len; 3366 usbd_status err; 3367 3368 isread = req->bmRequestType & UT_READ; 3369 len = UGETW(req->wLength); 3370 3371 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3372 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3373 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3374 UGETW(req->wIndex), len, addr, 3375 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3376 3377 setup = ehci_alloc_sqtd(sc); 3378 if (setup == NULL) { 3379 err = USBD_NOMEM; 3380 goto bad1; 3381 } 3382 stat = ehci_alloc_sqtd(sc); 3383 if (stat == NULL) { 3384 err = USBD_NOMEM; 3385 goto bad2; 3386 } 3387 3388 mutex_enter(&sc->sc_lock); 3389 3390 sqh = epipe->sqh; 3391 epipe->u.ctl.length = len; 3392 3393 /* Update device address and length since they may have changed 3394 during the setup of the control pipe in usbd_new_device(). */ 3395 /* XXX This only needs to be done once, but it's too early in open. */ 3396 /* XXXX Should not touch ED here! */ 3397 sqh->qh.qh_endp = 3398 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3399 htole32( 3400 EHCI_QH_SET_ADDR(addr) | 3401 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3402 ); 3403 3404 /* Set up data transaction */ 3405 if (len != 0) { 3406 ehci_soft_qtd_t *end; 3407 3408 /* Start toggle at 1. */ 3409 epipe->nexttoggle = 1; 3410 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3411 &next, &end); 3412 if (err) 3413 goto bad3; 3414 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3415 end->nextqtd = stat; 3416 end->qtd.qtd_next = 3417 end->qtd.qtd_altnext = htole32(stat->physaddr); 3418 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3419 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3420 } else { 3421 next = stat; 3422 } 3423 3424 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3425 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3426 3427 /* Clear toggle */ 3428 setup->qtd.qtd_status = htole32( 3429 EHCI_QTD_ACTIVE | 3430 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3431 EHCI_QTD_SET_CERR(3) | 3432 EHCI_QTD_SET_TOGGLE(0) | 3433 EHCI_QTD_SET_BYTES(sizeof *req) 3434 ); 3435 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3436 setup->qtd.qtd_buffer_hi[0] = 0; 3437 setup->nextqtd = next; 3438 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3439 setup->xfer = xfer; 3440 setup->len = sizeof *req; 3441 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3442 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3443 3444 stat->qtd.qtd_status = htole32( 3445 EHCI_QTD_ACTIVE | 3446 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3447 EHCI_QTD_SET_CERR(3) | 3448 EHCI_QTD_SET_TOGGLE(1) | 3449 EHCI_QTD_IOC 3450 ); 3451 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3452 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3453 stat->nextqtd = NULL; 3454 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3455 stat->xfer = xfer; 3456 stat->len = 0; 3457 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3458 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3459 3460 #ifdef EHCI_DEBUG 3461 if (ehcidebug > 5) { 3462 DPRINTF(("ehci_device_request:\n")); 3463 ehci_dump_sqh(sqh); 3464 ehci_dump_sqtds(setup); 3465 } 3466 #endif 3467 3468 exfer->sqtdstart = setup; 3469 exfer->sqtdend = stat; 3470 #ifdef DIAGNOSTIC 3471 if (!exfer->isdone) { 3472 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3473 } 3474 exfer->isdone = 0; 3475 #endif 3476 3477 /* Insert qTD in QH list. */ 3478 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3479 if (xfer->timeout && !sc->sc_bus.use_polling) { 3480 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3481 ehci_timeout, xfer); 3482 } 3483 ehci_add_intr_list(sc, exfer); 3484 xfer->status = USBD_IN_PROGRESS; 3485 mutex_exit(&sc->sc_lock); 3486 3487 #ifdef EHCI_DEBUG 3488 if (ehcidebug > 10) { 3489 DPRINTF(("ehci_device_request: status=%x\n", 3490 EOREAD4(sc, EHCI_USBSTS))); 3491 delay(10000); 3492 ehci_dump_regs(sc); 3493 ehci_dump_sqh(sc->sc_async_head); 3494 ehci_dump_sqh(sqh); 3495 ehci_dump_sqtds(setup); 3496 } 3497 #endif 3498 3499 return (USBD_NORMAL_COMPLETION); 3500 3501 bad3: 3502 mutex_exit(&sc->sc_lock); 3503 ehci_free_sqtd(sc, stat); 3504 bad2: 3505 ehci_free_sqtd(sc, setup); 3506 bad1: 3507 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3508 mutex_enter(&sc->sc_lock); 3509 xfer->status = err; 3510 usb_transfer_complete(xfer); 3511 mutex_exit(&sc->sc_lock); 3512 return (err); 3513 #undef exfer 3514 } 3515 3516 /* 3517 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3518 * qTD status, or miss signalling occasionally under heavy load. If the host 3519 * machine is too fast, we we can miss transaction completion - when we scan 3520 * the active list the transaction still seems to be active. This generally 3521 * exhibits itself as a umass stall that never recovers. 3522 * 3523 * We work around this behaviour by setting up this callback after any softintr 3524 * that completes with transactions still pending, giving us another chance to 3525 * check for completion after the writeback has taken place. 3526 */ 3527 Static void 3528 ehci_intrlist_timeout(void *arg) 3529 { 3530 ehci_softc_t *sc = arg; 3531 3532 DPRINTF(("ehci_intrlist_timeout\n")); 3533 usb_schedsoftintr(&sc->sc_bus); 3534 } 3535 3536 /************************/ 3537 3538 Static usbd_status 3539 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3540 { 3541 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3542 usbd_status err; 3543 3544 /* Insert last in queue. */ 3545 mutex_enter(&sc->sc_lock); 3546 err = usb_insert_transfer(xfer); 3547 mutex_exit(&sc->sc_lock); 3548 if (err) 3549 return (err); 3550 3551 /* Pipe isn't running, start first */ 3552 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3553 } 3554 3555 Static usbd_status 3556 ehci_device_bulk_start(usbd_xfer_handle xfer) 3557 { 3558 #define exfer EXFER(xfer) 3559 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3560 usbd_device_handle dev = epipe->pipe.device; 3561 ehci_softc_t *sc = dev->bus->hci_private; 3562 ehci_soft_qtd_t *data, *dataend; 3563 ehci_soft_qh_t *sqh; 3564 usbd_status err; 3565 int len, isread, endpt; 3566 3567 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3568 xfer, xfer->length, xfer->flags)); 3569 3570 if (sc->sc_dying) 3571 return (USBD_IOERROR); 3572 3573 #ifdef DIAGNOSTIC 3574 if (xfer->rqflags & URQ_REQUEST) 3575 panic("ehci_device_bulk_start: a request"); 3576 #endif 3577 3578 mutex_enter(&sc->sc_lock); 3579 3580 len = xfer->length; 3581 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3582 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3583 sqh = epipe->sqh; 3584 3585 epipe->u.bulk.length = len; 3586 3587 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3588 &dataend); 3589 if (err) { 3590 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3591 xfer->status = err; 3592 usb_transfer_complete(xfer); 3593 mutex_exit(&sc->sc_lock); 3594 return (err); 3595 } 3596 3597 #ifdef EHCI_DEBUG 3598 if (ehcidebug > 5) { 3599 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3600 ehci_dump_sqh(sqh); 3601 ehci_dump_sqtds(data); 3602 } 3603 #endif 3604 3605 /* Set up interrupt info. */ 3606 exfer->sqtdstart = data; 3607 exfer->sqtdend = dataend; 3608 #ifdef DIAGNOSTIC 3609 if (!exfer->isdone) { 3610 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3611 } 3612 exfer->isdone = 0; 3613 #endif 3614 3615 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3616 if (xfer->timeout && !sc->sc_bus.use_polling) { 3617 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3618 ehci_timeout, xfer); 3619 } 3620 ehci_add_intr_list(sc, exfer); 3621 xfer->status = USBD_IN_PROGRESS; 3622 mutex_exit(&sc->sc_lock); 3623 3624 #ifdef EHCI_DEBUG 3625 if (ehcidebug > 10) { 3626 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3627 delay(10000); 3628 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3629 ehci_dump_regs(sc); 3630 #if 0 3631 printf("async_head:\n"); 3632 ehci_dump_sqh(sc->sc_async_head); 3633 #endif 3634 printf("sqh:\n"); 3635 ehci_dump_sqh(sqh); 3636 ehci_dump_sqtds(data); 3637 } 3638 #endif 3639 3640 if (sc->sc_bus.use_polling) 3641 ehci_waitintr(sc, xfer); 3642 3643 return (USBD_IN_PROGRESS); 3644 #undef exfer 3645 } 3646 3647 Static void 3648 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3649 { 3650 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3651 ehci_abort_xfer(xfer, USBD_CANCELLED); 3652 } 3653 3654 /* 3655 * Close a device bulk pipe. 3656 */ 3657 Static void 3658 ehci_device_bulk_close(usbd_pipe_handle pipe) 3659 { 3660 ehci_softc_t *sc = pipe->device->bus->hci_private; 3661 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3662 3663 KASSERT(mutex_owned(&sc->sc_lock)); 3664 3665 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3666 pipe->endpoint->datatoggle = epipe->nexttoggle; 3667 ehci_close_pipe(pipe, sc->sc_async_head); 3668 } 3669 3670 Static void 3671 ehci_device_bulk_done(usbd_xfer_handle xfer) 3672 { 3673 struct ehci_xfer *ex = EXFER(xfer); 3674 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3675 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3676 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3677 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3678 3679 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3680 xfer, xfer->actlen)); 3681 3682 KASSERT(mutex_owned(&sc->sc_lock)); 3683 3684 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3685 ehci_del_intr_list(sc, ex); /* remove from active list */ 3686 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3687 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3688 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3689 } 3690 3691 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3692 } 3693 3694 /************************/ 3695 3696 Static usbd_status 3697 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3698 { 3699 struct ehci_soft_islot *isp; 3700 int islot, lev; 3701 3702 /* Find a poll rate that is large enough. */ 3703 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3704 if (EHCI_ILEV_IVAL(lev) <= ival) 3705 break; 3706 3707 /* Pick an interrupt slot at the right level. */ 3708 /* XXX could do better than picking at random */ 3709 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3710 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3711 3712 sqh->islot = islot; 3713 isp = &sc->sc_islots[islot]; 3714 mutex_enter(&sc->sc_lock); 3715 ehci_add_qh(sc, sqh, isp->sqh); 3716 mutex_exit(&sc->sc_lock); 3717 3718 return (USBD_NORMAL_COMPLETION); 3719 } 3720 3721 Static usbd_status 3722 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3723 { 3724 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3725 usbd_status err; 3726 3727 /* Insert last in queue. */ 3728 mutex_enter(&sc->sc_lock); 3729 err = usb_insert_transfer(xfer); 3730 mutex_exit(&sc->sc_lock); 3731 if (err) 3732 return (err); 3733 3734 /* 3735 * Pipe isn't running (otherwise err would be USBD_INPROG), 3736 * so start it first. 3737 */ 3738 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3739 } 3740 3741 Static usbd_status 3742 ehci_device_intr_start(usbd_xfer_handle xfer) 3743 { 3744 #define exfer EXFER(xfer) 3745 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3746 usbd_device_handle dev = xfer->pipe->device; 3747 ehci_softc_t *sc = dev->bus->hci_private; 3748 ehci_soft_qtd_t *data, *dataend; 3749 ehci_soft_qh_t *sqh; 3750 usbd_status err; 3751 int len, isread, endpt; 3752 3753 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3754 xfer, xfer->length, xfer->flags)); 3755 3756 if (sc->sc_dying) 3757 return (USBD_IOERROR); 3758 3759 #ifdef DIAGNOSTIC 3760 if (xfer->rqflags & URQ_REQUEST) 3761 panic("ehci_device_intr_start: a request"); 3762 #endif 3763 3764 mutex_enter(&sc->sc_lock); 3765 3766 len = xfer->length; 3767 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3768 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3769 sqh = epipe->sqh; 3770 3771 epipe->u.intr.length = len; 3772 3773 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3774 &dataend); 3775 if (err) { 3776 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3777 xfer->status = err; 3778 usb_transfer_complete(xfer); 3779 mutex_exit(&sc->sc_lock); 3780 return (err); 3781 } 3782 3783 #ifdef EHCI_DEBUG 3784 if (ehcidebug > 5) { 3785 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3786 ehci_dump_sqh(sqh); 3787 ehci_dump_sqtds(data); 3788 } 3789 #endif 3790 3791 /* Set up interrupt info. */ 3792 exfer->sqtdstart = data; 3793 exfer->sqtdend = dataend; 3794 #ifdef DIAGNOSTIC 3795 if (!exfer->isdone) { 3796 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3797 } 3798 exfer->isdone = 0; 3799 #endif 3800 3801 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3802 if (xfer->timeout && !sc->sc_bus.use_polling) { 3803 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3804 ehci_timeout, xfer); 3805 } 3806 ehci_add_intr_list(sc, exfer); 3807 xfer->status = USBD_IN_PROGRESS; 3808 mutex_exit(&sc->sc_lock); 3809 3810 #ifdef EHCI_DEBUG 3811 if (ehcidebug > 10) { 3812 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3813 delay(10000); 3814 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3815 ehci_dump_regs(sc); 3816 printf("sqh:\n"); 3817 ehci_dump_sqh(sqh); 3818 ehci_dump_sqtds(data); 3819 } 3820 #endif 3821 3822 if (sc->sc_bus.use_polling) 3823 ehci_waitintr(sc, xfer); 3824 3825 return (USBD_IN_PROGRESS); 3826 #undef exfer 3827 } 3828 3829 Static void 3830 ehci_device_intr_abort(usbd_xfer_handle xfer) 3831 { 3832 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3833 if (xfer->pipe->intrxfer == xfer) { 3834 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3835 xfer->pipe->intrxfer = NULL; 3836 } 3837 /* 3838 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3839 * async doorbell. That's dependent on the async list, wheras 3840 * intr xfers are periodic, should not use this? 3841 */ 3842 ehci_abort_xfer(xfer, USBD_CANCELLED); 3843 } 3844 3845 Static void 3846 ehci_device_intr_close(usbd_pipe_handle pipe) 3847 { 3848 ehci_softc_t *sc = pipe->device->bus->hci_private; 3849 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3850 struct ehci_soft_islot *isp; 3851 3852 KASSERT(mutex_owned(&sc->sc_lock)); 3853 3854 isp = &sc->sc_islots[epipe->sqh->islot]; 3855 ehci_close_pipe(pipe, isp->sqh); 3856 } 3857 3858 Static void 3859 ehci_device_intr_done(usbd_xfer_handle xfer) 3860 { 3861 #define exfer EXFER(xfer) 3862 struct ehci_xfer *ex = EXFER(xfer); 3863 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3864 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3865 ehci_soft_qtd_t *data, *dataend; 3866 ehci_soft_qh_t *sqh; 3867 usbd_status err; 3868 int len, isread, endpt; 3869 3870 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3871 xfer, xfer->actlen)); 3872 3873 KASSERT(mutex_owned(&sc->sc_lock)); 3874 3875 if (xfer->pipe->repeat) { 3876 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3877 3878 len = epipe->u.intr.length; 3879 xfer->length = len; 3880 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3881 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3882 usb_syncmem(&xfer->dmabuf, 0, len, 3883 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3884 sqh = epipe->sqh; 3885 3886 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3887 &data, &dataend); 3888 if (err) { 3889 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3890 xfer->status = err; 3891 return; 3892 } 3893 3894 /* Set up interrupt info. */ 3895 exfer->sqtdstart = data; 3896 exfer->sqtdend = dataend; 3897 #ifdef DIAGNOSTIC 3898 if (!exfer->isdone) { 3899 printf("ehci_device_intr_done: not done, ex=%p\n", 3900 exfer); 3901 } 3902 exfer->isdone = 0; 3903 #endif 3904 3905 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3906 if (xfer->timeout && !sc->sc_bus.use_polling) { 3907 callout_reset(&xfer->timeout_handle, 3908 mstohz(xfer->timeout), ehci_timeout, xfer); 3909 } 3910 3911 xfer->status = USBD_IN_PROGRESS; 3912 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3913 ehci_del_intr_list(sc, ex); /* remove from active list */ 3914 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3915 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3916 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3917 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3918 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3919 } 3920 #undef exfer 3921 } 3922 3923 /************************/ 3924 3925 Static usbd_status 3926 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3927 { 3928 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3929 usbd_status err; 3930 3931 mutex_enter(&sc->sc_lock); 3932 err = usb_insert_transfer(xfer); 3933 mutex_exit(&sc->sc_lock); 3934 if (err && err != USBD_IN_PROGRESS) 3935 return err; 3936 3937 return ehci_device_isoc_start(xfer); 3938 } 3939 3940 Static usbd_status 3941 ehci_device_isoc_start(usbd_xfer_handle xfer) 3942 { 3943 struct ehci_pipe *epipe; 3944 usbd_device_handle dev; 3945 ehci_softc_t *sc; 3946 struct ehci_xfer *exfer; 3947 ehci_soft_itd_t *itd, *prev, *start, *stop; 3948 usb_dma_t *dma_buf; 3949 int i, j, k, frames, uframes, ufrperframe; 3950 int trans_count, offs, total_length; 3951 int frindex; 3952 3953 start = NULL; 3954 prev = NULL; 3955 itd = NULL; 3956 trans_count = 0; 3957 total_length = 0; 3958 exfer = (struct ehci_xfer *) xfer; 3959 sc = xfer->pipe->device->bus->hci_private; 3960 dev = xfer->pipe->device; 3961 epipe = (struct ehci_pipe *)xfer->pipe; 3962 3963 /* 3964 * To allow continuous transfers, above we start all transfers 3965 * immediately. However, we're still going to get usbd_start_next call 3966 * this when another xfer completes. So, check if this is already 3967 * in progress or not 3968 */ 3969 3970 if (exfer->itdstart != NULL) 3971 return USBD_IN_PROGRESS; 3972 3973 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3974 xfer, xfer->length, xfer->flags)); 3975 3976 if (sc->sc_dying) 3977 return USBD_IOERROR; 3978 3979 /* 3980 * To avoid complication, don't allow a request right now that'll span 3981 * the entire frame table. To within 4 frames, to allow some leeway 3982 * on either side of where the hc currently is. 3983 */ 3984 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3985 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3986 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3987 return USBD_INVAL; 3988 } 3989 3990 #ifdef DIAGNOSTIC 3991 if (xfer->rqflags & URQ_REQUEST) 3992 panic("ehci_device_isoc_start: request\n"); 3993 3994 if (!exfer->isdone) 3995 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3996 exfer->isdone = 0; 3997 #endif 3998 3999 /* 4000 * Step 1: Allocate and initialize itds, how many do we need? 4001 * One per transfer if interval >= 8 microframes, fewer if we use 4002 * multiple microframes per frame. 4003 */ 4004 4005 i = epipe->pipe.endpoint->edesc->bInterval; 4006 if (i > 16 || i == 0) { 4007 /* Spec page 271 says intervals > 16 are invalid */ 4008 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 4009 return USBD_INVAL; 4010 } 4011 4012 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4013 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4014 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4015 4016 if (frames == 0) { 4017 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 4018 return USBD_INVAL; 4019 } 4020 4021 dma_buf = &xfer->dmabuf; 4022 offs = 0; 4023 4024 for (i = 0; i < frames; i++) { 4025 int froffs = offs; 4026 itd = ehci_alloc_itd(sc); 4027 4028 if (prev != NULL) { 4029 prev->itd.itd_next = 4030 htole32(itd->physaddr | EHCI_LINK_ITD); 4031 usb_syncmem(&itd->dma, 4032 itd->offs + offsetof(ehci_itd_t, itd_next), 4033 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4034 4035 prev->xfer_next = itd; 4036 } else { 4037 start = itd; 4038 } 4039 4040 /* 4041 * Step 1.5, initialize uframes 4042 */ 4043 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4044 /* Calculate which page in the list this starts in */ 4045 int addr = DMAADDR(dma_buf, froffs); 4046 addr = EHCI_PAGE_OFFSET(addr); 4047 addr += (offs - froffs); 4048 addr = EHCI_PAGE(addr); 4049 addr /= EHCI_PAGE_SIZE; 4050 4051 /* This gets the initial offset into the first page, 4052 * looks how far further along the current uframe 4053 * offset is. Works out how many pages that is. 4054 */ 4055 4056 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4057 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4058 EHCI_ITD_SET_PG(addr) | 4059 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4060 4061 total_length += xfer->frlengths[trans_count]; 4062 offs += xfer->frlengths[trans_count]; 4063 trans_count++; 4064 4065 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4066 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4067 break; 4068 } 4069 } 4070 4071 /* Step 1.75, set buffer pointers. To simplify matters, all 4072 * pointers are filled out for the next 7 hardware pages in 4073 * the dma block, so no need to worry what pages to cover 4074 * and what to not. 4075 */ 4076 4077 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4078 /* 4079 * Don't try to lookup a page that's past the end 4080 * of buffer 4081 */ 4082 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4083 if (page_offs >= dma_buf->block->size) 4084 break; 4085 4086 unsigned long long page = DMAADDR(dma_buf, page_offs); 4087 page = EHCI_PAGE(page); 4088 itd->itd.itd_bufr[j] = 4089 htole32(EHCI_ITD_SET_BPTR(page)); 4090 itd->itd.itd_bufr_hi[j] = 4091 htole32(page >> 32); 4092 } 4093 4094 /* 4095 * Other special values 4096 */ 4097 4098 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4099 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4100 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4101 4102 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4103 ? 1 : 0; 4104 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4105 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4106 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4107 4108 /* FIXME: handle invalid trans */ 4109 itd->itd.itd_bufr[2] |= 4110 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4111 4112 usb_syncmem(&itd->dma, 4113 itd->offs + offsetof(ehci_itd_t, itd_next), 4114 sizeof(ehci_itd_t), 4115 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4116 4117 prev = itd; 4118 } /* End of frame */ 4119 4120 stop = itd; 4121 stop->xfer_next = NULL; 4122 exfer->isoc_len = total_length; 4123 4124 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4125 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4126 4127 /* 4128 * Part 2: Transfer descriptors have now been set up, now they must 4129 * be scheduled into the period frame list. Erk. Not wanting to 4130 * complicate matters, transfer is denied if the transfer spans 4131 * more than the period frame list. 4132 */ 4133 4134 mutex_enter(&sc->sc_lock); 4135 4136 /* Start inserting frames */ 4137 if (epipe->u.isoc.cur_xfers > 0) { 4138 frindex = epipe->u.isoc.next_frame; 4139 } else { 4140 frindex = EOREAD4(sc, EHCI_FRINDEX); 4141 frindex = frindex >> 3; /* Erase microframe index */ 4142 frindex += 2; 4143 } 4144 4145 if (frindex >= sc->sc_flsize) 4146 frindex &= (sc->sc_flsize - 1); 4147 4148 /* What's the frame interval? */ 4149 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4150 if (i / USB_UFRAMES_PER_FRAME == 0) 4151 i = 1; 4152 else 4153 i /= USB_UFRAMES_PER_FRAME; 4154 4155 itd = start; 4156 for (j = 0; j < frames; j++) { 4157 if (itd == NULL) 4158 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4159 4160 itd->itd.itd_next = sc->sc_flist[frindex]; 4161 if (itd->itd.itd_next == 0) 4162 /* FIXME: frindex table gets initialized to NULL 4163 * or EHCI_NULL? */ 4164 itd->itd.itd_next = EHCI_NULL; 4165 4166 usb_syncmem(&itd->dma, 4167 itd->offs + offsetof(ehci_itd_t, itd_next), 4168 sizeof(itd->itd.itd_next), 4169 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4170 4171 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4172 4173 usb_syncmem(&sc->sc_fldma, 4174 sizeof(ehci_link_t) * frindex, 4175 sizeof(ehci_link_t), 4176 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4177 4178 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4179 sc->sc_softitds[frindex] = itd; 4180 if (itd->u.frame_list.next != NULL) 4181 itd->u.frame_list.next->u.frame_list.prev = itd; 4182 itd->slot = frindex; 4183 itd->u.frame_list.prev = NULL; 4184 4185 frindex += i; 4186 if (frindex >= sc->sc_flsize) 4187 frindex -= sc->sc_flsize; 4188 4189 itd = itd->xfer_next; 4190 } 4191 4192 epipe->u.isoc.cur_xfers++; 4193 epipe->u.isoc.next_frame = frindex; 4194 4195 exfer->itdstart = start; 4196 exfer->itdend = stop; 4197 exfer->sqtdstart = NULL; 4198 exfer->sqtdstart = NULL; 4199 4200 ehci_add_intr_list(sc, exfer); 4201 xfer->status = USBD_IN_PROGRESS; 4202 xfer->done = 0; 4203 mutex_exit(&sc->sc_lock); 4204 4205 if (sc->sc_bus.use_polling) { 4206 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4207 ehci_waitintr(sc, xfer); 4208 } 4209 4210 return USBD_IN_PROGRESS; 4211 } 4212 4213 Static void 4214 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4215 { 4216 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4217 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4218 } 4219 4220 Static void 4221 ehci_device_isoc_close(usbd_pipe_handle pipe) 4222 { 4223 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4224 } 4225 4226 Static void 4227 ehci_device_isoc_done(usbd_xfer_handle xfer) 4228 { 4229 struct ehci_xfer *exfer; 4230 ehci_softc_t *sc; 4231 struct ehci_pipe *epipe; 4232 4233 exfer = EXFER(xfer); 4234 sc = xfer->pipe->device->bus->hci_private; 4235 epipe = (struct ehci_pipe *) xfer->pipe; 4236 4237 KASSERT(mutex_owned(&sc->sc_lock)); 4238 4239 epipe->u.isoc.cur_xfers--; 4240 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4241 ehci_del_intr_list(sc, exfer); 4242 ehci_rem_free_itd_chain(sc, exfer); 4243 } 4244 4245 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4246 BUS_DMASYNC_POSTREAD); 4247 4248 } 4249
Indexes created Thu Oct 02 01:09:59 GMT 2025