ehci.c revision 1.181.6.14
1 /* $NetBSD: ehci.c,v 1.181.6.14 2012/02/26 05:05:44 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.181.6.14 2012/02/26 05:05:44 mrg Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/kmem.h> 66 #include <sys/device.h> 67 #include <sys/select.h> 68 #include <sys/proc.h> 69 #include <sys/queue.h> 70 #include <sys/mutex.h> 71 #include <sys/bus.h> 72 #include <sys/cpu.h> 73 74 #include <machine/endian.h> 75 76 #include <dev/usb/usb.h> 77 #include <dev/usb/usbdi.h> 78 #include <dev/usb/usbdivar.h> 79 #include <dev/usb/usb_mem.h> 80 #include <dev/usb/usb_quirks.h> 81 82 #include <dev/usb/ehcireg.h> 83 #include <dev/usb/ehcivar.h> 84 #include <dev/usb/usbroothub_subr.h> 85 86 #ifdef EHCI_DEBUG 87 #include <sys/kprintf.h> 88 static void 89 ehciprintf(const char *fmt, ...) 90 { 91 va_list ap; 92 93 va_start(ap, fmt); 94 kprintf(fmt, TOLOG|TOCONS, NULL, NULL, ap); 95 va_end(ap); 96 } 97 98 #define DPRINTF(x) do { if (ehcidebug) ehciprintf x; } while(0) 99 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) ehciprintf x; } while (0) 100 int ehcidebug = 0; 101 #else 102 #define DPRINTF(x) 103 #define DPRINTFN(n,x) 104 #endif 105 106 struct ehci_pipe { 107 struct usbd_pipe pipe; 108 int nexttoggle; 109 110 ehci_soft_qh_t *sqh; 111 union { 112 ehci_soft_qtd_t *qtd; 113 /* ehci_soft_itd_t *itd; */ 114 } tail; 115 union { 116 /* Control pipe */ 117 struct { 118 usb_dma_t reqdma; 119 u_int length; 120 } ctl; 121 /* Interrupt pipe */ 122 struct { 123 u_int length; 124 } intr; 125 /* Bulk pipe */ 126 struct { 127 u_int length; 128 } bulk; 129 /* Iso pipe */ 130 struct { 131 u_int next_frame; 132 u_int cur_xfers; 133 } isoc; 134 } u; 135 }; 136 137 Static usbd_status ehci_open(usbd_pipe_handle); 138 Static void ehci_poll(struct usbd_bus *); 139 Static void ehci_softintr(void *); 140 Static int ehci_intr1(ehci_softc_t *); 141 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 142 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 143 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 144 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 145 Static void ehci_idone(struct ehci_xfer *); 146 Static void ehci_timeout(void *); 147 Static void ehci_timeout_task(void *); 148 Static void ehci_intrlist_timeout(void *); 149 Static void ehci_doorbell(void *); 150 Static void ehci_pcd(void *); 151 152 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 153 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 154 155 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 156 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 157 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 158 159 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 160 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 161 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 162 Static void ehci_root_ctrl_close(usbd_pipe_handle); 163 Static void ehci_root_ctrl_done(usbd_xfer_handle); 164 165 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 166 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 167 Static void ehci_root_intr_abort(usbd_xfer_handle); 168 Static void ehci_root_intr_close(usbd_pipe_handle); 169 Static void ehci_root_intr_done(usbd_xfer_handle); 170 171 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 172 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 173 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 174 Static void ehci_device_ctrl_close(usbd_pipe_handle); 175 Static void ehci_device_ctrl_done(usbd_xfer_handle); 176 177 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 178 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 179 Static void ehci_device_bulk_abort(usbd_xfer_handle); 180 Static void ehci_device_bulk_close(usbd_pipe_handle); 181 Static void ehci_device_bulk_done(usbd_xfer_handle); 182 183 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 184 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 185 Static void ehci_device_intr_abort(usbd_xfer_handle); 186 Static void ehci_device_intr_close(usbd_pipe_handle); 187 Static void ehci_device_intr_done(usbd_xfer_handle); 188 189 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 190 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 191 Static void ehci_device_isoc_abort(usbd_xfer_handle); 192 Static void ehci_device_isoc_close(usbd_pipe_handle); 193 Static void ehci_device_isoc_done(usbd_xfer_handle); 194 195 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 196 Static void ehci_noop(usbd_pipe_handle pipe); 197 198 Static void ehci_disown(ehci_softc_t *, int, int); 199 200 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 201 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 202 203 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 204 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 205 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 206 ehci_softc_t *, int, int, usbd_xfer_handle, 207 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 208 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 209 ehci_soft_qtd_t *); 210 211 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 212 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 213 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 214 struct ehci_xfer *exfer); 215 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 216 usbd_status status); 217 218 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 219 220 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 221 int ival); 222 223 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 224 ehci_soft_qh_t *); 225 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 226 ehci_soft_qh_t *); 227 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 228 Static void ehci_sync_hc(ehci_softc_t *); 229 230 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 231 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 232 233 #ifdef EHCI_DEBUG 234 Static void ehci_dump_regs(ehci_softc_t *); 235 void ehci_dump(void); 236 Static ehci_softc_t *theehci; 237 Static void ehci_dump_link(ehci_link_t, int); 238 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 239 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 240 Static void ehci_dump_qtd(ehci_qtd_t *); 241 Static void ehci_dump_sqh(ehci_soft_qh_t *); 242 #if notyet 243 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 244 Static void ehci_dump_itd(struct ehci_soft_itd *); 245 #endif 246 #ifdef DIAGNOSTIC 247 Static void ehci_dump_exfer(struct ehci_xfer *); 248 #endif 249 #endif 250 251 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 252 253 #define EHCI_INTR_ENDPT 1 254 255 #define ehci_add_intr_list(sc, ex) \ 256 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 257 #define ehci_del_intr_list(sc, ex) \ 258 do { \ 259 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 260 (ex)->inext.tqe_prev = NULL; \ 261 } while (0) 262 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 263 264 Static const struct usbd_bus_methods ehci_bus_methods = { 265 .open_pipe = ehci_open, 266 .soft_intr = ehci_softintr, 267 .do_poll = ehci_poll, 268 .allocm = ehci_allocm, 269 .freem = ehci_freem, 270 .allocx = ehci_allocx, 271 .freex = ehci_freex, 272 .get_lock = ehci_get_lock, 273 }; 274 275 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 276 .transfer = ehci_root_ctrl_transfer, 277 .start = ehci_root_ctrl_start, 278 .abort = ehci_root_ctrl_abort, 279 .close = ehci_root_ctrl_close, 280 .cleartoggle = ehci_noop, 281 .done = ehci_root_ctrl_done, 282 }; 283 284 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 285 .transfer = ehci_root_intr_transfer, 286 .start = ehci_root_intr_start, 287 .abort = ehci_root_intr_abort, 288 .close = ehci_root_intr_close, 289 .cleartoggle = ehci_noop, 290 .done = ehci_root_intr_done, 291 }; 292 293 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 294 .transfer = ehci_device_ctrl_transfer, 295 .start = ehci_device_ctrl_start, 296 .abort = ehci_device_ctrl_abort, 297 .close = ehci_device_ctrl_close, 298 .cleartoggle = ehci_noop, 299 .done = ehci_device_ctrl_done, 300 }; 301 302 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 303 .transfer = ehci_device_intr_transfer, 304 .start = ehci_device_intr_start, 305 .abort = ehci_device_intr_abort, 306 .close = ehci_device_intr_close, 307 .cleartoggle = ehci_device_clear_toggle, 308 .done = ehci_device_intr_done, 309 }; 310 311 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 312 .transfer = ehci_device_bulk_transfer, 313 .start = ehci_device_bulk_start, 314 .abort = ehci_device_bulk_abort, 315 .close = ehci_device_bulk_close, 316 .cleartoggle = ehci_device_clear_toggle, 317 .done = ehci_device_bulk_done, 318 }; 319 320 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 321 .transfer = ehci_device_isoc_transfer, 322 .start = ehci_device_isoc_start, 323 .abort = ehci_device_isoc_abort, 324 .close = ehci_device_isoc_close, 325 .cleartoggle = ehci_noop, 326 .done = ehci_device_isoc_done, 327 }; 328 329 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 330 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 331 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 332 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 333 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 334 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 335 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 336 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 337 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 338 }; 339 340 usbd_status 341 ehci_init(ehci_softc_t *sc) 342 { 343 u_int32_t vers, sparams, cparams, hcr; 344 u_int i; 345 usbd_status err; 346 ehci_soft_qh_t *sqh; 347 u_int ncomp; 348 349 DPRINTF(("ehci_init: start\n")); 350 #ifdef EHCI_DEBUG 351 theehci = sc; 352 #endif 353 354 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 355 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 356 cv_init(&sc->sc_softwake_cv, "ehciab"); 357 cv_init(&sc->sc_doorbell, "ehcidi"); 358 359 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 360 ehci_doorbell, sc); 361 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 362 ehci_pcd, sc); 363 364 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 365 366 vers = EREAD2(sc, EHCI_HCIVERSION); 367 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 368 vers >> 8, vers & 0xff); 369 370 sparams = EREAD4(sc, EHCI_HCSPARAMS); 371 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 372 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 373 ncomp = EHCI_HCS_N_CC(sparams); 374 if (ncomp != sc->sc_ncomp) { 375 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 376 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 377 #if NOHCI == 0 || NUHCI == 0 378 aprint_error("%s: ohci or uhci probably not configured\n", 379 device_xname(sc->sc_dev)); 380 #endif 381 if (ncomp < sc->sc_ncomp) 382 sc->sc_ncomp = ncomp; 383 } 384 if (sc->sc_ncomp > 0) { 385 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 386 aprint_normal("%s: companion controller%s, %d port%s each:", 387 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 388 EHCI_HCS_N_PCC(sparams), 389 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 390 for (i = 0; i < sc->sc_ncomp; i++) 391 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 392 aprint_normal("\n"); 393 } 394 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 395 cparams = EREAD4(sc, EHCI_HCCPARAMS); 396 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 397 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 398 399 if (EHCI_HCC_64BIT(cparams)) { 400 /* MUST clear segment register if 64 bit capable. */ 401 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 402 } 403 404 sc->sc_bus.usbrev = USBREV_2_0; 405 406 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 407 USB_MEM_RESERVE); 408 409 /* Reset the controller */ 410 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 411 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 412 usb_delay_ms(&sc->sc_bus, 1); 413 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 414 for (i = 0; i < 100; i++) { 415 usb_delay_ms(&sc->sc_bus, 1); 416 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 417 if (!hcr) 418 break; 419 } 420 if (hcr) { 421 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 422 return (USBD_IOERROR); 423 } 424 if (sc->sc_vendor_init) 425 sc->sc_vendor_init(sc); 426 427 /* 428 * If we are doing embedded transaction translation function, force 429 * the controller to host mode. 430 */ 431 if (sc->sc_flags & EHCIF_ETTF) { 432 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 433 usbmode &= ~EHCI_USBMODE_CM; 434 usbmode |= EHCI_USBMODE_CM_HOST; 435 EWRITE4(sc, EHCI_USBMODE, usbmode); 436 } 437 438 /* XXX need proper intr scheduling */ 439 sc->sc_rand = 96; 440 441 /* frame list size at default, read back what we got and use that */ 442 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 443 case 0: sc->sc_flsize = 1024; break; 444 case 1: sc->sc_flsize = 512; break; 445 case 2: sc->sc_flsize = 256; break; 446 case 3: return (USBD_IOERROR); 447 } 448 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 449 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 450 if (err) 451 return (err); 452 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 453 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 454 455 for (i = 0; i < sc->sc_flsize; i++) { 456 sc->sc_flist[i] = EHCI_NULL; 457 } 458 459 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 460 461 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 462 KM_SLEEP); 463 if (sc->sc_softitds == NULL) 464 return ENOMEM; 465 LIST_INIT(&sc->sc_freeitds); 466 TAILQ_INIT(&sc->sc_intrhead); 467 468 /* Set up the bus struct. */ 469 sc->sc_bus.methods = &ehci_bus_methods; 470 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 471 472 sc->sc_eintrs = EHCI_NORMAL_INTRS; 473 474 /* 475 * Allocate the interrupt dummy QHs. These are arranged to give poll 476 * intervals that are powers of 2 times 1ms. 477 */ 478 for (i = 0; i < EHCI_INTRQHS; i++) { 479 sqh = ehci_alloc_sqh(sc); 480 if (sqh == NULL) { 481 err = USBD_NOMEM; 482 goto bad1; 483 } 484 sc->sc_islots[i].sqh = sqh; 485 } 486 for (i = 0; i < EHCI_INTRQHS; i++) { 487 sqh = sc->sc_islots[i].sqh; 488 if (i == 0) { 489 /* The last (1ms) QH terminates. */ 490 sqh->qh.qh_link = EHCI_NULL; 491 sqh->next = NULL; 492 } else { 493 /* Otherwise the next QH has half the poll interval */ 494 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 495 sqh->qh.qh_link = htole32(sqh->next->physaddr | 496 EHCI_LINK_QH); 497 } 498 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 499 sqh->qh.qh_curqtd = EHCI_NULL; 500 sqh->next = NULL; 501 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 502 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 503 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 504 sqh->sqtd = NULL; 505 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 506 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 507 } 508 /* Point the frame list at the last level (128ms). */ 509 for (i = 0; i < sc->sc_flsize; i++) { 510 int j; 511 512 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 513 revbits[i & (EHCI_MAX_POLLRATE-1)]; 514 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 515 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 516 i)].sqh->physaddr); 517 } 518 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 519 BUS_DMASYNC_PREWRITE); 520 521 /* Allocate dummy QH that starts the async list. */ 522 sqh = ehci_alloc_sqh(sc); 523 if (sqh == NULL) { 524 err = USBD_NOMEM; 525 goto bad1; 526 } 527 /* Fill the QH */ 528 sqh->qh.qh_endp = 529 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 530 sqh->qh.qh_link = 531 htole32(sqh->physaddr | EHCI_LINK_QH); 532 sqh->qh.qh_curqtd = EHCI_NULL; 533 sqh->next = NULL; 534 /* Fill the overlay qTD */ 535 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 536 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 537 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 538 sqh->sqtd = NULL; 539 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 540 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 541 #ifdef EHCI_DEBUG 542 if (ehcidebug) { 543 ehci_dump_sqh(sqh); 544 } 545 #endif 546 547 /* Point to async list */ 548 sc->sc_async_head = sqh; 549 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 550 551 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 552 553 /* Turn on controller */ 554 EOWRITE4(sc, EHCI_USBCMD, 555 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 556 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 557 EHCI_CMD_ASE | 558 EHCI_CMD_PSE | 559 EHCI_CMD_RS); 560 561 /* Take over port ownership */ 562 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 563 564 for (i = 0; i < 100; i++) { 565 usb_delay_ms(&sc->sc_bus, 1); 566 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 567 if (!hcr) 568 break; 569 } 570 if (hcr) { 571 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 572 return (USBD_IOERROR); 573 } 574 575 /* Enable interrupts */ 576 DPRINTFN(1,("ehci_init: enabling\n")); 577 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 578 579 return (USBD_NORMAL_COMPLETION); 580 581 #if 0 582 bad2: 583 ehci_free_sqh(sc, sc->sc_async_head); 584 #endif 585 bad1: 586 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 587 return (err); 588 } 589 590 int 591 ehci_intr(void *v) 592 { 593 ehci_softc_t *sc = v; 594 int ret = 0; 595 596 if (sc == NULL) 597 return 0; 598 599 mutex_spin_enter(&sc->sc_intr_lock); 600 601 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 602 goto done; 603 604 /* If we get an interrupt while polling, then just ignore it. */ 605 if (sc->sc_bus.use_polling) { 606 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 607 608 if (intrs) 609 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 610 #ifdef DIAGNOSTIC 611 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 612 #endif 613 goto done; 614 } 615 616 ret = ehci_intr1(sc); 617 618 done: 619 mutex_spin_exit(&sc->sc_intr_lock); 620 return ret; 621 } 622 623 Static int 624 ehci_intr1(ehci_softc_t *sc) 625 { 626 u_int32_t intrs, eintrs; 627 628 DPRINTFN(20,("ehci_intr1: enter\n")); 629 630 /* In case the interrupt occurs before initialization has completed. */ 631 if (sc == NULL) { 632 #ifdef DIAGNOSTIC 633 printf("ehci_intr1: sc == NULL\n"); 634 #endif 635 return (0); 636 } 637 638 KASSERT(mutex_owned(&sc->sc_intr_lock)); 639 640 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 641 if (!intrs) 642 return (0); 643 644 eintrs = intrs & sc->sc_eintrs; 645 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 646 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 647 (u_int)eintrs)); 648 if (!eintrs) 649 return (0); 650 651 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 652 sc->sc_bus.no_intrs++; 653 if (eintrs & EHCI_STS_IAA) { 654 DPRINTF(("ehci_intr1: door bell\n")); 655 kpreempt_disable(); 656 softint_schedule(sc->sc_doorbell_si); 657 kpreempt_enable(); 658 eintrs &= ~EHCI_STS_IAA; 659 } 660 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 661 DPRINTFN(5,("ehci_intr1: %s %s\n", 662 eintrs & EHCI_STS_INT ? "INT" : "", 663 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 664 usb_schedsoftintr(&sc->sc_bus); 665 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 666 } 667 if (eintrs & EHCI_STS_HSE) { 668 printf("%s: unrecoverable error, controller halted\n", 669 device_xname(sc->sc_dev)); 670 /* XXX what else */ 671 } 672 if (eintrs & EHCI_STS_PCD) { 673 kpreempt_disable(); 674 softint_schedule(sc->sc_pcd_si); 675 kpreempt_enable(); 676 eintrs &= ~EHCI_STS_PCD; 677 } 678 679 if (eintrs != 0) { 680 /* Block unprocessed interrupts. */ 681 sc->sc_eintrs &= ~eintrs; 682 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 683 printf("%s: blocking intrs 0x%x\n", 684 device_xname(sc->sc_dev), eintrs); 685 } 686 687 return (1); 688 } 689 690 Static void 691 ehci_doorbell(void *addr) 692 { 693 ehci_softc_t *sc = addr; 694 695 mutex_enter(&sc->sc_lock); 696 cv_broadcast(&sc->sc_doorbell); 697 mutex_exit(&sc->sc_lock); 698 } 699 700 Static void 701 ehci_pcd(void *addr) 702 { 703 ehci_softc_t *sc = addr; 704 usbd_xfer_handle xfer; 705 usbd_pipe_handle pipe; 706 u_char *p; 707 int i, m; 708 709 mutex_enter(&sc->sc_lock); 710 xfer = sc->sc_intrxfer; 711 712 if (xfer == NULL) { 713 /* Just ignore the change. */ 714 goto done; 715 } 716 717 pipe = xfer->pipe; 718 719 p = KERNADDR(&xfer->dmabuf, 0); 720 m = min(sc->sc_noport, xfer->length * 8 - 1); 721 memset(p, 0, xfer->length); 722 for (i = 1; i <= m; i++) { 723 /* Pick out CHANGE bits from the status reg. */ 724 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 725 p[i/8] |= 1 << (i%8); 726 } 727 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 728 xfer->actlen = xfer->length; 729 xfer->status = USBD_NORMAL_COMPLETION; 730 731 usb_transfer_complete(xfer); 732 733 done: 734 mutex_exit(&sc->sc_lock); 735 } 736 737 Static void 738 ehci_softintr(void *v) 739 { 740 struct usbd_bus *bus = v; 741 ehci_softc_t *sc = bus->hci_private; 742 struct ehci_xfer *ex, *nextex; 743 744 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 745 746 DPRINTFN(10,("%s: ehci_softintr\n", device_xname(sc->sc_dev))); 747 748 /* 749 * The only explanation I can think of for why EHCI is as brain dead 750 * as UHCI interrupt-wise is that Intel was involved in both. 751 * An interrupt just tells us that something is done, we have no 752 * clue what, so we need to scan through all active transfers. :-( 753 */ 754 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 755 nextex = TAILQ_NEXT(ex, inext); 756 ehci_check_intr(sc, ex); 757 } 758 759 /* Schedule a callout to catch any dropped transactions. */ 760 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 761 !TAILQ_EMPTY(&sc->sc_intrhead)) 762 callout_reset(&sc->sc_tmo_intrlist, 763 hz, ehci_intrlist_timeout, sc); 764 765 if (sc->sc_softwake) { 766 sc->sc_softwake = 0; 767 cv_broadcast(&sc->sc_softwake_cv); 768 } 769 } 770 771 /* Check for an interrupt. */ 772 Static void 773 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 774 { 775 int attr; 776 777 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 778 779 KASSERT(mutex_owned(&sc->sc_lock)); 780 781 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 782 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 783 ehci_check_itd_intr(sc, ex); 784 else 785 ehci_check_qh_intr(sc, ex); 786 787 return; 788 } 789 790 Static void 791 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 792 { 793 ehci_soft_qtd_t *sqtd, *lsqtd; 794 __uint32_t status; 795 796 KASSERT(mutex_owned(&sc->sc_lock)); 797 798 if (ex->sqtdstart == NULL) { 799 printf("ehci_check_qh_intr: not valid sqtd\n"); 800 return; 801 } 802 803 lsqtd = ex->sqtdend; 804 #ifdef DIAGNOSTIC 805 if (lsqtd == NULL) { 806 printf("ehci_check_qh_intr: lsqtd==0\n"); 807 return; 808 } 809 #endif 810 /* 811 * If the last TD is still active we need to check whether there 812 * is a an error somewhere in the middle, or whether there was a 813 * short packet (SPD and not ACTIVE). 814 */ 815 usb_syncmem(&lsqtd->dma, 816 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 817 sizeof(lsqtd->qtd.qtd_status), 818 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 819 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 820 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 821 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 822 usb_syncmem(&sqtd->dma, 823 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 824 sizeof(sqtd->qtd.qtd_status), 825 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 826 status = le32toh(sqtd->qtd.qtd_status); 827 usb_syncmem(&sqtd->dma, 828 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 829 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 830 /* If there's an active QTD the xfer isn't done. */ 831 if (status & EHCI_QTD_ACTIVE) 832 break; 833 /* Any kind of error makes the xfer done. */ 834 if (status & EHCI_QTD_HALTED) 835 goto done; 836 /* We want short packets, and it is short: it's done */ 837 if (EHCI_QTD_GET_BYTES(status) != 0) 838 goto done; 839 } 840 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 841 ex, ex->sqtdstart)); 842 usb_syncmem(&lsqtd->dma, 843 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 844 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 845 return; 846 } 847 done: 848 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 849 callout_stop(&ex->xfer.timeout_handle); 850 ehci_idone(ex); 851 } 852 853 Static void 854 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 855 ehci_soft_itd_t *itd; 856 int i; 857 858 KASSERT(mutex_owned(&sc->sc_lock)); 859 860 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 861 return; 862 863 if (ex->itdstart == NULL) { 864 printf("ehci_check_itd_intr: not valid itd\n"); 865 return; 866 } 867 868 itd = ex->itdend; 869 #ifdef DIAGNOSTIC 870 if (itd == NULL) { 871 printf("ehci_check_itd_intr: itdend == 0\n"); 872 return; 873 } 874 #endif 875 876 /* 877 * check no active transfers in last itd, meaning we're finished 878 */ 879 880 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 881 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 882 BUS_DMASYNC_POSTREAD); 883 884 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 885 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 886 break; 887 } 888 889 if (i == EHCI_ITD_NUFRAMES) { 890 goto done; /* All 8 descriptors inactive, it's done */ 891 } 892 893 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 894 ex->itdstart)); 895 return; 896 done: 897 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 898 callout_stop(&ex->xfer.timeout_handle); 899 ehci_idone(ex); 900 } 901 902 Static void 903 ehci_idone(struct ehci_xfer *ex) 904 { 905 usbd_xfer_handle xfer = &ex->xfer; 906 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 907 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 908 ehci_soft_qtd_t *sqtd, *lsqtd; 909 u_int32_t status = 0, nstatus = 0; 910 int actlen; 911 912 KASSERT(mutex_owned(&sc->sc_lock)); 913 914 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 915 916 #ifdef DIAGNOSTIC 917 { 918 if (ex->isdone) { 919 #ifdef EHCI_DEBUG 920 printf("ehci_idone: ex is done!\n "); 921 ehci_dump_exfer(ex); 922 #else 923 printf("ehci_idone: ex=%p is done!\n", ex); 924 #endif 925 return; 926 } 927 ex->isdone = 1; 928 } 929 #endif 930 if (xfer->status == USBD_CANCELLED || 931 xfer->status == USBD_TIMEOUT) { 932 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 933 return; 934 } 935 936 #ifdef EHCI_DEBUG 937 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 938 if (ehcidebug > 10) 939 ehci_dump_sqtds(ex->sqtdstart); 940 #endif 941 942 /* The transfer is done, compute actual length and status. */ 943 944 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 945 == UE_ISOCHRONOUS) { 946 /* Isoc transfer */ 947 struct ehci_soft_itd *itd; 948 int i, nframes, len, uframes; 949 950 nframes = 0; 951 actlen = 0; 952 953 i = xfer->pipe->endpoint->edesc->bInterval; 954 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 955 956 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 957 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 958 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 959 BUS_DMASYNC_POSTREAD); 960 961 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 962 /* XXX - driver didn't fill in the frame full 963 * of uframes. This leads to scheduling 964 * inefficiencies, but working around 965 * this doubles complexity of tracking 966 * an xfer. 967 */ 968 if (nframes >= xfer->nframes) 969 break; 970 971 status = le32toh(itd->itd.itd_ctl[i]); 972 len = EHCI_ITD_GET_LEN(status); 973 if (EHCI_ITD_GET_STATUS(status) != 0) 974 len = 0; /*No valid data on error*/ 975 976 xfer->frlengths[nframes++] = len; 977 actlen += len; 978 } 979 980 if (nframes >= xfer->nframes) 981 break; 982 } 983 984 xfer->actlen = actlen; 985 xfer->status = USBD_NORMAL_COMPLETION; 986 goto end; 987 } 988 989 /* Continue processing xfers using queue heads */ 990 991 lsqtd = ex->sqtdend; 992 actlen = 0; 993 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 994 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 995 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 996 nstatus = le32toh(sqtd->qtd.qtd_status); 997 if (nstatus & EHCI_QTD_ACTIVE) 998 break; 999 1000 status = nstatus; 1001 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1002 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1003 } 1004 1005 1006 /* 1007 * If there are left over TDs we need to update the toggle. 1008 * The default pipe doesn't need it since control transfers 1009 * start the toggle at 0 every time. 1010 * For a short transfer we need to update the toggle for the missing 1011 * packets within the qTD. 1012 */ 1013 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1014 xfer->pipe->device->default_pipe != xfer->pipe) { 1015 DPRINTFN(2, ("ehci_idone: need toggle update " 1016 "status=%08x nstatus=%08x\n", status, nstatus)); 1017 #if 0 1018 ehci_dump_sqh(epipe->sqh); 1019 ehci_dump_sqtds(ex->sqtdstart); 1020 #endif 1021 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1022 } 1023 1024 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 1025 xfer->length, actlen, status)); 1026 xfer->actlen = actlen; 1027 if (status & EHCI_QTD_HALTED) { 1028 #ifdef EHCI_DEBUG 1029 char sbuf[128]; 1030 1031 snprintb(sbuf, sizeof(sbuf), 1032 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 1033 (u_int32_t)status); 1034 1035 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 1036 "status 0x%s\n", 1037 xfer->pipe->device->address, 1038 xfer->pipe->endpoint->edesc->bEndpointAddress, 1039 sbuf)); 1040 if (ehcidebug > 2) { 1041 ehci_dump_sqh(epipe->sqh); 1042 ehci_dump_sqtds(ex->sqtdstart); 1043 } 1044 #endif 1045 /* low&full speed has an extra error flag */ 1046 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1047 EHCI_QH_SPEED_HIGH) 1048 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1049 else 1050 status &= EHCI_QTD_STATERRS; 1051 if (status == 0) /* no other errors means a stall */ { 1052 xfer->status = USBD_STALLED; 1053 } else { 1054 xfer->status = USBD_IOERROR; /* more info XXX */ 1055 } 1056 /* XXX need to reset TT on missed microframe */ 1057 if (status & EHCI_QTD_MISSEDMICRO) { 1058 printf("%s: missed microframe, TT reset not " 1059 "implemented, hub might be inoperational\n", 1060 device_xname(sc->sc_dev)); 1061 } 1062 } else { 1063 xfer->status = USBD_NORMAL_COMPLETION; 1064 } 1065 1066 end: 1067 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1068 * during this call, before methods->done is called: dma sync required 1069 * beforehand? */ 1070 usb_transfer_complete(xfer); 1071 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1072 } 1073 1074 /* 1075 * Wait here until controller claims to have an interrupt. 1076 * Then call ehci_intr and return. Use timeout to avoid waiting 1077 * too long. 1078 */ 1079 Static void 1080 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1081 { 1082 int timo; 1083 u_int32_t intrs; 1084 1085 xfer->status = USBD_IN_PROGRESS; 1086 for (timo = xfer->timeout; timo >= 0; timo--) { 1087 usb_delay_ms(&sc->sc_bus, 1); 1088 if (sc->sc_dying) 1089 break; 1090 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1091 sc->sc_eintrs; 1092 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1093 #ifdef EHCI_DEBUG 1094 if (ehcidebug > 15) 1095 ehci_dump_regs(sc); 1096 #endif 1097 if (intrs) { 1098 mutex_spin_enter(&sc->sc_intr_lock); 1099 ehci_intr1(sc); 1100 mutex_spin_exit(&sc->sc_intr_lock); 1101 if (xfer->status != USBD_IN_PROGRESS) 1102 return; 1103 } 1104 } 1105 1106 /* Timeout */ 1107 DPRINTF(("ehci_waitintr: timeout\n")); 1108 xfer->status = USBD_TIMEOUT; 1109 mutex_enter(&sc->sc_lock); 1110 usb_transfer_complete(xfer); 1111 mutex_exit(&sc->sc_lock); 1112 /* XXX should free TD */ 1113 } 1114 1115 Static void 1116 ehci_poll(struct usbd_bus *bus) 1117 { 1118 ehci_softc_t *sc = bus->hci_private; 1119 #ifdef EHCI_DEBUG 1120 static int last; 1121 int new; 1122 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1123 if (new != last) { 1124 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1125 last = new; 1126 } 1127 #endif 1128 1129 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1130 mutex_spin_enter(&sc->sc_intr_lock); 1131 ehci_intr1(sc); 1132 mutex_spin_exit(&sc->sc_intr_lock); 1133 } 1134 } 1135 1136 void 1137 ehci_childdet(device_t self, device_t child) 1138 { 1139 struct ehci_softc *sc = device_private(self); 1140 1141 KASSERT(sc->sc_child == child); 1142 sc->sc_child = NULL; 1143 } 1144 1145 int 1146 ehci_detach(struct ehci_softc *sc, int flags) 1147 { 1148 usbd_xfer_handle xfer; 1149 int rv = 0; 1150 1151 if (sc->sc_child != NULL) 1152 rv = config_detach(sc->sc_child, flags); 1153 1154 if (rv != 0) 1155 return (rv); 1156 1157 callout_halt(&sc->sc_tmo_intrlist, NULL); 1158 callout_destroy(&sc->sc_tmo_intrlist); 1159 1160 /* XXX free other data structures XXX */ 1161 if (sc->sc_softitds) 1162 kmem_free(sc->sc_softitds, 1163 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1164 cv_destroy(&sc->sc_doorbell); 1165 cv_destroy(&sc->sc_softwake_cv); 1166 1167 softint_disestablish(sc->sc_doorbell_si); 1168 softint_disestablish(sc->sc_pcd_si); 1169 1170 while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 1171 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1172 kmem_free(xfer, sizeof(struct ehci_xfer)); 1173 } 1174 1175 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1176 1177 return (rv); 1178 } 1179 1180 1181 int 1182 ehci_activate(device_t self, enum devact act) 1183 { 1184 struct ehci_softc *sc = device_private(self); 1185 1186 switch (act) { 1187 case DVACT_DEACTIVATE: 1188 sc->sc_dying = 1; 1189 return 0; 1190 default: 1191 return EOPNOTSUPP; 1192 } 1193 } 1194 1195 /* 1196 * Handle suspend/resume. 1197 * 1198 * We need to switch to polling mode here, because this routine is 1199 * called from an interrupt context. This is all right since we 1200 * are almost suspended anyway. 1201 * 1202 * Note that this power handler isn't to be registered directly; the 1203 * bus glue needs to call out to it. 1204 */ 1205 bool 1206 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1207 { 1208 ehci_softc_t *sc = device_private(dv); 1209 int i; 1210 uint32_t cmd, hcr; 1211 1212 mutex_spin_enter(&sc->sc_intr_lock); 1213 sc->sc_bus.use_polling++; 1214 mutex_spin_exit(&sc->sc_intr_lock); 1215 1216 for (i = 1; i <= sc->sc_noport; i++) { 1217 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1218 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1219 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1220 } 1221 1222 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1223 1224 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1225 EOWRITE4(sc, EHCI_USBCMD, cmd); 1226 1227 for (i = 0; i < 100; i++) { 1228 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1229 if (hcr == 0) 1230 break; 1231 1232 usb_delay_ms(&sc->sc_bus, 1); 1233 } 1234 if (hcr != 0) 1235 printf("%s: reset timeout\n", device_xname(dv)); 1236 1237 cmd &= ~EHCI_CMD_RS; 1238 EOWRITE4(sc, EHCI_USBCMD, cmd); 1239 1240 for (i = 0; i < 100; i++) { 1241 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1242 if (hcr == EHCI_STS_HCH) 1243 break; 1244 1245 usb_delay_ms(&sc->sc_bus, 1); 1246 } 1247 if (hcr != EHCI_STS_HCH) 1248 printf("%s: config timeout\n", device_xname(dv)); 1249 1250 mutex_spin_enter(&sc->sc_intr_lock); 1251 sc->sc_bus.use_polling--; 1252 mutex_spin_exit(&sc->sc_intr_lock); 1253 1254 return true; 1255 } 1256 1257 bool 1258 ehci_resume(device_t dv, const pmf_qual_t *qual) 1259 { 1260 ehci_softc_t *sc = device_private(dv); 1261 int i; 1262 uint32_t cmd, hcr; 1263 1264 /* restore things in case the bios sucks */ 1265 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1266 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1267 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1268 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1269 1270 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1271 1272 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1273 1274 hcr = 0; 1275 for (i = 1; i <= sc->sc_noport; i++) { 1276 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1277 if ((cmd & EHCI_PS_PO) == 0 && 1278 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1279 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1280 hcr = 1; 1281 } 1282 } 1283 1284 if (hcr) { 1285 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1286 1287 for (i = 1; i <= sc->sc_noport; i++) { 1288 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1289 if ((cmd & EHCI_PS_PO) == 0 && 1290 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1291 EOWRITE4(sc, EHCI_PORTSC(i), 1292 cmd & ~EHCI_PS_FPR); 1293 } 1294 } 1295 1296 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1297 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1298 1299 for (i = 0; i < 100; i++) { 1300 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1301 if (hcr != EHCI_STS_HCH) 1302 break; 1303 1304 usb_delay_ms(&sc->sc_bus, 1); 1305 } 1306 if (hcr == EHCI_STS_HCH) 1307 printf("%s: config timeout\n", device_xname(dv)); 1308 1309 return true; 1310 } 1311 1312 /* 1313 * Shut down the controller when the system is going down. 1314 */ 1315 bool 1316 ehci_shutdown(device_t self, int flags) 1317 { 1318 ehci_softc_t *sc = device_private(self); 1319 1320 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1321 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1322 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1323 return true; 1324 } 1325 1326 Static usbd_status 1327 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1328 { 1329 struct ehci_softc *sc = bus->hci_private; 1330 usbd_status err; 1331 1332 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1333 if (err == USBD_NOMEM) 1334 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1335 #ifdef EHCI_DEBUG 1336 if (err) 1337 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1338 #endif 1339 return (err); 1340 } 1341 1342 Static void 1343 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1344 { 1345 struct ehci_softc *sc = bus->hci_private; 1346 1347 if (dma->block->flags & USB_DMA_RESERVE) { 1348 usb_reserve_freem(&sc->sc_dma_reserve, 1349 dma); 1350 return; 1351 } 1352 usb_freemem(&sc->sc_bus, dma); 1353 } 1354 1355 Static usbd_xfer_handle 1356 ehci_allocx(struct usbd_bus *bus) 1357 { 1358 struct ehci_softc *sc = bus->hci_private; 1359 usbd_xfer_handle xfer; 1360 1361 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1362 if (xfer != NULL) { 1363 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1364 #ifdef DIAGNOSTIC 1365 if (xfer->busy_free != XFER_FREE) { 1366 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1367 xfer->busy_free); 1368 } 1369 #endif 1370 } else { 1371 xfer = kmem_alloc(sizeof(struct ehci_xfer), KM_SLEEP); 1372 } 1373 if (xfer != NULL) { 1374 memset(xfer, 0, sizeof(struct ehci_xfer)); 1375 #ifdef DIAGNOSTIC 1376 EXFER(xfer)->isdone = 1; 1377 xfer->busy_free = XFER_BUSY; 1378 #endif 1379 } 1380 return (xfer); 1381 } 1382 1383 Static void 1384 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1385 { 1386 struct ehci_softc *sc = bus->hci_private; 1387 1388 #ifdef DIAGNOSTIC 1389 if (xfer->busy_free != XFER_BUSY) { 1390 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1391 xfer->busy_free); 1392 } 1393 xfer->busy_free = XFER_FREE; 1394 if (!EXFER(xfer)->isdone) { 1395 printf("ehci_freex: !isdone\n"); 1396 } 1397 #endif 1398 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1399 } 1400 1401 Static void 1402 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1403 { 1404 struct ehci_softc *sc = bus->hci_private; 1405 1406 *lock = &sc->sc_lock; 1407 } 1408 1409 Static void 1410 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1411 { 1412 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1413 1414 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1415 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1416 #ifdef EHCI_DEBUG 1417 if (ehcidebug) 1418 usbd_dump_pipe(pipe); 1419 #endif 1420 epipe->nexttoggle = 0; 1421 } 1422 1423 Static void 1424 ehci_noop(usbd_pipe_handle pipe) 1425 { 1426 } 1427 1428 #ifdef EHCI_DEBUG 1429 Static void 1430 ehci_dump_regs(ehci_softc_t *sc) 1431 { 1432 int i; 1433 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1434 EOREAD4(sc, EHCI_USBCMD), 1435 EOREAD4(sc, EHCI_USBSTS), 1436 EOREAD4(sc, EHCI_USBINTR)); 1437 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1438 EOREAD4(sc, EHCI_FRINDEX), 1439 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1440 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1441 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1442 for (i = 1; i <= sc->sc_noport; i++) 1443 printf("port %d status=0x%08x\n", i, 1444 EOREAD4(sc, EHCI_PORTSC(i))); 1445 } 1446 1447 /* 1448 * Unused function - this is meant to be called from a kernel 1449 * debugger. 1450 */ 1451 void 1452 ehci_dump(void) 1453 { 1454 ehci_dump_regs(theehci); 1455 } 1456 1457 Static void 1458 ehci_dump_link(ehci_link_t link, int type) 1459 { 1460 link = le32toh(link); 1461 printf("0x%08x", link); 1462 if (link & EHCI_LINK_TERMINATE) 1463 printf("<T>"); 1464 else { 1465 printf("<"); 1466 if (type) { 1467 switch (EHCI_LINK_TYPE(link)) { 1468 case EHCI_LINK_ITD: printf("ITD"); break; 1469 case EHCI_LINK_QH: printf("QH"); break; 1470 case EHCI_LINK_SITD: printf("SITD"); break; 1471 case EHCI_LINK_FSTN: printf("FSTN"); break; 1472 } 1473 } 1474 printf(">"); 1475 } 1476 } 1477 1478 Static void 1479 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1480 { 1481 int i; 1482 u_int32_t stop; 1483 1484 stop = 0; 1485 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1486 ehci_dump_sqtd(sqtd); 1487 usb_syncmem(&sqtd->dma, 1488 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1489 sizeof(sqtd->qtd), 1490 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1491 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1492 usb_syncmem(&sqtd->dma, 1493 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1494 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1495 } 1496 if (sqtd) 1497 printf("dump aborted, too many TDs\n"); 1498 } 1499 1500 Static void 1501 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1502 { 1503 usb_syncmem(&sqtd->dma, sqtd->offs, 1504 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1505 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1506 ehci_dump_qtd(&sqtd->qtd); 1507 usb_syncmem(&sqtd->dma, sqtd->offs, 1508 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1509 } 1510 1511 Static void 1512 ehci_dump_qtd(ehci_qtd_t *qtd) 1513 { 1514 u_int32_t s; 1515 char sbuf[128]; 1516 1517 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1518 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1519 printf("\n"); 1520 s = le32toh(qtd->qtd_status); 1521 snprintb(sbuf, sizeof(sbuf), 1522 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1523 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1524 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1525 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1526 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1527 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1528 EHCI_QTD_GET_PID(s), sbuf); 1529 for (s = 0; s < 5; s++) 1530 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1531 } 1532 1533 Static void 1534 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1535 { 1536 ehci_qh_t *qh = &sqh->qh; 1537 u_int32_t endp, endphub; 1538 1539 usb_syncmem(&sqh->dma, sqh->offs, 1540 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1541 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1542 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1543 endp = le32toh(qh->qh_endp); 1544 printf(" endp=0x%08x\n", endp); 1545 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1546 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1547 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1548 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1549 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1550 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1551 EHCI_QH_GET_NRL(endp)); 1552 endphub = le32toh(qh->qh_endphub); 1553 printf(" endphub=0x%08x\n", endphub); 1554 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1555 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1556 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1557 EHCI_QH_GET_MULT(endphub)); 1558 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1559 printf("Overlay qTD:\n"); 1560 ehci_dump_qtd(&qh->qh_qtd); 1561 usb_syncmem(&sqh->dma, sqh->offs, 1562 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1563 } 1564 1565 #if notyet 1566 Static void 1567 ehci_dump_itd(struct ehci_soft_itd *itd) 1568 { 1569 ehci_isoc_trans_t t; 1570 ehci_isoc_bufr_ptr_t b, b2, b3; 1571 int i; 1572 1573 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1574 1575 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1576 t = le32toh(itd->itd.itd_ctl[i]); 1577 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1578 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1579 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1580 EHCI_ITD_GET_OFFS(t)); 1581 } 1582 printf("ITDbufr: "); 1583 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1584 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1585 1586 b = le32toh(itd->itd.itd_bufr[0]); 1587 b2 = le32toh(itd->itd.itd_bufr[1]); 1588 b3 = le32toh(itd->itd.itd_bufr[2]); 1589 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1590 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1591 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1592 } 1593 1594 Static void 1595 ehci_dump_sitd(struct ehci_soft_itd *itd) 1596 { 1597 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1598 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1599 itd->xfer_next, itd->physaddr, itd->slot); 1600 } 1601 #endif 1602 1603 #ifdef DIAGNOSTIC 1604 Static void 1605 ehci_dump_exfer(struct ehci_xfer *ex) 1606 { 1607 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1608 } 1609 #endif 1610 #endif 1611 1612 Static usbd_status 1613 ehci_open(usbd_pipe_handle pipe) 1614 { 1615 usbd_device_handle dev = pipe->device; 1616 ehci_softc_t *sc = dev->bus->hci_private; 1617 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1618 u_int8_t addr = dev->address; 1619 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1620 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1621 ehci_soft_qh_t *sqh; 1622 usbd_status err; 1623 int ival, speed, naks; 1624 int hshubaddr, hshubport; 1625 1626 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1627 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1628 1629 if (dev->myhsport) { 1630 /* 1631 * When directly attached FS/LS device while doing embedded 1632 * transaction translations and we are the hub, set the hub 1633 * adddress to 0 (us). 1634 */ 1635 if (!(sc->sc_flags & EHCIF_ETTF) 1636 || (dev->myhsport->parent->address != sc->sc_addr)) { 1637 hshubaddr = dev->myhsport->parent->address; 1638 } else { 1639 hshubaddr = 0; 1640 } 1641 hshubport = dev->myhsport->portno; 1642 } else { 1643 hshubaddr = 0; 1644 hshubport = 0; 1645 } 1646 1647 if (sc->sc_dying) 1648 return (USBD_IOERROR); 1649 1650 /* toggle state needed for bulk endpoints */ 1651 epipe->nexttoggle = pipe->endpoint->datatoggle; 1652 1653 if (addr == sc->sc_addr) { 1654 switch (ed->bEndpointAddress) { 1655 case USB_CONTROL_ENDPOINT: 1656 pipe->methods = &ehci_root_ctrl_methods; 1657 break; 1658 case UE_DIR_IN | EHCI_INTR_ENDPT: 1659 pipe->methods = &ehci_root_intr_methods; 1660 break; 1661 default: 1662 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1663 ed->bEndpointAddress)); 1664 return (USBD_INVAL); 1665 } 1666 return (USBD_NORMAL_COMPLETION); 1667 } 1668 1669 /* XXX All this stuff is only valid for async. */ 1670 switch (dev->speed) { 1671 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1672 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1673 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1674 default: panic("ehci_open: bad device speed %d", dev->speed); 1675 } 1676 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1677 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1678 "isoc endpoint.\n"); 1679 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1680 "attached to a USB2 hub, and transaction translations are " 1681 "not yet supported.\n"); 1682 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1683 "root hub instead.\n"); 1684 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1685 hshubaddr, hshubport)); 1686 return USBD_INVAL; 1687 } 1688 1689 /* 1690 * For interrupt transfer, nak throttling must be disabled, but for 1691 * the other transfer type, nak throttling should be enabled from the 1692 * veiwpoint that avoids the memory thrashing. 1693 */ 1694 naks = (xfertype == UE_INTERRUPT) ? 0 1695 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1696 1697 /* Allocate sqh for everything, save isoc xfers */ 1698 if (xfertype != UE_ISOCHRONOUS) { 1699 sqh = ehci_alloc_sqh(sc); 1700 if (sqh == NULL) 1701 return (USBD_NOMEM); 1702 /* qh_link filled when the QH is added */ 1703 sqh->qh.qh_endp = htole32( 1704 EHCI_QH_SET_ADDR(addr) | 1705 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1706 EHCI_QH_SET_EPS(speed) | 1707 EHCI_QH_DTC | 1708 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1709 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1710 EHCI_QH_CTL : 0) | 1711 EHCI_QH_SET_NRL(naks) 1712 ); 1713 sqh->qh.qh_endphub = htole32( 1714 EHCI_QH_SET_MULT(1) | 1715 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1716 ); 1717 if (speed != EHCI_QH_SPEED_HIGH) 1718 sqh->qh.qh_endphub |= htole32( 1719 EHCI_QH_SET_PORT(hshubport) | 1720 EHCI_QH_SET_HUBA(hshubaddr) | 1721 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1722 ); 1723 sqh->qh.qh_curqtd = EHCI_NULL; 1724 /* Fill the overlay qTD */ 1725 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1726 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1727 sqh->qh.qh_qtd.qtd_status = htole32(0); 1728 1729 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1730 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1731 epipe->sqh = sqh; 1732 } else { 1733 sqh = NULL; 1734 } /*xfertype == UE_ISOC*/ 1735 1736 switch (xfertype) { 1737 case UE_CONTROL: 1738 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1739 0, &epipe->u.ctl.reqdma); 1740 #ifdef EHCI_DEBUG 1741 if (err) 1742 printf("ehci_open: usb_allocmem()=%d\n", err); 1743 #endif 1744 if (err) 1745 goto bad; 1746 pipe->methods = &ehci_device_ctrl_methods; 1747 mutex_enter(&sc->sc_lock); 1748 ehci_add_qh(sc, sqh, sc->sc_async_head); 1749 mutex_exit(&sc->sc_lock); 1750 break; 1751 case UE_BULK: 1752 pipe->methods = &ehci_device_bulk_methods; 1753 mutex_enter(&sc->sc_lock); 1754 ehci_add_qh(sc, sqh, sc->sc_async_head); 1755 mutex_exit(&sc->sc_lock); 1756 break; 1757 case UE_INTERRUPT: 1758 pipe->methods = &ehci_device_intr_methods; 1759 ival = pipe->interval; 1760 if (ival == USBD_DEFAULT_INTERVAL) { 1761 if (speed == EHCI_QH_SPEED_HIGH) { 1762 if (ed->bInterval > 16) { 1763 /* 1764 * illegal with high-speed, but there 1765 * were documentation bugs in the spec, 1766 * so be generous 1767 */ 1768 ival = 256; 1769 } else 1770 ival = (1 << (ed->bInterval - 1)) / 8; 1771 } else 1772 ival = ed->bInterval; 1773 } 1774 err = ehci_device_setintr(sc, sqh, ival); 1775 if (err) 1776 goto bad; 1777 break; 1778 case UE_ISOCHRONOUS: 1779 pipe->methods = &ehci_device_isoc_methods; 1780 if (ed->bInterval == 0 || ed->bInterval > 16) { 1781 printf("ehci: opening pipe with invalid bInterval\n"); 1782 err = USBD_INVAL; 1783 goto bad; 1784 } 1785 if (UGETW(ed->wMaxPacketSize) == 0) { 1786 printf("ehci: zero length endpoint open request\n"); 1787 err = USBD_INVAL; 1788 goto bad; 1789 } 1790 epipe->u.isoc.next_frame = 0; 1791 epipe->u.isoc.cur_xfers = 0; 1792 break; 1793 default: 1794 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1795 err = USBD_INVAL; 1796 goto bad; 1797 } 1798 return (USBD_NORMAL_COMPLETION); 1799 1800 bad: 1801 if (sqh != NULL) 1802 ehci_free_sqh(sc, sqh); 1803 return (err); 1804 } 1805 1806 /* 1807 * Add an ED to the schedule. Called with USB lock held. 1808 */ 1809 Static void 1810 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1811 { 1812 1813 KASSERT(mutex_owned(&sc->sc_lock)); 1814 1815 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1816 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1817 sqh->next = head->next; 1818 sqh->qh.qh_link = head->qh.qh_link; 1819 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1820 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1821 head->next = sqh; 1822 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1823 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1824 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1825 1826 #ifdef EHCI_DEBUG 1827 if (ehcidebug > 5) { 1828 printf("ehci_add_qh:\n"); 1829 ehci_dump_sqh(sqh); 1830 } 1831 #endif 1832 } 1833 1834 /* 1835 * Remove an ED from the schedule. Called with USB lock held. 1836 */ 1837 Static void 1838 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1839 { 1840 ehci_soft_qh_t *p; 1841 1842 KASSERT(mutex_owned(&sc->sc_lock)); 1843 1844 /* XXX */ 1845 for (p = head; p != NULL && p->next != sqh; p = p->next) 1846 ; 1847 if (p == NULL) 1848 panic("ehci_rem_qh: ED not found"); 1849 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1850 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1851 p->next = sqh->next; 1852 p->qh.qh_link = sqh->qh.qh_link; 1853 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1854 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1855 1856 ehci_sync_hc(sc); 1857 } 1858 1859 Static void 1860 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1861 { 1862 int i; 1863 u_int32_t status; 1864 1865 /* Save toggle bit and ping status. */ 1866 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1867 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1868 status = sqh->qh.qh_qtd.qtd_status & 1869 htole32(EHCI_QTD_TOGGLE_MASK | 1870 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1871 /* Set HALTED to make hw leave it alone. */ 1872 sqh->qh.qh_qtd.qtd_status = 1873 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1874 usb_syncmem(&sqh->dma, 1875 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1876 sizeof(sqh->qh.qh_qtd.qtd_status), 1877 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1878 sqh->qh.qh_curqtd = 0; 1879 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1880 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1881 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1882 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1883 sqh->sqtd = sqtd; 1884 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1885 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1886 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1887 sqh->qh.qh_qtd.qtd_status = status; 1888 usb_syncmem(&sqh->dma, 1889 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1890 sizeof(sqh->qh.qh_qtd.qtd_status), 1891 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1892 } 1893 1894 /* 1895 * Ensure that the HC has released all references to the QH. We do this 1896 * by asking for a Async Advance Doorbell interrupt and then we wait for 1897 * the interrupt. 1898 * To make this easier we first obtain exclusive use of the doorbell. 1899 */ 1900 Static void 1901 ehci_sync_hc(ehci_softc_t *sc) 1902 { 1903 int error; 1904 1905 KASSERT(mutex_owned(&sc->sc_lock)); 1906 1907 if (sc->sc_dying) { 1908 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1909 return; 1910 } 1911 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1912 /* ask for doorbell */ 1913 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1914 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1915 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1916 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 1917 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1918 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1919 #ifdef DIAGNOSTIC 1920 if (error) 1921 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 1922 #endif 1923 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1924 } 1925 1926 Static void 1927 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1928 { 1929 struct ehci_soft_itd *itd, *prev; 1930 1931 prev = NULL; 1932 1933 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1934 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1935 1936 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1937 prev = itd->u.frame_list.prev; 1938 /* Unlink itd from hardware chain, or frame array */ 1939 if (prev == NULL) { /* We're at the table head */ 1940 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1941 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1942 usb_syncmem(&sc->sc_fldma, 1943 sizeof(ehci_link_t) * itd->slot, 1944 sizeof(ehci_link_t), 1945 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1946 1947 if (itd->u.frame_list.next != NULL) 1948 itd->u.frame_list.next->u.frame_list.prev = NULL; 1949 } else { 1950 /* XXX this part is untested... */ 1951 prev->itd.itd_next = itd->itd.itd_next; 1952 usb_syncmem(&itd->dma, 1953 itd->offs + offsetof(ehci_itd_t, itd_next), 1954 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1955 1956 prev->u.frame_list.next = itd->u.frame_list.next; 1957 if (itd->u.frame_list.next != NULL) 1958 itd->u.frame_list.next->u.frame_list.prev = prev; 1959 } 1960 } 1961 1962 prev = NULL; 1963 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1964 if (prev != NULL) 1965 ehci_free_itd(sc, prev); 1966 prev = itd; 1967 } 1968 if (prev) 1969 ehci_free_itd(sc, prev); 1970 exfer->itdstart = NULL; 1971 exfer->itdend = NULL; 1972 } 1973 1974 /***********/ 1975 1976 /* 1977 * Data structures and routines to emulate the root hub. 1978 */ 1979 Static usb_device_descriptor_t ehci_devd = { 1980 USB_DEVICE_DESCRIPTOR_SIZE, 1981 UDESC_DEVICE, /* type */ 1982 {0x00, 0x02}, /* USB version */ 1983 UDCLASS_HUB, /* class */ 1984 UDSUBCLASS_HUB, /* subclass */ 1985 UDPROTO_HSHUBSTT, /* protocol */ 1986 64, /* max packet */ 1987 {0},{0},{0x00,0x01}, /* device id */ 1988 1,2,0, /* string indicies */ 1989 1 /* # of configurations */ 1990 }; 1991 1992 Static const usb_device_qualifier_t ehci_odevd = { 1993 USB_DEVICE_DESCRIPTOR_SIZE, 1994 UDESC_DEVICE_QUALIFIER, /* type */ 1995 {0x00, 0x02}, /* USB version */ 1996 UDCLASS_HUB, /* class */ 1997 UDSUBCLASS_HUB, /* subclass */ 1998 UDPROTO_FSHUB, /* protocol */ 1999 64, /* max packet */ 2000 1, /* # of configurations */ 2001 0 2002 }; 2003 2004 Static const usb_config_descriptor_t ehci_confd = { 2005 USB_CONFIG_DESCRIPTOR_SIZE, 2006 UDESC_CONFIG, 2007 {USB_CONFIG_DESCRIPTOR_SIZE + 2008 USB_INTERFACE_DESCRIPTOR_SIZE + 2009 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2010 1, 2011 1, 2012 0, 2013 UC_ATTR_MBO | UC_SELF_POWERED, 2014 0 /* max power */ 2015 }; 2016 2017 Static const usb_interface_descriptor_t ehci_ifcd = { 2018 USB_INTERFACE_DESCRIPTOR_SIZE, 2019 UDESC_INTERFACE, 2020 0, 2021 0, 2022 1, 2023 UICLASS_HUB, 2024 UISUBCLASS_HUB, 2025 UIPROTO_HSHUBSTT, 2026 0 2027 }; 2028 2029 Static const usb_endpoint_descriptor_t ehci_endpd = { 2030 USB_ENDPOINT_DESCRIPTOR_SIZE, 2031 UDESC_ENDPOINT, 2032 UE_DIR_IN | EHCI_INTR_ENDPT, 2033 UE_INTERRUPT, 2034 {8, 0}, /* max packet */ 2035 12 2036 }; 2037 2038 Static const usb_hub_descriptor_t ehci_hubd = { 2039 USB_HUB_DESCRIPTOR_SIZE, 2040 UDESC_HUB, 2041 0, 2042 {0,0}, 2043 0, 2044 0, 2045 {""}, 2046 {""}, 2047 }; 2048 2049 /* 2050 * Simulate a hardware hub by handling all the necessary requests. 2051 */ 2052 Static usbd_status 2053 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2054 { 2055 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2056 usbd_status err; 2057 2058 /* Insert last in queue. */ 2059 mutex_enter(&sc->sc_lock); 2060 err = usb_insert_transfer(xfer); 2061 mutex_exit(&sc->sc_lock); 2062 if (err) 2063 return (err); 2064 2065 /* Pipe isn't running, start first */ 2066 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2067 } 2068 2069 Static usbd_status 2070 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2071 { 2072 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2073 usb_device_request_t *req; 2074 void *buf = NULL; 2075 int port, i; 2076 int len, value, index, l, totlen = 0; 2077 usb_port_status_t ps; 2078 usb_hub_descriptor_t hubd; 2079 usbd_status err; 2080 u_int32_t v; 2081 2082 if (sc->sc_dying) 2083 return (USBD_IOERROR); 2084 2085 #ifdef DIAGNOSTIC 2086 if (!(xfer->rqflags & URQ_REQUEST)) 2087 /* XXX panic */ 2088 return (USBD_INVAL); 2089 #endif 2090 req = &xfer->request; 2091 2092 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2093 req->bmRequestType, req->bRequest)); 2094 2095 len = UGETW(req->wLength); 2096 value = UGETW(req->wValue); 2097 index = UGETW(req->wIndex); 2098 2099 if (len != 0) 2100 buf = KERNADDR(&xfer->dmabuf, 0); 2101 2102 #define C(x,y) ((x) | ((y) << 8)) 2103 switch(C(req->bRequest, req->bmRequestType)) { 2104 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2105 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2106 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2107 /* 2108 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2109 * for the integrated root hub. 2110 */ 2111 break; 2112 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2113 if (len > 0) { 2114 *(u_int8_t *)buf = sc->sc_conf; 2115 totlen = 1; 2116 } 2117 break; 2118 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2119 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2120 if (len == 0) 2121 break; 2122 switch(value >> 8) { 2123 case UDESC_DEVICE: 2124 if ((value & 0xff) != 0) { 2125 err = USBD_IOERROR; 2126 goto ret; 2127 } 2128 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2129 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2130 memcpy(buf, &ehci_devd, l); 2131 break; 2132 /* 2133 * We can't really operate at another speed, but the spec says 2134 * we need this descriptor. 2135 */ 2136 case UDESC_DEVICE_QUALIFIER: 2137 if ((value & 0xff) != 0) { 2138 err = USBD_IOERROR; 2139 goto ret; 2140 } 2141 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2142 memcpy(buf, &ehci_odevd, l); 2143 break; 2144 /* 2145 * We can't really operate at another speed, but the spec says 2146 * we need this descriptor. 2147 */ 2148 case UDESC_OTHER_SPEED_CONFIGURATION: 2149 case UDESC_CONFIG: 2150 if ((value & 0xff) != 0) { 2151 err = USBD_IOERROR; 2152 goto ret; 2153 } 2154 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2155 memcpy(buf, &ehci_confd, l); 2156 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2157 value >> 8; 2158 buf = (char *)buf + l; 2159 len -= l; 2160 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2161 totlen += l; 2162 memcpy(buf, &ehci_ifcd, l); 2163 buf = (char *)buf + l; 2164 len -= l; 2165 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2166 totlen += l; 2167 memcpy(buf, &ehci_endpd, l); 2168 break; 2169 case UDESC_STRING: 2170 #define sd ((usb_string_descriptor_t *)buf) 2171 switch (value & 0xff) { 2172 case 0: /* Language table */ 2173 totlen = usb_makelangtbl(sd, len); 2174 break; 2175 case 1: /* Vendor */ 2176 totlen = usb_makestrdesc(sd, len, 2177 sc->sc_vendor); 2178 break; 2179 case 2: /* Product */ 2180 totlen = usb_makestrdesc(sd, len, 2181 "EHCI root hub"); 2182 break; 2183 } 2184 #undef sd 2185 break; 2186 default: 2187 err = USBD_IOERROR; 2188 goto ret; 2189 } 2190 break; 2191 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2192 if (len > 0) { 2193 *(u_int8_t *)buf = 0; 2194 totlen = 1; 2195 } 2196 break; 2197 case C(UR_GET_STATUS, UT_READ_DEVICE): 2198 if (len > 1) { 2199 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2200 totlen = 2; 2201 } 2202 break; 2203 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2204 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2205 if (len > 1) { 2206 USETW(((usb_status_t *)buf)->wStatus, 0); 2207 totlen = 2; 2208 } 2209 break; 2210 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2211 if (value >= USB_MAX_DEVICES) { 2212 err = USBD_IOERROR; 2213 goto ret; 2214 } 2215 sc->sc_addr = value; 2216 break; 2217 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2218 if (value != 0 && value != 1) { 2219 err = USBD_IOERROR; 2220 goto ret; 2221 } 2222 sc->sc_conf = value; 2223 break; 2224 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2225 break; 2226 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2227 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2228 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2229 err = USBD_IOERROR; 2230 goto ret; 2231 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2232 break; 2233 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2234 break; 2235 /* Hub requests */ 2236 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2237 break; 2238 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2239 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2240 "port=%d feature=%d\n", 2241 index, value)); 2242 if (index < 1 || index > sc->sc_noport) { 2243 err = USBD_IOERROR; 2244 goto ret; 2245 } 2246 port = EHCI_PORTSC(index); 2247 v = EOREAD4(sc, port); 2248 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2249 v &= ~EHCI_PS_CLEAR; 2250 switch(value) { 2251 case UHF_PORT_ENABLE: 2252 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2253 break; 2254 case UHF_PORT_SUSPEND: 2255 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2256 break; 2257 v &= ~EHCI_PS_SUSP; 2258 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2259 /* see USB2 spec ch. 7.1.7.7 */ 2260 usb_delay_ms(&sc->sc_bus, 20); 2261 EOWRITE4(sc, port, v); 2262 usb_delay_ms(&sc->sc_bus, 2); 2263 #ifdef DEBUG 2264 v = EOREAD4(sc, port); 2265 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2266 printf("ehci: resume failed: %x\n", v); 2267 #endif 2268 break; 2269 case UHF_PORT_POWER: 2270 if (sc->sc_hasppc) 2271 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2272 break; 2273 case UHF_PORT_TEST: 2274 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2275 "%d\n", index)); 2276 break; 2277 case UHF_PORT_INDICATOR: 2278 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2279 "%d\n", index)); 2280 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2281 break; 2282 case UHF_C_PORT_CONNECTION: 2283 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2284 break; 2285 case UHF_C_PORT_ENABLE: 2286 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2287 break; 2288 case UHF_C_PORT_SUSPEND: 2289 /* how? */ 2290 break; 2291 case UHF_C_PORT_OVER_CURRENT: 2292 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2293 break; 2294 case UHF_C_PORT_RESET: 2295 sc->sc_isreset[index] = 0; 2296 break; 2297 default: 2298 err = USBD_IOERROR; 2299 goto ret; 2300 } 2301 #if 0 2302 switch(value) { 2303 case UHF_C_PORT_CONNECTION: 2304 case UHF_C_PORT_ENABLE: 2305 case UHF_C_PORT_SUSPEND: 2306 case UHF_C_PORT_OVER_CURRENT: 2307 case UHF_C_PORT_RESET: 2308 default: 2309 break; 2310 } 2311 #endif 2312 break; 2313 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2314 if (len == 0) 2315 break; 2316 if ((value & 0xff) != 0) { 2317 err = USBD_IOERROR; 2318 goto ret; 2319 } 2320 hubd = ehci_hubd; 2321 hubd.bNbrPorts = sc->sc_noport; 2322 v = EOREAD4(sc, EHCI_HCSPARAMS); 2323 USETW(hubd.wHubCharacteristics, 2324 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2325 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2326 ? UHD_PORT_IND : 0); 2327 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2328 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2329 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2330 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2331 l = min(len, hubd.bDescLength); 2332 totlen = l; 2333 memcpy(buf, &hubd, l); 2334 break; 2335 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2336 if (len != 4) { 2337 err = USBD_IOERROR; 2338 goto ret; 2339 } 2340 memset(buf, 0, len); /* ? XXX */ 2341 totlen = len; 2342 break; 2343 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2344 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2345 index)); 2346 if (index < 1 || index > sc->sc_noport) { 2347 err = USBD_IOERROR; 2348 goto ret; 2349 } 2350 if (len != 4) { 2351 err = USBD_IOERROR; 2352 goto ret; 2353 } 2354 v = EOREAD4(sc, EHCI_PORTSC(index)); 2355 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2356 2357 i = UPS_HIGH_SPEED; 2358 #if 0 2359 if (sc->sc_flags & EHCIF_ETTF) { 2360 /* 2361 * If we are doing embedded transaction translation, 2362 * then directly attached LS/FS devices are reset by 2363 * the EHCI controller itself. PSPD is encoded 2364 * the same way as in USBSTATUS. 2365 */ 2366 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2367 } 2368 #endif 2369 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2370 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2371 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2372 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2373 if (v & EHCI_PS_PR) i |= UPS_RESET; 2374 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2375 if (sc->sc_vendor_port_status) 2376 i = sc->sc_vendor_port_status(sc, v, i); 2377 USETW(ps.wPortStatus, i); 2378 i = 0; 2379 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2380 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2381 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2382 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2383 USETW(ps.wPortChange, i); 2384 l = min(len, sizeof ps); 2385 memcpy(buf, &ps, l); 2386 totlen = l; 2387 break; 2388 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2389 err = USBD_IOERROR; 2390 goto ret; 2391 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2392 break; 2393 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2394 if (index < 1 || index > sc->sc_noport) { 2395 err = USBD_IOERROR; 2396 goto ret; 2397 } 2398 port = EHCI_PORTSC(index); 2399 v = EOREAD4(sc, port); 2400 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2401 v &= ~EHCI_PS_CLEAR; 2402 switch(value) { 2403 case UHF_PORT_ENABLE: 2404 EOWRITE4(sc, port, v | EHCI_PS_PE); 2405 break; 2406 case UHF_PORT_SUSPEND: 2407 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2408 break; 2409 case UHF_PORT_RESET: 2410 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2411 index)); 2412 if (EHCI_PS_IS_LOWSPEED(v) 2413 && sc->sc_ncomp > 0 2414 && !(sc->sc_flags & EHCIF_ETTF)) { 2415 /* 2416 * Low speed device on non-ETTF controller or 2417 * unaccompanied controller, give up ownership. 2418 */ 2419 ehci_disown(sc, index, 1); 2420 break; 2421 } 2422 /* Start reset sequence. */ 2423 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2424 EOWRITE4(sc, port, v | EHCI_PS_PR); 2425 /* Wait for reset to complete. */ 2426 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2427 if (sc->sc_dying) { 2428 err = USBD_IOERROR; 2429 goto ret; 2430 } 2431 /* 2432 * An embedded transaction translater will automatically 2433 * terminate the reset sequence so there's no need to 2434 * it. 2435 */ 2436 v = EOREAD4(sc, port); 2437 if (v & EHCI_PS_PR) { 2438 /* Terminate reset sequence. */ 2439 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2440 /* Wait for HC to complete reset. */ 2441 usb_delay_ms(&sc->sc_bus, 2442 EHCI_PORT_RESET_COMPLETE); 2443 if (sc->sc_dying) { 2444 err = USBD_IOERROR; 2445 goto ret; 2446 } 2447 } 2448 2449 v = EOREAD4(sc, port); 2450 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2451 if (v & EHCI_PS_PR) { 2452 printf("%s: port reset timeout\n", 2453 device_xname(sc->sc_dev)); 2454 return (USBD_TIMEOUT); 2455 } 2456 if (!(v & EHCI_PS_PE)) { 2457 /* Not a high speed device, give up ownership.*/ 2458 ehci_disown(sc, index, 0); 2459 break; 2460 } 2461 sc->sc_isreset[index] = 1; 2462 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2463 index, v)); 2464 break; 2465 case UHF_PORT_POWER: 2466 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2467 "%d (has PPC = %d)\n", index, 2468 sc->sc_hasppc)); 2469 if (sc->sc_hasppc) 2470 EOWRITE4(sc, port, v | EHCI_PS_PP); 2471 break; 2472 case UHF_PORT_TEST: 2473 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2474 "%d\n", index)); 2475 break; 2476 case UHF_PORT_INDICATOR: 2477 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2478 "%d\n", index)); 2479 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2480 break; 2481 default: 2482 err = USBD_IOERROR; 2483 goto ret; 2484 } 2485 break; 2486 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2487 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2488 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2489 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2490 break; 2491 default: 2492 err = USBD_IOERROR; 2493 goto ret; 2494 } 2495 xfer->actlen = totlen; 2496 err = USBD_NORMAL_COMPLETION; 2497 ret: 2498 mutex_enter(&sc->sc_lock); 2499 xfer->status = err; 2500 usb_transfer_complete(xfer); 2501 mutex_exit(&sc->sc_lock); 2502 return (USBD_IN_PROGRESS); 2503 } 2504 2505 Static void 2506 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2507 { 2508 int port; 2509 u_int32_t v; 2510 2511 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2512 #ifdef DIAGNOSTIC 2513 if (sc->sc_npcomp != 0) { 2514 int i = (index-1) / sc->sc_npcomp; 2515 if (i >= sc->sc_ncomp) 2516 printf("%s: strange port\n", 2517 device_xname(sc->sc_dev)); 2518 else 2519 printf("%s: handing over %s speed device on " 2520 "port %d to %s\n", 2521 device_xname(sc->sc_dev), 2522 lowspeed ? "low" : "full", 2523 index, device_xname(sc->sc_comps[i])); 2524 } else { 2525 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2526 } 2527 #endif 2528 port = EHCI_PORTSC(index); 2529 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2530 EOWRITE4(sc, port, v | EHCI_PS_PO); 2531 } 2532 2533 /* Abort a root control request. */ 2534 Static void 2535 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2536 { 2537 /* Nothing to do, all transfers are synchronous. */ 2538 } 2539 2540 /* Close the root pipe. */ 2541 Static void 2542 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2543 { 2544 DPRINTF(("ehci_root_ctrl_close\n")); 2545 /* Nothing to do. */ 2546 } 2547 2548 Static void 2549 ehci_root_intr_done(usbd_xfer_handle xfer) 2550 { 2551 xfer->hcpriv = NULL; 2552 } 2553 2554 Static usbd_status 2555 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2556 { 2557 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2558 usbd_status err; 2559 2560 /* Insert last in queue. */ 2561 mutex_enter(&sc->sc_lock); 2562 err = usb_insert_transfer(xfer); 2563 mutex_exit(&sc->sc_lock); 2564 if (err) 2565 return (err); 2566 2567 /* Pipe isn't running, start first */ 2568 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2569 } 2570 2571 Static usbd_status 2572 ehci_root_intr_start(usbd_xfer_handle xfer) 2573 { 2574 usbd_pipe_handle pipe = xfer->pipe; 2575 ehci_softc_t *sc = pipe->device->bus->hci_private; 2576 2577 if (sc->sc_dying) 2578 return (USBD_IOERROR); 2579 2580 mutex_enter(&sc->sc_lock); 2581 sc->sc_intrxfer = xfer; 2582 mutex_exit(&sc->sc_lock); 2583 2584 return (USBD_IN_PROGRESS); 2585 } 2586 2587 /* Abort a root interrupt request. */ 2588 Static void 2589 ehci_root_intr_abort(usbd_xfer_handle xfer) 2590 { 2591 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2592 2593 KASSERT(mutex_owned(&sc->sc_lock)); 2594 if (xfer->pipe->intrxfer == xfer) { 2595 DPRINTF(("ehci_root_intr_abort: remove\n")); 2596 xfer->pipe->intrxfer = NULL; 2597 } 2598 xfer->status = USBD_CANCELLED; 2599 usb_transfer_complete(xfer); 2600 } 2601 2602 /* Close the root pipe. */ 2603 Static void 2604 ehci_root_intr_close(usbd_pipe_handle pipe) 2605 { 2606 ehci_softc_t *sc = pipe->device->bus->hci_private; 2607 2608 KASSERT(mutex_owned(&sc->sc_lock)); 2609 2610 DPRINTF(("ehci_root_intr_close\n")); 2611 2612 sc->sc_intrxfer = NULL; 2613 } 2614 2615 Static void 2616 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2617 { 2618 xfer->hcpriv = NULL; 2619 } 2620 2621 /************************/ 2622 2623 Static ehci_soft_qh_t * 2624 ehci_alloc_sqh(ehci_softc_t *sc) 2625 { 2626 ehci_soft_qh_t *sqh; 2627 usbd_status err; 2628 int i, offs; 2629 usb_dma_t dma; 2630 2631 if (sc->sc_freeqhs == NULL) { 2632 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2633 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2634 EHCI_PAGE_SIZE, &dma); 2635 #ifdef EHCI_DEBUG 2636 if (err) 2637 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2638 #endif 2639 if (err) 2640 return (NULL); 2641 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2642 offs = i * EHCI_SQH_SIZE; 2643 sqh = KERNADDR(&dma, offs); 2644 sqh->physaddr = DMAADDR(&dma, offs); 2645 sqh->dma = dma; 2646 sqh->offs = offs; 2647 sqh->next = sc->sc_freeqhs; 2648 sc->sc_freeqhs = sqh; 2649 } 2650 } 2651 sqh = sc->sc_freeqhs; 2652 sc->sc_freeqhs = sqh->next; 2653 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2654 sqh->next = NULL; 2655 return (sqh); 2656 } 2657 2658 Static void 2659 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2660 { 2661 sqh->next = sc->sc_freeqhs; 2662 sc->sc_freeqhs = sqh; 2663 } 2664 2665 Static ehci_soft_qtd_t * 2666 ehci_alloc_sqtd(ehci_softc_t *sc) 2667 { 2668 ehci_soft_qtd_t *sqtd = NULL; 2669 usbd_status err; 2670 int i, offs; 2671 usb_dma_t dma; 2672 2673 if (sc->sc_freeqtds == NULL) { 2674 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2675 2676 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2677 EHCI_PAGE_SIZE, &dma); 2678 #ifdef EHCI_DEBUG 2679 if (err) 2680 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2681 #endif 2682 if (err) 2683 goto done; 2684 2685 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2686 offs = i * EHCI_SQTD_SIZE; 2687 sqtd = KERNADDR(&dma, offs); 2688 sqtd->physaddr = DMAADDR(&dma, offs); 2689 sqtd->dma = dma; 2690 sqtd->offs = offs; 2691 2692 sqtd->nextqtd = sc->sc_freeqtds; 2693 sc->sc_freeqtds = sqtd; 2694 } 2695 } 2696 2697 sqtd = sc->sc_freeqtds; 2698 sc->sc_freeqtds = sqtd->nextqtd; 2699 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2700 sqtd->nextqtd = NULL; 2701 sqtd->xfer = NULL; 2702 2703 done: 2704 return (sqtd); 2705 } 2706 2707 Static void 2708 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2709 { 2710 2711 KASSERT(mutex_owned(&sc->sc_lock)); 2712 2713 sqtd->nextqtd = sc->sc_freeqtds; 2714 sc->sc_freeqtds = sqtd; 2715 } 2716 2717 Static usbd_status 2718 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2719 int alen, int rd, usbd_xfer_handle xfer, 2720 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2721 { 2722 ehci_soft_qtd_t *next, *cur; 2723 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2724 u_int32_t qtdstatus; 2725 int len, curlen, mps; 2726 int i, tog; 2727 usb_dma_t *dma = &xfer->dmabuf; 2728 u_int16_t flags = xfer->flags; 2729 2730 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2731 2732 len = alen; 2733 dataphys = DMAADDR(dma, 0); 2734 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2735 qtdstatus = EHCI_QTD_ACTIVE | 2736 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2737 EHCI_QTD_SET_CERR(3) 2738 /* IOC set below */ 2739 /* BYTES set below */ 2740 ; 2741 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2742 tog = epipe->nexttoggle; 2743 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2744 2745 cur = ehci_alloc_sqtd(sc); 2746 *sp = cur; 2747 if (cur == NULL) 2748 goto nomem; 2749 2750 usb_syncmem(dma, 0, alen, 2751 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2752 for (;;) { 2753 dataphyspage = EHCI_PAGE(dataphys); 2754 /* The EHCI hardware can handle at most 5 pages. */ 2755 if (dataphyslastpage - dataphyspage < 2756 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2757 /* we can handle it in this QTD */ 2758 curlen = len; 2759 } else { 2760 /* must use multiple TDs, fill as much as possible. */ 2761 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2762 EHCI_PAGE_OFFSET(dataphys); 2763 #ifdef DIAGNOSTIC 2764 if (curlen > len) { 2765 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2766 "len=0x%x offs=0x%x\n", curlen, len, 2767 EHCI_PAGE_OFFSET(dataphys)); 2768 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2769 dataphyslastpage, dataphyspage, 2770 dataphys); 2771 curlen = len; 2772 } 2773 #endif 2774 /* the length must be a multiple of the max size */ 2775 curlen -= curlen % mps; 2776 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2777 "curlen=%d\n", curlen)); 2778 #ifdef DIAGNOSTIC 2779 if (curlen == 0) 2780 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2781 #endif 2782 } 2783 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2784 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2785 dataphys, dataphyslastpage, 2786 len, curlen)); 2787 len -= curlen; 2788 2789 /* 2790 * Allocate another transfer if there's more data left, 2791 * or if force last short transfer flag is set and we're 2792 * allocating a multiple of the max packet size. 2793 */ 2794 if (len != 0 || 2795 ((curlen % mps) == 0 && !rd && curlen != 0 && 2796 (flags & USBD_FORCE_SHORT_XFER))) { 2797 next = ehci_alloc_sqtd(sc); 2798 if (next == NULL) 2799 goto nomem; 2800 nextphys = htole32(next->physaddr); 2801 } else { 2802 next = NULL; 2803 nextphys = EHCI_NULL; 2804 } 2805 2806 for (i = 0; i * EHCI_PAGE_SIZE < 2807 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2808 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2809 if (i != 0) /* use offset only in first buffer */ 2810 a = EHCI_PAGE(a); 2811 cur->qtd.qtd_buffer[i] = htole32(a); 2812 cur->qtd.qtd_buffer_hi[i] = 0; 2813 #ifdef DIAGNOSTIC 2814 if (i >= EHCI_QTD_NBUFFERS) { 2815 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2816 goto nomem; 2817 } 2818 #endif 2819 } 2820 cur->nextqtd = next; 2821 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2822 cur->qtd.qtd_status = 2823 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2824 cur->xfer = xfer; 2825 cur->len = curlen; 2826 2827 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2828 dataphys, dataphys + curlen)); 2829 /* adjust the toggle based on the number of packets in this 2830 qtd */ 2831 if (((curlen + mps - 1) / mps) & 1) { 2832 tog ^= 1; 2833 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2834 } 2835 if (next == NULL) 2836 break; 2837 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2838 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2839 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2840 if (len) 2841 dataphys += curlen; 2842 cur = next; 2843 } 2844 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2845 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2846 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2847 *ep = cur; 2848 epipe->nexttoggle = tog; 2849 2850 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2851 *sp, *ep)); 2852 2853 return (USBD_NORMAL_COMPLETION); 2854 2855 nomem: 2856 /* XXX free chain */ 2857 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2858 return (USBD_NOMEM); 2859 } 2860 2861 Static void 2862 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2863 ehci_soft_qtd_t *sqtdend) 2864 { 2865 ehci_soft_qtd_t *p; 2866 int i; 2867 2868 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2869 sqtd, sqtdend)); 2870 2871 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2872 p = sqtd->nextqtd; 2873 ehci_free_sqtd(sc, sqtd); 2874 } 2875 } 2876 2877 Static ehci_soft_itd_t * 2878 ehci_alloc_itd(ehci_softc_t *sc) 2879 { 2880 struct ehci_soft_itd *itd, *freeitd; 2881 usbd_status err; 2882 int i, s, offs, frindex, previndex; 2883 usb_dma_t dma; 2884 2885 KASSERT(mutex_owned(&sc->sc_lock)); 2886 2887 /* Find an itd that wasn't freed this frame or last frame. This can 2888 * discard itds that were freed before frindex wrapped around 2889 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2890 * interrupt and fiddling with list when that happens */ 2891 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2892 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2893 2894 freeitd = NULL; 2895 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2896 if (itd == NULL) 2897 break; 2898 if (itd->slot != frindex && itd->slot != previndex) { 2899 freeitd = itd; 2900 break; 2901 } 2902 } 2903 2904 if (freeitd == NULL) { 2905 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2906 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2907 EHCI_PAGE_SIZE, &dma); 2908 2909 if (err) { 2910 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2911 return NULL; 2912 } 2913 2914 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2915 offs = i * EHCI_ITD_SIZE; 2916 itd = KERNADDR(&dma, offs); 2917 itd->physaddr = DMAADDR(&dma, offs); 2918 itd->dma = dma; 2919 itd->offs = offs; 2920 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2921 } 2922 freeitd = LIST_FIRST(&sc->sc_freeitds); 2923 } 2924 2925 itd = freeitd; 2926 LIST_REMOVE(itd, u.free_list); 2927 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2928 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2929 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2930 BUS_DMASYNC_PREREAD); 2931 2932 itd->u.frame_list.next = NULL; 2933 itd->u.frame_list.prev = NULL; 2934 itd->xfer_next = NULL; 2935 itd->slot = 0; 2936 splx(s); 2937 2938 return itd; 2939 } 2940 2941 Static void 2942 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2943 { 2944 2945 KASSERT(mutex_owned(&sc->sc_lock)); 2946 2947 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2948 } 2949 2950 /****************/ 2951 2952 /* 2953 * Close a reqular pipe. 2954 * Assumes that there are no pending transactions. 2955 */ 2956 Static void 2957 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2958 { 2959 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2960 ehci_softc_t *sc = pipe->device->bus->hci_private; 2961 ehci_soft_qh_t *sqh = epipe->sqh; 2962 2963 KASSERT(mutex_owned(&sc->sc_lock)); 2964 2965 ehci_rem_qh(sc, sqh, head); 2966 ehci_free_sqh(sc, epipe->sqh); 2967 } 2968 2969 /* 2970 * Abort a device request. 2971 * If this routine is called at splusb() it guarantees that the request 2972 * will be removed from the hardware scheduling and that the callback 2973 * for it will be called with USBD_CANCELLED status. 2974 * It's impossible to guarantee that the requested transfer will not 2975 * have happened since the hardware runs concurrently. 2976 * If the transaction has already happened we rely on the ordinary 2977 * interrupt processing to process it. 2978 * XXX This is most probably wrong. 2979 * XXXMRG this doesn't make sense anymore. 2980 */ 2981 Static void 2982 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2983 { 2984 #define exfer EXFER(xfer) 2985 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2986 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2987 ehci_soft_qh_t *sqh = epipe->sqh; 2988 ehci_soft_qtd_t *sqtd; 2989 ehci_physaddr_t cur; 2990 u_int32_t qhstatus; 2991 int hit; 2992 int wake; 2993 2994 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2995 2996 KASSERT(mutex_owned(&sc->sc_lock)); 2997 2998 if (sc->sc_dying) { 2999 /* If we're dying, just do the software part. */ 3000 xfer->status = status; /* make software ignore it */ 3001 callout_stop(&xfer->timeout_handle); 3002 usb_transfer_complete(xfer); 3003 return; 3004 } 3005 3006 if (cpu_intr_p() || cpu_softintr_p()) 3007 panic("ehci_abort_xfer: not in process context"); 3008 3009 /* 3010 * If an abort is already in progress then just wait for it to 3011 * complete and return. 3012 */ 3013 if (xfer->hcflags & UXFER_ABORTING) { 3014 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3015 #ifdef DIAGNOSTIC 3016 if (status == USBD_TIMEOUT) 3017 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3018 #endif 3019 /* Override the status which might be USBD_TIMEOUT. */ 3020 xfer->status = status; 3021 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3022 xfer->hcflags |= UXFER_ABORTWAIT; 3023 while (xfer->hcflags & UXFER_ABORTING) 3024 cv_wait(&xfer->hccv, &sc->sc_lock); 3025 return; 3026 } 3027 xfer->hcflags |= UXFER_ABORTING; 3028 3029 /* 3030 * Step 1: Make interrupt routine and hardware ignore xfer. 3031 */ 3032 xfer->status = status; /* make software ignore it */ 3033 callout_stop(&xfer->timeout_handle); 3034 3035 usb_syncmem(&sqh->dma, 3036 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3037 sizeof(sqh->qh.qh_qtd.qtd_status), 3038 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3039 qhstatus = sqh->qh.qh_qtd.qtd_status; 3040 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3041 usb_syncmem(&sqh->dma, 3042 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3043 sizeof(sqh->qh.qh_qtd.qtd_status), 3044 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3045 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3046 usb_syncmem(&sqtd->dma, 3047 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3048 sizeof(sqtd->qtd.qtd_status), 3049 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3050 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3051 usb_syncmem(&sqtd->dma, 3052 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3053 sizeof(sqtd->qtd.qtd_status), 3054 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3055 if (sqtd == exfer->sqtdend) 3056 break; 3057 } 3058 3059 /* 3060 * Step 2: Wait until we know hardware has finished any possible 3061 * use of the xfer. Also make sure the soft interrupt routine 3062 * has run. 3063 */ 3064 ehci_sync_hc(sc); 3065 sc->sc_softwake = 1; 3066 usb_schedsoftintr(&sc->sc_bus); 3067 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3068 3069 /* 3070 * Step 3: Remove any vestiges of the xfer from the hardware. 3071 * The complication here is that the hardware may have executed 3072 * beyond the xfer we're trying to abort. So as we're scanning 3073 * the TDs of this xfer we check if the hardware points to 3074 * any of them. 3075 */ 3076 3077 usb_syncmem(&sqh->dma, 3078 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3079 sizeof(sqh->qh.qh_curqtd), 3080 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3081 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3082 hit = 0; 3083 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3084 hit |= cur == sqtd->physaddr; 3085 if (sqtd == exfer->sqtdend) 3086 break; 3087 } 3088 sqtd = sqtd->nextqtd; 3089 /* Zap curqtd register if hardware pointed inside the xfer. */ 3090 if (hit && sqtd != NULL) { 3091 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3092 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3093 usb_syncmem(&sqh->dma, 3094 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3095 sizeof(sqh->qh.qh_curqtd), 3096 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3097 sqh->qh.qh_qtd.qtd_status = qhstatus; 3098 usb_syncmem(&sqh->dma, 3099 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3100 sizeof(sqh->qh.qh_qtd.qtd_status), 3101 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3102 } else { 3103 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3104 } 3105 3106 /* 3107 * Step 4: Execute callback. 3108 */ 3109 #ifdef DIAGNOSTIC 3110 exfer->isdone = 1; 3111 #endif 3112 wake = xfer->hcflags & UXFER_ABORTWAIT; 3113 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3114 usb_transfer_complete(xfer); 3115 if (wake) { 3116 cv_broadcast(&xfer->hccv); 3117 } 3118 3119 KASSERT(mutex_owned(&sc->sc_lock)); 3120 #undef exfer 3121 } 3122 3123 Static void 3124 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3125 { 3126 ehci_isoc_trans_t trans_status; 3127 struct ehci_pipe *epipe; 3128 struct ehci_xfer *exfer; 3129 ehci_softc_t *sc; 3130 struct ehci_soft_itd *itd; 3131 int i, wake; 3132 3133 epipe = (struct ehci_pipe *) xfer->pipe; 3134 exfer = EXFER(xfer); 3135 sc = epipe->pipe.device->bus->hci_private; 3136 3137 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3138 3139 KASSERT(mutex_owned(&sc->sc_lock)); 3140 3141 if (sc->sc_dying) { 3142 xfer->status = status; 3143 callout_stop(&xfer->timeout_handle); 3144 usb_transfer_complete(xfer); 3145 return; 3146 } 3147 3148 if (xfer->hcflags & UXFER_ABORTING) { 3149 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3150 3151 #ifdef DIAGNOSTIC 3152 if (status == USBD_TIMEOUT) 3153 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3154 #endif 3155 3156 xfer->status = status; 3157 DPRINTFN(2, ("ehci_abort_isoc_xfer: waiting for abort to finish\n")); 3158 xfer->hcflags |= UXFER_ABORTWAIT; 3159 while (xfer->hcflags & UXFER_ABORTING) 3160 cv_wait(&xfer->hccv, &sc->sc_lock); 3161 goto done; 3162 } 3163 xfer->hcflags |= UXFER_ABORTING; 3164 3165 xfer->status = status; 3166 callout_stop(&xfer->timeout_handle); 3167 3168 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3169 usb_syncmem(&itd->dma, 3170 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3171 sizeof(itd->itd.itd_ctl), 3172 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3173 3174 for (i = 0; i < 8; i++) { 3175 trans_status = le32toh(itd->itd.itd_ctl[i]); 3176 trans_status &= ~EHCI_ITD_ACTIVE; 3177 itd->itd.itd_ctl[i] = htole32(trans_status); 3178 } 3179 3180 usb_syncmem(&itd->dma, 3181 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3182 sizeof(itd->itd.itd_ctl), 3183 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3184 } 3185 3186 sc->sc_softwake = 1; 3187 usb_schedsoftintr(&sc->sc_bus); 3188 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3189 3190 #ifdef DIAGNOSTIC 3191 exfer->isdone = 1; 3192 #endif 3193 wake = xfer->hcflags & UXFER_ABORTWAIT; 3194 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3195 usb_transfer_complete(xfer); 3196 if (wake) { 3197 cv_broadcast(&xfer->hccv); 3198 } 3199 3200 done: 3201 KASSERT(mutex_owned(&sc->sc_lock)); 3202 return; 3203 } 3204 3205 Static void 3206 ehci_timeout(void *addr) 3207 { 3208 struct ehci_xfer *exfer = addr; 3209 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3210 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3211 3212 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3213 #ifdef EHCI_DEBUG 3214 if (ehcidebug > 1) 3215 usbd_dump_pipe(exfer->xfer.pipe); 3216 #endif 3217 3218 if (sc->sc_dying) { 3219 mutex_enter(&sc->sc_lock); 3220 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3221 mutex_exit(&sc->sc_lock); 3222 return; 3223 } 3224 3225 /* Execute the abort in a process context. */ 3226 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3227 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3228 USB_TASKQ_HC); 3229 } 3230 3231 Static void 3232 ehci_timeout_task(void *addr) 3233 { 3234 usbd_xfer_handle xfer = addr; 3235 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3236 3237 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3238 3239 mutex_enter(&sc->sc_lock); 3240 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3241 mutex_exit(&sc->sc_lock); 3242 } 3243 3244 /************************/ 3245 3246 Static usbd_status 3247 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3248 { 3249 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3250 usbd_status err; 3251 3252 /* Insert last in queue. */ 3253 mutex_enter(&sc->sc_lock); 3254 err = usb_insert_transfer(xfer); 3255 mutex_exit(&sc->sc_lock); 3256 if (err) 3257 return (err); 3258 3259 /* Pipe isn't running, start first */ 3260 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3261 } 3262 3263 Static usbd_status 3264 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3265 { 3266 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3267 usbd_status err; 3268 3269 if (sc->sc_dying) 3270 return (USBD_IOERROR); 3271 3272 #ifdef DIAGNOSTIC 3273 if (!(xfer->rqflags & URQ_REQUEST)) { 3274 /* XXX panic */ 3275 printf("ehci_device_ctrl_transfer: not a request\n"); 3276 return (USBD_INVAL); 3277 } 3278 #endif 3279 3280 err = ehci_device_request(xfer); 3281 if (err) { 3282 return (err); 3283 } 3284 3285 if (sc->sc_bus.use_polling) 3286 ehci_waitintr(sc, xfer); 3287 3288 return (USBD_IN_PROGRESS); 3289 } 3290 3291 Static void 3292 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3293 { 3294 struct ehci_xfer *ex = EXFER(xfer); 3295 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3296 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3297 usb_device_request_t *req = &xfer->request; 3298 int len = UGETW(req->wLength); 3299 int rd = req->bmRequestType & UT_READ; 3300 3301 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3302 3303 KASSERT(mutex_owned(&sc->sc_lock)); 3304 3305 #ifdef DIAGNOSTIC 3306 if (!(xfer->rqflags & URQ_REQUEST)) { 3307 panic("ehci_ctrl_done: not a request"); 3308 } 3309 #endif 3310 3311 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3312 ehci_del_intr_list(sc, ex); /* remove from active list */ 3313 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3314 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3315 BUS_DMASYNC_POSTWRITE); 3316 if (len) 3317 usb_syncmem(&xfer->dmabuf, 0, len, 3318 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3319 } 3320 3321 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3322 } 3323 3324 /* Abort a device control request. */ 3325 Static void 3326 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3327 { 3328 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3329 ehci_abort_xfer(xfer, USBD_CANCELLED); 3330 } 3331 3332 /* Close a device control pipe. */ 3333 Static void 3334 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3335 { 3336 ehci_softc_t *sc = pipe->device->bus->hci_private; 3337 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3338 3339 KASSERT(mutex_owned(&sc->sc_lock)); 3340 3341 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3342 3343 ehci_close_pipe(pipe, sc->sc_async_head); 3344 } 3345 3346 Static usbd_status 3347 ehci_device_request(usbd_xfer_handle xfer) 3348 { 3349 #define exfer EXFER(xfer) 3350 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3351 usb_device_request_t *req = &xfer->request; 3352 usbd_device_handle dev = epipe->pipe.device; 3353 ehci_softc_t *sc = dev->bus->hci_private; 3354 int addr = dev->address; 3355 ehci_soft_qtd_t *setup, *stat, *next; 3356 ehci_soft_qh_t *sqh; 3357 int isread; 3358 int len; 3359 usbd_status err; 3360 3361 isread = req->bmRequestType & UT_READ; 3362 len = UGETW(req->wLength); 3363 3364 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3365 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3366 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3367 UGETW(req->wIndex), len, addr, 3368 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3369 3370 setup = ehci_alloc_sqtd(sc); 3371 if (setup == NULL) { 3372 err = USBD_NOMEM; 3373 goto bad1; 3374 } 3375 stat = ehci_alloc_sqtd(sc); 3376 if (stat == NULL) { 3377 err = USBD_NOMEM; 3378 goto bad2; 3379 } 3380 3381 mutex_enter(&sc->sc_lock); 3382 3383 sqh = epipe->sqh; 3384 epipe->u.ctl.length = len; 3385 3386 /* Update device address and length since they may have changed 3387 during the setup of the control pipe in usbd_new_device(). */ 3388 /* XXX This only needs to be done once, but it's too early in open. */ 3389 /* XXXX Should not touch ED here! */ 3390 sqh->qh.qh_endp = 3391 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3392 htole32( 3393 EHCI_QH_SET_ADDR(addr) | 3394 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3395 ); 3396 3397 /* Set up data transaction */ 3398 if (len != 0) { 3399 ehci_soft_qtd_t *end; 3400 3401 /* Start toggle at 1. */ 3402 epipe->nexttoggle = 1; 3403 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3404 &next, &end); 3405 if (err) 3406 goto bad3; 3407 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3408 end->nextqtd = stat; 3409 end->qtd.qtd_next = 3410 end->qtd.qtd_altnext = htole32(stat->physaddr); 3411 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3412 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3413 } else { 3414 next = stat; 3415 } 3416 3417 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3418 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3419 3420 /* Clear toggle */ 3421 setup->qtd.qtd_status = htole32( 3422 EHCI_QTD_ACTIVE | 3423 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3424 EHCI_QTD_SET_CERR(3) | 3425 EHCI_QTD_SET_TOGGLE(0) | 3426 EHCI_QTD_SET_BYTES(sizeof *req) 3427 ); 3428 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3429 setup->qtd.qtd_buffer_hi[0] = 0; 3430 setup->nextqtd = next; 3431 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3432 setup->xfer = xfer; 3433 setup->len = sizeof *req; 3434 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3435 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3436 3437 stat->qtd.qtd_status = htole32( 3438 EHCI_QTD_ACTIVE | 3439 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3440 EHCI_QTD_SET_CERR(3) | 3441 EHCI_QTD_SET_TOGGLE(1) | 3442 EHCI_QTD_IOC 3443 ); 3444 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3445 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3446 stat->nextqtd = NULL; 3447 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3448 stat->xfer = xfer; 3449 stat->len = 0; 3450 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3451 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3452 3453 #ifdef EHCI_DEBUG 3454 if (ehcidebug > 5) { 3455 DPRINTF(("ehci_device_request:\n")); 3456 ehci_dump_sqh(sqh); 3457 ehci_dump_sqtds(setup); 3458 } 3459 #endif 3460 3461 exfer->sqtdstart = setup; 3462 exfer->sqtdend = stat; 3463 #ifdef DIAGNOSTIC 3464 if (!exfer->isdone) { 3465 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3466 } 3467 exfer->isdone = 0; 3468 #endif 3469 3470 /* Insert qTD in QH list. */ 3471 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3472 if (xfer->timeout && !sc->sc_bus.use_polling) { 3473 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3474 ehci_timeout, xfer); 3475 } 3476 ehci_add_intr_list(sc, exfer); 3477 xfer->status = USBD_IN_PROGRESS; 3478 mutex_exit(&sc->sc_lock); 3479 3480 #ifdef EHCI_DEBUG 3481 if (ehcidebug > 10) { 3482 DPRINTF(("ehci_device_request: status=%x\n", 3483 EOREAD4(sc, EHCI_USBSTS))); 3484 delay(10000); 3485 ehci_dump_regs(sc); 3486 ehci_dump_sqh(sc->sc_async_head); 3487 ehci_dump_sqh(sqh); 3488 ehci_dump_sqtds(setup); 3489 } 3490 #endif 3491 3492 return (USBD_NORMAL_COMPLETION); 3493 3494 bad3: 3495 mutex_exit(&sc->sc_lock); 3496 ehci_free_sqtd(sc, stat); 3497 bad2: 3498 ehci_free_sqtd(sc, setup); 3499 bad1: 3500 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3501 mutex_enter(&sc->sc_lock); 3502 xfer->status = err; 3503 usb_transfer_complete(xfer); 3504 mutex_exit(&sc->sc_lock); 3505 return (err); 3506 #undef exfer 3507 } 3508 3509 /* 3510 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3511 * qTD status, or miss signalling occasionally under heavy load. If the host 3512 * machine is too fast, we we can miss transaction completion - when we scan 3513 * the active list the transaction still seems to be active. This generally 3514 * exhibits itself as a umass stall that never recovers. 3515 * 3516 * We work around this behaviour by setting up this callback after any softintr 3517 * that completes with transactions still pending, giving us another chance to 3518 * check for completion after the writeback has taken place. 3519 */ 3520 Static void 3521 ehci_intrlist_timeout(void *arg) 3522 { 3523 ehci_softc_t *sc = arg; 3524 3525 DPRINTF(("ehci_intrlist_timeout\n")); 3526 usb_schedsoftintr(&sc->sc_bus); 3527 } 3528 3529 /************************/ 3530 3531 Static usbd_status 3532 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3533 { 3534 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3535 usbd_status err; 3536 3537 /* Insert last in queue. */ 3538 mutex_enter(&sc->sc_lock); 3539 err = usb_insert_transfer(xfer); 3540 mutex_exit(&sc->sc_lock); 3541 if (err) 3542 return (err); 3543 3544 /* Pipe isn't running, start first */ 3545 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3546 } 3547 3548 Static usbd_status 3549 ehci_device_bulk_start(usbd_xfer_handle xfer) 3550 { 3551 #define exfer EXFER(xfer) 3552 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3553 usbd_device_handle dev = epipe->pipe.device; 3554 ehci_softc_t *sc = dev->bus->hci_private; 3555 ehci_soft_qtd_t *data, *dataend; 3556 ehci_soft_qh_t *sqh; 3557 usbd_status err; 3558 int len, isread, endpt; 3559 3560 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3561 xfer, xfer->length, xfer->flags)); 3562 3563 if (sc->sc_dying) 3564 return (USBD_IOERROR); 3565 3566 #ifdef DIAGNOSTIC 3567 if (xfer->rqflags & URQ_REQUEST) 3568 panic("ehci_device_bulk_start: a request"); 3569 #endif 3570 3571 mutex_enter(&sc->sc_lock); 3572 3573 len = xfer->length; 3574 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3575 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3576 sqh = epipe->sqh; 3577 3578 epipe->u.bulk.length = len; 3579 3580 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3581 &dataend); 3582 if (err) { 3583 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3584 xfer->status = err; 3585 usb_transfer_complete(xfer); 3586 mutex_exit(&sc->sc_lock); 3587 return (err); 3588 } 3589 3590 #ifdef EHCI_DEBUG 3591 if (ehcidebug > 5) { 3592 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3593 ehci_dump_sqh(sqh); 3594 ehci_dump_sqtds(data); 3595 } 3596 #endif 3597 3598 /* Set up interrupt info. */ 3599 exfer->sqtdstart = data; 3600 exfer->sqtdend = dataend; 3601 #ifdef DIAGNOSTIC 3602 if (!exfer->isdone) { 3603 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3604 } 3605 exfer->isdone = 0; 3606 #endif 3607 3608 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3609 if (xfer->timeout && !sc->sc_bus.use_polling) { 3610 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3611 ehci_timeout, xfer); 3612 } 3613 ehci_add_intr_list(sc, exfer); 3614 xfer->status = USBD_IN_PROGRESS; 3615 mutex_exit(&sc->sc_lock); 3616 3617 #ifdef EHCI_DEBUG 3618 if (ehcidebug > 10) { 3619 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3620 delay(10000); 3621 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3622 ehci_dump_regs(sc); 3623 #if 0 3624 printf("async_head:\n"); 3625 ehci_dump_sqh(sc->sc_async_head); 3626 #endif 3627 printf("sqh:\n"); 3628 ehci_dump_sqh(sqh); 3629 ehci_dump_sqtds(data); 3630 } 3631 #endif 3632 3633 if (sc->sc_bus.use_polling) 3634 ehci_waitintr(sc, xfer); 3635 3636 return (USBD_IN_PROGRESS); 3637 #undef exfer 3638 } 3639 3640 Static void 3641 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3642 { 3643 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3644 ehci_abort_xfer(xfer, USBD_CANCELLED); 3645 } 3646 3647 /* 3648 * Close a device bulk pipe. 3649 */ 3650 Static void 3651 ehci_device_bulk_close(usbd_pipe_handle pipe) 3652 { 3653 ehci_softc_t *sc = pipe->device->bus->hci_private; 3654 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3655 3656 KASSERT(mutex_owned(&sc->sc_lock)); 3657 3658 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3659 pipe->endpoint->datatoggle = epipe->nexttoggle; 3660 ehci_close_pipe(pipe, sc->sc_async_head); 3661 } 3662 3663 Static void 3664 ehci_device_bulk_done(usbd_xfer_handle xfer) 3665 { 3666 struct ehci_xfer *ex = EXFER(xfer); 3667 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3668 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3669 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3670 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3671 3672 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3673 xfer, xfer->actlen)); 3674 3675 KASSERT(mutex_owned(&sc->sc_lock)); 3676 3677 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3678 ehci_del_intr_list(sc, ex); /* remove from active list */ 3679 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3680 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3681 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3682 } 3683 3684 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3685 } 3686 3687 /************************/ 3688 3689 Static usbd_status 3690 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3691 { 3692 struct ehci_soft_islot *isp; 3693 int islot, lev; 3694 3695 /* Find a poll rate that is large enough. */ 3696 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3697 if (EHCI_ILEV_IVAL(lev) <= ival) 3698 break; 3699 3700 /* Pick an interrupt slot at the right level. */ 3701 /* XXX could do better than picking at random */ 3702 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3703 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3704 3705 sqh->islot = islot; 3706 isp = &sc->sc_islots[islot]; 3707 mutex_enter(&sc->sc_lock); 3708 ehci_add_qh(sc, sqh, isp->sqh); 3709 mutex_exit(&sc->sc_lock); 3710 3711 return (USBD_NORMAL_COMPLETION); 3712 } 3713 3714 Static usbd_status 3715 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3716 { 3717 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3718 usbd_status err; 3719 3720 /* Insert last in queue. */ 3721 mutex_enter(&sc->sc_lock); 3722 err = usb_insert_transfer(xfer); 3723 mutex_exit(&sc->sc_lock); 3724 if (err) 3725 return (err); 3726 3727 /* 3728 * Pipe isn't running (otherwise err would be USBD_INPROG), 3729 * so start it first. 3730 */ 3731 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3732 } 3733 3734 Static usbd_status 3735 ehci_device_intr_start(usbd_xfer_handle xfer) 3736 { 3737 #define exfer EXFER(xfer) 3738 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3739 usbd_device_handle dev = xfer->pipe->device; 3740 ehci_softc_t *sc = dev->bus->hci_private; 3741 ehci_soft_qtd_t *data, *dataend; 3742 ehci_soft_qh_t *sqh; 3743 usbd_status err; 3744 int len, isread, endpt; 3745 3746 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3747 xfer, xfer->length, xfer->flags)); 3748 3749 if (sc->sc_dying) 3750 return (USBD_IOERROR); 3751 3752 #ifdef DIAGNOSTIC 3753 if (xfer->rqflags & URQ_REQUEST) 3754 panic("ehci_device_intr_start: a request"); 3755 #endif 3756 3757 mutex_enter(&sc->sc_lock); 3758 3759 len = xfer->length; 3760 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3761 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3762 sqh = epipe->sqh; 3763 3764 epipe->u.intr.length = len; 3765 3766 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3767 &dataend); 3768 if (err) { 3769 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3770 xfer->status = err; 3771 usb_transfer_complete(xfer); 3772 mutex_exit(&sc->sc_lock); 3773 return (err); 3774 } 3775 3776 #ifdef EHCI_DEBUG 3777 if (ehcidebug > 5) { 3778 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3779 ehci_dump_sqh(sqh); 3780 ehci_dump_sqtds(data); 3781 } 3782 #endif 3783 3784 /* Set up interrupt info. */ 3785 exfer->sqtdstart = data; 3786 exfer->sqtdend = dataend; 3787 #ifdef DIAGNOSTIC 3788 if (!exfer->isdone) { 3789 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3790 } 3791 exfer->isdone = 0; 3792 #endif 3793 3794 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3795 if (xfer->timeout && !sc->sc_bus.use_polling) { 3796 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3797 ehci_timeout, xfer); 3798 } 3799 ehci_add_intr_list(sc, exfer); 3800 xfer->status = USBD_IN_PROGRESS; 3801 mutex_exit(&sc->sc_lock); 3802 3803 #ifdef EHCI_DEBUG 3804 if (ehcidebug > 10) { 3805 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3806 delay(10000); 3807 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3808 ehci_dump_regs(sc); 3809 printf("sqh:\n"); 3810 ehci_dump_sqh(sqh); 3811 ehci_dump_sqtds(data); 3812 } 3813 #endif 3814 3815 if (sc->sc_bus.use_polling) 3816 ehci_waitintr(sc, xfer); 3817 3818 return (USBD_IN_PROGRESS); 3819 #undef exfer 3820 } 3821 3822 Static void 3823 ehci_device_intr_abort(usbd_xfer_handle xfer) 3824 { 3825 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3826 if (xfer->pipe->intrxfer == xfer) { 3827 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3828 xfer->pipe->intrxfer = NULL; 3829 } 3830 /* 3831 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3832 * async doorbell. That's dependent on the async list, wheras 3833 * intr xfers are periodic, should not use this? 3834 */ 3835 ehci_abort_xfer(xfer, USBD_CANCELLED); 3836 } 3837 3838 Static void 3839 ehci_device_intr_close(usbd_pipe_handle pipe) 3840 { 3841 ehci_softc_t *sc = pipe->device->bus->hci_private; 3842 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3843 struct ehci_soft_islot *isp; 3844 3845 KASSERT(mutex_owned(&sc->sc_lock)); 3846 3847 isp = &sc->sc_islots[epipe->sqh->islot]; 3848 ehci_close_pipe(pipe, isp->sqh); 3849 } 3850 3851 Static void 3852 ehci_device_intr_done(usbd_xfer_handle xfer) 3853 { 3854 #define exfer EXFER(xfer) 3855 struct ehci_xfer *ex = EXFER(xfer); 3856 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3857 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3858 ehci_soft_qtd_t *data, *dataend; 3859 ehci_soft_qh_t *sqh; 3860 usbd_status err; 3861 int len, isread, endpt; 3862 3863 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3864 xfer, xfer->actlen)); 3865 3866 KASSERT(mutex_owned(&sc->sc_lock)); 3867 3868 if (xfer->pipe->repeat) { 3869 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3870 3871 len = epipe->u.intr.length; 3872 xfer->length = len; 3873 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3874 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3875 usb_syncmem(&xfer->dmabuf, 0, len, 3876 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3877 sqh = epipe->sqh; 3878 3879 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3880 &data, &dataend); 3881 if (err) { 3882 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3883 xfer->status = err; 3884 return; 3885 } 3886 3887 /* Set up interrupt info. */ 3888 exfer->sqtdstart = data; 3889 exfer->sqtdend = dataend; 3890 #ifdef DIAGNOSTIC 3891 if (!exfer->isdone) { 3892 printf("ehci_device_intr_done: not done, ex=%p\n", 3893 exfer); 3894 } 3895 exfer->isdone = 0; 3896 #endif 3897 3898 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3899 if (xfer->timeout && !sc->sc_bus.use_polling) { 3900 callout_reset(&xfer->timeout_handle, 3901 mstohz(xfer->timeout), ehci_timeout, xfer); 3902 } 3903 3904 xfer->status = USBD_IN_PROGRESS; 3905 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3906 ehci_del_intr_list(sc, ex); /* remove from active list */ 3907 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3908 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3909 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3910 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3911 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3912 } 3913 #undef exfer 3914 } 3915 3916 /************************/ 3917 3918 Static usbd_status 3919 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3920 { 3921 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3922 usbd_status err; 3923 3924 mutex_enter(&sc->sc_lock); 3925 err = usb_insert_transfer(xfer); 3926 mutex_exit(&sc->sc_lock); 3927 if (err && err != USBD_IN_PROGRESS) 3928 return err; 3929 3930 return ehci_device_isoc_start(xfer); 3931 } 3932 3933 Static usbd_status 3934 ehci_device_isoc_start(usbd_xfer_handle xfer) 3935 { 3936 struct ehci_pipe *epipe; 3937 usbd_device_handle dev; 3938 ehci_softc_t *sc; 3939 struct ehci_xfer *exfer; 3940 ehci_soft_itd_t *itd, *prev, *start, *stop; 3941 usb_dma_t *dma_buf; 3942 int i, j, k, frames, uframes, ufrperframe; 3943 int trans_count, offs, total_length; 3944 int frindex; 3945 3946 start = NULL; 3947 prev = NULL; 3948 itd = NULL; 3949 trans_count = 0; 3950 total_length = 0; 3951 exfer = (struct ehci_xfer *) xfer; 3952 sc = xfer->pipe->device->bus->hci_private; 3953 dev = xfer->pipe->device; 3954 epipe = (struct ehci_pipe *)xfer->pipe; 3955 3956 /* 3957 * To allow continuous transfers, above we start all transfers 3958 * immediately. However, we're still going to get usbd_start_next call 3959 * this when another xfer completes. So, check if this is already 3960 * in progress or not 3961 */ 3962 3963 if (exfer->itdstart != NULL) 3964 return USBD_IN_PROGRESS; 3965 3966 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3967 xfer, xfer->length, xfer->flags)); 3968 3969 if (sc->sc_dying) 3970 return USBD_IOERROR; 3971 3972 /* 3973 * To avoid complication, don't allow a request right now that'll span 3974 * the entire frame table. To within 4 frames, to allow some leeway 3975 * on either side of where the hc currently is. 3976 */ 3977 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3978 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3979 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3980 return USBD_INVAL; 3981 } 3982 3983 #ifdef DIAGNOSTIC 3984 if (xfer->rqflags & URQ_REQUEST) 3985 panic("ehci_device_isoc_start: request\n"); 3986 3987 if (!exfer->isdone) 3988 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3989 exfer->isdone = 0; 3990 #endif 3991 3992 /* 3993 * Step 1: Allocate and initialize itds, how many do we need? 3994 * One per transfer if interval >= 8 microframes, fewer if we use 3995 * multiple microframes per frame. 3996 */ 3997 3998 i = epipe->pipe.endpoint->edesc->bInterval; 3999 if (i > 16 || i == 0) { 4000 /* Spec page 271 says intervals > 16 are invalid */ 4001 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 4002 return USBD_INVAL; 4003 } 4004 4005 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4006 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4007 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4008 4009 if (frames == 0) { 4010 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 4011 return USBD_INVAL; 4012 } 4013 4014 dma_buf = &xfer->dmabuf; 4015 offs = 0; 4016 4017 for (i = 0; i < frames; i++) { 4018 int froffs = offs; 4019 itd = ehci_alloc_itd(sc); 4020 4021 if (prev != NULL) { 4022 prev->itd.itd_next = 4023 htole32(itd->physaddr | EHCI_LINK_ITD); 4024 usb_syncmem(&itd->dma, 4025 itd->offs + offsetof(ehci_itd_t, itd_next), 4026 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4027 4028 prev->xfer_next = itd; 4029 } else { 4030 start = itd; 4031 } 4032 4033 /* 4034 * Step 1.5, initialize uframes 4035 */ 4036 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4037 /* Calculate which page in the list this starts in */ 4038 int addr = DMAADDR(dma_buf, froffs); 4039 addr = EHCI_PAGE_OFFSET(addr); 4040 addr += (offs - froffs); 4041 addr = EHCI_PAGE(addr); 4042 addr /= EHCI_PAGE_SIZE; 4043 4044 /* This gets the initial offset into the first page, 4045 * looks how far further along the current uframe 4046 * offset is. Works out how many pages that is. 4047 */ 4048 4049 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4050 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4051 EHCI_ITD_SET_PG(addr) | 4052 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4053 4054 total_length += xfer->frlengths[trans_count]; 4055 offs += xfer->frlengths[trans_count]; 4056 trans_count++; 4057 4058 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4059 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4060 break; 4061 } 4062 } 4063 4064 /* Step 1.75, set buffer pointers. To simplify matters, all 4065 * pointers are filled out for the next 7 hardware pages in 4066 * the dma block, so no need to worry what pages to cover 4067 * and what to not. 4068 */ 4069 4070 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4071 /* 4072 * Don't try to lookup a page that's past the end 4073 * of buffer 4074 */ 4075 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4076 if (page_offs >= dma_buf->block->size) 4077 break; 4078 4079 unsigned long long page = DMAADDR(dma_buf, page_offs); 4080 page = EHCI_PAGE(page); 4081 itd->itd.itd_bufr[j] = 4082 htole32(EHCI_ITD_SET_BPTR(page)); 4083 itd->itd.itd_bufr_hi[j] = 4084 htole32(page >> 32); 4085 } 4086 4087 /* 4088 * Other special values 4089 */ 4090 4091 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4092 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4093 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4094 4095 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4096 ? 1 : 0; 4097 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4098 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4099 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4100 4101 /* FIXME: handle invalid trans */ 4102 itd->itd.itd_bufr[2] |= 4103 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4104 4105 usb_syncmem(&itd->dma, 4106 itd->offs + offsetof(ehci_itd_t, itd_next), 4107 sizeof(ehci_itd_t), 4108 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4109 4110 prev = itd; 4111 } /* End of frame */ 4112 4113 stop = itd; 4114 stop->xfer_next = NULL; 4115 exfer->isoc_len = total_length; 4116 4117 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4118 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4119 4120 /* 4121 * Part 2: Transfer descriptors have now been set up, now they must 4122 * be scheduled into the period frame list. Erk. Not wanting to 4123 * complicate matters, transfer is denied if the transfer spans 4124 * more than the period frame list. 4125 */ 4126 4127 mutex_enter(&sc->sc_lock); 4128 4129 /* Start inserting frames */ 4130 if (epipe->u.isoc.cur_xfers > 0) { 4131 frindex = epipe->u.isoc.next_frame; 4132 } else { 4133 frindex = EOREAD4(sc, EHCI_FRINDEX); 4134 frindex = frindex >> 3; /* Erase microframe index */ 4135 frindex += 2; 4136 } 4137 4138 if (frindex >= sc->sc_flsize) 4139 frindex &= (sc->sc_flsize - 1); 4140 4141 /* What's the frame interval? */ 4142 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4143 if (i / USB_UFRAMES_PER_FRAME == 0) 4144 i = 1; 4145 else 4146 i /= USB_UFRAMES_PER_FRAME; 4147 4148 itd = start; 4149 for (j = 0; j < frames; j++) { 4150 if (itd == NULL) 4151 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4152 4153 itd->itd.itd_next = sc->sc_flist[frindex]; 4154 if (itd->itd.itd_next == 0) 4155 /* FIXME: frindex table gets initialized to NULL 4156 * or EHCI_NULL? */ 4157 itd->itd.itd_next = EHCI_NULL; 4158 4159 usb_syncmem(&itd->dma, 4160 itd->offs + offsetof(ehci_itd_t, itd_next), 4161 sizeof(itd->itd.itd_next), 4162 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4163 4164 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4165 4166 usb_syncmem(&sc->sc_fldma, 4167 sizeof(ehci_link_t) * frindex, 4168 sizeof(ehci_link_t), 4169 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4170 4171 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4172 sc->sc_softitds[frindex] = itd; 4173 if (itd->u.frame_list.next != NULL) 4174 itd->u.frame_list.next->u.frame_list.prev = itd; 4175 itd->slot = frindex; 4176 itd->u.frame_list.prev = NULL; 4177 4178 frindex += i; 4179 if (frindex >= sc->sc_flsize) 4180 frindex -= sc->sc_flsize; 4181 4182 itd = itd->xfer_next; 4183 } 4184 4185 epipe->u.isoc.cur_xfers++; 4186 epipe->u.isoc.next_frame = frindex; 4187 4188 exfer->itdstart = start; 4189 exfer->itdend = stop; 4190 exfer->sqtdstart = NULL; 4191 exfer->sqtdstart = NULL; 4192 4193 ehci_add_intr_list(sc, exfer); 4194 xfer->status = USBD_IN_PROGRESS; 4195 xfer->done = 0; 4196 mutex_exit(&sc->sc_lock); 4197 4198 if (sc->sc_bus.use_polling) { 4199 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4200 ehci_waitintr(sc, xfer); 4201 } 4202 4203 return USBD_IN_PROGRESS; 4204 } 4205 4206 Static void 4207 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4208 { 4209 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4210 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4211 } 4212 4213 Static void 4214 ehci_device_isoc_close(usbd_pipe_handle pipe) 4215 { 4216 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4217 } 4218 4219 Static void 4220 ehci_device_isoc_done(usbd_xfer_handle xfer) 4221 { 4222 struct ehci_xfer *exfer; 4223 ehci_softc_t *sc; 4224 struct ehci_pipe *epipe; 4225 4226 exfer = EXFER(xfer); 4227 sc = xfer->pipe->device->bus->hci_private; 4228 epipe = (struct ehci_pipe *) xfer->pipe; 4229 4230 KASSERT(mutex_owned(&sc->sc_lock)); 4231 4232 epipe->u.isoc.cur_xfers--; 4233 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4234 ehci_del_intr_list(sc, exfer); 4235 ehci_rem_free_itd_chain(sc, exfer); 4236 } 4237 4238 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4239 BUS_DMASYNC_POSTREAD); 4240 4241 } 4242
Indexes created Thu Oct 02 01:09:59 GMT 2025