ehci.c revision 1.181.6.17
1 /* $NetBSD: ehci.c,v 1.181.6.17 2012/03/11 01:52:28 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.181.6.17 2012/03/11 01:52:28 mrg Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/kmem.h> 66 #include <sys/device.h> 67 #include <sys/select.h> 68 #include <sys/proc.h> 69 #include <sys/queue.h> 70 #include <sys/mutex.h> 71 #include <sys/bus.h> 72 #include <sys/cpu.h> 73 74 #include <machine/endian.h> 75 76 #include <dev/usb/usb.h> 77 #include <dev/usb/usbdi.h> 78 #include <dev/usb/usbdivar.h> 79 #include <dev/usb/usb_mem.h> 80 #include <dev/usb/usb_quirks.h> 81 82 #include <dev/usb/ehcireg.h> 83 #include <dev/usb/ehcivar.h> 84 #include <dev/usb/usbroothub_subr.h> 85 86 #ifdef EHCI_DEBUG 87 #include <sys/kprintf.h> 88 static void 89 ehciprintf(const char *fmt, ...) 90 { 91 va_list ap; 92 93 va_start(ap, fmt); 94 kprintf(fmt, TOLOG|TOCONS, NULL, NULL, ap); 95 va_end(ap); 96 } 97 98 #define DPRINTF(x) do { if (ehcidebug) ehciprintf x; } while(0) 99 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) ehciprintf x; } while (0) 100 int ehcidebug = 0; 101 #else 102 #define DPRINTF(x) 103 #define DPRINTFN(n,x) 104 #endif 105 106 struct ehci_pipe { 107 struct usbd_pipe pipe; 108 int nexttoggle; 109 110 ehci_soft_qh_t *sqh; 111 union { 112 ehci_soft_qtd_t *qtd; 113 /* ehci_soft_itd_t *itd; */ 114 } tail; 115 union { 116 /* Control pipe */ 117 struct { 118 usb_dma_t reqdma; 119 u_int length; 120 } ctl; 121 /* Interrupt pipe */ 122 struct { 123 u_int length; 124 } intr; 125 /* Bulk pipe */ 126 struct { 127 u_int length; 128 } bulk; 129 /* Iso pipe */ 130 struct { 131 u_int next_frame; 132 u_int cur_xfers; 133 } isoc; 134 } u; 135 }; 136 137 Static usbd_status ehci_open(usbd_pipe_handle); 138 Static void ehci_poll(struct usbd_bus *); 139 Static void ehci_softintr(void *); 140 Static int ehci_intr1(ehci_softc_t *); 141 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 142 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 143 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 144 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 145 Static void ehci_idone(struct ehci_xfer *); 146 Static void ehci_timeout(void *); 147 Static void ehci_timeout_task(void *); 148 Static void ehci_intrlist_timeout(void *); 149 Static void ehci_doorbell(void *); 150 Static void ehci_pcd(void *); 151 152 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 153 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 154 155 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 156 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 157 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 158 159 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 160 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 161 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 162 Static void ehci_root_ctrl_close(usbd_pipe_handle); 163 Static void ehci_root_ctrl_done(usbd_xfer_handle); 164 165 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 166 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 167 Static void ehci_root_intr_abort(usbd_xfer_handle); 168 Static void ehci_root_intr_close(usbd_pipe_handle); 169 Static void ehci_root_intr_done(usbd_xfer_handle); 170 171 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 172 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 173 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 174 Static void ehci_device_ctrl_close(usbd_pipe_handle); 175 Static void ehci_device_ctrl_done(usbd_xfer_handle); 176 177 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 178 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 179 Static void ehci_device_bulk_abort(usbd_xfer_handle); 180 Static void ehci_device_bulk_close(usbd_pipe_handle); 181 Static void ehci_device_bulk_done(usbd_xfer_handle); 182 183 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 184 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 185 Static void ehci_device_intr_abort(usbd_xfer_handle); 186 Static void ehci_device_intr_close(usbd_pipe_handle); 187 Static void ehci_device_intr_done(usbd_xfer_handle); 188 189 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 190 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 191 Static void ehci_device_isoc_abort(usbd_xfer_handle); 192 Static void ehci_device_isoc_close(usbd_pipe_handle); 193 Static void ehci_device_isoc_done(usbd_xfer_handle); 194 195 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 196 Static void ehci_noop(usbd_pipe_handle pipe); 197 198 Static void ehci_disown(ehci_softc_t *, int, int); 199 200 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 201 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 202 203 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 204 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 205 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 206 ehci_softc_t *, int, int, usbd_xfer_handle, 207 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 208 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 209 ehci_soft_qtd_t *); 210 211 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 212 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 213 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 214 struct ehci_xfer *exfer); 215 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 216 usbd_status status); 217 218 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 219 220 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 221 int ival); 222 223 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 224 ehci_soft_qh_t *); 225 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 226 ehci_soft_qh_t *); 227 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 228 Static void ehci_sync_hc(ehci_softc_t *); 229 230 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 231 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 232 233 #ifdef EHCI_DEBUG 234 Static void ehci_dump_regs(ehci_softc_t *); 235 void ehci_dump(void); 236 Static ehci_softc_t *theehci; 237 Static void ehci_dump_link(ehci_link_t, int); 238 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 239 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 240 Static void ehci_dump_qtd(ehci_qtd_t *); 241 Static void ehci_dump_sqh(ehci_soft_qh_t *); 242 #if notyet 243 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 244 Static void ehci_dump_itd(struct ehci_soft_itd *); 245 #endif 246 #ifdef DIAGNOSTIC 247 Static void ehci_dump_exfer(struct ehci_xfer *); 248 #endif 249 #endif 250 251 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 252 253 #define EHCI_INTR_ENDPT 1 254 255 #define ehci_add_intr_list(sc, ex) \ 256 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 257 #define ehci_del_intr_list(sc, ex) \ 258 do { \ 259 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 260 (ex)->inext.tqe_prev = NULL; \ 261 } while (0) 262 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 263 264 Static const struct usbd_bus_methods ehci_bus_methods = { 265 .open_pipe = ehci_open, 266 .soft_intr = ehci_softintr, 267 .do_poll = ehci_poll, 268 .allocm = ehci_allocm, 269 .freem = ehci_freem, 270 .allocx = ehci_allocx, 271 .freex = ehci_freex, 272 .get_lock = ehci_get_lock, 273 }; 274 275 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 276 .transfer = ehci_root_ctrl_transfer, 277 .start = ehci_root_ctrl_start, 278 .abort = ehci_root_ctrl_abort, 279 .close = ehci_root_ctrl_close, 280 .cleartoggle = ehci_noop, 281 .done = ehci_root_ctrl_done, 282 }; 283 284 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 285 .transfer = ehci_root_intr_transfer, 286 .start = ehci_root_intr_start, 287 .abort = ehci_root_intr_abort, 288 .close = ehci_root_intr_close, 289 .cleartoggle = ehci_noop, 290 .done = ehci_root_intr_done, 291 }; 292 293 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 294 .transfer = ehci_device_ctrl_transfer, 295 .start = ehci_device_ctrl_start, 296 .abort = ehci_device_ctrl_abort, 297 .close = ehci_device_ctrl_close, 298 .cleartoggle = ehci_noop, 299 .done = ehci_device_ctrl_done, 300 }; 301 302 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 303 .transfer = ehci_device_intr_transfer, 304 .start = ehci_device_intr_start, 305 .abort = ehci_device_intr_abort, 306 .close = ehci_device_intr_close, 307 .cleartoggle = ehci_device_clear_toggle, 308 .done = ehci_device_intr_done, 309 }; 310 311 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 312 .transfer = ehci_device_bulk_transfer, 313 .start = ehci_device_bulk_start, 314 .abort = ehci_device_bulk_abort, 315 .close = ehci_device_bulk_close, 316 .cleartoggle = ehci_device_clear_toggle, 317 .done = ehci_device_bulk_done, 318 }; 319 320 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 321 .transfer = ehci_device_isoc_transfer, 322 .start = ehci_device_isoc_start, 323 .abort = ehci_device_isoc_abort, 324 .close = ehci_device_isoc_close, 325 .cleartoggle = ehci_noop, 326 .done = ehci_device_isoc_done, 327 }; 328 329 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 330 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 331 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 332 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 333 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 334 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 335 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 336 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 337 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 338 }; 339 340 usbd_status 341 ehci_init(ehci_softc_t *sc) 342 { 343 u_int32_t vers, sparams, cparams, hcr; 344 u_int i; 345 usbd_status err; 346 ehci_soft_qh_t *sqh; 347 u_int ncomp; 348 349 DPRINTF(("ehci_init: start\n")); 350 #ifdef EHCI_DEBUG 351 theehci = sc; 352 #endif 353 354 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 355 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 356 cv_init(&sc->sc_softwake_cv, "ehciab"); 357 cv_init(&sc->sc_doorbell, "ehcidi"); 358 359 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 360 ehci_doorbell, sc); 361 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 362 ehci_pcd, sc); 363 364 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 365 366 vers = EREAD2(sc, EHCI_HCIVERSION); 367 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 368 vers >> 8, vers & 0xff); 369 370 sparams = EREAD4(sc, EHCI_HCSPARAMS); 371 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 372 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 373 ncomp = EHCI_HCS_N_CC(sparams); 374 if (ncomp != sc->sc_ncomp) { 375 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 376 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 377 #if NOHCI == 0 || NUHCI == 0 378 aprint_error("%s: ohci or uhci probably not configured\n", 379 device_xname(sc->sc_dev)); 380 #endif 381 if (ncomp < sc->sc_ncomp) 382 sc->sc_ncomp = ncomp; 383 } 384 if (sc->sc_ncomp > 0) { 385 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 386 aprint_normal("%s: companion controller%s, %d port%s each:", 387 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 388 EHCI_HCS_N_PCC(sparams), 389 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 390 for (i = 0; i < sc->sc_ncomp; i++) 391 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 392 aprint_normal("\n"); 393 } 394 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 395 cparams = EREAD4(sc, EHCI_HCCPARAMS); 396 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 397 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 398 399 if (EHCI_HCC_64BIT(cparams)) { 400 /* MUST clear segment register if 64 bit capable. */ 401 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 402 } 403 404 sc->sc_bus.usbrev = USBREV_2_0; 405 406 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 407 USB_MEM_RESERVE); 408 409 /* Reset the controller */ 410 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 411 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 412 usb_delay_ms(&sc->sc_bus, 1); 413 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 414 for (i = 0; i < 100; i++) { 415 usb_delay_ms(&sc->sc_bus, 1); 416 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 417 if (!hcr) 418 break; 419 } 420 if (hcr) { 421 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 422 return (USBD_IOERROR); 423 } 424 if (sc->sc_vendor_init) 425 sc->sc_vendor_init(sc); 426 427 /* 428 * If we are doing embedded transaction translation function, force 429 * the controller to host mode. 430 */ 431 if (sc->sc_flags & EHCIF_ETTF) { 432 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 433 usbmode &= ~EHCI_USBMODE_CM; 434 usbmode |= EHCI_USBMODE_CM_HOST; 435 EWRITE4(sc, EHCI_USBMODE, usbmode); 436 } 437 438 /* XXX need proper intr scheduling */ 439 sc->sc_rand = 96; 440 441 /* frame list size at default, read back what we got and use that */ 442 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 443 case 0: sc->sc_flsize = 1024; break; 444 case 1: sc->sc_flsize = 512; break; 445 case 2: sc->sc_flsize = 256; break; 446 case 3: return (USBD_IOERROR); 447 } 448 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 449 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 450 if (err) 451 return (err); 452 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 453 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 454 455 for (i = 0; i < sc->sc_flsize; i++) { 456 sc->sc_flist[i] = EHCI_NULL; 457 } 458 459 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 460 461 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 462 KM_SLEEP); 463 if (sc->sc_softitds == NULL) 464 return ENOMEM; 465 LIST_INIT(&sc->sc_freeitds); 466 TAILQ_INIT(&sc->sc_intrhead); 467 468 /* Set up the bus struct. */ 469 sc->sc_bus.methods = &ehci_bus_methods; 470 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 471 472 sc->sc_eintrs = EHCI_NORMAL_INTRS; 473 474 /* 475 * Allocate the interrupt dummy QHs. These are arranged to give poll 476 * intervals that are powers of 2 times 1ms. 477 */ 478 for (i = 0; i < EHCI_INTRQHS; i++) { 479 sqh = ehci_alloc_sqh(sc); 480 if (sqh == NULL) { 481 err = USBD_NOMEM; 482 goto bad1; 483 } 484 sc->sc_islots[i].sqh = sqh; 485 } 486 for (i = 0; i < EHCI_INTRQHS; i++) { 487 sqh = sc->sc_islots[i].sqh; 488 if (i == 0) { 489 /* The last (1ms) QH terminates. */ 490 sqh->qh.qh_link = EHCI_NULL; 491 sqh->next = NULL; 492 } else { 493 /* Otherwise the next QH has half the poll interval */ 494 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 495 sqh->qh.qh_link = htole32(sqh->next->physaddr | 496 EHCI_LINK_QH); 497 } 498 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 499 sqh->qh.qh_curqtd = EHCI_NULL; 500 sqh->next = NULL; 501 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 502 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 503 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 504 sqh->sqtd = NULL; 505 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 506 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 507 } 508 /* Point the frame list at the last level (128ms). */ 509 for (i = 0; i < sc->sc_flsize; i++) { 510 int j; 511 512 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 513 revbits[i & (EHCI_MAX_POLLRATE-1)]; 514 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 515 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 516 i)].sqh->physaddr); 517 } 518 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 519 BUS_DMASYNC_PREWRITE); 520 521 /* Allocate dummy QH that starts the async list. */ 522 sqh = ehci_alloc_sqh(sc); 523 if (sqh == NULL) { 524 err = USBD_NOMEM; 525 goto bad1; 526 } 527 /* Fill the QH */ 528 sqh->qh.qh_endp = 529 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 530 sqh->qh.qh_link = 531 htole32(sqh->physaddr | EHCI_LINK_QH); 532 sqh->qh.qh_curqtd = EHCI_NULL; 533 sqh->next = NULL; 534 /* Fill the overlay qTD */ 535 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 536 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 537 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 538 sqh->sqtd = NULL; 539 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 540 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 541 #ifdef EHCI_DEBUG 542 if (ehcidebug) { 543 ehci_dump_sqh(sqh); 544 } 545 #endif 546 547 /* Point to async list */ 548 sc->sc_async_head = sqh; 549 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 550 551 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 552 553 /* Turn on controller */ 554 EOWRITE4(sc, EHCI_USBCMD, 555 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 556 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 557 EHCI_CMD_ASE | 558 EHCI_CMD_PSE | 559 EHCI_CMD_RS); 560 561 /* Take over port ownership */ 562 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 563 564 for (i = 0; i < 100; i++) { 565 usb_delay_ms(&sc->sc_bus, 1); 566 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 567 if (!hcr) 568 break; 569 } 570 if (hcr) { 571 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 572 return (USBD_IOERROR); 573 } 574 575 /* Enable interrupts */ 576 DPRINTFN(1,("ehci_init: enabling\n")); 577 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 578 579 return (USBD_NORMAL_COMPLETION); 580 581 #if 0 582 bad2: 583 ehci_free_sqh(sc, sc->sc_async_head); 584 #endif 585 bad1: 586 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 587 return (err); 588 } 589 590 int 591 ehci_intr(void *v) 592 { 593 ehci_softc_t *sc = v; 594 int ret = 0; 595 596 if (sc == NULL) 597 return 0; 598 599 mutex_spin_enter(&sc->sc_intr_lock); 600 601 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 602 goto done; 603 604 /* If we get an interrupt while polling, then just ignore it. */ 605 if (sc->sc_bus.use_polling) { 606 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 607 608 if (intrs) 609 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 610 #ifdef DIAGNOSTIC 611 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 612 #endif 613 goto done; 614 } 615 616 ret = ehci_intr1(sc); 617 618 done: 619 mutex_spin_exit(&sc->sc_intr_lock); 620 return ret; 621 } 622 623 Static int 624 ehci_intr1(ehci_softc_t *sc) 625 { 626 u_int32_t intrs, eintrs; 627 628 DPRINTFN(20,("ehci_intr1: enter\n")); 629 630 /* In case the interrupt occurs before initialization has completed. */ 631 if (sc == NULL) { 632 #ifdef DIAGNOSTIC 633 printf("ehci_intr1: sc == NULL\n"); 634 #endif 635 return (0); 636 } 637 638 KASSERT(mutex_owned(&sc->sc_intr_lock)); 639 640 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 641 if (!intrs) 642 return (0); 643 644 eintrs = intrs & sc->sc_eintrs; 645 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 646 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 647 (u_int)eintrs)); 648 if (!eintrs) 649 return (0); 650 651 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 652 sc->sc_bus.no_intrs++; 653 if (eintrs & EHCI_STS_IAA) { 654 DPRINTF(("ehci_intr1: door bell\n")); 655 kpreempt_disable(); 656 softint_schedule(sc->sc_doorbell_si); 657 kpreempt_enable(); 658 eintrs &= ~EHCI_STS_IAA; 659 } 660 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 661 DPRINTFN(5,("ehci_intr1: %s %s\n", 662 eintrs & EHCI_STS_INT ? "INT" : "", 663 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 664 usb_schedsoftintr(&sc->sc_bus); 665 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 666 } 667 if (eintrs & EHCI_STS_HSE) { 668 printf("%s: unrecoverable error, controller halted\n", 669 device_xname(sc->sc_dev)); 670 /* XXX what else */ 671 } 672 if (eintrs & EHCI_STS_PCD) { 673 kpreempt_disable(); 674 softint_schedule(sc->sc_pcd_si); 675 kpreempt_enable(); 676 eintrs &= ~EHCI_STS_PCD; 677 } 678 679 if (eintrs != 0) { 680 /* Block unprocessed interrupts. */ 681 sc->sc_eintrs &= ~eintrs; 682 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 683 printf("%s: blocking intrs 0x%x\n", 684 device_xname(sc->sc_dev), eintrs); 685 } 686 687 return (1); 688 } 689 690 Static void 691 ehci_doorbell(void *addr) 692 { 693 ehci_softc_t *sc = addr; 694 695 mutex_enter(&sc->sc_lock); 696 cv_broadcast(&sc->sc_doorbell); 697 mutex_exit(&sc->sc_lock); 698 } 699 700 Static void 701 ehci_pcd(void *addr) 702 { 703 ehci_softc_t *sc = addr; 704 usbd_xfer_handle xfer; 705 usbd_pipe_handle pipe; 706 u_char *p; 707 int i, m; 708 709 mutex_enter(&sc->sc_lock); 710 xfer = sc->sc_intrxfer; 711 712 if (xfer == NULL) { 713 /* Just ignore the change. */ 714 goto done; 715 } 716 717 pipe = xfer->pipe; 718 719 p = KERNADDR(&xfer->dmabuf, 0); 720 m = min(sc->sc_noport, xfer->length * 8 - 1); 721 memset(p, 0, xfer->length); 722 for (i = 1; i <= m; i++) { 723 /* Pick out CHANGE bits from the status reg. */ 724 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 725 p[i/8] |= 1 << (i%8); 726 } 727 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 728 xfer->actlen = xfer->length; 729 xfer->status = USBD_NORMAL_COMPLETION; 730 731 usb_transfer_complete(xfer); 732 733 done: 734 mutex_exit(&sc->sc_lock); 735 } 736 737 Static void 738 ehci_softintr(void *v) 739 { 740 struct usbd_bus *bus = v; 741 ehci_softc_t *sc = bus->hci_private; 742 struct ehci_xfer *ex, *nextex; 743 744 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 745 746 DPRINTFN(10,("%s: ehci_softintr\n", device_xname(sc->sc_dev))); 747 748 /* 749 * The only explanation I can think of for why EHCI is as brain dead 750 * as UHCI interrupt-wise is that Intel was involved in both. 751 * An interrupt just tells us that something is done, we have no 752 * clue what, so we need to scan through all active transfers. :-( 753 */ 754 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 755 nextex = TAILQ_NEXT(ex, inext); 756 ehci_check_intr(sc, ex); 757 } 758 759 /* Schedule a callout to catch any dropped transactions. */ 760 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 761 !TAILQ_EMPTY(&sc->sc_intrhead)) 762 callout_reset(&sc->sc_tmo_intrlist, 763 hz, ehci_intrlist_timeout, sc); 764 765 if (sc->sc_softwake) { 766 sc->sc_softwake = 0; 767 cv_broadcast(&sc->sc_softwake_cv); 768 } 769 } 770 771 /* Check for an interrupt. */ 772 Static void 773 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 774 { 775 int attr; 776 777 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 778 779 KASSERT(mutex_owned(&sc->sc_lock)); 780 781 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 782 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 783 ehci_check_itd_intr(sc, ex); 784 else 785 ehci_check_qh_intr(sc, ex); 786 787 return; 788 } 789 790 Static void 791 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 792 { 793 ehci_soft_qtd_t *sqtd, *lsqtd; 794 __uint32_t status; 795 796 KASSERT(mutex_owned(&sc->sc_lock)); 797 798 if (ex->sqtdstart == NULL) { 799 printf("ehci_check_qh_intr: not valid sqtd\n"); 800 return; 801 } 802 803 lsqtd = ex->sqtdend; 804 #ifdef DIAGNOSTIC 805 if (lsqtd == NULL) { 806 printf("ehci_check_qh_intr: lsqtd==0\n"); 807 return; 808 } 809 #endif 810 /* 811 * If the last TD is still active we need to check whether there 812 * is a an error somewhere in the middle, or whether there was a 813 * short packet (SPD and not ACTIVE). 814 */ 815 usb_syncmem(&lsqtd->dma, 816 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 817 sizeof(lsqtd->qtd.qtd_status), 818 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 819 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 820 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 821 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 822 usb_syncmem(&sqtd->dma, 823 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 824 sizeof(sqtd->qtd.qtd_status), 825 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 826 status = le32toh(sqtd->qtd.qtd_status); 827 usb_syncmem(&sqtd->dma, 828 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 829 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 830 /* If there's an active QTD the xfer isn't done. */ 831 if (status & EHCI_QTD_ACTIVE) 832 break; 833 /* Any kind of error makes the xfer done. */ 834 if (status & EHCI_QTD_HALTED) 835 goto done; 836 /* We want short packets, and it is short: it's done */ 837 if (EHCI_QTD_GET_BYTES(status) != 0) 838 goto done; 839 } 840 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 841 ex, ex->sqtdstart)); 842 usb_syncmem(&lsqtd->dma, 843 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 844 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 845 return; 846 } 847 done: 848 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 849 callout_stop(&ex->xfer.timeout_handle); 850 ehci_idone(ex); 851 } 852 853 Static void 854 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 855 { 856 ehci_soft_itd_t *itd; 857 int i; 858 859 KASSERT(mutex_owned(&sc->sc_lock)); 860 861 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 862 return; 863 864 if (ex->itdstart == NULL) { 865 printf("ehci_check_itd_intr: not valid itd\n"); 866 return; 867 } 868 869 itd = ex->itdend; 870 #ifdef DIAGNOSTIC 871 if (itd == NULL) { 872 printf("ehci_check_itd_intr: itdend == 0\n"); 873 return; 874 } 875 #endif 876 877 /* 878 * check no active transfers in last itd, meaning we're finished 879 */ 880 881 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 882 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 883 BUS_DMASYNC_POSTREAD); 884 885 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 886 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 887 break; 888 } 889 890 if (i == EHCI_ITD_NUFRAMES) { 891 goto done; /* All 8 descriptors inactive, it's done */ 892 } 893 894 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 895 ex->itdstart)); 896 return; 897 done: 898 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 899 callout_stop(&ex->xfer.timeout_handle); 900 ehci_idone(ex); 901 } 902 903 Static void 904 ehci_idone(struct ehci_xfer *ex) 905 { 906 usbd_xfer_handle xfer = &ex->xfer; 907 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 908 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 909 ehci_soft_qtd_t *sqtd, *lsqtd; 910 u_int32_t status = 0, nstatus = 0; 911 int actlen; 912 913 KASSERT(mutex_owned(&sc->sc_lock)); 914 915 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 916 917 #ifdef DIAGNOSTIC 918 { 919 if (ex->isdone) { 920 #ifdef EHCI_DEBUG 921 printf("ehci_idone: ex is done!\n "); 922 ehci_dump_exfer(ex); 923 #else 924 printf("ehci_idone: ex=%p is done!\n", ex); 925 #endif 926 return; 927 } 928 ex->isdone = 1; 929 } 930 #endif 931 if (xfer->status == USBD_CANCELLED || 932 xfer->status == USBD_TIMEOUT) { 933 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 934 return; 935 } 936 937 #ifdef EHCI_DEBUG 938 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 939 if (ehcidebug > 10) 940 ehci_dump_sqtds(ex->sqtdstart); 941 #endif 942 943 /* The transfer is done, compute actual length and status. */ 944 945 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 946 == UE_ISOCHRONOUS) { 947 /* Isoc transfer */ 948 struct ehci_soft_itd *itd; 949 int i, nframes, len, uframes; 950 951 nframes = 0; 952 actlen = 0; 953 954 i = xfer->pipe->endpoint->edesc->bInterval; 955 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 956 957 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 958 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 959 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 960 BUS_DMASYNC_POSTREAD); 961 962 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 963 /* XXX - driver didn't fill in the frame full 964 * of uframes. This leads to scheduling 965 * inefficiencies, but working around 966 * this doubles complexity of tracking 967 * an xfer. 968 */ 969 if (nframes >= xfer->nframes) 970 break; 971 972 status = le32toh(itd->itd.itd_ctl[i]); 973 len = EHCI_ITD_GET_LEN(status); 974 if (EHCI_ITD_GET_STATUS(status) != 0) 975 len = 0; /*No valid data on error*/ 976 977 xfer->frlengths[nframes++] = len; 978 actlen += len; 979 } 980 981 if (nframes >= xfer->nframes) 982 break; 983 } 984 985 xfer->actlen = actlen; 986 xfer->status = USBD_NORMAL_COMPLETION; 987 goto end; 988 } 989 990 /* Continue processing xfers using queue heads */ 991 992 lsqtd = ex->sqtdend; 993 actlen = 0; 994 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 995 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 996 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 997 nstatus = le32toh(sqtd->qtd.qtd_status); 998 if (nstatus & EHCI_QTD_ACTIVE) 999 break; 1000 1001 status = nstatus; 1002 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1003 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1004 } 1005 1006 1007 /* 1008 * If there are left over TDs we need to update the toggle. 1009 * The default pipe doesn't need it since control transfers 1010 * start the toggle at 0 every time. 1011 * For a short transfer we need to update the toggle for the missing 1012 * packets within the qTD. 1013 */ 1014 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1015 xfer->pipe->device->default_pipe != xfer->pipe) { 1016 DPRINTFN(2, ("ehci_idone: need toggle update " 1017 "status=%08x nstatus=%08x\n", status, nstatus)); 1018 #if 0 1019 ehci_dump_sqh(epipe->sqh); 1020 ehci_dump_sqtds(ex->sqtdstart); 1021 #endif 1022 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1023 } 1024 1025 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 1026 xfer->length, actlen, status)); 1027 xfer->actlen = actlen; 1028 if (status & EHCI_QTD_HALTED) { 1029 #ifdef EHCI_DEBUG 1030 char sbuf[128]; 1031 1032 snprintb(sbuf, sizeof(sbuf), 1033 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 1034 (u_int32_t)status); 1035 1036 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 1037 "status 0x%s\n", 1038 xfer->pipe->device->address, 1039 xfer->pipe->endpoint->edesc->bEndpointAddress, 1040 sbuf)); 1041 if (ehcidebug > 2) { 1042 ehci_dump_sqh(epipe->sqh); 1043 ehci_dump_sqtds(ex->sqtdstart); 1044 } 1045 #endif 1046 /* low&full speed has an extra error flag */ 1047 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1048 EHCI_QH_SPEED_HIGH) 1049 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1050 else 1051 status &= EHCI_QTD_STATERRS; 1052 if (status == 0) /* no other errors means a stall */ { 1053 xfer->status = USBD_STALLED; 1054 } else { 1055 xfer->status = USBD_IOERROR; /* more info XXX */ 1056 } 1057 /* XXX need to reset TT on missed microframe */ 1058 if (status & EHCI_QTD_MISSEDMICRO) { 1059 printf("%s: missed microframe, TT reset not " 1060 "implemented, hub might be inoperational\n", 1061 device_xname(sc->sc_dev)); 1062 } 1063 } else { 1064 xfer->status = USBD_NORMAL_COMPLETION; 1065 } 1066 1067 end: 1068 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1069 * during this call, before methods->done is called: dma sync required 1070 * beforehand? */ 1071 usb_transfer_complete(xfer); 1072 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1073 } 1074 1075 /* 1076 * Wait here until controller claims to have an interrupt. 1077 * Then call ehci_intr and return. Use timeout to avoid waiting 1078 * too long. 1079 */ 1080 Static void 1081 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1082 { 1083 int timo; 1084 u_int32_t intrs; 1085 1086 xfer->status = USBD_IN_PROGRESS; 1087 for (timo = xfer->timeout; timo >= 0; timo--) { 1088 usb_delay_ms(&sc->sc_bus, 1); 1089 if (sc->sc_dying) 1090 break; 1091 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1092 sc->sc_eintrs; 1093 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1094 #ifdef EHCI_DEBUG 1095 if (ehcidebug > 15) 1096 ehci_dump_regs(sc); 1097 #endif 1098 if (intrs) { 1099 mutex_spin_enter(&sc->sc_intr_lock); 1100 ehci_intr1(sc); 1101 mutex_spin_exit(&sc->sc_intr_lock); 1102 if (xfer->status != USBD_IN_PROGRESS) 1103 return; 1104 } 1105 } 1106 1107 /* Timeout */ 1108 DPRINTF(("ehci_waitintr: timeout\n")); 1109 xfer->status = USBD_TIMEOUT; 1110 mutex_enter(&sc->sc_lock); 1111 usb_transfer_complete(xfer); 1112 mutex_exit(&sc->sc_lock); 1113 /* XXX should free TD */ 1114 } 1115 1116 Static void 1117 ehci_poll(struct usbd_bus *bus) 1118 { 1119 ehci_softc_t *sc = bus->hci_private; 1120 #ifdef EHCI_DEBUG 1121 static int last; 1122 int new; 1123 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1124 if (new != last) { 1125 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1126 last = new; 1127 } 1128 #endif 1129 1130 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1131 mutex_spin_enter(&sc->sc_intr_lock); 1132 ehci_intr1(sc); 1133 mutex_spin_exit(&sc->sc_intr_lock); 1134 } 1135 } 1136 1137 void 1138 ehci_childdet(device_t self, device_t child) 1139 { 1140 struct ehci_softc *sc = device_private(self); 1141 1142 KASSERT(sc->sc_child == child); 1143 sc->sc_child = NULL; 1144 } 1145 1146 int 1147 ehci_detach(struct ehci_softc *sc, int flags) 1148 { 1149 usbd_xfer_handle xfer; 1150 int rv = 0; 1151 1152 if (sc->sc_child != NULL) 1153 rv = config_detach(sc->sc_child, flags); 1154 1155 if (rv != 0) 1156 return (rv); 1157 1158 callout_halt(&sc->sc_tmo_intrlist, NULL); 1159 callout_destroy(&sc->sc_tmo_intrlist); 1160 1161 /* XXX free other data structures XXX */ 1162 if (sc->sc_softitds) 1163 kmem_free(sc->sc_softitds, 1164 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1165 cv_destroy(&sc->sc_doorbell); 1166 cv_destroy(&sc->sc_softwake_cv); 1167 1168 softint_disestablish(sc->sc_doorbell_si); 1169 softint_disestablish(sc->sc_pcd_si); 1170 1171 while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 1172 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1173 kmem_free(xfer, sizeof(struct ehci_xfer)); 1174 } 1175 1176 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1177 1178 return (rv); 1179 } 1180 1181 1182 int 1183 ehci_activate(device_t self, enum devact act) 1184 { 1185 struct ehci_softc *sc = device_private(self); 1186 1187 switch (act) { 1188 case DVACT_DEACTIVATE: 1189 sc->sc_dying = 1; 1190 return 0; 1191 default: 1192 return EOPNOTSUPP; 1193 } 1194 } 1195 1196 /* 1197 * Handle suspend/resume. 1198 * 1199 * We need to switch to polling mode here, because this routine is 1200 * called from an interrupt context. This is all right since we 1201 * are almost suspended anyway. 1202 * 1203 * Note that this power handler isn't to be registered directly; the 1204 * bus glue needs to call out to it. 1205 */ 1206 bool 1207 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1208 { 1209 ehci_softc_t *sc = device_private(dv); 1210 int i; 1211 uint32_t cmd, hcr; 1212 1213 mutex_spin_enter(&sc->sc_intr_lock); 1214 sc->sc_bus.use_polling++; 1215 mutex_spin_exit(&sc->sc_intr_lock); 1216 1217 for (i = 1; i <= sc->sc_noport; i++) { 1218 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1219 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1220 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1221 } 1222 1223 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1224 1225 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1226 EOWRITE4(sc, EHCI_USBCMD, cmd); 1227 1228 for (i = 0; i < 100; i++) { 1229 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1230 if (hcr == 0) 1231 break; 1232 1233 usb_delay_ms(&sc->sc_bus, 1); 1234 } 1235 if (hcr != 0) 1236 printf("%s: reset timeout\n", device_xname(dv)); 1237 1238 cmd &= ~EHCI_CMD_RS; 1239 EOWRITE4(sc, EHCI_USBCMD, cmd); 1240 1241 for (i = 0; i < 100; i++) { 1242 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1243 if (hcr == EHCI_STS_HCH) 1244 break; 1245 1246 usb_delay_ms(&sc->sc_bus, 1); 1247 } 1248 if (hcr != EHCI_STS_HCH) 1249 printf("%s: config timeout\n", device_xname(dv)); 1250 1251 mutex_spin_enter(&sc->sc_intr_lock); 1252 sc->sc_bus.use_polling--; 1253 mutex_spin_exit(&sc->sc_intr_lock); 1254 1255 return true; 1256 } 1257 1258 bool 1259 ehci_resume(device_t dv, const pmf_qual_t *qual) 1260 { 1261 ehci_softc_t *sc = device_private(dv); 1262 int i; 1263 uint32_t cmd, hcr; 1264 1265 /* restore things in case the bios sucks */ 1266 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1267 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1268 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1269 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1270 1271 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1272 1273 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1274 1275 hcr = 0; 1276 for (i = 1; i <= sc->sc_noport; i++) { 1277 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1278 if ((cmd & EHCI_PS_PO) == 0 && 1279 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1280 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1281 hcr = 1; 1282 } 1283 } 1284 1285 if (hcr) { 1286 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1287 1288 for (i = 1; i <= sc->sc_noport; i++) { 1289 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1290 if ((cmd & EHCI_PS_PO) == 0 && 1291 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1292 EOWRITE4(sc, EHCI_PORTSC(i), 1293 cmd & ~EHCI_PS_FPR); 1294 } 1295 } 1296 1297 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1298 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1299 1300 for (i = 0; i < 100; i++) { 1301 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1302 if (hcr != EHCI_STS_HCH) 1303 break; 1304 1305 usb_delay_ms(&sc->sc_bus, 1); 1306 } 1307 if (hcr == EHCI_STS_HCH) 1308 printf("%s: config timeout\n", device_xname(dv)); 1309 1310 return true; 1311 } 1312 1313 /* 1314 * Shut down the controller when the system is going down. 1315 */ 1316 bool 1317 ehci_shutdown(device_t self, int flags) 1318 { 1319 ehci_softc_t *sc = device_private(self); 1320 1321 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1322 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1323 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1324 return true; 1325 } 1326 1327 Static usbd_status 1328 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1329 { 1330 struct ehci_softc *sc = bus->hci_private; 1331 usbd_status err; 1332 1333 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1334 if (err == USBD_NOMEM) 1335 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1336 #ifdef EHCI_DEBUG 1337 if (err) 1338 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1339 #endif 1340 return (err); 1341 } 1342 1343 Static void 1344 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1345 { 1346 struct ehci_softc *sc = bus->hci_private; 1347 1348 if (dma->block->flags & USB_DMA_RESERVE) { 1349 usb_reserve_freem(&sc->sc_dma_reserve, 1350 dma); 1351 return; 1352 } 1353 usb_freemem(&sc->sc_bus, dma); 1354 } 1355 1356 Static usbd_xfer_handle 1357 ehci_allocx(struct usbd_bus *bus) 1358 { 1359 struct ehci_softc *sc = bus->hci_private; 1360 usbd_xfer_handle xfer; 1361 1362 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1363 if (xfer != NULL) { 1364 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1365 #ifdef DIAGNOSTIC 1366 if (xfer->busy_free != XFER_FREE) { 1367 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1368 xfer->busy_free); 1369 } 1370 #endif 1371 } else { 1372 xfer = kmem_alloc(sizeof(struct ehci_xfer), KM_SLEEP); 1373 } 1374 if (xfer != NULL) { 1375 memset(xfer, 0, sizeof(struct ehci_xfer)); 1376 #ifdef DIAGNOSTIC 1377 EXFER(xfer)->isdone = 1; 1378 xfer->busy_free = XFER_BUSY; 1379 #endif 1380 } 1381 return (xfer); 1382 } 1383 1384 Static void 1385 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1386 { 1387 struct ehci_softc *sc = bus->hci_private; 1388 1389 #ifdef DIAGNOSTIC 1390 if (xfer->busy_free != XFER_BUSY) { 1391 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1392 xfer->busy_free); 1393 } 1394 xfer->busy_free = XFER_FREE; 1395 if (!EXFER(xfer)->isdone) { 1396 printf("ehci_freex: !isdone\n"); 1397 } 1398 #endif 1399 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1400 } 1401 1402 Static void 1403 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1404 { 1405 struct ehci_softc *sc = bus->hci_private; 1406 1407 *lock = &sc->sc_lock; 1408 } 1409 1410 Static void 1411 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1412 { 1413 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1414 1415 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1416 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1417 #ifdef EHCI_DEBUG 1418 if (ehcidebug) 1419 usbd_dump_pipe(pipe); 1420 #endif 1421 epipe->nexttoggle = 0; 1422 } 1423 1424 Static void 1425 ehci_noop(usbd_pipe_handle pipe) 1426 { 1427 } 1428 1429 #ifdef EHCI_DEBUG 1430 Static void 1431 ehci_dump_regs(ehci_softc_t *sc) 1432 { 1433 int i; 1434 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1435 EOREAD4(sc, EHCI_USBCMD), 1436 EOREAD4(sc, EHCI_USBSTS), 1437 EOREAD4(sc, EHCI_USBINTR)); 1438 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1439 EOREAD4(sc, EHCI_FRINDEX), 1440 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1441 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1442 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1443 for (i = 1; i <= sc->sc_noport; i++) 1444 printf("port %d status=0x%08x\n", i, 1445 EOREAD4(sc, EHCI_PORTSC(i))); 1446 } 1447 1448 /* 1449 * Unused function - this is meant to be called from a kernel 1450 * debugger. 1451 */ 1452 void 1453 ehci_dump(void) 1454 { 1455 ehci_dump_regs(theehci); 1456 } 1457 1458 Static void 1459 ehci_dump_link(ehci_link_t link, int type) 1460 { 1461 link = le32toh(link); 1462 printf("0x%08x", link); 1463 if (link & EHCI_LINK_TERMINATE) 1464 printf("<T>"); 1465 else { 1466 printf("<"); 1467 if (type) { 1468 switch (EHCI_LINK_TYPE(link)) { 1469 case EHCI_LINK_ITD: printf("ITD"); break; 1470 case EHCI_LINK_QH: printf("QH"); break; 1471 case EHCI_LINK_SITD: printf("SITD"); break; 1472 case EHCI_LINK_FSTN: printf("FSTN"); break; 1473 } 1474 } 1475 printf(">"); 1476 } 1477 } 1478 1479 Static void 1480 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1481 { 1482 int i; 1483 u_int32_t stop; 1484 1485 stop = 0; 1486 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1487 ehci_dump_sqtd(sqtd); 1488 usb_syncmem(&sqtd->dma, 1489 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1490 sizeof(sqtd->qtd), 1491 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1492 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1493 usb_syncmem(&sqtd->dma, 1494 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1495 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1496 } 1497 if (sqtd) 1498 printf("dump aborted, too many TDs\n"); 1499 } 1500 1501 Static void 1502 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1503 { 1504 usb_syncmem(&sqtd->dma, sqtd->offs, 1505 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1506 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1507 ehci_dump_qtd(&sqtd->qtd); 1508 usb_syncmem(&sqtd->dma, sqtd->offs, 1509 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1510 } 1511 1512 Static void 1513 ehci_dump_qtd(ehci_qtd_t *qtd) 1514 { 1515 u_int32_t s; 1516 char sbuf[128]; 1517 1518 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1519 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1520 printf("\n"); 1521 s = le32toh(qtd->qtd_status); 1522 snprintb(sbuf, sizeof(sbuf), 1523 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1524 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1525 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1526 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1527 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1528 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1529 EHCI_QTD_GET_PID(s), sbuf); 1530 for (s = 0; s < 5; s++) 1531 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1532 } 1533 1534 Static void 1535 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1536 { 1537 ehci_qh_t *qh = &sqh->qh; 1538 u_int32_t endp, endphub; 1539 1540 usb_syncmem(&sqh->dma, sqh->offs, 1541 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1542 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1543 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1544 endp = le32toh(qh->qh_endp); 1545 printf(" endp=0x%08x\n", endp); 1546 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1547 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1548 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1549 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1550 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1551 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1552 EHCI_QH_GET_NRL(endp)); 1553 endphub = le32toh(qh->qh_endphub); 1554 printf(" endphub=0x%08x\n", endphub); 1555 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1556 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1557 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1558 EHCI_QH_GET_MULT(endphub)); 1559 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1560 printf("Overlay qTD:\n"); 1561 ehci_dump_qtd(&qh->qh_qtd); 1562 usb_syncmem(&sqh->dma, sqh->offs, 1563 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1564 } 1565 1566 #if notyet 1567 Static void 1568 ehci_dump_itd(struct ehci_soft_itd *itd) 1569 { 1570 ehci_isoc_trans_t t; 1571 ehci_isoc_bufr_ptr_t b, b2, b3; 1572 int i; 1573 1574 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1575 1576 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1577 t = le32toh(itd->itd.itd_ctl[i]); 1578 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1579 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1580 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1581 EHCI_ITD_GET_OFFS(t)); 1582 } 1583 printf("ITDbufr: "); 1584 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1585 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1586 1587 b = le32toh(itd->itd.itd_bufr[0]); 1588 b2 = le32toh(itd->itd.itd_bufr[1]); 1589 b3 = le32toh(itd->itd.itd_bufr[2]); 1590 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1591 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1592 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1593 } 1594 1595 Static void 1596 ehci_dump_sitd(struct ehci_soft_itd *itd) 1597 { 1598 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1599 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1600 itd->xfer_next, itd->physaddr, itd->slot); 1601 } 1602 #endif 1603 1604 #ifdef DIAGNOSTIC 1605 Static void 1606 ehci_dump_exfer(struct ehci_xfer *ex) 1607 { 1608 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1609 } 1610 #endif 1611 #endif 1612 1613 Static usbd_status 1614 ehci_open(usbd_pipe_handle pipe) 1615 { 1616 usbd_device_handle dev = pipe->device; 1617 ehci_softc_t *sc = dev->bus->hci_private; 1618 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1619 u_int8_t addr = dev->address; 1620 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1621 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1622 ehci_soft_qh_t *sqh; 1623 usbd_status err; 1624 int ival, speed, naks; 1625 int hshubaddr, hshubport; 1626 1627 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1628 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1629 1630 if (dev->myhsport) { 1631 /* 1632 * When directly attached FS/LS device while doing embedded 1633 * transaction translations and we are the hub, set the hub 1634 * adddress to 0 (us). 1635 */ 1636 if (!(sc->sc_flags & EHCIF_ETTF) 1637 || (dev->myhsport->parent->address != sc->sc_addr)) { 1638 hshubaddr = dev->myhsport->parent->address; 1639 } else { 1640 hshubaddr = 0; 1641 } 1642 hshubport = dev->myhsport->portno; 1643 } else { 1644 hshubaddr = 0; 1645 hshubport = 0; 1646 } 1647 1648 if (sc->sc_dying) 1649 return (USBD_IOERROR); 1650 1651 /* toggle state needed for bulk endpoints */ 1652 epipe->nexttoggle = pipe->endpoint->datatoggle; 1653 1654 if (addr == sc->sc_addr) { 1655 switch (ed->bEndpointAddress) { 1656 case USB_CONTROL_ENDPOINT: 1657 pipe->methods = &ehci_root_ctrl_methods; 1658 break; 1659 case UE_DIR_IN | EHCI_INTR_ENDPT: 1660 pipe->methods = &ehci_root_intr_methods; 1661 break; 1662 default: 1663 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1664 ed->bEndpointAddress)); 1665 return (USBD_INVAL); 1666 } 1667 return (USBD_NORMAL_COMPLETION); 1668 } 1669 1670 /* XXX All this stuff is only valid for async. */ 1671 switch (dev->speed) { 1672 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1673 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1674 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1675 default: panic("ehci_open: bad device speed %d", dev->speed); 1676 } 1677 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1678 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1679 "isoc endpoint.\n"); 1680 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1681 "attached to a USB2 hub, and transaction translations are " 1682 "not yet supported.\n"); 1683 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1684 "root hub instead.\n"); 1685 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1686 hshubaddr, hshubport)); 1687 return USBD_INVAL; 1688 } 1689 1690 /* 1691 * For interrupt transfer, nak throttling must be disabled, but for 1692 * the other transfer type, nak throttling should be enabled from the 1693 * veiwpoint that avoids the memory thrashing. 1694 */ 1695 naks = (xfertype == UE_INTERRUPT) ? 0 1696 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1697 1698 /* Allocate sqh for everything, save isoc xfers */ 1699 if (xfertype != UE_ISOCHRONOUS) { 1700 sqh = ehci_alloc_sqh(sc); 1701 if (sqh == NULL) 1702 return (USBD_NOMEM); 1703 /* qh_link filled when the QH is added */ 1704 sqh->qh.qh_endp = htole32( 1705 EHCI_QH_SET_ADDR(addr) | 1706 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1707 EHCI_QH_SET_EPS(speed) | 1708 EHCI_QH_DTC | 1709 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1710 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1711 EHCI_QH_CTL : 0) | 1712 EHCI_QH_SET_NRL(naks) 1713 ); 1714 sqh->qh.qh_endphub = htole32( 1715 EHCI_QH_SET_MULT(1) | 1716 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1717 ); 1718 if (speed != EHCI_QH_SPEED_HIGH) 1719 sqh->qh.qh_endphub |= htole32( 1720 EHCI_QH_SET_PORT(hshubport) | 1721 EHCI_QH_SET_HUBA(hshubaddr) | 1722 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1723 ); 1724 sqh->qh.qh_curqtd = EHCI_NULL; 1725 /* Fill the overlay qTD */ 1726 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1727 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1728 sqh->qh.qh_qtd.qtd_status = htole32(0); 1729 1730 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1731 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1732 epipe->sqh = sqh; 1733 } else { 1734 sqh = NULL; 1735 } /*xfertype == UE_ISOC*/ 1736 1737 switch (xfertype) { 1738 case UE_CONTROL: 1739 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1740 0, &epipe->u.ctl.reqdma); 1741 #ifdef EHCI_DEBUG 1742 if (err) 1743 printf("ehci_open: usb_allocmem()=%d\n", err); 1744 #endif 1745 if (err) 1746 goto bad; 1747 pipe->methods = &ehci_device_ctrl_methods; 1748 mutex_enter(&sc->sc_lock); 1749 ehci_add_qh(sc, sqh, sc->sc_async_head); 1750 mutex_exit(&sc->sc_lock); 1751 break; 1752 case UE_BULK: 1753 pipe->methods = &ehci_device_bulk_methods; 1754 mutex_enter(&sc->sc_lock); 1755 ehci_add_qh(sc, sqh, sc->sc_async_head); 1756 mutex_exit(&sc->sc_lock); 1757 break; 1758 case UE_INTERRUPT: 1759 pipe->methods = &ehci_device_intr_methods; 1760 ival = pipe->interval; 1761 if (ival == USBD_DEFAULT_INTERVAL) { 1762 if (speed == EHCI_QH_SPEED_HIGH) { 1763 if (ed->bInterval > 16) { 1764 /* 1765 * illegal with high-speed, but there 1766 * were documentation bugs in the spec, 1767 * so be generous 1768 */ 1769 ival = 256; 1770 } else 1771 ival = (1 << (ed->bInterval - 1)) / 8; 1772 } else 1773 ival = ed->bInterval; 1774 } 1775 err = ehci_device_setintr(sc, sqh, ival); 1776 if (err) 1777 goto bad; 1778 break; 1779 case UE_ISOCHRONOUS: 1780 pipe->methods = &ehci_device_isoc_methods; 1781 if (ed->bInterval == 0 || ed->bInterval > 16) { 1782 printf("ehci: opening pipe with invalid bInterval\n"); 1783 err = USBD_INVAL; 1784 goto bad; 1785 } 1786 if (UGETW(ed->wMaxPacketSize) == 0) { 1787 printf("ehci: zero length endpoint open request\n"); 1788 err = USBD_INVAL; 1789 goto bad; 1790 } 1791 epipe->u.isoc.next_frame = 0; 1792 epipe->u.isoc.cur_xfers = 0; 1793 break; 1794 default: 1795 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1796 err = USBD_INVAL; 1797 goto bad; 1798 } 1799 return (USBD_NORMAL_COMPLETION); 1800 1801 bad: 1802 if (sqh != NULL) 1803 ehci_free_sqh(sc, sqh); 1804 return (err); 1805 } 1806 1807 /* 1808 * Add an ED to the schedule. Called with USB lock held. 1809 */ 1810 Static void 1811 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1812 { 1813 1814 KASSERT(mutex_owned(&sc->sc_lock)); 1815 1816 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1817 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1818 sqh->next = head->next; 1819 sqh->qh.qh_link = head->qh.qh_link; 1820 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1821 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1822 head->next = sqh; 1823 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1824 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1825 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1826 1827 #ifdef EHCI_DEBUG 1828 if (ehcidebug > 5) { 1829 printf("ehci_add_qh:\n"); 1830 ehci_dump_sqh(sqh); 1831 } 1832 #endif 1833 } 1834 1835 /* 1836 * Remove an ED from the schedule. Called with USB lock held. 1837 */ 1838 Static void 1839 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1840 { 1841 ehci_soft_qh_t *p; 1842 1843 KASSERT(mutex_owned(&sc->sc_lock)); 1844 1845 /* XXX */ 1846 for (p = head; p != NULL && p->next != sqh; p = p->next) 1847 ; 1848 if (p == NULL) 1849 panic("ehci_rem_qh: ED not found"); 1850 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1851 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1852 p->next = sqh->next; 1853 p->qh.qh_link = sqh->qh.qh_link; 1854 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1855 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1856 1857 ehci_sync_hc(sc); 1858 } 1859 1860 Static void 1861 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1862 { 1863 int i; 1864 u_int32_t status; 1865 1866 /* Save toggle bit and ping status. */ 1867 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1868 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1869 status = sqh->qh.qh_qtd.qtd_status & 1870 htole32(EHCI_QTD_TOGGLE_MASK | 1871 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1872 /* Set HALTED to make hw leave it alone. */ 1873 sqh->qh.qh_qtd.qtd_status = 1874 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1875 usb_syncmem(&sqh->dma, 1876 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1877 sizeof(sqh->qh.qh_qtd.qtd_status), 1878 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1879 sqh->qh.qh_curqtd = 0; 1880 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1881 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1882 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1883 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1884 sqh->sqtd = sqtd; 1885 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1886 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1887 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1888 sqh->qh.qh_qtd.qtd_status = status; 1889 usb_syncmem(&sqh->dma, 1890 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1891 sizeof(sqh->qh.qh_qtd.qtd_status), 1892 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1893 } 1894 1895 /* 1896 * Ensure that the HC has released all references to the QH. We do this 1897 * by asking for a Async Advance Doorbell interrupt and then we wait for 1898 * the interrupt. 1899 * To make this easier we first obtain exclusive use of the doorbell. 1900 */ 1901 Static void 1902 ehci_sync_hc(ehci_softc_t *sc) 1903 { 1904 int error; 1905 1906 KASSERT(mutex_owned(&sc->sc_lock)); 1907 1908 if (sc->sc_dying) { 1909 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1910 return; 1911 } 1912 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1913 /* ask for doorbell */ 1914 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1915 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1916 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1917 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 1918 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1919 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1920 #ifdef DIAGNOSTIC 1921 if (error) 1922 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 1923 #endif 1924 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1925 } 1926 1927 Static void 1928 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1929 { 1930 struct ehci_soft_itd *itd, *prev; 1931 1932 prev = NULL; 1933 1934 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1935 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1936 1937 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1938 prev = itd->u.frame_list.prev; 1939 /* Unlink itd from hardware chain, or frame array */ 1940 if (prev == NULL) { /* We're at the table head */ 1941 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1942 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1943 usb_syncmem(&sc->sc_fldma, 1944 sizeof(ehci_link_t) * itd->slot, 1945 sizeof(ehci_link_t), 1946 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1947 1948 if (itd->u.frame_list.next != NULL) 1949 itd->u.frame_list.next->u.frame_list.prev = NULL; 1950 } else { 1951 /* XXX this part is untested... */ 1952 prev->itd.itd_next = itd->itd.itd_next; 1953 usb_syncmem(&itd->dma, 1954 itd->offs + offsetof(ehci_itd_t, itd_next), 1955 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1956 1957 prev->u.frame_list.next = itd->u.frame_list.next; 1958 if (itd->u.frame_list.next != NULL) 1959 itd->u.frame_list.next->u.frame_list.prev = prev; 1960 } 1961 } 1962 1963 prev = NULL; 1964 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1965 if (prev != NULL) 1966 ehci_free_itd(sc, prev); 1967 prev = itd; 1968 } 1969 if (prev) 1970 ehci_free_itd(sc, prev); 1971 exfer->itdstart = NULL; 1972 exfer->itdend = NULL; 1973 } 1974 1975 /***********/ 1976 1977 /* 1978 * Data structures and routines to emulate the root hub. 1979 */ 1980 Static usb_device_descriptor_t ehci_devd = { 1981 USB_DEVICE_DESCRIPTOR_SIZE, 1982 UDESC_DEVICE, /* type */ 1983 {0x00, 0x02}, /* USB version */ 1984 UDCLASS_HUB, /* class */ 1985 UDSUBCLASS_HUB, /* subclass */ 1986 UDPROTO_HSHUBSTT, /* protocol */ 1987 64, /* max packet */ 1988 {0},{0},{0x00,0x01}, /* device id */ 1989 1,2,0, /* string indicies */ 1990 1 /* # of configurations */ 1991 }; 1992 1993 Static const usb_device_qualifier_t ehci_odevd = { 1994 USB_DEVICE_DESCRIPTOR_SIZE, 1995 UDESC_DEVICE_QUALIFIER, /* type */ 1996 {0x00, 0x02}, /* USB version */ 1997 UDCLASS_HUB, /* class */ 1998 UDSUBCLASS_HUB, /* subclass */ 1999 UDPROTO_FSHUB, /* protocol */ 2000 64, /* max packet */ 2001 1, /* # of configurations */ 2002 0 2003 }; 2004 2005 Static const usb_config_descriptor_t ehci_confd = { 2006 USB_CONFIG_DESCRIPTOR_SIZE, 2007 UDESC_CONFIG, 2008 {USB_CONFIG_DESCRIPTOR_SIZE + 2009 USB_INTERFACE_DESCRIPTOR_SIZE + 2010 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2011 1, 2012 1, 2013 0, 2014 UC_ATTR_MBO | UC_SELF_POWERED, 2015 0 /* max power */ 2016 }; 2017 2018 Static const usb_interface_descriptor_t ehci_ifcd = { 2019 USB_INTERFACE_DESCRIPTOR_SIZE, 2020 UDESC_INTERFACE, 2021 0, 2022 0, 2023 1, 2024 UICLASS_HUB, 2025 UISUBCLASS_HUB, 2026 UIPROTO_HSHUBSTT, 2027 0 2028 }; 2029 2030 Static const usb_endpoint_descriptor_t ehci_endpd = { 2031 USB_ENDPOINT_DESCRIPTOR_SIZE, 2032 UDESC_ENDPOINT, 2033 UE_DIR_IN | EHCI_INTR_ENDPT, 2034 UE_INTERRUPT, 2035 {8, 0}, /* max packet */ 2036 12 2037 }; 2038 2039 Static const usb_hub_descriptor_t ehci_hubd = { 2040 USB_HUB_DESCRIPTOR_SIZE, 2041 UDESC_HUB, 2042 0, 2043 {0,0}, 2044 0, 2045 0, 2046 {""}, 2047 {""}, 2048 }; 2049 2050 /* 2051 * Simulate a hardware hub by handling all the necessary requests. 2052 */ 2053 Static usbd_status 2054 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2055 { 2056 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2057 usbd_status err; 2058 2059 /* Insert last in queue. */ 2060 mutex_enter(&sc->sc_lock); 2061 err = usb_insert_transfer(xfer); 2062 mutex_exit(&sc->sc_lock); 2063 if (err) 2064 return (err); 2065 2066 /* Pipe isn't running, start first */ 2067 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2068 } 2069 2070 Static usbd_status 2071 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2072 { 2073 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2074 usb_device_request_t *req; 2075 void *buf = NULL; 2076 int port, i; 2077 int len, value, index, l, totlen = 0; 2078 usb_port_status_t ps; 2079 usb_hub_descriptor_t hubd; 2080 usbd_status err; 2081 u_int32_t v; 2082 2083 if (sc->sc_dying) 2084 return (USBD_IOERROR); 2085 2086 #ifdef DIAGNOSTIC 2087 if (!(xfer->rqflags & URQ_REQUEST)) 2088 /* XXX panic */ 2089 return (USBD_INVAL); 2090 #endif 2091 req = &xfer->request; 2092 2093 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2094 req->bmRequestType, req->bRequest)); 2095 2096 len = UGETW(req->wLength); 2097 value = UGETW(req->wValue); 2098 index = UGETW(req->wIndex); 2099 2100 if (len != 0) 2101 buf = KERNADDR(&xfer->dmabuf, 0); 2102 2103 #define C(x,y) ((x) | ((y) << 8)) 2104 switch(C(req->bRequest, req->bmRequestType)) { 2105 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2106 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2107 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2108 /* 2109 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2110 * for the integrated root hub. 2111 */ 2112 break; 2113 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2114 if (len > 0) { 2115 *(u_int8_t *)buf = sc->sc_conf; 2116 totlen = 1; 2117 } 2118 break; 2119 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2120 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2121 if (len == 0) 2122 break; 2123 switch(value >> 8) { 2124 case UDESC_DEVICE: 2125 if ((value & 0xff) != 0) { 2126 err = USBD_IOERROR; 2127 goto ret; 2128 } 2129 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2130 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2131 memcpy(buf, &ehci_devd, l); 2132 break; 2133 /* 2134 * We can't really operate at another speed, but the spec says 2135 * we need this descriptor. 2136 */ 2137 case UDESC_DEVICE_QUALIFIER: 2138 if ((value & 0xff) != 0) { 2139 err = USBD_IOERROR; 2140 goto ret; 2141 } 2142 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2143 memcpy(buf, &ehci_odevd, l); 2144 break; 2145 /* 2146 * We can't really operate at another speed, but the spec says 2147 * we need this descriptor. 2148 */ 2149 case UDESC_OTHER_SPEED_CONFIGURATION: 2150 case UDESC_CONFIG: 2151 if ((value & 0xff) != 0) { 2152 err = USBD_IOERROR; 2153 goto ret; 2154 } 2155 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2156 memcpy(buf, &ehci_confd, l); 2157 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2158 value >> 8; 2159 buf = (char *)buf + l; 2160 len -= l; 2161 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2162 totlen += l; 2163 memcpy(buf, &ehci_ifcd, l); 2164 buf = (char *)buf + l; 2165 len -= l; 2166 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2167 totlen += l; 2168 memcpy(buf, &ehci_endpd, l); 2169 break; 2170 case UDESC_STRING: 2171 #define sd ((usb_string_descriptor_t *)buf) 2172 switch (value & 0xff) { 2173 case 0: /* Language table */ 2174 totlen = usb_makelangtbl(sd, len); 2175 break; 2176 case 1: /* Vendor */ 2177 totlen = usb_makestrdesc(sd, len, 2178 sc->sc_vendor); 2179 break; 2180 case 2: /* Product */ 2181 totlen = usb_makestrdesc(sd, len, 2182 "EHCI root hub"); 2183 break; 2184 } 2185 #undef sd 2186 break; 2187 default: 2188 err = USBD_IOERROR; 2189 goto ret; 2190 } 2191 break; 2192 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2193 if (len > 0) { 2194 *(u_int8_t *)buf = 0; 2195 totlen = 1; 2196 } 2197 break; 2198 case C(UR_GET_STATUS, UT_READ_DEVICE): 2199 if (len > 1) { 2200 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2201 totlen = 2; 2202 } 2203 break; 2204 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2205 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2206 if (len > 1) { 2207 USETW(((usb_status_t *)buf)->wStatus, 0); 2208 totlen = 2; 2209 } 2210 break; 2211 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2212 if (value >= USB_MAX_DEVICES) { 2213 err = USBD_IOERROR; 2214 goto ret; 2215 } 2216 sc->sc_addr = value; 2217 break; 2218 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2219 if (value != 0 && value != 1) { 2220 err = USBD_IOERROR; 2221 goto ret; 2222 } 2223 sc->sc_conf = value; 2224 break; 2225 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2226 break; 2227 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2228 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2229 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2230 err = USBD_IOERROR; 2231 goto ret; 2232 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2233 break; 2234 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2235 break; 2236 /* Hub requests */ 2237 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2238 break; 2239 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2240 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2241 "port=%d feature=%d\n", 2242 index, value)); 2243 if (index < 1 || index > sc->sc_noport) { 2244 err = USBD_IOERROR; 2245 goto ret; 2246 } 2247 port = EHCI_PORTSC(index); 2248 v = EOREAD4(sc, port); 2249 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2250 v &= ~EHCI_PS_CLEAR; 2251 switch(value) { 2252 case UHF_PORT_ENABLE: 2253 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2254 break; 2255 case UHF_PORT_SUSPEND: 2256 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2257 break; 2258 v &= ~EHCI_PS_SUSP; 2259 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2260 /* see USB2 spec ch. 7.1.7.7 */ 2261 usb_delay_ms(&sc->sc_bus, 20); 2262 EOWRITE4(sc, port, v); 2263 usb_delay_ms(&sc->sc_bus, 2); 2264 #ifdef DEBUG 2265 v = EOREAD4(sc, port); 2266 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2267 printf("ehci: resume failed: %x\n", v); 2268 #endif 2269 break; 2270 case UHF_PORT_POWER: 2271 if (sc->sc_hasppc) 2272 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2273 break; 2274 case UHF_PORT_TEST: 2275 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2276 "%d\n", index)); 2277 break; 2278 case UHF_PORT_INDICATOR: 2279 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2280 "%d\n", index)); 2281 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2282 break; 2283 case UHF_C_PORT_CONNECTION: 2284 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2285 break; 2286 case UHF_C_PORT_ENABLE: 2287 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2288 break; 2289 case UHF_C_PORT_SUSPEND: 2290 /* how? */ 2291 break; 2292 case UHF_C_PORT_OVER_CURRENT: 2293 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2294 break; 2295 case UHF_C_PORT_RESET: 2296 sc->sc_isreset[index] = 0; 2297 break; 2298 default: 2299 err = USBD_IOERROR; 2300 goto ret; 2301 } 2302 #if 0 2303 switch(value) { 2304 case UHF_C_PORT_CONNECTION: 2305 case UHF_C_PORT_ENABLE: 2306 case UHF_C_PORT_SUSPEND: 2307 case UHF_C_PORT_OVER_CURRENT: 2308 case UHF_C_PORT_RESET: 2309 default: 2310 break; 2311 } 2312 #endif 2313 break; 2314 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2315 if (len == 0) 2316 break; 2317 if ((value & 0xff) != 0) { 2318 err = USBD_IOERROR; 2319 goto ret; 2320 } 2321 hubd = ehci_hubd; 2322 hubd.bNbrPorts = sc->sc_noport; 2323 v = EOREAD4(sc, EHCI_HCSPARAMS); 2324 USETW(hubd.wHubCharacteristics, 2325 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2326 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2327 ? UHD_PORT_IND : 0); 2328 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2329 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2330 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2331 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2332 l = min(len, hubd.bDescLength); 2333 totlen = l; 2334 memcpy(buf, &hubd, l); 2335 break; 2336 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2337 if (len != 4) { 2338 err = USBD_IOERROR; 2339 goto ret; 2340 } 2341 memset(buf, 0, len); /* ? XXX */ 2342 totlen = len; 2343 break; 2344 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2345 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2346 index)); 2347 if (index < 1 || index > sc->sc_noport) { 2348 err = USBD_IOERROR; 2349 goto ret; 2350 } 2351 if (len != 4) { 2352 err = USBD_IOERROR; 2353 goto ret; 2354 } 2355 v = EOREAD4(sc, EHCI_PORTSC(index)); 2356 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2357 2358 i = UPS_HIGH_SPEED; 2359 #if 0 2360 if (sc->sc_flags & EHCIF_ETTF) { 2361 /* 2362 * If we are doing embedded transaction translation, 2363 * then directly attached LS/FS devices are reset by 2364 * the EHCI controller itself. PSPD is encoded 2365 * the same way as in USBSTATUS. 2366 */ 2367 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2368 } 2369 #endif 2370 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2371 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2372 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2373 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2374 if (v & EHCI_PS_PR) i |= UPS_RESET; 2375 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2376 if (sc->sc_vendor_port_status) 2377 i = sc->sc_vendor_port_status(sc, v, i); 2378 USETW(ps.wPortStatus, i); 2379 i = 0; 2380 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2381 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2382 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2383 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2384 USETW(ps.wPortChange, i); 2385 l = min(len, sizeof ps); 2386 memcpy(buf, &ps, l); 2387 totlen = l; 2388 break; 2389 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2390 err = USBD_IOERROR; 2391 goto ret; 2392 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2393 break; 2394 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2395 if (index < 1 || index > sc->sc_noport) { 2396 err = USBD_IOERROR; 2397 goto ret; 2398 } 2399 port = EHCI_PORTSC(index); 2400 v = EOREAD4(sc, port); 2401 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2402 v &= ~EHCI_PS_CLEAR; 2403 switch(value) { 2404 case UHF_PORT_ENABLE: 2405 EOWRITE4(sc, port, v | EHCI_PS_PE); 2406 break; 2407 case UHF_PORT_SUSPEND: 2408 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2409 break; 2410 case UHF_PORT_RESET: 2411 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2412 index)); 2413 if (EHCI_PS_IS_LOWSPEED(v) 2414 && sc->sc_ncomp > 0 2415 && !(sc->sc_flags & EHCIF_ETTF)) { 2416 /* 2417 * Low speed device on non-ETTF controller or 2418 * unaccompanied controller, give up ownership. 2419 */ 2420 ehci_disown(sc, index, 1); 2421 break; 2422 } 2423 /* Start reset sequence. */ 2424 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2425 EOWRITE4(sc, port, v | EHCI_PS_PR); 2426 /* Wait for reset to complete. */ 2427 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2428 if (sc->sc_dying) { 2429 err = USBD_IOERROR; 2430 goto ret; 2431 } 2432 /* 2433 * An embedded transaction translater will automatically 2434 * terminate the reset sequence so there's no need to 2435 * it. 2436 */ 2437 v = EOREAD4(sc, port); 2438 if (v & EHCI_PS_PR) { 2439 /* Terminate reset sequence. */ 2440 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2441 /* Wait for HC to complete reset. */ 2442 usb_delay_ms(&sc->sc_bus, 2443 EHCI_PORT_RESET_COMPLETE); 2444 if (sc->sc_dying) { 2445 err = USBD_IOERROR; 2446 goto ret; 2447 } 2448 } 2449 2450 v = EOREAD4(sc, port); 2451 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2452 if (v & EHCI_PS_PR) { 2453 printf("%s: port reset timeout\n", 2454 device_xname(sc->sc_dev)); 2455 return (USBD_TIMEOUT); 2456 } 2457 if (!(v & EHCI_PS_PE)) { 2458 /* Not a high speed device, give up ownership.*/ 2459 ehci_disown(sc, index, 0); 2460 break; 2461 } 2462 sc->sc_isreset[index] = 1; 2463 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2464 index, v)); 2465 break; 2466 case UHF_PORT_POWER: 2467 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2468 "%d (has PPC = %d)\n", index, 2469 sc->sc_hasppc)); 2470 if (sc->sc_hasppc) 2471 EOWRITE4(sc, port, v | EHCI_PS_PP); 2472 break; 2473 case UHF_PORT_TEST: 2474 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2475 "%d\n", index)); 2476 break; 2477 case UHF_PORT_INDICATOR: 2478 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2479 "%d\n", index)); 2480 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2481 break; 2482 default: 2483 err = USBD_IOERROR; 2484 goto ret; 2485 } 2486 break; 2487 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2488 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2489 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2490 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2491 break; 2492 default: 2493 err = USBD_IOERROR; 2494 goto ret; 2495 } 2496 xfer->actlen = totlen; 2497 err = USBD_NORMAL_COMPLETION; 2498 ret: 2499 mutex_enter(&sc->sc_lock); 2500 xfer->status = err; 2501 usb_transfer_complete(xfer); 2502 mutex_exit(&sc->sc_lock); 2503 return (USBD_IN_PROGRESS); 2504 } 2505 2506 Static void 2507 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2508 { 2509 int port; 2510 u_int32_t v; 2511 2512 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2513 #ifdef DIAGNOSTIC 2514 if (sc->sc_npcomp != 0) { 2515 int i = (index-1) / sc->sc_npcomp; 2516 if (i >= sc->sc_ncomp) 2517 printf("%s: strange port\n", 2518 device_xname(sc->sc_dev)); 2519 else 2520 printf("%s: handing over %s speed device on " 2521 "port %d to %s\n", 2522 device_xname(sc->sc_dev), 2523 lowspeed ? "low" : "full", 2524 index, device_xname(sc->sc_comps[i])); 2525 } else { 2526 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2527 } 2528 #endif 2529 port = EHCI_PORTSC(index); 2530 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2531 EOWRITE4(sc, port, v | EHCI_PS_PO); 2532 } 2533 2534 /* Abort a root control request. */ 2535 Static void 2536 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2537 { 2538 /* Nothing to do, all transfers are synchronous. */ 2539 } 2540 2541 /* Close the root pipe. */ 2542 Static void 2543 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2544 { 2545 DPRINTF(("ehci_root_ctrl_close\n")); 2546 /* Nothing to do. */ 2547 } 2548 2549 Static void 2550 ehci_root_intr_done(usbd_xfer_handle xfer) 2551 { 2552 xfer->hcpriv = NULL; 2553 } 2554 2555 Static usbd_status 2556 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2557 { 2558 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2559 usbd_status err; 2560 2561 /* Insert last in queue. */ 2562 mutex_enter(&sc->sc_lock); 2563 err = usb_insert_transfer(xfer); 2564 mutex_exit(&sc->sc_lock); 2565 if (err) 2566 return (err); 2567 2568 /* Pipe isn't running, start first */ 2569 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2570 } 2571 2572 Static usbd_status 2573 ehci_root_intr_start(usbd_xfer_handle xfer) 2574 { 2575 usbd_pipe_handle pipe = xfer->pipe; 2576 ehci_softc_t *sc = pipe->device->bus->hci_private; 2577 2578 if (sc->sc_dying) 2579 return (USBD_IOERROR); 2580 2581 mutex_enter(&sc->sc_lock); 2582 sc->sc_intrxfer = xfer; 2583 mutex_exit(&sc->sc_lock); 2584 2585 return (USBD_IN_PROGRESS); 2586 } 2587 2588 /* Abort a root interrupt request. */ 2589 Static void 2590 ehci_root_intr_abort(usbd_xfer_handle xfer) 2591 { 2592 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2593 2594 KASSERT(mutex_owned(&sc->sc_lock)); 2595 if (xfer->pipe->intrxfer == xfer) { 2596 DPRINTF(("ehci_root_intr_abort: remove\n")); 2597 xfer->pipe->intrxfer = NULL; 2598 } 2599 xfer->status = USBD_CANCELLED; 2600 usb_transfer_complete(xfer); 2601 } 2602 2603 /* Close the root pipe. */ 2604 Static void 2605 ehci_root_intr_close(usbd_pipe_handle pipe) 2606 { 2607 ehci_softc_t *sc = pipe->device->bus->hci_private; 2608 2609 KASSERT(mutex_owned(&sc->sc_lock)); 2610 2611 DPRINTF(("ehci_root_intr_close\n")); 2612 2613 sc->sc_intrxfer = NULL; 2614 } 2615 2616 Static void 2617 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2618 { 2619 xfer->hcpriv = NULL; 2620 } 2621 2622 /************************/ 2623 2624 Static ehci_soft_qh_t * 2625 ehci_alloc_sqh(ehci_softc_t *sc) 2626 { 2627 ehci_soft_qh_t *sqh; 2628 usbd_status err; 2629 int i, offs; 2630 usb_dma_t dma; 2631 2632 if (sc->sc_freeqhs == NULL) { 2633 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2634 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2635 EHCI_PAGE_SIZE, &dma); 2636 #ifdef EHCI_DEBUG 2637 if (err) 2638 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2639 #endif 2640 if (err) 2641 return (NULL); 2642 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2643 offs = i * EHCI_SQH_SIZE; 2644 sqh = KERNADDR(&dma, offs); 2645 sqh->physaddr = DMAADDR(&dma, offs); 2646 sqh->dma = dma; 2647 sqh->offs = offs; 2648 sqh->next = sc->sc_freeqhs; 2649 sc->sc_freeqhs = sqh; 2650 } 2651 } 2652 sqh = sc->sc_freeqhs; 2653 sc->sc_freeqhs = sqh->next; 2654 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2655 sqh->next = NULL; 2656 return (sqh); 2657 } 2658 2659 Static void 2660 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2661 { 2662 sqh->next = sc->sc_freeqhs; 2663 sc->sc_freeqhs = sqh; 2664 } 2665 2666 Static ehci_soft_qtd_t * 2667 ehci_alloc_sqtd(ehci_softc_t *sc) 2668 { 2669 ehci_soft_qtd_t *sqtd = NULL; 2670 usbd_status err; 2671 int i, offs; 2672 usb_dma_t dma; 2673 2674 if (sc->sc_freeqtds == NULL) { 2675 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2676 2677 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2678 EHCI_PAGE_SIZE, &dma); 2679 #ifdef EHCI_DEBUG 2680 if (err) 2681 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2682 #endif 2683 if (err) 2684 goto done; 2685 2686 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2687 offs = i * EHCI_SQTD_SIZE; 2688 sqtd = KERNADDR(&dma, offs); 2689 sqtd->physaddr = DMAADDR(&dma, offs); 2690 sqtd->dma = dma; 2691 sqtd->offs = offs; 2692 2693 sqtd->nextqtd = sc->sc_freeqtds; 2694 sc->sc_freeqtds = sqtd; 2695 } 2696 } 2697 2698 sqtd = sc->sc_freeqtds; 2699 sc->sc_freeqtds = sqtd->nextqtd; 2700 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2701 sqtd->nextqtd = NULL; 2702 sqtd->xfer = NULL; 2703 2704 done: 2705 return (sqtd); 2706 } 2707 2708 Static void 2709 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2710 { 2711 2712 KASSERT(mutex_owned(&sc->sc_lock)); 2713 2714 sqtd->nextqtd = sc->sc_freeqtds; 2715 sc->sc_freeqtds = sqtd; 2716 } 2717 2718 Static usbd_status 2719 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2720 int alen, int rd, usbd_xfer_handle xfer, 2721 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2722 { 2723 ehci_soft_qtd_t *next, *cur; 2724 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2725 u_int32_t qtdstatus; 2726 int len, curlen, mps; 2727 int i, tog; 2728 usb_dma_t *dma = &xfer->dmabuf; 2729 u_int16_t flags = xfer->flags; 2730 2731 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2732 2733 len = alen; 2734 dataphys = DMAADDR(dma, 0); 2735 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2736 qtdstatus = EHCI_QTD_ACTIVE | 2737 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2738 EHCI_QTD_SET_CERR(3) 2739 /* IOC set below */ 2740 /* BYTES set below */ 2741 ; 2742 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2743 tog = epipe->nexttoggle; 2744 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2745 2746 cur = ehci_alloc_sqtd(sc); 2747 *sp = cur; 2748 if (cur == NULL) 2749 goto nomem; 2750 2751 usb_syncmem(dma, 0, alen, 2752 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2753 for (;;) { 2754 dataphyspage = EHCI_PAGE(dataphys); 2755 /* The EHCI hardware can handle at most 5 pages. */ 2756 if (dataphyslastpage - dataphyspage < 2757 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2758 /* we can handle it in this QTD */ 2759 curlen = len; 2760 } else { 2761 /* must use multiple TDs, fill as much as possible. */ 2762 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2763 EHCI_PAGE_OFFSET(dataphys); 2764 #ifdef DIAGNOSTIC 2765 if (curlen > len) { 2766 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2767 "len=0x%x offs=0x%x\n", curlen, len, 2768 EHCI_PAGE_OFFSET(dataphys)); 2769 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2770 dataphyslastpage, dataphyspage, 2771 dataphys); 2772 curlen = len; 2773 } 2774 #endif 2775 /* the length must be a multiple of the max size */ 2776 curlen -= curlen % mps; 2777 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2778 "curlen=%d\n", curlen)); 2779 #ifdef DIAGNOSTIC 2780 if (curlen == 0) 2781 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2782 #endif 2783 } 2784 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2785 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2786 dataphys, dataphyslastpage, 2787 len, curlen)); 2788 len -= curlen; 2789 2790 /* 2791 * Allocate another transfer if there's more data left, 2792 * or if force last short transfer flag is set and we're 2793 * allocating a multiple of the max packet size. 2794 */ 2795 if (len != 0 || 2796 ((curlen % mps) == 0 && !rd && curlen != 0 && 2797 (flags & USBD_FORCE_SHORT_XFER))) { 2798 next = ehci_alloc_sqtd(sc); 2799 if (next == NULL) 2800 goto nomem; 2801 nextphys = htole32(next->physaddr); 2802 } else { 2803 next = NULL; 2804 nextphys = EHCI_NULL; 2805 } 2806 2807 for (i = 0; i * EHCI_PAGE_SIZE < 2808 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2809 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2810 if (i != 0) /* use offset only in first buffer */ 2811 a = EHCI_PAGE(a); 2812 cur->qtd.qtd_buffer[i] = htole32(a); 2813 cur->qtd.qtd_buffer_hi[i] = 0; 2814 #ifdef DIAGNOSTIC 2815 if (i >= EHCI_QTD_NBUFFERS) { 2816 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2817 goto nomem; 2818 } 2819 #endif 2820 } 2821 cur->nextqtd = next; 2822 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2823 cur->qtd.qtd_status = 2824 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2825 cur->xfer = xfer; 2826 cur->len = curlen; 2827 2828 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2829 dataphys, dataphys + curlen)); 2830 /* adjust the toggle based on the number of packets in this 2831 qtd */ 2832 if (((curlen + mps - 1) / mps) & 1) { 2833 tog ^= 1; 2834 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2835 } 2836 if (next == NULL) 2837 break; 2838 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2839 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2840 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2841 if (len) 2842 dataphys += curlen; 2843 cur = next; 2844 } 2845 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2846 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2847 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2848 *ep = cur; 2849 epipe->nexttoggle = tog; 2850 2851 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2852 *sp, *ep)); 2853 2854 return (USBD_NORMAL_COMPLETION); 2855 2856 nomem: 2857 /* XXX free chain */ 2858 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2859 return (USBD_NOMEM); 2860 } 2861 2862 Static void 2863 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2864 ehci_soft_qtd_t *sqtdend) 2865 { 2866 ehci_soft_qtd_t *p; 2867 int i; 2868 2869 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2870 sqtd, sqtdend)); 2871 2872 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2873 p = sqtd->nextqtd; 2874 ehci_free_sqtd(sc, sqtd); 2875 } 2876 } 2877 2878 Static ehci_soft_itd_t * 2879 ehci_alloc_itd(ehci_softc_t *sc) 2880 { 2881 struct ehci_soft_itd *itd, *freeitd; 2882 usbd_status err; 2883 int i, offs, frindex, previndex; 2884 usb_dma_t dma; 2885 2886 KASSERT(mutex_owned(&sc->sc_lock)); 2887 2888 /* Find an itd that wasn't freed this frame or last frame. This can 2889 * discard itds that were freed before frindex wrapped around 2890 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2891 * interrupt and fiddling with list when that happens */ 2892 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2893 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2894 2895 freeitd = NULL; 2896 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2897 if (itd == NULL) 2898 break; 2899 if (itd->slot != frindex && itd->slot != previndex) { 2900 freeitd = itd; 2901 break; 2902 } 2903 } 2904 2905 if (freeitd == NULL) { 2906 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2907 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2908 EHCI_PAGE_SIZE, &dma); 2909 2910 if (err) { 2911 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2912 return NULL; 2913 } 2914 2915 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2916 offs = i * EHCI_ITD_SIZE; 2917 itd = KERNADDR(&dma, offs); 2918 itd->physaddr = DMAADDR(&dma, offs); 2919 itd->dma = dma; 2920 itd->offs = offs; 2921 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2922 } 2923 freeitd = LIST_FIRST(&sc->sc_freeitds); 2924 } 2925 2926 itd = freeitd; 2927 LIST_REMOVE(itd, u.free_list); 2928 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2929 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2930 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2931 BUS_DMASYNC_PREREAD); 2932 2933 itd->u.frame_list.next = NULL; 2934 itd->u.frame_list.prev = NULL; 2935 itd->xfer_next = NULL; 2936 itd->slot = 0; 2937 2938 return itd; 2939 } 2940 2941 Static void 2942 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2943 { 2944 2945 KASSERT(mutex_owned(&sc->sc_lock)); 2946 2947 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2948 } 2949 2950 /****************/ 2951 2952 /* 2953 * Close a reqular pipe. 2954 * Assumes that there are no pending transactions. 2955 */ 2956 Static void 2957 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2958 { 2959 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2960 ehci_softc_t *sc = pipe->device->bus->hci_private; 2961 ehci_soft_qh_t *sqh = epipe->sqh; 2962 2963 KASSERT(mutex_owned(&sc->sc_lock)); 2964 2965 ehci_rem_qh(sc, sqh, head); 2966 ehci_free_sqh(sc, epipe->sqh); 2967 } 2968 2969 /* 2970 * Abort a device request. 2971 * If this routine is called at splusb() it guarantees that the request 2972 * will be removed from the hardware scheduling and that the callback 2973 * for it will be called with USBD_CANCELLED status. 2974 * It's impossible to guarantee that the requested transfer will not 2975 * have happened since the hardware runs concurrently. 2976 * If the transaction has already happened we rely on the ordinary 2977 * interrupt processing to process it. 2978 * XXX This is most probably wrong. 2979 * XXXMRG this doesn't make sense anymore. 2980 */ 2981 Static void 2982 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2983 { 2984 #define exfer EXFER(xfer) 2985 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2986 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2987 ehci_soft_qh_t *sqh = epipe->sqh; 2988 ehci_soft_qtd_t *sqtd; 2989 ehci_physaddr_t cur; 2990 u_int32_t qhstatus; 2991 int hit; 2992 int wake; 2993 2994 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2995 2996 KASSERT(mutex_owned(&sc->sc_lock)); 2997 2998 if (sc->sc_dying) { 2999 /* If we're dying, just do the software part. */ 3000 xfer->status = status; /* make software ignore it */ 3001 callout_stop(&xfer->timeout_handle); 3002 usb_transfer_complete(xfer); 3003 return; 3004 } 3005 3006 if (cpu_intr_p() || cpu_softintr_p()) 3007 panic("ehci_abort_xfer: not in process context"); 3008 3009 /* 3010 * If an abort is already in progress then just wait for it to 3011 * complete and return. 3012 */ 3013 if (xfer->hcflags & UXFER_ABORTING) { 3014 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3015 #ifdef DIAGNOSTIC 3016 if (status == USBD_TIMEOUT) 3017 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3018 #endif 3019 /* Override the status which might be USBD_TIMEOUT. */ 3020 xfer->status = status; 3021 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3022 xfer->hcflags |= UXFER_ABORTWAIT; 3023 while (xfer->hcflags & UXFER_ABORTING) 3024 cv_wait(&xfer->hccv, &sc->sc_lock); 3025 return; 3026 } 3027 xfer->hcflags |= UXFER_ABORTING; 3028 3029 /* 3030 * Step 1: Make interrupt routine and hardware ignore xfer. 3031 */ 3032 xfer->status = status; /* make software ignore it */ 3033 callout_stop(&xfer->timeout_handle); 3034 3035 usb_syncmem(&sqh->dma, 3036 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3037 sizeof(sqh->qh.qh_qtd.qtd_status), 3038 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3039 qhstatus = sqh->qh.qh_qtd.qtd_status; 3040 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3041 usb_syncmem(&sqh->dma, 3042 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3043 sizeof(sqh->qh.qh_qtd.qtd_status), 3044 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3045 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3046 usb_syncmem(&sqtd->dma, 3047 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3048 sizeof(sqtd->qtd.qtd_status), 3049 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3050 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3051 usb_syncmem(&sqtd->dma, 3052 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3053 sizeof(sqtd->qtd.qtd_status), 3054 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3055 if (sqtd == exfer->sqtdend) 3056 break; 3057 } 3058 3059 /* 3060 * Step 2: Wait until we know hardware has finished any possible 3061 * use of the xfer. Also make sure the soft interrupt routine 3062 * has run. 3063 */ 3064 ehci_sync_hc(sc); 3065 sc->sc_softwake = 1; 3066 usb_schedsoftintr(&sc->sc_bus); 3067 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3068 3069 /* 3070 * Step 3: Remove any vestiges of the xfer from the hardware. 3071 * The complication here is that the hardware may have executed 3072 * beyond the xfer we're trying to abort. So as we're scanning 3073 * the TDs of this xfer we check if the hardware points to 3074 * any of them. 3075 */ 3076 3077 usb_syncmem(&sqh->dma, 3078 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3079 sizeof(sqh->qh.qh_curqtd), 3080 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3081 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3082 hit = 0; 3083 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3084 hit |= cur == sqtd->physaddr; 3085 if (sqtd == exfer->sqtdend) 3086 break; 3087 } 3088 sqtd = sqtd->nextqtd; 3089 /* Zap curqtd register if hardware pointed inside the xfer. */ 3090 if (hit && sqtd != NULL) { 3091 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3092 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3093 usb_syncmem(&sqh->dma, 3094 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3095 sizeof(sqh->qh.qh_curqtd), 3096 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3097 sqh->qh.qh_qtd.qtd_status = qhstatus; 3098 usb_syncmem(&sqh->dma, 3099 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3100 sizeof(sqh->qh.qh_qtd.qtd_status), 3101 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3102 } else { 3103 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3104 } 3105 3106 /* 3107 * Step 4: Execute callback. 3108 */ 3109 #ifdef DIAGNOSTIC 3110 exfer->isdone = 1; 3111 #endif 3112 wake = xfer->hcflags & UXFER_ABORTWAIT; 3113 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3114 usb_transfer_complete(xfer); 3115 if (wake) { 3116 cv_broadcast(&xfer->hccv); 3117 } 3118 3119 KASSERT(mutex_owned(&sc->sc_lock)); 3120 #undef exfer 3121 } 3122 3123 Static void 3124 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3125 { 3126 ehci_isoc_trans_t trans_status; 3127 struct ehci_pipe *epipe; 3128 struct ehci_xfer *exfer; 3129 ehci_softc_t *sc; 3130 struct ehci_soft_itd *itd; 3131 int i, wake; 3132 3133 epipe = (struct ehci_pipe *) xfer->pipe; 3134 exfer = EXFER(xfer); 3135 sc = epipe->pipe.device->bus->hci_private; 3136 3137 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3138 3139 KASSERT(mutex_owned(&sc->sc_lock)); 3140 3141 if (sc->sc_dying) { 3142 xfer->status = status; 3143 callout_stop(&xfer->timeout_handle); 3144 usb_transfer_complete(xfer); 3145 return; 3146 } 3147 3148 if (xfer->hcflags & UXFER_ABORTING) { 3149 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3150 3151 #ifdef DIAGNOSTIC 3152 if (status == USBD_TIMEOUT) 3153 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3154 #endif 3155 3156 xfer->status = status; 3157 DPRINTFN(2, ("ehci_abort_isoc_xfer: waiting for abort to finish\n")); 3158 xfer->hcflags |= UXFER_ABORTWAIT; 3159 while (xfer->hcflags & UXFER_ABORTING) 3160 cv_wait(&xfer->hccv, &sc->sc_lock); 3161 goto done; 3162 } 3163 xfer->hcflags |= UXFER_ABORTING; 3164 3165 xfer->status = status; 3166 callout_stop(&xfer->timeout_handle); 3167 3168 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3169 usb_syncmem(&itd->dma, 3170 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3171 sizeof(itd->itd.itd_ctl), 3172 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3173 3174 for (i = 0; i < 8; i++) { 3175 trans_status = le32toh(itd->itd.itd_ctl[i]); 3176 trans_status &= ~EHCI_ITD_ACTIVE; 3177 itd->itd.itd_ctl[i] = htole32(trans_status); 3178 } 3179 3180 usb_syncmem(&itd->dma, 3181 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3182 sizeof(itd->itd.itd_ctl), 3183 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3184 } 3185 3186 sc->sc_softwake = 1; 3187 usb_schedsoftintr(&sc->sc_bus); 3188 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3189 3190 #ifdef DIAGNOSTIC 3191 exfer->isdone = 1; 3192 #endif 3193 wake = xfer->hcflags & UXFER_ABORTWAIT; 3194 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3195 usb_transfer_complete(xfer); 3196 if (wake) { 3197 cv_broadcast(&xfer->hccv); 3198 } 3199 3200 done: 3201 KASSERT(mutex_owned(&sc->sc_lock)); 3202 return; 3203 } 3204 3205 Static void 3206 ehci_timeout(void *addr) 3207 { 3208 struct ehci_xfer *exfer = addr; 3209 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3210 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3211 3212 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3213 #ifdef EHCI_DEBUG 3214 if (ehcidebug > 1) 3215 usbd_dump_pipe(exfer->xfer.pipe); 3216 #endif 3217 3218 if (sc->sc_dying) { 3219 mutex_enter(&sc->sc_lock); 3220 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3221 mutex_exit(&sc->sc_lock); 3222 return; 3223 } 3224 3225 /* Execute the abort in a process context. */ 3226 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3227 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3228 USB_TASKQ_HC); 3229 } 3230 3231 Static void 3232 ehci_timeout_task(void *addr) 3233 { 3234 usbd_xfer_handle xfer = addr; 3235 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3236 3237 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3238 3239 mutex_enter(&sc->sc_lock); 3240 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3241 mutex_exit(&sc->sc_lock); 3242 } 3243 3244 /************************/ 3245 3246 Static usbd_status 3247 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3248 { 3249 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3250 usbd_status err; 3251 3252 /* Insert last in queue. */ 3253 mutex_enter(&sc->sc_lock); 3254 err = usb_insert_transfer(xfer); 3255 mutex_exit(&sc->sc_lock); 3256 if (err) 3257 return (err); 3258 3259 /* Pipe isn't running, start first */ 3260 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3261 } 3262 3263 Static usbd_status 3264 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3265 { 3266 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3267 usbd_status err; 3268 3269 if (sc->sc_dying) 3270 return (USBD_IOERROR); 3271 3272 #ifdef DIAGNOSTIC 3273 if (!(xfer->rqflags & URQ_REQUEST)) { 3274 /* XXX panic */ 3275 printf("ehci_device_ctrl_transfer: not a request\n"); 3276 return (USBD_INVAL); 3277 } 3278 #endif 3279 3280 err = ehci_device_request(xfer); 3281 if (err) { 3282 return (err); 3283 } 3284 3285 if (sc->sc_bus.use_polling) 3286 ehci_waitintr(sc, xfer); 3287 3288 return (USBD_IN_PROGRESS); 3289 } 3290 3291 Static void 3292 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3293 { 3294 struct ehci_xfer *ex = EXFER(xfer); 3295 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3296 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3297 usb_device_request_t *req = &xfer->request; 3298 int len = UGETW(req->wLength); 3299 int rd = req->bmRequestType & UT_READ; 3300 3301 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3302 3303 KASSERT(mutex_owned(&sc->sc_lock)); 3304 3305 #ifdef DIAGNOSTIC 3306 if (!(xfer->rqflags & URQ_REQUEST)) { 3307 panic("ehci_ctrl_done: not a request"); 3308 } 3309 #endif 3310 3311 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3312 ehci_del_intr_list(sc, ex); /* remove from active list */ 3313 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3314 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3315 BUS_DMASYNC_POSTWRITE); 3316 if (len) 3317 usb_syncmem(&xfer->dmabuf, 0, len, 3318 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3319 } 3320 3321 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3322 } 3323 3324 /* Abort a device control request. */ 3325 Static void 3326 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3327 { 3328 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3329 ehci_abort_xfer(xfer, USBD_CANCELLED); 3330 } 3331 3332 /* Close a device control pipe. */ 3333 Static void 3334 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3335 { 3336 ehci_softc_t *sc = pipe->device->bus->hci_private; 3337 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3338 3339 KASSERT(mutex_owned(&sc->sc_lock)); 3340 3341 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3342 3343 ehci_close_pipe(pipe, sc->sc_async_head); 3344 } 3345 3346 Static usbd_status 3347 ehci_device_request(usbd_xfer_handle xfer) 3348 { 3349 #define exfer EXFER(xfer) 3350 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3351 usb_device_request_t *req = &xfer->request; 3352 usbd_device_handle dev = epipe->pipe.device; 3353 ehci_softc_t *sc = dev->bus->hci_private; 3354 int addr = dev->address; 3355 ehci_soft_qtd_t *setup, *stat, *next; 3356 ehci_soft_qh_t *sqh; 3357 int isread; 3358 int len; 3359 usbd_status err; 3360 3361 isread = req->bmRequestType & UT_READ; 3362 len = UGETW(req->wLength); 3363 3364 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3365 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3366 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3367 UGETW(req->wIndex), len, addr, 3368 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3369 3370 setup = ehci_alloc_sqtd(sc); 3371 if (setup == NULL) { 3372 err = USBD_NOMEM; 3373 goto bad1; 3374 } 3375 stat = ehci_alloc_sqtd(sc); 3376 if (stat == NULL) { 3377 err = USBD_NOMEM; 3378 goto bad2; 3379 } 3380 3381 mutex_enter(&sc->sc_lock); 3382 3383 sqh = epipe->sqh; 3384 epipe->u.ctl.length = len; 3385 3386 /* Update device address and length since they may have changed 3387 during the setup of the control pipe in usbd_new_device(). */ 3388 /* XXX This only needs to be done once, but it's too early in open. */ 3389 /* XXXX Should not touch ED here! */ 3390 sqh->qh.qh_endp = 3391 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3392 htole32( 3393 EHCI_QH_SET_ADDR(addr) | 3394 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3395 ); 3396 3397 /* Set up data transaction */ 3398 if (len != 0) { 3399 ehci_soft_qtd_t *end; 3400 3401 /* Start toggle at 1. */ 3402 epipe->nexttoggle = 1; 3403 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3404 &next, &end); 3405 if (err) 3406 goto bad3; 3407 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3408 end->nextqtd = stat; 3409 end->qtd.qtd_next = 3410 end->qtd.qtd_altnext = htole32(stat->physaddr); 3411 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3412 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3413 } else { 3414 next = stat; 3415 } 3416 3417 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3418 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3419 3420 /* Clear toggle */ 3421 setup->qtd.qtd_status = htole32( 3422 EHCI_QTD_ACTIVE | 3423 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3424 EHCI_QTD_SET_CERR(3) | 3425 EHCI_QTD_SET_TOGGLE(0) | 3426 EHCI_QTD_SET_BYTES(sizeof *req) 3427 ); 3428 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3429 setup->qtd.qtd_buffer_hi[0] = 0; 3430 setup->nextqtd = next; 3431 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3432 setup->xfer = xfer; 3433 setup->len = sizeof *req; 3434 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3435 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3436 3437 stat->qtd.qtd_status = htole32( 3438 EHCI_QTD_ACTIVE | 3439 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3440 EHCI_QTD_SET_CERR(3) | 3441 EHCI_QTD_SET_TOGGLE(1) | 3442 EHCI_QTD_IOC 3443 ); 3444 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3445 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3446 stat->nextqtd = NULL; 3447 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3448 stat->xfer = xfer; 3449 stat->len = 0; 3450 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3451 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3452 3453 #ifdef EHCI_DEBUG 3454 if (ehcidebug > 5) { 3455 DPRINTF(("ehci_device_request:\n")); 3456 ehci_dump_sqh(sqh); 3457 ehci_dump_sqtds(setup); 3458 } 3459 #endif 3460 3461 exfer->sqtdstart = setup; 3462 exfer->sqtdend = stat; 3463 #ifdef DIAGNOSTIC 3464 if (!exfer->isdone) { 3465 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3466 } 3467 exfer->isdone = 0; 3468 #endif 3469 3470 /* Insert qTD in QH list. */ 3471 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3472 if (xfer->timeout && !sc->sc_bus.use_polling) { 3473 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3474 ehci_timeout, xfer); 3475 } 3476 ehci_add_intr_list(sc, exfer); 3477 xfer->status = USBD_IN_PROGRESS; 3478 mutex_exit(&sc->sc_lock); 3479 3480 #ifdef EHCI_DEBUG 3481 if (ehcidebug > 10) { 3482 DPRINTF(("ehci_device_request: status=%x\n", 3483 EOREAD4(sc, EHCI_USBSTS))); 3484 delay(10000); 3485 ehci_dump_regs(sc); 3486 ehci_dump_sqh(sc->sc_async_head); 3487 ehci_dump_sqh(sqh); 3488 ehci_dump_sqtds(setup); 3489 } 3490 #endif 3491 3492 return (USBD_NORMAL_COMPLETION); 3493 3494 bad3: 3495 mutex_exit(&sc->sc_lock); 3496 ehci_free_sqtd(sc, stat); 3497 bad2: 3498 ehci_free_sqtd(sc, setup); 3499 bad1: 3500 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3501 mutex_enter(&sc->sc_lock); 3502 xfer->status = err; 3503 usb_transfer_complete(xfer); 3504 mutex_exit(&sc->sc_lock); 3505 return (err); 3506 #undef exfer 3507 } 3508 3509 /* 3510 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3511 * qTD status, or miss signalling occasionally under heavy load. If the host 3512 * machine is too fast, we we can miss transaction completion - when we scan 3513 * the active list the transaction still seems to be active. This generally 3514 * exhibits itself as a umass stall that never recovers. 3515 * 3516 * We work around this behaviour by setting up this callback after any softintr 3517 * that completes with transactions still pending, giving us another chance to 3518 * check for completion after the writeback has taken place. 3519 */ 3520 Static void 3521 ehci_intrlist_timeout(void *arg) 3522 { 3523 ehci_softc_t *sc = arg; 3524 3525 DPRINTF(("ehci_intrlist_timeout\n")); 3526 usb_schedsoftintr(&sc->sc_bus); 3527 } 3528 3529 /************************/ 3530 3531 Static usbd_status 3532 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3533 { 3534 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3535 usbd_status err; 3536 3537 /* Insert last in queue. */ 3538 mutex_enter(&sc->sc_lock); 3539 err = usb_insert_transfer(xfer); 3540 mutex_exit(&sc->sc_lock); 3541 if (err) 3542 return (err); 3543 3544 /* Pipe isn't running, start first */ 3545 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3546 } 3547 3548 Static usbd_status 3549 ehci_device_bulk_start(usbd_xfer_handle xfer) 3550 { 3551 #define exfer EXFER(xfer) 3552 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3553 usbd_device_handle dev = epipe->pipe.device; 3554 ehci_softc_t *sc = dev->bus->hci_private; 3555 ehci_soft_qtd_t *data, *dataend; 3556 ehci_soft_qh_t *sqh; 3557 usbd_status err; 3558 int len, isread, endpt; 3559 3560 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3561 xfer, xfer->length, xfer->flags)); 3562 3563 if (sc->sc_dying) 3564 return (USBD_IOERROR); 3565 3566 #ifdef DIAGNOSTIC 3567 if (xfer->rqflags & URQ_REQUEST) 3568 panic("ehci_device_bulk_start: a request"); 3569 #endif 3570 3571 mutex_enter(&sc->sc_lock); 3572 3573 len = xfer->length; 3574 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3575 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3576 sqh = epipe->sqh; 3577 3578 epipe->u.bulk.length = len; 3579 3580 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3581 &dataend); 3582 if (err) { 3583 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3584 xfer->status = err; 3585 usb_transfer_complete(xfer); 3586 mutex_exit(&sc->sc_lock); 3587 return (err); 3588 } 3589 3590 #ifdef EHCI_DEBUG 3591 if (ehcidebug > 5) { 3592 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3593 ehci_dump_sqh(sqh); 3594 ehci_dump_sqtds(data); 3595 } 3596 #endif 3597 3598 /* Set up interrupt info. */ 3599 exfer->sqtdstart = data; 3600 exfer->sqtdend = dataend; 3601 #ifdef DIAGNOSTIC 3602 if (!exfer->isdone) { 3603 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3604 } 3605 exfer->isdone = 0; 3606 #endif 3607 3608 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3609 if (xfer->timeout && !sc->sc_bus.use_polling) { 3610 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3611 ehci_timeout, xfer); 3612 } 3613 ehci_add_intr_list(sc, exfer); 3614 xfer->status = USBD_IN_PROGRESS; 3615 mutex_exit(&sc->sc_lock); 3616 3617 #ifdef EHCI_DEBUG 3618 if (ehcidebug > 10) { 3619 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3620 delay(10000); 3621 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3622 ehci_dump_regs(sc); 3623 #if 0 3624 printf("async_head:\n"); 3625 ehci_dump_sqh(sc->sc_async_head); 3626 #endif 3627 printf("sqh:\n"); 3628 ehci_dump_sqh(sqh); 3629 ehci_dump_sqtds(data); 3630 } 3631 #endif 3632 3633 if (sc->sc_bus.use_polling) 3634 ehci_waitintr(sc, xfer); 3635 3636 return (USBD_IN_PROGRESS); 3637 #undef exfer 3638 } 3639 3640 Static void 3641 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3642 { 3643 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3644 ehci_abort_xfer(xfer, USBD_CANCELLED); 3645 } 3646 3647 /* 3648 * Close a device bulk pipe. 3649 */ 3650 Static void 3651 ehci_device_bulk_close(usbd_pipe_handle pipe) 3652 { 3653 ehci_softc_t *sc = pipe->device->bus->hci_private; 3654 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3655 3656 KASSERT(mutex_owned(&sc->sc_lock)); 3657 3658 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3659 pipe->endpoint->datatoggle = epipe->nexttoggle; 3660 ehci_close_pipe(pipe, sc->sc_async_head); 3661 } 3662 3663 Static void 3664 ehci_device_bulk_done(usbd_xfer_handle xfer) 3665 { 3666 struct ehci_xfer *ex = EXFER(xfer); 3667 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3668 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3669 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3670 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3671 3672 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3673 xfer, xfer->actlen)); 3674 3675 KASSERT(mutex_owned(&sc->sc_lock)); 3676 3677 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3678 ehci_del_intr_list(sc, ex); /* remove from active list */ 3679 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3680 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3681 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3682 } 3683 3684 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3685 } 3686 3687 /************************/ 3688 3689 Static usbd_status 3690 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3691 { 3692 struct ehci_soft_islot *isp; 3693 int islot, lev; 3694 3695 /* Find a poll rate that is large enough. */ 3696 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3697 if (EHCI_ILEV_IVAL(lev) <= ival) 3698 break; 3699 3700 /* Pick an interrupt slot at the right level. */ 3701 /* XXX could do better than picking at random */ 3702 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3703 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3704 3705 sqh->islot = islot; 3706 isp = &sc->sc_islots[islot]; 3707 mutex_enter(&sc->sc_lock); 3708 ehci_add_qh(sc, sqh, isp->sqh); 3709 mutex_exit(&sc->sc_lock); 3710 3711 return (USBD_NORMAL_COMPLETION); 3712 } 3713 3714 Static usbd_status 3715 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3716 { 3717 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3718 usbd_status err; 3719 3720 /* Insert last in queue. */ 3721 mutex_enter(&sc->sc_lock); 3722 err = usb_insert_transfer(xfer); 3723 mutex_exit(&sc->sc_lock); 3724 if (err) 3725 return (err); 3726 3727 /* 3728 * Pipe isn't running (otherwise err would be USBD_INPROG), 3729 * so start it first. 3730 */ 3731 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3732 } 3733 3734 Static usbd_status 3735 ehci_device_intr_start(usbd_xfer_handle xfer) 3736 { 3737 #define exfer EXFER(xfer) 3738 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3739 usbd_device_handle dev = xfer->pipe->device; 3740 ehci_softc_t *sc = dev->bus->hci_private; 3741 ehci_soft_qtd_t *data, *dataend; 3742 ehci_soft_qh_t *sqh; 3743 usbd_status err; 3744 int len, isread, endpt; 3745 3746 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3747 xfer, xfer->length, xfer->flags)); 3748 3749 if (sc->sc_dying) 3750 return (USBD_IOERROR); 3751 3752 #ifdef DIAGNOSTIC 3753 if (xfer->rqflags & URQ_REQUEST) 3754 panic("ehci_device_intr_start: a request"); 3755 #endif 3756 3757 mutex_enter(&sc->sc_lock); 3758 3759 len = xfer->length; 3760 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3761 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3762 sqh = epipe->sqh; 3763 3764 epipe->u.intr.length = len; 3765 3766 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3767 &dataend); 3768 if (err) { 3769 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3770 xfer->status = err; 3771 usb_transfer_complete(xfer); 3772 mutex_exit(&sc->sc_lock); 3773 return (err); 3774 } 3775 3776 #ifdef EHCI_DEBUG 3777 if (ehcidebug > 5) { 3778 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3779 ehci_dump_sqh(sqh); 3780 ehci_dump_sqtds(data); 3781 } 3782 #endif 3783 3784 /* Set up interrupt info. */ 3785 exfer->sqtdstart = data; 3786 exfer->sqtdend = dataend; 3787 #ifdef DIAGNOSTIC 3788 if (!exfer->isdone) { 3789 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3790 } 3791 exfer->isdone = 0; 3792 #endif 3793 3794 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3795 if (xfer->timeout && !sc->sc_bus.use_polling) { 3796 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3797 ehci_timeout, xfer); 3798 } 3799 ehci_add_intr_list(sc, exfer); 3800 xfer->status = USBD_IN_PROGRESS; 3801 mutex_exit(&sc->sc_lock); 3802 3803 #ifdef EHCI_DEBUG 3804 if (ehcidebug > 10) { 3805 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3806 delay(10000); 3807 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3808 ehci_dump_regs(sc); 3809 printf("sqh:\n"); 3810 ehci_dump_sqh(sqh); 3811 ehci_dump_sqtds(data); 3812 } 3813 #endif 3814 3815 if (sc->sc_bus.use_polling) 3816 ehci_waitintr(sc, xfer); 3817 3818 return (USBD_IN_PROGRESS); 3819 #undef exfer 3820 } 3821 3822 Static void 3823 ehci_device_intr_abort(usbd_xfer_handle xfer) 3824 { 3825 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3826 if (xfer->pipe->intrxfer == xfer) { 3827 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3828 xfer->pipe->intrxfer = NULL; 3829 } 3830 /* 3831 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3832 * async doorbell. That's dependent on the async list, wheras 3833 * intr xfers are periodic, should not use this? 3834 */ 3835 ehci_abort_xfer(xfer, USBD_CANCELLED); 3836 } 3837 3838 Static void 3839 ehci_device_intr_close(usbd_pipe_handle pipe) 3840 { 3841 ehci_softc_t *sc = pipe->device->bus->hci_private; 3842 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3843 struct ehci_soft_islot *isp; 3844 3845 KASSERT(mutex_owned(&sc->sc_lock)); 3846 3847 isp = &sc->sc_islots[epipe->sqh->islot]; 3848 ehci_close_pipe(pipe, isp->sqh); 3849 } 3850 3851 Static void 3852 ehci_device_intr_done(usbd_xfer_handle xfer) 3853 { 3854 #define exfer EXFER(xfer) 3855 struct ehci_xfer *ex = EXFER(xfer); 3856 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3857 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3858 ehci_soft_qtd_t *data, *dataend; 3859 ehci_soft_qh_t *sqh; 3860 usbd_status err; 3861 int len, isread, endpt; 3862 3863 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3864 xfer, xfer->actlen)); 3865 3866 KASSERT(mutex_owned(&sc->sc_lock)); 3867 3868 if (xfer->pipe->repeat) { 3869 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3870 3871 len = epipe->u.intr.length; 3872 xfer->length = len; 3873 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3874 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3875 usb_syncmem(&xfer->dmabuf, 0, len, 3876 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3877 sqh = epipe->sqh; 3878 3879 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3880 &data, &dataend); 3881 if (err) { 3882 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3883 xfer->status = err; 3884 return; 3885 } 3886 3887 /* Set up interrupt info. */ 3888 exfer->sqtdstart = data; 3889 exfer->sqtdend = dataend; 3890 #ifdef DIAGNOSTIC 3891 if (!exfer->isdone) { 3892 printf("ehci_device_intr_done: not done, ex=%p\n", 3893 exfer); 3894 } 3895 exfer->isdone = 0; 3896 #endif 3897 3898 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3899 if (xfer->timeout && !sc->sc_bus.use_polling) { 3900 callout_reset(&xfer->timeout_handle, 3901 mstohz(xfer->timeout), ehci_timeout, xfer); 3902 } 3903 3904 xfer->status = USBD_IN_PROGRESS; 3905 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3906 ehci_del_intr_list(sc, ex); /* remove from active list */ 3907 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3908 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3909 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3910 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3911 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3912 } 3913 #undef exfer 3914 } 3915 3916 /************************/ 3917 3918 Static usbd_status 3919 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3920 { 3921 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3922 usbd_status err; 3923 3924 mutex_enter(&sc->sc_lock); 3925 err = usb_insert_transfer(xfer); 3926 mutex_exit(&sc->sc_lock); 3927 if (err && err != USBD_IN_PROGRESS) 3928 return err; 3929 3930 return ehci_device_isoc_start(xfer); 3931 } 3932 3933 Static usbd_status 3934 ehci_device_isoc_start(usbd_xfer_handle xfer) 3935 { 3936 struct ehci_pipe *epipe; 3937 usbd_device_handle dev; 3938 ehci_softc_t *sc; 3939 struct ehci_xfer *exfer; 3940 ehci_soft_itd_t *itd, *prev, *start, *stop; 3941 usb_dma_t *dma_buf; 3942 int i, j, k, frames, uframes, ufrperframe; 3943 int trans_count, offs, total_length; 3944 int frindex; 3945 3946 start = NULL; 3947 prev = NULL; 3948 itd = NULL; 3949 trans_count = 0; 3950 total_length = 0; 3951 exfer = (struct ehci_xfer *) xfer; 3952 sc = xfer->pipe->device->bus->hci_private; 3953 dev = xfer->pipe->device; 3954 epipe = (struct ehci_pipe *)xfer->pipe; 3955 3956 /* 3957 * To allow continuous transfers, above we start all transfers 3958 * immediately. However, we're still going to get usbd_start_next call 3959 * this when another xfer completes. So, check if this is already 3960 * in progress or not 3961 */ 3962 3963 if (exfer->itdstart != NULL) 3964 return USBD_IN_PROGRESS; 3965 3966 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3967 xfer, xfer->length, xfer->flags)); 3968 3969 if (sc->sc_dying) 3970 return USBD_IOERROR; 3971 3972 /* 3973 * To avoid complication, don't allow a request right now that'll span 3974 * the entire frame table. To within 4 frames, to allow some leeway 3975 * on either side of where the hc currently is. 3976 */ 3977 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3978 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3979 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3980 return USBD_INVAL; 3981 } 3982 3983 #ifdef DIAGNOSTIC 3984 if (xfer->rqflags & URQ_REQUEST) 3985 panic("ehci_device_isoc_start: request\n"); 3986 3987 if (!exfer->isdone) 3988 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3989 exfer->isdone = 0; 3990 #endif 3991 3992 /* 3993 * Step 1: Allocate and initialize itds, how many do we need? 3994 * One per transfer if interval >= 8 microframes, fewer if we use 3995 * multiple microframes per frame. 3996 */ 3997 3998 i = epipe->pipe.endpoint->edesc->bInterval; 3999 if (i > 16 || i == 0) { 4000 /* Spec page 271 says intervals > 16 are invalid */ 4001 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 4002 return USBD_INVAL; 4003 } 4004 4005 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4006 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4007 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4008 4009 if (frames == 0) { 4010 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 4011 return USBD_INVAL; 4012 } 4013 4014 dma_buf = &xfer->dmabuf; 4015 offs = 0; 4016 4017 for (i = 0; i < frames; i++) { 4018 int froffs = offs; 4019 itd = ehci_alloc_itd(sc); 4020 4021 if (prev != NULL) { 4022 prev->itd.itd_next = 4023 htole32(itd->physaddr | EHCI_LINK_ITD); 4024 usb_syncmem(&itd->dma, 4025 itd->offs + offsetof(ehci_itd_t, itd_next), 4026 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4027 4028 prev->xfer_next = itd; 4029 } else { 4030 start = itd; 4031 } 4032 4033 /* 4034 * Step 1.5, initialize uframes 4035 */ 4036 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4037 /* Calculate which page in the list this starts in */ 4038 int addr = DMAADDR(dma_buf, froffs); 4039 addr = EHCI_PAGE_OFFSET(addr); 4040 addr += (offs - froffs); 4041 addr = EHCI_PAGE(addr); 4042 addr /= EHCI_PAGE_SIZE; 4043 4044 /* This gets the initial offset into the first page, 4045 * looks how far further along the current uframe 4046 * offset is. Works out how many pages that is. 4047 */ 4048 4049 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4050 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4051 EHCI_ITD_SET_PG(addr) | 4052 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4053 4054 total_length += xfer->frlengths[trans_count]; 4055 offs += xfer->frlengths[trans_count]; 4056 trans_count++; 4057 4058 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4059 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4060 break; 4061 } 4062 } 4063 4064 /* Step 1.75, set buffer pointers. To simplify matters, all 4065 * pointers are filled out for the next 7 hardware pages in 4066 * the dma block, so no need to worry what pages to cover 4067 * and what to not. 4068 */ 4069 4070 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4071 /* 4072 * Don't try to lookup a page that's past the end 4073 * of buffer 4074 */ 4075 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4076 if (page_offs >= dma_buf->block->size) 4077 break; 4078 4079 unsigned long long page = DMAADDR(dma_buf, page_offs); 4080 page = EHCI_PAGE(page); 4081 itd->itd.itd_bufr[j] = 4082 htole32(EHCI_ITD_SET_BPTR(page)); 4083 itd->itd.itd_bufr_hi[j] = 4084 htole32(page >> 32); 4085 } 4086 4087 /* 4088 * Other special values 4089 */ 4090 4091 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4092 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4093 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4094 4095 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4096 ? 1 : 0; 4097 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4098 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4099 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4100 4101 /* FIXME: handle invalid trans */ 4102 itd->itd.itd_bufr[2] |= 4103 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4104 4105 usb_syncmem(&itd->dma, 4106 itd->offs + offsetof(ehci_itd_t, itd_next), 4107 sizeof(ehci_itd_t), 4108 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4109 4110 prev = itd; 4111 } /* End of frame */ 4112 4113 stop = itd; 4114 stop->xfer_next = NULL; 4115 exfer->isoc_len = total_length; 4116 4117 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4118 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4119 4120 /* 4121 * Part 2: Transfer descriptors have now been set up, now they must 4122 * be scheduled into the period frame list. Erk. Not wanting to 4123 * complicate matters, transfer is denied if the transfer spans 4124 * more than the period frame list. 4125 */ 4126 4127 mutex_enter(&sc->sc_lock); 4128 4129 /* Start inserting frames */ 4130 if (epipe->u.isoc.cur_xfers > 0) { 4131 frindex = epipe->u.isoc.next_frame; 4132 } else { 4133 frindex = EOREAD4(sc, EHCI_FRINDEX); 4134 frindex = frindex >> 3; /* Erase microframe index */ 4135 frindex += 2; 4136 } 4137 4138 if (frindex >= sc->sc_flsize) 4139 frindex &= (sc->sc_flsize - 1); 4140 4141 /* What's the frame interval? */ 4142 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4143 if (i / USB_UFRAMES_PER_FRAME == 0) 4144 i = 1; 4145 else 4146 i /= USB_UFRAMES_PER_FRAME; 4147 4148 itd = start; 4149 for (j = 0; j < frames; j++) { 4150 if (itd == NULL) 4151 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4152 4153 itd->itd.itd_next = sc->sc_flist[frindex]; 4154 if (itd->itd.itd_next == 0) 4155 /* FIXME: frindex table gets initialized to NULL 4156 * or EHCI_NULL? */ 4157 itd->itd.itd_next = EHCI_NULL; 4158 4159 usb_syncmem(&itd->dma, 4160 itd->offs + offsetof(ehci_itd_t, itd_next), 4161 sizeof(itd->itd.itd_next), 4162 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4163 4164 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4165 4166 usb_syncmem(&sc->sc_fldma, 4167 sizeof(ehci_link_t) * frindex, 4168 sizeof(ehci_link_t), 4169 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4170 4171 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4172 sc->sc_softitds[frindex] = itd; 4173 if (itd->u.frame_list.next != NULL) 4174 itd->u.frame_list.next->u.frame_list.prev = itd; 4175 itd->slot = frindex; 4176 itd->u.frame_list.prev = NULL; 4177 4178 frindex += i; 4179 if (frindex >= sc->sc_flsize) 4180 frindex -= sc->sc_flsize; 4181 4182 itd = itd->xfer_next; 4183 } 4184 4185 epipe->u.isoc.cur_xfers++; 4186 epipe->u.isoc.next_frame = frindex; 4187 4188 exfer->itdstart = start; 4189 exfer->itdend = stop; 4190 exfer->sqtdstart = NULL; 4191 exfer->sqtdstart = NULL; 4192 4193 ehci_add_intr_list(sc, exfer); 4194 xfer->status = USBD_IN_PROGRESS; 4195 xfer->done = 0; 4196 mutex_exit(&sc->sc_lock); 4197 4198 if (sc->sc_bus.use_polling) { 4199 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4200 ehci_waitintr(sc, xfer); 4201 } 4202 4203 return USBD_IN_PROGRESS; 4204 } 4205 4206 Static void 4207 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4208 { 4209 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4210 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4211 } 4212 4213 Static void 4214 ehci_device_isoc_close(usbd_pipe_handle pipe) 4215 { 4216 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4217 } 4218 4219 Static void 4220 ehci_device_isoc_done(usbd_xfer_handle xfer) 4221 { 4222 struct ehci_xfer *exfer; 4223 ehci_softc_t *sc; 4224 struct ehci_pipe *epipe; 4225 4226 exfer = EXFER(xfer); 4227 sc = xfer->pipe->device->bus->hci_private; 4228 epipe = (struct ehci_pipe *) xfer->pipe; 4229 4230 KASSERT(mutex_owned(&sc->sc_lock)); 4231 4232 epipe->u.isoc.cur_xfers--; 4233 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4234 ehci_del_intr_list(sc, exfer); 4235 ehci_rem_free_itd_chain(sc, exfer); 4236 } 4237 4238 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4239 BUS_DMASYNC_POSTREAD); 4240 4241 } 4242
Indexes created Thu Oct 02 01:09:59 GMT 2025