ehci.c revision 1.181.6.6
1 /* $NetBSD: ehci.c,v 1.181.6.6 2012/02/20 02:12:23 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2011 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), and Jared D. McNeill 10 * (jmcneill (at) invisible.ca). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.181.6.6 2012/02/20 02:12:23 mrg Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/kmem.h> 66 #include <sys/device.h> 67 #include <sys/select.h> 68 #include <sys/proc.h> 69 #include <sys/queue.h> 70 #include <sys/mutex.h> 71 #include <sys/bus.h> 72 73 #include <machine/endian.h> 74 75 #include <dev/usb/usb.h> 76 #include <dev/usb/usbdi.h> 77 #include <dev/usb/usbdivar.h> 78 #include <dev/usb/usb_mem.h> 79 #include <dev/usb/usb_quirks.h> 80 81 #include <dev/usb/ehcireg.h> 82 #include <dev/usb/ehcivar.h> 83 #include <dev/usb/usbroothub_subr.h> 84 85 #ifdef EHCI_DEBUG 86 #include <sys/kprintf.h> 87 static void 88 ehciprintf(const char *fmt, ...) 89 { 90 va_list ap; 91 92 va_start(ap, fmt); 93 kprintf(fmt, TOLOG|TOCONS, NULL, NULL, ap); 94 va_end(ap); 95 } 96 97 #define DPRINTF(x) do { if (ehcidebug) ehciprintf x; } while(0) 98 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) ehciprintf x; } while (0) 99 int ehcidebug = 0; 100 #else 101 #define DPRINTF(x) 102 #define DPRINTFN(n,x) 103 #endif 104 105 struct ehci_pipe { 106 struct usbd_pipe pipe; 107 int nexttoggle; 108 109 ehci_soft_qh_t *sqh; 110 union { 111 ehci_soft_qtd_t *qtd; 112 /* ehci_soft_itd_t *itd; */ 113 } tail; 114 union { 115 /* Control pipe */ 116 struct { 117 usb_dma_t reqdma; 118 u_int length; 119 } ctl; 120 /* Interrupt pipe */ 121 struct { 122 u_int length; 123 } intr; 124 /* Bulk pipe */ 125 struct { 126 u_int length; 127 } bulk; 128 /* Iso pipe */ 129 struct { 130 u_int next_frame; 131 u_int cur_xfers; 132 } isoc; 133 } u; 134 }; 135 136 Static usbd_status ehci_open(usbd_pipe_handle); 137 Static void ehci_poll(struct usbd_bus *); 138 Static void ehci_softintr(void *); 139 Static int ehci_intr1(ehci_softc_t *); 140 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 141 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 142 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 143 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 144 Static void ehci_idone(struct ehci_xfer *); 145 Static void ehci_timeout(void *); 146 Static void ehci_timeout_task(void *); 147 Static void ehci_intrlist_timeout(void *); 148 Static void ehci_doorbell(void *); 149 Static void ehci_pcd(void *); 150 151 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 152 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 153 154 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 155 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 156 Static void ehci_get_locks(struct usbd_bus *, kmutex_t **, 157 kmutex_t **); 158 159 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 160 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 161 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 162 Static void ehci_root_ctrl_close(usbd_pipe_handle); 163 Static void ehci_root_ctrl_done(usbd_xfer_handle); 164 165 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 166 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 167 Static void ehci_root_intr_abort(usbd_xfer_handle); 168 Static void ehci_root_intr_close(usbd_pipe_handle); 169 Static void ehci_root_intr_done(usbd_xfer_handle); 170 171 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 172 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 173 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 174 Static void ehci_device_ctrl_close(usbd_pipe_handle); 175 Static void ehci_device_ctrl_done(usbd_xfer_handle); 176 177 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 178 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 179 Static void ehci_device_bulk_abort(usbd_xfer_handle); 180 Static void ehci_device_bulk_close(usbd_pipe_handle); 181 Static void ehci_device_bulk_done(usbd_xfer_handle); 182 183 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 184 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 185 Static void ehci_device_intr_abort(usbd_xfer_handle); 186 Static void ehci_device_intr_close(usbd_pipe_handle); 187 Static void ehci_device_intr_done(usbd_xfer_handle); 188 189 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 190 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 191 Static void ehci_device_isoc_abort(usbd_xfer_handle); 192 Static void ehci_device_isoc_close(usbd_pipe_handle); 193 Static void ehci_device_isoc_done(usbd_xfer_handle); 194 195 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 196 Static void ehci_noop(usbd_pipe_handle pipe); 197 198 Static void ehci_disown(ehci_softc_t *, int, int); 199 200 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 201 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 202 203 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 204 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 205 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 206 ehci_softc_t *, int, int, usbd_xfer_handle, 207 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 208 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 209 ehci_soft_qtd_t *); 210 211 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 212 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 213 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 214 struct ehci_xfer *exfer); 215 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 216 usbd_status status); 217 218 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 219 220 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 221 int ival); 222 223 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 224 ehci_soft_qh_t *); 225 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 226 ehci_soft_qh_t *); 227 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 228 Static void ehci_sync_hc(ehci_softc_t *); 229 230 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 231 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 232 233 #ifdef EHCI_DEBUG 234 Static void ehci_dump_regs(ehci_softc_t *); 235 void ehci_dump(void); 236 Static ehci_softc_t *theehci; 237 Static void ehci_dump_link(ehci_link_t, int); 238 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 239 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 240 Static void ehci_dump_qtd(ehci_qtd_t *); 241 Static void ehci_dump_sqh(ehci_soft_qh_t *); 242 #if notyet 243 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 244 Static void ehci_dump_itd(struct ehci_soft_itd *); 245 #endif 246 #ifdef DIAGNOSTIC 247 Static void ehci_dump_exfer(struct ehci_xfer *); 248 #endif 249 #endif 250 251 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 252 253 #define EHCI_INTR_ENDPT 1 254 255 #define ehci_add_intr_list(sc, ex) \ 256 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 257 #define ehci_del_intr_list(sc, ex) \ 258 do { \ 259 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 260 (ex)->inext.tqe_prev = NULL; \ 261 } while (0) 262 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 263 264 Static const struct usbd_bus_methods ehci_bus_methods = { 265 .open_pipe = ehci_open, 266 .soft_intr = ehci_softintr, 267 .do_poll = ehci_poll, 268 .allocm = ehci_allocm, 269 .freem = ehci_freem, 270 .allocx = ehci_allocx, 271 .freex = ehci_freex, 272 .get_locks = ehci_get_locks, 273 }; 274 275 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 276 .transfer = ehci_root_ctrl_transfer, 277 .start = ehci_root_ctrl_start, 278 .abort = ehci_root_ctrl_abort, 279 .close = ehci_root_ctrl_close, 280 .cleartoggle = ehci_noop, 281 .done = ehci_root_ctrl_done, 282 }; 283 284 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 285 .transfer = ehci_root_intr_transfer, 286 .start = ehci_root_intr_start, 287 .abort = ehci_root_intr_abort, 288 .close = ehci_root_intr_close, 289 .cleartoggle = ehci_noop, 290 .done = ehci_root_intr_done, 291 }; 292 293 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 294 .transfer = ehci_device_ctrl_transfer, 295 .start = ehci_device_ctrl_start, 296 .abort = ehci_device_ctrl_abort, 297 .close = ehci_device_ctrl_close, 298 .cleartoggle = ehci_noop, 299 .done = ehci_device_ctrl_done, 300 }; 301 302 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 303 .transfer = ehci_device_intr_transfer, 304 .start = ehci_device_intr_start, 305 .abort = ehci_device_intr_abort, 306 .close = ehci_device_intr_close, 307 .cleartoggle = ehci_device_clear_toggle, 308 .done = ehci_device_intr_done, 309 }; 310 311 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 312 .transfer = ehci_device_bulk_transfer, 313 .start = ehci_device_bulk_start, 314 .abort = ehci_device_bulk_abort, 315 .close = ehci_device_bulk_close, 316 .cleartoggle = ehci_device_clear_toggle, 317 .done = ehci_device_bulk_done, 318 }; 319 320 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 321 .transfer = ehci_device_isoc_transfer, 322 .start = ehci_device_isoc_start, 323 .abort = ehci_device_isoc_abort, 324 .close = ehci_device_isoc_close, 325 .cleartoggle = ehci_noop, 326 .done = ehci_device_isoc_done, 327 }; 328 329 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 330 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 331 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 332 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 333 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 334 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 335 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 336 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 337 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 338 }; 339 340 usbd_status 341 ehci_init(ehci_softc_t *sc) 342 { 343 u_int32_t vers, sparams, cparams, hcr; 344 u_int i; 345 usbd_status err; 346 ehci_soft_qh_t *sqh; 347 u_int ncomp; 348 349 DPRINTF(("ehci_init: start\n")); 350 #ifdef EHCI_DEBUG 351 theehci = sc; 352 #endif 353 354 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 355 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 356 cv_init(&sc->sc_softwake_cv, "ehciab"); 357 cv_init(&sc->sc_doorbell, "ehcidi"); 358 359 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 360 ehci_doorbell, sc); 361 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 362 ehci_pcd, sc); 363 364 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 365 366 vers = EREAD2(sc, EHCI_HCIVERSION); 367 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 368 vers >> 8, vers & 0xff); 369 370 sparams = EREAD4(sc, EHCI_HCSPARAMS); 371 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 372 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 373 ncomp = EHCI_HCS_N_CC(sparams); 374 if (ncomp != sc->sc_ncomp) { 375 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 376 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 377 #if NOHCI == 0 || NUHCI == 0 378 aprint_error("%s: ohci or uhci probably not configured\n", 379 device_xname(sc->sc_dev)); 380 #endif 381 if (ncomp < sc->sc_ncomp) 382 sc->sc_ncomp = ncomp; 383 } 384 if (sc->sc_ncomp > 0) { 385 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 386 aprint_normal("%s: companion controller%s, %d port%s each:", 387 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 388 EHCI_HCS_N_PCC(sparams), 389 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 390 for (i = 0; i < sc->sc_ncomp; i++) 391 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 392 aprint_normal("\n"); 393 } 394 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 395 cparams = EREAD4(sc, EHCI_HCCPARAMS); 396 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 397 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 398 399 if (EHCI_HCC_64BIT(cparams)) { 400 /* MUST clear segment register if 64 bit capable. */ 401 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 402 } 403 404 sc->sc_bus.usbrev = USBREV_2_0; 405 406 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 407 USB_MEM_RESERVE); 408 409 /* Reset the controller */ 410 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 411 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 412 usb_delay_ms(&sc->sc_bus, 1); 413 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 414 for (i = 0; i < 100; i++) { 415 usb_delay_ms(&sc->sc_bus, 1); 416 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 417 if (!hcr) 418 break; 419 } 420 if (hcr) { 421 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 422 return (USBD_IOERROR); 423 } 424 if (sc->sc_vendor_init) 425 sc->sc_vendor_init(sc); 426 427 /* 428 * If we are doing embedded transaction translation function, force 429 * the controller to host mode. 430 */ 431 if (sc->sc_flags & EHCIF_ETTF) { 432 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 433 usbmode &= ~EHCI_USBMODE_CM; 434 usbmode |= EHCI_USBMODE_CM_HOST; 435 EWRITE4(sc, EHCI_USBMODE, usbmode); 436 } 437 438 /* XXX need proper intr scheduling */ 439 sc->sc_rand = 96; 440 441 /* frame list size at default, read back what we got and use that */ 442 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 443 case 0: sc->sc_flsize = 1024; break; 444 case 1: sc->sc_flsize = 512; break; 445 case 2: sc->sc_flsize = 256; break; 446 case 3: return (USBD_IOERROR); 447 } 448 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 449 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 450 if (err) 451 return (err); 452 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 453 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 454 455 for (i = 0; i < sc->sc_flsize; i++) { 456 sc->sc_flist[i] = EHCI_NULL; 457 } 458 459 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 460 461 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 462 KM_SLEEP); 463 if (sc->sc_softitds == NULL) 464 return ENOMEM; 465 LIST_INIT(&sc->sc_freeitds); 466 TAILQ_INIT(&sc->sc_intrhead); 467 468 /* Set up the bus struct. */ 469 sc->sc_bus.methods = &ehci_bus_methods; 470 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 471 472 sc->sc_eintrs = EHCI_NORMAL_INTRS; 473 474 /* 475 * Allocate the interrupt dummy QHs. These are arranged to give poll 476 * intervals that are powers of 2 times 1ms. 477 */ 478 for (i = 0; i < EHCI_INTRQHS; i++) { 479 sqh = ehci_alloc_sqh(sc); 480 if (sqh == NULL) { 481 err = USBD_NOMEM; 482 goto bad1; 483 } 484 sc->sc_islots[i].sqh = sqh; 485 } 486 for (i = 0; i < EHCI_INTRQHS; i++) { 487 sqh = sc->sc_islots[i].sqh; 488 if (i == 0) { 489 /* The last (1ms) QH terminates. */ 490 sqh->qh.qh_link = EHCI_NULL; 491 sqh->next = NULL; 492 } else { 493 /* Otherwise the next QH has half the poll interval */ 494 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 495 sqh->qh.qh_link = htole32(sqh->next->physaddr | 496 EHCI_LINK_QH); 497 } 498 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 499 sqh->qh.qh_curqtd = EHCI_NULL; 500 sqh->next = NULL; 501 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 502 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 503 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 504 sqh->sqtd = NULL; 505 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 506 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 507 } 508 /* Point the frame list at the last level (128ms). */ 509 for (i = 0; i < sc->sc_flsize; i++) { 510 int j; 511 512 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 513 revbits[i & (EHCI_MAX_POLLRATE-1)]; 514 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 515 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 516 i)].sqh->physaddr); 517 } 518 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 519 BUS_DMASYNC_PREWRITE); 520 521 /* Allocate dummy QH that starts the async list. */ 522 sqh = ehci_alloc_sqh(sc); 523 if (sqh == NULL) { 524 err = USBD_NOMEM; 525 goto bad1; 526 } 527 /* Fill the QH */ 528 sqh->qh.qh_endp = 529 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 530 sqh->qh.qh_link = 531 htole32(sqh->physaddr | EHCI_LINK_QH); 532 sqh->qh.qh_curqtd = EHCI_NULL; 533 sqh->next = NULL; 534 /* Fill the overlay qTD */ 535 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 536 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 537 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 538 sqh->sqtd = NULL; 539 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 540 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 541 #ifdef EHCI_DEBUG 542 if (ehcidebug) { 543 ehci_dump_sqh(sqh); 544 } 545 #endif 546 547 /* Point to async list */ 548 sc->sc_async_head = sqh; 549 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 550 551 callout_init(&(sc->sc_tmo_intrlist), CALLOUT_MPSAFE); 552 553 /* Turn on controller */ 554 EOWRITE4(sc, EHCI_USBCMD, 555 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 556 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 557 EHCI_CMD_ASE | 558 EHCI_CMD_PSE | 559 EHCI_CMD_RS); 560 561 /* Take over port ownership */ 562 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 563 564 for (i = 0; i < 100; i++) { 565 usb_delay_ms(&sc->sc_bus, 1); 566 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 567 if (!hcr) 568 break; 569 } 570 if (hcr) { 571 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 572 return (USBD_IOERROR); 573 } 574 575 /* Enable interrupts */ 576 DPRINTFN(1,("ehci_init: enabling\n")); 577 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 578 579 return (USBD_NORMAL_COMPLETION); 580 581 #if 0 582 bad2: 583 ehci_free_sqh(sc, sc->sc_async_head); 584 #endif 585 bad1: 586 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 587 return (err); 588 } 589 590 int 591 ehci_intr(void *v) 592 { 593 ehci_softc_t *sc = v; 594 int ret = 0; 595 596 if (sc == NULL) 597 return 0; 598 599 mutex_spin_enter(&sc->sc_intr_lock); 600 601 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 602 goto done; 603 604 /* If we get an interrupt while polling, then just ignore it. */ 605 if (sc->sc_bus.use_polling) { 606 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 607 608 if (intrs) 609 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 610 #ifdef DIAGNOSTIC 611 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 612 #endif 613 goto done; 614 } 615 616 ret = ehci_intr1(sc); 617 618 done: 619 mutex_spin_exit(&sc->sc_intr_lock); 620 return ret; 621 } 622 623 Static int 624 ehci_intr1(ehci_softc_t *sc) 625 { 626 u_int32_t intrs, eintrs; 627 628 DPRINTFN(20,("ehci_intr1: enter\n")); 629 630 /* In case the interrupt occurs before initialization has completed. */ 631 if (sc == NULL) { 632 #ifdef DIAGNOSTIC 633 printf("ehci_intr1: sc == NULL\n"); 634 #endif 635 return (0); 636 } 637 638 KASSERT(mutex_owned(&sc->sc_intr_lock)); 639 640 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 641 if (!intrs) 642 return (0); 643 644 eintrs = intrs & sc->sc_eintrs; 645 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 646 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 647 (u_int)eintrs)); 648 if (!eintrs) 649 return (0); 650 651 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 652 sc->sc_bus.intr_context++; 653 sc->sc_bus.no_intrs++; 654 if (eintrs & EHCI_STS_IAA) { 655 DPRINTF(("ehci_intr1: door bell\n")); 656 kpreempt_disable(); 657 softint_schedule(sc->sc_doorbell_si); 658 kpreempt_enable(); 659 eintrs &= ~EHCI_STS_IAA; 660 } 661 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 662 DPRINTFN(5,("ehci_intr1: %s %s\n", 663 eintrs & EHCI_STS_INT ? "INT" : "", 664 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 665 usb_schedsoftintr(&sc->sc_bus); 666 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 667 } 668 if (eintrs & EHCI_STS_HSE) { 669 printf("%s: unrecoverable error, controller halted\n", 670 device_xname(sc->sc_dev)); 671 /* XXX what else */ 672 } 673 if (eintrs & EHCI_STS_PCD) { 674 kpreempt_disable(); 675 softint_schedule(sc->sc_pcd_si); 676 kpreempt_enable(); 677 eintrs &= ~EHCI_STS_PCD; 678 } 679 680 sc->sc_bus.intr_context--; 681 682 if (eintrs != 0) { 683 /* Block unprocessed interrupts. */ 684 sc->sc_eintrs &= ~eintrs; 685 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 686 printf("%s: blocking intrs 0x%x\n", 687 device_xname(sc->sc_dev), eintrs); 688 } 689 690 return (1); 691 } 692 693 Static void 694 ehci_doorbell(void *addr) 695 { 696 ehci_softc_t *sc = addr; 697 698 mutex_enter(&sc->sc_lock); 699 cv_broadcast(&sc->sc_doorbell); 700 mutex_exit(&sc->sc_lock); 701 } 702 703 Static void 704 ehci_pcd(void *addr) 705 { 706 ehci_softc_t *sc = addr; 707 usbd_xfer_handle xfer; 708 usbd_pipe_handle pipe; 709 u_char *p; 710 int i, m; 711 712 mutex_enter(&sc->sc_lock); 713 xfer = sc->sc_intrxfer; 714 715 if (xfer == NULL) { 716 /* Just ignore the change. */ 717 goto done; 718 } 719 720 pipe = xfer->pipe; 721 722 p = KERNADDR(&xfer->dmabuf, 0); 723 m = min(sc->sc_noport, xfer->length * 8 - 1); 724 memset(p, 0, xfer->length); 725 for (i = 1; i <= m; i++) { 726 /* Pick out CHANGE bits from the status reg. */ 727 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 728 p[i/8] |= 1 << (i%8); 729 } 730 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 731 xfer->actlen = xfer->length; 732 xfer->status = USBD_NORMAL_COMPLETION; 733 734 usb_transfer_complete(xfer); 735 736 done: 737 mutex_exit(&sc->sc_lock); 738 } 739 740 Static void 741 ehci_softintr(void *v) 742 { 743 struct usbd_bus *bus = v; 744 ehci_softc_t *sc = bus->hci_private; 745 struct ehci_xfer *ex, *nextex; 746 747 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 748 749 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 750 sc->sc_bus.intr_context)); 751 752 sc->sc_bus.intr_context++; 753 754 /* 755 * The only explanation I can think of for why EHCI is as brain dead 756 * as UHCI interrupt-wise is that Intel was involved in both. 757 * An interrupt just tells us that something is done, we have no 758 * clue what, so we need to scan through all active transfers. :-( 759 */ 760 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 761 nextex = TAILQ_NEXT(ex, inext); 762 ehci_check_intr(sc, ex); 763 } 764 765 /* Schedule a callout to catch any dropped transactions. */ 766 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 767 !TAILQ_EMPTY(&sc->sc_intrhead)) 768 callout_reset(&sc->sc_tmo_intrlist, 769 hz, ehci_intrlist_timeout, sc); 770 771 if (sc->sc_softwake) { 772 sc->sc_softwake = 0; 773 cv_broadcast(&sc->sc_softwake_cv); 774 } 775 776 sc->sc_bus.intr_context--; 777 } 778 779 /* Check for an interrupt. */ 780 Static void 781 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 782 { 783 int attr; 784 785 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 786 787 KASSERT(mutex_owned(&sc->sc_lock)); 788 789 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 790 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 791 ehci_check_itd_intr(sc, ex); 792 else 793 ehci_check_qh_intr(sc, ex); 794 795 return; 796 } 797 798 Static void 799 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 800 { 801 ehci_soft_qtd_t *sqtd, *lsqtd; 802 __uint32_t status; 803 804 KASSERT(mutex_owned(&sc->sc_lock)); 805 806 if (ex->sqtdstart == NULL) { 807 printf("ehci_check_qh_intr: not valid sqtd\n"); 808 return; 809 } 810 811 lsqtd = ex->sqtdend; 812 #ifdef DIAGNOSTIC 813 if (lsqtd == NULL) { 814 printf("ehci_check_qh_intr: lsqtd==0\n"); 815 return; 816 } 817 #endif 818 /* 819 * If the last TD is still active we need to check whether there 820 * is a an error somewhere in the middle, or whether there was a 821 * short packet (SPD and not ACTIVE). 822 */ 823 usb_syncmem(&lsqtd->dma, 824 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 825 sizeof(lsqtd->qtd.qtd_status), 826 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 827 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 828 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 829 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 830 usb_syncmem(&sqtd->dma, 831 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 832 sizeof(sqtd->qtd.qtd_status), 833 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 834 status = le32toh(sqtd->qtd.qtd_status); 835 usb_syncmem(&sqtd->dma, 836 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 837 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 838 /* If there's an active QTD the xfer isn't done. */ 839 if (status & EHCI_QTD_ACTIVE) 840 break; 841 /* Any kind of error makes the xfer done. */ 842 if (status & EHCI_QTD_HALTED) 843 goto done; 844 /* We want short packets, and it is short: it's done */ 845 if (EHCI_QTD_GET_BYTES(status) != 0) 846 goto done; 847 } 848 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 849 ex, ex->sqtdstart)); 850 usb_syncmem(&lsqtd->dma, 851 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 852 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 853 return; 854 } 855 done: 856 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 857 callout_stop(&ex->xfer.timeout_handle); 858 ehci_idone(ex); 859 } 860 861 Static void 862 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 863 ehci_soft_itd_t *itd; 864 int i; 865 866 KASSERT(mutex_owned(&sc->sc_lock)); 867 868 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 869 return; 870 871 if (ex->itdstart == NULL) { 872 printf("ehci_check_itd_intr: not valid itd\n"); 873 return; 874 } 875 876 itd = ex->itdend; 877 #ifdef DIAGNOSTIC 878 if (itd == NULL) { 879 printf("ehci_check_itd_intr: itdend == 0\n"); 880 return; 881 } 882 #endif 883 884 /* 885 * check no active transfers in last itd, meaning we're finished 886 */ 887 888 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 889 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 890 BUS_DMASYNC_POSTREAD); 891 892 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 893 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 894 break; 895 } 896 897 if (i == EHCI_ITD_NUFRAMES) { 898 goto done; /* All 8 descriptors inactive, it's done */ 899 } 900 901 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 902 ex->itdstart)); 903 return; 904 done: 905 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 906 callout_stop(&ex->xfer.timeout_handle); 907 ehci_idone(ex); 908 } 909 910 Static void 911 ehci_idone(struct ehci_xfer *ex) 912 { 913 usbd_xfer_handle xfer = &ex->xfer; 914 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 915 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 916 ehci_soft_qtd_t *sqtd, *lsqtd; 917 u_int32_t status = 0, nstatus = 0; 918 int actlen; 919 920 KASSERT(mutex_owned(&sc->sc_lock)); 921 922 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 923 924 #ifdef DIAGNOSTIC 925 { 926 if (ex->isdone) { 927 #ifdef EHCI_DEBUG 928 printf("ehci_idone: ex is done!\n "); 929 ehci_dump_exfer(ex); 930 #else 931 printf("ehci_idone: ex=%p is done!\n", ex); 932 #endif 933 return; 934 } 935 ex->isdone = 1; 936 } 937 #endif 938 if (xfer->status == USBD_CANCELLED || 939 xfer->status == USBD_TIMEOUT) { 940 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 941 return; 942 } 943 944 #ifdef EHCI_DEBUG 945 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 946 if (ehcidebug > 10) 947 ehci_dump_sqtds(ex->sqtdstart); 948 #endif 949 950 /* The transfer is done, compute actual length and status. */ 951 952 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 953 == UE_ISOCHRONOUS) { 954 /* Isoc transfer */ 955 struct ehci_soft_itd *itd; 956 int i, nframes, len, uframes; 957 958 nframes = 0; 959 actlen = 0; 960 961 i = xfer->pipe->endpoint->edesc->bInterval; 962 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 963 964 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 965 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 966 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 967 BUS_DMASYNC_POSTREAD); 968 969 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 970 /* XXX - driver didn't fill in the frame full 971 * of uframes. This leads to scheduling 972 * inefficiencies, but working around 973 * this doubles complexity of tracking 974 * an xfer. 975 */ 976 if (nframes >= xfer->nframes) 977 break; 978 979 status = le32toh(itd->itd.itd_ctl[i]); 980 len = EHCI_ITD_GET_LEN(status); 981 if (EHCI_ITD_GET_STATUS(status) != 0) 982 len = 0; /*No valid data on error*/ 983 984 xfer->frlengths[nframes++] = len; 985 actlen += len; 986 } 987 988 if (nframes >= xfer->nframes) 989 break; 990 } 991 992 xfer->actlen = actlen; 993 xfer->status = USBD_NORMAL_COMPLETION; 994 goto end; 995 } 996 997 /* Continue processing xfers using queue heads */ 998 999 lsqtd = ex->sqtdend; 1000 actlen = 0; 1001 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1002 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1003 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1004 nstatus = le32toh(sqtd->qtd.qtd_status); 1005 if (nstatus & EHCI_QTD_ACTIVE) 1006 break; 1007 1008 status = nstatus; 1009 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1010 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1011 } 1012 1013 1014 /* 1015 * If there are left over TDs we need to update the toggle. 1016 * The default pipe doesn't need it since control transfers 1017 * start the toggle at 0 every time. 1018 * For a short transfer we need to update the toggle for the missing 1019 * packets within the qTD. 1020 */ 1021 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1022 xfer->pipe->device->default_pipe != xfer->pipe) { 1023 DPRINTFN(2, ("ehci_idone: need toggle update " 1024 "status=%08x nstatus=%08x\n", status, nstatus)); 1025 #if 0 1026 ehci_dump_sqh(epipe->sqh); 1027 ehci_dump_sqtds(ex->sqtdstart); 1028 #endif 1029 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1030 } 1031 1032 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 1033 xfer->length, actlen, status)); 1034 xfer->actlen = actlen; 1035 if (status & EHCI_QTD_HALTED) { 1036 #ifdef EHCI_DEBUG 1037 char sbuf[128]; 1038 1039 snprintb(sbuf, sizeof(sbuf), 1040 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 1041 (u_int32_t)status); 1042 1043 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 1044 "status 0x%s\n", 1045 xfer->pipe->device->address, 1046 xfer->pipe->endpoint->edesc->bEndpointAddress, 1047 sbuf)); 1048 if (ehcidebug > 2) { 1049 ehci_dump_sqh(epipe->sqh); 1050 ehci_dump_sqtds(ex->sqtdstart); 1051 } 1052 #endif 1053 /* low&full speed has an extra error flag */ 1054 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1055 EHCI_QH_SPEED_HIGH) 1056 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1057 else 1058 status &= EHCI_QTD_STATERRS; 1059 if (status == 0) /* no other errors means a stall */ { 1060 xfer->status = USBD_STALLED; 1061 } else { 1062 xfer->status = USBD_IOERROR; /* more info XXX */ 1063 } 1064 /* XXX need to reset TT on missed microframe */ 1065 if (status & EHCI_QTD_MISSEDMICRO) { 1066 printf("%s: missed microframe, TT reset not " 1067 "implemented, hub might be inoperational\n", 1068 device_xname(sc->sc_dev)); 1069 } 1070 } else { 1071 xfer->status = USBD_NORMAL_COMPLETION; 1072 } 1073 1074 end: 1075 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1076 * during this call, before methods->done is called: dma sync required 1077 * beforehand? */ 1078 usb_transfer_complete(xfer); 1079 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1080 } 1081 1082 /* 1083 * Wait here until controller claims to have an interrupt. 1084 * Then call ehci_intr and return. Use timeout to avoid waiting 1085 * too long. 1086 */ 1087 Static void 1088 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1089 { 1090 int timo; 1091 u_int32_t intrs; 1092 1093 xfer->status = USBD_IN_PROGRESS; 1094 for (timo = xfer->timeout; timo >= 0; timo--) { 1095 usb_delay_ms(&sc->sc_bus, 1); 1096 if (sc->sc_dying) 1097 break; 1098 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1099 sc->sc_eintrs; 1100 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1101 #ifdef EHCI_DEBUG 1102 if (ehcidebug > 15) 1103 ehci_dump_regs(sc); 1104 #endif 1105 if (intrs) { 1106 mutex_spin_enter(&sc->sc_intr_lock); 1107 ehci_intr1(sc); 1108 mutex_spin_exit(&sc->sc_intr_lock); 1109 if (xfer->status != USBD_IN_PROGRESS) 1110 return; 1111 } 1112 } 1113 1114 /* Timeout */ 1115 DPRINTF(("ehci_waitintr: timeout\n")); 1116 xfer->status = USBD_TIMEOUT; 1117 mutex_enter(&sc->sc_lock); 1118 usb_transfer_complete(xfer); 1119 mutex_exit(&sc->sc_lock); 1120 /* XXX should free TD */ 1121 } 1122 1123 Static void 1124 ehci_poll(struct usbd_bus *bus) 1125 { 1126 ehci_softc_t *sc = bus->hci_private; 1127 #ifdef EHCI_DEBUG 1128 static int last; 1129 int new; 1130 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1131 if (new != last) { 1132 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1133 last = new; 1134 } 1135 #endif 1136 1137 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1138 mutex_spin_enter(&sc->sc_intr_lock); 1139 ehci_intr1(sc); 1140 mutex_spin_exit(&sc->sc_intr_lock); 1141 } 1142 } 1143 1144 void 1145 ehci_childdet(device_t self, device_t child) 1146 { 1147 struct ehci_softc *sc = device_private(self); 1148 1149 KASSERT(sc->sc_child == child); 1150 sc->sc_child = NULL; 1151 } 1152 1153 int 1154 ehci_detach(struct ehci_softc *sc, int flags) 1155 { 1156 usbd_xfer_handle xfer; 1157 int rv = 0; 1158 1159 if (sc->sc_child != NULL) 1160 rv = config_detach(sc->sc_child, flags); 1161 1162 if (rv != 0) 1163 return (rv); 1164 1165 callout_halt(&sc->sc_tmo_intrlist, NULL); 1166 callout_destroy(&sc->sc_tmo_intrlist); 1167 1168 /* XXX free other data structures XXX */ 1169 if (sc->sc_softitds) 1170 kmem_free(sc->sc_softitds, 1171 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1172 cv_destroy(&sc->sc_doorbell); 1173 cv_destroy(&sc->sc_softwake_cv); 1174 1175 softint_disestablish(sc->sc_doorbell_si); 1176 softint_disestablish(sc->sc_pcd_si); 1177 1178 while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 1179 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1180 kmem_free(xfer, sizeof(struct ehci_xfer)); 1181 } 1182 1183 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1184 1185 return (rv); 1186 } 1187 1188 1189 int 1190 ehci_activate(device_t self, enum devact act) 1191 { 1192 struct ehci_softc *sc = device_private(self); 1193 1194 switch (act) { 1195 case DVACT_DEACTIVATE: 1196 sc->sc_dying = 1; 1197 return 0; 1198 default: 1199 return EOPNOTSUPP; 1200 } 1201 } 1202 1203 /* 1204 * Handle suspend/resume. 1205 * 1206 * We need to switch to polling mode here, because this routine is 1207 * called from an interrupt context. This is all right since we 1208 * are almost suspended anyway. 1209 * 1210 * Note that this power handler isn't to be registered directly; the 1211 * bus glue needs to call out to it. 1212 */ 1213 bool 1214 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1215 { 1216 ehci_softc_t *sc = device_private(dv); 1217 int i; 1218 uint32_t cmd, hcr; 1219 1220 mutex_spin_enter(&sc->sc_intr_lock); 1221 sc->sc_bus.use_polling++; 1222 mutex_spin_exit(&sc->sc_intr_lock); 1223 1224 for (i = 1; i <= sc->sc_noport; i++) { 1225 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1226 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1227 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1228 } 1229 1230 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1231 1232 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1233 EOWRITE4(sc, EHCI_USBCMD, cmd); 1234 1235 for (i = 0; i < 100; i++) { 1236 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1237 if (hcr == 0) 1238 break; 1239 1240 usb_delay_ms(&sc->sc_bus, 1); 1241 } 1242 if (hcr != 0) 1243 printf("%s: reset timeout\n", device_xname(dv)); 1244 1245 cmd &= ~EHCI_CMD_RS; 1246 EOWRITE4(sc, EHCI_USBCMD, cmd); 1247 1248 for (i = 0; i < 100; i++) { 1249 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1250 if (hcr == EHCI_STS_HCH) 1251 break; 1252 1253 usb_delay_ms(&sc->sc_bus, 1); 1254 } 1255 if (hcr != EHCI_STS_HCH) 1256 printf("%s: config timeout\n", device_xname(dv)); 1257 1258 mutex_spin_enter(&sc->sc_intr_lock); 1259 sc->sc_bus.use_polling--; 1260 mutex_spin_exit(&sc->sc_intr_lock); 1261 1262 return true; 1263 } 1264 1265 bool 1266 ehci_resume(device_t dv, const pmf_qual_t *qual) 1267 { 1268 ehci_softc_t *sc = device_private(dv); 1269 int i; 1270 uint32_t cmd, hcr; 1271 1272 /* restore things in case the bios sucks */ 1273 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1274 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1275 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1276 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1277 1278 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1279 1280 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1281 1282 hcr = 0; 1283 for (i = 1; i <= sc->sc_noport; i++) { 1284 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1285 if ((cmd & EHCI_PS_PO) == 0 && 1286 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1287 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1288 hcr = 1; 1289 } 1290 } 1291 1292 if (hcr) { 1293 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1294 1295 for (i = 1; i <= sc->sc_noport; i++) { 1296 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1297 if ((cmd & EHCI_PS_PO) == 0 && 1298 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1299 EOWRITE4(sc, EHCI_PORTSC(i), 1300 cmd & ~EHCI_PS_FPR); 1301 } 1302 } 1303 1304 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1305 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1306 1307 for (i = 0; i < 100; i++) { 1308 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1309 if (hcr != EHCI_STS_HCH) 1310 break; 1311 1312 usb_delay_ms(&sc->sc_bus, 1); 1313 } 1314 if (hcr == EHCI_STS_HCH) 1315 printf("%s: config timeout\n", device_xname(dv)); 1316 1317 return true; 1318 } 1319 1320 /* 1321 * Shut down the controller when the system is going down. 1322 */ 1323 bool 1324 ehci_shutdown(device_t self, int flags) 1325 { 1326 ehci_softc_t *sc = device_private(self); 1327 1328 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1329 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1330 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1331 return true; 1332 } 1333 1334 Static usbd_status 1335 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1336 { 1337 struct ehci_softc *sc = bus->hci_private; 1338 usbd_status err; 1339 1340 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1341 if (err == USBD_NOMEM) 1342 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1343 #ifdef EHCI_DEBUG 1344 if (err) 1345 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1346 #endif 1347 return (err); 1348 } 1349 1350 Static void 1351 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1352 { 1353 struct ehci_softc *sc = bus->hci_private; 1354 1355 if (dma->block->flags & USB_DMA_RESERVE) { 1356 usb_reserve_freem(&sc->sc_dma_reserve, 1357 dma); 1358 return; 1359 } 1360 usb_freemem(&sc->sc_bus, dma); 1361 } 1362 1363 Static usbd_xfer_handle 1364 ehci_allocx(struct usbd_bus *bus) 1365 { 1366 struct ehci_softc *sc = bus->hci_private; 1367 usbd_xfer_handle xfer; 1368 1369 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1370 if (xfer != NULL) { 1371 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1372 #ifdef DIAGNOSTIC 1373 if (xfer->busy_free != XFER_FREE) { 1374 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1375 xfer->busy_free); 1376 } 1377 #endif 1378 } else { 1379 xfer = kmem_alloc(sizeof(struct ehci_xfer), KM_SLEEP); 1380 } 1381 if (xfer != NULL) { 1382 memset(xfer, 0, sizeof(struct ehci_xfer)); 1383 #ifdef DIAGNOSTIC 1384 EXFER(xfer)->isdone = 1; 1385 xfer->busy_free = XFER_BUSY; 1386 #endif 1387 } 1388 return (xfer); 1389 } 1390 1391 Static void 1392 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1393 { 1394 struct ehci_softc *sc = bus->hci_private; 1395 1396 #ifdef DIAGNOSTIC 1397 if (xfer->busy_free != XFER_BUSY) { 1398 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1399 xfer->busy_free); 1400 } 1401 xfer->busy_free = XFER_FREE; 1402 if (!EXFER(xfer)->isdone) { 1403 printf("ehci_freex: !isdone\n"); 1404 } 1405 #endif 1406 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1407 } 1408 1409 Static void 1410 ehci_get_locks(struct usbd_bus *bus, kmutex_t **intr, kmutex_t **thread) 1411 { 1412 struct ehci_softc *sc = bus->hci_private; 1413 1414 *intr = &sc->sc_intr_lock; 1415 *thread = &sc->sc_lock; 1416 } 1417 1418 Static void 1419 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1420 { 1421 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1422 1423 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1424 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1425 #ifdef EHCI_DEBUG 1426 if (ehcidebug) 1427 usbd_dump_pipe(pipe); 1428 #endif 1429 epipe->nexttoggle = 0; 1430 } 1431 1432 Static void 1433 ehci_noop(usbd_pipe_handle pipe) 1434 { 1435 } 1436 1437 #ifdef EHCI_DEBUG 1438 Static void 1439 ehci_dump_regs(ehci_softc_t *sc) 1440 { 1441 int i; 1442 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1443 EOREAD4(sc, EHCI_USBCMD), 1444 EOREAD4(sc, EHCI_USBSTS), 1445 EOREAD4(sc, EHCI_USBINTR)); 1446 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1447 EOREAD4(sc, EHCI_FRINDEX), 1448 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1449 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1450 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1451 for (i = 1; i <= sc->sc_noport; i++) 1452 printf("port %d status=0x%08x\n", i, 1453 EOREAD4(sc, EHCI_PORTSC(i))); 1454 } 1455 1456 /* 1457 * Unused function - this is meant to be called from a kernel 1458 * debugger. 1459 */ 1460 void 1461 ehci_dump(void) 1462 { 1463 ehci_dump_regs(theehci); 1464 } 1465 1466 Static void 1467 ehci_dump_link(ehci_link_t link, int type) 1468 { 1469 link = le32toh(link); 1470 printf("0x%08x", link); 1471 if (link & EHCI_LINK_TERMINATE) 1472 printf("<T>"); 1473 else { 1474 printf("<"); 1475 if (type) { 1476 switch (EHCI_LINK_TYPE(link)) { 1477 case EHCI_LINK_ITD: printf("ITD"); break; 1478 case EHCI_LINK_QH: printf("QH"); break; 1479 case EHCI_LINK_SITD: printf("SITD"); break; 1480 case EHCI_LINK_FSTN: printf("FSTN"); break; 1481 } 1482 } 1483 printf(">"); 1484 } 1485 } 1486 1487 Static void 1488 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1489 { 1490 int i; 1491 u_int32_t stop; 1492 1493 stop = 0; 1494 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1495 ehci_dump_sqtd(sqtd); 1496 usb_syncmem(&sqtd->dma, 1497 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1498 sizeof(sqtd->qtd), 1499 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1500 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1501 usb_syncmem(&sqtd->dma, 1502 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1503 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1504 } 1505 if (sqtd) 1506 printf("dump aborted, too many TDs\n"); 1507 } 1508 1509 Static void 1510 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1511 { 1512 usb_syncmem(&sqtd->dma, sqtd->offs, 1513 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1514 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1515 ehci_dump_qtd(&sqtd->qtd); 1516 usb_syncmem(&sqtd->dma, sqtd->offs, 1517 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1518 } 1519 1520 Static void 1521 ehci_dump_qtd(ehci_qtd_t *qtd) 1522 { 1523 u_int32_t s; 1524 char sbuf[128]; 1525 1526 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1527 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1528 printf("\n"); 1529 s = le32toh(qtd->qtd_status); 1530 snprintb(sbuf, sizeof(sbuf), 1531 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1532 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1533 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1534 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1535 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1536 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1537 EHCI_QTD_GET_PID(s), sbuf); 1538 for (s = 0; s < 5; s++) 1539 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1540 } 1541 1542 Static void 1543 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1544 { 1545 ehci_qh_t *qh = &sqh->qh; 1546 u_int32_t endp, endphub; 1547 1548 usb_syncmem(&sqh->dma, sqh->offs, 1549 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1550 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1551 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1552 endp = le32toh(qh->qh_endp); 1553 printf(" endp=0x%08x\n", endp); 1554 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1555 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1556 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1557 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1558 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1559 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1560 EHCI_QH_GET_NRL(endp)); 1561 endphub = le32toh(qh->qh_endphub); 1562 printf(" endphub=0x%08x\n", endphub); 1563 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1564 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1565 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1566 EHCI_QH_GET_MULT(endphub)); 1567 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1568 printf("Overlay qTD:\n"); 1569 ehci_dump_qtd(&qh->qh_qtd); 1570 usb_syncmem(&sqh->dma, sqh->offs, 1571 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1572 } 1573 1574 #if notyet 1575 Static void 1576 ehci_dump_itd(struct ehci_soft_itd *itd) 1577 { 1578 ehci_isoc_trans_t t; 1579 ehci_isoc_bufr_ptr_t b, b2, b3; 1580 int i; 1581 1582 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1583 1584 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1585 t = le32toh(itd->itd.itd_ctl[i]); 1586 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1587 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1588 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1589 EHCI_ITD_GET_OFFS(t)); 1590 } 1591 printf("ITDbufr: "); 1592 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1593 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1594 1595 b = le32toh(itd->itd.itd_bufr[0]); 1596 b2 = le32toh(itd->itd.itd_bufr[1]); 1597 b3 = le32toh(itd->itd.itd_bufr[2]); 1598 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1599 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1600 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1601 } 1602 1603 Static void 1604 ehci_dump_sitd(struct ehci_soft_itd *itd) 1605 { 1606 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1607 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1608 itd->xfer_next, itd->physaddr, itd->slot); 1609 } 1610 #endif 1611 1612 #ifdef DIAGNOSTIC 1613 Static void 1614 ehci_dump_exfer(struct ehci_xfer *ex) 1615 { 1616 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1617 } 1618 #endif 1619 #endif 1620 1621 Static usbd_status 1622 ehci_open(usbd_pipe_handle pipe) 1623 { 1624 usbd_device_handle dev = pipe->device; 1625 ehci_softc_t *sc = dev->bus->hci_private; 1626 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1627 u_int8_t addr = dev->address; 1628 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1629 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1630 ehci_soft_qh_t *sqh; 1631 usbd_status err; 1632 int ival, speed, naks; 1633 int hshubaddr, hshubport; 1634 1635 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1636 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1637 1638 if (dev->myhsport) { 1639 /* 1640 * When directly attached FS/LS device while doing embedded 1641 * transaction translations and we are the hub, set the hub 1642 * adddress to 0 (us). 1643 */ 1644 if (!(sc->sc_flags & EHCIF_ETTF) 1645 || (dev->myhsport->parent->address != sc->sc_addr)) { 1646 hshubaddr = dev->myhsport->parent->address; 1647 } else { 1648 hshubaddr = 0; 1649 } 1650 hshubport = dev->myhsport->portno; 1651 } else { 1652 hshubaddr = 0; 1653 hshubport = 0; 1654 } 1655 1656 if (sc->sc_dying) 1657 return (USBD_IOERROR); 1658 1659 /* toggle state needed for bulk endpoints */ 1660 epipe->nexttoggle = pipe->endpoint->datatoggle; 1661 1662 if (addr == sc->sc_addr) { 1663 switch (ed->bEndpointAddress) { 1664 case USB_CONTROL_ENDPOINT: 1665 pipe->methods = &ehci_root_ctrl_methods; 1666 break; 1667 case UE_DIR_IN | EHCI_INTR_ENDPT: 1668 pipe->methods = &ehci_root_intr_methods; 1669 break; 1670 default: 1671 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1672 ed->bEndpointAddress)); 1673 return (USBD_INVAL); 1674 } 1675 return (USBD_NORMAL_COMPLETION); 1676 } 1677 1678 /* XXX All this stuff is only valid for async. */ 1679 switch (dev->speed) { 1680 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1681 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1682 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1683 default: panic("ehci_open: bad device speed %d", dev->speed); 1684 } 1685 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1686 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1687 "isoc endpoint.\n"); 1688 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1689 "attached to a USB2 hub, and transaction translations are " 1690 "not yet supported.\n"); 1691 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1692 "root hub instead.\n"); 1693 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1694 hshubaddr, hshubport)); 1695 return USBD_INVAL; 1696 } 1697 1698 /* 1699 * For interrupt transfer, nak throttling must be disabled, but for 1700 * the other transfer type, nak throttling should be enabled from the 1701 * veiwpoint that avoids the memory thrashing. 1702 */ 1703 naks = (xfertype == UE_INTERRUPT) ? 0 1704 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1705 1706 /* Allocate sqh for everything, save isoc xfers */ 1707 if (xfertype != UE_ISOCHRONOUS) { 1708 sqh = ehci_alloc_sqh(sc); 1709 if (sqh == NULL) 1710 return (USBD_NOMEM); 1711 /* qh_link filled when the QH is added */ 1712 sqh->qh.qh_endp = htole32( 1713 EHCI_QH_SET_ADDR(addr) | 1714 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1715 EHCI_QH_SET_EPS(speed) | 1716 EHCI_QH_DTC | 1717 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1718 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1719 EHCI_QH_CTL : 0) | 1720 EHCI_QH_SET_NRL(naks) 1721 ); 1722 sqh->qh.qh_endphub = htole32( 1723 EHCI_QH_SET_MULT(1) | 1724 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1725 ); 1726 if (speed != EHCI_QH_SPEED_HIGH) 1727 sqh->qh.qh_endphub |= htole32( 1728 EHCI_QH_SET_PORT(hshubport) | 1729 EHCI_QH_SET_HUBA(hshubaddr) | 1730 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1731 ); 1732 sqh->qh.qh_curqtd = EHCI_NULL; 1733 /* Fill the overlay qTD */ 1734 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1735 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1736 sqh->qh.qh_qtd.qtd_status = htole32(0); 1737 1738 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1739 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1740 epipe->sqh = sqh; 1741 } else { 1742 sqh = NULL; 1743 } /*xfertype == UE_ISOC*/ 1744 1745 switch (xfertype) { 1746 case UE_CONTROL: 1747 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1748 0, &epipe->u.ctl.reqdma); 1749 #ifdef EHCI_DEBUG 1750 if (err) 1751 printf("ehci_open: usb_allocmem()=%d\n", err); 1752 #endif 1753 if (err) 1754 goto bad; 1755 pipe->methods = &ehci_device_ctrl_methods; 1756 mutex_enter(&sc->sc_lock); 1757 ehci_add_qh(sc, sqh, sc->sc_async_head); 1758 mutex_exit(&sc->sc_lock); 1759 break; 1760 case UE_BULK: 1761 pipe->methods = &ehci_device_bulk_methods; 1762 mutex_enter(&sc->sc_lock); 1763 ehci_add_qh(sc, sqh, sc->sc_async_head); 1764 mutex_exit(&sc->sc_lock); 1765 break; 1766 case UE_INTERRUPT: 1767 pipe->methods = &ehci_device_intr_methods; 1768 ival = pipe->interval; 1769 if (ival == USBD_DEFAULT_INTERVAL) { 1770 if (speed == EHCI_QH_SPEED_HIGH) { 1771 if (ed->bInterval > 16) { 1772 /* 1773 * illegal with high-speed, but there 1774 * were documentation bugs in the spec, 1775 * so be generous 1776 */ 1777 ival = 256; 1778 } else 1779 ival = (1 << (ed->bInterval - 1)) / 8; 1780 } else 1781 ival = ed->bInterval; 1782 } 1783 err = ehci_device_setintr(sc, sqh, ival); 1784 if (err) 1785 goto bad; 1786 break; 1787 case UE_ISOCHRONOUS: 1788 pipe->methods = &ehci_device_isoc_methods; 1789 if (ed->bInterval == 0 || ed->bInterval > 16) { 1790 printf("ehci: opening pipe with invalid bInterval\n"); 1791 err = USBD_INVAL; 1792 goto bad; 1793 } 1794 if (UGETW(ed->wMaxPacketSize) == 0) { 1795 printf("ehci: zero length endpoint open request\n"); 1796 err = USBD_INVAL; 1797 goto bad; 1798 } 1799 epipe->u.isoc.next_frame = 0; 1800 epipe->u.isoc.cur_xfers = 0; 1801 break; 1802 default: 1803 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1804 err = USBD_INVAL; 1805 goto bad; 1806 } 1807 return (USBD_NORMAL_COMPLETION); 1808 1809 bad: 1810 if (sqh != NULL) 1811 ehci_free_sqh(sc, sqh); 1812 return (err); 1813 } 1814 1815 /* 1816 * Add an ED to the schedule. Called with USB thread lock held. 1817 */ 1818 Static void 1819 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1820 { 1821 1822 KASSERT(mutex_owned(&sc->sc_lock)); 1823 1824 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1825 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1826 sqh->next = head->next; 1827 sqh->qh.qh_link = head->qh.qh_link; 1828 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1829 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1830 head->next = sqh; 1831 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1832 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1833 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1834 1835 #ifdef EHCI_DEBUG 1836 if (ehcidebug > 5) { 1837 printf("ehci_add_qh:\n"); 1838 ehci_dump_sqh(sqh); 1839 } 1840 #endif 1841 } 1842 1843 /* 1844 * Remove an ED from the schedule. Called with USB thread lock held. 1845 */ 1846 Static void 1847 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1848 { 1849 ehci_soft_qh_t *p; 1850 1851 KASSERT(mutex_owned(&sc->sc_lock)); 1852 1853 /* XXX */ 1854 for (p = head; p != NULL && p->next != sqh; p = p->next) 1855 ; 1856 if (p == NULL) 1857 panic("ehci_rem_qh: ED not found"); 1858 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1859 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1860 p->next = sqh->next; 1861 p->qh.qh_link = sqh->qh.qh_link; 1862 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1863 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1864 1865 ehci_sync_hc(sc); 1866 } 1867 1868 Static void 1869 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1870 { 1871 int i; 1872 u_int32_t status; 1873 1874 /* Save toggle bit and ping status. */ 1875 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1876 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1877 status = sqh->qh.qh_qtd.qtd_status & 1878 htole32(EHCI_QTD_TOGGLE_MASK | 1879 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1880 /* Set HALTED to make hw leave it alone. */ 1881 sqh->qh.qh_qtd.qtd_status = 1882 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1883 usb_syncmem(&sqh->dma, 1884 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1885 sizeof(sqh->qh.qh_qtd.qtd_status), 1886 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1887 sqh->qh.qh_curqtd = 0; 1888 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1889 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1890 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1891 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1892 sqh->sqtd = sqtd; 1893 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1894 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1895 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1896 sqh->qh.qh_qtd.qtd_status = status; 1897 usb_syncmem(&sqh->dma, 1898 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1899 sizeof(sqh->qh.qh_qtd.qtd_status), 1900 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1901 } 1902 1903 /* 1904 * Ensure that the HC has released all references to the QH. We do this 1905 * by asking for a Async Advance Doorbell interrupt and then we wait for 1906 * the interrupt. 1907 * To make this easier we first obtain exclusive use of the doorbell. 1908 */ 1909 Static void 1910 ehci_sync_hc(ehci_softc_t *sc) 1911 { 1912 int error; 1913 1914 KASSERT(mutex_owned(&sc->sc_lock)); 1915 1916 if (sc->sc_dying) { 1917 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1918 return; 1919 } 1920 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1921 /* ask for doorbell */ 1922 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1923 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1924 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1925 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 1926 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1927 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1928 #ifdef DIAGNOSTIC 1929 if (error) 1930 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 1931 #endif 1932 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1933 } 1934 1935 /*Call at splusb*/ 1936 Static void 1937 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1938 { 1939 struct ehci_soft_itd *itd, *prev; 1940 1941 prev = NULL; 1942 1943 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1944 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1945 1946 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1947 prev = itd->u.frame_list.prev; 1948 /* Unlink itd from hardware chain, or frame array */ 1949 if (prev == NULL) { /* We're at the table head */ 1950 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1951 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1952 usb_syncmem(&sc->sc_fldma, 1953 sizeof(ehci_link_t) * itd->slot, 1954 sizeof(ehci_link_t), 1955 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1956 1957 if (itd->u.frame_list.next != NULL) 1958 itd->u.frame_list.next->u.frame_list.prev = NULL; 1959 } else { 1960 /* XXX this part is untested... */ 1961 prev->itd.itd_next = itd->itd.itd_next; 1962 usb_syncmem(&itd->dma, 1963 itd->offs + offsetof(ehci_itd_t, itd_next), 1964 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1965 1966 prev->u.frame_list.next = itd->u.frame_list.next; 1967 if (itd->u.frame_list.next != NULL) 1968 itd->u.frame_list.next->u.frame_list.prev = prev; 1969 } 1970 } 1971 1972 prev = NULL; 1973 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1974 if (prev != NULL) 1975 ehci_free_itd(sc, prev); 1976 prev = itd; 1977 } 1978 if (prev) 1979 ehci_free_itd(sc, prev); 1980 exfer->itdstart = NULL; 1981 exfer->itdend = NULL; 1982 } 1983 1984 /***********/ 1985 1986 /* 1987 * Data structures and routines to emulate the root hub. 1988 */ 1989 Static usb_device_descriptor_t ehci_devd = { 1990 USB_DEVICE_DESCRIPTOR_SIZE, 1991 UDESC_DEVICE, /* type */ 1992 {0x00, 0x02}, /* USB version */ 1993 UDCLASS_HUB, /* class */ 1994 UDSUBCLASS_HUB, /* subclass */ 1995 UDPROTO_HSHUBSTT, /* protocol */ 1996 64, /* max packet */ 1997 {0},{0},{0x00,0x01}, /* device id */ 1998 1,2,0, /* string indicies */ 1999 1 /* # of configurations */ 2000 }; 2001 2002 Static const usb_device_qualifier_t ehci_odevd = { 2003 USB_DEVICE_DESCRIPTOR_SIZE, 2004 UDESC_DEVICE_QUALIFIER, /* type */ 2005 {0x00, 0x02}, /* USB version */ 2006 UDCLASS_HUB, /* class */ 2007 UDSUBCLASS_HUB, /* subclass */ 2008 UDPROTO_FSHUB, /* protocol */ 2009 64, /* max packet */ 2010 1, /* # of configurations */ 2011 0 2012 }; 2013 2014 Static const usb_config_descriptor_t ehci_confd = { 2015 USB_CONFIG_DESCRIPTOR_SIZE, 2016 UDESC_CONFIG, 2017 {USB_CONFIG_DESCRIPTOR_SIZE + 2018 USB_INTERFACE_DESCRIPTOR_SIZE + 2019 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2020 1, 2021 1, 2022 0, 2023 UC_ATTR_MBO | UC_SELF_POWERED, 2024 0 /* max power */ 2025 }; 2026 2027 Static const usb_interface_descriptor_t ehci_ifcd = { 2028 USB_INTERFACE_DESCRIPTOR_SIZE, 2029 UDESC_INTERFACE, 2030 0, 2031 0, 2032 1, 2033 UICLASS_HUB, 2034 UISUBCLASS_HUB, 2035 UIPROTO_HSHUBSTT, 2036 0 2037 }; 2038 2039 Static const usb_endpoint_descriptor_t ehci_endpd = { 2040 USB_ENDPOINT_DESCRIPTOR_SIZE, 2041 UDESC_ENDPOINT, 2042 UE_DIR_IN | EHCI_INTR_ENDPT, 2043 UE_INTERRUPT, 2044 {8, 0}, /* max packet */ 2045 12 2046 }; 2047 2048 Static const usb_hub_descriptor_t ehci_hubd = { 2049 USB_HUB_DESCRIPTOR_SIZE, 2050 UDESC_HUB, 2051 0, 2052 {0,0}, 2053 0, 2054 0, 2055 {""}, 2056 {""}, 2057 }; 2058 2059 /* 2060 * Simulate a hardware hub by handling all the necessary requests. 2061 */ 2062 Static usbd_status 2063 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2064 { 2065 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2066 usbd_status err; 2067 2068 /* Insert last in queue. */ 2069 mutex_enter(&sc->sc_lock); 2070 err = usb_insert_transfer(xfer); 2071 mutex_exit(&sc->sc_lock); 2072 if (err) 2073 return (err); 2074 2075 /* Pipe isn't running, start first */ 2076 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2077 } 2078 2079 Static usbd_status 2080 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2081 { 2082 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2083 usb_device_request_t *req; 2084 void *buf = NULL; 2085 int port, i; 2086 int len, value, index, l, totlen = 0; 2087 usb_port_status_t ps; 2088 usb_hub_descriptor_t hubd; 2089 usbd_status err; 2090 u_int32_t v; 2091 2092 if (sc->sc_dying) 2093 return (USBD_IOERROR); 2094 2095 #ifdef DIAGNOSTIC 2096 if (!(xfer->rqflags & URQ_REQUEST)) 2097 /* XXX panic */ 2098 return (USBD_INVAL); 2099 #endif 2100 req = &xfer->request; 2101 2102 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2103 req->bmRequestType, req->bRequest)); 2104 2105 len = UGETW(req->wLength); 2106 value = UGETW(req->wValue); 2107 index = UGETW(req->wIndex); 2108 2109 if (len != 0) 2110 buf = KERNADDR(&xfer->dmabuf, 0); 2111 2112 #define C(x,y) ((x) | ((y) << 8)) 2113 switch(C(req->bRequest, req->bmRequestType)) { 2114 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2115 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2116 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2117 /* 2118 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2119 * for the integrated root hub. 2120 */ 2121 break; 2122 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2123 if (len > 0) { 2124 *(u_int8_t *)buf = sc->sc_conf; 2125 totlen = 1; 2126 } 2127 break; 2128 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2129 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2130 if (len == 0) 2131 break; 2132 switch(value >> 8) { 2133 case UDESC_DEVICE: 2134 if ((value & 0xff) != 0) { 2135 err = USBD_IOERROR; 2136 goto ret; 2137 } 2138 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2139 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2140 memcpy(buf, &ehci_devd, l); 2141 break; 2142 /* 2143 * We can't really operate at another speed, but the spec says 2144 * we need this descriptor. 2145 */ 2146 case UDESC_DEVICE_QUALIFIER: 2147 if ((value & 0xff) != 0) { 2148 err = USBD_IOERROR; 2149 goto ret; 2150 } 2151 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2152 memcpy(buf, &ehci_odevd, l); 2153 break; 2154 /* 2155 * We can't really operate at another speed, but the spec says 2156 * we need this descriptor. 2157 */ 2158 case UDESC_OTHER_SPEED_CONFIGURATION: 2159 case UDESC_CONFIG: 2160 if ((value & 0xff) != 0) { 2161 err = USBD_IOERROR; 2162 goto ret; 2163 } 2164 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2165 memcpy(buf, &ehci_confd, l); 2166 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2167 value >> 8; 2168 buf = (char *)buf + l; 2169 len -= l; 2170 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2171 totlen += l; 2172 memcpy(buf, &ehci_ifcd, l); 2173 buf = (char *)buf + l; 2174 len -= l; 2175 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2176 totlen += l; 2177 memcpy(buf, &ehci_endpd, l); 2178 break; 2179 case UDESC_STRING: 2180 #define sd ((usb_string_descriptor_t *)buf) 2181 switch (value & 0xff) { 2182 case 0: /* Language table */ 2183 totlen = usb_makelangtbl(sd, len); 2184 break; 2185 case 1: /* Vendor */ 2186 totlen = usb_makestrdesc(sd, len, 2187 sc->sc_vendor); 2188 break; 2189 case 2: /* Product */ 2190 totlen = usb_makestrdesc(sd, len, 2191 "EHCI root hub"); 2192 break; 2193 } 2194 #undef sd 2195 break; 2196 default: 2197 err = USBD_IOERROR; 2198 goto ret; 2199 } 2200 break; 2201 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2202 if (len > 0) { 2203 *(u_int8_t *)buf = 0; 2204 totlen = 1; 2205 } 2206 break; 2207 case C(UR_GET_STATUS, UT_READ_DEVICE): 2208 if (len > 1) { 2209 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2210 totlen = 2; 2211 } 2212 break; 2213 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2214 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2215 if (len > 1) { 2216 USETW(((usb_status_t *)buf)->wStatus, 0); 2217 totlen = 2; 2218 } 2219 break; 2220 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2221 if (value >= USB_MAX_DEVICES) { 2222 err = USBD_IOERROR; 2223 goto ret; 2224 } 2225 sc->sc_addr = value; 2226 break; 2227 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2228 if (value != 0 && value != 1) { 2229 err = USBD_IOERROR; 2230 goto ret; 2231 } 2232 sc->sc_conf = value; 2233 break; 2234 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2235 break; 2236 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2237 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2238 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2239 err = USBD_IOERROR; 2240 goto ret; 2241 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2242 break; 2243 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2244 break; 2245 /* Hub requests */ 2246 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2247 break; 2248 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2249 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2250 "port=%d feature=%d\n", 2251 index, value)); 2252 if (index < 1 || index > sc->sc_noport) { 2253 err = USBD_IOERROR; 2254 goto ret; 2255 } 2256 port = EHCI_PORTSC(index); 2257 v = EOREAD4(sc, port); 2258 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2259 v &= ~EHCI_PS_CLEAR; 2260 switch(value) { 2261 case UHF_PORT_ENABLE: 2262 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2263 break; 2264 case UHF_PORT_SUSPEND: 2265 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2266 break; 2267 v &= ~EHCI_PS_SUSP; 2268 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2269 /* see USB2 spec ch. 7.1.7.7 */ 2270 usb_delay_ms(&sc->sc_bus, 20); 2271 EOWRITE4(sc, port, v); 2272 usb_delay_ms(&sc->sc_bus, 2); 2273 #ifdef DEBUG 2274 v = EOREAD4(sc, port); 2275 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2276 printf("ehci: resume failed: %x\n", v); 2277 #endif 2278 break; 2279 case UHF_PORT_POWER: 2280 if (sc->sc_hasppc) 2281 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2282 break; 2283 case UHF_PORT_TEST: 2284 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2285 "%d\n", index)); 2286 break; 2287 case UHF_PORT_INDICATOR: 2288 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2289 "%d\n", index)); 2290 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2291 break; 2292 case UHF_C_PORT_CONNECTION: 2293 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2294 break; 2295 case UHF_C_PORT_ENABLE: 2296 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2297 break; 2298 case UHF_C_PORT_SUSPEND: 2299 /* how? */ 2300 break; 2301 case UHF_C_PORT_OVER_CURRENT: 2302 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2303 break; 2304 case UHF_C_PORT_RESET: 2305 sc->sc_isreset[index] = 0; 2306 break; 2307 default: 2308 err = USBD_IOERROR; 2309 goto ret; 2310 } 2311 #if 0 2312 switch(value) { 2313 case UHF_C_PORT_CONNECTION: 2314 case UHF_C_PORT_ENABLE: 2315 case UHF_C_PORT_SUSPEND: 2316 case UHF_C_PORT_OVER_CURRENT: 2317 case UHF_C_PORT_RESET: 2318 default: 2319 break; 2320 } 2321 #endif 2322 break; 2323 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2324 if (len == 0) 2325 break; 2326 if ((value & 0xff) != 0) { 2327 err = USBD_IOERROR; 2328 goto ret; 2329 } 2330 hubd = ehci_hubd; 2331 hubd.bNbrPorts = sc->sc_noport; 2332 v = EOREAD4(sc, EHCI_HCSPARAMS); 2333 USETW(hubd.wHubCharacteristics, 2334 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2335 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2336 ? UHD_PORT_IND : 0); 2337 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2338 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2339 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2340 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2341 l = min(len, hubd.bDescLength); 2342 totlen = l; 2343 memcpy(buf, &hubd, l); 2344 break; 2345 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2346 if (len != 4) { 2347 err = USBD_IOERROR; 2348 goto ret; 2349 } 2350 memset(buf, 0, len); /* ? XXX */ 2351 totlen = len; 2352 break; 2353 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2354 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2355 index)); 2356 if (index < 1 || index > sc->sc_noport) { 2357 err = USBD_IOERROR; 2358 goto ret; 2359 } 2360 if (len != 4) { 2361 err = USBD_IOERROR; 2362 goto ret; 2363 } 2364 v = EOREAD4(sc, EHCI_PORTSC(index)); 2365 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2366 2367 i = UPS_HIGH_SPEED; 2368 #if 0 2369 if (sc->sc_flags & EHCIF_ETTF) { 2370 /* 2371 * If we are doing embedded transaction translation, 2372 * then directly attached LS/FS devices are reset by 2373 * the EHCI controller itself. PSPD is encoded 2374 * the same way as in USBSTATUS. 2375 */ 2376 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2377 } 2378 #endif 2379 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2380 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2381 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2382 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2383 if (v & EHCI_PS_PR) i |= UPS_RESET; 2384 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2385 if (sc->sc_vendor_port_status) 2386 i = sc->sc_vendor_port_status(sc, v, i); 2387 USETW(ps.wPortStatus, i); 2388 i = 0; 2389 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2390 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2391 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2392 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2393 USETW(ps.wPortChange, i); 2394 l = min(len, sizeof ps); 2395 memcpy(buf, &ps, l); 2396 totlen = l; 2397 break; 2398 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2399 err = USBD_IOERROR; 2400 goto ret; 2401 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2402 break; 2403 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2404 if (index < 1 || index > sc->sc_noport) { 2405 err = USBD_IOERROR; 2406 goto ret; 2407 } 2408 port = EHCI_PORTSC(index); 2409 v = EOREAD4(sc, port); 2410 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2411 v &= ~EHCI_PS_CLEAR; 2412 switch(value) { 2413 case UHF_PORT_ENABLE: 2414 EOWRITE4(sc, port, v | EHCI_PS_PE); 2415 break; 2416 case UHF_PORT_SUSPEND: 2417 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2418 break; 2419 case UHF_PORT_RESET: 2420 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2421 index)); 2422 if (EHCI_PS_IS_LOWSPEED(v) 2423 && sc->sc_ncomp > 0 2424 && !(sc->sc_flags & EHCIF_ETTF)) { 2425 /* 2426 * Low speed device on non-ETTF controller or 2427 * unaccompanied controller, give up ownership. 2428 */ 2429 ehci_disown(sc, index, 1); 2430 break; 2431 } 2432 /* Start reset sequence. */ 2433 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2434 EOWRITE4(sc, port, v | EHCI_PS_PR); 2435 /* Wait for reset to complete. */ 2436 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2437 if (sc->sc_dying) { 2438 err = USBD_IOERROR; 2439 goto ret; 2440 } 2441 /* 2442 * An embedded transaction translater will automatically 2443 * terminate the reset sequence so there's no need to 2444 * it. 2445 */ 2446 v = EOREAD4(sc, port); 2447 if (v & EHCI_PS_PR) { 2448 /* Terminate reset sequence. */ 2449 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2450 /* Wait for HC to complete reset. */ 2451 usb_delay_ms(&sc->sc_bus, 2452 EHCI_PORT_RESET_COMPLETE); 2453 if (sc->sc_dying) { 2454 err = USBD_IOERROR; 2455 goto ret; 2456 } 2457 } 2458 2459 v = EOREAD4(sc, port); 2460 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2461 if (v & EHCI_PS_PR) { 2462 printf("%s: port reset timeout\n", 2463 device_xname(sc->sc_dev)); 2464 return (USBD_TIMEOUT); 2465 } 2466 if (!(v & EHCI_PS_PE)) { 2467 /* Not a high speed device, give up ownership.*/ 2468 ehci_disown(sc, index, 0); 2469 break; 2470 } 2471 sc->sc_isreset[index] = 1; 2472 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2473 index, v)); 2474 break; 2475 case UHF_PORT_POWER: 2476 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2477 "%d (has PPC = %d)\n", index, 2478 sc->sc_hasppc)); 2479 if (sc->sc_hasppc) 2480 EOWRITE4(sc, port, v | EHCI_PS_PP); 2481 break; 2482 case UHF_PORT_TEST: 2483 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2484 "%d\n", index)); 2485 break; 2486 case UHF_PORT_INDICATOR: 2487 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2488 "%d\n", index)); 2489 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2490 break; 2491 default: 2492 err = USBD_IOERROR; 2493 goto ret; 2494 } 2495 break; 2496 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2497 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2498 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2499 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2500 break; 2501 default: 2502 err = USBD_IOERROR; 2503 goto ret; 2504 } 2505 xfer->actlen = totlen; 2506 err = USBD_NORMAL_COMPLETION; 2507 ret: 2508 mutex_enter(&sc->sc_lock); 2509 xfer->status = err; 2510 usb_transfer_complete(xfer); 2511 mutex_exit(&sc->sc_lock); 2512 return (USBD_IN_PROGRESS); 2513 } 2514 2515 Static void 2516 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2517 { 2518 int port; 2519 u_int32_t v; 2520 2521 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2522 #ifdef DIAGNOSTIC 2523 if (sc->sc_npcomp != 0) { 2524 int i = (index-1) / sc->sc_npcomp; 2525 if (i >= sc->sc_ncomp) 2526 printf("%s: strange port\n", 2527 device_xname(sc->sc_dev)); 2528 else 2529 printf("%s: handing over %s speed device on " 2530 "port %d to %s\n", 2531 device_xname(sc->sc_dev), 2532 lowspeed ? "low" : "full", 2533 index, device_xname(sc->sc_comps[i])); 2534 } else { 2535 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2536 } 2537 #endif 2538 port = EHCI_PORTSC(index); 2539 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2540 EOWRITE4(sc, port, v | EHCI_PS_PO); 2541 } 2542 2543 /* Abort a root control request. */ 2544 Static void 2545 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2546 { 2547 /* Nothing to do, all transfers are synchronous. */ 2548 } 2549 2550 /* Close the root pipe. */ 2551 Static void 2552 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2553 { 2554 DPRINTF(("ehci_root_ctrl_close\n")); 2555 /* Nothing to do. */ 2556 } 2557 2558 Static void 2559 ehci_root_intr_done(usbd_xfer_handle xfer) 2560 { 2561 xfer->hcpriv = NULL; 2562 } 2563 2564 Static usbd_status 2565 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2566 { 2567 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2568 usbd_status err; 2569 2570 /* Insert last in queue. */ 2571 mutex_enter(&sc->sc_lock); 2572 err = usb_insert_transfer(xfer); 2573 mutex_exit(&sc->sc_lock); 2574 if (err) 2575 return (err); 2576 2577 /* Pipe isn't running, start first */ 2578 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2579 } 2580 2581 Static usbd_status 2582 ehci_root_intr_start(usbd_xfer_handle xfer) 2583 { 2584 usbd_pipe_handle pipe = xfer->pipe; 2585 ehci_softc_t *sc = pipe->device->bus->hci_private; 2586 2587 if (sc->sc_dying) 2588 return (USBD_IOERROR); 2589 2590 mutex_enter(&sc->sc_lock); 2591 sc->sc_intrxfer = xfer; 2592 mutex_exit(&sc->sc_lock); 2593 2594 return (USBD_IN_PROGRESS); 2595 } 2596 2597 /* Abort a root interrupt request. */ 2598 Static void 2599 ehci_root_intr_abort(usbd_xfer_handle xfer) 2600 { 2601 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2602 2603 KASSERT(mutex_owned(&sc->sc_lock)); 2604 if (xfer->pipe->intrxfer == xfer) { 2605 DPRINTF(("ehci_root_intr_abort: remove\n")); 2606 xfer->pipe->intrxfer = NULL; 2607 } 2608 xfer->status = USBD_CANCELLED; 2609 usb_transfer_complete(xfer); 2610 } 2611 2612 /* Close the root pipe. */ 2613 Static void 2614 ehci_root_intr_close(usbd_pipe_handle pipe) 2615 { 2616 ehci_softc_t *sc = pipe->device->bus->hci_private; 2617 2618 KASSERT(mutex_owned(&sc->sc_lock)); 2619 2620 DPRINTF(("ehci_root_intr_close\n")); 2621 2622 sc->sc_intrxfer = NULL; 2623 } 2624 2625 Static void 2626 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2627 { 2628 xfer->hcpriv = NULL; 2629 } 2630 2631 /************************/ 2632 2633 Static ehci_soft_qh_t * 2634 ehci_alloc_sqh(ehci_softc_t *sc) 2635 { 2636 ehci_soft_qh_t *sqh; 2637 usbd_status err; 2638 int i, offs; 2639 usb_dma_t dma; 2640 2641 if (sc->sc_freeqhs == NULL) { 2642 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2643 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2644 EHCI_PAGE_SIZE, &dma); 2645 #ifdef EHCI_DEBUG 2646 if (err) 2647 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2648 #endif 2649 if (err) 2650 return (NULL); 2651 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2652 offs = i * EHCI_SQH_SIZE; 2653 sqh = KERNADDR(&dma, offs); 2654 sqh->physaddr = DMAADDR(&dma, offs); 2655 sqh->dma = dma; 2656 sqh->offs = offs; 2657 sqh->next = sc->sc_freeqhs; 2658 sc->sc_freeqhs = sqh; 2659 } 2660 } 2661 sqh = sc->sc_freeqhs; 2662 sc->sc_freeqhs = sqh->next; 2663 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2664 sqh->next = NULL; 2665 return (sqh); 2666 } 2667 2668 Static void 2669 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2670 { 2671 sqh->next = sc->sc_freeqhs; 2672 sc->sc_freeqhs = sqh; 2673 } 2674 2675 Static ehci_soft_qtd_t * 2676 ehci_alloc_sqtd(ehci_softc_t *sc) 2677 { 2678 ehci_soft_qtd_t *sqtd = NULL; 2679 usbd_status err; 2680 int i, offs; 2681 usb_dma_t dma; 2682 2683 if (sc->sc_freeqtds == NULL) { 2684 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2685 2686 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2687 EHCI_PAGE_SIZE, &dma); 2688 #ifdef EHCI_DEBUG 2689 if (err) 2690 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2691 #endif 2692 if (err) 2693 goto done; 2694 2695 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2696 offs = i * EHCI_SQTD_SIZE; 2697 sqtd = KERNADDR(&dma, offs); 2698 sqtd->physaddr = DMAADDR(&dma, offs); 2699 sqtd->dma = dma; 2700 sqtd->offs = offs; 2701 2702 sqtd->nextqtd = sc->sc_freeqtds; 2703 sc->sc_freeqtds = sqtd; 2704 } 2705 } 2706 2707 sqtd = sc->sc_freeqtds; 2708 sc->sc_freeqtds = sqtd->nextqtd; 2709 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2710 sqtd->nextqtd = NULL; 2711 sqtd->xfer = NULL; 2712 2713 done: 2714 return (sqtd); 2715 } 2716 2717 Static void 2718 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2719 { 2720 2721 KASSERT(mutex_owned(&sc->sc_lock)); 2722 2723 sqtd->nextqtd = sc->sc_freeqtds; 2724 sc->sc_freeqtds = sqtd; 2725 } 2726 2727 Static usbd_status 2728 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2729 int alen, int rd, usbd_xfer_handle xfer, 2730 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2731 { 2732 ehci_soft_qtd_t *next, *cur; 2733 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2734 u_int32_t qtdstatus; 2735 int len, curlen, mps; 2736 int i, tog; 2737 usb_dma_t *dma = &xfer->dmabuf; 2738 u_int16_t flags = xfer->flags; 2739 2740 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2741 2742 len = alen; 2743 dataphys = DMAADDR(dma, 0); 2744 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2745 qtdstatus = EHCI_QTD_ACTIVE | 2746 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2747 EHCI_QTD_SET_CERR(3) 2748 /* IOC set below */ 2749 /* BYTES set below */ 2750 ; 2751 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2752 tog = epipe->nexttoggle; 2753 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2754 2755 cur = ehci_alloc_sqtd(sc); 2756 *sp = cur; 2757 if (cur == NULL) 2758 goto nomem; 2759 2760 usb_syncmem(dma, 0, alen, 2761 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2762 for (;;) { 2763 dataphyspage = EHCI_PAGE(dataphys); 2764 /* The EHCI hardware can handle at most 5 pages. */ 2765 if (dataphyslastpage - dataphyspage < 2766 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2767 /* we can handle it in this QTD */ 2768 curlen = len; 2769 } else { 2770 /* must use multiple TDs, fill as much as possible. */ 2771 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2772 EHCI_PAGE_OFFSET(dataphys); 2773 #ifdef DIAGNOSTIC 2774 if (curlen > len) { 2775 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2776 "len=0x%x offs=0x%x\n", curlen, len, 2777 EHCI_PAGE_OFFSET(dataphys)); 2778 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2779 dataphyslastpage, dataphyspage, 2780 dataphys); 2781 curlen = len; 2782 } 2783 #endif 2784 /* the length must be a multiple of the max size */ 2785 curlen -= curlen % mps; 2786 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2787 "curlen=%d\n", curlen)); 2788 #ifdef DIAGNOSTIC 2789 if (curlen == 0) 2790 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2791 #endif 2792 } 2793 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2794 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2795 dataphys, dataphyslastpage, 2796 len, curlen)); 2797 len -= curlen; 2798 2799 /* 2800 * Allocate another transfer if there's more data left, 2801 * or if force last short transfer flag is set and we're 2802 * allocating a multiple of the max packet size. 2803 */ 2804 if (len != 0 || 2805 ((curlen % mps) == 0 && !rd && curlen != 0 && 2806 (flags & USBD_FORCE_SHORT_XFER))) { 2807 next = ehci_alloc_sqtd(sc); 2808 if (next == NULL) 2809 goto nomem; 2810 nextphys = htole32(next->physaddr); 2811 } else { 2812 next = NULL; 2813 nextphys = EHCI_NULL; 2814 } 2815 2816 for (i = 0; i * EHCI_PAGE_SIZE < 2817 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2818 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2819 if (i != 0) /* use offset only in first buffer */ 2820 a = EHCI_PAGE(a); 2821 cur->qtd.qtd_buffer[i] = htole32(a); 2822 cur->qtd.qtd_buffer_hi[i] = 0; 2823 #ifdef DIAGNOSTIC 2824 if (i >= EHCI_QTD_NBUFFERS) { 2825 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2826 goto nomem; 2827 } 2828 #endif 2829 } 2830 cur->nextqtd = next; 2831 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2832 cur->qtd.qtd_status = 2833 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2834 cur->xfer = xfer; 2835 cur->len = curlen; 2836 2837 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2838 dataphys, dataphys + curlen)); 2839 /* adjust the toggle based on the number of packets in this 2840 qtd */ 2841 if (((curlen + mps - 1) / mps) & 1) { 2842 tog ^= 1; 2843 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2844 } 2845 if (next == NULL) 2846 break; 2847 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2848 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2849 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2850 if (len) 2851 dataphys += curlen; 2852 cur = next; 2853 } 2854 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2855 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2856 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2857 *ep = cur; 2858 epipe->nexttoggle = tog; 2859 2860 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2861 *sp, *ep)); 2862 2863 return (USBD_NORMAL_COMPLETION); 2864 2865 nomem: 2866 /* XXX free chain */ 2867 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2868 return (USBD_NOMEM); 2869 } 2870 2871 Static void 2872 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2873 ehci_soft_qtd_t *sqtdend) 2874 { 2875 ehci_soft_qtd_t *p; 2876 int i; 2877 2878 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2879 sqtd, sqtdend)); 2880 2881 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2882 p = sqtd->nextqtd; 2883 ehci_free_sqtd(sc, sqtd); 2884 } 2885 } 2886 2887 Static ehci_soft_itd_t * 2888 ehci_alloc_itd(ehci_softc_t *sc) 2889 { 2890 struct ehci_soft_itd *itd, *freeitd; 2891 usbd_status err; 2892 int i, s, offs, frindex, previndex; 2893 usb_dma_t dma; 2894 2895 KASSERT(mutex_owned(&sc->sc_lock)); 2896 2897 /* Find an itd that wasn't freed this frame or last frame. This can 2898 * discard itds that were freed before frindex wrapped around 2899 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2900 * interrupt and fiddling with list when that happens */ 2901 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2902 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2903 2904 freeitd = NULL; 2905 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2906 if (itd == NULL) 2907 break; 2908 if (itd->slot != frindex && itd->slot != previndex) { 2909 freeitd = itd; 2910 break; 2911 } 2912 } 2913 2914 if (freeitd == NULL) { 2915 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2916 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2917 EHCI_PAGE_SIZE, &dma); 2918 2919 if (err) { 2920 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2921 return NULL; 2922 } 2923 2924 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2925 offs = i * EHCI_ITD_SIZE; 2926 itd = KERNADDR(&dma, offs); 2927 itd->physaddr = DMAADDR(&dma, offs); 2928 itd->dma = dma; 2929 itd->offs = offs; 2930 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2931 } 2932 freeitd = LIST_FIRST(&sc->sc_freeitds); 2933 } 2934 2935 itd = freeitd; 2936 LIST_REMOVE(itd, u.free_list); 2937 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2938 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2939 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2940 BUS_DMASYNC_PREREAD); 2941 2942 itd->u.frame_list.next = NULL; 2943 itd->u.frame_list.prev = NULL; 2944 itd->xfer_next = NULL; 2945 itd->slot = 0; 2946 splx(s); 2947 2948 return itd; 2949 } 2950 2951 Static void 2952 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2953 { 2954 2955 KASSERT(mutex_owned(&sc->sc_lock)); 2956 2957 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2958 } 2959 2960 /****************/ 2961 2962 /* 2963 * Close a reqular pipe. 2964 * Assumes that there are no pending transactions. 2965 */ 2966 Static void 2967 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2968 { 2969 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2970 ehci_softc_t *sc = pipe->device->bus->hci_private; 2971 ehci_soft_qh_t *sqh = epipe->sqh; 2972 2973 KASSERT(mutex_owned(&sc->sc_lock)); 2974 2975 ehci_rem_qh(sc, sqh, head); 2976 ehci_free_sqh(sc, epipe->sqh); 2977 } 2978 2979 /* 2980 * Abort a device request. 2981 * If this routine is called at splusb() it guarantees that the request 2982 * will be removed from the hardware scheduling and that the callback 2983 * for it will be called with USBD_CANCELLED status. 2984 * It's impossible to guarantee that the requested transfer will not 2985 * have happened since the hardware runs concurrently. 2986 * If the transaction has already happened we rely on the ordinary 2987 * interrupt processing to process it. 2988 * XXX This is most probably wrong. 2989 */ 2990 Static void 2991 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2992 { 2993 #define exfer EXFER(xfer) 2994 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2995 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2996 ehci_soft_qh_t *sqh = epipe->sqh; 2997 ehci_soft_qtd_t *sqtd; 2998 ehci_physaddr_t cur; 2999 u_int32_t qhstatus; 3000 int hit; 3001 int wake; 3002 3003 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 3004 3005 KASSERT(mutex_owned(&sc->sc_lock)); 3006 3007 if (sc->sc_dying) { 3008 /* If we're dying, just do the software part. */ 3009 xfer->status = status; /* make software ignore it */ 3010 callout_stop(&xfer->timeout_handle); 3011 usb_transfer_complete(xfer); 3012 return; 3013 } 3014 3015 if (xfer->device->bus->intr_context) 3016 panic("ehci_abort_xfer: not in process context"); 3017 3018 /* 3019 * If an abort is already in progress then just wait for it to 3020 * complete and return. 3021 */ 3022 if (xfer->hcflags & UXFER_ABORTING) { 3023 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3024 #ifdef DIAGNOSTIC 3025 if (status == USBD_TIMEOUT) 3026 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3027 #endif 3028 /* Override the status which might be USBD_TIMEOUT. */ 3029 xfer->status = status; 3030 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3031 xfer->hcflags |= UXFER_ABORTWAIT; 3032 while (xfer->hcflags & UXFER_ABORTING) 3033 cv_wait(&xfer->hccv, &sc->sc_lock); 3034 return; 3035 } 3036 xfer->hcflags |= UXFER_ABORTING; 3037 3038 /* 3039 * Step 1: Make interrupt routine and hardware ignore xfer. 3040 */ 3041 xfer->status = status; /* make software ignore it */ 3042 callout_stop(&xfer->timeout_handle); 3043 3044 usb_syncmem(&sqh->dma, 3045 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3046 sizeof(sqh->qh.qh_qtd.qtd_status), 3047 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3048 qhstatus = sqh->qh.qh_qtd.qtd_status; 3049 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3050 usb_syncmem(&sqh->dma, 3051 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3052 sizeof(sqh->qh.qh_qtd.qtd_status), 3053 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3054 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3055 usb_syncmem(&sqtd->dma, 3056 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3057 sizeof(sqtd->qtd.qtd_status), 3058 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3059 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3060 usb_syncmem(&sqtd->dma, 3061 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3062 sizeof(sqtd->qtd.qtd_status), 3063 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3064 if (sqtd == exfer->sqtdend) 3065 break; 3066 } 3067 3068 /* 3069 * Step 2: Wait until we know hardware has finished any possible 3070 * use of the xfer. Also make sure the soft interrupt routine 3071 * has run. 3072 */ 3073 ehci_sync_hc(sc); 3074 sc->sc_softwake = 1; 3075 usb_schedsoftintr(&sc->sc_bus); 3076 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3077 3078 /* 3079 * Step 3: Remove any vestiges of the xfer from the hardware. 3080 * The complication here is that the hardware may have executed 3081 * beyond the xfer we're trying to abort. So as we're scanning 3082 * the TDs of this xfer we check if the hardware points to 3083 * any of them. 3084 */ 3085 3086 usb_syncmem(&sqh->dma, 3087 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3088 sizeof(sqh->qh.qh_curqtd), 3089 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3090 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3091 hit = 0; 3092 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3093 hit |= cur == sqtd->physaddr; 3094 if (sqtd == exfer->sqtdend) 3095 break; 3096 } 3097 sqtd = sqtd->nextqtd; 3098 /* Zap curqtd register if hardware pointed inside the xfer. */ 3099 if (hit && sqtd != NULL) { 3100 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3101 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3102 usb_syncmem(&sqh->dma, 3103 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3104 sizeof(sqh->qh.qh_curqtd), 3105 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3106 sqh->qh.qh_qtd.qtd_status = qhstatus; 3107 usb_syncmem(&sqh->dma, 3108 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3109 sizeof(sqh->qh.qh_qtd.qtd_status), 3110 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3111 } else { 3112 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3113 } 3114 3115 /* 3116 * Step 4: Execute callback. 3117 */ 3118 #ifdef DIAGNOSTIC 3119 exfer->isdone = 1; 3120 #endif 3121 wake = xfer->hcflags & UXFER_ABORTWAIT; 3122 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3123 usb_transfer_complete(xfer); 3124 if (wake) { 3125 cv_broadcast(&xfer->hccv); 3126 } 3127 3128 KASSERT(mutex_owned(&sc->sc_lock)); 3129 #undef exfer 3130 } 3131 3132 Static void 3133 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3134 { 3135 ehci_isoc_trans_t trans_status; 3136 struct ehci_pipe *epipe; 3137 struct ehci_xfer *exfer; 3138 ehci_softc_t *sc; 3139 struct ehci_soft_itd *itd; 3140 int i, wake; 3141 3142 epipe = (struct ehci_pipe *) xfer->pipe; 3143 exfer = EXFER(xfer); 3144 sc = epipe->pipe.device->bus->hci_private; 3145 3146 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3147 3148 KASSERT(mutex_owned(&sc->sc_lock)); 3149 3150 if (sc->sc_dying) { 3151 xfer->status = status; 3152 callout_stop(&xfer->timeout_handle); 3153 usb_transfer_complete(xfer); 3154 return; 3155 } 3156 3157 if (xfer->hcflags & UXFER_ABORTING) { 3158 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3159 3160 #ifdef DIAGNOSTIC 3161 if (status == USBD_TIMEOUT) 3162 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3163 #endif 3164 3165 xfer->status = status; 3166 DPRINTFN(2, ("ehci_abort_isoc_xfer: waiting for abort to finish\n")); 3167 xfer->hcflags |= UXFER_ABORTWAIT; 3168 while (xfer->hcflags & UXFER_ABORTING) 3169 cv_wait(&xfer->hccv, &sc->sc_lock); 3170 goto done; 3171 } 3172 xfer->hcflags |= UXFER_ABORTING; 3173 3174 xfer->status = status; 3175 callout_stop(&xfer->timeout_handle); 3176 3177 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3178 usb_syncmem(&itd->dma, 3179 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3180 sizeof(itd->itd.itd_ctl), 3181 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3182 3183 for (i = 0; i < 8; i++) { 3184 trans_status = le32toh(itd->itd.itd_ctl[i]); 3185 trans_status &= ~EHCI_ITD_ACTIVE; 3186 itd->itd.itd_ctl[i] = htole32(trans_status); 3187 } 3188 3189 usb_syncmem(&itd->dma, 3190 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3191 sizeof(itd->itd.itd_ctl), 3192 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3193 } 3194 3195 sc->sc_softwake = 1; 3196 usb_schedsoftintr(&sc->sc_bus); 3197 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3198 3199 #ifdef DIAGNOSTIC 3200 exfer->isdone = 1; 3201 #endif 3202 wake = xfer->hcflags & UXFER_ABORTWAIT; 3203 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3204 usb_transfer_complete(xfer); 3205 if (wake) { 3206 cv_broadcast(&xfer->hccv); 3207 } 3208 3209 done: 3210 KASSERT(mutex_owned(&sc->sc_lock)); 3211 return; 3212 } 3213 3214 Static void 3215 ehci_timeout(void *addr) 3216 { 3217 struct ehci_xfer *exfer = addr; 3218 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3219 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3220 3221 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3222 #ifdef EHCI_DEBUG 3223 if (ehcidebug > 1) 3224 usbd_dump_pipe(exfer->xfer.pipe); 3225 #endif 3226 3227 if (sc->sc_dying) { 3228 mutex_enter(&sc->sc_lock); 3229 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3230 mutex_exit(&sc->sc_lock); 3231 return; 3232 } 3233 3234 /* Execute the abort in a process context. */ 3235 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3236 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3237 USB_TASKQ_HC); 3238 } 3239 3240 Static void 3241 ehci_timeout_task(void *addr) 3242 { 3243 usbd_xfer_handle xfer = addr; 3244 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3245 3246 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3247 3248 mutex_enter(&sc->sc_lock); 3249 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3250 mutex_exit(&sc->sc_lock); 3251 } 3252 3253 /************************/ 3254 3255 Static usbd_status 3256 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3257 { 3258 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3259 usbd_status err; 3260 3261 /* Insert last in queue. */ 3262 mutex_enter(&sc->sc_lock); 3263 err = usb_insert_transfer(xfer); 3264 mutex_exit(&sc->sc_lock); 3265 if (err) 3266 return (err); 3267 3268 /* Pipe isn't running, start first */ 3269 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3270 } 3271 3272 Static usbd_status 3273 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3274 { 3275 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3276 usbd_status err; 3277 3278 if (sc->sc_dying) 3279 return (USBD_IOERROR); 3280 3281 #ifdef DIAGNOSTIC 3282 if (!(xfer->rqflags & URQ_REQUEST)) { 3283 /* XXX panic */ 3284 printf("ehci_device_ctrl_transfer: not a request\n"); 3285 return (USBD_INVAL); 3286 } 3287 #endif 3288 3289 err = ehci_device_request(xfer); 3290 if (err) { 3291 return (err); 3292 } 3293 3294 if (sc->sc_bus.use_polling) 3295 ehci_waitintr(sc, xfer); 3296 3297 return (USBD_IN_PROGRESS); 3298 } 3299 3300 Static void 3301 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3302 { 3303 struct ehci_xfer *ex = EXFER(xfer); 3304 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3305 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3306 usb_device_request_t *req = &xfer->request; 3307 int len = UGETW(req->wLength); 3308 int rd = req->bmRequestType & UT_READ; 3309 3310 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3311 3312 KASSERT(mutex_owned(&sc->sc_lock)); 3313 3314 #ifdef DIAGNOSTIC 3315 if (!(xfer->rqflags & URQ_REQUEST)) { 3316 panic("ehci_ctrl_done: not a request"); 3317 } 3318 #endif 3319 3320 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3321 ehci_del_intr_list(sc, ex); /* remove from active list */ 3322 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3323 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3324 BUS_DMASYNC_POSTWRITE); 3325 if (len) 3326 usb_syncmem(&xfer->dmabuf, 0, len, 3327 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3328 } 3329 3330 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3331 } 3332 3333 /* Abort a device control request. */ 3334 Static void 3335 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3336 { 3337 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3338 ehci_abort_xfer(xfer, USBD_CANCELLED); 3339 } 3340 3341 /* Close a device control pipe. */ 3342 Static void 3343 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3344 { 3345 ehci_softc_t *sc = pipe->device->bus->hci_private; 3346 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3347 3348 KASSERT(mutex_owned(&sc->sc_lock)); 3349 3350 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3351 3352 ehci_close_pipe(pipe, sc->sc_async_head); 3353 } 3354 3355 Static usbd_status 3356 ehci_device_request(usbd_xfer_handle xfer) 3357 { 3358 #define exfer EXFER(xfer) 3359 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3360 usb_device_request_t *req = &xfer->request; 3361 usbd_device_handle dev = epipe->pipe.device; 3362 ehci_softc_t *sc = dev->bus->hci_private; 3363 int addr = dev->address; 3364 ehci_soft_qtd_t *setup, *stat, *next; 3365 ehci_soft_qh_t *sqh; 3366 int isread; 3367 int len; 3368 usbd_status err; 3369 3370 isread = req->bmRequestType & UT_READ; 3371 len = UGETW(req->wLength); 3372 3373 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3374 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3375 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3376 UGETW(req->wIndex), len, addr, 3377 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3378 3379 setup = ehci_alloc_sqtd(sc); 3380 if (setup == NULL) { 3381 err = USBD_NOMEM; 3382 goto bad1; 3383 } 3384 stat = ehci_alloc_sqtd(sc); 3385 if (stat == NULL) { 3386 err = USBD_NOMEM; 3387 goto bad2; 3388 } 3389 3390 mutex_enter(&sc->sc_lock); 3391 3392 sqh = epipe->sqh; 3393 epipe->u.ctl.length = len; 3394 3395 /* Update device address and length since they may have changed 3396 during the setup of the control pipe in usbd_new_device(). */ 3397 /* XXX This only needs to be done once, but it's too early in open. */ 3398 /* XXXX Should not touch ED here! */ 3399 sqh->qh.qh_endp = 3400 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3401 htole32( 3402 EHCI_QH_SET_ADDR(addr) | 3403 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3404 ); 3405 3406 /* Set up data transaction */ 3407 if (len != 0) { 3408 ehci_soft_qtd_t *end; 3409 3410 /* Start toggle at 1. */ 3411 epipe->nexttoggle = 1; 3412 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3413 &next, &end); 3414 if (err) 3415 goto bad3; 3416 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3417 end->nextqtd = stat; 3418 end->qtd.qtd_next = 3419 end->qtd.qtd_altnext = htole32(stat->physaddr); 3420 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3421 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3422 } else { 3423 next = stat; 3424 } 3425 3426 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3427 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3428 3429 /* Clear toggle */ 3430 setup->qtd.qtd_status = htole32( 3431 EHCI_QTD_ACTIVE | 3432 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3433 EHCI_QTD_SET_CERR(3) | 3434 EHCI_QTD_SET_TOGGLE(0) | 3435 EHCI_QTD_SET_BYTES(sizeof *req) 3436 ); 3437 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3438 setup->qtd.qtd_buffer_hi[0] = 0; 3439 setup->nextqtd = next; 3440 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3441 setup->xfer = xfer; 3442 setup->len = sizeof *req; 3443 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3444 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3445 3446 stat->qtd.qtd_status = htole32( 3447 EHCI_QTD_ACTIVE | 3448 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3449 EHCI_QTD_SET_CERR(3) | 3450 EHCI_QTD_SET_TOGGLE(1) | 3451 EHCI_QTD_IOC 3452 ); 3453 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3454 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3455 stat->nextqtd = NULL; 3456 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3457 stat->xfer = xfer; 3458 stat->len = 0; 3459 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3460 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3461 3462 #ifdef EHCI_DEBUG 3463 if (ehcidebug > 5) { 3464 DPRINTF(("ehci_device_request:\n")); 3465 ehci_dump_sqh(sqh); 3466 ehci_dump_sqtds(setup); 3467 } 3468 #endif 3469 3470 exfer->sqtdstart = setup; 3471 exfer->sqtdend = stat; 3472 #ifdef DIAGNOSTIC 3473 if (!exfer->isdone) { 3474 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3475 } 3476 exfer->isdone = 0; 3477 #endif 3478 3479 /* Insert qTD in QH list. */ 3480 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3481 if (xfer->timeout && !sc->sc_bus.use_polling) { 3482 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3483 (ehci_timeout), (xfer)); 3484 } 3485 ehci_add_intr_list(sc, exfer); 3486 xfer->status = USBD_IN_PROGRESS; 3487 mutex_exit(&sc->sc_lock); 3488 3489 #ifdef EHCI_DEBUG 3490 if (ehcidebug > 10) { 3491 DPRINTF(("ehci_device_request: status=%x\n", 3492 EOREAD4(sc, EHCI_USBSTS))); 3493 delay(10000); 3494 ehci_dump_regs(sc); 3495 ehci_dump_sqh(sc->sc_async_head); 3496 ehci_dump_sqh(sqh); 3497 ehci_dump_sqtds(setup); 3498 } 3499 #endif 3500 3501 return (USBD_NORMAL_COMPLETION); 3502 3503 bad3: 3504 mutex_exit(&sc->sc_lock); 3505 ehci_free_sqtd(sc, stat); 3506 bad2: 3507 ehci_free_sqtd(sc, setup); 3508 bad1: 3509 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3510 mutex_enter(&sc->sc_lock); 3511 xfer->status = err; 3512 usb_transfer_complete(xfer); 3513 mutex_exit(&sc->sc_lock); 3514 return (err); 3515 #undef exfer 3516 } 3517 3518 /* 3519 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3520 * qTD status, or miss signalling occasionally under heavy load. If the host 3521 * machine is too fast, we we can miss transaction completion - when we scan 3522 * the active list the transaction still seems to be active. This generally 3523 * exhibits itself as a umass stall that never recovers. 3524 * 3525 * We work around this behaviour by setting up this callback after any softintr 3526 * that completes with transactions still pending, giving us another chance to 3527 * check for completion after the writeback has taken place. 3528 */ 3529 Static void 3530 ehci_intrlist_timeout(void *arg) 3531 { 3532 ehci_softc_t *sc = arg; 3533 3534 DPRINTF(("ehci_intrlist_timeout\n")); 3535 usb_schedsoftintr(&sc->sc_bus); 3536 } 3537 3538 /************************/ 3539 3540 Static usbd_status 3541 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3542 { 3543 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3544 usbd_status err; 3545 3546 /* Insert last in queue. */ 3547 mutex_enter(&sc->sc_lock); 3548 err = usb_insert_transfer(xfer); 3549 mutex_exit(&sc->sc_lock); 3550 if (err) 3551 return (err); 3552 3553 /* Pipe isn't running, start first */ 3554 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3555 } 3556 3557 Static usbd_status 3558 ehci_device_bulk_start(usbd_xfer_handle xfer) 3559 { 3560 #define exfer EXFER(xfer) 3561 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3562 usbd_device_handle dev = epipe->pipe.device; 3563 ehci_softc_t *sc = dev->bus->hci_private; 3564 ehci_soft_qtd_t *data, *dataend; 3565 ehci_soft_qh_t *sqh; 3566 usbd_status err; 3567 int len, isread, endpt; 3568 3569 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3570 xfer, xfer->length, xfer->flags)); 3571 3572 if (sc->sc_dying) 3573 return (USBD_IOERROR); 3574 3575 #ifdef DIAGNOSTIC 3576 if (xfer->rqflags & URQ_REQUEST) 3577 panic("ehci_device_bulk_start: a request"); 3578 #endif 3579 3580 len = xfer->length; 3581 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3582 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3583 sqh = epipe->sqh; 3584 3585 epipe->u.bulk.length = len; 3586 3587 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3588 &dataend); 3589 if (err) { 3590 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3591 xfer->status = err; 3592 usb_transfer_complete(xfer); 3593 return (err); 3594 } 3595 3596 #ifdef EHCI_DEBUG 3597 if (ehcidebug > 5) { 3598 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3599 ehci_dump_sqh(sqh); 3600 ehci_dump_sqtds(data); 3601 } 3602 #endif 3603 3604 /* Set up interrupt info. */ 3605 exfer->sqtdstart = data; 3606 exfer->sqtdend = dataend; 3607 #ifdef DIAGNOSTIC 3608 if (!exfer->isdone) { 3609 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3610 } 3611 exfer->isdone = 0; 3612 #endif 3613 3614 mutex_enter(&sc->sc_lock); 3615 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3616 if (xfer->timeout && !sc->sc_bus.use_polling) { 3617 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3618 (ehci_timeout), (xfer)); 3619 } 3620 ehci_add_intr_list(sc, exfer); 3621 xfer->status = USBD_IN_PROGRESS; 3622 mutex_exit(&sc->sc_lock); 3623 3624 #ifdef EHCI_DEBUG 3625 if (ehcidebug > 10) { 3626 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3627 delay(10000); 3628 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3629 ehci_dump_regs(sc); 3630 #if 0 3631 printf("async_head:\n"); 3632 ehci_dump_sqh(sc->sc_async_head); 3633 #endif 3634 printf("sqh:\n"); 3635 ehci_dump_sqh(sqh); 3636 ehci_dump_sqtds(data); 3637 } 3638 #endif 3639 3640 if (sc->sc_bus.use_polling) 3641 ehci_waitintr(sc, xfer); 3642 3643 return (USBD_IN_PROGRESS); 3644 #undef exfer 3645 } 3646 3647 Static void 3648 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3649 { 3650 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3651 ehci_abort_xfer(xfer, USBD_CANCELLED); 3652 } 3653 3654 /* 3655 * Close a device bulk pipe. 3656 */ 3657 Static void 3658 ehci_device_bulk_close(usbd_pipe_handle pipe) 3659 { 3660 ehci_softc_t *sc = pipe->device->bus->hci_private; 3661 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3662 3663 KASSERT(mutex_owned(&sc->sc_lock)); 3664 3665 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3666 pipe->endpoint->datatoggle = epipe->nexttoggle; 3667 ehci_close_pipe(pipe, sc->sc_async_head); 3668 } 3669 3670 Static void 3671 ehci_device_bulk_done(usbd_xfer_handle xfer) 3672 { 3673 struct ehci_xfer *ex = EXFER(xfer); 3674 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3675 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3676 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3677 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3678 3679 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3680 xfer, xfer->actlen)); 3681 3682 KASSERT(mutex_owned(&sc->sc_lock)); 3683 3684 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3685 ehci_del_intr_list(sc, ex); /* remove from active list */ 3686 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3687 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3688 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3689 } 3690 3691 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3692 } 3693 3694 /************************/ 3695 3696 Static usbd_status 3697 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3698 { 3699 struct ehci_soft_islot *isp; 3700 int islot, lev; 3701 3702 /* Find a poll rate that is large enough. */ 3703 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3704 if (EHCI_ILEV_IVAL(lev) <= ival) 3705 break; 3706 3707 /* Pick an interrupt slot at the right level. */ 3708 /* XXX could do better than picking at random */ 3709 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3710 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3711 3712 sqh->islot = islot; 3713 isp = &sc->sc_islots[islot]; 3714 mutex_enter(&sc->sc_lock); 3715 ehci_add_qh(sc, sqh, isp->sqh); 3716 mutex_exit(&sc->sc_lock); 3717 3718 return (USBD_NORMAL_COMPLETION); 3719 } 3720 3721 Static usbd_status 3722 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3723 { 3724 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3725 usbd_status err; 3726 3727 /* Insert last in queue. */ 3728 mutex_enter(&sc->sc_lock); 3729 err = usb_insert_transfer(xfer); 3730 mutex_exit(&sc->sc_lock); 3731 if (err) 3732 return (err); 3733 3734 /* 3735 * Pipe isn't running (otherwise err would be USBD_INPROG), 3736 * so start it first. 3737 */ 3738 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3739 } 3740 3741 Static usbd_status 3742 ehci_device_intr_start(usbd_xfer_handle xfer) 3743 { 3744 #define exfer EXFER(xfer) 3745 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3746 usbd_device_handle dev = xfer->pipe->device; 3747 ehci_softc_t *sc = dev->bus->hci_private; 3748 ehci_soft_qtd_t *data, *dataend; 3749 ehci_soft_qh_t *sqh; 3750 usbd_status err; 3751 int len, isread, endpt; 3752 3753 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3754 xfer, xfer->length, xfer->flags)); 3755 3756 if (sc->sc_dying) 3757 return (USBD_IOERROR); 3758 3759 #ifdef DIAGNOSTIC 3760 if (xfer->rqflags & URQ_REQUEST) 3761 panic("ehci_device_intr_start: a request"); 3762 #endif 3763 3764 len = xfer->length; 3765 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3766 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3767 sqh = epipe->sqh; 3768 3769 epipe->u.intr.length = len; 3770 3771 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3772 &dataend); 3773 if (err) { 3774 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3775 xfer->status = err; 3776 usb_transfer_complete(xfer); 3777 return (err); 3778 } 3779 3780 #ifdef EHCI_DEBUG 3781 if (ehcidebug > 5) { 3782 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3783 ehci_dump_sqh(sqh); 3784 ehci_dump_sqtds(data); 3785 } 3786 #endif 3787 3788 /* Set up interrupt info. */ 3789 exfer->sqtdstart = data; 3790 exfer->sqtdend = dataend; 3791 #ifdef DIAGNOSTIC 3792 if (!exfer->isdone) { 3793 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3794 } 3795 exfer->isdone = 0; 3796 #endif 3797 3798 mutex_enter(&sc->sc_lock); 3799 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3800 if (xfer->timeout && !sc->sc_bus.use_polling) { 3801 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3802 (ehci_timeout), (xfer)); 3803 } 3804 ehci_add_intr_list(sc, exfer); 3805 xfer->status = USBD_IN_PROGRESS; 3806 mutex_exit(&sc->sc_lock); 3807 3808 #ifdef EHCI_DEBUG 3809 if (ehcidebug > 10) { 3810 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3811 delay(10000); 3812 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3813 ehci_dump_regs(sc); 3814 printf("sqh:\n"); 3815 ehci_dump_sqh(sqh); 3816 ehci_dump_sqtds(data); 3817 } 3818 #endif 3819 3820 if (sc->sc_bus.use_polling) 3821 ehci_waitintr(sc, xfer); 3822 3823 return (USBD_IN_PROGRESS); 3824 #undef exfer 3825 } 3826 3827 Static void 3828 ehci_device_intr_abort(usbd_xfer_handle xfer) 3829 { 3830 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3831 if (xfer->pipe->intrxfer == xfer) { 3832 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3833 xfer->pipe->intrxfer = NULL; 3834 } 3835 /* 3836 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3837 * async doorbell. That's dependent on the async list, wheras 3838 * intr xfers are periodic, should not use this? 3839 */ 3840 ehci_abort_xfer(xfer, USBD_CANCELLED); 3841 } 3842 3843 Static void 3844 ehci_device_intr_close(usbd_pipe_handle pipe) 3845 { 3846 ehci_softc_t *sc = pipe->device->bus->hci_private; 3847 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3848 struct ehci_soft_islot *isp; 3849 3850 KASSERT(mutex_owned(&sc->sc_lock)); 3851 3852 isp = &sc->sc_islots[epipe->sqh->islot]; 3853 ehci_close_pipe(pipe, isp->sqh); 3854 } 3855 3856 Static void 3857 ehci_device_intr_done(usbd_xfer_handle xfer) 3858 { 3859 #define exfer EXFER(xfer) 3860 struct ehci_xfer *ex = EXFER(xfer); 3861 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3862 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3863 ehci_soft_qtd_t *data, *dataend; 3864 ehci_soft_qh_t *sqh; 3865 usbd_status err; 3866 int len, isread, endpt; 3867 3868 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3869 xfer, xfer->actlen)); 3870 3871 KASSERT(mutex_owned(&sc->sc_lock)); 3872 3873 if (xfer->pipe->repeat) { 3874 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3875 3876 len = epipe->u.intr.length; 3877 xfer->length = len; 3878 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3879 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3880 usb_syncmem(&xfer->dmabuf, 0, len, 3881 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3882 sqh = epipe->sqh; 3883 3884 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3885 &data, &dataend); 3886 if (err) { 3887 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3888 xfer->status = err; 3889 return; 3890 } 3891 3892 /* Set up interrupt info. */ 3893 exfer->sqtdstart = data; 3894 exfer->sqtdend = dataend; 3895 #ifdef DIAGNOSTIC 3896 if (!exfer->isdone) { 3897 printf("ehci_device_intr_done: not done, ex=%p\n", 3898 exfer); 3899 } 3900 exfer->isdone = 0; 3901 #endif 3902 3903 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3904 if (xfer->timeout && !sc->sc_bus.use_polling) { 3905 callout_reset(&(xfer->timeout_handle), 3906 (mstohz(xfer->timeout)), (ehci_timeout), (xfer)); 3907 } 3908 3909 xfer->status = USBD_IN_PROGRESS; 3910 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3911 ehci_del_intr_list(sc, ex); /* remove from active list */ 3912 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3913 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3914 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3915 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3916 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3917 } 3918 #undef exfer 3919 } 3920 3921 /************************/ 3922 3923 Static usbd_status 3924 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3925 { 3926 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3927 usbd_status err; 3928 3929 mutex_enter(&sc->sc_lock); 3930 err = usb_insert_transfer(xfer); 3931 mutex_exit(&sc->sc_lock); 3932 if (err && err != USBD_IN_PROGRESS) 3933 return err; 3934 3935 return ehci_device_isoc_start(xfer); 3936 } 3937 3938 Static usbd_status 3939 ehci_device_isoc_start(usbd_xfer_handle xfer) 3940 { 3941 struct ehci_pipe *epipe; 3942 usbd_device_handle dev; 3943 ehci_softc_t *sc; 3944 struct ehci_xfer *exfer; 3945 ehci_soft_itd_t *itd, *prev, *start, *stop; 3946 usb_dma_t *dma_buf; 3947 int i, j, k, frames, uframes, ufrperframe; 3948 int trans_count, offs, total_length; 3949 int frindex; 3950 3951 start = NULL; 3952 prev = NULL; 3953 itd = NULL; 3954 trans_count = 0; 3955 total_length = 0; 3956 exfer = (struct ehci_xfer *) xfer; 3957 sc = xfer->pipe->device->bus->hci_private; 3958 dev = xfer->pipe->device; 3959 epipe = (struct ehci_pipe *)xfer->pipe; 3960 3961 /* 3962 * To allow continuous transfers, above we start all transfers 3963 * immediately. However, we're still going to get usbd_start_next call 3964 * this when another xfer completes. So, check if this is already 3965 * in progress or not 3966 */ 3967 3968 if (exfer->itdstart != NULL) 3969 return USBD_IN_PROGRESS; 3970 3971 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3972 xfer, xfer->length, xfer->flags)); 3973 3974 if (sc->sc_dying) 3975 return USBD_IOERROR; 3976 3977 /* 3978 * To avoid complication, don't allow a request right now that'll span 3979 * the entire frame table. To within 4 frames, to allow some leeway 3980 * on either side of where the hc currently is. 3981 */ 3982 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3983 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3984 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3985 return USBD_INVAL; 3986 } 3987 3988 #ifdef DIAGNOSTIC 3989 if (xfer->rqflags & URQ_REQUEST) 3990 panic("ehci_device_isoc_start: request\n"); 3991 3992 if (!exfer->isdone) 3993 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3994 exfer->isdone = 0; 3995 #endif 3996 3997 /* 3998 * Step 1: Allocate and initialize itds, how many do we need? 3999 * One per transfer if interval >= 8 microframes, fewer if we use 4000 * multiple microframes per frame. 4001 */ 4002 4003 i = epipe->pipe.endpoint->edesc->bInterval; 4004 if (i > 16 || i == 0) { 4005 /* Spec page 271 says intervals > 16 are invalid */ 4006 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 4007 return USBD_INVAL; 4008 } 4009 4010 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4011 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4012 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4013 4014 if (frames == 0) { 4015 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 4016 return USBD_INVAL; 4017 } 4018 4019 dma_buf = &xfer->dmabuf; 4020 offs = 0; 4021 4022 for (i = 0; i < frames; i++) { 4023 int froffs = offs; 4024 itd = ehci_alloc_itd(sc); 4025 4026 if (prev != NULL) { 4027 prev->itd.itd_next = 4028 htole32(itd->physaddr | EHCI_LINK_ITD); 4029 usb_syncmem(&itd->dma, 4030 itd->offs + offsetof(ehci_itd_t, itd_next), 4031 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4032 4033 prev->xfer_next = itd; 4034 } else { 4035 start = itd; 4036 } 4037 4038 /* 4039 * Step 1.5, initialize uframes 4040 */ 4041 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4042 /* Calculate which page in the list this starts in */ 4043 int addr = DMAADDR(dma_buf, froffs); 4044 addr = EHCI_PAGE_OFFSET(addr); 4045 addr += (offs - froffs); 4046 addr = EHCI_PAGE(addr); 4047 addr /= EHCI_PAGE_SIZE; 4048 4049 /* This gets the initial offset into the first page, 4050 * looks how far further along the current uframe 4051 * offset is. Works out how many pages that is. 4052 */ 4053 4054 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4055 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4056 EHCI_ITD_SET_PG(addr) | 4057 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4058 4059 total_length += xfer->frlengths[trans_count]; 4060 offs += xfer->frlengths[trans_count]; 4061 trans_count++; 4062 4063 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4064 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4065 break; 4066 } 4067 } 4068 4069 /* Step 1.75, set buffer pointers. To simplify matters, all 4070 * pointers are filled out for the next 7 hardware pages in 4071 * the dma block, so no need to worry what pages to cover 4072 * and what to not. 4073 */ 4074 4075 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4076 /* 4077 * Don't try to lookup a page that's past the end 4078 * of buffer 4079 */ 4080 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4081 if (page_offs >= dma_buf->block->size) 4082 break; 4083 4084 unsigned long long page = DMAADDR(dma_buf, page_offs); 4085 page = EHCI_PAGE(page); 4086 itd->itd.itd_bufr[j] = 4087 htole32(EHCI_ITD_SET_BPTR(page)); 4088 itd->itd.itd_bufr_hi[j] = 4089 htole32(page >> 32); 4090 } 4091 4092 /* 4093 * Other special values 4094 */ 4095 4096 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4097 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4098 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4099 4100 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4101 ? 1 : 0; 4102 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4103 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4104 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4105 4106 /* FIXME: handle invalid trans */ 4107 itd->itd.itd_bufr[2] |= 4108 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4109 4110 usb_syncmem(&itd->dma, 4111 itd->offs + offsetof(ehci_itd_t, itd_next), 4112 sizeof(ehci_itd_t), 4113 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4114 4115 prev = itd; 4116 } /* End of frame */ 4117 4118 stop = itd; 4119 stop->xfer_next = NULL; 4120 exfer->isoc_len = total_length; 4121 4122 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4123 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4124 4125 /* 4126 * Part 2: Transfer descriptors have now been set up, now they must 4127 * be scheduled into the period frame list. Erk. Not wanting to 4128 * complicate matters, transfer is denied if the transfer spans 4129 * more than the period frame list. 4130 */ 4131 4132 mutex_enter(&sc->sc_lock); 4133 4134 /* Start inserting frames */ 4135 if (epipe->u.isoc.cur_xfers > 0) { 4136 frindex = epipe->u.isoc.next_frame; 4137 } else { 4138 frindex = EOREAD4(sc, EHCI_FRINDEX); 4139 frindex = frindex >> 3; /* Erase microframe index */ 4140 frindex += 2; 4141 } 4142 4143 if (frindex >= sc->sc_flsize) 4144 frindex &= (sc->sc_flsize - 1); 4145 4146 /* What's the frame interval? */ 4147 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4148 if (i / USB_UFRAMES_PER_FRAME == 0) 4149 i = 1; 4150 else 4151 i /= USB_UFRAMES_PER_FRAME; 4152 4153 itd = start; 4154 for (j = 0; j < frames; j++) { 4155 if (itd == NULL) 4156 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4157 4158 itd->itd.itd_next = sc->sc_flist[frindex]; 4159 if (itd->itd.itd_next == 0) 4160 /* FIXME: frindex table gets initialized to NULL 4161 * or EHCI_NULL? */ 4162 itd->itd.itd_next = EHCI_NULL; 4163 4164 usb_syncmem(&itd->dma, 4165 itd->offs + offsetof(ehci_itd_t, itd_next), 4166 sizeof(itd->itd.itd_next), 4167 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4168 4169 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4170 4171 usb_syncmem(&sc->sc_fldma, 4172 sizeof(ehci_link_t) * frindex, 4173 sizeof(ehci_link_t), 4174 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4175 4176 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4177 sc->sc_softitds[frindex] = itd; 4178 if (itd->u.frame_list.next != NULL) 4179 itd->u.frame_list.next->u.frame_list.prev = itd; 4180 itd->slot = frindex; 4181 itd->u.frame_list.prev = NULL; 4182 4183 frindex += i; 4184 if (frindex >= sc->sc_flsize) 4185 frindex -= sc->sc_flsize; 4186 4187 itd = itd->xfer_next; 4188 } 4189 4190 epipe->u.isoc.cur_xfers++; 4191 epipe->u.isoc.next_frame = frindex; 4192 4193 exfer->itdstart = start; 4194 exfer->itdend = stop; 4195 exfer->sqtdstart = NULL; 4196 exfer->sqtdstart = NULL; 4197 4198 ehci_add_intr_list(sc, exfer); 4199 xfer->status = USBD_IN_PROGRESS; 4200 xfer->done = 0; 4201 mutex_exit(&sc->sc_lock); 4202 4203 if (sc->sc_bus.use_polling) { 4204 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4205 ehci_waitintr(sc, xfer); 4206 } 4207 4208 return USBD_IN_PROGRESS; 4209 } 4210 4211 Static void 4212 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4213 { 4214 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4215 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4216 } 4217 4218 Static void 4219 ehci_device_isoc_close(usbd_pipe_handle pipe) 4220 { 4221 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4222 } 4223 4224 Static void 4225 ehci_device_isoc_done(usbd_xfer_handle xfer) 4226 { 4227 struct ehci_xfer *exfer; 4228 ehci_softc_t *sc; 4229 struct ehci_pipe *epipe; 4230 4231 exfer = EXFER(xfer); 4232 sc = xfer->pipe->device->bus->hci_private; 4233 epipe = (struct ehci_pipe *) xfer->pipe; 4234 4235 KASSERT(mutex_owned(&sc->sc_lock)); 4236 4237 epipe->u.isoc.cur_xfers--; 4238 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4239 ehci_del_intr_list(sc, exfer); 4240 ehci_rem_free_itd_chain(sc, exfer); 4241 } 4242 4243 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4244 BUS_DMASYNC_POSTREAD); 4245 4246 } 4247
Indexes created Thu Oct 02 01:09:59 GMT 2025