ehci.c revision 1.183.2.2
1 /* $NetBSD: ehci.c,v 1.183.2.2 2013/12/14 19:26:39 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum and 9 * Jeremy Morse (jeremy.morse (at) gmail.com). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 35 * 36 * The EHCI 1.0 spec can be found at 37 * http://www.intel.com/technology/usb/spec.htm 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/ 40 * 41 */ 42 43 /* 44 * TODO: 45 * 1) hold off explorations by companion controllers until ehci has started. 46 * 47 * 2) The hub driver needs to handle and schedule the transaction translator, 48 * to assign place in frame where different devices get to go. See chapter 49 * on hubs in USB 2.0 for details. 50 * 51 * 3) Command failures are not recovered correctly. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.183.2.2 2013/12/14 19:26:39 bouyer Exp $"); 56 57 #include "ohci.h" 58 #include "uhci.h" 59 #include "opt_usb.h" 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/kernel.h> 64 #include <sys/malloc.h> 65 #include <sys/device.h> 66 #include <sys/select.h> 67 #include <sys/proc.h> 68 #include <sys/queue.h> 69 #include <sys/mutex.h> 70 #include <sys/bus.h> 71 72 #include <machine/endian.h> 73 74 #include <dev/usb/usb.h> 75 #include <dev/usb/usbdi.h> 76 #include <dev/usb/usbdivar.h> 77 #include <dev/usb/usb_mem.h> 78 #include <dev/usb/usb_quirks.h> 79 80 #include <dev/usb/ehcireg.h> 81 #include <dev/usb/ehcivar.h> 82 #include <dev/usb/usbroothub_subr.h> 83 84 #ifdef EHCI_DEBUG 85 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 86 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 87 int ehcidebug = 0; 88 #else 89 #define DPRINTF(x) 90 #define DPRINTFN(n,x) 91 #endif 92 93 struct ehci_pipe { 94 struct usbd_pipe pipe; 95 int nexttoggle; 96 97 ehci_soft_qh_t *sqh; 98 union { 99 ehci_soft_qtd_t *qtd; 100 /* ehci_soft_itd_t *itd; */ 101 } tail; 102 union { 103 /* Control pipe */ 104 struct { 105 usb_dma_t reqdma; 106 u_int length; 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 u_int length; 111 } intr; 112 /* Bulk pipe */ 113 struct { 114 u_int length; 115 } bulk; 116 /* Iso pipe */ 117 struct { 118 u_int next_frame; 119 u_int cur_xfers; 120 } isoc; 121 } u; 122 }; 123 124 Static usbd_status ehci_open(usbd_pipe_handle); 125 Static void ehci_poll(struct usbd_bus *); 126 Static void ehci_softintr(void *); 127 Static int ehci_intr1(ehci_softc_t *); 128 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 129 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 130 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 131 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 132 Static void ehci_idone(struct ehci_xfer *); 133 Static void ehci_timeout(void *); 134 Static void ehci_timeout_task(void *); 135 Static void ehci_intrlist_timeout(void *); 136 137 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 138 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 139 140 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 141 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 142 143 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 144 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 145 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 146 Static void ehci_root_ctrl_close(usbd_pipe_handle); 147 Static void ehci_root_ctrl_done(usbd_xfer_handle); 148 149 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 150 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 151 Static void ehci_root_intr_abort(usbd_xfer_handle); 152 Static void ehci_root_intr_close(usbd_pipe_handle); 153 Static void ehci_root_intr_done(usbd_xfer_handle); 154 155 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 156 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 157 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 158 Static void ehci_device_ctrl_close(usbd_pipe_handle); 159 Static void ehci_device_ctrl_done(usbd_xfer_handle); 160 161 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 162 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 163 Static void ehci_device_bulk_abort(usbd_xfer_handle); 164 Static void ehci_device_bulk_close(usbd_pipe_handle); 165 Static void ehci_device_bulk_done(usbd_xfer_handle); 166 167 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 168 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 169 Static void ehci_device_intr_abort(usbd_xfer_handle); 170 Static void ehci_device_intr_close(usbd_pipe_handle); 171 Static void ehci_device_intr_done(usbd_xfer_handle); 172 173 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 174 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 175 Static void ehci_device_isoc_abort(usbd_xfer_handle); 176 Static void ehci_device_isoc_close(usbd_pipe_handle); 177 Static void ehci_device_isoc_done(usbd_xfer_handle); 178 179 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 180 Static void ehci_noop(usbd_pipe_handle pipe); 181 182 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 183 Static void ehci_disown(ehci_softc_t *, int, int); 184 185 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 186 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 187 188 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 189 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 190 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 191 ehci_softc_t *, int, int, usbd_xfer_handle, 192 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 193 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 194 ehci_soft_qtd_t *); 195 196 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 197 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 198 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 199 struct ehci_xfer *exfer); 200 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 201 usbd_status status); 202 203 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 204 205 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 206 int ival); 207 208 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 209 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 210 ehci_soft_qh_t *); 211 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 212 Static void ehci_sync_hc(ehci_softc_t *); 213 214 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 215 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 216 217 #ifdef EHCI_DEBUG 218 Static void ehci_dump_regs(ehci_softc_t *); 219 void ehci_dump(void); 220 Static ehci_softc_t *theehci; 221 Static void ehci_dump_link(ehci_link_t, int); 222 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 223 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 224 Static void ehci_dump_qtd(ehci_qtd_t *); 225 Static void ehci_dump_sqh(ehci_soft_qh_t *); 226 #if notyet 227 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 228 Static void ehci_dump_itd(struct ehci_soft_itd *); 229 #endif 230 #ifdef DIAGNOSTIC 231 Static void ehci_dump_exfer(struct ehci_xfer *); 232 #endif 233 #endif 234 235 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 236 237 #define EHCI_INTR_ENDPT 1 238 239 #define ehci_add_intr_list(sc, ex) \ 240 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 241 #define ehci_del_intr_list(sc, ex) \ 242 do { \ 243 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 244 (ex)->inext.tqe_prev = NULL; \ 245 } while (0) 246 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 247 248 Static const struct usbd_bus_methods ehci_bus_methods = { 249 ehci_open, 250 ehci_softintr, 251 ehci_poll, 252 ehci_allocm, 253 ehci_freem, 254 ehci_allocx, 255 ehci_freex, 256 }; 257 258 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 259 ehci_root_ctrl_transfer, 260 ehci_root_ctrl_start, 261 ehci_root_ctrl_abort, 262 ehci_root_ctrl_close, 263 ehci_noop, 264 ehci_root_ctrl_done, 265 }; 266 267 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 268 ehci_root_intr_transfer, 269 ehci_root_intr_start, 270 ehci_root_intr_abort, 271 ehci_root_intr_close, 272 ehci_noop, 273 ehci_root_intr_done, 274 }; 275 276 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 277 ehci_device_ctrl_transfer, 278 ehci_device_ctrl_start, 279 ehci_device_ctrl_abort, 280 ehci_device_ctrl_close, 281 ehci_noop, 282 ehci_device_ctrl_done, 283 }; 284 285 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 286 ehci_device_intr_transfer, 287 ehci_device_intr_start, 288 ehci_device_intr_abort, 289 ehci_device_intr_close, 290 ehci_device_clear_toggle, 291 ehci_device_intr_done, 292 }; 293 294 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 295 ehci_device_bulk_transfer, 296 ehci_device_bulk_start, 297 ehci_device_bulk_abort, 298 ehci_device_bulk_close, 299 ehci_device_clear_toggle, 300 ehci_device_bulk_done, 301 }; 302 303 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 304 ehci_device_isoc_transfer, 305 ehci_device_isoc_start, 306 ehci_device_isoc_abort, 307 ehci_device_isoc_close, 308 ehci_noop, 309 ehci_device_isoc_done, 310 }; 311 312 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 313 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 314 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 315 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 316 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 317 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 318 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 319 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 320 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 321 }; 322 323 usbd_status 324 ehci_init(ehci_softc_t *sc) 325 { 326 u_int32_t vers, sparams, cparams, hcr; 327 u_int i; 328 usbd_status err; 329 ehci_soft_qh_t *sqh; 330 u_int ncomp; 331 332 DPRINTF(("ehci_init: start\n")); 333 #ifdef EHCI_DEBUG 334 theehci = sc; 335 #endif 336 337 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 338 339 vers = EREAD2(sc, EHCI_HCIVERSION); 340 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 341 vers >> 8, vers & 0xff); 342 343 sparams = EREAD4(sc, EHCI_HCSPARAMS); 344 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 345 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 346 ncomp = EHCI_HCS_N_CC(sparams); 347 if (ncomp != sc->sc_ncomp) { 348 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 349 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 350 #if NOHCI == 0 || NUHCI == 0 351 aprint_error("%s: ohci or uhci probably not configured\n", 352 device_xname(sc->sc_dev)); 353 #endif 354 if (ncomp < sc->sc_ncomp) 355 sc->sc_ncomp = ncomp; 356 } 357 if (sc->sc_ncomp > 0) { 358 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 359 aprint_normal("%s: companion controller%s, %d port%s each:", 360 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 361 EHCI_HCS_N_PCC(sparams), 362 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 363 for (i = 0; i < sc->sc_ncomp; i++) 364 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 365 aprint_normal("\n"); 366 } 367 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 368 cparams = EREAD4(sc, EHCI_HCCPARAMS); 369 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 370 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 371 372 if (EHCI_HCC_64BIT(cparams)) { 373 /* MUST clear segment register if 64 bit capable. */ 374 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 375 } 376 377 sc->sc_bus.usbrev = USBREV_2_0; 378 379 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 380 USB_MEM_RESERVE); 381 382 /* Reset the controller */ 383 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 384 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 385 usb_delay_ms(&sc->sc_bus, 1); 386 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 387 for (i = 0; i < 100; i++) { 388 usb_delay_ms(&sc->sc_bus, 1); 389 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 390 if (!hcr) 391 break; 392 } 393 if (hcr) { 394 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 395 return (USBD_IOERROR); 396 } 397 if (sc->sc_vendor_init) 398 sc->sc_vendor_init(sc); 399 400 /* 401 * If we are doing embedded transaction translation function, force 402 * the controller to host mode. 403 */ 404 if (sc->sc_flags & EHCIF_ETTF) { 405 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 406 usbmode &= ~EHCI_USBMODE_CM; 407 usbmode |= EHCI_USBMODE_CM_HOST; 408 EWRITE4(sc, EHCI_USBMODE, usbmode); 409 } 410 411 /* XXX need proper intr scheduling */ 412 sc->sc_rand = 96; 413 414 /* frame list size at default, read back what we got and use that */ 415 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 416 case 0: sc->sc_flsize = 1024; break; 417 case 1: sc->sc_flsize = 512; break; 418 case 2: sc->sc_flsize = 256; break; 419 case 3: return (USBD_IOERROR); 420 } 421 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 422 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 423 if (err) 424 return (err); 425 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 426 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 427 428 for (i = 0; i < sc->sc_flsize; i++) { 429 sc->sc_flist[i] = EHCI_NULL; 430 } 431 432 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 433 434 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 435 M_USB, M_NOWAIT | M_ZERO); 436 if (sc->sc_softitds == NULL) 437 return ENOMEM; 438 LIST_INIT(&sc->sc_freeitds); 439 TAILQ_INIT(&sc->sc_intrhead); 440 mutex_init(&sc->sc_intrhead_lock, MUTEX_DEFAULT, IPL_USB); 441 442 /* Set up the bus struct. */ 443 sc->sc_bus.methods = &ehci_bus_methods; 444 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 445 446 sc->sc_eintrs = EHCI_NORMAL_INTRS; 447 448 /* 449 * Allocate the interrupt dummy QHs. These are arranged to give poll 450 * intervals that are powers of 2 times 1ms. 451 */ 452 for (i = 0; i < EHCI_INTRQHS; i++) { 453 sqh = ehci_alloc_sqh(sc); 454 if (sqh == NULL) { 455 err = USBD_NOMEM; 456 goto bad1; 457 } 458 sc->sc_islots[i].sqh = sqh; 459 } 460 for (i = 0; i < EHCI_INTRQHS; i++) { 461 sqh = sc->sc_islots[i].sqh; 462 if (i == 0) { 463 /* The last (1ms) QH terminates. */ 464 sqh->qh.qh_link = EHCI_NULL; 465 sqh->next = NULL; 466 } else { 467 /* Otherwise the next QH has half the poll interval */ 468 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 469 sqh->qh.qh_link = htole32(sqh->next->physaddr | 470 EHCI_LINK_QH); 471 } 472 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 473 sqh->qh.qh_curqtd = EHCI_NULL; 474 sqh->next = NULL; 475 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 476 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 477 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 478 sqh->sqtd = NULL; 479 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 480 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 481 } 482 /* Point the frame list at the last level (128ms). */ 483 for (i = 0; i < sc->sc_flsize; i++) { 484 int j; 485 486 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 487 revbits[i & (EHCI_MAX_POLLRATE-1)]; 488 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 489 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 490 i)].sqh->physaddr); 491 } 492 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 493 BUS_DMASYNC_PREWRITE); 494 495 /* Allocate dummy QH that starts the async list. */ 496 sqh = ehci_alloc_sqh(sc); 497 if (sqh == NULL) { 498 err = USBD_NOMEM; 499 goto bad1; 500 } 501 /* Fill the QH */ 502 sqh->qh.qh_endp = 503 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 504 sqh->qh.qh_link = 505 htole32(sqh->physaddr | EHCI_LINK_QH); 506 sqh->qh.qh_curqtd = EHCI_NULL; 507 sqh->next = NULL; 508 /* Fill the overlay qTD */ 509 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 510 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 511 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 512 sqh->sqtd = NULL; 513 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 514 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 515 #ifdef EHCI_DEBUG 516 if (ehcidebug) { 517 ehci_dump_sqh(sqh); 518 } 519 #endif 520 521 /* Point to async list */ 522 sc->sc_async_head = sqh; 523 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 524 525 callout_init(&(sc->sc_tmo_intrlist), 0); 526 527 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE); 528 529 /* Turn on controller */ 530 EOWRITE4(sc, EHCI_USBCMD, 531 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 532 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 533 EHCI_CMD_ASE | 534 EHCI_CMD_PSE | 535 EHCI_CMD_RS); 536 537 /* Take over port ownership */ 538 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 539 540 for (i = 0; i < 100; i++) { 541 usb_delay_ms(&sc->sc_bus, 1); 542 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 543 if (!hcr) 544 break; 545 } 546 if (hcr) { 547 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 548 return (USBD_IOERROR); 549 } 550 551 /* Enable interrupts */ 552 DPRINTFN(1,("ehci_init: enabling\n")); 553 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 554 555 return (USBD_NORMAL_COMPLETION); 556 557 #if 0 558 bad2: 559 ehci_free_sqh(sc, sc->sc_async_head); 560 #endif 561 bad1: 562 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 563 return (err); 564 } 565 566 int 567 ehci_intr(void *v) 568 { 569 ehci_softc_t *sc = v; 570 571 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 572 return (0); 573 574 /* If we get an interrupt while polling, then just ignore it. */ 575 if (sc->sc_bus.use_polling) { 576 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 577 578 if (intrs) 579 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 580 #ifdef DIAGNOSTIC 581 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 582 #endif 583 return (0); 584 } 585 586 return (ehci_intr1(sc)); 587 } 588 589 Static int 590 ehci_intr1(ehci_softc_t *sc) 591 { 592 u_int32_t intrs, eintrs; 593 594 DPRINTFN(20,("ehci_intr1: enter\n")); 595 596 /* In case the interrupt occurs before initialization has completed. */ 597 if (sc == NULL) { 598 #ifdef DIAGNOSTIC 599 printf("ehci_intr1: sc == NULL\n"); 600 #endif 601 return (0); 602 } 603 604 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 605 if (!intrs) 606 return (0); 607 608 eintrs = intrs & sc->sc_eintrs; 609 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 610 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 611 (u_int)eintrs)); 612 if (!eintrs) 613 return (0); 614 615 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 616 sc->sc_bus.intr_context++; 617 sc->sc_bus.no_intrs++; 618 if (eintrs & EHCI_STS_IAA) { 619 DPRINTF(("ehci_intr1: door bell\n")); 620 wakeup(&sc->sc_async_head); 621 eintrs &= ~EHCI_STS_IAA; 622 } 623 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 624 DPRINTFN(5,("ehci_intr1: %s %s\n", 625 eintrs & EHCI_STS_INT ? "INT" : "", 626 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 627 usb_schedsoftintr(&sc->sc_bus); 628 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 629 } 630 if (eintrs & EHCI_STS_HSE) { 631 printf("%s: unrecoverable error, controller halted\n", 632 device_xname(sc->sc_dev)); 633 /* XXX what else */ 634 } 635 if (eintrs & EHCI_STS_PCD) { 636 ehci_pcd(sc, sc->sc_intrxfer); 637 eintrs &= ~EHCI_STS_PCD; 638 } 639 640 sc->sc_bus.intr_context--; 641 642 if (eintrs != 0) { 643 /* Block unprocessed interrupts. */ 644 sc->sc_eintrs &= ~eintrs; 645 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 646 printf("%s: blocking intrs 0x%x\n", 647 device_xname(sc->sc_dev), eintrs); 648 } 649 650 return (1); 651 } 652 653 654 Static void 655 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 656 { 657 usbd_pipe_handle pipe; 658 u_char *p; 659 int i, m; 660 661 if (xfer == NULL) { 662 /* Just ignore the change. */ 663 return; 664 } 665 666 pipe = xfer->pipe; 667 668 p = KERNADDR(&xfer->dmabuf, 0); 669 m = min(sc->sc_noport, xfer->length * 8 - 1); 670 memset(p, 0, xfer->length); 671 for (i = 1; i <= m; i++) { 672 /* Pick out CHANGE bits from the status reg. */ 673 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 674 p[i/8] |= 1 << (i%8); 675 } 676 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 677 xfer->actlen = xfer->length; 678 xfer->status = USBD_NORMAL_COMPLETION; 679 680 usb_transfer_complete(xfer); 681 } 682 683 Static void 684 ehci_softintr(void *v) 685 { 686 struct usbd_bus *bus = v; 687 ehci_softc_t *sc = bus->hci_private; 688 struct ehci_xfer *ex, *nextex; 689 690 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 691 sc->sc_bus.intr_context)); 692 693 sc->sc_bus.intr_context++; 694 695 /* 696 * The only explanation I can think of for why EHCI is as brain dead 697 * as UHCI interrupt-wise is that Intel was involved in both. 698 * An interrupt just tells us that something is done, we have no 699 * clue what, so we need to scan through all active transfers. :-( 700 */ 701 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 702 nextex = TAILQ_NEXT(ex, inext); 703 ehci_check_intr(sc, ex); 704 } 705 706 /* Schedule a callout to catch any dropped transactions. */ 707 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 708 !TAILQ_EMPTY(&sc->sc_intrhead)) 709 callout_reset(&(sc->sc_tmo_intrlist), 710 (hz), (ehci_intrlist_timeout), (sc)); 711 712 #ifdef USB_USE_SOFTINTR 713 if (sc->sc_softwake) { 714 sc->sc_softwake = 0; 715 wakeup(&sc->sc_softwake); 716 } 717 #endif /* USB_USE_SOFTINTR */ 718 719 sc->sc_bus.intr_context--; 720 } 721 722 /* Check for an interrupt. */ 723 Static void 724 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 725 { 726 int attr; 727 728 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 729 730 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 731 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 732 ehci_check_itd_intr(sc, ex); 733 else 734 ehci_check_qh_intr(sc, ex); 735 736 return; 737 } 738 739 Static void 740 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 741 { 742 ehci_soft_qtd_t *sqtd, *lsqtd; 743 __uint32_t status; 744 745 if (ex->sqtdstart == NULL) { 746 printf("ehci_check_qh_intr: not valid sqtd\n"); 747 return; 748 } 749 750 lsqtd = ex->sqtdend; 751 #ifdef DIAGNOSTIC 752 if (lsqtd == NULL) { 753 printf("ehci_check_qh_intr: lsqtd==0\n"); 754 return; 755 } 756 #endif 757 /* 758 * If the last TD is still active we need to check whether there 759 * is a an error somewhere in the middle, or whether there was a 760 * short packet (SPD and not ACTIVE). 761 */ 762 usb_syncmem(&lsqtd->dma, 763 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 764 sizeof(lsqtd->qtd.qtd_status), 765 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 766 status = le32toh(lsqtd->qtd.qtd_status); 767 usb_syncmem(&lsqtd->dma, 768 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 769 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 770 if (status & EHCI_QTD_ACTIVE) { 771 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 772 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 773 usb_syncmem(&sqtd->dma, 774 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 775 sizeof(sqtd->qtd.qtd_status), 776 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 777 status = le32toh(sqtd->qtd.qtd_status); 778 usb_syncmem(&sqtd->dma, 779 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 780 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 781 /* If there's an active QTD the xfer isn't done. */ 782 if (status & EHCI_QTD_ACTIVE) 783 break; 784 /* Any kind of error makes the xfer done. */ 785 if (status & EHCI_QTD_HALTED) 786 goto done; 787 /* Handle short packets */ 788 if (EHCI_QTD_GET_BYTES(status) != 0) { 789 usbd_pipe_handle pipe = ex->xfer.pipe; 790 usb_endpoint_descriptor_t *ed = 791 pipe->endpoint->edesc; 792 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 793 794 /* 795 * If we get here for a control transfer then 796 * we need to let the hardware complete the 797 * status phase. That is, we're not done 798 * quite yet. 799 * 800 * Otherwise, we're done. 801 */ 802 if (xt == UE_CONTROL) { 803 break; 804 } 805 goto done; 806 } 807 } 808 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 809 ex, ex->sqtdstart)); 810 return; 811 } 812 done: 813 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 814 callout_stop(&ex->xfer.timeout_handle); 815 ehci_idone(ex); 816 } 817 818 Static void 819 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 820 ehci_soft_itd_t *itd; 821 int i; 822 823 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 824 return; 825 826 if (ex->itdstart == NULL) { 827 printf("ehci_check_itd_intr: not valid itd\n"); 828 return; 829 } 830 831 itd = ex->itdend; 832 #ifdef DIAGNOSTIC 833 if (itd == NULL) { 834 printf("ehci_check_itd_intr: itdend == 0\n"); 835 return; 836 } 837 #endif 838 839 /* 840 * check no active transfers in last itd, meaning we're finished 841 */ 842 843 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 844 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 845 BUS_DMASYNC_POSTREAD); 846 847 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 848 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 849 break; 850 } 851 852 if (i == EHCI_ITD_NUFRAMES) { 853 goto done; /* All 8 descriptors inactive, it's done */ 854 } 855 856 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 857 ex->itdstart)); 858 return; 859 done: 860 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 861 callout_stop(&ex->xfer.timeout_handle); 862 ehci_idone(ex); 863 } 864 865 Static void 866 ehci_idone(struct ehci_xfer *ex) 867 { 868 usbd_xfer_handle xfer = &ex->xfer; 869 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 870 ehci_soft_qtd_t *sqtd, *lsqtd; 871 u_int32_t status = 0, nstatus = 0; 872 int actlen; 873 874 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 875 #ifdef DIAGNOSTIC 876 { 877 int s = splhigh(); 878 if (ex->isdone) { 879 splx(s); 880 #ifdef EHCI_DEBUG 881 printf("ehci_idone: ex is done!\n "); 882 ehci_dump_exfer(ex); 883 #else 884 printf("ehci_idone: ex=%p is done!\n", ex); 885 #endif 886 return; 887 } 888 ex->isdone = 1; 889 splx(s); 890 } 891 #endif 892 if (xfer->status == USBD_CANCELLED || 893 xfer->status == USBD_TIMEOUT) { 894 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 895 return; 896 } 897 898 #ifdef EHCI_DEBUG 899 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 900 if (ehcidebug > 10) 901 ehci_dump_sqtds(ex->sqtdstart); 902 #endif 903 904 /* The transfer is done, compute actual length and status. */ 905 906 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 907 == UE_ISOCHRONOUS) { 908 /* Isoc transfer */ 909 struct ehci_soft_itd *itd; 910 int i, nframes, len, uframes; 911 912 nframes = 0; 913 actlen = 0; 914 915 i = xfer->pipe->endpoint->edesc->bInterval; 916 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 917 918 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 919 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 920 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 921 BUS_DMASYNC_POSTREAD); 922 923 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 924 /* XXX - driver didn't fill in the frame full 925 * of uframes. This leads to scheduling 926 * inefficiencies, but working around 927 * this doubles complexity of tracking 928 * an xfer. 929 */ 930 if (nframes >= xfer->nframes) 931 break; 932 933 status = le32toh(itd->itd.itd_ctl[i]); 934 len = EHCI_ITD_GET_LEN(status); 935 if (EHCI_ITD_GET_STATUS(status) != 0) 936 len = 0; /*No valid data on error*/ 937 938 xfer->frlengths[nframes++] = len; 939 actlen += len; 940 } 941 942 if (nframes >= xfer->nframes) 943 break; 944 } 945 946 xfer->actlen = actlen; 947 xfer->status = USBD_NORMAL_COMPLETION; 948 goto end; 949 } 950 951 /* Continue processing xfers using queue heads */ 952 953 lsqtd = ex->sqtdend; 954 actlen = 0; 955 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 956 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 957 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 958 nstatus = le32toh(sqtd->qtd.qtd_status); 959 if (nstatus & EHCI_QTD_ACTIVE) 960 break; 961 962 status = nstatus; 963 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 964 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 965 } 966 967 968 /* 969 * If there are left over TDs we need to update the toggle. 970 * The default pipe doesn't need it since control transfers 971 * start the toggle at 0 every time. 972 * For a short transfer we need to update the toggle for the missing 973 * packets within the qTD. 974 */ 975 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 976 xfer->pipe->device->default_pipe != xfer->pipe) { 977 DPRINTFN(2, ("ehci_idone: need toggle update " 978 "status=%08x nstatus=%08x\n", status, nstatus)); 979 #if 0 980 ehci_dump_sqh(epipe->sqh); 981 ehci_dump_sqtds(ex->sqtdstart); 982 #endif 983 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 984 } 985 986 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 987 xfer->length, actlen, status)); 988 xfer->actlen = actlen; 989 if (status & EHCI_QTD_HALTED) { 990 #ifdef EHCI_DEBUG 991 char sbuf[128]; 992 993 snprintb(sbuf, sizeof(sbuf), 994 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 995 (u_int32_t)status); 996 997 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 998 "status 0x%s\n", 999 xfer->pipe->device->address, 1000 xfer->pipe->endpoint->edesc->bEndpointAddress, 1001 sbuf)); 1002 if (ehcidebug > 2) { 1003 ehci_dump_sqh(epipe->sqh); 1004 ehci_dump_sqtds(ex->sqtdstart); 1005 } 1006 #endif 1007 /* low&full speed has an extra error flag */ 1008 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1009 EHCI_QH_SPEED_HIGH) 1010 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1011 else 1012 status &= EHCI_QTD_STATERRS; 1013 if (status == 0) /* no other errors means a stall */ { 1014 xfer->status = USBD_STALLED; 1015 } else { 1016 xfer->status = USBD_IOERROR; /* more info XXX */ 1017 } 1018 /* XXX need to reset TT on missed microframe */ 1019 if (status & EHCI_QTD_MISSEDMICRO) { 1020 ehci_softc_t *sc = 1021 xfer->pipe->device->bus->hci_private; 1022 1023 printf("%s: missed microframe, TT reset not " 1024 "implemented, hub might be inoperational\n", 1025 device_xname(sc->sc_dev)); 1026 } 1027 } else { 1028 xfer->status = USBD_NORMAL_COMPLETION; 1029 } 1030 1031 end: 1032 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1033 * during this call, before methods->done is called: dma sync required 1034 * beforehand? */ 1035 usb_transfer_complete(xfer); 1036 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1037 } 1038 1039 /* 1040 * Wait here until controller claims to have an interrupt. 1041 * Then call ehci_intr and return. Use timeout to avoid waiting 1042 * too long. 1043 */ 1044 Static void 1045 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1046 { 1047 int timo; 1048 u_int32_t intrs; 1049 1050 xfer->status = USBD_IN_PROGRESS; 1051 for (timo = xfer->timeout; timo >= 0; timo--) { 1052 usb_delay_ms(&sc->sc_bus, 1); 1053 if (sc->sc_dying) 1054 break; 1055 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1056 sc->sc_eintrs; 1057 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1058 #ifdef EHCI_DEBUG 1059 if (ehcidebug > 15) 1060 ehci_dump_regs(sc); 1061 #endif 1062 if (intrs) { 1063 ehci_intr1(sc); 1064 if (xfer->status != USBD_IN_PROGRESS) 1065 return; 1066 } 1067 } 1068 1069 /* Timeout */ 1070 DPRINTF(("ehci_waitintr: timeout\n")); 1071 xfer->status = USBD_TIMEOUT; 1072 usb_transfer_complete(xfer); 1073 /* XXX should free TD */ 1074 } 1075 1076 Static void 1077 ehci_poll(struct usbd_bus *bus) 1078 { 1079 ehci_softc_t *sc = bus->hci_private; 1080 #ifdef EHCI_DEBUG 1081 static int last; 1082 int new; 1083 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1084 if (new != last) { 1085 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1086 last = new; 1087 } 1088 #endif 1089 1090 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1091 ehci_intr1(sc); 1092 } 1093 1094 void 1095 ehci_childdet(device_t self, device_t child) 1096 { 1097 struct ehci_softc *sc = device_private(self); 1098 1099 KASSERT(sc->sc_child == child); 1100 sc->sc_child = NULL; 1101 } 1102 1103 int 1104 ehci_detach(struct ehci_softc *sc, int flags) 1105 { 1106 int rv = 0; 1107 1108 if (sc->sc_child != NULL) 1109 rv = config_detach(sc->sc_child, flags); 1110 1111 if (rv != 0) 1112 return (rv); 1113 1114 callout_stop(&sc->sc_tmo_intrlist); 1115 1116 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1117 1118 /* XXX free other data structures XXX */ 1119 mutex_destroy(&sc->sc_doorbell_lock); 1120 mutex_destroy(&sc->sc_intrhead_lock); 1121 1122 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1123 1124 return (rv); 1125 } 1126 1127 1128 int 1129 ehci_activate(device_t self, enum devact act) 1130 { 1131 struct ehci_softc *sc = device_private(self); 1132 1133 switch (act) { 1134 case DVACT_DEACTIVATE: 1135 sc->sc_dying = 1; 1136 return 0; 1137 default: 1138 return EOPNOTSUPP; 1139 } 1140 } 1141 1142 /* 1143 * Handle suspend/resume. 1144 * 1145 * We need to switch to polling mode here, because this routine is 1146 * called from an interrupt context. This is all right since we 1147 * are almost suspended anyway. 1148 * 1149 * Note that this power handler isn't to be registered directly; the 1150 * bus glue needs to call out to it. 1151 */ 1152 bool 1153 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1154 { 1155 ehci_softc_t *sc = device_private(dv); 1156 int i, s; 1157 uint32_t cmd, hcr; 1158 1159 s = splhardusb(); 1160 1161 sc->sc_bus.use_polling++; 1162 1163 for (i = 1; i <= sc->sc_noport; i++) { 1164 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1165 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1166 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1167 } 1168 1169 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1170 1171 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1172 EOWRITE4(sc, EHCI_USBCMD, cmd); 1173 1174 for (i = 0; i < 100; i++) { 1175 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1176 if (hcr == 0) 1177 break; 1178 1179 usb_delay_ms(&sc->sc_bus, 1); 1180 } 1181 if (hcr != 0) 1182 printf("%s: reset timeout\n", device_xname(dv)); 1183 1184 cmd &= ~EHCI_CMD_RS; 1185 EOWRITE4(sc, EHCI_USBCMD, cmd); 1186 1187 for (i = 0; i < 100; i++) { 1188 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1189 if (hcr == EHCI_STS_HCH) 1190 break; 1191 1192 usb_delay_ms(&sc->sc_bus, 1); 1193 } 1194 if (hcr != EHCI_STS_HCH) 1195 printf("%s: config timeout\n", device_xname(dv)); 1196 1197 sc->sc_bus.use_polling--; 1198 splx(s); 1199 1200 return true; 1201 } 1202 1203 bool 1204 ehci_resume(device_t dv, const pmf_qual_t *qual) 1205 { 1206 ehci_softc_t *sc = device_private(dv); 1207 int i; 1208 uint32_t cmd, hcr; 1209 1210 /* restore things in case the bios sucks */ 1211 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1212 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1213 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1214 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1215 1216 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1217 1218 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1219 1220 hcr = 0; 1221 for (i = 1; i <= sc->sc_noport; i++) { 1222 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1223 if ((cmd & EHCI_PS_PO) == 0 && 1224 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1225 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1226 hcr = 1; 1227 } 1228 } 1229 1230 if (hcr) { 1231 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1232 1233 for (i = 1; i <= sc->sc_noport; i++) { 1234 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1235 if ((cmd & EHCI_PS_PO) == 0 && 1236 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1237 EOWRITE4(sc, EHCI_PORTSC(i), 1238 cmd & ~EHCI_PS_FPR); 1239 } 1240 } 1241 1242 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1243 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1244 1245 for (i = 0; i < 100; i++) { 1246 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1247 if (hcr != EHCI_STS_HCH) 1248 break; 1249 1250 usb_delay_ms(&sc->sc_bus, 1); 1251 } 1252 if (hcr == EHCI_STS_HCH) 1253 printf("%s: config timeout\n", device_xname(dv)); 1254 1255 return true; 1256 } 1257 1258 /* 1259 * Shut down the controller when the system is going down. 1260 */ 1261 bool 1262 ehci_shutdown(device_t self, int flags) 1263 { 1264 ehci_softc_t *sc = device_private(self); 1265 1266 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1267 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1268 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1269 return true; 1270 } 1271 1272 Static usbd_status 1273 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1274 { 1275 struct ehci_softc *sc = bus->hci_private; 1276 usbd_status err; 1277 1278 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1279 if (err == USBD_NOMEM) 1280 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1281 #ifdef EHCI_DEBUG 1282 if (err) 1283 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1284 #endif 1285 return (err); 1286 } 1287 1288 Static void 1289 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1290 { 1291 struct ehci_softc *sc = bus->hci_private; 1292 1293 if (dma->block->flags & USB_DMA_RESERVE) { 1294 usb_reserve_freem(&sc->sc_dma_reserve, 1295 dma); 1296 return; 1297 } 1298 usb_freemem(&sc->sc_bus, dma); 1299 } 1300 1301 Static usbd_xfer_handle 1302 ehci_allocx(struct usbd_bus *bus) 1303 { 1304 struct ehci_softc *sc = bus->hci_private; 1305 usbd_xfer_handle xfer; 1306 1307 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1308 if (xfer != NULL) { 1309 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1310 #ifdef DIAGNOSTIC 1311 if (xfer->busy_free != XFER_FREE) { 1312 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1313 xfer->busy_free); 1314 } 1315 #endif 1316 } else { 1317 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1318 } 1319 if (xfer != NULL) { 1320 memset(xfer, 0, sizeof(struct ehci_xfer)); 1321 #ifdef DIAGNOSTIC 1322 EXFER(xfer)->isdone = 1; 1323 xfer->busy_free = XFER_BUSY; 1324 #endif 1325 } 1326 return (xfer); 1327 } 1328 1329 Static void 1330 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1331 { 1332 struct ehci_softc *sc = bus->hci_private; 1333 1334 #ifdef DIAGNOSTIC 1335 if (xfer->busy_free != XFER_BUSY) { 1336 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1337 xfer->busy_free); 1338 } 1339 xfer->busy_free = XFER_FREE; 1340 if (!EXFER(xfer)->isdone) { 1341 printf("ehci_freex: !isdone\n"); 1342 } 1343 #endif 1344 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1345 } 1346 1347 Static void 1348 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1349 { 1350 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1351 1352 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1353 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1354 #ifdef EHCI_DEBUG 1355 if (ehcidebug) 1356 usbd_dump_pipe(pipe); 1357 #endif 1358 epipe->nexttoggle = 0; 1359 } 1360 1361 Static void 1362 ehci_noop(usbd_pipe_handle pipe) 1363 { 1364 } 1365 1366 #ifdef EHCI_DEBUG 1367 Static void 1368 ehci_dump_regs(ehci_softc_t *sc) 1369 { 1370 int i; 1371 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1372 EOREAD4(sc, EHCI_USBCMD), 1373 EOREAD4(sc, EHCI_USBSTS), 1374 EOREAD4(sc, EHCI_USBINTR)); 1375 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1376 EOREAD4(sc, EHCI_FRINDEX), 1377 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1378 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1379 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1380 for (i = 1; i <= sc->sc_noport; i++) 1381 printf("port %d status=0x%08x\n", i, 1382 EOREAD4(sc, EHCI_PORTSC(i))); 1383 } 1384 1385 /* 1386 * Unused function - this is meant to be called from a kernel 1387 * debugger. 1388 */ 1389 void 1390 ehci_dump(void) 1391 { 1392 ehci_dump_regs(theehci); 1393 } 1394 1395 Static void 1396 ehci_dump_link(ehci_link_t link, int type) 1397 { 1398 link = le32toh(link); 1399 printf("0x%08x", link); 1400 if (link & EHCI_LINK_TERMINATE) 1401 printf("<T>"); 1402 else { 1403 printf("<"); 1404 if (type) { 1405 switch (EHCI_LINK_TYPE(link)) { 1406 case EHCI_LINK_ITD: printf("ITD"); break; 1407 case EHCI_LINK_QH: printf("QH"); break; 1408 case EHCI_LINK_SITD: printf("SITD"); break; 1409 case EHCI_LINK_FSTN: printf("FSTN"); break; 1410 } 1411 } 1412 printf(">"); 1413 } 1414 } 1415 1416 Static void 1417 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1418 { 1419 int i; 1420 u_int32_t stop; 1421 1422 stop = 0; 1423 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1424 ehci_dump_sqtd(sqtd); 1425 usb_syncmem(&sqtd->dma, 1426 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1427 sizeof(sqtd->qtd), 1428 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1429 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1430 usb_syncmem(&sqtd->dma, 1431 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1432 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1433 } 1434 if (sqtd) 1435 printf("dump aborted, too many TDs\n"); 1436 } 1437 1438 Static void 1439 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1440 { 1441 usb_syncmem(&sqtd->dma, sqtd->offs, 1442 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1443 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1444 ehci_dump_qtd(&sqtd->qtd); 1445 usb_syncmem(&sqtd->dma, sqtd->offs, 1446 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1447 } 1448 1449 Static void 1450 ehci_dump_qtd(ehci_qtd_t *qtd) 1451 { 1452 u_int32_t s; 1453 char sbuf[128]; 1454 1455 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1456 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1457 printf("\n"); 1458 s = le32toh(qtd->qtd_status); 1459 snprintb(sbuf, sizeof(sbuf), 1460 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1461 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1462 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1463 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1464 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1465 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1466 EHCI_QTD_GET_PID(s), sbuf); 1467 for (s = 0; s < 5; s++) 1468 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1469 } 1470 1471 Static void 1472 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1473 { 1474 ehci_qh_t *qh = &sqh->qh; 1475 u_int32_t endp, endphub; 1476 1477 usb_syncmem(&sqh->dma, sqh->offs, 1478 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1479 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1480 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1481 endp = le32toh(qh->qh_endp); 1482 printf(" endp=0x%08x\n", endp); 1483 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1484 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1485 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1486 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1487 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1488 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1489 EHCI_QH_GET_NRL(endp)); 1490 endphub = le32toh(qh->qh_endphub); 1491 printf(" endphub=0x%08x\n", endphub); 1492 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1493 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1494 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1495 EHCI_QH_GET_MULT(endphub)); 1496 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1497 printf("Overlay qTD:\n"); 1498 ehci_dump_qtd(&qh->qh_qtd); 1499 usb_syncmem(&sqh->dma, sqh->offs, 1500 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1501 } 1502 1503 #if notyet 1504 Static void 1505 ehci_dump_itd(struct ehci_soft_itd *itd) 1506 { 1507 ehci_isoc_trans_t t; 1508 ehci_isoc_bufr_ptr_t b, b2, b3; 1509 int i; 1510 1511 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1512 1513 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1514 t = le32toh(itd->itd.itd_ctl[i]); 1515 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1516 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1517 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1518 EHCI_ITD_GET_OFFS(t)); 1519 } 1520 printf("ITDbufr: "); 1521 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1522 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1523 1524 b = le32toh(itd->itd.itd_bufr[0]); 1525 b2 = le32toh(itd->itd.itd_bufr[1]); 1526 b3 = le32toh(itd->itd.itd_bufr[2]); 1527 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1528 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1529 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1530 } 1531 1532 Static void 1533 ehci_dump_sitd(struct ehci_soft_itd *itd) 1534 { 1535 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1536 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1537 itd->xfer_next, itd->physaddr, itd->slot); 1538 } 1539 #endif 1540 1541 #ifdef DIAGNOSTIC 1542 Static void 1543 ehci_dump_exfer(struct ehci_xfer *ex) 1544 { 1545 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1546 } 1547 #endif 1548 #endif 1549 1550 Static usbd_status 1551 ehci_open(usbd_pipe_handle pipe) 1552 { 1553 usbd_device_handle dev = pipe->device; 1554 ehci_softc_t *sc = dev->bus->hci_private; 1555 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1556 u_int8_t addr = dev->address; 1557 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1558 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1559 ehci_soft_qh_t *sqh; 1560 usbd_status err; 1561 int s; 1562 int ival, speed, naks; 1563 int hshubaddr, hshubport; 1564 1565 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1566 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1567 1568 if (dev->myhsport) { 1569 /* 1570 * When directly attached FS/LS device while doing embedded 1571 * transaction translations and we are the hub, set the hub 1572 * adddress to 0 (us). 1573 */ 1574 if (!(sc->sc_flags & EHCIF_ETTF) 1575 || (dev->myhsport->parent->address != sc->sc_addr)) { 1576 hshubaddr = dev->myhsport->parent->address; 1577 } else { 1578 hshubaddr = 0; 1579 } 1580 hshubport = dev->myhsport->portno; 1581 } else { 1582 hshubaddr = 0; 1583 hshubport = 0; 1584 } 1585 1586 if (sc->sc_dying) 1587 return (USBD_IOERROR); 1588 1589 /* toggle state needed for bulk endpoints */ 1590 epipe->nexttoggle = pipe->endpoint->datatoggle; 1591 1592 if (addr == sc->sc_addr) { 1593 switch (ed->bEndpointAddress) { 1594 case USB_CONTROL_ENDPOINT: 1595 pipe->methods = &ehci_root_ctrl_methods; 1596 break; 1597 case UE_DIR_IN | EHCI_INTR_ENDPT: 1598 pipe->methods = &ehci_root_intr_methods; 1599 break; 1600 default: 1601 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1602 ed->bEndpointAddress)); 1603 return (USBD_INVAL); 1604 } 1605 return (USBD_NORMAL_COMPLETION); 1606 } 1607 1608 /* XXX All this stuff is only valid for async. */ 1609 switch (dev->speed) { 1610 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1611 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1612 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1613 default: panic("ehci_open: bad device speed %d", dev->speed); 1614 } 1615 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1616 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1617 "isoc endpoint.\n"); 1618 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1619 "attached to a USB2 hub, and transaction translations are " 1620 "not yet supported.\n"); 1621 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1622 "root hub instead.\n"); 1623 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1624 hshubaddr, hshubport)); 1625 return USBD_INVAL; 1626 } 1627 1628 /* 1629 * For interrupt transfer, nak throttling must be disabled, but for 1630 * the other transfer type, nak throttling should be enabled from the 1631 * veiwpoint that avoids the memory thrashing. 1632 */ 1633 naks = (xfertype == UE_INTERRUPT) ? 0 1634 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1635 1636 /* Allocate sqh for everything, save isoc xfers */ 1637 if (xfertype != UE_ISOCHRONOUS) { 1638 sqh = ehci_alloc_sqh(sc); 1639 if (sqh == NULL) 1640 return (USBD_NOMEM); 1641 /* qh_link filled when the QH is added */ 1642 sqh->qh.qh_endp = htole32( 1643 EHCI_QH_SET_ADDR(addr) | 1644 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1645 EHCI_QH_SET_EPS(speed) | 1646 EHCI_QH_DTC | 1647 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1648 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1649 EHCI_QH_CTL : 0) | 1650 EHCI_QH_SET_NRL(naks) 1651 ); 1652 sqh->qh.qh_endphub = htole32( 1653 EHCI_QH_SET_MULT(1) | 1654 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1655 ); 1656 if (speed != EHCI_QH_SPEED_HIGH) 1657 sqh->qh.qh_endphub |= htole32( 1658 EHCI_QH_SET_PORT(hshubport) | 1659 EHCI_QH_SET_HUBA(hshubaddr) | 1660 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1661 ); 1662 sqh->qh.qh_curqtd = EHCI_NULL; 1663 /* Fill the overlay qTD */ 1664 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1665 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1666 sqh->qh.qh_qtd.qtd_status = htole32(0); 1667 1668 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1669 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1670 epipe->sqh = sqh; 1671 } else { 1672 sqh = NULL; 1673 } /*xfertype == UE_ISOC*/ 1674 1675 switch (xfertype) { 1676 case UE_CONTROL: 1677 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1678 0, &epipe->u.ctl.reqdma); 1679 #ifdef EHCI_DEBUG 1680 if (err) 1681 printf("ehci_open: usb_allocmem()=%d\n", err); 1682 #endif 1683 if (err) 1684 goto bad; 1685 pipe->methods = &ehci_device_ctrl_methods; 1686 s = splusb(); 1687 ehci_add_qh(sqh, sc->sc_async_head); 1688 splx(s); 1689 break; 1690 case UE_BULK: 1691 pipe->methods = &ehci_device_bulk_methods; 1692 s = splusb(); 1693 ehci_add_qh(sqh, sc->sc_async_head); 1694 splx(s); 1695 break; 1696 case UE_INTERRUPT: 1697 pipe->methods = &ehci_device_intr_methods; 1698 ival = pipe->interval; 1699 if (ival == USBD_DEFAULT_INTERVAL) { 1700 if (speed == EHCI_QH_SPEED_HIGH) { 1701 if (ed->bInterval > 16) { 1702 /* 1703 * illegal with high-speed, but there 1704 * were documentation bugs in the spec, 1705 * so be generous 1706 */ 1707 ival = 256; 1708 } else 1709 ival = (1 << (ed->bInterval - 1)) / 8; 1710 } else 1711 ival = ed->bInterval; 1712 } 1713 err = ehci_device_setintr(sc, sqh, ival); 1714 if (err) 1715 goto bad; 1716 break; 1717 case UE_ISOCHRONOUS: 1718 pipe->methods = &ehci_device_isoc_methods; 1719 if (ed->bInterval == 0 || ed->bInterval > 16) { 1720 printf("ehci: opening pipe with invalid bInterval\n"); 1721 err = USBD_INVAL; 1722 goto bad; 1723 } 1724 if (UGETW(ed->wMaxPacketSize) == 0) { 1725 printf("ehci: zero length endpoint open request\n"); 1726 err = USBD_INVAL; 1727 goto bad; 1728 } 1729 epipe->u.isoc.next_frame = 0; 1730 epipe->u.isoc.cur_xfers = 0; 1731 break; 1732 default: 1733 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1734 err = USBD_INVAL; 1735 goto bad; 1736 } 1737 return (USBD_NORMAL_COMPLETION); 1738 1739 bad: 1740 if (sqh != NULL) 1741 ehci_free_sqh(sc, sqh); 1742 return (err); 1743 } 1744 1745 /* 1746 * Add an ED to the schedule. Called at splusb(). 1747 */ 1748 Static void 1749 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1750 { 1751 SPLUSBCHECK; 1752 1753 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1754 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1755 sqh->next = head->next; 1756 sqh->qh.qh_link = head->qh.qh_link; 1757 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1758 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1759 head->next = sqh; 1760 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1761 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1762 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1763 1764 #ifdef EHCI_DEBUG 1765 if (ehcidebug > 5) { 1766 printf("ehci_add_qh:\n"); 1767 ehci_dump_sqh(sqh); 1768 } 1769 #endif 1770 } 1771 1772 /* 1773 * Remove an ED from the schedule. Called at splusb(). 1774 */ 1775 Static void 1776 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1777 { 1778 ehci_soft_qh_t *p; 1779 1780 SPLUSBCHECK; 1781 /* XXX */ 1782 for (p = head; p != NULL && p->next != sqh; p = p->next) 1783 ; 1784 if (p == NULL) 1785 panic("ehci_rem_qh: ED not found"); 1786 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1787 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1788 p->next = sqh->next; 1789 p->qh.qh_link = sqh->qh.qh_link; 1790 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1791 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1792 1793 ehci_sync_hc(sc); 1794 } 1795 1796 Static void 1797 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1798 { 1799 int i; 1800 u_int32_t status; 1801 1802 /* Save toggle bit and ping status. */ 1803 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1804 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1805 status = sqh->qh.qh_qtd.qtd_status & 1806 htole32(EHCI_QTD_TOGGLE_MASK | 1807 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1808 /* Set HALTED to make hw leave it alone. */ 1809 sqh->qh.qh_qtd.qtd_status = 1810 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1811 usb_syncmem(&sqh->dma, 1812 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1813 sizeof(sqh->qh.qh_qtd.qtd_status), 1814 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1815 sqh->qh.qh_curqtd = 0; 1816 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1817 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1818 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1819 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1820 sqh->sqtd = sqtd; 1821 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1822 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1823 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1824 sqh->qh.qh_qtd.qtd_status = status; 1825 usb_syncmem(&sqh->dma, 1826 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1827 sizeof(sqh->qh.qh_qtd.qtd_status), 1828 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1829 } 1830 1831 /* 1832 * Ensure that the HC has released all references to the QH. We do this 1833 * by asking for a Async Advance Doorbell interrupt and then we wait for 1834 * the interrupt. 1835 * To make this easier we first obtain exclusive use of the doorbell. 1836 */ 1837 Static void 1838 ehci_sync_hc(ehci_softc_t *sc) 1839 { 1840 int s, error; 1841 1842 if (sc->sc_dying) { 1843 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1844 return; 1845 } 1846 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1847 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */ 1848 s = splhardusb(); 1849 /* ask for doorbell */ 1850 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1851 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1852 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1853 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1854 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1855 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1856 splx(s); 1857 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */ 1858 #ifdef DIAGNOSTIC 1859 if (error) 1860 printf("ehci_sync_hc: tsleep() = %d\n", error); 1861 #endif 1862 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1863 } 1864 1865 /*Call at splusb*/ 1866 Static void 1867 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1868 { 1869 struct ehci_soft_itd *itd, *prev; 1870 1871 prev = NULL; 1872 1873 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1874 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1875 1876 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1877 prev = itd->u.frame_list.prev; 1878 /* Unlink itd from hardware chain, or frame array */ 1879 if (prev == NULL) { /* We're at the table head */ 1880 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1881 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1882 usb_syncmem(&sc->sc_fldma, 1883 sizeof(ehci_link_t) * itd->slot, 1884 sizeof(ehci_link_t), 1885 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1886 1887 if (itd->u.frame_list.next != NULL) 1888 itd->u.frame_list.next->u.frame_list.prev = NULL; 1889 } else { 1890 /* XXX this part is untested... */ 1891 prev->itd.itd_next = itd->itd.itd_next; 1892 usb_syncmem(&itd->dma, 1893 itd->offs + offsetof(ehci_itd_t, itd_next), 1894 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1895 1896 prev->u.frame_list.next = itd->u.frame_list.next; 1897 if (itd->u.frame_list.next != NULL) 1898 itd->u.frame_list.next->u.frame_list.prev = prev; 1899 } 1900 } 1901 1902 prev = NULL; 1903 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1904 if (prev != NULL) 1905 ehci_free_itd(sc, prev); 1906 prev = itd; 1907 } 1908 if (prev) 1909 ehci_free_itd(sc, prev); 1910 exfer->itdstart = NULL; 1911 exfer->itdend = NULL; 1912 } 1913 1914 /***********/ 1915 1916 /* 1917 * Data structures and routines to emulate the root hub. 1918 */ 1919 Static usb_device_descriptor_t ehci_devd = { 1920 USB_DEVICE_DESCRIPTOR_SIZE, 1921 UDESC_DEVICE, /* type */ 1922 {0x00, 0x02}, /* USB version */ 1923 UDCLASS_HUB, /* class */ 1924 UDSUBCLASS_HUB, /* subclass */ 1925 UDPROTO_HSHUBSTT, /* protocol */ 1926 64, /* max packet */ 1927 {0},{0},{0x00,0x01}, /* device id */ 1928 1,2,0, /* string indicies */ 1929 1 /* # of configurations */ 1930 }; 1931 1932 Static const usb_device_qualifier_t ehci_odevd = { 1933 USB_DEVICE_DESCRIPTOR_SIZE, 1934 UDESC_DEVICE_QUALIFIER, /* type */ 1935 {0x00, 0x02}, /* USB version */ 1936 UDCLASS_HUB, /* class */ 1937 UDSUBCLASS_HUB, /* subclass */ 1938 UDPROTO_FSHUB, /* protocol */ 1939 64, /* max packet */ 1940 1, /* # of configurations */ 1941 0 1942 }; 1943 1944 Static const usb_config_descriptor_t ehci_confd = { 1945 USB_CONFIG_DESCRIPTOR_SIZE, 1946 UDESC_CONFIG, 1947 {USB_CONFIG_DESCRIPTOR_SIZE + 1948 USB_INTERFACE_DESCRIPTOR_SIZE + 1949 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1950 1, 1951 1, 1952 0, 1953 UC_ATTR_MBO | UC_SELF_POWERED, 1954 0 /* max power */ 1955 }; 1956 1957 Static const usb_interface_descriptor_t ehci_ifcd = { 1958 USB_INTERFACE_DESCRIPTOR_SIZE, 1959 UDESC_INTERFACE, 1960 0, 1961 0, 1962 1, 1963 UICLASS_HUB, 1964 UISUBCLASS_HUB, 1965 UIPROTO_HSHUBSTT, 1966 0 1967 }; 1968 1969 Static const usb_endpoint_descriptor_t ehci_endpd = { 1970 USB_ENDPOINT_DESCRIPTOR_SIZE, 1971 UDESC_ENDPOINT, 1972 UE_DIR_IN | EHCI_INTR_ENDPT, 1973 UE_INTERRUPT, 1974 {8, 0}, /* max packet */ 1975 12 1976 }; 1977 1978 Static const usb_hub_descriptor_t ehci_hubd = { 1979 USB_HUB_DESCRIPTOR_SIZE, 1980 UDESC_HUB, 1981 0, 1982 {0,0}, 1983 0, 1984 0, 1985 {""}, 1986 {""}, 1987 }; 1988 1989 /* 1990 * Simulate a hardware hub by handling all the necessary requests. 1991 */ 1992 Static usbd_status 1993 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1994 { 1995 usbd_status err; 1996 1997 /* Insert last in queue. */ 1998 err = usb_insert_transfer(xfer); 1999 if (err) 2000 return (err); 2001 2002 /* Pipe isn't running, start first */ 2003 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2004 } 2005 2006 Static usbd_status 2007 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2008 { 2009 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2010 usb_device_request_t *req; 2011 void *buf = NULL; 2012 int port, i; 2013 int s, len, value, index, l, totlen = 0; 2014 usb_port_status_t ps; 2015 usb_hub_descriptor_t hubd; 2016 usbd_status err; 2017 u_int32_t v; 2018 2019 if (sc->sc_dying) 2020 return (USBD_IOERROR); 2021 2022 #ifdef DIAGNOSTIC 2023 if (!(xfer->rqflags & URQ_REQUEST)) 2024 /* XXX panic */ 2025 return (USBD_INVAL); 2026 #endif 2027 req = &xfer->request; 2028 2029 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2030 req->bmRequestType, req->bRequest)); 2031 2032 len = UGETW(req->wLength); 2033 value = UGETW(req->wValue); 2034 index = UGETW(req->wIndex); 2035 2036 if (len != 0) 2037 buf = KERNADDR(&xfer->dmabuf, 0); 2038 2039 #define C(x,y) ((x) | ((y) << 8)) 2040 switch(C(req->bRequest, req->bmRequestType)) { 2041 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2042 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2043 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2044 /* 2045 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2046 * for the integrated root hub. 2047 */ 2048 break; 2049 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2050 if (len > 0) { 2051 *(u_int8_t *)buf = sc->sc_conf; 2052 totlen = 1; 2053 } 2054 break; 2055 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2056 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2057 if (len == 0) 2058 break; 2059 switch(value >> 8) { 2060 case UDESC_DEVICE: 2061 if ((value & 0xff) != 0) { 2062 err = USBD_IOERROR; 2063 goto ret; 2064 } 2065 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2066 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2067 memcpy(buf, &ehci_devd, l); 2068 break; 2069 /* 2070 * We can't really operate at another speed, but the spec says 2071 * we need this descriptor. 2072 */ 2073 case UDESC_DEVICE_QUALIFIER: 2074 if ((value & 0xff) != 0) { 2075 err = USBD_IOERROR; 2076 goto ret; 2077 } 2078 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2079 memcpy(buf, &ehci_odevd, l); 2080 break; 2081 /* 2082 * We can't really operate at another speed, but the spec says 2083 * we need this descriptor. 2084 */ 2085 case UDESC_OTHER_SPEED_CONFIGURATION: 2086 case UDESC_CONFIG: 2087 if ((value & 0xff) != 0) { 2088 err = USBD_IOERROR; 2089 goto ret; 2090 } 2091 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2092 memcpy(buf, &ehci_confd, l); 2093 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2094 value >> 8; 2095 buf = (char *)buf + l; 2096 len -= l; 2097 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2098 totlen += l; 2099 memcpy(buf, &ehci_ifcd, l); 2100 buf = (char *)buf + l; 2101 len -= l; 2102 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2103 totlen += l; 2104 memcpy(buf, &ehci_endpd, l); 2105 break; 2106 case UDESC_STRING: 2107 #define sd ((usb_string_descriptor_t *)buf) 2108 switch (value & 0xff) { 2109 case 0: /* Language table */ 2110 totlen = usb_makelangtbl(sd, len); 2111 break; 2112 case 1: /* Vendor */ 2113 totlen = usb_makestrdesc(sd, len, 2114 sc->sc_vendor); 2115 break; 2116 case 2: /* Product */ 2117 totlen = usb_makestrdesc(sd, len, 2118 "EHCI root hub"); 2119 break; 2120 } 2121 #undef sd 2122 break; 2123 default: 2124 err = USBD_IOERROR; 2125 goto ret; 2126 } 2127 break; 2128 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2129 if (len > 0) { 2130 *(u_int8_t *)buf = 0; 2131 totlen = 1; 2132 } 2133 break; 2134 case C(UR_GET_STATUS, UT_READ_DEVICE): 2135 if (len > 1) { 2136 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2137 totlen = 2; 2138 } 2139 break; 2140 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2141 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2142 if (len > 1) { 2143 USETW(((usb_status_t *)buf)->wStatus, 0); 2144 totlen = 2; 2145 } 2146 break; 2147 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2148 if (value >= USB_MAX_DEVICES) { 2149 err = USBD_IOERROR; 2150 goto ret; 2151 } 2152 sc->sc_addr = value; 2153 break; 2154 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2155 if (value != 0 && value != 1) { 2156 err = USBD_IOERROR; 2157 goto ret; 2158 } 2159 sc->sc_conf = value; 2160 break; 2161 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2162 break; 2163 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2164 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2165 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2166 err = USBD_IOERROR; 2167 goto ret; 2168 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2169 break; 2170 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2171 break; 2172 /* Hub requests */ 2173 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2174 break; 2175 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2176 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2177 "port=%d feature=%d\n", 2178 index, value)); 2179 if (index < 1 || index > sc->sc_noport) { 2180 err = USBD_IOERROR; 2181 goto ret; 2182 } 2183 port = EHCI_PORTSC(index); 2184 v = EOREAD4(sc, port); 2185 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2186 v &= ~EHCI_PS_CLEAR; 2187 switch(value) { 2188 case UHF_PORT_ENABLE: 2189 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2190 break; 2191 case UHF_PORT_SUSPEND: 2192 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2193 break; 2194 v &= ~EHCI_PS_SUSP; 2195 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2196 /* see USB2 spec ch. 7.1.7.7 */ 2197 usb_delay_ms(&sc->sc_bus, 20); 2198 EOWRITE4(sc, port, v); 2199 usb_delay_ms(&sc->sc_bus, 2); 2200 #ifdef DEBUG 2201 v = EOREAD4(sc, port); 2202 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2203 printf("ehci: resume failed: %x\n", v); 2204 #endif 2205 break; 2206 case UHF_PORT_POWER: 2207 if (sc->sc_hasppc) 2208 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2209 break; 2210 case UHF_PORT_TEST: 2211 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2212 "%d\n", index)); 2213 break; 2214 case UHF_PORT_INDICATOR: 2215 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2216 "%d\n", index)); 2217 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2218 break; 2219 case UHF_C_PORT_CONNECTION: 2220 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2221 break; 2222 case UHF_C_PORT_ENABLE: 2223 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2224 break; 2225 case UHF_C_PORT_SUSPEND: 2226 /* how? */ 2227 break; 2228 case UHF_C_PORT_OVER_CURRENT: 2229 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2230 break; 2231 case UHF_C_PORT_RESET: 2232 sc->sc_isreset[index] = 0; 2233 break; 2234 default: 2235 err = USBD_IOERROR; 2236 goto ret; 2237 } 2238 #if 0 2239 switch(value) { 2240 case UHF_C_PORT_CONNECTION: 2241 case UHF_C_PORT_ENABLE: 2242 case UHF_C_PORT_SUSPEND: 2243 case UHF_C_PORT_OVER_CURRENT: 2244 case UHF_C_PORT_RESET: 2245 default: 2246 break; 2247 } 2248 #endif 2249 break; 2250 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2251 if (len == 0) 2252 break; 2253 if ((value & 0xff) != 0) { 2254 err = USBD_IOERROR; 2255 goto ret; 2256 } 2257 hubd = ehci_hubd; 2258 hubd.bNbrPorts = sc->sc_noport; 2259 v = EOREAD4(sc, EHCI_HCSPARAMS); 2260 USETW(hubd.wHubCharacteristics, 2261 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2262 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2263 ? UHD_PORT_IND : 0); 2264 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2265 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2266 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2267 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2268 l = min(len, hubd.bDescLength); 2269 totlen = l; 2270 memcpy(buf, &hubd, l); 2271 break; 2272 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2273 if (len != 4) { 2274 err = USBD_IOERROR; 2275 goto ret; 2276 } 2277 memset(buf, 0, len); /* ? XXX */ 2278 totlen = len; 2279 break; 2280 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2281 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2282 index)); 2283 if (index < 1 || index > sc->sc_noport) { 2284 err = USBD_IOERROR; 2285 goto ret; 2286 } 2287 if (len != 4) { 2288 err = USBD_IOERROR; 2289 goto ret; 2290 } 2291 v = EOREAD4(sc, EHCI_PORTSC(index)); 2292 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2293 2294 i = UPS_HIGH_SPEED; 2295 #if 0 2296 if (sc->sc_flags & EHCIF_ETTF) { 2297 /* 2298 * If we are doing embedded transaction translation, 2299 * then directly attached LS/FS devices are reset by 2300 * the EHCI controller itself. PSPD is encoded 2301 * the same way as in USBSTATUS. 2302 */ 2303 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2304 } 2305 #endif 2306 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2307 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2308 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2309 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2310 if (v & EHCI_PS_PR) i |= UPS_RESET; 2311 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2312 if (sc->sc_vendor_port_status) 2313 i = sc->sc_vendor_port_status(sc, v, i); 2314 USETW(ps.wPortStatus, i); 2315 i = 0; 2316 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2317 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2318 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2319 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2320 USETW(ps.wPortChange, i); 2321 l = min(len, sizeof ps); 2322 memcpy(buf, &ps, l); 2323 totlen = l; 2324 break; 2325 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2326 err = USBD_IOERROR; 2327 goto ret; 2328 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2329 break; 2330 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2331 if (index < 1 || index > sc->sc_noport) { 2332 err = USBD_IOERROR; 2333 goto ret; 2334 } 2335 port = EHCI_PORTSC(index); 2336 v = EOREAD4(sc, port); 2337 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2338 v &= ~EHCI_PS_CLEAR; 2339 switch(value) { 2340 case UHF_PORT_ENABLE: 2341 EOWRITE4(sc, port, v | EHCI_PS_PE); 2342 break; 2343 case UHF_PORT_SUSPEND: 2344 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2345 break; 2346 case UHF_PORT_RESET: 2347 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2348 index)); 2349 if (EHCI_PS_IS_LOWSPEED(v) 2350 && sc->sc_ncomp > 0 2351 && !(sc->sc_flags & EHCIF_ETTF)) { 2352 /* 2353 * Low speed device on non-ETTF controller or 2354 * unaccompanied controller, give up ownership. 2355 */ 2356 ehci_disown(sc, index, 1); 2357 break; 2358 } 2359 /* Start reset sequence. */ 2360 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2361 EOWRITE4(sc, port, v | EHCI_PS_PR); 2362 /* Wait for reset to complete. */ 2363 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2364 if (sc->sc_dying) { 2365 err = USBD_IOERROR; 2366 goto ret; 2367 } 2368 /* 2369 * An embedded transaction translater will automatically 2370 * terminate the reset sequence so there's no need to 2371 * it. 2372 */ 2373 v = EOREAD4(sc, port); 2374 if (v & EHCI_PS_PR) { 2375 /* Terminate reset sequence. */ 2376 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2377 /* Wait for HC to complete reset. */ 2378 usb_delay_ms(&sc->sc_bus, 2379 EHCI_PORT_RESET_COMPLETE); 2380 if (sc->sc_dying) { 2381 err = USBD_IOERROR; 2382 goto ret; 2383 } 2384 } 2385 2386 v = EOREAD4(sc, port); 2387 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2388 if (v & EHCI_PS_PR) { 2389 printf("%s: port reset timeout\n", 2390 device_xname(sc->sc_dev)); 2391 return (USBD_TIMEOUT); 2392 } 2393 if (!(v & EHCI_PS_PE)) { 2394 /* Not a high speed device, give up ownership.*/ 2395 ehci_disown(sc, index, 0); 2396 break; 2397 } 2398 sc->sc_isreset[index] = 1; 2399 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2400 index, v)); 2401 break; 2402 case UHF_PORT_POWER: 2403 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2404 "%d (has PPC = %d)\n", index, 2405 sc->sc_hasppc)); 2406 if (sc->sc_hasppc) 2407 EOWRITE4(sc, port, v | EHCI_PS_PP); 2408 break; 2409 case UHF_PORT_TEST: 2410 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2411 "%d\n", index)); 2412 break; 2413 case UHF_PORT_INDICATOR: 2414 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2415 "%d\n", index)); 2416 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2417 break; 2418 default: 2419 err = USBD_IOERROR; 2420 goto ret; 2421 } 2422 break; 2423 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2424 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2425 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2426 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2427 break; 2428 default: 2429 err = USBD_IOERROR; 2430 goto ret; 2431 } 2432 xfer->actlen = totlen; 2433 err = USBD_NORMAL_COMPLETION; 2434 ret: 2435 xfer->status = err; 2436 s = splusb(); 2437 usb_transfer_complete(xfer); 2438 splx(s); 2439 return (USBD_IN_PROGRESS); 2440 } 2441 2442 Static void 2443 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2444 { 2445 int port; 2446 u_int32_t v; 2447 2448 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2449 #ifdef DIAGNOSTIC 2450 if (sc->sc_npcomp != 0) { 2451 int i = (index-1) / sc->sc_npcomp; 2452 if (i >= sc->sc_ncomp) 2453 printf("%s: strange port\n", 2454 device_xname(sc->sc_dev)); 2455 else 2456 printf("%s: handing over %s speed device on " 2457 "port %d to %s\n", 2458 device_xname(sc->sc_dev), 2459 lowspeed ? "low" : "full", 2460 index, device_xname(sc->sc_comps[i])); 2461 } else { 2462 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2463 } 2464 #endif 2465 port = EHCI_PORTSC(index); 2466 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2467 EOWRITE4(sc, port, v | EHCI_PS_PO); 2468 } 2469 2470 /* Abort a root control request. */ 2471 Static void 2472 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2473 { 2474 /* Nothing to do, all transfers are synchronous. */ 2475 } 2476 2477 /* Close the root pipe. */ 2478 Static void 2479 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2480 { 2481 DPRINTF(("ehci_root_ctrl_close\n")); 2482 /* Nothing to do. */ 2483 } 2484 2485 Static void 2486 ehci_root_intr_done(usbd_xfer_handle xfer) 2487 { 2488 xfer->hcpriv = NULL; 2489 } 2490 2491 Static usbd_status 2492 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2493 { 2494 usbd_status err; 2495 2496 /* Insert last in queue. */ 2497 err = usb_insert_transfer(xfer); 2498 if (err) 2499 return (err); 2500 2501 /* Pipe isn't running, start first */ 2502 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2503 } 2504 2505 Static usbd_status 2506 ehci_root_intr_start(usbd_xfer_handle xfer) 2507 { 2508 usbd_pipe_handle pipe = xfer->pipe; 2509 ehci_softc_t *sc = pipe->device->bus->hci_private; 2510 2511 if (sc->sc_dying) 2512 return (USBD_IOERROR); 2513 2514 sc->sc_intrxfer = xfer; 2515 2516 return (USBD_IN_PROGRESS); 2517 } 2518 2519 /* Abort a root interrupt request. */ 2520 Static void 2521 ehci_root_intr_abort(usbd_xfer_handle xfer) 2522 { 2523 int s; 2524 2525 if (xfer->pipe->intrxfer == xfer) { 2526 DPRINTF(("ehci_root_intr_abort: remove\n")); 2527 xfer->pipe->intrxfer = NULL; 2528 } 2529 xfer->status = USBD_CANCELLED; 2530 s = splusb(); 2531 usb_transfer_complete(xfer); 2532 splx(s); 2533 } 2534 2535 /* Close the root pipe. */ 2536 Static void 2537 ehci_root_intr_close(usbd_pipe_handle pipe) 2538 { 2539 ehci_softc_t *sc = pipe->device->bus->hci_private; 2540 2541 DPRINTF(("ehci_root_intr_close\n")); 2542 2543 sc->sc_intrxfer = NULL; 2544 } 2545 2546 Static void 2547 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2548 { 2549 xfer->hcpriv = NULL; 2550 } 2551 2552 /************************/ 2553 2554 Static ehci_soft_qh_t * 2555 ehci_alloc_sqh(ehci_softc_t *sc) 2556 { 2557 ehci_soft_qh_t *sqh; 2558 usbd_status err; 2559 int i, offs; 2560 usb_dma_t dma; 2561 2562 if (sc->sc_freeqhs == NULL) { 2563 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2564 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2565 EHCI_PAGE_SIZE, &dma); 2566 #ifdef EHCI_DEBUG 2567 if (err) 2568 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2569 #endif 2570 if (err) 2571 return (NULL); 2572 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2573 offs = i * EHCI_SQH_SIZE; 2574 sqh = KERNADDR(&dma, offs); 2575 sqh->physaddr = DMAADDR(&dma, offs); 2576 sqh->dma = dma; 2577 sqh->offs = offs; 2578 sqh->next = sc->sc_freeqhs; 2579 sc->sc_freeqhs = sqh; 2580 } 2581 } 2582 sqh = sc->sc_freeqhs; 2583 sc->sc_freeqhs = sqh->next; 2584 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2585 sqh->next = NULL; 2586 return (sqh); 2587 } 2588 2589 Static void 2590 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2591 { 2592 sqh->next = sc->sc_freeqhs; 2593 sc->sc_freeqhs = sqh; 2594 } 2595 2596 Static ehci_soft_qtd_t * 2597 ehci_alloc_sqtd(ehci_softc_t *sc) 2598 { 2599 ehci_soft_qtd_t *sqtd; 2600 usbd_status err; 2601 int i, offs; 2602 usb_dma_t dma; 2603 int s; 2604 2605 if (sc->sc_freeqtds == NULL) { 2606 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2607 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2608 EHCI_PAGE_SIZE, &dma); 2609 #ifdef EHCI_DEBUG 2610 if (err) 2611 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2612 #endif 2613 if (err) 2614 return (NULL); 2615 s = splusb(); 2616 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2617 offs = i * EHCI_SQTD_SIZE; 2618 sqtd = KERNADDR(&dma, offs); 2619 sqtd->physaddr = DMAADDR(&dma, offs); 2620 sqtd->dma = dma; 2621 sqtd->offs = offs; 2622 sqtd->nextqtd = sc->sc_freeqtds; 2623 sc->sc_freeqtds = sqtd; 2624 } 2625 splx(s); 2626 } 2627 2628 s = splusb(); 2629 sqtd = sc->sc_freeqtds; 2630 sc->sc_freeqtds = sqtd->nextqtd; 2631 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2632 sqtd->nextqtd = NULL; 2633 sqtd->xfer = NULL; 2634 splx(s); 2635 2636 return (sqtd); 2637 } 2638 2639 Static void 2640 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2641 { 2642 int s; 2643 2644 s = splusb(); 2645 sqtd->nextqtd = sc->sc_freeqtds; 2646 sc->sc_freeqtds = sqtd; 2647 splx(s); 2648 } 2649 2650 Static usbd_status 2651 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2652 int alen, int rd, usbd_xfer_handle xfer, 2653 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2654 { 2655 ehci_soft_qtd_t *next, *cur; 2656 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2657 u_int32_t qtdstatus; 2658 int len, curlen, mps; 2659 int i, tog; 2660 usb_dma_t *dma = &xfer->dmabuf; 2661 u_int16_t flags = xfer->flags; 2662 2663 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2664 2665 len = alen; 2666 dataphys = DMAADDR(dma, 0); 2667 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2668 qtdstatus = EHCI_QTD_ACTIVE | 2669 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2670 EHCI_QTD_SET_CERR(3) 2671 /* IOC set below */ 2672 /* BYTES set below */ 2673 ; 2674 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2675 tog = epipe->nexttoggle; 2676 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2677 2678 cur = ehci_alloc_sqtd(sc); 2679 *sp = cur; 2680 if (cur == NULL) 2681 goto nomem; 2682 2683 usb_syncmem(dma, 0, alen, 2684 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2685 for (;;) { 2686 dataphyspage = EHCI_PAGE(dataphys); 2687 /* The EHCI hardware can handle at most 5 pages. */ 2688 if (dataphyslastpage - dataphyspage < 2689 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2690 /* we can handle it in this QTD */ 2691 curlen = len; 2692 } else { 2693 /* must use multiple TDs, fill as much as possible. */ 2694 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2695 EHCI_PAGE_OFFSET(dataphys); 2696 #ifdef DIAGNOSTIC 2697 if (curlen > len) { 2698 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2699 "len=0x%x offs=0x%x\n", curlen, len, 2700 EHCI_PAGE_OFFSET(dataphys)); 2701 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2702 dataphyslastpage, dataphyspage, 2703 dataphys); 2704 curlen = len; 2705 } 2706 #endif 2707 /* the length must be a multiple of the max size */ 2708 curlen -= curlen % mps; 2709 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2710 "curlen=%d\n", curlen)); 2711 #ifdef DIAGNOSTIC 2712 if (curlen == 0) 2713 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2714 #endif 2715 } 2716 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2717 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2718 dataphys, dataphyslastpage, 2719 len, curlen)); 2720 len -= curlen; 2721 2722 /* 2723 * Allocate another transfer if there's more data left, 2724 * or if force last short transfer flag is set and we're 2725 * allocating a multiple of the max packet size. 2726 */ 2727 if (len != 0 || 2728 ((curlen % mps) == 0 && !rd && curlen != 0 && 2729 (flags & USBD_FORCE_SHORT_XFER))) { 2730 next = ehci_alloc_sqtd(sc); 2731 if (next == NULL) 2732 goto nomem; 2733 nextphys = htole32(next->physaddr); 2734 } else { 2735 next = NULL; 2736 nextphys = EHCI_NULL; 2737 } 2738 2739 for (i = 0; i * EHCI_PAGE_SIZE < 2740 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2741 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2742 if (i != 0) /* use offset only in first buffer */ 2743 a = EHCI_PAGE(a); 2744 cur->qtd.qtd_buffer[i] = htole32(a); 2745 cur->qtd.qtd_buffer_hi[i] = 0; 2746 #ifdef DIAGNOSTIC 2747 if (i >= EHCI_QTD_NBUFFERS) { 2748 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2749 goto nomem; 2750 } 2751 #endif 2752 } 2753 cur->nextqtd = next; 2754 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2755 cur->qtd.qtd_status = 2756 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2757 cur->xfer = xfer; 2758 cur->len = curlen; 2759 2760 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2761 dataphys, dataphys + curlen)); 2762 /* adjust the toggle based on the number of packets in this 2763 qtd */ 2764 if (((curlen + mps - 1) / mps) & 1) { 2765 tog ^= 1; 2766 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2767 } 2768 if (next == NULL) 2769 break; 2770 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2771 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2772 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2773 if (len) 2774 dataphys += curlen; 2775 cur = next; 2776 } 2777 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2778 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2779 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2780 *ep = cur; 2781 epipe->nexttoggle = tog; 2782 2783 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2784 *sp, *ep)); 2785 2786 return (USBD_NORMAL_COMPLETION); 2787 2788 nomem: 2789 /* XXX free chain */ 2790 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2791 return (USBD_NOMEM); 2792 } 2793 2794 Static void 2795 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2796 ehci_soft_qtd_t *sqtdend) 2797 { 2798 ehci_soft_qtd_t *p; 2799 int i; 2800 2801 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2802 sqtd, sqtdend)); 2803 2804 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2805 p = sqtd->nextqtd; 2806 ehci_free_sqtd(sc, sqtd); 2807 } 2808 } 2809 2810 Static ehci_soft_itd_t * 2811 ehci_alloc_itd(ehci_softc_t *sc) 2812 { 2813 struct ehci_soft_itd *itd, *freeitd; 2814 usbd_status err; 2815 int i, s, offs, frindex, previndex; 2816 usb_dma_t dma; 2817 2818 s = splusb(); 2819 2820 /* Find an itd that wasn't freed this frame or last frame. This can 2821 * discard itds that were freed before frindex wrapped around 2822 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2823 * interrupt and fiddling with list when that happens */ 2824 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2825 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2826 2827 freeitd = NULL; 2828 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2829 if (itd == NULL) 2830 break; 2831 if (itd->slot != frindex && itd->slot != previndex) { 2832 freeitd = itd; 2833 break; 2834 } 2835 } 2836 2837 if (freeitd == NULL) { 2838 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2839 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2840 EHCI_PAGE_SIZE, &dma); 2841 2842 if (err) { 2843 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2844 return NULL; 2845 } 2846 2847 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2848 offs = i * EHCI_ITD_SIZE; 2849 itd = KERNADDR(&dma, offs); 2850 itd->physaddr = DMAADDR(&dma, offs); 2851 itd->dma = dma; 2852 itd->offs = offs; 2853 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2854 } 2855 freeitd = LIST_FIRST(&sc->sc_freeitds); 2856 } 2857 2858 itd = freeitd; 2859 LIST_REMOVE(itd, u.free_list); 2860 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2861 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2862 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2863 BUS_DMASYNC_PREREAD); 2864 2865 itd->u.frame_list.next = NULL; 2866 itd->u.frame_list.prev = NULL; 2867 itd->xfer_next = NULL; 2868 itd->slot = 0; 2869 splx(s); 2870 2871 return itd; 2872 } 2873 2874 Static void 2875 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2876 { 2877 int s; 2878 2879 s = splusb(); 2880 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2881 splx(s); 2882 } 2883 2884 /****************/ 2885 2886 /* 2887 * Close a reqular pipe. 2888 * Assumes that there are no pending transactions. 2889 */ 2890 Static void 2891 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2892 { 2893 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2894 ehci_softc_t *sc = pipe->device->bus->hci_private; 2895 ehci_soft_qh_t *sqh = epipe->sqh; 2896 int s; 2897 2898 s = splusb(); 2899 ehci_rem_qh(sc, sqh, head); 2900 splx(s); 2901 ehci_free_sqh(sc, epipe->sqh); 2902 } 2903 2904 /* 2905 * Abort a device request. 2906 * If this routine is called at splusb() it guarantees that the request 2907 * will be removed from the hardware scheduling and that the callback 2908 * for it will be called with USBD_CANCELLED status. 2909 * It's impossible to guarantee that the requested transfer will not 2910 * have happened since the hardware runs concurrently. 2911 * If the transaction has already happened we rely on the ordinary 2912 * interrupt processing to process it. 2913 * XXX This is most probably wrong. 2914 */ 2915 Static void 2916 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2917 { 2918 #define exfer EXFER(xfer) 2919 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2920 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2921 ehci_soft_qh_t *sqh = epipe->sqh; 2922 ehci_soft_qtd_t *sqtd; 2923 ehci_physaddr_t cur; 2924 u_int32_t qhstatus; 2925 int s; 2926 int hit; 2927 int wake; 2928 2929 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2930 2931 if (sc->sc_dying) { 2932 /* If we're dying, just do the software part. */ 2933 s = splusb(); 2934 xfer->status = status; /* make software ignore it */ 2935 callout_stop(&xfer->timeout_handle); 2936 usb_transfer_complete(xfer); 2937 splx(s); 2938 return; 2939 } 2940 2941 if (xfer->device->bus->intr_context) 2942 panic("ehci_abort_xfer: not in process context"); 2943 2944 /* 2945 * If an abort is already in progress then just wait for it to 2946 * complete and return. 2947 */ 2948 if (xfer->hcflags & UXFER_ABORTING) { 2949 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2950 #ifdef DIAGNOSTIC 2951 if (status == USBD_TIMEOUT) 2952 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2953 #endif 2954 /* Override the status which might be USBD_TIMEOUT. */ 2955 xfer->status = status; 2956 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2957 xfer->hcflags |= UXFER_ABORTWAIT; 2958 while (xfer->hcflags & UXFER_ABORTING) 2959 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2960 return; 2961 } 2962 xfer->hcflags |= UXFER_ABORTING; 2963 2964 /* 2965 * Step 1: Make interrupt routine and hardware ignore xfer. 2966 */ 2967 s = splusb(); 2968 xfer->status = status; /* make software ignore it */ 2969 callout_stop(&xfer->timeout_handle); 2970 2971 usb_syncmem(&sqh->dma, 2972 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2973 sizeof(sqh->qh.qh_qtd.qtd_status), 2974 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2975 qhstatus = sqh->qh.qh_qtd.qtd_status; 2976 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2977 usb_syncmem(&sqh->dma, 2978 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2979 sizeof(sqh->qh.qh_qtd.qtd_status), 2980 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2981 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2982 usb_syncmem(&sqtd->dma, 2983 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2984 sizeof(sqtd->qtd.qtd_status), 2985 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2986 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2987 usb_syncmem(&sqtd->dma, 2988 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2989 sizeof(sqtd->qtd.qtd_status), 2990 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2991 if (sqtd == exfer->sqtdend) 2992 break; 2993 } 2994 splx(s); 2995 2996 /* 2997 * Step 2: Wait until we know hardware has finished any possible 2998 * use of the xfer. Also make sure the soft interrupt routine 2999 * has run. 3000 */ 3001 ehci_sync_hc(sc); 3002 s = splusb(); 3003 #ifdef USB_USE_SOFTINTR 3004 sc->sc_softwake = 1; 3005 #endif /* USB_USE_SOFTINTR */ 3006 usb_schedsoftintr(&sc->sc_bus); 3007 #ifdef USB_USE_SOFTINTR 3008 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3009 #endif /* USB_USE_SOFTINTR */ 3010 splx(s); 3011 3012 /* 3013 * Step 3: Remove any vestiges of the xfer from the hardware. 3014 * The complication here is that the hardware may have executed 3015 * beyond the xfer we're trying to abort. So as we're scanning 3016 * the TDs of this xfer we check if the hardware points to 3017 * any of them. 3018 */ 3019 s = splusb(); /* XXX why? */ 3020 3021 usb_syncmem(&sqh->dma, 3022 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3023 sizeof(sqh->qh.qh_curqtd), 3024 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3025 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3026 hit = 0; 3027 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3028 hit |= cur == sqtd->physaddr; 3029 if (sqtd == exfer->sqtdend) 3030 break; 3031 } 3032 sqtd = sqtd->nextqtd; 3033 /* Zap curqtd register if hardware pointed inside the xfer. */ 3034 if (hit && sqtd != NULL) { 3035 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3036 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3037 usb_syncmem(&sqh->dma, 3038 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3039 sizeof(sqh->qh.qh_curqtd), 3040 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3041 sqh->qh.qh_qtd.qtd_status = qhstatus; 3042 usb_syncmem(&sqh->dma, 3043 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3044 sizeof(sqh->qh.qh_qtd.qtd_status), 3045 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3046 } else { 3047 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3048 } 3049 3050 /* 3051 * Step 4: Execute callback. 3052 */ 3053 #ifdef DIAGNOSTIC 3054 exfer->isdone = 1; 3055 #endif 3056 wake = xfer->hcflags & UXFER_ABORTWAIT; 3057 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3058 usb_transfer_complete(xfer); 3059 if (wake) 3060 wakeup(&xfer->hcflags); 3061 3062 splx(s); 3063 #undef exfer 3064 } 3065 3066 Static void 3067 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3068 { 3069 ehci_isoc_trans_t trans_status; 3070 struct ehci_pipe *epipe; 3071 struct ehci_xfer *exfer; 3072 ehci_softc_t *sc; 3073 struct ehci_soft_itd *itd; 3074 int s, i, wake; 3075 3076 epipe = (struct ehci_pipe *) xfer->pipe; 3077 exfer = EXFER(xfer); 3078 sc = epipe->pipe.device->bus->hci_private; 3079 3080 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3081 3082 if (sc->sc_dying) { 3083 s = splusb(); 3084 xfer->status = status; 3085 callout_stop(&xfer->timeout_handle); 3086 usb_transfer_complete(xfer); 3087 splx(s); 3088 return; 3089 } 3090 3091 if (xfer->hcflags & UXFER_ABORTING) { 3092 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3093 3094 #ifdef DIAGNOSTIC 3095 if (status == USBD_TIMEOUT) 3096 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3097 #endif 3098 3099 xfer->status = status; 3100 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3101 xfer->hcflags |= UXFER_ABORTWAIT; 3102 while (xfer->hcflags & UXFER_ABORTING) 3103 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0); 3104 return; 3105 } 3106 xfer->hcflags |= UXFER_ABORTING; 3107 3108 xfer->status = status; 3109 callout_stop(&xfer->timeout_handle); 3110 3111 s = splusb(); 3112 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3113 usb_syncmem(&itd->dma, 3114 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3115 sizeof(itd->itd.itd_ctl), 3116 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3117 3118 for (i = 0; i < 8; i++) { 3119 trans_status = le32toh(itd->itd.itd_ctl[i]); 3120 trans_status &= ~EHCI_ITD_ACTIVE; 3121 itd->itd.itd_ctl[i] = htole32(trans_status); 3122 } 3123 3124 usb_syncmem(&itd->dma, 3125 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3126 sizeof(itd->itd.itd_ctl), 3127 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3128 } 3129 splx(s); 3130 3131 s = splusb(); 3132 #ifdef USB_USE_SOFTINTR 3133 sc->sc_softwake = 1; 3134 #endif /* USB_USE_SOFTINTR */ 3135 usb_schedsoftintr(&sc->sc_bus); 3136 #ifdef USB_USE_SOFTINTR 3137 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3138 #endif /* USB_USE_SOFTINTR */ 3139 splx(s); 3140 3141 #ifdef DIAGNOSTIC 3142 exfer->isdone = 1; 3143 #endif 3144 wake = xfer->hcflags & UXFER_ABORTWAIT; 3145 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3146 usb_transfer_complete(xfer); 3147 if (wake) 3148 wakeup(&xfer->hcflags); 3149 3150 return; 3151 } 3152 3153 Static void 3154 ehci_timeout(void *addr) 3155 { 3156 struct ehci_xfer *exfer = addr; 3157 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3158 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3159 3160 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3161 #ifdef EHCI_DEBUG 3162 if (ehcidebug > 1) 3163 usbd_dump_pipe(exfer->xfer.pipe); 3164 #endif 3165 3166 if (sc->sc_dying) { 3167 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3168 return; 3169 } 3170 3171 /* Execute the abort in a process context. */ 3172 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3173 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3174 USB_TASKQ_HC); 3175 } 3176 3177 Static void 3178 ehci_timeout_task(void *addr) 3179 { 3180 usbd_xfer_handle xfer = addr; 3181 int s; 3182 3183 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3184 3185 s = splusb(); 3186 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3187 splx(s); 3188 } 3189 3190 /************************/ 3191 3192 Static usbd_status 3193 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3194 { 3195 usbd_status err; 3196 3197 /* Insert last in queue. */ 3198 err = usb_insert_transfer(xfer); 3199 if (err) 3200 return (err); 3201 3202 /* Pipe isn't running, start first */ 3203 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3204 } 3205 3206 Static usbd_status 3207 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3208 { 3209 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3210 usbd_status err; 3211 3212 if (sc->sc_dying) 3213 return (USBD_IOERROR); 3214 3215 #ifdef DIAGNOSTIC 3216 if (!(xfer->rqflags & URQ_REQUEST)) { 3217 /* XXX panic */ 3218 printf("ehci_device_ctrl_transfer: not a request\n"); 3219 return (USBD_INVAL); 3220 } 3221 #endif 3222 3223 err = ehci_device_request(xfer); 3224 if (err) 3225 return (err); 3226 3227 if (sc->sc_bus.use_polling) 3228 ehci_waitintr(sc, xfer); 3229 return (USBD_IN_PROGRESS); 3230 } 3231 3232 Static void 3233 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3234 { 3235 struct ehci_xfer *ex = EXFER(xfer); 3236 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3237 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3238 usb_device_request_t *req = &xfer->request; 3239 int len = UGETW(req->wLength); 3240 int rd = req->bmRequestType & UT_READ; 3241 3242 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3243 3244 #ifdef DIAGNOSTIC 3245 if (!(xfer->rqflags & URQ_REQUEST)) { 3246 panic("ehci_ctrl_done: not a request"); 3247 } 3248 #endif 3249 3250 mutex_enter(&sc->sc_intrhead_lock); 3251 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3252 ehci_del_intr_list(sc, ex); /* remove from active list */ 3253 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3254 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3255 BUS_DMASYNC_POSTWRITE); 3256 if (len) 3257 usb_syncmem(&xfer->dmabuf, 0, len, 3258 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3259 } 3260 mutex_exit(&sc->sc_intrhead_lock); 3261 3262 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3263 } 3264 3265 /* Abort a device control request. */ 3266 Static void 3267 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3268 { 3269 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3270 ehci_abort_xfer(xfer, USBD_CANCELLED); 3271 } 3272 3273 /* Close a device control pipe. */ 3274 Static void 3275 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3276 { 3277 ehci_softc_t *sc = pipe->device->bus->hci_private; 3278 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3279 3280 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3281 ehci_close_pipe(pipe, sc->sc_async_head); 3282 } 3283 3284 Static usbd_status 3285 ehci_device_request(usbd_xfer_handle xfer) 3286 { 3287 #define exfer EXFER(xfer) 3288 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3289 usb_device_request_t *req = &xfer->request; 3290 usbd_device_handle dev = epipe->pipe.device; 3291 ehci_softc_t *sc = dev->bus->hci_private; 3292 int addr = dev->address; 3293 ehci_soft_qtd_t *setup, *stat, *next; 3294 ehci_soft_qh_t *sqh; 3295 int isread; 3296 int len; 3297 usbd_status err; 3298 int s; 3299 3300 isread = req->bmRequestType & UT_READ; 3301 len = UGETW(req->wLength); 3302 3303 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3304 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3305 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3306 UGETW(req->wIndex), len, addr, 3307 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3308 3309 setup = ehci_alloc_sqtd(sc); 3310 if (setup == NULL) { 3311 err = USBD_NOMEM; 3312 goto bad1; 3313 } 3314 stat = ehci_alloc_sqtd(sc); 3315 if (stat == NULL) { 3316 err = USBD_NOMEM; 3317 goto bad2; 3318 } 3319 3320 sqh = epipe->sqh; 3321 epipe->u.ctl.length = len; 3322 3323 /* Update device address and length since they may have changed 3324 during the setup of the control pipe in usbd_new_device(). */ 3325 /* XXX This only needs to be done once, but it's too early in open. */ 3326 /* XXXX Should not touch ED here! */ 3327 sqh->qh.qh_endp = 3328 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3329 htole32( 3330 EHCI_QH_SET_ADDR(addr) | 3331 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3332 ); 3333 3334 /* Set up data transaction */ 3335 if (len != 0) { 3336 ehci_soft_qtd_t *end; 3337 3338 /* Start toggle at 1. */ 3339 epipe->nexttoggle = 1; 3340 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3341 &next, &end); 3342 if (err) 3343 goto bad3; 3344 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3345 end->nextqtd = stat; 3346 end->qtd.qtd_next = 3347 end->qtd.qtd_altnext = htole32(stat->physaddr); 3348 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3349 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3350 } else { 3351 next = stat; 3352 } 3353 3354 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3355 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3356 3357 /* Clear toggle */ 3358 setup->qtd.qtd_status = htole32( 3359 EHCI_QTD_ACTIVE | 3360 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3361 EHCI_QTD_SET_CERR(3) | 3362 EHCI_QTD_SET_TOGGLE(0) | 3363 EHCI_QTD_SET_BYTES(sizeof *req) 3364 ); 3365 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3366 setup->qtd.qtd_buffer_hi[0] = 0; 3367 setup->nextqtd = next; 3368 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3369 setup->xfer = xfer; 3370 setup->len = sizeof *req; 3371 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3372 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3373 3374 stat->qtd.qtd_status = htole32( 3375 EHCI_QTD_ACTIVE | 3376 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3377 EHCI_QTD_SET_CERR(3) | 3378 EHCI_QTD_SET_TOGGLE(1) | 3379 EHCI_QTD_IOC 3380 ); 3381 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3382 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3383 stat->nextqtd = NULL; 3384 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3385 stat->xfer = xfer; 3386 stat->len = 0; 3387 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3388 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3389 3390 #ifdef EHCI_DEBUG 3391 if (ehcidebug > 5) { 3392 DPRINTF(("ehci_device_request:\n")); 3393 ehci_dump_sqh(sqh); 3394 ehci_dump_sqtds(setup); 3395 } 3396 #endif 3397 3398 exfer->sqtdstart = setup; 3399 exfer->sqtdend = stat; 3400 #ifdef DIAGNOSTIC 3401 if (!exfer->isdone) { 3402 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3403 } 3404 exfer->isdone = 0; 3405 #endif 3406 3407 /* Insert qTD in QH list. */ 3408 s = splusb(); 3409 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3410 if (xfer->timeout && !sc->sc_bus.use_polling) { 3411 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3412 (ehci_timeout), (xfer)); 3413 } 3414 mutex_enter(&sc->sc_intrhead_lock); 3415 ehci_add_intr_list(sc, exfer); 3416 mutex_exit(&sc->sc_intrhead_lock); 3417 xfer->status = USBD_IN_PROGRESS; 3418 splx(s); 3419 3420 #ifdef EHCI_DEBUG 3421 if (ehcidebug > 10) { 3422 DPRINTF(("ehci_device_request: status=%x\n", 3423 EOREAD4(sc, EHCI_USBSTS))); 3424 delay(10000); 3425 ehci_dump_regs(sc); 3426 ehci_dump_sqh(sc->sc_async_head); 3427 ehci_dump_sqh(sqh); 3428 ehci_dump_sqtds(setup); 3429 } 3430 #endif 3431 3432 return (USBD_NORMAL_COMPLETION); 3433 3434 bad3: 3435 ehci_free_sqtd(sc, stat); 3436 bad2: 3437 ehci_free_sqtd(sc, setup); 3438 bad1: 3439 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3440 xfer->status = err; 3441 usb_transfer_complete(xfer); 3442 return (err); 3443 #undef exfer 3444 } 3445 3446 /* 3447 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3448 * qTD status, or miss signalling occasionally under heavy load. If the host 3449 * machine is too fast, we we can miss transaction completion - when we scan 3450 * the active list the transaction still seems to be active. This generally 3451 * exhibits itself as a umass stall that never recovers. 3452 * 3453 * We work around this behaviour by setting up this callback after any softintr 3454 * that completes with transactions still pending, giving us another chance to 3455 * check for completion after the writeback has taken place. 3456 */ 3457 Static void 3458 ehci_intrlist_timeout(void *arg) 3459 { 3460 ehci_softc_t *sc = arg; 3461 int s = splusb(); 3462 3463 DPRINTF(("ehci_intrlist_timeout\n")); 3464 usb_schedsoftintr(&sc->sc_bus); 3465 3466 splx(s); 3467 } 3468 3469 /************************/ 3470 3471 Static usbd_status 3472 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3473 { 3474 usbd_status err; 3475 3476 /* Insert last in queue. */ 3477 err = usb_insert_transfer(xfer); 3478 if (err) 3479 return (err); 3480 3481 /* Pipe isn't running, start first */ 3482 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3483 } 3484 3485 Static usbd_status 3486 ehci_device_bulk_start(usbd_xfer_handle xfer) 3487 { 3488 #define exfer EXFER(xfer) 3489 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3490 usbd_device_handle dev = epipe->pipe.device; 3491 ehci_softc_t *sc = dev->bus->hci_private; 3492 ehci_soft_qtd_t *data, *dataend; 3493 ehci_soft_qh_t *sqh; 3494 usbd_status err; 3495 int len, isread, endpt; 3496 int s; 3497 3498 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3499 xfer, xfer->length, xfer->flags)); 3500 3501 if (sc->sc_dying) 3502 return (USBD_IOERROR); 3503 3504 #ifdef DIAGNOSTIC 3505 if (xfer->rqflags & URQ_REQUEST) 3506 panic("ehci_device_bulk_start: a request"); 3507 #endif 3508 3509 len = xfer->length; 3510 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3511 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3512 sqh = epipe->sqh; 3513 3514 epipe->u.bulk.length = len; 3515 3516 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3517 &dataend); 3518 if (err) { 3519 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3520 xfer->status = err; 3521 usb_transfer_complete(xfer); 3522 return (err); 3523 } 3524 3525 #ifdef EHCI_DEBUG 3526 if (ehcidebug > 5) { 3527 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3528 ehci_dump_sqh(sqh); 3529 ehci_dump_sqtds(data); 3530 } 3531 #endif 3532 3533 /* Set up interrupt info. */ 3534 exfer->sqtdstart = data; 3535 exfer->sqtdend = dataend; 3536 #ifdef DIAGNOSTIC 3537 if (!exfer->isdone) { 3538 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3539 } 3540 exfer->isdone = 0; 3541 #endif 3542 3543 s = splusb(); 3544 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3545 if (xfer->timeout && !sc->sc_bus.use_polling) { 3546 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3547 (ehci_timeout), (xfer)); 3548 } 3549 mutex_enter(&sc->sc_intrhead_lock); 3550 ehci_add_intr_list(sc, exfer); 3551 mutex_exit(&sc->sc_intrhead_lock); 3552 xfer->status = USBD_IN_PROGRESS; 3553 splx(s); 3554 3555 #ifdef EHCI_DEBUG 3556 if (ehcidebug > 10) { 3557 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3558 delay(10000); 3559 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3560 ehci_dump_regs(sc); 3561 #if 0 3562 printf("async_head:\n"); 3563 ehci_dump_sqh(sc->sc_async_head); 3564 #endif 3565 printf("sqh:\n"); 3566 ehci_dump_sqh(sqh); 3567 ehci_dump_sqtds(data); 3568 } 3569 #endif 3570 3571 if (sc->sc_bus.use_polling) 3572 ehci_waitintr(sc, xfer); 3573 3574 return (USBD_IN_PROGRESS); 3575 #undef exfer 3576 } 3577 3578 Static void 3579 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3580 { 3581 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3582 ehci_abort_xfer(xfer, USBD_CANCELLED); 3583 } 3584 3585 /* 3586 * Close a device bulk pipe. 3587 */ 3588 Static void 3589 ehci_device_bulk_close(usbd_pipe_handle pipe) 3590 { 3591 ehci_softc_t *sc = pipe->device->bus->hci_private; 3592 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3593 3594 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3595 pipe->endpoint->datatoggle = epipe->nexttoggle; 3596 ehci_close_pipe(pipe, sc->sc_async_head); 3597 } 3598 3599 Static void 3600 ehci_device_bulk_done(usbd_xfer_handle xfer) 3601 { 3602 struct ehci_xfer *ex = EXFER(xfer); 3603 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3604 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3605 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3606 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3607 3608 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3609 xfer, xfer->actlen)); 3610 3611 mutex_enter(&sc->sc_intrhead_lock); 3612 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3613 ehci_del_intr_list(sc, ex); /* remove from active list */ 3614 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3615 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3616 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3617 } 3618 mutex_exit(&sc->sc_intrhead_lock); 3619 3620 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3621 } 3622 3623 /************************/ 3624 3625 Static usbd_status 3626 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3627 { 3628 struct ehci_soft_islot *isp; 3629 int islot, lev; 3630 3631 /* Find a poll rate that is large enough. */ 3632 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3633 if (EHCI_ILEV_IVAL(lev) <= ival) 3634 break; 3635 3636 /* Pick an interrupt slot at the right level. */ 3637 /* XXX could do better than picking at random */ 3638 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3639 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3640 3641 sqh->islot = islot; 3642 isp = &sc->sc_islots[islot]; 3643 ehci_add_qh(sqh, isp->sqh); 3644 3645 return (USBD_NORMAL_COMPLETION); 3646 } 3647 3648 Static usbd_status 3649 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3650 { 3651 usbd_status err; 3652 3653 /* Insert last in queue. */ 3654 err = usb_insert_transfer(xfer); 3655 if (err) 3656 return (err); 3657 3658 /* 3659 * Pipe isn't running (otherwise err would be USBD_INPROG), 3660 * so start it first. 3661 */ 3662 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3663 } 3664 3665 Static usbd_status 3666 ehci_device_intr_start(usbd_xfer_handle xfer) 3667 { 3668 #define exfer EXFER(xfer) 3669 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3670 usbd_device_handle dev = xfer->pipe->device; 3671 ehci_softc_t *sc = dev->bus->hci_private; 3672 ehci_soft_qtd_t *data, *dataend; 3673 ehci_soft_qh_t *sqh; 3674 usbd_status err; 3675 int len, isread, endpt; 3676 int s; 3677 3678 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3679 xfer, xfer->length, xfer->flags)); 3680 3681 if (sc->sc_dying) 3682 return (USBD_IOERROR); 3683 3684 #ifdef DIAGNOSTIC 3685 if (xfer->rqflags & URQ_REQUEST) 3686 panic("ehci_device_intr_start: a request"); 3687 #endif 3688 3689 len = xfer->length; 3690 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3691 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3692 sqh = epipe->sqh; 3693 3694 epipe->u.intr.length = len; 3695 3696 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3697 &dataend); 3698 if (err) { 3699 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3700 xfer->status = err; 3701 usb_transfer_complete(xfer); 3702 return (err); 3703 } 3704 3705 #ifdef EHCI_DEBUG 3706 if (ehcidebug > 5) { 3707 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3708 ehci_dump_sqh(sqh); 3709 ehci_dump_sqtds(data); 3710 } 3711 #endif 3712 3713 /* Set up interrupt info. */ 3714 exfer->sqtdstart = data; 3715 exfer->sqtdend = dataend; 3716 #ifdef DIAGNOSTIC 3717 if (!exfer->isdone) { 3718 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3719 } 3720 exfer->isdone = 0; 3721 #endif 3722 3723 s = splusb(); 3724 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3725 if (xfer->timeout && !sc->sc_bus.use_polling) { 3726 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3727 (ehci_timeout), (xfer)); 3728 } 3729 mutex_enter(&sc->sc_intrhead_lock); 3730 ehci_add_intr_list(sc, exfer); 3731 mutex_exit(&sc->sc_intrhead_lock); 3732 xfer->status = USBD_IN_PROGRESS; 3733 splx(s); 3734 3735 #ifdef EHCI_DEBUG 3736 if (ehcidebug > 10) { 3737 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3738 delay(10000); 3739 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3740 ehci_dump_regs(sc); 3741 printf("sqh:\n"); 3742 ehci_dump_sqh(sqh); 3743 ehci_dump_sqtds(data); 3744 } 3745 #endif 3746 3747 if (sc->sc_bus.use_polling) 3748 ehci_waitintr(sc, xfer); 3749 3750 return (USBD_IN_PROGRESS); 3751 #undef exfer 3752 } 3753 3754 Static void 3755 ehci_device_intr_abort(usbd_xfer_handle xfer) 3756 { 3757 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3758 if (xfer->pipe->intrxfer == xfer) { 3759 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3760 xfer->pipe->intrxfer = NULL; 3761 } 3762 /* 3763 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3764 * async doorbell. That's dependent on the async list, wheras 3765 * intr xfers are periodic, should not use this? 3766 */ 3767 ehci_abort_xfer(xfer, USBD_CANCELLED); 3768 } 3769 3770 Static void 3771 ehci_device_intr_close(usbd_pipe_handle pipe) 3772 { 3773 ehci_softc_t *sc = pipe->device->bus->hci_private; 3774 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3775 struct ehci_soft_islot *isp; 3776 3777 isp = &sc->sc_islots[epipe->sqh->islot]; 3778 ehci_close_pipe(pipe, isp->sqh); 3779 } 3780 3781 Static void 3782 ehci_device_intr_done(usbd_xfer_handle xfer) 3783 { 3784 #define exfer EXFER(xfer) 3785 struct ehci_xfer *ex = EXFER(xfer); 3786 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3787 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3788 ehci_soft_qtd_t *data, *dataend; 3789 ehci_soft_qh_t *sqh; 3790 usbd_status err; 3791 int len, isread, endpt, s; 3792 3793 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3794 xfer, xfer->actlen)); 3795 3796 mutex_enter(&sc->sc_intrhead_lock); 3797 if (xfer->pipe->repeat) { 3798 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3799 3800 len = epipe->u.intr.length; 3801 xfer->length = len; 3802 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3803 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3804 usb_syncmem(&xfer->dmabuf, 0, len, 3805 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3806 sqh = epipe->sqh; 3807 3808 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3809 &data, &dataend); 3810 if (err) { 3811 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3812 xfer->status = err; 3813 mutex_exit(&sc->sc_intrhead_lock); 3814 return; 3815 } 3816 3817 /* Set up interrupt info. */ 3818 exfer->sqtdstart = data; 3819 exfer->sqtdend = dataend; 3820 #ifdef DIAGNOSTIC 3821 if (!exfer->isdone) { 3822 printf("ehci_device_intr_done: not done, ex=%p\n", 3823 exfer); 3824 } 3825 exfer->isdone = 0; 3826 #endif 3827 3828 s = splusb(); 3829 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3830 if (xfer->timeout && !sc->sc_bus.use_polling) { 3831 callout_reset(&(xfer->timeout_handle), 3832 (mstohz(xfer->timeout)), (ehci_timeout), (xfer)); 3833 } 3834 splx(s); 3835 3836 xfer->status = USBD_IN_PROGRESS; 3837 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3838 ehci_del_intr_list(sc, ex); /* remove from active list */ 3839 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3840 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3841 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3842 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3843 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3844 } 3845 mutex_exit(&sc->sc_intrhead_lock); 3846 #undef exfer 3847 } 3848 3849 /************************/ 3850 3851 Static usbd_status 3852 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3853 { 3854 usbd_status err; 3855 3856 err = usb_insert_transfer(xfer); 3857 if (err && err != USBD_IN_PROGRESS) 3858 return err; 3859 3860 return ehci_device_isoc_start(xfer); 3861 } 3862 3863 Static usbd_status 3864 ehci_device_isoc_start(usbd_xfer_handle xfer) 3865 { 3866 struct ehci_pipe *epipe; 3867 usbd_device_handle dev; 3868 ehci_softc_t *sc; 3869 struct ehci_xfer *exfer; 3870 ehci_soft_itd_t *itd, *prev, *start, *stop; 3871 usb_dma_t *dma_buf; 3872 int i, j, k, frames, uframes, ufrperframe; 3873 int s, trans_count, offs, total_length; 3874 int frindex; 3875 3876 start = NULL; 3877 prev = NULL; 3878 itd = NULL; 3879 trans_count = 0; 3880 total_length = 0; 3881 exfer = (struct ehci_xfer *) xfer; 3882 sc = xfer->pipe->device->bus->hci_private; 3883 dev = xfer->pipe->device; 3884 epipe = (struct ehci_pipe *)xfer->pipe; 3885 3886 /* 3887 * To allow continuous transfers, above we start all transfers 3888 * immediately. However, we're still going to get usbd_start_next call 3889 * this when another xfer completes. So, check if this is already 3890 * in progress or not 3891 */ 3892 3893 if (exfer->itdstart != NULL) 3894 return USBD_IN_PROGRESS; 3895 3896 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3897 xfer, xfer->length, xfer->flags)); 3898 3899 if (sc->sc_dying) 3900 return USBD_IOERROR; 3901 3902 /* 3903 * To avoid complication, don't allow a request right now that'll span 3904 * the entire frame table. To within 4 frames, to allow some leeway 3905 * on either side of where the hc currently is. 3906 */ 3907 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3908 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3909 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3910 return USBD_INVAL; 3911 } 3912 3913 #ifdef DIAGNOSTIC 3914 if (xfer->rqflags & URQ_REQUEST) 3915 panic("ehci_device_isoc_start: request\n"); 3916 3917 if (!exfer->isdone) 3918 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3919 exfer->isdone = 0; 3920 #endif 3921 3922 /* 3923 * Step 1: Allocate and initialize itds, how many do we need? 3924 * One per transfer if interval >= 8 microframes, fewer if we use 3925 * multiple microframes per frame. 3926 */ 3927 3928 i = epipe->pipe.endpoint->edesc->bInterval; 3929 if (i > 16 || i == 0) { 3930 /* Spec page 271 says intervals > 16 are invalid */ 3931 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3932 return USBD_INVAL; 3933 } 3934 3935 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 3936 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3937 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 3938 3939 if (frames == 0) { 3940 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3941 return USBD_INVAL; 3942 } 3943 3944 dma_buf = &xfer->dmabuf; 3945 offs = 0; 3946 3947 for (i = 0; i < frames; i++) { 3948 int froffs = offs; 3949 itd = ehci_alloc_itd(sc); 3950 3951 if (prev != NULL) { 3952 prev->itd.itd_next = 3953 htole32(itd->physaddr | EHCI_LINK_ITD); 3954 usb_syncmem(&itd->dma, 3955 itd->offs + offsetof(ehci_itd_t, itd_next), 3956 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 3957 3958 prev->xfer_next = itd; 3959 } else { 3960 start = itd; 3961 } 3962 3963 /* 3964 * Step 1.5, initialize uframes 3965 */ 3966 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 3967 /* Calculate which page in the list this starts in */ 3968 int addr = DMAADDR(dma_buf, froffs); 3969 addr = EHCI_PAGE_OFFSET(addr); 3970 addr += (offs - froffs); 3971 addr = EHCI_PAGE(addr); 3972 addr /= EHCI_PAGE_SIZE; 3973 3974 /* This gets the initial offset into the first page, 3975 * looks how far further along the current uframe 3976 * offset is. Works out how many pages that is. 3977 */ 3978 3979 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3980 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3981 EHCI_ITD_SET_PG(addr) | 3982 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 3983 3984 total_length += xfer->frlengths[trans_count]; 3985 offs += xfer->frlengths[trans_count]; 3986 trans_count++; 3987 3988 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3989 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3990 break; 3991 } 3992 } 3993 3994 /* Step 1.75, set buffer pointers. To simplify matters, all 3995 * pointers are filled out for the next 7 hardware pages in 3996 * the dma block, so no need to worry what pages to cover 3997 * and what to not. 3998 */ 3999 4000 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4001 /* 4002 * Don't try to lookup a page that's past the end 4003 * of buffer 4004 */ 4005 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4006 if (page_offs >= dma_buf->block->size) 4007 break; 4008 4009 unsigned long long page = DMAADDR(dma_buf, page_offs); 4010 page = EHCI_PAGE(page); 4011 itd->itd.itd_bufr[j] = 4012 htole32(EHCI_ITD_SET_BPTR(page)); 4013 itd->itd.itd_bufr_hi[j] = 4014 htole32(page >> 32); 4015 } 4016 4017 /* 4018 * Other special values 4019 */ 4020 4021 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4022 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4023 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4024 4025 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4026 ? 1 : 0; 4027 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4028 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4029 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4030 4031 /* FIXME: handle invalid trans */ 4032 itd->itd.itd_bufr[2] |= 4033 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4034 4035 usb_syncmem(&itd->dma, 4036 itd->offs + offsetof(ehci_itd_t, itd_next), 4037 sizeof(ehci_itd_t), 4038 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4039 4040 prev = itd; 4041 } /* End of frame */ 4042 4043 stop = itd; 4044 stop->xfer_next = NULL; 4045 exfer->isoc_len = total_length; 4046 4047 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4048 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4049 4050 /* 4051 * Part 2: Transfer descriptors have now been set up, now they must 4052 * be scheduled into the period frame list. Erk. Not wanting to 4053 * complicate matters, transfer is denied if the transfer spans 4054 * more than the period frame list. 4055 */ 4056 4057 s = splusb(); 4058 4059 /* Start inserting frames */ 4060 if (epipe->u.isoc.cur_xfers > 0) { 4061 frindex = epipe->u.isoc.next_frame; 4062 } else { 4063 frindex = EOREAD4(sc, EHCI_FRINDEX); 4064 frindex = frindex >> 3; /* Erase microframe index */ 4065 frindex += 2; 4066 } 4067 4068 if (frindex >= sc->sc_flsize) 4069 frindex &= (sc->sc_flsize - 1); 4070 4071 /* What's the frame interval? */ 4072 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4073 if (i / USB_UFRAMES_PER_FRAME == 0) 4074 i = 1; 4075 else 4076 i /= USB_UFRAMES_PER_FRAME; 4077 4078 itd = start; 4079 for (j = 0; j < frames; j++) { 4080 if (itd == NULL) 4081 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4082 4083 itd->itd.itd_next = sc->sc_flist[frindex]; 4084 if (itd->itd.itd_next == 0) 4085 /* FIXME: frindex table gets initialized to NULL 4086 * or EHCI_NULL? */ 4087 itd->itd.itd_next = EHCI_NULL; 4088 4089 usb_syncmem(&itd->dma, 4090 itd->offs + offsetof(ehci_itd_t, itd_next), 4091 sizeof(itd->itd.itd_next), 4092 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4093 4094 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4095 4096 usb_syncmem(&sc->sc_fldma, 4097 sizeof(ehci_link_t) * frindex, 4098 sizeof(ehci_link_t), 4099 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4100 4101 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4102 sc->sc_softitds[frindex] = itd; 4103 if (itd->u.frame_list.next != NULL) 4104 itd->u.frame_list.next->u.frame_list.prev = itd; 4105 itd->slot = frindex; 4106 itd->u.frame_list.prev = NULL; 4107 4108 frindex += i; 4109 if (frindex >= sc->sc_flsize) 4110 frindex -= sc->sc_flsize; 4111 4112 itd = itd->xfer_next; 4113 } 4114 4115 epipe->u.isoc.cur_xfers++; 4116 epipe->u.isoc.next_frame = frindex; 4117 4118 exfer->itdstart = start; 4119 exfer->itdend = stop; 4120 exfer->sqtdstart = NULL; 4121 exfer->sqtdstart = NULL; 4122 4123 mutex_enter(&sc->sc_intrhead_lock); 4124 ehci_add_intr_list(sc, exfer); 4125 mutex_exit(&sc->sc_intrhead_lock); 4126 xfer->status = USBD_IN_PROGRESS; 4127 xfer->done = 0; 4128 splx(s); 4129 4130 if (sc->sc_bus.use_polling) { 4131 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4132 ehci_waitintr(sc, xfer); 4133 } 4134 4135 return USBD_IN_PROGRESS; 4136 } 4137 4138 Static void 4139 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4140 { 4141 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4142 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4143 } 4144 4145 Static void 4146 ehci_device_isoc_close(usbd_pipe_handle pipe) 4147 { 4148 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4149 } 4150 4151 Static void 4152 ehci_device_isoc_done(usbd_xfer_handle xfer) 4153 { 4154 struct ehci_xfer *exfer; 4155 ehci_softc_t *sc; 4156 struct ehci_pipe *epipe; 4157 int s; 4158 4159 exfer = EXFER(xfer); 4160 sc = xfer->pipe->device->bus->hci_private; 4161 epipe = (struct ehci_pipe *) xfer->pipe; 4162 4163 s = splusb(); 4164 epipe->u.isoc.cur_xfers--; 4165 mutex_enter(&sc->sc_intrhead_lock); 4166 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4167 ehci_del_intr_list(sc, exfer); 4168 ehci_rem_free_itd_chain(sc, exfer); 4169 } 4170 mutex_exit(&sc->sc_intrhead_lock); 4171 splx(s); 4172 4173 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4174 BUS_DMASYNC_POSTREAD); 4175 4176 } 4177
Indexes created Wed Oct 01 19:09:53 GMT 2025