ehci.c revision 1.186
1 /* $NetBSD: ehci.c,v 1.186 2012/03/06 03:35:29 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2008 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum and 9 * Jeremy Morse (jeremy.morse (at) gmail.com). 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 35 * 36 * The EHCI 1.0 spec can be found at 37 * http://www.intel.com/technology/usb/spec.htm 38 * and the USB 2.0 spec at 39 * http://www.usb.org/developers/docs/ 40 * 41 */ 42 43 /* 44 * TODO: 45 * 1) hold off explorations by companion controllers until ehci has started. 46 * 47 * 2) The hub driver needs to handle and schedule the transaction translator, 48 * to assign place in frame where different devices get to go. See chapter 49 * on hubs in USB 2.0 for details. 50 * 51 * 3) Command failures are not recovered correctly. 52 */ 53 54 #include <sys/cdefs.h> 55 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.186 2012/03/06 03:35:29 mrg Exp $"); 56 57 #include "ohci.h" 58 #include "uhci.h" 59 #include "opt_usb.h" 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/kernel.h> 64 #include <sys/malloc.h> 65 #include <sys/device.h> 66 #include <sys/select.h> 67 #include <sys/proc.h> 68 #include <sys/queue.h> 69 #include <sys/mutex.h> 70 #include <sys/bus.h> 71 72 #include <machine/endian.h> 73 74 #include <dev/usb/usb.h> 75 #include <dev/usb/usbdi.h> 76 #include <dev/usb/usbdivar.h> 77 #include <dev/usb/usb_mem.h> 78 #include <dev/usb/usb_quirks.h> 79 80 #include <dev/usb/ehcireg.h> 81 #include <dev/usb/ehcivar.h> 82 #include <dev/usb/usbroothub_subr.h> 83 84 #ifdef EHCI_DEBUG 85 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0) 86 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0) 87 int ehcidebug = 0; 88 #else 89 #define DPRINTF(x) 90 #define DPRINTFN(n,x) 91 #endif 92 93 struct ehci_pipe { 94 struct usbd_pipe pipe; 95 int nexttoggle; 96 97 ehci_soft_qh_t *sqh; 98 union { 99 ehci_soft_qtd_t *qtd; 100 /* ehci_soft_itd_t *itd; */ 101 } tail; 102 union { 103 /* Control pipe */ 104 struct { 105 usb_dma_t reqdma; 106 u_int length; 107 } ctl; 108 /* Interrupt pipe */ 109 struct { 110 u_int length; 111 } intr; 112 /* Bulk pipe */ 113 struct { 114 u_int length; 115 } bulk; 116 /* Iso pipe */ 117 struct { 118 u_int next_frame; 119 u_int cur_xfers; 120 } isoc; 121 } u; 122 }; 123 124 Static usbd_status ehci_open(usbd_pipe_handle); 125 Static void ehci_poll(struct usbd_bus *); 126 Static void ehci_softintr(void *); 127 Static int ehci_intr1(ehci_softc_t *); 128 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 129 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 130 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 131 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 132 Static void ehci_idone(struct ehci_xfer *); 133 Static void ehci_timeout(void *); 134 Static void ehci_timeout_task(void *); 135 Static void ehci_intrlist_timeout(void *); 136 137 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 138 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 139 140 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 141 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 142 143 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 144 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 145 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 146 Static void ehci_root_ctrl_close(usbd_pipe_handle); 147 Static void ehci_root_ctrl_done(usbd_xfer_handle); 148 149 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 150 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 151 Static void ehci_root_intr_abort(usbd_xfer_handle); 152 Static void ehci_root_intr_close(usbd_pipe_handle); 153 Static void ehci_root_intr_done(usbd_xfer_handle); 154 155 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 156 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 157 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 158 Static void ehci_device_ctrl_close(usbd_pipe_handle); 159 Static void ehci_device_ctrl_done(usbd_xfer_handle); 160 161 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 162 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 163 Static void ehci_device_bulk_abort(usbd_xfer_handle); 164 Static void ehci_device_bulk_close(usbd_pipe_handle); 165 Static void ehci_device_bulk_done(usbd_xfer_handle); 166 167 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 168 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 169 Static void ehci_device_intr_abort(usbd_xfer_handle); 170 Static void ehci_device_intr_close(usbd_pipe_handle); 171 Static void ehci_device_intr_done(usbd_xfer_handle); 172 173 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 174 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 175 Static void ehci_device_isoc_abort(usbd_xfer_handle); 176 Static void ehci_device_isoc_close(usbd_pipe_handle); 177 Static void ehci_device_isoc_done(usbd_xfer_handle); 178 179 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 180 Static void ehci_noop(usbd_pipe_handle pipe); 181 182 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle); 183 Static void ehci_disown(ehci_softc_t *, int, int); 184 185 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 186 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 187 188 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 189 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 190 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 191 ehci_softc_t *, int, int, usbd_xfer_handle, 192 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 193 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 194 ehci_soft_qtd_t *); 195 196 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 197 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 198 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 199 struct ehci_xfer *exfer); 200 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 201 usbd_status status); 202 203 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 204 205 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 206 int ival); 207 208 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *); 209 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 210 ehci_soft_qh_t *); 211 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 212 Static void ehci_sync_hc(ehci_softc_t *); 213 214 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 215 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 216 217 #ifdef EHCI_DEBUG 218 Static void ehci_dump_regs(ehci_softc_t *); 219 void ehci_dump(void); 220 Static ehci_softc_t *theehci; 221 Static void ehci_dump_link(ehci_link_t, int); 222 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 223 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 224 Static void ehci_dump_qtd(ehci_qtd_t *); 225 Static void ehci_dump_sqh(ehci_soft_qh_t *); 226 #if notyet 227 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 228 Static void ehci_dump_itd(struct ehci_soft_itd *); 229 #endif 230 #ifdef DIAGNOSTIC 231 Static void ehci_dump_exfer(struct ehci_xfer *); 232 #endif 233 #endif 234 235 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 236 237 #define EHCI_INTR_ENDPT 1 238 239 #define ehci_add_intr_list(sc, ex) \ 240 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 241 #define ehci_del_intr_list(sc, ex) \ 242 do { \ 243 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 244 (ex)->inext.tqe_prev = NULL; \ 245 } while (0) 246 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 247 248 Static const struct usbd_bus_methods ehci_bus_methods = { 249 .open_pipe = ehci_open, 250 .soft_intr = ehci_softintr, 251 .do_poll = ehci_poll, 252 .allocm = ehci_allocm, 253 .freem = ehci_freem, 254 .allocx = ehci_allocx, 255 .freex = ehci_freex, 256 }; 257 258 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 259 .transfer = ehci_root_ctrl_transfer, 260 .start = ehci_root_ctrl_start, 261 .abort = ehci_root_ctrl_abort, 262 .close = ehci_root_ctrl_close, 263 .cleartoggle = ehci_noop, 264 .done = ehci_root_ctrl_done, 265 }; 266 267 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 268 .transfer = ehci_root_intr_transfer, 269 .start = ehci_root_intr_start, 270 .abort = ehci_root_intr_abort, 271 .close = ehci_root_intr_close, 272 .cleartoggle = ehci_noop, 273 .done = ehci_root_intr_done, 274 }; 275 276 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 277 .transfer = ehci_device_ctrl_transfer, 278 .start = ehci_device_ctrl_start, 279 .abort = ehci_device_ctrl_abort, 280 .close = ehci_device_ctrl_close, 281 .cleartoggle = ehci_noop, 282 .done = ehci_device_ctrl_done, 283 }; 284 285 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 286 .transfer = ehci_device_intr_transfer, 287 .start = ehci_device_intr_start, 288 .abort = ehci_device_intr_abort, 289 .close = ehci_device_intr_close, 290 .cleartoggle = ehci_device_clear_toggle, 291 .done = ehci_device_intr_done, 292 }; 293 294 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 295 .transfer = ehci_device_bulk_transfer, 296 .start = ehci_device_bulk_start, 297 .abort = ehci_device_bulk_abort, 298 .close = ehci_device_bulk_close, 299 .cleartoggle = ehci_device_clear_toggle, 300 .done = ehci_device_bulk_done, 301 }; 302 303 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 304 .transfer = ehci_device_isoc_transfer, 305 .start = ehci_device_isoc_start, 306 .abort = ehci_device_isoc_abort, 307 .close = ehci_device_isoc_close, 308 .cleartoggle = ehci_noop, 309 .done = ehci_device_isoc_done, 310 }; 311 312 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 313 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 314 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 315 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 316 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 317 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 318 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 319 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 320 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 321 }; 322 323 usbd_status 324 ehci_init(ehci_softc_t *sc) 325 { 326 u_int32_t vers, sparams, cparams, hcr; 327 u_int i; 328 usbd_status err; 329 ehci_soft_qh_t *sqh; 330 u_int ncomp; 331 332 DPRINTF(("ehci_init: start\n")); 333 #ifdef EHCI_DEBUG 334 theehci = sc; 335 #endif 336 337 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 338 339 vers = EREAD2(sc, EHCI_HCIVERSION); 340 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 341 vers >> 8, vers & 0xff); 342 343 sparams = EREAD4(sc, EHCI_HCSPARAMS); 344 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 345 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 346 ncomp = EHCI_HCS_N_CC(sparams); 347 if (ncomp != sc->sc_ncomp) { 348 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 349 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 350 #if NOHCI == 0 || NUHCI == 0 351 aprint_error("%s: ohci or uhci probably not configured\n", 352 device_xname(sc->sc_dev)); 353 #endif 354 if (ncomp < sc->sc_ncomp) 355 sc->sc_ncomp = ncomp; 356 } 357 if (sc->sc_ncomp > 0) { 358 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 359 aprint_normal("%s: companion controller%s, %d port%s each:", 360 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 361 EHCI_HCS_N_PCC(sparams), 362 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 363 for (i = 0; i < sc->sc_ncomp; i++) 364 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 365 aprint_normal("\n"); 366 } 367 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 368 cparams = EREAD4(sc, EHCI_HCCPARAMS); 369 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 370 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 371 372 if (EHCI_HCC_64BIT(cparams)) { 373 /* MUST clear segment register if 64 bit capable. */ 374 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 375 } 376 377 sc->sc_bus.usbrev = USBREV_2_0; 378 379 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 380 USB_MEM_RESERVE); 381 382 /* Reset the controller */ 383 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 384 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 385 usb_delay_ms(&sc->sc_bus, 1); 386 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 387 for (i = 0; i < 100; i++) { 388 usb_delay_ms(&sc->sc_bus, 1); 389 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 390 if (!hcr) 391 break; 392 } 393 if (hcr) { 394 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 395 return (USBD_IOERROR); 396 } 397 if (sc->sc_vendor_init) 398 sc->sc_vendor_init(sc); 399 400 /* 401 * If we are doing embedded transaction translation function, force 402 * the controller to host mode. 403 */ 404 if (sc->sc_flags & EHCIF_ETTF) { 405 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 406 usbmode &= ~EHCI_USBMODE_CM; 407 usbmode |= EHCI_USBMODE_CM_HOST; 408 EWRITE4(sc, EHCI_USBMODE, usbmode); 409 } 410 411 /* XXX need proper intr scheduling */ 412 sc->sc_rand = 96; 413 414 /* frame list size at default, read back what we got and use that */ 415 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 416 case 0: sc->sc_flsize = 1024; break; 417 case 1: sc->sc_flsize = 512; break; 418 case 2: sc->sc_flsize = 256; break; 419 case 3: return (USBD_IOERROR); 420 } 421 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 422 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 423 if (err) 424 return (err); 425 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 426 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 427 428 for (i = 0; i < sc->sc_flsize; i++) { 429 sc->sc_flist[i] = EHCI_NULL; 430 } 431 432 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 433 434 sc->sc_softitds = malloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 435 M_USB, M_NOWAIT | M_ZERO); 436 if (sc->sc_softitds == NULL) 437 return ENOMEM; 438 LIST_INIT(&sc->sc_freeitds); 439 TAILQ_INIT(&sc->sc_intrhead); 440 mutex_init(&sc->sc_intrhead_lock, MUTEX_DEFAULT, IPL_USB); 441 442 /* Set up the bus struct. */ 443 sc->sc_bus.methods = &ehci_bus_methods; 444 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 445 446 sc->sc_eintrs = EHCI_NORMAL_INTRS; 447 448 /* 449 * Allocate the interrupt dummy QHs. These are arranged to give poll 450 * intervals that are powers of 2 times 1ms. 451 */ 452 for (i = 0; i < EHCI_INTRQHS; i++) { 453 sqh = ehci_alloc_sqh(sc); 454 if (sqh == NULL) { 455 err = USBD_NOMEM; 456 goto bad1; 457 } 458 sc->sc_islots[i].sqh = sqh; 459 } 460 for (i = 0; i < EHCI_INTRQHS; i++) { 461 sqh = sc->sc_islots[i].sqh; 462 if (i == 0) { 463 /* The last (1ms) QH terminates. */ 464 sqh->qh.qh_link = EHCI_NULL; 465 sqh->next = NULL; 466 } else { 467 /* Otherwise the next QH has half the poll interval */ 468 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 469 sqh->qh.qh_link = htole32(sqh->next->physaddr | 470 EHCI_LINK_QH); 471 } 472 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 473 sqh->qh.qh_curqtd = EHCI_NULL; 474 sqh->next = NULL; 475 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 476 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 477 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 478 sqh->sqtd = NULL; 479 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 480 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 481 } 482 /* Point the frame list at the last level (128ms). */ 483 for (i = 0; i < sc->sc_flsize; i++) { 484 int j; 485 486 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 487 revbits[i & (EHCI_MAX_POLLRATE-1)]; 488 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 489 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 490 i)].sqh->physaddr); 491 } 492 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 493 BUS_DMASYNC_PREWRITE); 494 495 /* Allocate dummy QH that starts the async list. */ 496 sqh = ehci_alloc_sqh(sc); 497 if (sqh == NULL) { 498 err = USBD_NOMEM; 499 goto bad1; 500 } 501 /* Fill the QH */ 502 sqh->qh.qh_endp = 503 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 504 sqh->qh.qh_link = 505 htole32(sqh->physaddr | EHCI_LINK_QH); 506 sqh->qh.qh_curqtd = EHCI_NULL; 507 sqh->next = NULL; 508 /* Fill the overlay qTD */ 509 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 510 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 511 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 512 sqh->sqtd = NULL; 513 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 514 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 515 #ifdef EHCI_DEBUG 516 if (ehcidebug) { 517 ehci_dump_sqh(sqh); 518 } 519 #endif 520 521 /* Point to async list */ 522 sc->sc_async_head = sqh; 523 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 524 525 callout_init(&(sc->sc_tmo_intrlist), 0); 526 527 mutex_init(&sc->sc_doorbell_lock, MUTEX_DEFAULT, IPL_NONE); 528 529 /* Turn on controller */ 530 EOWRITE4(sc, EHCI_USBCMD, 531 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 532 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 533 EHCI_CMD_ASE | 534 EHCI_CMD_PSE | 535 EHCI_CMD_RS); 536 537 /* Take over port ownership */ 538 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 539 540 for (i = 0; i < 100; i++) { 541 usb_delay_ms(&sc->sc_bus, 1); 542 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 543 if (!hcr) 544 break; 545 } 546 if (hcr) { 547 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 548 return (USBD_IOERROR); 549 } 550 551 /* Enable interrupts */ 552 DPRINTFN(1,("ehci_init: enabling\n")); 553 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 554 555 return (USBD_NORMAL_COMPLETION); 556 557 #if 0 558 bad2: 559 ehci_free_sqh(sc, sc->sc_async_head); 560 #endif 561 bad1: 562 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 563 return (err); 564 } 565 566 int 567 ehci_intr(void *v) 568 { 569 ehci_softc_t *sc = v; 570 571 if (sc == NULL || sc->sc_dying || !device_has_power(sc->sc_dev)) 572 return (0); 573 574 /* If we get an interrupt while polling, then just ignore it. */ 575 if (sc->sc_bus.use_polling) { 576 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 577 578 if (intrs) 579 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 580 #ifdef DIAGNOSTIC 581 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 582 #endif 583 return (0); 584 } 585 586 return (ehci_intr1(sc)); 587 } 588 589 Static int 590 ehci_intr1(ehci_softc_t *sc) 591 { 592 u_int32_t intrs, eintrs; 593 594 DPRINTFN(20,("ehci_intr1: enter\n")); 595 596 /* In case the interrupt occurs before initialization has completed. */ 597 if (sc == NULL) { 598 #ifdef DIAGNOSTIC 599 printf("ehci_intr1: sc == NULL\n"); 600 #endif 601 return (0); 602 } 603 604 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 605 if (!intrs) 606 return (0); 607 608 eintrs = intrs & sc->sc_eintrs; 609 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 610 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 611 (u_int)eintrs)); 612 if (!eintrs) 613 return (0); 614 615 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 616 sc->sc_bus.intr_context++; 617 sc->sc_bus.no_intrs++; 618 if (eintrs & EHCI_STS_IAA) { 619 DPRINTF(("ehci_intr1: door bell\n")); 620 wakeup(&sc->sc_async_head); 621 eintrs &= ~EHCI_STS_IAA; 622 } 623 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 624 DPRINTFN(5,("ehci_intr1: %s %s\n", 625 eintrs & EHCI_STS_INT ? "INT" : "", 626 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 627 usb_schedsoftintr(&sc->sc_bus); 628 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 629 } 630 if (eintrs & EHCI_STS_HSE) { 631 printf("%s: unrecoverable error, controller halted\n", 632 device_xname(sc->sc_dev)); 633 /* XXX what else */ 634 } 635 if (eintrs & EHCI_STS_PCD) { 636 ehci_pcd(sc, sc->sc_intrxfer); 637 eintrs &= ~EHCI_STS_PCD; 638 } 639 640 sc->sc_bus.intr_context--; 641 642 if (eintrs != 0) { 643 /* Block unprocessed interrupts. */ 644 sc->sc_eintrs &= ~eintrs; 645 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 646 printf("%s: blocking intrs 0x%x\n", 647 device_xname(sc->sc_dev), eintrs); 648 } 649 650 return (1); 651 } 652 653 654 Static void 655 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer) 656 { 657 usbd_pipe_handle pipe; 658 u_char *p; 659 int i, m; 660 661 if (xfer == NULL) { 662 /* Just ignore the change. */ 663 return; 664 } 665 666 pipe = xfer->pipe; 667 668 p = KERNADDR(&xfer->dmabuf, 0); 669 m = min(sc->sc_noport, xfer->length * 8 - 1); 670 memset(p, 0, xfer->length); 671 for (i = 1; i <= m; i++) { 672 /* Pick out CHANGE bits from the status reg. */ 673 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 674 p[i/8] |= 1 << (i%8); 675 } 676 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 677 xfer->actlen = xfer->length; 678 xfer->status = USBD_NORMAL_COMPLETION; 679 680 usb_transfer_complete(xfer); 681 } 682 683 Static void 684 ehci_softintr(void *v) 685 { 686 struct usbd_bus *bus = v; 687 ehci_softc_t *sc = bus->hci_private; 688 struct ehci_xfer *ex, *nextex; 689 690 DPRINTFN(10,("%s: ehci_softintr (%d)\n", device_xname(sc->sc_dev), 691 sc->sc_bus.intr_context)); 692 693 sc->sc_bus.intr_context++; 694 695 /* 696 * The only explanation I can think of for why EHCI is as brain dead 697 * as UHCI interrupt-wise is that Intel was involved in both. 698 * An interrupt just tells us that something is done, we have no 699 * clue what, so we need to scan through all active transfers. :-( 700 */ 701 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 702 nextex = TAILQ_NEXT(ex, inext); 703 ehci_check_intr(sc, ex); 704 } 705 706 /* Schedule a callout to catch any dropped transactions. */ 707 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 708 !TAILQ_EMPTY(&sc->sc_intrhead)) 709 callout_reset(&(sc->sc_tmo_intrlist), 710 (hz), (ehci_intrlist_timeout), (sc)); 711 712 if (sc->sc_softwake) { 713 sc->sc_softwake = 0; 714 wakeup(&sc->sc_softwake); 715 } 716 717 sc->sc_bus.intr_context--; 718 } 719 720 /* Check for an interrupt. */ 721 Static void 722 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 723 { 724 int attr; 725 726 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 727 728 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 729 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 730 ehci_check_itd_intr(sc, ex); 731 else 732 ehci_check_qh_intr(sc, ex); 733 734 return; 735 } 736 737 Static void 738 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 739 { 740 ehci_soft_qtd_t *sqtd, *lsqtd; 741 __uint32_t status; 742 743 if (ex->sqtdstart == NULL) { 744 printf("ehci_check_qh_intr: not valid sqtd\n"); 745 return; 746 } 747 748 lsqtd = ex->sqtdend; 749 #ifdef DIAGNOSTIC 750 if (lsqtd == NULL) { 751 printf("ehci_check_qh_intr: lsqtd==0\n"); 752 return; 753 } 754 #endif 755 /* 756 * If the last TD is still active we need to check whether there 757 * is a an error somewhere in the middle, or whether there was a 758 * short packet (SPD and not ACTIVE). 759 */ 760 usb_syncmem(&lsqtd->dma, 761 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 762 sizeof(lsqtd->qtd.qtd_status), 763 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 764 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 765 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 766 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 767 usb_syncmem(&sqtd->dma, 768 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 769 sizeof(sqtd->qtd.qtd_status), 770 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 771 status = le32toh(sqtd->qtd.qtd_status); 772 usb_syncmem(&sqtd->dma, 773 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 774 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 775 /* If there's an active QTD the xfer isn't done. */ 776 if (status & EHCI_QTD_ACTIVE) 777 break; 778 /* Any kind of error makes the xfer done. */ 779 if (status & EHCI_QTD_HALTED) 780 goto done; 781 /* We want short packets, and it is short: it's done */ 782 if (EHCI_QTD_GET_BYTES(status) != 0) 783 goto done; 784 } 785 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 786 ex, ex->sqtdstart)); 787 usb_syncmem(&lsqtd->dma, 788 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 789 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 790 return; 791 } 792 done: 793 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 794 callout_stop(&ex->xfer.timeout_handle); 795 ehci_idone(ex); 796 } 797 798 Static void 799 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) { 800 ehci_soft_itd_t *itd; 801 int i; 802 803 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 804 return; 805 806 if (ex->itdstart == NULL) { 807 printf("ehci_check_itd_intr: not valid itd\n"); 808 return; 809 } 810 811 itd = ex->itdend; 812 #ifdef DIAGNOSTIC 813 if (itd == NULL) { 814 printf("ehci_check_itd_intr: itdend == 0\n"); 815 return; 816 } 817 #endif 818 819 /* 820 * check no active transfers in last itd, meaning we're finished 821 */ 822 823 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 824 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 825 BUS_DMASYNC_POSTREAD); 826 827 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 828 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 829 break; 830 } 831 832 if (i == EHCI_ITD_NUFRAMES) { 833 goto done; /* All 8 descriptors inactive, it's done */ 834 } 835 836 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 837 ex->itdstart)); 838 return; 839 done: 840 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 841 callout_stop(&ex->xfer.timeout_handle); 842 ehci_idone(ex); 843 } 844 845 Static void 846 ehci_idone(struct ehci_xfer *ex) 847 { 848 usbd_xfer_handle xfer = &ex->xfer; 849 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 850 ehci_soft_qtd_t *sqtd, *lsqtd; 851 u_int32_t status = 0, nstatus = 0; 852 int actlen; 853 854 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 855 #ifdef DIAGNOSTIC 856 { 857 int s = splhigh(); 858 if (ex->isdone) { 859 splx(s); 860 #ifdef EHCI_DEBUG 861 printf("ehci_idone: ex is done!\n "); 862 ehci_dump_exfer(ex); 863 #else 864 printf("ehci_idone: ex=%p is done!\n", ex); 865 #endif 866 return; 867 } 868 ex->isdone = 1; 869 splx(s); 870 } 871 #endif 872 if (xfer->status == USBD_CANCELLED || 873 xfer->status == USBD_TIMEOUT) { 874 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 875 return; 876 } 877 878 #ifdef EHCI_DEBUG 879 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 880 if (ehcidebug > 10) 881 ehci_dump_sqtds(ex->sqtdstart); 882 #endif 883 884 /* The transfer is done, compute actual length and status. */ 885 886 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 887 == UE_ISOCHRONOUS) { 888 /* Isoc transfer */ 889 struct ehci_soft_itd *itd; 890 int i, nframes, len, uframes; 891 892 nframes = 0; 893 actlen = 0; 894 895 i = xfer->pipe->endpoint->edesc->bInterval; 896 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 897 898 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 899 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 900 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 901 BUS_DMASYNC_POSTREAD); 902 903 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 904 /* XXX - driver didn't fill in the frame full 905 * of uframes. This leads to scheduling 906 * inefficiencies, but working around 907 * this doubles complexity of tracking 908 * an xfer. 909 */ 910 if (nframes >= xfer->nframes) 911 break; 912 913 status = le32toh(itd->itd.itd_ctl[i]); 914 len = EHCI_ITD_GET_LEN(status); 915 if (EHCI_ITD_GET_STATUS(status) != 0) 916 len = 0; /*No valid data on error*/ 917 918 xfer->frlengths[nframes++] = len; 919 actlen += len; 920 } 921 922 if (nframes >= xfer->nframes) 923 break; 924 } 925 926 xfer->actlen = actlen; 927 xfer->status = USBD_NORMAL_COMPLETION; 928 goto end; 929 } 930 931 /* Continue processing xfers using queue heads */ 932 933 lsqtd = ex->sqtdend; 934 actlen = 0; 935 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 936 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 937 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 938 nstatus = le32toh(sqtd->qtd.qtd_status); 939 if (nstatus & EHCI_QTD_ACTIVE) 940 break; 941 942 status = nstatus; 943 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 944 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 945 } 946 947 948 /* 949 * If there are left over TDs we need to update the toggle. 950 * The default pipe doesn't need it since control transfers 951 * start the toggle at 0 every time. 952 * For a short transfer we need to update the toggle for the missing 953 * packets within the qTD. 954 */ 955 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 956 xfer->pipe->device->default_pipe != xfer->pipe) { 957 DPRINTFN(2, ("ehci_idone: need toggle update " 958 "status=%08x nstatus=%08x\n", status, nstatus)); 959 #if 0 960 ehci_dump_sqh(epipe->sqh); 961 ehci_dump_sqtds(ex->sqtdstart); 962 #endif 963 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 964 } 965 966 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 967 xfer->length, actlen, status)); 968 xfer->actlen = actlen; 969 if (status & EHCI_QTD_HALTED) { 970 #ifdef EHCI_DEBUG 971 char sbuf[128]; 972 973 snprintb(sbuf, sizeof(sbuf), 974 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 975 (u_int32_t)status); 976 977 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 978 "status 0x%s\n", 979 xfer->pipe->device->address, 980 xfer->pipe->endpoint->edesc->bEndpointAddress, 981 sbuf)); 982 if (ehcidebug > 2) { 983 ehci_dump_sqh(epipe->sqh); 984 ehci_dump_sqtds(ex->sqtdstart); 985 } 986 #endif 987 /* low&full speed has an extra error flag */ 988 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 989 EHCI_QH_SPEED_HIGH) 990 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 991 else 992 status &= EHCI_QTD_STATERRS; 993 if (status == 0) /* no other errors means a stall */ { 994 xfer->status = USBD_STALLED; 995 } else { 996 xfer->status = USBD_IOERROR; /* more info XXX */ 997 } 998 /* XXX need to reset TT on missed microframe */ 999 if (status & EHCI_QTD_MISSEDMICRO) { 1000 ehci_softc_t *sc = 1001 xfer->pipe->device->bus->hci_private; 1002 1003 printf("%s: missed microframe, TT reset not " 1004 "implemented, hub might be inoperational\n", 1005 device_xname(sc->sc_dev)); 1006 } 1007 } else { 1008 xfer->status = USBD_NORMAL_COMPLETION; 1009 } 1010 1011 end: 1012 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1013 * during this call, before methods->done is called: dma sync required 1014 * beforehand? */ 1015 usb_transfer_complete(xfer); 1016 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1017 } 1018 1019 /* 1020 * Wait here until controller claims to have an interrupt. 1021 * Then call ehci_intr and return. Use timeout to avoid waiting 1022 * too long. 1023 */ 1024 Static void 1025 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1026 { 1027 int timo; 1028 u_int32_t intrs; 1029 1030 xfer->status = USBD_IN_PROGRESS; 1031 for (timo = xfer->timeout; timo >= 0; timo--) { 1032 usb_delay_ms(&sc->sc_bus, 1); 1033 if (sc->sc_dying) 1034 break; 1035 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1036 sc->sc_eintrs; 1037 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1038 #ifdef EHCI_DEBUG 1039 if (ehcidebug > 15) 1040 ehci_dump_regs(sc); 1041 #endif 1042 if (intrs) { 1043 ehci_intr1(sc); 1044 if (xfer->status != USBD_IN_PROGRESS) 1045 return; 1046 } 1047 } 1048 1049 /* Timeout */ 1050 DPRINTF(("ehci_waitintr: timeout\n")); 1051 xfer->status = USBD_TIMEOUT; 1052 usb_transfer_complete(xfer); 1053 /* XXX should free TD */ 1054 } 1055 1056 Static void 1057 ehci_poll(struct usbd_bus *bus) 1058 { 1059 ehci_softc_t *sc = bus->hci_private; 1060 #ifdef EHCI_DEBUG 1061 static int last; 1062 int new; 1063 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1064 if (new != last) { 1065 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1066 last = new; 1067 } 1068 #endif 1069 1070 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) 1071 ehci_intr1(sc); 1072 } 1073 1074 void 1075 ehci_childdet(device_t self, device_t child) 1076 { 1077 struct ehci_softc *sc = device_private(self); 1078 1079 KASSERT(sc->sc_child == child); 1080 sc->sc_child = NULL; 1081 } 1082 1083 int 1084 ehci_detach(struct ehci_softc *sc, int flags) 1085 { 1086 int rv = 0; 1087 1088 if (sc->sc_child != NULL) 1089 rv = config_detach(sc->sc_child, flags); 1090 1091 if (rv != 0) 1092 return (rv); 1093 1094 callout_stop(&sc->sc_tmo_intrlist); 1095 1096 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */ 1097 1098 /* XXX free other data structures XXX */ 1099 mutex_destroy(&sc->sc_doorbell_lock); 1100 mutex_destroy(&sc->sc_intrhead_lock); 1101 1102 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1103 1104 return (rv); 1105 } 1106 1107 1108 int 1109 ehci_activate(device_t self, enum devact act) 1110 { 1111 struct ehci_softc *sc = device_private(self); 1112 1113 switch (act) { 1114 case DVACT_DEACTIVATE: 1115 sc->sc_dying = 1; 1116 return 0; 1117 default: 1118 return EOPNOTSUPP; 1119 } 1120 } 1121 1122 /* 1123 * Handle suspend/resume. 1124 * 1125 * We need to switch to polling mode here, because this routine is 1126 * called from an interrupt context. This is all right since we 1127 * are almost suspended anyway. 1128 * 1129 * Note that this power handler isn't to be registered directly; the 1130 * bus glue needs to call out to it. 1131 */ 1132 bool 1133 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1134 { 1135 ehci_softc_t *sc = device_private(dv); 1136 int i, s; 1137 uint32_t cmd, hcr; 1138 1139 s = splhardusb(); 1140 1141 sc->sc_bus.use_polling++; 1142 1143 for (i = 1; i <= sc->sc_noport; i++) { 1144 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1145 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1146 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1147 } 1148 1149 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1150 1151 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1152 EOWRITE4(sc, EHCI_USBCMD, cmd); 1153 1154 for (i = 0; i < 100; i++) { 1155 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1156 if (hcr == 0) 1157 break; 1158 1159 usb_delay_ms(&sc->sc_bus, 1); 1160 } 1161 if (hcr != 0) 1162 printf("%s: reset timeout\n", device_xname(dv)); 1163 1164 cmd &= ~EHCI_CMD_RS; 1165 EOWRITE4(sc, EHCI_USBCMD, cmd); 1166 1167 for (i = 0; i < 100; i++) { 1168 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1169 if (hcr == EHCI_STS_HCH) 1170 break; 1171 1172 usb_delay_ms(&sc->sc_bus, 1); 1173 } 1174 if (hcr != EHCI_STS_HCH) 1175 printf("%s: config timeout\n", device_xname(dv)); 1176 1177 sc->sc_bus.use_polling--; 1178 splx(s); 1179 1180 return true; 1181 } 1182 1183 bool 1184 ehci_resume(device_t dv, const pmf_qual_t *qual) 1185 { 1186 ehci_softc_t *sc = device_private(dv); 1187 int i; 1188 uint32_t cmd, hcr; 1189 1190 /* restore things in case the bios sucks */ 1191 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1192 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1193 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1194 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1195 1196 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1197 1198 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1199 1200 hcr = 0; 1201 for (i = 1; i <= sc->sc_noport; i++) { 1202 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1203 if ((cmd & EHCI_PS_PO) == 0 && 1204 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1205 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1206 hcr = 1; 1207 } 1208 } 1209 1210 if (hcr) { 1211 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1212 1213 for (i = 1; i <= sc->sc_noport; i++) { 1214 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1215 if ((cmd & EHCI_PS_PO) == 0 && 1216 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1217 EOWRITE4(sc, EHCI_PORTSC(i), 1218 cmd & ~EHCI_PS_FPR); 1219 } 1220 } 1221 1222 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1223 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1224 1225 for (i = 0; i < 100; i++) { 1226 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1227 if (hcr != EHCI_STS_HCH) 1228 break; 1229 1230 usb_delay_ms(&sc->sc_bus, 1); 1231 } 1232 if (hcr == EHCI_STS_HCH) 1233 printf("%s: config timeout\n", device_xname(dv)); 1234 1235 return true; 1236 } 1237 1238 /* 1239 * Shut down the controller when the system is going down. 1240 */ 1241 bool 1242 ehci_shutdown(device_t self, int flags) 1243 { 1244 ehci_softc_t *sc = device_private(self); 1245 1246 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1247 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1248 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1249 return true; 1250 } 1251 1252 Static usbd_status 1253 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1254 { 1255 struct ehci_softc *sc = bus->hci_private; 1256 usbd_status err; 1257 1258 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1259 if (err == USBD_NOMEM) 1260 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1261 #ifdef EHCI_DEBUG 1262 if (err) 1263 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1264 #endif 1265 return (err); 1266 } 1267 1268 Static void 1269 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1270 { 1271 struct ehci_softc *sc = bus->hci_private; 1272 1273 if (dma->block->flags & USB_DMA_RESERVE) { 1274 usb_reserve_freem(&sc->sc_dma_reserve, 1275 dma); 1276 return; 1277 } 1278 usb_freemem(&sc->sc_bus, dma); 1279 } 1280 1281 Static usbd_xfer_handle 1282 ehci_allocx(struct usbd_bus *bus) 1283 { 1284 struct ehci_softc *sc = bus->hci_private; 1285 usbd_xfer_handle xfer; 1286 1287 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1288 if (xfer != NULL) { 1289 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1290 #ifdef DIAGNOSTIC 1291 if (xfer->busy_free != XFER_FREE) { 1292 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1293 xfer->busy_free); 1294 } 1295 #endif 1296 } else { 1297 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT); 1298 } 1299 if (xfer != NULL) { 1300 memset(xfer, 0, sizeof(struct ehci_xfer)); 1301 #ifdef DIAGNOSTIC 1302 EXFER(xfer)->isdone = 1; 1303 xfer->busy_free = XFER_BUSY; 1304 #endif 1305 } 1306 return (xfer); 1307 } 1308 1309 Static void 1310 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1311 { 1312 struct ehci_softc *sc = bus->hci_private; 1313 1314 #ifdef DIAGNOSTIC 1315 if (xfer->busy_free != XFER_BUSY) { 1316 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1317 xfer->busy_free); 1318 } 1319 xfer->busy_free = XFER_FREE; 1320 if (!EXFER(xfer)->isdone) { 1321 printf("ehci_freex: !isdone\n"); 1322 } 1323 #endif 1324 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1325 } 1326 1327 Static void 1328 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1329 { 1330 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1331 1332 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1333 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1334 #ifdef EHCI_DEBUG 1335 if (ehcidebug) 1336 usbd_dump_pipe(pipe); 1337 #endif 1338 epipe->nexttoggle = 0; 1339 } 1340 1341 Static void 1342 ehci_noop(usbd_pipe_handle pipe) 1343 { 1344 } 1345 1346 #ifdef EHCI_DEBUG 1347 Static void 1348 ehci_dump_regs(ehci_softc_t *sc) 1349 { 1350 int i; 1351 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1352 EOREAD4(sc, EHCI_USBCMD), 1353 EOREAD4(sc, EHCI_USBSTS), 1354 EOREAD4(sc, EHCI_USBINTR)); 1355 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1356 EOREAD4(sc, EHCI_FRINDEX), 1357 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1358 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1359 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1360 for (i = 1; i <= sc->sc_noport; i++) 1361 printf("port %d status=0x%08x\n", i, 1362 EOREAD4(sc, EHCI_PORTSC(i))); 1363 } 1364 1365 /* 1366 * Unused function - this is meant to be called from a kernel 1367 * debugger. 1368 */ 1369 void 1370 ehci_dump(void) 1371 { 1372 ehci_dump_regs(theehci); 1373 } 1374 1375 Static void 1376 ehci_dump_link(ehci_link_t link, int type) 1377 { 1378 link = le32toh(link); 1379 printf("0x%08x", link); 1380 if (link & EHCI_LINK_TERMINATE) 1381 printf("<T>"); 1382 else { 1383 printf("<"); 1384 if (type) { 1385 switch (EHCI_LINK_TYPE(link)) { 1386 case EHCI_LINK_ITD: printf("ITD"); break; 1387 case EHCI_LINK_QH: printf("QH"); break; 1388 case EHCI_LINK_SITD: printf("SITD"); break; 1389 case EHCI_LINK_FSTN: printf("FSTN"); break; 1390 } 1391 } 1392 printf(">"); 1393 } 1394 } 1395 1396 Static void 1397 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1398 { 1399 int i; 1400 u_int32_t stop; 1401 1402 stop = 0; 1403 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1404 ehci_dump_sqtd(sqtd); 1405 usb_syncmem(&sqtd->dma, 1406 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1407 sizeof(sqtd->qtd), 1408 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1409 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1410 usb_syncmem(&sqtd->dma, 1411 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1412 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1413 } 1414 if (sqtd) 1415 printf("dump aborted, too many TDs\n"); 1416 } 1417 1418 Static void 1419 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1420 { 1421 usb_syncmem(&sqtd->dma, sqtd->offs, 1422 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1423 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1424 ehci_dump_qtd(&sqtd->qtd); 1425 usb_syncmem(&sqtd->dma, sqtd->offs, 1426 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1427 } 1428 1429 Static void 1430 ehci_dump_qtd(ehci_qtd_t *qtd) 1431 { 1432 u_int32_t s; 1433 char sbuf[128]; 1434 1435 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1436 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1437 printf("\n"); 1438 s = le32toh(qtd->qtd_status); 1439 snprintb(sbuf, sizeof(sbuf), 1440 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1441 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1442 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1443 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1444 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1445 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1446 EHCI_QTD_GET_PID(s), sbuf); 1447 for (s = 0; s < 5; s++) 1448 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1449 } 1450 1451 Static void 1452 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1453 { 1454 ehci_qh_t *qh = &sqh->qh; 1455 u_int32_t endp, endphub; 1456 1457 usb_syncmem(&sqh->dma, sqh->offs, 1458 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1459 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1460 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1461 endp = le32toh(qh->qh_endp); 1462 printf(" endp=0x%08x\n", endp); 1463 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1464 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1465 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1466 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1467 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1468 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1469 EHCI_QH_GET_NRL(endp)); 1470 endphub = le32toh(qh->qh_endphub); 1471 printf(" endphub=0x%08x\n", endphub); 1472 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1473 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1474 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1475 EHCI_QH_GET_MULT(endphub)); 1476 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1477 printf("Overlay qTD:\n"); 1478 ehci_dump_qtd(&qh->qh_qtd); 1479 usb_syncmem(&sqh->dma, sqh->offs, 1480 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1481 } 1482 1483 #if notyet 1484 Static void 1485 ehci_dump_itd(struct ehci_soft_itd *itd) 1486 { 1487 ehci_isoc_trans_t t; 1488 ehci_isoc_bufr_ptr_t b, b2, b3; 1489 int i; 1490 1491 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1492 1493 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1494 t = le32toh(itd->itd.itd_ctl[i]); 1495 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1496 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1497 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1498 EHCI_ITD_GET_OFFS(t)); 1499 } 1500 printf("ITDbufr: "); 1501 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1502 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1503 1504 b = le32toh(itd->itd.itd_bufr[0]); 1505 b2 = le32toh(itd->itd.itd_bufr[1]); 1506 b3 = le32toh(itd->itd.itd_bufr[2]); 1507 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1508 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1509 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1510 } 1511 1512 Static void 1513 ehci_dump_sitd(struct ehci_soft_itd *itd) 1514 { 1515 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1516 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1517 itd->xfer_next, itd->physaddr, itd->slot); 1518 } 1519 #endif 1520 1521 #ifdef DIAGNOSTIC 1522 Static void 1523 ehci_dump_exfer(struct ehci_xfer *ex) 1524 { 1525 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1526 } 1527 #endif 1528 #endif 1529 1530 Static usbd_status 1531 ehci_open(usbd_pipe_handle pipe) 1532 { 1533 usbd_device_handle dev = pipe->device; 1534 ehci_softc_t *sc = dev->bus->hci_private; 1535 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1536 u_int8_t addr = dev->address; 1537 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1538 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1539 ehci_soft_qh_t *sqh; 1540 usbd_status err; 1541 int s; 1542 int ival, speed, naks; 1543 int hshubaddr, hshubport; 1544 1545 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1546 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1547 1548 if (dev->myhsport) { 1549 /* 1550 * When directly attached FS/LS device while doing embedded 1551 * transaction translations and we are the hub, set the hub 1552 * adddress to 0 (us). 1553 */ 1554 if (!(sc->sc_flags & EHCIF_ETTF) 1555 || (dev->myhsport->parent->address != sc->sc_addr)) { 1556 hshubaddr = dev->myhsport->parent->address; 1557 } else { 1558 hshubaddr = 0; 1559 } 1560 hshubport = dev->myhsport->portno; 1561 } else { 1562 hshubaddr = 0; 1563 hshubport = 0; 1564 } 1565 1566 if (sc->sc_dying) 1567 return (USBD_IOERROR); 1568 1569 /* toggle state needed for bulk endpoints */ 1570 epipe->nexttoggle = pipe->endpoint->datatoggle; 1571 1572 if (addr == sc->sc_addr) { 1573 switch (ed->bEndpointAddress) { 1574 case USB_CONTROL_ENDPOINT: 1575 pipe->methods = &ehci_root_ctrl_methods; 1576 break; 1577 case UE_DIR_IN | EHCI_INTR_ENDPT: 1578 pipe->methods = &ehci_root_intr_methods; 1579 break; 1580 default: 1581 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1582 ed->bEndpointAddress)); 1583 return (USBD_INVAL); 1584 } 1585 return (USBD_NORMAL_COMPLETION); 1586 } 1587 1588 /* XXX All this stuff is only valid for async. */ 1589 switch (dev->speed) { 1590 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1591 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1592 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1593 default: panic("ehci_open: bad device speed %d", dev->speed); 1594 } 1595 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1596 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1597 "isoc endpoint.\n"); 1598 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1599 "attached to a USB2 hub, and transaction translations are " 1600 "not yet supported.\n"); 1601 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1602 "root hub instead.\n"); 1603 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1604 hshubaddr, hshubport)); 1605 return USBD_INVAL; 1606 } 1607 1608 /* 1609 * For interrupt transfer, nak throttling must be disabled, but for 1610 * the other transfer type, nak throttling should be enabled from the 1611 * veiwpoint that avoids the memory thrashing. 1612 */ 1613 naks = (xfertype == UE_INTERRUPT) ? 0 1614 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1615 1616 /* Allocate sqh for everything, save isoc xfers */ 1617 if (xfertype != UE_ISOCHRONOUS) { 1618 sqh = ehci_alloc_sqh(sc); 1619 if (sqh == NULL) 1620 return (USBD_NOMEM); 1621 /* qh_link filled when the QH is added */ 1622 sqh->qh.qh_endp = htole32( 1623 EHCI_QH_SET_ADDR(addr) | 1624 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1625 EHCI_QH_SET_EPS(speed) | 1626 EHCI_QH_DTC | 1627 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1628 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1629 EHCI_QH_CTL : 0) | 1630 EHCI_QH_SET_NRL(naks) 1631 ); 1632 sqh->qh.qh_endphub = htole32( 1633 EHCI_QH_SET_MULT(1) | 1634 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1635 ); 1636 if (speed != EHCI_QH_SPEED_HIGH) 1637 sqh->qh.qh_endphub |= htole32( 1638 EHCI_QH_SET_PORT(hshubport) | 1639 EHCI_QH_SET_HUBA(hshubaddr) | 1640 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1641 ); 1642 sqh->qh.qh_curqtd = EHCI_NULL; 1643 /* Fill the overlay qTD */ 1644 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1645 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1646 sqh->qh.qh_qtd.qtd_status = htole32(0); 1647 1648 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1649 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1650 epipe->sqh = sqh; 1651 } else { 1652 sqh = NULL; 1653 } /*xfertype == UE_ISOC*/ 1654 1655 switch (xfertype) { 1656 case UE_CONTROL: 1657 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1658 0, &epipe->u.ctl.reqdma); 1659 #ifdef EHCI_DEBUG 1660 if (err) 1661 printf("ehci_open: usb_allocmem()=%d\n", err); 1662 #endif 1663 if (err) 1664 goto bad; 1665 pipe->methods = &ehci_device_ctrl_methods; 1666 s = splusb(); 1667 ehci_add_qh(sqh, sc->sc_async_head); 1668 splx(s); 1669 break; 1670 case UE_BULK: 1671 pipe->methods = &ehci_device_bulk_methods; 1672 s = splusb(); 1673 ehci_add_qh(sqh, sc->sc_async_head); 1674 splx(s); 1675 break; 1676 case UE_INTERRUPT: 1677 pipe->methods = &ehci_device_intr_methods; 1678 ival = pipe->interval; 1679 if (ival == USBD_DEFAULT_INTERVAL) { 1680 if (speed == EHCI_QH_SPEED_HIGH) { 1681 if (ed->bInterval > 16) { 1682 /* 1683 * illegal with high-speed, but there 1684 * were documentation bugs in the spec, 1685 * so be generous 1686 */ 1687 ival = 256; 1688 } else 1689 ival = (1 << (ed->bInterval - 1)) / 8; 1690 } else 1691 ival = ed->bInterval; 1692 } 1693 err = ehci_device_setintr(sc, sqh, ival); 1694 if (err) 1695 goto bad; 1696 break; 1697 case UE_ISOCHRONOUS: 1698 pipe->methods = &ehci_device_isoc_methods; 1699 if (ed->bInterval == 0 || ed->bInterval > 16) { 1700 printf("ehci: opening pipe with invalid bInterval\n"); 1701 err = USBD_INVAL; 1702 goto bad; 1703 } 1704 if (UGETW(ed->wMaxPacketSize) == 0) { 1705 printf("ehci: zero length endpoint open request\n"); 1706 err = USBD_INVAL; 1707 goto bad; 1708 } 1709 epipe->u.isoc.next_frame = 0; 1710 epipe->u.isoc.cur_xfers = 0; 1711 break; 1712 default: 1713 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1714 err = USBD_INVAL; 1715 goto bad; 1716 } 1717 return (USBD_NORMAL_COMPLETION); 1718 1719 bad: 1720 if (sqh != NULL) 1721 ehci_free_sqh(sc, sqh); 1722 return (err); 1723 } 1724 1725 /* 1726 * Add an ED to the schedule. Called at splusb(). 1727 */ 1728 Static void 1729 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1730 { 1731 1732 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1733 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1734 sqh->next = head->next; 1735 sqh->qh.qh_link = head->qh.qh_link; 1736 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1737 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1738 head->next = sqh; 1739 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1740 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1741 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1742 1743 #ifdef EHCI_DEBUG 1744 if (ehcidebug > 5) { 1745 printf("ehci_add_qh:\n"); 1746 ehci_dump_sqh(sqh); 1747 } 1748 #endif 1749 } 1750 1751 /* 1752 * Remove an ED from the schedule. Called at splusb(). 1753 */ 1754 Static void 1755 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1756 { 1757 ehci_soft_qh_t *p; 1758 1759 /* XXX */ 1760 for (p = head; p != NULL && p->next != sqh; p = p->next) 1761 ; 1762 if (p == NULL) 1763 panic("ehci_rem_qh: ED not found"); 1764 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1765 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1766 p->next = sqh->next; 1767 p->qh.qh_link = sqh->qh.qh_link; 1768 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1769 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1770 1771 ehci_sync_hc(sc); 1772 } 1773 1774 Static void 1775 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1776 { 1777 int i; 1778 u_int32_t status; 1779 1780 /* Save toggle bit and ping status. */ 1781 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1782 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1783 status = sqh->qh.qh_qtd.qtd_status & 1784 htole32(EHCI_QTD_TOGGLE_MASK | 1785 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1786 /* Set HALTED to make hw leave it alone. */ 1787 sqh->qh.qh_qtd.qtd_status = 1788 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1789 usb_syncmem(&sqh->dma, 1790 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1791 sizeof(sqh->qh.qh_qtd.qtd_status), 1792 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1793 sqh->qh.qh_curqtd = 0; 1794 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1795 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1796 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1797 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1798 sqh->sqtd = sqtd; 1799 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1800 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1801 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1802 sqh->qh.qh_qtd.qtd_status = status; 1803 usb_syncmem(&sqh->dma, 1804 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1805 sizeof(sqh->qh.qh_qtd.qtd_status), 1806 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1807 } 1808 1809 /* 1810 * Ensure that the HC has released all references to the QH. We do this 1811 * by asking for a Async Advance Doorbell interrupt and then we wait for 1812 * the interrupt. 1813 * To make this easier we first obtain exclusive use of the doorbell. 1814 */ 1815 Static void 1816 ehci_sync_hc(ehci_softc_t *sc) 1817 { 1818 int s, error; 1819 1820 if (sc->sc_dying) { 1821 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1822 return; 1823 } 1824 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1825 mutex_enter(&sc->sc_doorbell_lock); /* get doorbell */ 1826 s = splhardusb(); 1827 /* ask for doorbell */ 1828 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1829 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1830 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1831 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */ 1832 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1833 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1834 splx(s); 1835 mutex_exit(&sc->sc_doorbell_lock); /* release doorbell */ 1836 #ifdef DIAGNOSTIC 1837 if (error) 1838 printf("ehci_sync_hc: tsleep() = %d\n", error); 1839 #endif 1840 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1841 } 1842 1843 /*Call at splusb*/ 1844 Static void 1845 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1846 { 1847 struct ehci_soft_itd *itd, *prev; 1848 1849 prev = NULL; 1850 1851 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1852 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1853 1854 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1855 prev = itd->u.frame_list.prev; 1856 /* Unlink itd from hardware chain, or frame array */ 1857 if (prev == NULL) { /* We're at the table head */ 1858 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1859 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1860 usb_syncmem(&sc->sc_fldma, 1861 sizeof(ehci_link_t) * itd->slot, 1862 sizeof(ehci_link_t), 1863 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1864 1865 if (itd->u.frame_list.next != NULL) 1866 itd->u.frame_list.next->u.frame_list.prev = NULL; 1867 } else { 1868 /* XXX this part is untested... */ 1869 prev->itd.itd_next = itd->itd.itd_next; 1870 usb_syncmem(&itd->dma, 1871 itd->offs + offsetof(ehci_itd_t, itd_next), 1872 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1873 1874 prev->u.frame_list.next = itd->u.frame_list.next; 1875 if (itd->u.frame_list.next != NULL) 1876 itd->u.frame_list.next->u.frame_list.prev = prev; 1877 } 1878 } 1879 1880 prev = NULL; 1881 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1882 if (prev != NULL) 1883 ehci_free_itd(sc, prev); 1884 prev = itd; 1885 } 1886 if (prev) 1887 ehci_free_itd(sc, prev); 1888 exfer->itdstart = NULL; 1889 exfer->itdend = NULL; 1890 } 1891 1892 /***********/ 1893 1894 /* 1895 * Data structures and routines to emulate the root hub. 1896 */ 1897 Static usb_device_descriptor_t ehci_devd = { 1898 USB_DEVICE_DESCRIPTOR_SIZE, 1899 UDESC_DEVICE, /* type */ 1900 {0x00, 0x02}, /* USB version */ 1901 UDCLASS_HUB, /* class */ 1902 UDSUBCLASS_HUB, /* subclass */ 1903 UDPROTO_HSHUBSTT, /* protocol */ 1904 64, /* max packet */ 1905 {0},{0},{0x00,0x01}, /* device id */ 1906 1,2,0, /* string indicies */ 1907 1 /* # of configurations */ 1908 }; 1909 1910 Static const usb_device_qualifier_t ehci_odevd = { 1911 USB_DEVICE_DESCRIPTOR_SIZE, 1912 UDESC_DEVICE_QUALIFIER, /* type */ 1913 {0x00, 0x02}, /* USB version */ 1914 UDCLASS_HUB, /* class */ 1915 UDSUBCLASS_HUB, /* subclass */ 1916 UDPROTO_FSHUB, /* protocol */ 1917 64, /* max packet */ 1918 1, /* # of configurations */ 1919 0 1920 }; 1921 1922 Static const usb_config_descriptor_t ehci_confd = { 1923 USB_CONFIG_DESCRIPTOR_SIZE, 1924 UDESC_CONFIG, 1925 {USB_CONFIG_DESCRIPTOR_SIZE + 1926 USB_INTERFACE_DESCRIPTOR_SIZE + 1927 USB_ENDPOINT_DESCRIPTOR_SIZE}, 1928 1, 1929 1, 1930 0, 1931 UC_ATTR_MBO | UC_SELF_POWERED, 1932 0 /* max power */ 1933 }; 1934 1935 Static const usb_interface_descriptor_t ehci_ifcd = { 1936 USB_INTERFACE_DESCRIPTOR_SIZE, 1937 UDESC_INTERFACE, 1938 0, 1939 0, 1940 1, 1941 UICLASS_HUB, 1942 UISUBCLASS_HUB, 1943 UIPROTO_HSHUBSTT, 1944 0 1945 }; 1946 1947 Static const usb_endpoint_descriptor_t ehci_endpd = { 1948 USB_ENDPOINT_DESCRIPTOR_SIZE, 1949 UDESC_ENDPOINT, 1950 UE_DIR_IN | EHCI_INTR_ENDPT, 1951 UE_INTERRUPT, 1952 {8, 0}, /* max packet */ 1953 12 1954 }; 1955 1956 Static const usb_hub_descriptor_t ehci_hubd = { 1957 USB_HUB_DESCRIPTOR_SIZE, 1958 UDESC_HUB, 1959 0, 1960 {0,0}, 1961 0, 1962 0, 1963 {""}, 1964 {""}, 1965 }; 1966 1967 /* 1968 * Simulate a hardware hub by handling all the necessary requests. 1969 */ 1970 Static usbd_status 1971 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 1972 { 1973 usbd_status err; 1974 1975 /* Insert last in queue. */ 1976 err = usb_insert_transfer(xfer); 1977 if (err) 1978 return (err); 1979 1980 /* Pipe isn't running, start first */ 1981 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 1982 } 1983 1984 Static usbd_status 1985 ehci_root_ctrl_start(usbd_xfer_handle xfer) 1986 { 1987 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 1988 usb_device_request_t *req; 1989 void *buf = NULL; 1990 int port, i; 1991 int s, len, value, index, l, totlen = 0; 1992 usb_port_status_t ps; 1993 usb_hub_descriptor_t hubd; 1994 usbd_status err; 1995 u_int32_t v; 1996 1997 if (sc->sc_dying) 1998 return (USBD_IOERROR); 1999 2000 #ifdef DIAGNOSTIC 2001 if (!(xfer->rqflags & URQ_REQUEST)) 2002 /* XXX panic */ 2003 return (USBD_INVAL); 2004 #endif 2005 req = &xfer->request; 2006 2007 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2008 req->bmRequestType, req->bRequest)); 2009 2010 len = UGETW(req->wLength); 2011 value = UGETW(req->wValue); 2012 index = UGETW(req->wIndex); 2013 2014 if (len != 0) 2015 buf = KERNADDR(&xfer->dmabuf, 0); 2016 2017 #define C(x,y) ((x) | ((y) << 8)) 2018 switch(C(req->bRequest, req->bmRequestType)) { 2019 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2020 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2021 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2022 /* 2023 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2024 * for the integrated root hub. 2025 */ 2026 break; 2027 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2028 if (len > 0) { 2029 *(u_int8_t *)buf = sc->sc_conf; 2030 totlen = 1; 2031 } 2032 break; 2033 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2034 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2035 if (len == 0) 2036 break; 2037 switch(value >> 8) { 2038 case UDESC_DEVICE: 2039 if ((value & 0xff) != 0) { 2040 err = USBD_IOERROR; 2041 goto ret; 2042 } 2043 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2044 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2045 memcpy(buf, &ehci_devd, l); 2046 break; 2047 /* 2048 * We can't really operate at another speed, but the spec says 2049 * we need this descriptor. 2050 */ 2051 case UDESC_DEVICE_QUALIFIER: 2052 if ((value & 0xff) != 0) { 2053 err = USBD_IOERROR; 2054 goto ret; 2055 } 2056 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2057 memcpy(buf, &ehci_odevd, l); 2058 break; 2059 /* 2060 * We can't really operate at another speed, but the spec says 2061 * we need this descriptor. 2062 */ 2063 case UDESC_OTHER_SPEED_CONFIGURATION: 2064 case UDESC_CONFIG: 2065 if ((value & 0xff) != 0) { 2066 err = USBD_IOERROR; 2067 goto ret; 2068 } 2069 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2070 memcpy(buf, &ehci_confd, l); 2071 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2072 value >> 8; 2073 buf = (char *)buf + l; 2074 len -= l; 2075 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2076 totlen += l; 2077 memcpy(buf, &ehci_ifcd, l); 2078 buf = (char *)buf + l; 2079 len -= l; 2080 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2081 totlen += l; 2082 memcpy(buf, &ehci_endpd, l); 2083 break; 2084 case UDESC_STRING: 2085 #define sd ((usb_string_descriptor_t *)buf) 2086 switch (value & 0xff) { 2087 case 0: /* Language table */ 2088 totlen = usb_makelangtbl(sd, len); 2089 break; 2090 case 1: /* Vendor */ 2091 totlen = usb_makestrdesc(sd, len, 2092 sc->sc_vendor); 2093 break; 2094 case 2: /* Product */ 2095 totlen = usb_makestrdesc(sd, len, 2096 "EHCI root hub"); 2097 break; 2098 } 2099 #undef sd 2100 break; 2101 default: 2102 err = USBD_IOERROR; 2103 goto ret; 2104 } 2105 break; 2106 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2107 if (len > 0) { 2108 *(u_int8_t *)buf = 0; 2109 totlen = 1; 2110 } 2111 break; 2112 case C(UR_GET_STATUS, UT_READ_DEVICE): 2113 if (len > 1) { 2114 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2115 totlen = 2; 2116 } 2117 break; 2118 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2119 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2120 if (len > 1) { 2121 USETW(((usb_status_t *)buf)->wStatus, 0); 2122 totlen = 2; 2123 } 2124 break; 2125 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2126 if (value >= USB_MAX_DEVICES) { 2127 err = USBD_IOERROR; 2128 goto ret; 2129 } 2130 sc->sc_addr = value; 2131 break; 2132 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2133 if (value != 0 && value != 1) { 2134 err = USBD_IOERROR; 2135 goto ret; 2136 } 2137 sc->sc_conf = value; 2138 break; 2139 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2140 break; 2141 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2142 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2143 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2144 err = USBD_IOERROR; 2145 goto ret; 2146 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2147 break; 2148 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2149 break; 2150 /* Hub requests */ 2151 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2152 break; 2153 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2154 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2155 "port=%d feature=%d\n", 2156 index, value)); 2157 if (index < 1 || index > sc->sc_noport) { 2158 err = USBD_IOERROR; 2159 goto ret; 2160 } 2161 port = EHCI_PORTSC(index); 2162 v = EOREAD4(sc, port); 2163 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2164 v &= ~EHCI_PS_CLEAR; 2165 switch(value) { 2166 case UHF_PORT_ENABLE: 2167 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2168 break; 2169 case UHF_PORT_SUSPEND: 2170 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2171 break; 2172 v &= ~EHCI_PS_SUSP; 2173 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2174 /* see USB2 spec ch. 7.1.7.7 */ 2175 usb_delay_ms(&sc->sc_bus, 20); 2176 EOWRITE4(sc, port, v); 2177 usb_delay_ms(&sc->sc_bus, 2); 2178 #ifdef DEBUG 2179 v = EOREAD4(sc, port); 2180 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2181 printf("ehci: resume failed: %x\n", v); 2182 #endif 2183 break; 2184 case UHF_PORT_POWER: 2185 if (sc->sc_hasppc) 2186 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2187 break; 2188 case UHF_PORT_TEST: 2189 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2190 "%d\n", index)); 2191 break; 2192 case UHF_PORT_INDICATOR: 2193 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2194 "%d\n", index)); 2195 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2196 break; 2197 case UHF_C_PORT_CONNECTION: 2198 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2199 break; 2200 case UHF_C_PORT_ENABLE: 2201 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2202 break; 2203 case UHF_C_PORT_SUSPEND: 2204 /* how? */ 2205 break; 2206 case UHF_C_PORT_OVER_CURRENT: 2207 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2208 break; 2209 case UHF_C_PORT_RESET: 2210 sc->sc_isreset[index] = 0; 2211 break; 2212 default: 2213 err = USBD_IOERROR; 2214 goto ret; 2215 } 2216 #if 0 2217 switch(value) { 2218 case UHF_C_PORT_CONNECTION: 2219 case UHF_C_PORT_ENABLE: 2220 case UHF_C_PORT_SUSPEND: 2221 case UHF_C_PORT_OVER_CURRENT: 2222 case UHF_C_PORT_RESET: 2223 default: 2224 break; 2225 } 2226 #endif 2227 break; 2228 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2229 if (len == 0) 2230 break; 2231 if ((value & 0xff) != 0) { 2232 err = USBD_IOERROR; 2233 goto ret; 2234 } 2235 hubd = ehci_hubd; 2236 hubd.bNbrPorts = sc->sc_noport; 2237 v = EOREAD4(sc, EHCI_HCSPARAMS); 2238 USETW(hubd.wHubCharacteristics, 2239 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2240 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2241 ? UHD_PORT_IND : 0); 2242 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2243 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2244 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2245 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2246 l = min(len, hubd.bDescLength); 2247 totlen = l; 2248 memcpy(buf, &hubd, l); 2249 break; 2250 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2251 if (len != 4) { 2252 err = USBD_IOERROR; 2253 goto ret; 2254 } 2255 memset(buf, 0, len); /* ? XXX */ 2256 totlen = len; 2257 break; 2258 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2259 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2260 index)); 2261 if (index < 1 || index > sc->sc_noport) { 2262 err = USBD_IOERROR; 2263 goto ret; 2264 } 2265 if (len != 4) { 2266 err = USBD_IOERROR; 2267 goto ret; 2268 } 2269 v = EOREAD4(sc, EHCI_PORTSC(index)); 2270 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2271 2272 i = UPS_HIGH_SPEED; 2273 #if 0 2274 if (sc->sc_flags & EHCIF_ETTF) { 2275 /* 2276 * If we are doing embedded transaction translation, 2277 * then directly attached LS/FS devices are reset by 2278 * the EHCI controller itself. PSPD is encoded 2279 * the same way as in USBSTATUS. 2280 */ 2281 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2282 } 2283 #endif 2284 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2285 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2286 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2287 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2288 if (v & EHCI_PS_PR) i |= UPS_RESET; 2289 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2290 if (sc->sc_vendor_port_status) 2291 i = sc->sc_vendor_port_status(sc, v, i); 2292 USETW(ps.wPortStatus, i); 2293 i = 0; 2294 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2295 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2296 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2297 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2298 USETW(ps.wPortChange, i); 2299 l = min(len, sizeof ps); 2300 memcpy(buf, &ps, l); 2301 totlen = l; 2302 break; 2303 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2304 err = USBD_IOERROR; 2305 goto ret; 2306 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2307 break; 2308 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2309 if (index < 1 || index > sc->sc_noport) { 2310 err = USBD_IOERROR; 2311 goto ret; 2312 } 2313 port = EHCI_PORTSC(index); 2314 v = EOREAD4(sc, port); 2315 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2316 v &= ~EHCI_PS_CLEAR; 2317 switch(value) { 2318 case UHF_PORT_ENABLE: 2319 EOWRITE4(sc, port, v | EHCI_PS_PE); 2320 break; 2321 case UHF_PORT_SUSPEND: 2322 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2323 break; 2324 case UHF_PORT_RESET: 2325 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2326 index)); 2327 if (EHCI_PS_IS_LOWSPEED(v) 2328 && sc->sc_ncomp > 0 2329 && !(sc->sc_flags & EHCIF_ETTF)) { 2330 /* 2331 * Low speed device on non-ETTF controller or 2332 * unaccompanied controller, give up ownership. 2333 */ 2334 ehci_disown(sc, index, 1); 2335 break; 2336 } 2337 /* Start reset sequence. */ 2338 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2339 EOWRITE4(sc, port, v | EHCI_PS_PR); 2340 /* Wait for reset to complete. */ 2341 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2342 if (sc->sc_dying) { 2343 err = USBD_IOERROR; 2344 goto ret; 2345 } 2346 /* 2347 * An embedded transaction translater will automatically 2348 * terminate the reset sequence so there's no need to 2349 * it. 2350 */ 2351 v = EOREAD4(sc, port); 2352 if (v & EHCI_PS_PR) { 2353 /* Terminate reset sequence. */ 2354 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2355 /* Wait for HC to complete reset. */ 2356 usb_delay_ms(&sc->sc_bus, 2357 EHCI_PORT_RESET_COMPLETE); 2358 if (sc->sc_dying) { 2359 err = USBD_IOERROR; 2360 goto ret; 2361 } 2362 } 2363 2364 v = EOREAD4(sc, port); 2365 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2366 if (v & EHCI_PS_PR) { 2367 printf("%s: port reset timeout\n", 2368 device_xname(sc->sc_dev)); 2369 return (USBD_TIMEOUT); 2370 } 2371 if (!(v & EHCI_PS_PE)) { 2372 /* Not a high speed device, give up ownership.*/ 2373 ehci_disown(sc, index, 0); 2374 break; 2375 } 2376 sc->sc_isreset[index] = 1; 2377 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2378 index, v)); 2379 break; 2380 case UHF_PORT_POWER: 2381 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2382 "%d (has PPC = %d)\n", index, 2383 sc->sc_hasppc)); 2384 if (sc->sc_hasppc) 2385 EOWRITE4(sc, port, v | EHCI_PS_PP); 2386 break; 2387 case UHF_PORT_TEST: 2388 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2389 "%d\n", index)); 2390 break; 2391 case UHF_PORT_INDICATOR: 2392 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2393 "%d\n", index)); 2394 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2395 break; 2396 default: 2397 err = USBD_IOERROR; 2398 goto ret; 2399 } 2400 break; 2401 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2402 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2403 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2404 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2405 break; 2406 default: 2407 err = USBD_IOERROR; 2408 goto ret; 2409 } 2410 xfer->actlen = totlen; 2411 err = USBD_NORMAL_COMPLETION; 2412 ret: 2413 xfer->status = err; 2414 s = splusb(); 2415 usb_transfer_complete(xfer); 2416 splx(s); 2417 return (USBD_IN_PROGRESS); 2418 } 2419 2420 Static void 2421 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2422 { 2423 int port; 2424 u_int32_t v; 2425 2426 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2427 #ifdef DIAGNOSTIC 2428 if (sc->sc_npcomp != 0) { 2429 int i = (index-1) / sc->sc_npcomp; 2430 if (i >= sc->sc_ncomp) 2431 printf("%s: strange port\n", 2432 device_xname(sc->sc_dev)); 2433 else 2434 printf("%s: handing over %s speed device on " 2435 "port %d to %s\n", 2436 device_xname(sc->sc_dev), 2437 lowspeed ? "low" : "full", 2438 index, device_xname(sc->sc_comps[i])); 2439 } else { 2440 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2441 } 2442 #endif 2443 port = EHCI_PORTSC(index); 2444 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2445 EOWRITE4(sc, port, v | EHCI_PS_PO); 2446 } 2447 2448 /* Abort a root control request. */ 2449 Static void 2450 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2451 { 2452 /* Nothing to do, all transfers are synchronous. */ 2453 } 2454 2455 /* Close the root pipe. */ 2456 Static void 2457 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2458 { 2459 DPRINTF(("ehci_root_ctrl_close\n")); 2460 /* Nothing to do. */ 2461 } 2462 2463 Static void 2464 ehci_root_intr_done(usbd_xfer_handle xfer) 2465 { 2466 xfer->hcpriv = NULL; 2467 } 2468 2469 Static usbd_status 2470 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2471 { 2472 usbd_status err; 2473 2474 /* Insert last in queue. */ 2475 err = usb_insert_transfer(xfer); 2476 if (err) 2477 return (err); 2478 2479 /* Pipe isn't running, start first */ 2480 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2481 } 2482 2483 Static usbd_status 2484 ehci_root_intr_start(usbd_xfer_handle xfer) 2485 { 2486 usbd_pipe_handle pipe = xfer->pipe; 2487 ehci_softc_t *sc = pipe->device->bus->hci_private; 2488 2489 if (sc->sc_dying) 2490 return (USBD_IOERROR); 2491 2492 sc->sc_intrxfer = xfer; 2493 2494 return (USBD_IN_PROGRESS); 2495 } 2496 2497 /* Abort a root interrupt request. */ 2498 Static void 2499 ehci_root_intr_abort(usbd_xfer_handle xfer) 2500 { 2501 int s; 2502 2503 if (xfer->pipe->intrxfer == xfer) { 2504 DPRINTF(("ehci_root_intr_abort: remove\n")); 2505 xfer->pipe->intrxfer = NULL; 2506 } 2507 xfer->status = USBD_CANCELLED; 2508 s = splusb(); 2509 usb_transfer_complete(xfer); 2510 splx(s); 2511 } 2512 2513 /* Close the root pipe. */ 2514 Static void 2515 ehci_root_intr_close(usbd_pipe_handle pipe) 2516 { 2517 ehci_softc_t *sc = pipe->device->bus->hci_private; 2518 2519 DPRINTF(("ehci_root_intr_close\n")); 2520 2521 sc->sc_intrxfer = NULL; 2522 } 2523 2524 Static void 2525 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2526 { 2527 xfer->hcpriv = NULL; 2528 } 2529 2530 /************************/ 2531 2532 Static ehci_soft_qh_t * 2533 ehci_alloc_sqh(ehci_softc_t *sc) 2534 { 2535 ehci_soft_qh_t *sqh; 2536 usbd_status err; 2537 int i, offs; 2538 usb_dma_t dma; 2539 2540 if (sc->sc_freeqhs == NULL) { 2541 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2542 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2543 EHCI_PAGE_SIZE, &dma); 2544 #ifdef EHCI_DEBUG 2545 if (err) 2546 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2547 #endif 2548 if (err) 2549 return (NULL); 2550 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2551 offs = i * EHCI_SQH_SIZE; 2552 sqh = KERNADDR(&dma, offs); 2553 sqh->physaddr = DMAADDR(&dma, offs); 2554 sqh->dma = dma; 2555 sqh->offs = offs; 2556 sqh->next = sc->sc_freeqhs; 2557 sc->sc_freeqhs = sqh; 2558 } 2559 } 2560 sqh = sc->sc_freeqhs; 2561 sc->sc_freeqhs = sqh->next; 2562 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2563 sqh->next = NULL; 2564 return (sqh); 2565 } 2566 2567 Static void 2568 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2569 { 2570 sqh->next = sc->sc_freeqhs; 2571 sc->sc_freeqhs = sqh; 2572 } 2573 2574 Static ehci_soft_qtd_t * 2575 ehci_alloc_sqtd(ehci_softc_t *sc) 2576 { 2577 ehci_soft_qtd_t *sqtd; 2578 usbd_status err; 2579 int i, offs; 2580 usb_dma_t dma; 2581 int s; 2582 2583 if (sc->sc_freeqtds == NULL) { 2584 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2585 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2586 EHCI_PAGE_SIZE, &dma); 2587 #ifdef EHCI_DEBUG 2588 if (err) 2589 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2590 #endif 2591 if (err) 2592 return (NULL); 2593 s = splusb(); 2594 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2595 offs = i * EHCI_SQTD_SIZE; 2596 sqtd = KERNADDR(&dma, offs); 2597 sqtd->physaddr = DMAADDR(&dma, offs); 2598 sqtd->dma = dma; 2599 sqtd->offs = offs; 2600 sqtd->nextqtd = sc->sc_freeqtds; 2601 sc->sc_freeqtds = sqtd; 2602 } 2603 splx(s); 2604 } 2605 2606 s = splusb(); 2607 sqtd = sc->sc_freeqtds; 2608 sc->sc_freeqtds = sqtd->nextqtd; 2609 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2610 sqtd->nextqtd = NULL; 2611 sqtd->xfer = NULL; 2612 splx(s); 2613 2614 return (sqtd); 2615 } 2616 2617 Static void 2618 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2619 { 2620 int s; 2621 2622 s = splusb(); 2623 sqtd->nextqtd = sc->sc_freeqtds; 2624 sc->sc_freeqtds = sqtd; 2625 splx(s); 2626 } 2627 2628 Static usbd_status 2629 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2630 int alen, int rd, usbd_xfer_handle xfer, 2631 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2632 { 2633 ehci_soft_qtd_t *next, *cur; 2634 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2635 u_int32_t qtdstatus; 2636 int len, curlen, mps; 2637 int i, tog; 2638 usb_dma_t *dma = &xfer->dmabuf; 2639 u_int16_t flags = xfer->flags; 2640 2641 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2642 2643 len = alen; 2644 dataphys = DMAADDR(dma, 0); 2645 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2646 qtdstatus = EHCI_QTD_ACTIVE | 2647 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2648 EHCI_QTD_SET_CERR(3) 2649 /* IOC set below */ 2650 /* BYTES set below */ 2651 ; 2652 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2653 tog = epipe->nexttoggle; 2654 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2655 2656 cur = ehci_alloc_sqtd(sc); 2657 *sp = cur; 2658 if (cur == NULL) 2659 goto nomem; 2660 2661 usb_syncmem(dma, 0, alen, 2662 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2663 for (;;) { 2664 dataphyspage = EHCI_PAGE(dataphys); 2665 /* The EHCI hardware can handle at most 5 pages. */ 2666 if (dataphyslastpage - dataphyspage < 2667 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2668 /* we can handle it in this QTD */ 2669 curlen = len; 2670 } else { 2671 /* must use multiple TDs, fill as much as possible. */ 2672 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2673 EHCI_PAGE_OFFSET(dataphys); 2674 #ifdef DIAGNOSTIC 2675 if (curlen > len) { 2676 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2677 "len=0x%x offs=0x%x\n", curlen, len, 2678 EHCI_PAGE_OFFSET(dataphys)); 2679 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2680 dataphyslastpage, dataphyspage, 2681 dataphys); 2682 curlen = len; 2683 } 2684 #endif 2685 /* the length must be a multiple of the max size */ 2686 curlen -= curlen % mps; 2687 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2688 "curlen=%d\n", curlen)); 2689 #ifdef DIAGNOSTIC 2690 if (curlen == 0) 2691 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2692 #endif 2693 } 2694 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2695 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2696 dataphys, dataphyslastpage, 2697 len, curlen)); 2698 len -= curlen; 2699 2700 /* 2701 * Allocate another transfer if there's more data left, 2702 * or if force last short transfer flag is set and we're 2703 * allocating a multiple of the max packet size. 2704 */ 2705 if (len != 0 || 2706 ((curlen % mps) == 0 && !rd && curlen != 0 && 2707 (flags & USBD_FORCE_SHORT_XFER))) { 2708 next = ehci_alloc_sqtd(sc); 2709 if (next == NULL) 2710 goto nomem; 2711 nextphys = htole32(next->physaddr); 2712 } else { 2713 next = NULL; 2714 nextphys = EHCI_NULL; 2715 } 2716 2717 for (i = 0; i * EHCI_PAGE_SIZE < 2718 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2719 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2720 if (i != 0) /* use offset only in first buffer */ 2721 a = EHCI_PAGE(a); 2722 cur->qtd.qtd_buffer[i] = htole32(a); 2723 cur->qtd.qtd_buffer_hi[i] = 0; 2724 #ifdef DIAGNOSTIC 2725 if (i >= EHCI_QTD_NBUFFERS) { 2726 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2727 goto nomem; 2728 } 2729 #endif 2730 } 2731 cur->nextqtd = next; 2732 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2733 cur->qtd.qtd_status = 2734 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2735 cur->xfer = xfer; 2736 cur->len = curlen; 2737 2738 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2739 dataphys, dataphys + curlen)); 2740 /* adjust the toggle based on the number of packets in this 2741 qtd */ 2742 if (((curlen + mps - 1) / mps) & 1) { 2743 tog ^= 1; 2744 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2745 } 2746 if (next == NULL) 2747 break; 2748 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2749 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2750 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2751 if (len) 2752 dataphys += curlen; 2753 cur = next; 2754 } 2755 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2756 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2757 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2758 *ep = cur; 2759 epipe->nexttoggle = tog; 2760 2761 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2762 *sp, *ep)); 2763 2764 return (USBD_NORMAL_COMPLETION); 2765 2766 nomem: 2767 /* XXX free chain */ 2768 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2769 return (USBD_NOMEM); 2770 } 2771 2772 Static void 2773 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2774 ehci_soft_qtd_t *sqtdend) 2775 { 2776 ehci_soft_qtd_t *p; 2777 int i; 2778 2779 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2780 sqtd, sqtdend)); 2781 2782 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2783 p = sqtd->nextqtd; 2784 ehci_free_sqtd(sc, sqtd); 2785 } 2786 } 2787 2788 Static ehci_soft_itd_t * 2789 ehci_alloc_itd(ehci_softc_t *sc) 2790 { 2791 struct ehci_soft_itd *itd, *freeitd; 2792 usbd_status err; 2793 int i, s, offs, frindex, previndex; 2794 usb_dma_t dma; 2795 2796 s = splusb(); 2797 2798 /* Find an itd that wasn't freed this frame or last frame. This can 2799 * discard itds that were freed before frindex wrapped around 2800 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2801 * interrupt and fiddling with list when that happens */ 2802 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2803 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2804 2805 freeitd = NULL; 2806 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2807 if (itd == NULL) 2808 break; 2809 if (itd->slot != frindex && itd->slot != previndex) { 2810 freeitd = itd; 2811 break; 2812 } 2813 } 2814 2815 if (freeitd == NULL) { 2816 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2817 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2818 EHCI_PAGE_SIZE, &dma); 2819 2820 if (err) { 2821 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2822 return NULL; 2823 } 2824 2825 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2826 offs = i * EHCI_ITD_SIZE; 2827 itd = KERNADDR(&dma, offs); 2828 itd->physaddr = DMAADDR(&dma, offs); 2829 itd->dma = dma; 2830 itd->offs = offs; 2831 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2832 } 2833 freeitd = LIST_FIRST(&sc->sc_freeitds); 2834 } 2835 2836 itd = freeitd; 2837 LIST_REMOVE(itd, u.free_list); 2838 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2839 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2840 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2841 BUS_DMASYNC_PREREAD); 2842 2843 itd->u.frame_list.next = NULL; 2844 itd->u.frame_list.prev = NULL; 2845 itd->xfer_next = NULL; 2846 itd->slot = 0; 2847 splx(s); 2848 2849 return itd; 2850 } 2851 2852 Static void 2853 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2854 { 2855 int s; 2856 2857 s = splusb(); 2858 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2859 splx(s); 2860 } 2861 2862 /****************/ 2863 2864 /* 2865 * Close a reqular pipe. 2866 * Assumes that there are no pending transactions. 2867 */ 2868 Static void 2869 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2870 { 2871 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2872 ehci_softc_t *sc = pipe->device->bus->hci_private; 2873 ehci_soft_qh_t *sqh = epipe->sqh; 2874 int s; 2875 2876 s = splusb(); 2877 ehci_rem_qh(sc, sqh, head); 2878 splx(s); 2879 ehci_free_sqh(sc, epipe->sqh); 2880 } 2881 2882 /* 2883 * Abort a device request. 2884 * If this routine is called at splusb() it guarantees that the request 2885 * will be removed from the hardware scheduling and that the callback 2886 * for it will be called with USBD_CANCELLED status. 2887 * It's impossible to guarantee that the requested transfer will not 2888 * have happened since the hardware runs concurrently. 2889 * If the transaction has already happened we rely on the ordinary 2890 * interrupt processing to process it. 2891 * XXX This is most probably wrong. 2892 */ 2893 Static void 2894 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2895 { 2896 #define exfer EXFER(xfer) 2897 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2898 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2899 ehci_soft_qh_t *sqh = epipe->sqh; 2900 ehci_soft_qtd_t *sqtd; 2901 ehci_physaddr_t cur; 2902 u_int32_t qhstatus; 2903 int s; 2904 int hit; 2905 int wake; 2906 2907 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2908 2909 if (sc->sc_dying) { 2910 /* If we're dying, just do the software part. */ 2911 s = splusb(); 2912 xfer->status = status; /* make software ignore it */ 2913 callout_stop(&xfer->timeout_handle); 2914 usb_transfer_complete(xfer); 2915 splx(s); 2916 return; 2917 } 2918 2919 if (xfer->device->bus->intr_context) 2920 panic("ehci_abort_xfer: not in process context"); 2921 2922 /* 2923 * If an abort is already in progress then just wait for it to 2924 * complete and return. 2925 */ 2926 if (xfer->hcflags & UXFER_ABORTING) { 2927 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 2928 #ifdef DIAGNOSTIC 2929 if (status == USBD_TIMEOUT) 2930 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 2931 #endif 2932 /* Override the status which might be USBD_TIMEOUT. */ 2933 xfer->status = status; 2934 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 2935 xfer->hcflags |= UXFER_ABORTWAIT; 2936 while (xfer->hcflags & UXFER_ABORTING) 2937 tsleep(&xfer->hcflags, PZERO, "ehciaw", 0); 2938 return; 2939 } 2940 xfer->hcflags |= UXFER_ABORTING; 2941 2942 /* 2943 * Step 1: Make interrupt routine and hardware ignore xfer. 2944 */ 2945 s = splusb(); 2946 xfer->status = status; /* make software ignore it */ 2947 callout_stop(&xfer->timeout_handle); 2948 2949 usb_syncmem(&sqh->dma, 2950 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2951 sizeof(sqh->qh.qh_qtd.qtd_status), 2952 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2953 qhstatus = sqh->qh.qh_qtd.qtd_status; 2954 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 2955 usb_syncmem(&sqh->dma, 2956 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2957 sizeof(sqh->qh.qh_qtd.qtd_status), 2958 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2959 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 2960 usb_syncmem(&sqtd->dma, 2961 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2962 sizeof(sqtd->qtd.qtd_status), 2963 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2964 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 2965 usb_syncmem(&sqtd->dma, 2966 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 2967 sizeof(sqtd->qtd.qtd_status), 2968 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2969 if (sqtd == exfer->sqtdend) 2970 break; 2971 } 2972 splx(s); 2973 2974 /* 2975 * Step 2: Wait until we know hardware has finished any possible 2976 * use of the xfer. Also make sure the soft interrupt routine 2977 * has run. 2978 */ 2979 ehci_sync_hc(sc); 2980 s = splusb(); 2981 sc->sc_softwake = 1; 2982 usb_schedsoftintr(&sc->sc_bus); 2983 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 2984 splx(s); 2985 2986 /* 2987 * Step 3: Remove any vestiges of the xfer from the hardware. 2988 * The complication here is that the hardware may have executed 2989 * beyond the xfer we're trying to abort. So as we're scanning 2990 * the TDs of this xfer we check if the hardware points to 2991 * any of them. 2992 */ 2993 s = splusb(); /* XXX why? */ 2994 2995 usb_syncmem(&sqh->dma, 2996 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 2997 sizeof(sqh->qh.qh_curqtd), 2998 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2999 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3000 hit = 0; 3001 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3002 hit |= cur == sqtd->physaddr; 3003 if (sqtd == exfer->sqtdend) 3004 break; 3005 } 3006 sqtd = sqtd->nextqtd; 3007 /* Zap curqtd register if hardware pointed inside the xfer. */ 3008 if (hit && sqtd != NULL) { 3009 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3010 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3011 usb_syncmem(&sqh->dma, 3012 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3013 sizeof(sqh->qh.qh_curqtd), 3014 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3015 sqh->qh.qh_qtd.qtd_status = qhstatus; 3016 usb_syncmem(&sqh->dma, 3017 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3018 sizeof(sqh->qh.qh_qtd.qtd_status), 3019 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3020 } else { 3021 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3022 } 3023 3024 /* 3025 * Step 4: Execute callback. 3026 */ 3027 #ifdef DIAGNOSTIC 3028 exfer->isdone = 1; 3029 #endif 3030 wake = xfer->hcflags & UXFER_ABORTWAIT; 3031 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3032 usb_transfer_complete(xfer); 3033 if (wake) 3034 wakeup(&xfer->hcflags); 3035 3036 splx(s); 3037 #undef exfer 3038 } 3039 3040 Static void 3041 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3042 { 3043 ehci_isoc_trans_t trans_status; 3044 struct ehci_pipe *epipe; 3045 struct ehci_xfer *exfer; 3046 ehci_softc_t *sc; 3047 struct ehci_soft_itd *itd; 3048 int s, i, wake; 3049 3050 epipe = (struct ehci_pipe *) xfer->pipe; 3051 exfer = EXFER(xfer); 3052 sc = epipe->pipe.device->bus->hci_private; 3053 3054 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3055 3056 if (sc->sc_dying) { 3057 s = splusb(); 3058 xfer->status = status; 3059 callout_stop(&xfer->timeout_handle); 3060 usb_transfer_complete(xfer); 3061 splx(s); 3062 return; 3063 } 3064 3065 if (xfer->hcflags & UXFER_ABORTING) { 3066 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3067 3068 #ifdef DIAGNOSTIC 3069 if (status == USBD_TIMEOUT) 3070 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3071 #endif 3072 3073 xfer->status = status; 3074 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3075 xfer->hcflags |= UXFER_ABORTWAIT; 3076 while (xfer->hcflags & UXFER_ABORTING) 3077 tsleep(&xfer->hcflags, PZERO, "ehciiaw", 0); 3078 return; 3079 } 3080 xfer->hcflags |= UXFER_ABORTING; 3081 3082 xfer->status = status; 3083 callout_stop(&xfer->timeout_handle); 3084 3085 s = splusb(); 3086 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3087 usb_syncmem(&itd->dma, 3088 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3089 sizeof(itd->itd.itd_ctl), 3090 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3091 3092 for (i = 0; i < 8; i++) { 3093 trans_status = le32toh(itd->itd.itd_ctl[i]); 3094 trans_status &= ~EHCI_ITD_ACTIVE; 3095 itd->itd.itd_ctl[i] = htole32(trans_status); 3096 } 3097 3098 usb_syncmem(&itd->dma, 3099 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3100 sizeof(itd->itd.itd_ctl), 3101 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3102 } 3103 splx(s); 3104 3105 s = splusb(); 3106 sc->sc_softwake = 1; 3107 usb_schedsoftintr(&sc->sc_bus); 3108 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0); 3109 splx(s); 3110 3111 #ifdef DIAGNOSTIC 3112 exfer->isdone = 1; 3113 #endif 3114 wake = xfer->hcflags & UXFER_ABORTWAIT; 3115 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3116 usb_transfer_complete(xfer); 3117 if (wake) 3118 wakeup(&xfer->hcflags); 3119 3120 return; 3121 } 3122 3123 Static void 3124 ehci_timeout(void *addr) 3125 { 3126 struct ehci_xfer *exfer = addr; 3127 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3128 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3129 3130 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3131 #ifdef EHCI_DEBUG 3132 if (ehcidebug > 1) 3133 usbd_dump_pipe(exfer->xfer.pipe); 3134 #endif 3135 3136 if (sc->sc_dying) { 3137 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3138 return; 3139 } 3140 3141 /* Execute the abort in a process context. */ 3142 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3143 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3144 USB_TASKQ_HC); 3145 } 3146 3147 Static void 3148 ehci_timeout_task(void *addr) 3149 { 3150 usbd_xfer_handle xfer = addr; 3151 int s; 3152 3153 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3154 3155 s = splusb(); 3156 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3157 splx(s); 3158 } 3159 3160 /************************/ 3161 3162 Static usbd_status 3163 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3164 { 3165 usbd_status err; 3166 3167 /* Insert last in queue. */ 3168 err = usb_insert_transfer(xfer); 3169 if (err) 3170 return (err); 3171 3172 /* Pipe isn't running, start first */ 3173 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3174 } 3175 3176 Static usbd_status 3177 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3178 { 3179 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3180 usbd_status err; 3181 3182 if (sc->sc_dying) 3183 return (USBD_IOERROR); 3184 3185 #ifdef DIAGNOSTIC 3186 if (!(xfer->rqflags & URQ_REQUEST)) { 3187 /* XXX panic */ 3188 printf("ehci_device_ctrl_transfer: not a request\n"); 3189 return (USBD_INVAL); 3190 } 3191 #endif 3192 3193 err = ehci_device_request(xfer); 3194 if (err) 3195 return (err); 3196 3197 if (sc->sc_bus.use_polling) 3198 ehci_waitintr(sc, xfer); 3199 return (USBD_IN_PROGRESS); 3200 } 3201 3202 Static void 3203 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3204 { 3205 struct ehci_xfer *ex = EXFER(xfer); 3206 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3207 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3208 usb_device_request_t *req = &xfer->request; 3209 int len = UGETW(req->wLength); 3210 int rd = req->bmRequestType & UT_READ; 3211 3212 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3213 3214 #ifdef DIAGNOSTIC 3215 if (!(xfer->rqflags & URQ_REQUEST)) { 3216 panic("ehci_ctrl_done: not a request"); 3217 } 3218 #endif 3219 3220 mutex_enter(&sc->sc_intrhead_lock); 3221 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3222 ehci_del_intr_list(sc, ex); /* remove from active list */ 3223 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3224 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3225 BUS_DMASYNC_POSTWRITE); 3226 if (len) 3227 usb_syncmem(&xfer->dmabuf, 0, len, 3228 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3229 } 3230 mutex_exit(&sc->sc_intrhead_lock); 3231 3232 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3233 } 3234 3235 /* Abort a device control request. */ 3236 Static void 3237 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3238 { 3239 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3240 ehci_abort_xfer(xfer, USBD_CANCELLED); 3241 } 3242 3243 /* Close a device control pipe. */ 3244 Static void 3245 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3246 { 3247 ehci_softc_t *sc = pipe->device->bus->hci_private; 3248 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3249 3250 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3251 ehci_close_pipe(pipe, sc->sc_async_head); 3252 } 3253 3254 Static usbd_status 3255 ehci_device_request(usbd_xfer_handle xfer) 3256 { 3257 #define exfer EXFER(xfer) 3258 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3259 usb_device_request_t *req = &xfer->request; 3260 usbd_device_handle dev = epipe->pipe.device; 3261 ehci_softc_t *sc = dev->bus->hci_private; 3262 int addr = dev->address; 3263 ehci_soft_qtd_t *setup, *stat, *next; 3264 ehci_soft_qh_t *sqh; 3265 int isread; 3266 int len; 3267 usbd_status err; 3268 int s; 3269 3270 isread = req->bmRequestType & UT_READ; 3271 len = UGETW(req->wLength); 3272 3273 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3274 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3275 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3276 UGETW(req->wIndex), len, addr, 3277 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3278 3279 setup = ehci_alloc_sqtd(sc); 3280 if (setup == NULL) { 3281 err = USBD_NOMEM; 3282 goto bad1; 3283 } 3284 stat = ehci_alloc_sqtd(sc); 3285 if (stat == NULL) { 3286 err = USBD_NOMEM; 3287 goto bad2; 3288 } 3289 3290 sqh = epipe->sqh; 3291 epipe->u.ctl.length = len; 3292 3293 /* Update device address and length since they may have changed 3294 during the setup of the control pipe in usbd_new_device(). */ 3295 /* XXX This only needs to be done once, but it's too early in open. */ 3296 /* XXXX Should not touch ED here! */ 3297 sqh->qh.qh_endp = 3298 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3299 htole32( 3300 EHCI_QH_SET_ADDR(addr) | 3301 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3302 ); 3303 3304 /* Set up data transaction */ 3305 if (len != 0) { 3306 ehci_soft_qtd_t *end; 3307 3308 /* Start toggle at 1. */ 3309 epipe->nexttoggle = 1; 3310 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3311 &next, &end); 3312 if (err) 3313 goto bad3; 3314 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3315 end->nextqtd = stat; 3316 end->qtd.qtd_next = 3317 end->qtd.qtd_altnext = htole32(stat->physaddr); 3318 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3319 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3320 } else { 3321 next = stat; 3322 } 3323 3324 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3325 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3326 3327 /* Clear toggle */ 3328 setup->qtd.qtd_status = htole32( 3329 EHCI_QTD_ACTIVE | 3330 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3331 EHCI_QTD_SET_CERR(3) | 3332 EHCI_QTD_SET_TOGGLE(0) | 3333 EHCI_QTD_SET_BYTES(sizeof *req) 3334 ); 3335 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3336 setup->qtd.qtd_buffer_hi[0] = 0; 3337 setup->nextqtd = next; 3338 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3339 setup->xfer = xfer; 3340 setup->len = sizeof *req; 3341 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3342 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3343 3344 stat->qtd.qtd_status = htole32( 3345 EHCI_QTD_ACTIVE | 3346 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3347 EHCI_QTD_SET_CERR(3) | 3348 EHCI_QTD_SET_TOGGLE(1) | 3349 EHCI_QTD_IOC 3350 ); 3351 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3352 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3353 stat->nextqtd = NULL; 3354 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3355 stat->xfer = xfer; 3356 stat->len = 0; 3357 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3358 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3359 3360 #ifdef EHCI_DEBUG 3361 if (ehcidebug > 5) { 3362 DPRINTF(("ehci_device_request:\n")); 3363 ehci_dump_sqh(sqh); 3364 ehci_dump_sqtds(setup); 3365 } 3366 #endif 3367 3368 exfer->sqtdstart = setup; 3369 exfer->sqtdend = stat; 3370 #ifdef DIAGNOSTIC 3371 if (!exfer->isdone) { 3372 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3373 } 3374 exfer->isdone = 0; 3375 #endif 3376 3377 /* Insert qTD in QH list. */ 3378 s = splusb(); 3379 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3380 if (xfer->timeout && !sc->sc_bus.use_polling) { 3381 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3382 (ehci_timeout), (xfer)); 3383 } 3384 mutex_enter(&sc->sc_intrhead_lock); 3385 ehci_add_intr_list(sc, exfer); 3386 mutex_exit(&sc->sc_intrhead_lock); 3387 xfer->status = USBD_IN_PROGRESS; 3388 splx(s); 3389 3390 #ifdef EHCI_DEBUG 3391 if (ehcidebug > 10) { 3392 DPRINTF(("ehci_device_request: status=%x\n", 3393 EOREAD4(sc, EHCI_USBSTS))); 3394 delay(10000); 3395 ehci_dump_regs(sc); 3396 ehci_dump_sqh(sc->sc_async_head); 3397 ehci_dump_sqh(sqh); 3398 ehci_dump_sqtds(setup); 3399 } 3400 #endif 3401 3402 return (USBD_NORMAL_COMPLETION); 3403 3404 bad3: 3405 ehci_free_sqtd(sc, stat); 3406 bad2: 3407 ehci_free_sqtd(sc, setup); 3408 bad1: 3409 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3410 xfer->status = err; 3411 usb_transfer_complete(xfer); 3412 return (err); 3413 #undef exfer 3414 } 3415 3416 /* 3417 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3418 * qTD status, or miss signalling occasionally under heavy load. If the host 3419 * machine is too fast, we we can miss transaction completion - when we scan 3420 * the active list the transaction still seems to be active. This generally 3421 * exhibits itself as a umass stall that never recovers. 3422 * 3423 * We work around this behaviour by setting up this callback after any softintr 3424 * that completes with transactions still pending, giving us another chance to 3425 * check for completion after the writeback has taken place. 3426 */ 3427 Static void 3428 ehci_intrlist_timeout(void *arg) 3429 { 3430 ehci_softc_t *sc = arg; 3431 int s = splusb(); 3432 3433 DPRINTF(("ehci_intrlist_timeout\n")); 3434 usb_schedsoftintr(&sc->sc_bus); 3435 3436 splx(s); 3437 } 3438 3439 /************************/ 3440 3441 Static usbd_status 3442 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3443 { 3444 usbd_status err; 3445 3446 /* Insert last in queue. */ 3447 err = usb_insert_transfer(xfer); 3448 if (err) 3449 return (err); 3450 3451 /* Pipe isn't running, start first */ 3452 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3453 } 3454 3455 Static usbd_status 3456 ehci_device_bulk_start(usbd_xfer_handle xfer) 3457 { 3458 #define exfer EXFER(xfer) 3459 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3460 usbd_device_handle dev = epipe->pipe.device; 3461 ehci_softc_t *sc = dev->bus->hci_private; 3462 ehci_soft_qtd_t *data, *dataend; 3463 ehci_soft_qh_t *sqh; 3464 usbd_status err; 3465 int len, isread, endpt; 3466 int s; 3467 3468 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3469 xfer, xfer->length, xfer->flags)); 3470 3471 if (sc->sc_dying) 3472 return (USBD_IOERROR); 3473 3474 #ifdef DIAGNOSTIC 3475 if (xfer->rqflags & URQ_REQUEST) 3476 panic("ehci_device_bulk_start: a request"); 3477 #endif 3478 3479 len = xfer->length; 3480 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3481 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3482 sqh = epipe->sqh; 3483 3484 epipe->u.bulk.length = len; 3485 3486 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3487 &dataend); 3488 if (err) { 3489 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3490 xfer->status = err; 3491 usb_transfer_complete(xfer); 3492 return (err); 3493 } 3494 3495 #ifdef EHCI_DEBUG 3496 if (ehcidebug > 5) { 3497 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3498 ehci_dump_sqh(sqh); 3499 ehci_dump_sqtds(data); 3500 } 3501 #endif 3502 3503 /* Set up interrupt info. */ 3504 exfer->sqtdstart = data; 3505 exfer->sqtdend = dataend; 3506 #ifdef DIAGNOSTIC 3507 if (!exfer->isdone) { 3508 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3509 } 3510 exfer->isdone = 0; 3511 #endif 3512 3513 s = splusb(); 3514 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3515 if (xfer->timeout && !sc->sc_bus.use_polling) { 3516 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3517 (ehci_timeout), (xfer)); 3518 } 3519 mutex_enter(&sc->sc_intrhead_lock); 3520 ehci_add_intr_list(sc, exfer); 3521 mutex_exit(&sc->sc_intrhead_lock); 3522 xfer->status = USBD_IN_PROGRESS; 3523 splx(s); 3524 3525 #ifdef EHCI_DEBUG 3526 if (ehcidebug > 10) { 3527 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3528 delay(10000); 3529 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3530 ehci_dump_regs(sc); 3531 #if 0 3532 printf("async_head:\n"); 3533 ehci_dump_sqh(sc->sc_async_head); 3534 #endif 3535 printf("sqh:\n"); 3536 ehci_dump_sqh(sqh); 3537 ehci_dump_sqtds(data); 3538 } 3539 #endif 3540 3541 if (sc->sc_bus.use_polling) 3542 ehci_waitintr(sc, xfer); 3543 3544 return (USBD_IN_PROGRESS); 3545 #undef exfer 3546 } 3547 3548 Static void 3549 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3550 { 3551 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3552 ehci_abort_xfer(xfer, USBD_CANCELLED); 3553 } 3554 3555 /* 3556 * Close a device bulk pipe. 3557 */ 3558 Static void 3559 ehci_device_bulk_close(usbd_pipe_handle pipe) 3560 { 3561 ehci_softc_t *sc = pipe->device->bus->hci_private; 3562 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3563 3564 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3565 pipe->endpoint->datatoggle = epipe->nexttoggle; 3566 ehci_close_pipe(pipe, sc->sc_async_head); 3567 } 3568 3569 Static void 3570 ehci_device_bulk_done(usbd_xfer_handle xfer) 3571 { 3572 struct ehci_xfer *ex = EXFER(xfer); 3573 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3574 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3575 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3576 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3577 3578 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3579 xfer, xfer->actlen)); 3580 3581 mutex_enter(&sc->sc_intrhead_lock); 3582 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3583 ehci_del_intr_list(sc, ex); /* remove from active list */ 3584 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3585 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3586 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3587 } 3588 mutex_exit(&sc->sc_intrhead_lock); 3589 3590 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3591 } 3592 3593 /************************/ 3594 3595 Static usbd_status 3596 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3597 { 3598 struct ehci_soft_islot *isp; 3599 int islot, lev; 3600 3601 /* Find a poll rate that is large enough. */ 3602 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3603 if (EHCI_ILEV_IVAL(lev) <= ival) 3604 break; 3605 3606 /* Pick an interrupt slot at the right level. */ 3607 /* XXX could do better than picking at random */ 3608 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3609 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3610 3611 sqh->islot = islot; 3612 isp = &sc->sc_islots[islot]; 3613 ehci_add_qh(sqh, isp->sqh); 3614 3615 return (USBD_NORMAL_COMPLETION); 3616 } 3617 3618 Static usbd_status 3619 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3620 { 3621 usbd_status err; 3622 3623 /* Insert last in queue. */ 3624 err = usb_insert_transfer(xfer); 3625 if (err) 3626 return (err); 3627 3628 /* 3629 * Pipe isn't running (otherwise err would be USBD_INPROG), 3630 * so start it first. 3631 */ 3632 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3633 } 3634 3635 Static usbd_status 3636 ehci_device_intr_start(usbd_xfer_handle xfer) 3637 { 3638 #define exfer EXFER(xfer) 3639 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3640 usbd_device_handle dev = xfer->pipe->device; 3641 ehci_softc_t *sc = dev->bus->hci_private; 3642 ehci_soft_qtd_t *data, *dataend; 3643 ehci_soft_qh_t *sqh; 3644 usbd_status err; 3645 int len, isread, endpt; 3646 int s; 3647 3648 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3649 xfer, xfer->length, xfer->flags)); 3650 3651 if (sc->sc_dying) 3652 return (USBD_IOERROR); 3653 3654 #ifdef DIAGNOSTIC 3655 if (xfer->rqflags & URQ_REQUEST) 3656 panic("ehci_device_intr_start: a request"); 3657 #endif 3658 3659 len = xfer->length; 3660 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3661 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3662 sqh = epipe->sqh; 3663 3664 epipe->u.intr.length = len; 3665 3666 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3667 &dataend); 3668 if (err) { 3669 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3670 xfer->status = err; 3671 usb_transfer_complete(xfer); 3672 return (err); 3673 } 3674 3675 #ifdef EHCI_DEBUG 3676 if (ehcidebug > 5) { 3677 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3678 ehci_dump_sqh(sqh); 3679 ehci_dump_sqtds(data); 3680 } 3681 #endif 3682 3683 /* Set up interrupt info. */ 3684 exfer->sqtdstart = data; 3685 exfer->sqtdend = dataend; 3686 #ifdef DIAGNOSTIC 3687 if (!exfer->isdone) { 3688 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3689 } 3690 exfer->isdone = 0; 3691 #endif 3692 3693 s = splusb(); 3694 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3695 if (xfer->timeout && !sc->sc_bus.use_polling) { 3696 callout_reset(&(xfer->timeout_handle), (mstohz(xfer->timeout)), 3697 (ehci_timeout), (xfer)); 3698 } 3699 mutex_enter(&sc->sc_intrhead_lock); 3700 ehci_add_intr_list(sc, exfer); 3701 mutex_exit(&sc->sc_intrhead_lock); 3702 xfer->status = USBD_IN_PROGRESS; 3703 splx(s); 3704 3705 #ifdef EHCI_DEBUG 3706 if (ehcidebug > 10) { 3707 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3708 delay(10000); 3709 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3710 ehci_dump_regs(sc); 3711 printf("sqh:\n"); 3712 ehci_dump_sqh(sqh); 3713 ehci_dump_sqtds(data); 3714 } 3715 #endif 3716 3717 if (sc->sc_bus.use_polling) 3718 ehci_waitintr(sc, xfer); 3719 3720 return (USBD_IN_PROGRESS); 3721 #undef exfer 3722 } 3723 3724 Static void 3725 ehci_device_intr_abort(usbd_xfer_handle xfer) 3726 { 3727 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3728 if (xfer->pipe->intrxfer == xfer) { 3729 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3730 xfer->pipe->intrxfer = NULL; 3731 } 3732 /* 3733 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3734 * async doorbell. That's dependent on the async list, wheras 3735 * intr xfers are periodic, should not use this? 3736 */ 3737 ehci_abort_xfer(xfer, USBD_CANCELLED); 3738 } 3739 3740 Static void 3741 ehci_device_intr_close(usbd_pipe_handle pipe) 3742 { 3743 ehci_softc_t *sc = pipe->device->bus->hci_private; 3744 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3745 struct ehci_soft_islot *isp; 3746 3747 isp = &sc->sc_islots[epipe->sqh->islot]; 3748 ehci_close_pipe(pipe, isp->sqh); 3749 } 3750 3751 Static void 3752 ehci_device_intr_done(usbd_xfer_handle xfer) 3753 { 3754 #define exfer EXFER(xfer) 3755 struct ehci_xfer *ex = EXFER(xfer); 3756 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3757 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3758 ehci_soft_qtd_t *data, *dataend; 3759 ehci_soft_qh_t *sqh; 3760 usbd_status err; 3761 int len, isread, endpt, s; 3762 3763 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3764 xfer, xfer->actlen)); 3765 3766 mutex_enter(&sc->sc_intrhead_lock); 3767 if (xfer->pipe->repeat) { 3768 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3769 3770 len = epipe->u.intr.length; 3771 xfer->length = len; 3772 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3773 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3774 usb_syncmem(&xfer->dmabuf, 0, len, 3775 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3776 sqh = epipe->sqh; 3777 3778 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3779 &data, &dataend); 3780 if (err) { 3781 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3782 xfer->status = err; 3783 mutex_exit(&sc->sc_intrhead_lock); 3784 return; 3785 } 3786 3787 /* Set up interrupt info. */ 3788 exfer->sqtdstart = data; 3789 exfer->sqtdend = dataend; 3790 #ifdef DIAGNOSTIC 3791 if (!exfer->isdone) { 3792 printf("ehci_device_intr_done: not done, ex=%p\n", 3793 exfer); 3794 } 3795 exfer->isdone = 0; 3796 #endif 3797 3798 s = splusb(); 3799 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3800 if (xfer->timeout && !sc->sc_bus.use_polling) { 3801 callout_reset(&(xfer->timeout_handle), 3802 (mstohz(xfer->timeout)), (ehci_timeout), (xfer)); 3803 } 3804 splx(s); 3805 3806 xfer->status = USBD_IN_PROGRESS; 3807 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3808 ehci_del_intr_list(sc, ex); /* remove from active list */ 3809 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3810 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3811 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3812 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3813 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3814 } 3815 mutex_exit(&sc->sc_intrhead_lock); 3816 #undef exfer 3817 } 3818 3819 /************************/ 3820 3821 Static usbd_status 3822 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3823 { 3824 usbd_status err; 3825 3826 err = usb_insert_transfer(xfer); 3827 if (err && err != USBD_IN_PROGRESS) 3828 return err; 3829 3830 return ehci_device_isoc_start(xfer); 3831 } 3832 3833 Static usbd_status 3834 ehci_device_isoc_start(usbd_xfer_handle xfer) 3835 { 3836 struct ehci_pipe *epipe; 3837 usbd_device_handle dev; 3838 ehci_softc_t *sc; 3839 struct ehci_xfer *exfer; 3840 ehci_soft_itd_t *itd, *prev, *start, *stop; 3841 usb_dma_t *dma_buf; 3842 int i, j, k, frames, uframes, ufrperframe; 3843 int s, trans_count, offs, total_length; 3844 int frindex; 3845 3846 start = NULL; 3847 prev = NULL; 3848 itd = NULL; 3849 trans_count = 0; 3850 total_length = 0; 3851 exfer = (struct ehci_xfer *) xfer; 3852 sc = xfer->pipe->device->bus->hci_private; 3853 dev = xfer->pipe->device; 3854 epipe = (struct ehci_pipe *)xfer->pipe; 3855 3856 /* 3857 * To allow continuous transfers, above we start all transfers 3858 * immediately. However, we're still going to get usbd_start_next call 3859 * this when another xfer completes. So, check if this is already 3860 * in progress or not 3861 */ 3862 3863 if (exfer->itdstart != NULL) 3864 return USBD_IN_PROGRESS; 3865 3866 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3867 xfer, xfer->length, xfer->flags)); 3868 3869 if (sc->sc_dying) 3870 return USBD_IOERROR; 3871 3872 /* 3873 * To avoid complication, don't allow a request right now that'll span 3874 * the entire frame table. To within 4 frames, to allow some leeway 3875 * on either side of where the hc currently is. 3876 */ 3877 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3878 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3879 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3880 return USBD_INVAL; 3881 } 3882 3883 #ifdef DIAGNOSTIC 3884 if (xfer->rqflags & URQ_REQUEST) 3885 panic("ehci_device_isoc_start: request\n"); 3886 3887 if (!exfer->isdone) 3888 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3889 exfer->isdone = 0; 3890 #endif 3891 3892 /* 3893 * Step 1: Allocate and initialize itds, how many do we need? 3894 * One per transfer if interval >= 8 microframes, fewer if we use 3895 * multiple microframes per frame. 3896 */ 3897 3898 i = epipe->pipe.endpoint->edesc->bInterval; 3899 if (i > 16 || i == 0) { 3900 /* Spec page 271 says intervals > 16 are invalid */ 3901 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3902 return USBD_INVAL; 3903 } 3904 3905 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 3906 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 3907 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 3908 3909 if (frames == 0) { 3910 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 3911 return USBD_INVAL; 3912 } 3913 3914 dma_buf = &xfer->dmabuf; 3915 offs = 0; 3916 3917 for (i = 0; i < frames; i++) { 3918 int froffs = offs; 3919 itd = ehci_alloc_itd(sc); 3920 3921 if (prev != NULL) { 3922 prev->itd.itd_next = 3923 htole32(itd->physaddr | EHCI_LINK_ITD); 3924 usb_syncmem(&itd->dma, 3925 itd->offs + offsetof(ehci_itd_t, itd_next), 3926 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 3927 3928 prev->xfer_next = itd; 3929 } else { 3930 start = itd; 3931 } 3932 3933 /* 3934 * Step 1.5, initialize uframes 3935 */ 3936 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 3937 /* Calculate which page in the list this starts in */ 3938 int addr = DMAADDR(dma_buf, froffs); 3939 addr = EHCI_PAGE_OFFSET(addr); 3940 addr += (offs - froffs); 3941 addr = EHCI_PAGE(addr); 3942 addr /= EHCI_PAGE_SIZE; 3943 3944 /* This gets the initial offset into the first page, 3945 * looks how far further along the current uframe 3946 * offset is. Works out how many pages that is. 3947 */ 3948 3949 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 3950 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 3951 EHCI_ITD_SET_PG(addr) | 3952 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 3953 3954 total_length += xfer->frlengths[trans_count]; 3955 offs += xfer->frlengths[trans_count]; 3956 trans_count++; 3957 3958 if (trans_count >= xfer->nframes) { /*Set IOC*/ 3959 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 3960 break; 3961 } 3962 } 3963 3964 /* Step 1.75, set buffer pointers. To simplify matters, all 3965 * pointers are filled out for the next 7 hardware pages in 3966 * the dma block, so no need to worry what pages to cover 3967 * and what to not. 3968 */ 3969 3970 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 3971 /* 3972 * Don't try to lookup a page that's past the end 3973 * of buffer 3974 */ 3975 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 3976 if (page_offs >= dma_buf->block->size) 3977 break; 3978 3979 unsigned long long page = DMAADDR(dma_buf, page_offs); 3980 page = EHCI_PAGE(page); 3981 itd->itd.itd_bufr[j] = 3982 htole32(EHCI_ITD_SET_BPTR(page)); 3983 itd->itd.itd_bufr_hi[j] = 3984 htole32(page >> 32); 3985 } 3986 3987 /* 3988 * Other special values 3989 */ 3990 3991 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 3992 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 3993 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 3994 3995 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 3996 ? 1 : 0; 3997 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 3998 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 3999 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4000 4001 /* FIXME: handle invalid trans */ 4002 itd->itd.itd_bufr[2] |= 4003 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4004 4005 usb_syncmem(&itd->dma, 4006 itd->offs + offsetof(ehci_itd_t, itd_next), 4007 sizeof(ehci_itd_t), 4008 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4009 4010 prev = itd; 4011 } /* End of frame */ 4012 4013 stop = itd; 4014 stop->xfer_next = NULL; 4015 exfer->isoc_len = total_length; 4016 4017 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4018 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4019 4020 /* 4021 * Part 2: Transfer descriptors have now been set up, now they must 4022 * be scheduled into the period frame list. Erk. Not wanting to 4023 * complicate matters, transfer is denied if the transfer spans 4024 * more than the period frame list. 4025 */ 4026 4027 s = splusb(); 4028 4029 /* Start inserting frames */ 4030 if (epipe->u.isoc.cur_xfers > 0) { 4031 frindex = epipe->u.isoc.next_frame; 4032 } else { 4033 frindex = EOREAD4(sc, EHCI_FRINDEX); 4034 frindex = frindex >> 3; /* Erase microframe index */ 4035 frindex += 2; 4036 } 4037 4038 if (frindex >= sc->sc_flsize) 4039 frindex &= (sc->sc_flsize - 1); 4040 4041 /* What's the frame interval? */ 4042 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4043 if (i / USB_UFRAMES_PER_FRAME == 0) 4044 i = 1; 4045 else 4046 i /= USB_UFRAMES_PER_FRAME; 4047 4048 itd = start; 4049 for (j = 0; j < frames; j++) { 4050 if (itd == NULL) 4051 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4052 4053 itd->itd.itd_next = sc->sc_flist[frindex]; 4054 if (itd->itd.itd_next == 0) 4055 /* FIXME: frindex table gets initialized to NULL 4056 * or EHCI_NULL? */ 4057 itd->itd.itd_next = EHCI_NULL; 4058 4059 usb_syncmem(&itd->dma, 4060 itd->offs + offsetof(ehci_itd_t, itd_next), 4061 sizeof(itd->itd.itd_next), 4062 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4063 4064 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4065 4066 usb_syncmem(&sc->sc_fldma, 4067 sizeof(ehci_link_t) * frindex, 4068 sizeof(ehci_link_t), 4069 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4070 4071 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4072 sc->sc_softitds[frindex] = itd; 4073 if (itd->u.frame_list.next != NULL) 4074 itd->u.frame_list.next->u.frame_list.prev = itd; 4075 itd->slot = frindex; 4076 itd->u.frame_list.prev = NULL; 4077 4078 frindex += i; 4079 if (frindex >= sc->sc_flsize) 4080 frindex -= sc->sc_flsize; 4081 4082 itd = itd->xfer_next; 4083 } 4084 4085 epipe->u.isoc.cur_xfers++; 4086 epipe->u.isoc.next_frame = frindex; 4087 4088 exfer->itdstart = start; 4089 exfer->itdend = stop; 4090 exfer->sqtdstart = NULL; 4091 exfer->sqtdstart = NULL; 4092 4093 mutex_enter(&sc->sc_intrhead_lock); 4094 ehci_add_intr_list(sc, exfer); 4095 mutex_exit(&sc->sc_intrhead_lock); 4096 xfer->status = USBD_IN_PROGRESS; 4097 xfer->done = 0; 4098 splx(s); 4099 4100 if (sc->sc_bus.use_polling) { 4101 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4102 ehci_waitintr(sc, xfer); 4103 } 4104 4105 return USBD_IN_PROGRESS; 4106 } 4107 4108 Static void 4109 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4110 { 4111 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4112 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4113 } 4114 4115 Static void 4116 ehci_device_isoc_close(usbd_pipe_handle pipe) 4117 { 4118 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4119 } 4120 4121 Static void 4122 ehci_device_isoc_done(usbd_xfer_handle xfer) 4123 { 4124 struct ehci_xfer *exfer; 4125 ehci_softc_t *sc; 4126 struct ehci_pipe *epipe; 4127 int s; 4128 4129 exfer = EXFER(xfer); 4130 sc = xfer->pipe->device->bus->hci_private; 4131 epipe = (struct ehci_pipe *) xfer->pipe; 4132 4133 s = splusb(); 4134 epipe->u.isoc.cur_xfers--; 4135 mutex_enter(&sc->sc_intrhead_lock); 4136 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4137 ehci_del_intr_list(sc, exfer); 4138 ehci_rem_free_itd_chain(sc, exfer); 4139 } 4140 mutex_exit(&sc->sc_intrhead_lock); 4141 splx(s); 4142 4143 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4144 BUS_DMASYNC_POSTREAD); 4145 4146 } 4147
Indexes created Thu Sep 25 08:09:54 GMT 2025