ehci.c revision 1.192
1 /* $NetBSD: ehci.c,v 1.192 2012/06/22 00:12:23 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.192 2012/06/22 00:12:23 mrg Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/kernel.h> 65 #include <sys/kmem.h> 66 #include <sys/device.h> 67 #include <sys/select.h> 68 #include <sys/proc.h> 69 #include <sys/queue.h> 70 #include <sys/mutex.h> 71 #include <sys/bus.h> 72 #include <sys/cpu.h> 73 74 #include <machine/endian.h> 75 76 #include <dev/usb/usb.h> 77 #include <dev/usb/usbdi.h> 78 #include <dev/usb/usbdivar.h> 79 #include <dev/usb/usb_mem.h> 80 #include <dev/usb/usb_quirks.h> 81 82 #include <dev/usb/ehcireg.h> 83 #include <dev/usb/ehcivar.h> 84 #include <dev/usb/usbroothub_subr.h> 85 86 #ifdef EHCI_DEBUG 87 #include <sys/kprintf.h> 88 static void 89 ehciprintf(const char *fmt, ...) 90 { 91 va_list ap; 92 93 va_start(ap, fmt); 94 kprintf(fmt, TOLOG|TOCONS, NULL, NULL, ap); 95 va_end(ap); 96 } 97 98 #define DPRINTF(x) do { if (ehcidebug) ehciprintf x; } while(0) 99 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) ehciprintf x; } while (0) 100 int ehcidebug = 0; 101 #else 102 #define DPRINTF(x) 103 #define DPRINTFN(n,x) 104 #endif 105 106 struct ehci_pipe { 107 struct usbd_pipe pipe; 108 int nexttoggle; 109 110 ehci_soft_qh_t *sqh; 111 union { 112 ehci_soft_qtd_t *qtd; 113 /* ehci_soft_itd_t *itd; */ 114 } tail; 115 union { 116 /* Control pipe */ 117 struct { 118 usb_dma_t reqdma; 119 u_int length; 120 } ctl; 121 /* Interrupt pipe */ 122 struct { 123 u_int length; 124 } intr; 125 /* Bulk pipe */ 126 struct { 127 u_int length; 128 } bulk; 129 /* Iso pipe */ 130 struct { 131 u_int next_frame; 132 u_int cur_xfers; 133 } isoc; 134 } u; 135 }; 136 137 Static usbd_status ehci_open(usbd_pipe_handle); 138 Static void ehci_poll(struct usbd_bus *); 139 Static void ehci_softintr(void *); 140 Static int ehci_intr1(ehci_softc_t *); 141 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 142 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 143 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 144 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 145 Static void ehci_idone(struct ehci_xfer *); 146 Static void ehci_timeout(void *); 147 Static void ehci_timeout_task(void *); 148 Static void ehci_intrlist_timeout(void *); 149 Static void ehci_doorbell(void *); 150 Static void ehci_pcd(void *); 151 152 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 153 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 154 155 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 156 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 157 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 158 159 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 160 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 161 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 162 Static void ehci_root_ctrl_close(usbd_pipe_handle); 163 Static void ehci_root_ctrl_done(usbd_xfer_handle); 164 165 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 166 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 167 Static void ehci_root_intr_abort(usbd_xfer_handle); 168 Static void ehci_root_intr_close(usbd_pipe_handle); 169 Static void ehci_root_intr_done(usbd_xfer_handle); 170 171 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 172 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 173 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 174 Static void ehci_device_ctrl_close(usbd_pipe_handle); 175 Static void ehci_device_ctrl_done(usbd_xfer_handle); 176 177 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 178 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 179 Static void ehci_device_bulk_abort(usbd_xfer_handle); 180 Static void ehci_device_bulk_close(usbd_pipe_handle); 181 Static void ehci_device_bulk_done(usbd_xfer_handle); 182 183 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 184 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 185 Static void ehci_device_intr_abort(usbd_xfer_handle); 186 Static void ehci_device_intr_close(usbd_pipe_handle); 187 Static void ehci_device_intr_done(usbd_xfer_handle); 188 189 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 190 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 191 Static void ehci_device_isoc_abort(usbd_xfer_handle); 192 Static void ehci_device_isoc_close(usbd_pipe_handle); 193 Static void ehci_device_isoc_done(usbd_xfer_handle); 194 195 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 196 Static void ehci_noop(usbd_pipe_handle pipe); 197 198 Static void ehci_disown(ehci_softc_t *, int, int); 199 200 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 201 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 202 203 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 204 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 205 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 206 ehci_softc_t *, int, int, usbd_xfer_handle, 207 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 208 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 209 ehci_soft_qtd_t *); 210 211 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 212 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 213 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 214 struct ehci_xfer *exfer); 215 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 216 usbd_status status); 217 218 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 219 220 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 221 int ival); 222 223 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 224 ehci_soft_qh_t *); 225 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 226 ehci_soft_qh_t *); 227 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 228 Static void ehci_sync_hc(ehci_softc_t *); 229 230 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 231 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 232 233 #ifdef EHCI_DEBUG 234 Static void ehci_dump_regs(ehci_softc_t *); 235 void ehci_dump(void); 236 Static ehci_softc_t *theehci; 237 Static void ehci_dump_link(ehci_link_t, int); 238 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 239 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 240 Static void ehci_dump_qtd(ehci_qtd_t *); 241 Static void ehci_dump_sqh(ehci_soft_qh_t *); 242 #if notyet 243 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 244 Static void ehci_dump_itd(struct ehci_soft_itd *); 245 #endif 246 #ifdef DIAGNOSTIC 247 Static void ehci_dump_exfer(struct ehci_xfer *); 248 #endif 249 #endif 250 251 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 252 253 #define EHCI_INTR_ENDPT 1 254 255 #define ehci_add_intr_list(sc, ex) \ 256 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 257 #define ehci_del_intr_list(sc, ex) \ 258 do { \ 259 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 260 (ex)->inext.tqe_prev = NULL; \ 261 } while (0) 262 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 263 264 Static const struct usbd_bus_methods ehci_bus_methods = { 265 .open_pipe = ehci_open, 266 .soft_intr = ehci_softintr, 267 .do_poll = ehci_poll, 268 .allocm = ehci_allocm, 269 .freem = ehci_freem, 270 .allocx = ehci_allocx, 271 .freex = ehci_freex, 272 .get_lock = ehci_get_lock, 273 }; 274 275 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 276 .transfer = ehci_root_ctrl_transfer, 277 .start = ehci_root_ctrl_start, 278 .abort = ehci_root_ctrl_abort, 279 .close = ehci_root_ctrl_close, 280 .cleartoggle = ehci_noop, 281 .done = ehci_root_ctrl_done, 282 }; 283 284 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 285 .transfer = ehci_root_intr_transfer, 286 .start = ehci_root_intr_start, 287 .abort = ehci_root_intr_abort, 288 .close = ehci_root_intr_close, 289 .cleartoggle = ehci_noop, 290 .done = ehci_root_intr_done, 291 }; 292 293 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 294 .transfer = ehci_device_ctrl_transfer, 295 .start = ehci_device_ctrl_start, 296 .abort = ehci_device_ctrl_abort, 297 .close = ehci_device_ctrl_close, 298 .cleartoggle = ehci_noop, 299 .done = ehci_device_ctrl_done, 300 }; 301 302 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 303 .transfer = ehci_device_intr_transfer, 304 .start = ehci_device_intr_start, 305 .abort = ehci_device_intr_abort, 306 .close = ehci_device_intr_close, 307 .cleartoggle = ehci_device_clear_toggle, 308 .done = ehci_device_intr_done, 309 }; 310 311 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 312 .transfer = ehci_device_bulk_transfer, 313 .start = ehci_device_bulk_start, 314 .abort = ehci_device_bulk_abort, 315 .close = ehci_device_bulk_close, 316 .cleartoggle = ehci_device_clear_toggle, 317 .done = ehci_device_bulk_done, 318 }; 319 320 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 321 .transfer = ehci_device_isoc_transfer, 322 .start = ehci_device_isoc_start, 323 .abort = ehci_device_isoc_abort, 324 .close = ehci_device_isoc_close, 325 .cleartoggle = ehci_noop, 326 .done = ehci_device_isoc_done, 327 }; 328 329 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 330 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 331 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 332 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 333 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 334 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 335 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 336 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 337 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 338 }; 339 340 usbd_status 341 ehci_init(ehci_softc_t *sc) 342 { 343 u_int32_t vers, sparams, cparams, hcr; 344 u_int i; 345 usbd_status err; 346 ehci_soft_qh_t *sqh; 347 u_int ncomp; 348 349 DPRINTF(("ehci_init: start\n")); 350 #ifdef EHCI_DEBUG 351 theehci = sc; 352 #endif 353 354 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 355 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 356 cv_init(&sc->sc_softwake_cv, "ehciab"); 357 cv_init(&sc->sc_doorbell, "ehcidi"); 358 359 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 360 ehci_doorbell, sc); 361 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 362 ehci_pcd, sc); 363 364 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 365 366 vers = EREAD2(sc, EHCI_HCIVERSION); 367 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 368 vers >> 8, vers & 0xff); 369 370 sparams = EREAD4(sc, EHCI_HCSPARAMS); 371 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 372 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 373 ncomp = EHCI_HCS_N_CC(sparams); 374 if (ncomp != sc->sc_ncomp) { 375 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 376 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 377 #if NOHCI == 0 || NUHCI == 0 378 aprint_error("%s: ohci or uhci probably not configured\n", 379 device_xname(sc->sc_dev)); 380 #endif 381 if (ncomp < sc->sc_ncomp) 382 sc->sc_ncomp = ncomp; 383 } 384 if (sc->sc_ncomp > 0) { 385 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 386 aprint_normal("%s: companion controller%s, %d port%s each:", 387 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 388 EHCI_HCS_N_PCC(sparams), 389 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 390 for (i = 0; i < sc->sc_ncomp; i++) 391 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 392 aprint_normal("\n"); 393 } 394 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 395 cparams = EREAD4(sc, EHCI_HCCPARAMS); 396 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 397 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 398 399 if (EHCI_HCC_64BIT(cparams)) { 400 /* MUST clear segment register if 64 bit capable. */ 401 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 402 } 403 404 sc->sc_bus.usbrev = USBREV_2_0; 405 406 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 407 USB_MEM_RESERVE); 408 409 /* Reset the controller */ 410 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 411 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 412 usb_delay_ms(&sc->sc_bus, 1); 413 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 414 for (i = 0; i < 100; i++) { 415 usb_delay_ms(&sc->sc_bus, 1); 416 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 417 if (!hcr) 418 break; 419 } 420 if (hcr) { 421 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 422 return (USBD_IOERROR); 423 } 424 if (sc->sc_vendor_init) 425 sc->sc_vendor_init(sc); 426 427 /* 428 * If we are doing embedded transaction translation function, force 429 * the controller to host mode. 430 */ 431 if (sc->sc_flags & EHCIF_ETTF) { 432 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 433 usbmode &= ~EHCI_USBMODE_CM; 434 usbmode |= EHCI_USBMODE_CM_HOST; 435 EWRITE4(sc, EHCI_USBMODE, usbmode); 436 } 437 438 /* XXX need proper intr scheduling */ 439 sc->sc_rand = 96; 440 441 /* frame list size at default, read back what we got and use that */ 442 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 443 case 0: sc->sc_flsize = 1024; break; 444 case 1: sc->sc_flsize = 512; break; 445 case 2: sc->sc_flsize = 256; break; 446 case 3: return (USBD_IOERROR); 447 } 448 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 449 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 450 if (err) 451 return (err); 452 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 453 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 454 455 for (i = 0; i < sc->sc_flsize; i++) { 456 sc->sc_flist[i] = EHCI_NULL; 457 } 458 459 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 460 461 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 462 KM_SLEEP); 463 if (sc->sc_softitds == NULL) 464 return ENOMEM; 465 LIST_INIT(&sc->sc_freeitds); 466 TAILQ_INIT(&sc->sc_intrhead); 467 468 /* Set up the bus struct. */ 469 sc->sc_bus.methods = &ehci_bus_methods; 470 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 471 472 sc->sc_eintrs = EHCI_NORMAL_INTRS; 473 474 /* 475 * Allocate the interrupt dummy QHs. These are arranged to give poll 476 * intervals that are powers of 2 times 1ms. 477 */ 478 for (i = 0; i < EHCI_INTRQHS; i++) { 479 sqh = ehci_alloc_sqh(sc); 480 if (sqh == NULL) { 481 err = USBD_NOMEM; 482 goto bad1; 483 } 484 sc->sc_islots[i].sqh = sqh; 485 } 486 for (i = 0; i < EHCI_INTRQHS; i++) { 487 sqh = sc->sc_islots[i].sqh; 488 if (i == 0) { 489 /* The last (1ms) QH terminates. */ 490 sqh->qh.qh_link = EHCI_NULL; 491 sqh->next = NULL; 492 } else { 493 /* Otherwise the next QH has half the poll interval */ 494 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 495 sqh->qh.qh_link = htole32(sqh->next->physaddr | 496 EHCI_LINK_QH); 497 } 498 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 499 sqh->qh.qh_curqtd = EHCI_NULL; 500 sqh->next = NULL; 501 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 502 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 503 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 504 sqh->sqtd = NULL; 505 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 506 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 507 } 508 /* Point the frame list at the last level (128ms). */ 509 for (i = 0; i < sc->sc_flsize; i++) { 510 int j; 511 512 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 513 revbits[i & (EHCI_MAX_POLLRATE-1)]; 514 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 515 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 516 i)].sqh->physaddr); 517 } 518 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 519 BUS_DMASYNC_PREWRITE); 520 521 /* Allocate dummy QH that starts the async list. */ 522 sqh = ehci_alloc_sqh(sc); 523 if (sqh == NULL) { 524 err = USBD_NOMEM; 525 goto bad1; 526 } 527 /* Fill the QH */ 528 sqh->qh.qh_endp = 529 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 530 sqh->qh.qh_link = 531 htole32(sqh->physaddr | EHCI_LINK_QH); 532 sqh->qh.qh_curqtd = EHCI_NULL; 533 sqh->next = NULL; 534 /* Fill the overlay qTD */ 535 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 536 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 537 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 538 sqh->sqtd = NULL; 539 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 540 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 541 #ifdef EHCI_DEBUG 542 if (ehcidebug) { 543 ehci_dump_sqh(sqh); 544 } 545 #endif 546 547 /* Point to async list */ 548 sc->sc_async_head = sqh; 549 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 550 551 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 552 553 /* Turn on controller */ 554 EOWRITE4(sc, EHCI_USBCMD, 555 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 556 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 557 EHCI_CMD_ASE | 558 EHCI_CMD_PSE | 559 EHCI_CMD_RS); 560 561 /* Take over port ownership */ 562 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 563 564 for (i = 0; i < 100; i++) { 565 usb_delay_ms(&sc->sc_bus, 1); 566 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 567 if (!hcr) 568 break; 569 } 570 if (hcr) { 571 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 572 return (USBD_IOERROR); 573 } 574 575 /* Enable interrupts */ 576 DPRINTFN(1,("ehci_init: enabling\n")); 577 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 578 579 return (USBD_NORMAL_COMPLETION); 580 581 #if 0 582 bad2: 583 ehci_free_sqh(sc, sc->sc_async_head); 584 #endif 585 bad1: 586 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 587 return (err); 588 } 589 590 int 591 ehci_intr(void *v) 592 { 593 ehci_softc_t *sc = v; 594 int ret = 0; 595 596 if (sc == NULL) 597 return 0; 598 599 mutex_spin_enter(&sc->sc_intr_lock); 600 601 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 602 goto done; 603 604 /* If we get an interrupt while polling, then just ignore it. */ 605 if (sc->sc_bus.use_polling) { 606 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 607 608 if (intrs) 609 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 610 #ifdef DIAGNOSTIC 611 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 612 #endif 613 goto done; 614 } 615 616 ret = ehci_intr1(sc); 617 618 done: 619 mutex_spin_exit(&sc->sc_intr_lock); 620 return ret; 621 } 622 623 Static int 624 ehci_intr1(ehci_softc_t *sc) 625 { 626 u_int32_t intrs, eintrs; 627 628 DPRINTFN(20,("ehci_intr1: enter\n")); 629 630 /* In case the interrupt occurs before initialization has completed. */ 631 if (sc == NULL) { 632 #ifdef DIAGNOSTIC 633 printf("ehci_intr1: sc == NULL\n"); 634 #endif 635 return (0); 636 } 637 638 KASSERT(mutex_owned(&sc->sc_intr_lock)); 639 640 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 641 if (!intrs) 642 return (0); 643 644 eintrs = intrs & sc->sc_eintrs; 645 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 646 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 647 (u_int)eintrs)); 648 if (!eintrs) 649 return (0); 650 651 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 652 sc->sc_bus.no_intrs++; 653 if (eintrs & EHCI_STS_IAA) { 654 DPRINTF(("ehci_intr1: door bell\n")); 655 kpreempt_disable(); 656 softint_schedule(sc->sc_doorbell_si); 657 kpreempt_enable(); 658 eintrs &= ~EHCI_STS_IAA; 659 } 660 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 661 DPRINTFN(5,("ehci_intr1: %s %s\n", 662 eintrs & EHCI_STS_INT ? "INT" : "", 663 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 664 usb_schedsoftintr(&sc->sc_bus); 665 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 666 } 667 if (eintrs & EHCI_STS_HSE) { 668 printf("%s: unrecoverable error, controller halted\n", 669 device_xname(sc->sc_dev)); 670 /* XXX what else */ 671 } 672 if (eintrs & EHCI_STS_PCD) { 673 kpreempt_disable(); 674 softint_schedule(sc->sc_pcd_si); 675 kpreempt_enable(); 676 eintrs &= ~EHCI_STS_PCD; 677 } 678 679 if (eintrs != 0) { 680 /* Block unprocessed interrupts. */ 681 sc->sc_eintrs &= ~eintrs; 682 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 683 printf("%s: blocking intrs 0x%x\n", 684 device_xname(sc->sc_dev), eintrs); 685 } 686 687 return (1); 688 } 689 690 Static void 691 ehci_doorbell(void *addr) 692 { 693 ehci_softc_t *sc = addr; 694 695 mutex_enter(&sc->sc_lock); 696 cv_broadcast(&sc->sc_doorbell); 697 mutex_exit(&sc->sc_lock); 698 } 699 700 Static void 701 ehci_pcd(void *addr) 702 { 703 ehci_softc_t *sc = addr; 704 usbd_xfer_handle xfer; 705 usbd_pipe_handle pipe; 706 u_char *p; 707 int i, m; 708 709 mutex_enter(&sc->sc_lock); 710 xfer = sc->sc_intrxfer; 711 712 if (xfer == NULL) { 713 /* Just ignore the change. */ 714 goto done; 715 } 716 717 pipe = xfer->pipe; 718 719 p = KERNADDR(&xfer->dmabuf, 0); 720 m = min(sc->sc_noport, xfer->length * 8 - 1); 721 memset(p, 0, xfer->length); 722 for (i = 1; i <= m; i++) { 723 /* Pick out CHANGE bits from the status reg. */ 724 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 725 p[i/8] |= 1 << (i%8); 726 } 727 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 728 xfer->actlen = xfer->length; 729 xfer->status = USBD_NORMAL_COMPLETION; 730 731 usb_transfer_complete(xfer); 732 733 done: 734 mutex_exit(&sc->sc_lock); 735 } 736 737 Static void 738 ehci_softintr(void *v) 739 { 740 struct usbd_bus *bus = v; 741 ehci_softc_t *sc = bus->hci_private; 742 struct ehci_xfer *ex, *nextex; 743 744 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 745 746 DPRINTFN(10,("%s: ehci_softintr\n", device_xname(sc->sc_dev))); 747 748 /* 749 * The only explanation I can think of for why EHCI is as brain dead 750 * as UHCI interrupt-wise is that Intel was involved in both. 751 * An interrupt just tells us that something is done, we have no 752 * clue what, so we need to scan through all active transfers. :-( 753 */ 754 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 755 nextex = TAILQ_NEXT(ex, inext); 756 ehci_check_intr(sc, ex); 757 } 758 759 /* Schedule a callout to catch any dropped transactions. */ 760 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 761 !TAILQ_EMPTY(&sc->sc_intrhead)) 762 callout_reset(&sc->sc_tmo_intrlist, 763 hz, ehci_intrlist_timeout, sc); 764 765 if (sc->sc_softwake) { 766 sc->sc_softwake = 0; 767 cv_broadcast(&sc->sc_softwake_cv); 768 } 769 } 770 771 /* Check for an interrupt. */ 772 Static void 773 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 774 { 775 int attr; 776 777 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 778 779 KASSERT(mutex_owned(&sc->sc_lock)); 780 781 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 782 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 783 ehci_check_itd_intr(sc, ex); 784 else 785 ehci_check_qh_intr(sc, ex); 786 787 return; 788 } 789 790 Static void 791 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 792 { 793 ehci_soft_qtd_t *sqtd, *lsqtd; 794 __uint32_t status; 795 796 KASSERT(mutex_owned(&sc->sc_lock)); 797 798 if (ex->sqtdstart == NULL) { 799 printf("ehci_check_qh_intr: not valid sqtd\n"); 800 return; 801 } 802 803 lsqtd = ex->sqtdend; 804 #ifdef DIAGNOSTIC 805 if (lsqtd == NULL) { 806 printf("ehci_check_qh_intr: lsqtd==0\n"); 807 return; 808 } 809 #endif 810 /* 811 * If the last TD is still active we need to check whether there 812 * is a an error somewhere in the middle, or whether there was a 813 * short packet (SPD and not ACTIVE). 814 */ 815 usb_syncmem(&lsqtd->dma, 816 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 817 sizeof(lsqtd->qtd.qtd_status), 818 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 819 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 820 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 821 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 822 usb_syncmem(&sqtd->dma, 823 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 824 sizeof(sqtd->qtd.qtd_status), 825 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 826 status = le32toh(sqtd->qtd.qtd_status); 827 usb_syncmem(&sqtd->dma, 828 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 829 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 830 /* If there's an active QTD the xfer isn't done. */ 831 if (status & EHCI_QTD_ACTIVE) 832 break; 833 /* Any kind of error makes the xfer done. */ 834 if (status & EHCI_QTD_HALTED) 835 goto done; 836 /* We want short packets, and it is short: it's done */ 837 if (EHCI_QTD_GET_BYTES(status) != 0) 838 goto done; 839 } 840 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 841 ex, ex->sqtdstart)); 842 usb_syncmem(&lsqtd->dma, 843 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 844 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 845 return; 846 } 847 done: 848 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 849 callout_stop(&ex->xfer.timeout_handle); 850 ehci_idone(ex); 851 } 852 853 Static void 854 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 855 { 856 ehci_soft_itd_t *itd; 857 int i; 858 859 KASSERT(mutex_owned(&sc->sc_lock)); 860 861 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 862 return; 863 864 if (ex->itdstart == NULL) { 865 printf("ehci_check_itd_intr: not valid itd\n"); 866 return; 867 } 868 869 itd = ex->itdend; 870 #ifdef DIAGNOSTIC 871 if (itd == NULL) { 872 printf("ehci_check_itd_intr: itdend == 0\n"); 873 return; 874 } 875 #endif 876 877 /* 878 * check no active transfers in last itd, meaning we're finished 879 */ 880 881 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 882 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 883 BUS_DMASYNC_POSTREAD); 884 885 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 886 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 887 break; 888 } 889 890 if (i == EHCI_ITD_NUFRAMES) { 891 goto done; /* All 8 descriptors inactive, it's done */ 892 } 893 894 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 895 ex->itdstart)); 896 return; 897 done: 898 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 899 callout_stop(&ex->xfer.timeout_handle); 900 ehci_idone(ex); 901 } 902 903 Static void 904 ehci_idone(struct ehci_xfer *ex) 905 { 906 usbd_xfer_handle xfer = &ex->xfer; 907 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 908 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 909 ehci_soft_qtd_t *sqtd, *lsqtd; 910 u_int32_t status = 0, nstatus = 0; 911 int actlen; 912 913 KASSERT(mutex_owned(&sc->sc_lock)); 914 915 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 916 917 #ifdef DIAGNOSTIC 918 { 919 if (ex->isdone) { 920 #ifdef EHCI_DEBUG 921 printf("ehci_idone: ex is done!\n "); 922 ehci_dump_exfer(ex); 923 #else 924 printf("ehci_idone: ex=%p is done!\n", ex); 925 #endif 926 return; 927 } 928 ex->isdone = 1; 929 } 930 #endif 931 if (xfer->status == USBD_CANCELLED || 932 xfer->status == USBD_TIMEOUT) { 933 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 934 return; 935 } 936 937 #ifdef EHCI_DEBUG 938 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 939 if (ehcidebug > 10) 940 ehci_dump_sqtds(ex->sqtdstart); 941 #endif 942 943 /* The transfer is done, compute actual length and status. */ 944 945 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 946 == UE_ISOCHRONOUS) { 947 /* Isoc transfer */ 948 struct ehci_soft_itd *itd; 949 int i, nframes, len, uframes; 950 951 nframes = 0; 952 actlen = 0; 953 954 i = xfer->pipe->endpoint->edesc->bInterval; 955 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 956 957 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 958 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 959 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 960 BUS_DMASYNC_POSTREAD); 961 962 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 963 /* XXX - driver didn't fill in the frame full 964 * of uframes. This leads to scheduling 965 * inefficiencies, but working around 966 * this doubles complexity of tracking 967 * an xfer. 968 */ 969 if (nframes >= xfer->nframes) 970 break; 971 972 status = le32toh(itd->itd.itd_ctl[i]); 973 len = EHCI_ITD_GET_LEN(status); 974 if (EHCI_ITD_GET_STATUS(status) != 0) 975 len = 0; /*No valid data on error*/ 976 977 xfer->frlengths[nframes++] = len; 978 actlen += len; 979 } 980 981 if (nframes >= xfer->nframes) 982 break; 983 } 984 985 xfer->actlen = actlen; 986 xfer->status = USBD_NORMAL_COMPLETION; 987 goto end; 988 } 989 990 /* Continue processing xfers using queue heads */ 991 992 lsqtd = ex->sqtdend; 993 actlen = 0; 994 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 995 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 996 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 997 nstatus = le32toh(sqtd->qtd.qtd_status); 998 if (nstatus & EHCI_QTD_ACTIVE) 999 break; 1000 1001 status = nstatus; 1002 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1003 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1004 } 1005 1006 1007 /* 1008 * If there are left over TDs we need to update the toggle. 1009 * The default pipe doesn't need it since control transfers 1010 * start the toggle at 0 every time. 1011 * For a short transfer we need to update the toggle for the missing 1012 * packets within the qTD. 1013 */ 1014 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1015 xfer->pipe->device->default_pipe != xfer->pipe) { 1016 DPRINTFN(2, ("ehci_idone: need toggle update " 1017 "status=%08x nstatus=%08x\n", status, nstatus)); 1018 #if 0 1019 ehci_dump_sqh(epipe->sqh); 1020 ehci_dump_sqtds(ex->sqtdstart); 1021 #endif 1022 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1023 } 1024 1025 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 1026 xfer->length, actlen, status)); 1027 xfer->actlen = actlen; 1028 if (status & EHCI_QTD_HALTED) { 1029 #ifdef EHCI_DEBUG 1030 char sbuf[128]; 1031 1032 snprintb(sbuf, sizeof(sbuf), 1033 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 1034 (u_int32_t)status); 1035 1036 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 1037 "status 0x%s\n", 1038 xfer->pipe->device->address, 1039 xfer->pipe->endpoint->edesc->bEndpointAddress, 1040 sbuf)); 1041 if (ehcidebug > 2) { 1042 ehci_dump_sqh(epipe->sqh); 1043 ehci_dump_sqtds(ex->sqtdstart); 1044 } 1045 #endif 1046 /* low&full speed has an extra error flag */ 1047 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1048 EHCI_QH_SPEED_HIGH) 1049 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1050 else 1051 status &= EHCI_QTD_STATERRS; 1052 if (status == 0) /* no other errors means a stall */ { 1053 xfer->status = USBD_STALLED; 1054 } else { 1055 xfer->status = USBD_IOERROR; /* more info XXX */ 1056 } 1057 /* XXX need to reset TT on missed microframe */ 1058 if (status & EHCI_QTD_MISSEDMICRO) { 1059 printf("%s: missed microframe, TT reset not " 1060 "implemented, hub might be inoperational\n", 1061 device_xname(sc->sc_dev)); 1062 } 1063 } else { 1064 xfer->status = USBD_NORMAL_COMPLETION; 1065 } 1066 1067 end: 1068 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1069 * during this call, before methods->done is called: dma sync required 1070 * beforehand? */ 1071 usb_transfer_complete(xfer); 1072 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1073 } 1074 1075 /* 1076 * Wait here until controller claims to have an interrupt. 1077 * Then call ehci_intr and return. Use timeout to avoid waiting 1078 * too long. 1079 */ 1080 Static void 1081 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1082 { 1083 int timo; 1084 u_int32_t intrs; 1085 1086 xfer->status = USBD_IN_PROGRESS; 1087 for (timo = xfer->timeout; timo >= 0; timo--) { 1088 usb_delay_ms(&sc->sc_bus, 1); 1089 if (sc->sc_dying) 1090 break; 1091 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1092 sc->sc_eintrs; 1093 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1094 #ifdef EHCI_DEBUG 1095 if (ehcidebug > 15) 1096 ehci_dump_regs(sc); 1097 #endif 1098 if (intrs) { 1099 mutex_spin_enter(&sc->sc_intr_lock); 1100 ehci_intr1(sc); 1101 mutex_spin_exit(&sc->sc_intr_lock); 1102 if (xfer->status != USBD_IN_PROGRESS) 1103 return; 1104 } 1105 } 1106 1107 /* Timeout */ 1108 DPRINTF(("ehci_waitintr: timeout\n")); 1109 xfer->status = USBD_TIMEOUT; 1110 mutex_enter(&sc->sc_lock); 1111 usb_transfer_complete(xfer); 1112 mutex_exit(&sc->sc_lock); 1113 /* XXX should free TD */ 1114 } 1115 1116 Static void 1117 ehci_poll(struct usbd_bus *bus) 1118 { 1119 ehci_softc_t *sc = bus->hci_private; 1120 #ifdef EHCI_DEBUG 1121 static int last; 1122 int new; 1123 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1124 if (new != last) { 1125 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1126 last = new; 1127 } 1128 #endif 1129 1130 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1131 mutex_spin_enter(&sc->sc_intr_lock); 1132 ehci_intr1(sc); 1133 mutex_spin_exit(&sc->sc_intr_lock); 1134 } 1135 } 1136 1137 void 1138 ehci_childdet(device_t self, device_t child) 1139 { 1140 struct ehci_softc *sc = device_private(self); 1141 1142 KASSERT(sc->sc_child == child); 1143 sc->sc_child = NULL; 1144 } 1145 1146 int 1147 ehci_detach(struct ehci_softc *sc, int flags) 1148 { 1149 usbd_xfer_handle xfer; 1150 int rv = 0; 1151 1152 if (sc->sc_child != NULL) 1153 rv = config_detach(sc->sc_child, flags); 1154 1155 if (rv != 0) 1156 return (rv); 1157 1158 callout_halt(&sc->sc_tmo_intrlist, NULL); 1159 callout_destroy(&sc->sc_tmo_intrlist); 1160 1161 /* XXX free other data structures XXX */ 1162 if (sc->sc_softitds) 1163 kmem_free(sc->sc_softitds, 1164 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1165 cv_destroy(&sc->sc_doorbell); 1166 cv_destroy(&sc->sc_softwake_cv); 1167 1168 #if 0 1169 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1170 1171 softint_disestablish(sc->sc_doorbell_si); 1172 softint_disestablish(sc->sc_pcd_si); 1173 1174 mutex_destroy(&sc->sc_lock); 1175 mutex_destroy(&sc->sc_intr_lock); 1176 #endif 1177 1178 while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 1179 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1180 kmem_free(xfer, sizeof(struct ehci_xfer)); 1181 } 1182 1183 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1184 1185 return (rv); 1186 } 1187 1188 1189 int 1190 ehci_activate(device_t self, enum devact act) 1191 { 1192 struct ehci_softc *sc = device_private(self); 1193 1194 switch (act) { 1195 case DVACT_DEACTIVATE: 1196 sc->sc_dying = 1; 1197 return 0; 1198 default: 1199 return EOPNOTSUPP; 1200 } 1201 } 1202 1203 /* 1204 * Handle suspend/resume. 1205 * 1206 * We need to switch to polling mode here, because this routine is 1207 * called from an interrupt context. This is all right since we 1208 * are almost suspended anyway. 1209 * 1210 * Note that this power handler isn't to be registered directly; the 1211 * bus glue needs to call out to it. 1212 */ 1213 bool 1214 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1215 { 1216 ehci_softc_t *sc = device_private(dv); 1217 int i; 1218 uint32_t cmd, hcr; 1219 1220 mutex_spin_enter(&sc->sc_intr_lock); 1221 sc->sc_bus.use_polling++; 1222 mutex_spin_exit(&sc->sc_intr_lock); 1223 1224 for (i = 1; i <= sc->sc_noport; i++) { 1225 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1226 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1227 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1228 } 1229 1230 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1231 1232 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1233 EOWRITE4(sc, EHCI_USBCMD, cmd); 1234 1235 for (i = 0; i < 100; i++) { 1236 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1237 if (hcr == 0) 1238 break; 1239 1240 usb_delay_ms(&sc->sc_bus, 1); 1241 } 1242 if (hcr != 0) 1243 printf("%s: reset timeout\n", device_xname(dv)); 1244 1245 cmd &= ~EHCI_CMD_RS; 1246 EOWRITE4(sc, EHCI_USBCMD, cmd); 1247 1248 for (i = 0; i < 100; i++) { 1249 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1250 if (hcr == EHCI_STS_HCH) 1251 break; 1252 1253 usb_delay_ms(&sc->sc_bus, 1); 1254 } 1255 if (hcr != EHCI_STS_HCH) 1256 printf("%s: config timeout\n", device_xname(dv)); 1257 1258 mutex_spin_enter(&sc->sc_intr_lock); 1259 sc->sc_bus.use_polling--; 1260 mutex_spin_exit(&sc->sc_intr_lock); 1261 1262 return true; 1263 } 1264 1265 bool 1266 ehci_resume(device_t dv, const pmf_qual_t *qual) 1267 { 1268 ehci_softc_t *sc = device_private(dv); 1269 int i; 1270 uint32_t cmd, hcr; 1271 1272 /* restore things in case the bios sucks */ 1273 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1274 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1275 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1276 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1277 1278 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1279 1280 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1281 1282 hcr = 0; 1283 for (i = 1; i <= sc->sc_noport; i++) { 1284 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1285 if ((cmd & EHCI_PS_PO) == 0 && 1286 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1287 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1288 hcr = 1; 1289 } 1290 } 1291 1292 if (hcr) { 1293 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1294 1295 for (i = 1; i <= sc->sc_noport; i++) { 1296 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1297 if ((cmd & EHCI_PS_PO) == 0 && 1298 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1299 EOWRITE4(sc, EHCI_PORTSC(i), 1300 cmd & ~EHCI_PS_FPR); 1301 } 1302 } 1303 1304 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1305 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1306 1307 for (i = 0; i < 100; i++) { 1308 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1309 if (hcr != EHCI_STS_HCH) 1310 break; 1311 1312 usb_delay_ms(&sc->sc_bus, 1); 1313 } 1314 if (hcr == EHCI_STS_HCH) 1315 printf("%s: config timeout\n", device_xname(dv)); 1316 1317 return true; 1318 } 1319 1320 /* 1321 * Shut down the controller when the system is going down. 1322 */ 1323 bool 1324 ehci_shutdown(device_t self, int flags) 1325 { 1326 ehci_softc_t *sc = device_private(self); 1327 1328 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1329 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1330 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1331 return true; 1332 } 1333 1334 Static usbd_status 1335 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1336 { 1337 struct ehci_softc *sc = bus->hci_private; 1338 usbd_status err; 1339 1340 err = usb_allocmem(&sc->sc_bus, size, 0, dma); 1341 if (err == USBD_NOMEM) 1342 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1343 #ifdef EHCI_DEBUG 1344 if (err) 1345 printf("ehci_allocm: usb_allocmem()=%d\n", err); 1346 #endif 1347 return (err); 1348 } 1349 1350 Static void 1351 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1352 { 1353 struct ehci_softc *sc = bus->hci_private; 1354 1355 if (dma->block->flags & USB_DMA_RESERVE) { 1356 usb_reserve_freem(&sc->sc_dma_reserve, 1357 dma); 1358 return; 1359 } 1360 usb_freemem(&sc->sc_bus, dma); 1361 } 1362 1363 Static usbd_xfer_handle 1364 ehci_allocx(struct usbd_bus *bus) 1365 { 1366 struct ehci_softc *sc = bus->hci_private; 1367 usbd_xfer_handle xfer; 1368 1369 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1370 if (xfer != NULL) { 1371 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1372 #ifdef DIAGNOSTIC 1373 if (xfer->busy_free != XFER_FREE) { 1374 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1375 xfer->busy_free); 1376 } 1377 #endif 1378 } else { 1379 xfer = kmem_alloc(sizeof(struct ehci_xfer), KM_SLEEP); 1380 } 1381 if (xfer != NULL) { 1382 memset(xfer, 0, sizeof(struct ehci_xfer)); 1383 #ifdef DIAGNOSTIC 1384 EXFER(xfer)->isdone = 1; 1385 xfer->busy_free = XFER_BUSY; 1386 #endif 1387 } 1388 return (xfer); 1389 } 1390 1391 Static void 1392 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1393 { 1394 struct ehci_softc *sc = bus->hci_private; 1395 1396 #ifdef DIAGNOSTIC 1397 if (xfer->busy_free != XFER_BUSY) { 1398 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1399 xfer->busy_free); 1400 } 1401 xfer->busy_free = XFER_FREE; 1402 if (!EXFER(xfer)->isdone) { 1403 printf("ehci_freex: !isdone\n"); 1404 } 1405 #endif 1406 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1407 } 1408 1409 Static void 1410 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1411 { 1412 struct ehci_softc *sc = bus->hci_private; 1413 1414 *lock = &sc->sc_lock; 1415 } 1416 1417 Static void 1418 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1419 { 1420 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1421 1422 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1423 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1424 #ifdef EHCI_DEBUG 1425 if (ehcidebug) 1426 usbd_dump_pipe(pipe); 1427 #endif 1428 epipe->nexttoggle = 0; 1429 } 1430 1431 Static void 1432 ehci_noop(usbd_pipe_handle pipe) 1433 { 1434 } 1435 1436 #ifdef EHCI_DEBUG 1437 Static void 1438 ehci_dump_regs(ehci_softc_t *sc) 1439 { 1440 int i; 1441 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1442 EOREAD4(sc, EHCI_USBCMD), 1443 EOREAD4(sc, EHCI_USBSTS), 1444 EOREAD4(sc, EHCI_USBINTR)); 1445 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1446 EOREAD4(sc, EHCI_FRINDEX), 1447 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1448 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1449 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1450 for (i = 1; i <= sc->sc_noport; i++) 1451 printf("port %d status=0x%08x\n", i, 1452 EOREAD4(sc, EHCI_PORTSC(i))); 1453 } 1454 1455 /* 1456 * Unused function - this is meant to be called from a kernel 1457 * debugger. 1458 */ 1459 void 1460 ehci_dump(void) 1461 { 1462 ehci_dump_regs(theehci); 1463 } 1464 1465 Static void 1466 ehci_dump_link(ehci_link_t link, int type) 1467 { 1468 link = le32toh(link); 1469 printf("0x%08x", link); 1470 if (link & EHCI_LINK_TERMINATE) 1471 printf("<T>"); 1472 else { 1473 printf("<"); 1474 if (type) { 1475 switch (EHCI_LINK_TYPE(link)) { 1476 case EHCI_LINK_ITD: printf("ITD"); break; 1477 case EHCI_LINK_QH: printf("QH"); break; 1478 case EHCI_LINK_SITD: printf("SITD"); break; 1479 case EHCI_LINK_FSTN: printf("FSTN"); break; 1480 } 1481 } 1482 printf(">"); 1483 } 1484 } 1485 1486 Static void 1487 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1488 { 1489 int i; 1490 u_int32_t stop; 1491 1492 stop = 0; 1493 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1494 ehci_dump_sqtd(sqtd); 1495 usb_syncmem(&sqtd->dma, 1496 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1497 sizeof(sqtd->qtd), 1498 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1499 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1500 usb_syncmem(&sqtd->dma, 1501 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1502 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1503 } 1504 if (sqtd) 1505 printf("dump aborted, too many TDs\n"); 1506 } 1507 1508 Static void 1509 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1510 { 1511 usb_syncmem(&sqtd->dma, sqtd->offs, 1512 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1513 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1514 ehci_dump_qtd(&sqtd->qtd); 1515 usb_syncmem(&sqtd->dma, sqtd->offs, 1516 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1517 } 1518 1519 Static void 1520 ehci_dump_qtd(ehci_qtd_t *qtd) 1521 { 1522 u_int32_t s; 1523 char sbuf[128]; 1524 1525 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1526 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1527 printf("\n"); 1528 s = le32toh(qtd->qtd_status); 1529 snprintb(sbuf, sizeof(sbuf), 1530 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1531 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1532 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1533 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1534 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1535 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1536 EHCI_QTD_GET_PID(s), sbuf); 1537 for (s = 0; s < 5; s++) 1538 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1539 } 1540 1541 Static void 1542 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1543 { 1544 ehci_qh_t *qh = &sqh->qh; 1545 u_int32_t endp, endphub; 1546 1547 usb_syncmem(&sqh->dma, sqh->offs, 1548 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1549 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1550 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1551 endp = le32toh(qh->qh_endp); 1552 printf(" endp=0x%08x\n", endp); 1553 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1554 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1555 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1556 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1557 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1558 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1559 EHCI_QH_GET_NRL(endp)); 1560 endphub = le32toh(qh->qh_endphub); 1561 printf(" endphub=0x%08x\n", endphub); 1562 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1563 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1564 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1565 EHCI_QH_GET_MULT(endphub)); 1566 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1567 printf("Overlay qTD:\n"); 1568 ehci_dump_qtd(&qh->qh_qtd); 1569 usb_syncmem(&sqh->dma, sqh->offs, 1570 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1571 } 1572 1573 #if notyet 1574 Static void 1575 ehci_dump_itd(struct ehci_soft_itd *itd) 1576 { 1577 ehci_isoc_trans_t t; 1578 ehci_isoc_bufr_ptr_t b, b2, b3; 1579 int i; 1580 1581 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1582 1583 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1584 t = le32toh(itd->itd.itd_ctl[i]); 1585 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1586 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1587 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1588 EHCI_ITD_GET_OFFS(t)); 1589 } 1590 printf("ITDbufr: "); 1591 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1592 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1593 1594 b = le32toh(itd->itd.itd_bufr[0]); 1595 b2 = le32toh(itd->itd.itd_bufr[1]); 1596 b3 = le32toh(itd->itd.itd_bufr[2]); 1597 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1598 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1599 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1600 } 1601 1602 Static void 1603 ehci_dump_sitd(struct ehci_soft_itd *itd) 1604 { 1605 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1606 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1607 itd->xfer_next, itd->physaddr, itd->slot); 1608 } 1609 #endif 1610 1611 #ifdef DIAGNOSTIC 1612 Static void 1613 ehci_dump_exfer(struct ehci_xfer *ex) 1614 { 1615 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1616 } 1617 #endif 1618 #endif 1619 1620 Static usbd_status 1621 ehci_open(usbd_pipe_handle pipe) 1622 { 1623 usbd_device_handle dev = pipe->device; 1624 ehci_softc_t *sc = dev->bus->hci_private; 1625 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1626 u_int8_t addr = dev->address; 1627 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1628 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1629 ehci_soft_qh_t *sqh; 1630 usbd_status err; 1631 int ival, speed, naks; 1632 int hshubaddr, hshubport; 1633 1634 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1635 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1636 1637 if (dev->myhsport) { 1638 /* 1639 * When directly attached FS/LS device while doing embedded 1640 * transaction translations and we are the hub, set the hub 1641 * address to 0 (us). 1642 */ 1643 if (!(sc->sc_flags & EHCIF_ETTF) 1644 || (dev->myhsport->parent->address != sc->sc_addr)) { 1645 hshubaddr = dev->myhsport->parent->address; 1646 } else { 1647 hshubaddr = 0; 1648 } 1649 hshubport = dev->myhsport->portno; 1650 } else { 1651 hshubaddr = 0; 1652 hshubport = 0; 1653 } 1654 1655 if (sc->sc_dying) 1656 return (USBD_IOERROR); 1657 1658 /* toggle state needed for bulk endpoints */ 1659 epipe->nexttoggle = pipe->endpoint->datatoggle; 1660 1661 if (addr == sc->sc_addr) { 1662 switch (ed->bEndpointAddress) { 1663 case USB_CONTROL_ENDPOINT: 1664 pipe->methods = &ehci_root_ctrl_methods; 1665 break; 1666 case UE_DIR_IN | EHCI_INTR_ENDPT: 1667 pipe->methods = &ehci_root_intr_methods; 1668 break; 1669 default: 1670 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1671 ed->bEndpointAddress)); 1672 return (USBD_INVAL); 1673 } 1674 return (USBD_NORMAL_COMPLETION); 1675 } 1676 1677 /* XXX All this stuff is only valid for async. */ 1678 switch (dev->speed) { 1679 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1680 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1681 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1682 default: panic("ehci_open: bad device speed %d", dev->speed); 1683 } 1684 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1685 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1686 "isoc endpoint.\n"); 1687 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1688 "attached to a USB2 hub, and transaction translations are " 1689 "not yet supported.\n"); 1690 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1691 "root hub instead.\n"); 1692 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1693 hshubaddr, hshubport)); 1694 return USBD_INVAL; 1695 } 1696 1697 /* 1698 * For interrupt transfer, nak throttling must be disabled, but for 1699 * the other transfer type, nak throttling should be enabled from the 1700 * viewpoint that avoids the memory thrashing. 1701 */ 1702 naks = (xfertype == UE_INTERRUPT) ? 0 1703 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1704 1705 /* Allocate sqh for everything, save isoc xfers */ 1706 if (xfertype != UE_ISOCHRONOUS) { 1707 sqh = ehci_alloc_sqh(sc); 1708 if (sqh == NULL) 1709 return (USBD_NOMEM); 1710 /* qh_link filled when the QH is added */ 1711 sqh->qh.qh_endp = htole32( 1712 EHCI_QH_SET_ADDR(addr) | 1713 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1714 EHCI_QH_SET_EPS(speed) | 1715 EHCI_QH_DTC | 1716 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1717 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1718 EHCI_QH_CTL : 0) | 1719 EHCI_QH_SET_NRL(naks) 1720 ); 1721 sqh->qh.qh_endphub = htole32( 1722 EHCI_QH_SET_MULT(1) | 1723 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1724 ); 1725 if (speed != EHCI_QH_SPEED_HIGH) 1726 sqh->qh.qh_endphub |= htole32( 1727 EHCI_QH_SET_PORT(hshubport) | 1728 EHCI_QH_SET_HUBA(hshubaddr) | 1729 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1730 ); 1731 sqh->qh.qh_curqtd = EHCI_NULL; 1732 /* Fill the overlay qTD */ 1733 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1734 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1735 sqh->qh.qh_qtd.qtd_status = htole32(0); 1736 1737 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1738 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1739 epipe->sqh = sqh; 1740 } else { 1741 sqh = NULL; 1742 } /*xfertype == UE_ISOC*/ 1743 1744 switch (xfertype) { 1745 case UE_CONTROL: 1746 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1747 0, &epipe->u.ctl.reqdma); 1748 #ifdef EHCI_DEBUG 1749 if (err) 1750 printf("ehci_open: usb_allocmem()=%d\n", err); 1751 #endif 1752 if (err) 1753 goto bad; 1754 pipe->methods = &ehci_device_ctrl_methods; 1755 mutex_enter(&sc->sc_lock); 1756 ehci_add_qh(sc, sqh, sc->sc_async_head); 1757 mutex_exit(&sc->sc_lock); 1758 break; 1759 case UE_BULK: 1760 pipe->methods = &ehci_device_bulk_methods; 1761 mutex_enter(&sc->sc_lock); 1762 ehci_add_qh(sc, sqh, sc->sc_async_head); 1763 mutex_exit(&sc->sc_lock); 1764 break; 1765 case UE_INTERRUPT: 1766 pipe->methods = &ehci_device_intr_methods; 1767 ival = pipe->interval; 1768 if (ival == USBD_DEFAULT_INTERVAL) { 1769 if (speed == EHCI_QH_SPEED_HIGH) { 1770 if (ed->bInterval > 16) { 1771 /* 1772 * illegal with high-speed, but there 1773 * were documentation bugs in the spec, 1774 * so be generous 1775 */ 1776 ival = 256; 1777 } else 1778 ival = (1 << (ed->bInterval - 1)) / 8; 1779 } else 1780 ival = ed->bInterval; 1781 } 1782 err = ehci_device_setintr(sc, sqh, ival); 1783 if (err) 1784 goto bad; 1785 break; 1786 case UE_ISOCHRONOUS: 1787 pipe->methods = &ehci_device_isoc_methods; 1788 if (ed->bInterval == 0 || ed->bInterval > 16) { 1789 printf("ehci: opening pipe with invalid bInterval\n"); 1790 err = USBD_INVAL; 1791 goto bad; 1792 } 1793 if (UGETW(ed->wMaxPacketSize) == 0) { 1794 printf("ehci: zero length endpoint open request\n"); 1795 err = USBD_INVAL; 1796 goto bad; 1797 } 1798 epipe->u.isoc.next_frame = 0; 1799 epipe->u.isoc.cur_xfers = 0; 1800 break; 1801 default: 1802 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1803 err = USBD_INVAL; 1804 goto bad; 1805 } 1806 return (USBD_NORMAL_COMPLETION); 1807 1808 bad: 1809 if (sqh != NULL) 1810 ehci_free_sqh(sc, sqh); 1811 return (err); 1812 } 1813 1814 /* 1815 * Add an ED to the schedule. Called with USB lock held. 1816 */ 1817 Static void 1818 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1819 { 1820 1821 KASSERT(mutex_owned(&sc->sc_lock)); 1822 1823 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1824 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1825 sqh->next = head->next; 1826 sqh->qh.qh_link = head->qh.qh_link; 1827 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1828 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1829 head->next = sqh; 1830 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1831 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1832 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1833 1834 #ifdef EHCI_DEBUG 1835 if (ehcidebug > 5) { 1836 printf("ehci_add_qh:\n"); 1837 ehci_dump_sqh(sqh); 1838 } 1839 #endif 1840 } 1841 1842 /* 1843 * Remove an ED from the schedule. Called with USB lock held. 1844 */ 1845 Static void 1846 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1847 { 1848 ehci_soft_qh_t *p; 1849 1850 KASSERT(mutex_owned(&sc->sc_lock)); 1851 1852 /* XXX */ 1853 for (p = head; p != NULL && p->next != sqh; p = p->next) 1854 ; 1855 if (p == NULL) 1856 panic("ehci_rem_qh: ED not found"); 1857 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1858 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1859 p->next = sqh->next; 1860 p->qh.qh_link = sqh->qh.qh_link; 1861 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1862 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1863 1864 ehci_sync_hc(sc); 1865 } 1866 1867 Static void 1868 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1869 { 1870 int i; 1871 u_int32_t status; 1872 1873 /* Save toggle bit and ping status. */ 1874 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1875 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1876 status = sqh->qh.qh_qtd.qtd_status & 1877 htole32(EHCI_QTD_TOGGLE_MASK | 1878 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1879 /* Set HALTED to make hw leave it alone. */ 1880 sqh->qh.qh_qtd.qtd_status = 1881 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1882 usb_syncmem(&sqh->dma, 1883 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1884 sizeof(sqh->qh.qh_qtd.qtd_status), 1885 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1886 sqh->qh.qh_curqtd = 0; 1887 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1888 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1889 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1890 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1891 sqh->sqtd = sqtd; 1892 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1893 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1894 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1895 sqh->qh.qh_qtd.qtd_status = status; 1896 usb_syncmem(&sqh->dma, 1897 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1898 sizeof(sqh->qh.qh_qtd.qtd_status), 1899 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1900 } 1901 1902 /* 1903 * Ensure that the HC has released all references to the QH. We do this 1904 * by asking for a Async Advance Doorbell interrupt and then we wait for 1905 * the interrupt. 1906 * To make this easier we first obtain exclusive use of the doorbell. 1907 */ 1908 Static void 1909 ehci_sync_hc(ehci_softc_t *sc) 1910 { 1911 int error; 1912 1913 KASSERT(mutex_owned(&sc->sc_lock)); 1914 1915 if (sc->sc_dying) { 1916 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1917 return; 1918 } 1919 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1920 /* ask for doorbell */ 1921 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1922 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1923 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1924 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 1925 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1926 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1927 #ifdef DIAGNOSTIC 1928 if (error) 1929 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 1930 #endif 1931 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1932 } 1933 1934 Static void 1935 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1936 { 1937 struct ehci_soft_itd *itd, *prev; 1938 1939 prev = NULL; 1940 1941 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1942 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1943 1944 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1945 prev = itd->u.frame_list.prev; 1946 /* Unlink itd from hardware chain, or frame array */ 1947 if (prev == NULL) { /* We're at the table head */ 1948 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1949 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1950 usb_syncmem(&sc->sc_fldma, 1951 sizeof(ehci_link_t) * itd->slot, 1952 sizeof(ehci_link_t), 1953 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1954 1955 if (itd->u.frame_list.next != NULL) 1956 itd->u.frame_list.next->u.frame_list.prev = NULL; 1957 } else { 1958 /* XXX this part is untested... */ 1959 prev->itd.itd_next = itd->itd.itd_next; 1960 usb_syncmem(&itd->dma, 1961 itd->offs + offsetof(ehci_itd_t, itd_next), 1962 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1963 1964 prev->u.frame_list.next = itd->u.frame_list.next; 1965 if (itd->u.frame_list.next != NULL) 1966 itd->u.frame_list.next->u.frame_list.prev = prev; 1967 } 1968 } 1969 1970 prev = NULL; 1971 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1972 if (prev != NULL) 1973 ehci_free_itd(sc, prev); 1974 prev = itd; 1975 } 1976 if (prev) 1977 ehci_free_itd(sc, prev); 1978 exfer->itdstart = NULL; 1979 exfer->itdend = NULL; 1980 } 1981 1982 /***********/ 1983 1984 /* 1985 * Data structures and routines to emulate the root hub. 1986 */ 1987 Static usb_device_descriptor_t ehci_devd = { 1988 USB_DEVICE_DESCRIPTOR_SIZE, 1989 UDESC_DEVICE, /* type */ 1990 {0x00, 0x02}, /* USB version */ 1991 UDCLASS_HUB, /* class */ 1992 UDSUBCLASS_HUB, /* subclass */ 1993 UDPROTO_HSHUBSTT, /* protocol */ 1994 64, /* max packet */ 1995 {0},{0},{0x00,0x01}, /* device id */ 1996 1,2,0, /* string indicies */ 1997 1 /* # of configurations */ 1998 }; 1999 2000 Static const usb_device_qualifier_t ehci_odevd = { 2001 USB_DEVICE_DESCRIPTOR_SIZE, 2002 UDESC_DEVICE_QUALIFIER, /* type */ 2003 {0x00, 0x02}, /* USB version */ 2004 UDCLASS_HUB, /* class */ 2005 UDSUBCLASS_HUB, /* subclass */ 2006 UDPROTO_FSHUB, /* protocol */ 2007 64, /* max packet */ 2008 1, /* # of configurations */ 2009 0 2010 }; 2011 2012 Static const usb_config_descriptor_t ehci_confd = { 2013 USB_CONFIG_DESCRIPTOR_SIZE, 2014 UDESC_CONFIG, 2015 {USB_CONFIG_DESCRIPTOR_SIZE + 2016 USB_INTERFACE_DESCRIPTOR_SIZE + 2017 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2018 1, 2019 1, 2020 0, 2021 UC_ATTR_MBO | UC_SELF_POWERED, 2022 0 /* max power */ 2023 }; 2024 2025 Static const usb_interface_descriptor_t ehci_ifcd = { 2026 USB_INTERFACE_DESCRIPTOR_SIZE, 2027 UDESC_INTERFACE, 2028 0, 2029 0, 2030 1, 2031 UICLASS_HUB, 2032 UISUBCLASS_HUB, 2033 UIPROTO_HSHUBSTT, 2034 0 2035 }; 2036 2037 Static const usb_endpoint_descriptor_t ehci_endpd = { 2038 USB_ENDPOINT_DESCRIPTOR_SIZE, 2039 UDESC_ENDPOINT, 2040 UE_DIR_IN | EHCI_INTR_ENDPT, 2041 UE_INTERRUPT, 2042 {8, 0}, /* max packet */ 2043 12 2044 }; 2045 2046 Static const usb_hub_descriptor_t ehci_hubd = { 2047 USB_HUB_DESCRIPTOR_SIZE, 2048 UDESC_HUB, 2049 0, 2050 {0,0}, 2051 0, 2052 0, 2053 {""}, 2054 {""}, 2055 }; 2056 2057 /* 2058 * Simulate a hardware hub by handling all the necessary requests. 2059 */ 2060 Static usbd_status 2061 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2062 { 2063 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2064 usbd_status err; 2065 2066 /* Insert last in queue. */ 2067 mutex_enter(&sc->sc_lock); 2068 err = usb_insert_transfer(xfer); 2069 mutex_exit(&sc->sc_lock); 2070 if (err) 2071 return (err); 2072 2073 /* Pipe isn't running, start first */ 2074 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2075 } 2076 2077 Static usbd_status 2078 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2079 { 2080 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2081 usb_device_request_t *req; 2082 void *buf = NULL; 2083 int port, i; 2084 int len, value, index, l, totlen = 0; 2085 usb_port_status_t ps; 2086 usb_hub_descriptor_t hubd; 2087 usbd_status err; 2088 u_int32_t v; 2089 2090 if (sc->sc_dying) 2091 return (USBD_IOERROR); 2092 2093 #ifdef DIAGNOSTIC 2094 if (!(xfer->rqflags & URQ_REQUEST)) 2095 /* XXX panic */ 2096 return (USBD_INVAL); 2097 #endif 2098 req = &xfer->request; 2099 2100 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2101 req->bmRequestType, req->bRequest)); 2102 2103 len = UGETW(req->wLength); 2104 value = UGETW(req->wValue); 2105 index = UGETW(req->wIndex); 2106 2107 if (len != 0) 2108 buf = KERNADDR(&xfer->dmabuf, 0); 2109 2110 #define C(x,y) ((x) | ((y) << 8)) 2111 switch(C(req->bRequest, req->bmRequestType)) { 2112 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2113 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2114 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2115 /* 2116 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2117 * for the integrated root hub. 2118 */ 2119 break; 2120 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2121 if (len > 0) { 2122 *(u_int8_t *)buf = sc->sc_conf; 2123 totlen = 1; 2124 } 2125 break; 2126 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2127 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2128 if (len == 0) 2129 break; 2130 switch(value >> 8) { 2131 case UDESC_DEVICE: 2132 if ((value & 0xff) != 0) { 2133 err = USBD_IOERROR; 2134 goto ret; 2135 } 2136 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2137 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2138 memcpy(buf, &ehci_devd, l); 2139 break; 2140 /* 2141 * We can't really operate at another speed, but the spec says 2142 * we need this descriptor. 2143 */ 2144 case UDESC_DEVICE_QUALIFIER: 2145 if ((value & 0xff) != 0) { 2146 err = USBD_IOERROR; 2147 goto ret; 2148 } 2149 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2150 memcpy(buf, &ehci_odevd, l); 2151 break; 2152 /* 2153 * We can't really operate at another speed, but the spec says 2154 * we need this descriptor. 2155 */ 2156 case UDESC_OTHER_SPEED_CONFIGURATION: 2157 case UDESC_CONFIG: 2158 if ((value & 0xff) != 0) { 2159 err = USBD_IOERROR; 2160 goto ret; 2161 } 2162 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2163 memcpy(buf, &ehci_confd, l); 2164 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2165 value >> 8; 2166 buf = (char *)buf + l; 2167 len -= l; 2168 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2169 totlen += l; 2170 memcpy(buf, &ehci_ifcd, l); 2171 buf = (char *)buf + l; 2172 len -= l; 2173 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2174 totlen += l; 2175 memcpy(buf, &ehci_endpd, l); 2176 break; 2177 case UDESC_STRING: 2178 #define sd ((usb_string_descriptor_t *)buf) 2179 switch (value & 0xff) { 2180 case 0: /* Language table */ 2181 totlen = usb_makelangtbl(sd, len); 2182 break; 2183 case 1: /* Vendor */ 2184 totlen = usb_makestrdesc(sd, len, 2185 sc->sc_vendor); 2186 break; 2187 case 2: /* Product */ 2188 totlen = usb_makestrdesc(sd, len, 2189 "EHCI root hub"); 2190 break; 2191 } 2192 #undef sd 2193 break; 2194 default: 2195 err = USBD_IOERROR; 2196 goto ret; 2197 } 2198 break; 2199 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2200 if (len > 0) { 2201 *(u_int8_t *)buf = 0; 2202 totlen = 1; 2203 } 2204 break; 2205 case C(UR_GET_STATUS, UT_READ_DEVICE): 2206 if (len > 1) { 2207 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2208 totlen = 2; 2209 } 2210 break; 2211 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2212 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2213 if (len > 1) { 2214 USETW(((usb_status_t *)buf)->wStatus, 0); 2215 totlen = 2; 2216 } 2217 break; 2218 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2219 if (value >= USB_MAX_DEVICES) { 2220 err = USBD_IOERROR; 2221 goto ret; 2222 } 2223 sc->sc_addr = value; 2224 break; 2225 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2226 if (value != 0 && value != 1) { 2227 err = USBD_IOERROR; 2228 goto ret; 2229 } 2230 sc->sc_conf = value; 2231 break; 2232 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2233 break; 2234 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2235 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2236 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2237 err = USBD_IOERROR; 2238 goto ret; 2239 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2240 break; 2241 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2242 break; 2243 /* Hub requests */ 2244 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2245 break; 2246 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2247 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2248 "port=%d feature=%d\n", 2249 index, value)); 2250 if (index < 1 || index > sc->sc_noport) { 2251 err = USBD_IOERROR; 2252 goto ret; 2253 } 2254 port = EHCI_PORTSC(index); 2255 v = EOREAD4(sc, port); 2256 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2257 v &= ~EHCI_PS_CLEAR; 2258 switch(value) { 2259 case UHF_PORT_ENABLE: 2260 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2261 break; 2262 case UHF_PORT_SUSPEND: 2263 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2264 break; 2265 v &= ~EHCI_PS_SUSP; 2266 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2267 /* see USB2 spec ch. 7.1.7.7 */ 2268 usb_delay_ms(&sc->sc_bus, 20); 2269 EOWRITE4(sc, port, v); 2270 usb_delay_ms(&sc->sc_bus, 2); 2271 #ifdef DEBUG 2272 v = EOREAD4(sc, port); 2273 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2274 printf("ehci: resume failed: %x\n", v); 2275 #endif 2276 break; 2277 case UHF_PORT_POWER: 2278 if (sc->sc_hasppc) 2279 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2280 break; 2281 case UHF_PORT_TEST: 2282 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2283 "%d\n", index)); 2284 break; 2285 case UHF_PORT_INDICATOR: 2286 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2287 "%d\n", index)); 2288 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2289 break; 2290 case UHF_C_PORT_CONNECTION: 2291 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2292 break; 2293 case UHF_C_PORT_ENABLE: 2294 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2295 break; 2296 case UHF_C_PORT_SUSPEND: 2297 /* how? */ 2298 break; 2299 case UHF_C_PORT_OVER_CURRENT: 2300 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2301 break; 2302 case UHF_C_PORT_RESET: 2303 sc->sc_isreset[index] = 0; 2304 break; 2305 default: 2306 err = USBD_IOERROR; 2307 goto ret; 2308 } 2309 #if 0 2310 switch(value) { 2311 case UHF_C_PORT_CONNECTION: 2312 case UHF_C_PORT_ENABLE: 2313 case UHF_C_PORT_SUSPEND: 2314 case UHF_C_PORT_OVER_CURRENT: 2315 case UHF_C_PORT_RESET: 2316 default: 2317 break; 2318 } 2319 #endif 2320 break; 2321 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2322 if (len == 0) 2323 break; 2324 if ((value & 0xff) != 0) { 2325 err = USBD_IOERROR; 2326 goto ret; 2327 } 2328 hubd = ehci_hubd; 2329 hubd.bNbrPorts = sc->sc_noport; 2330 v = EOREAD4(sc, EHCI_HCSPARAMS); 2331 USETW(hubd.wHubCharacteristics, 2332 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2333 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2334 ? UHD_PORT_IND : 0); 2335 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2336 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2337 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2338 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2339 l = min(len, hubd.bDescLength); 2340 totlen = l; 2341 memcpy(buf, &hubd, l); 2342 break; 2343 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2344 if (len != 4) { 2345 err = USBD_IOERROR; 2346 goto ret; 2347 } 2348 memset(buf, 0, len); /* ? XXX */ 2349 totlen = len; 2350 break; 2351 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2352 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2353 index)); 2354 if (index < 1 || index > sc->sc_noport) { 2355 err = USBD_IOERROR; 2356 goto ret; 2357 } 2358 if (len != 4) { 2359 err = USBD_IOERROR; 2360 goto ret; 2361 } 2362 v = EOREAD4(sc, EHCI_PORTSC(index)); 2363 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2364 2365 i = UPS_HIGH_SPEED; 2366 #if 0 2367 if (sc->sc_flags & EHCIF_ETTF) { 2368 /* 2369 * If we are doing embedded transaction translation, 2370 * then directly attached LS/FS devices are reset by 2371 * the EHCI controller itself. PSPD is encoded 2372 * the same way as in USBSTATUS. 2373 */ 2374 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2375 } 2376 #endif 2377 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2378 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2379 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2380 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2381 if (v & EHCI_PS_PR) i |= UPS_RESET; 2382 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2383 if (sc->sc_vendor_port_status) 2384 i = sc->sc_vendor_port_status(sc, v, i); 2385 USETW(ps.wPortStatus, i); 2386 i = 0; 2387 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2388 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2389 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2390 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2391 USETW(ps.wPortChange, i); 2392 l = min(len, sizeof ps); 2393 memcpy(buf, &ps, l); 2394 totlen = l; 2395 break; 2396 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2397 err = USBD_IOERROR; 2398 goto ret; 2399 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2400 break; 2401 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2402 if (index < 1 || index > sc->sc_noport) { 2403 err = USBD_IOERROR; 2404 goto ret; 2405 } 2406 port = EHCI_PORTSC(index); 2407 v = EOREAD4(sc, port); 2408 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2409 v &= ~EHCI_PS_CLEAR; 2410 switch(value) { 2411 case UHF_PORT_ENABLE: 2412 EOWRITE4(sc, port, v | EHCI_PS_PE); 2413 break; 2414 case UHF_PORT_SUSPEND: 2415 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2416 break; 2417 case UHF_PORT_RESET: 2418 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2419 index)); 2420 if (EHCI_PS_IS_LOWSPEED(v) 2421 && sc->sc_ncomp > 0 2422 && !(sc->sc_flags & EHCIF_ETTF)) { 2423 /* 2424 * Low speed device on non-ETTF controller or 2425 * unaccompanied controller, give up ownership. 2426 */ 2427 ehci_disown(sc, index, 1); 2428 break; 2429 } 2430 /* Start reset sequence. */ 2431 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2432 EOWRITE4(sc, port, v | EHCI_PS_PR); 2433 /* Wait for reset to complete. */ 2434 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2435 if (sc->sc_dying) { 2436 err = USBD_IOERROR; 2437 goto ret; 2438 } 2439 /* 2440 * An embedded transaction translater will automatically 2441 * terminate the reset sequence so there's no need to 2442 * it. 2443 */ 2444 v = EOREAD4(sc, port); 2445 if (v & EHCI_PS_PR) { 2446 /* Terminate reset sequence. */ 2447 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2448 /* Wait for HC to complete reset. */ 2449 usb_delay_ms(&sc->sc_bus, 2450 EHCI_PORT_RESET_COMPLETE); 2451 if (sc->sc_dying) { 2452 err = USBD_IOERROR; 2453 goto ret; 2454 } 2455 } 2456 2457 v = EOREAD4(sc, port); 2458 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2459 if (v & EHCI_PS_PR) { 2460 printf("%s: port reset timeout\n", 2461 device_xname(sc->sc_dev)); 2462 return (USBD_TIMEOUT); 2463 } 2464 if (!(v & EHCI_PS_PE)) { 2465 /* Not a high speed device, give up ownership.*/ 2466 ehci_disown(sc, index, 0); 2467 break; 2468 } 2469 sc->sc_isreset[index] = 1; 2470 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2471 index, v)); 2472 break; 2473 case UHF_PORT_POWER: 2474 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2475 "%d (has PPC = %d)\n", index, 2476 sc->sc_hasppc)); 2477 if (sc->sc_hasppc) 2478 EOWRITE4(sc, port, v | EHCI_PS_PP); 2479 break; 2480 case UHF_PORT_TEST: 2481 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2482 "%d\n", index)); 2483 break; 2484 case UHF_PORT_INDICATOR: 2485 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2486 "%d\n", index)); 2487 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2488 break; 2489 default: 2490 err = USBD_IOERROR; 2491 goto ret; 2492 } 2493 break; 2494 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2495 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2496 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2497 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2498 break; 2499 default: 2500 err = USBD_IOERROR; 2501 goto ret; 2502 } 2503 xfer->actlen = totlen; 2504 err = USBD_NORMAL_COMPLETION; 2505 ret: 2506 mutex_enter(&sc->sc_lock); 2507 xfer->status = err; 2508 usb_transfer_complete(xfer); 2509 mutex_exit(&sc->sc_lock); 2510 return (USBD_IN_PROGRESS); 2511 } 2512 2513 Static void 2514 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2515 { 2516 int port; 2517 u_int32_t v; 2518 2519 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2520 #ifdef DIAGNOSTIC 2521 if (sc->sc_npcomp != 0) { 2522 int i = (index-1) / sc->sc_npcomp; 2523 if (i >= sc->sc_ncomp) 2524 printf("%s: strange port\n", 2525 device_xname(sc->sc_dev)); 2526 else 2527 printf("%s: handing over %s speed device on " 2528 "port %d to %s\n", 2529 device_xname(sc->sc_dev), 2530 lowspeed ? "low" : "full", 2531 index, device_xname(sc->sc_comps[i])); 2532 } else { 2533 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2534 } 2535 #endif 2536 port = EHCI_PORTSC(index); 2537 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2538 EOWRITE4(sc, port, v | EHCI_PS_PO); 2539 } 2540 2541 /* Abort a root control request. */ 2542 Static void 2543 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2544 { 2545 /* Nothing to do, all transfers are synchronous. */ 2546 } 2547 2548 /* Close the root pipe. */ 2549 Static void 2550 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2551 { 2552 DPRINTF(("ehci_root_ctrl_close\n")); 2553 /* Nothing to do. */ 2554 } 2555 2556 Static void 2557 ehci_root_intr_done(usbd_xfer_handle xfer) 2558 { 2559 xfer->hcpriv = NULL; 2560 } 2561 2562 Static usbd_status 2563 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2564 { 2565 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2566 usbd_status err; 2567 2568 /* Insert last in queue. */ 2569 mutex_enter(&sc->sc_lock); 2570 err = usb_insert_transfer(xfer); 2571 mutex_exit(&sc->sc_lock); 2572 if (err) 2573 return (err); 2574 2575 /* Pipe isn't running, start first */ 2576 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2577 } 2578 2579 Static usbd_status 2580 ehci_root_intr_start(usbd_xfer_handle xfer) 2581 { 2582 usbd_pipe_handle pipe = xfer->pipe; 2583 ehci_softc_t *sc = pipe->device->bus->hci_private; 2584 2585 if (sc->sc_dying) 2586 return (USBD_IOERROR); 2587 2588 mutex_enter(&sc->sc_lock); 2589 sc->sc_intrxfer = xfer; 2590 mutex_exit(&sc->sc_lock); 2591 2592 return (USBD_IN_PROGRESS); 2593 } 2594 2595 /* Abort a root interrupt request. */ 2596 Static void 2597 ehci_root_intr_abort(usbd_xfer_handle xfer) 2598 { 2599 #ifdef DIAGNOSTIC 2600 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2601 #endif 2602 2603 KASSERT(mutex_owned(&sc->sc_lock)); 2604 if (xfer->pipe->intrxfer == xfer) { 2605 DPRINTF(("ehci_root_intr_abort: remove\n")); 2606 xfer->pipe->intrxfer = NULL; 2607 } 2608 xfer->status = USBD_CANCELLED; 2609 usb_transfer_complete(xfer); 2610 } 2611 2612 /* Close the root pipe. */ 2613 Static void 2614 ehci_root_intr_close(usbd_pipe_handle pipe) 2615 { 2616 ehci_softc_t *sc = pipe->device->bus->hci_private; 2617 2618 KASSERT(mutex_owned(&sc->sc_lock)); 2619 2620 DPRINTF(("ehci_root_intr_close\n")); 2621 2622 sc->sc_intrxfer = NULL; 2623 } 2624 2625 Static void 2626 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2627 { 2628 xfer->hcpriv = NULL; 2629 } 2630 2631 /************************/ 2632 2633 Static ehci_soft_qh_t * 2634 ehci_alloc_sqh(ehci_softc_t *sc) 2635 { 2636 ehci_soft_qh_t *sqh; 2637 usbd_status err; 2638 int i, offs; 2639 usb_dma_t dma; 2640 2641 if (sc->sc_freeqhs == NULL) { 2642 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2643 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2644 EHCI_PAGE_SIZE, &dma); 2645 #ifdef EHCI_DEBUG 2646 if (err) 2647 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2648 #endif 2649 if (err) 2650 return (NULL); 2651 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2652 offs = i * EHCI_SQH_SIZE; 2653 sqh = KERNADDR(&dma, offs); 2654 sqh->physaddr = DMAADDR(&dma, offs); 2655 sqh->dma = dma; 2656 sqh->offs = offs; 2657 sqh->next = sc->sc_freeqhs; 2658 sc->sc_freeqhs = sqh; 2659 } 2660 } 2661 sqh = sc->sc_freeqhs; 2662 sc->sc_freeqhs = sqh->next; 2663 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2664 sqh->next = NULL; 2665 return (sqh); 2666 } 2667 2668 Static void 2669 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2670 { 2671 sqh->next = sc->sc_freeqhs; 2672 sc->sc_freeqhs = sqh; 2673 } 2674 2675 Static ehci_soft_qtd_t * 2676 ehci_alloc_sqtd(ehci_softc_t *sc) 2677 { 2678 ehci_soft_qtd_t *sqtd = NULL; 2679 usbd_status err; 2680 int i, offs; 2681 usb_dma_t dma; 2682 2683 if (sc->sc_freeqtds == NULL) { 2684 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2685 2686 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2687 EHCI_PAGE_SIZE, &dma); 2688 #ifdef EHCI_DEBUG 2689 if (err) 2690 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2691 #endif 2692 if (err) 2693 goto done; 2694 2695 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2696 offs = i * EHCI_SQTD_SIZE; 2697 sqtd = KERNADDR(&dma, offs); 2698 sqtd->physaddr = DMAADDR(&dma, offs); 2699 sqtd->dma = dma; 2700 sqtd->offs = offs; 2701 2702 sqtd->nextqtd = sc->sc_freeqtds; 2703 sc->sc_freeqtds = sqtd; 2704 } 2705 } 2706 2707 sqtd = sc->sc_freeqtds; 2708 sc->sc_freeqtds = sqtd->nextqtd; 2709 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2710 sqtd->nextqtd = NULL; 2711 sqtd->xfer = NULL; 2712 2713 done: 2714 return (sqtd); 2715 } 2716 2717 Static void 2718 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2719 { 2720 2721 KASSERT(mutex_owned(&sc->sc_lock)); 2722 2723 sqtd->nextqtd = sc->sc_freeqtds; 2724 sc->sc_freeqtds = sqtd; 2725 } 2726 2727 Static usbd_status 2728 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2729 int alen, int rd, usbd_xfer_handle xfer, 2730 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2731 { 2732 ehci_soft_qtd_t *next, *cur; 2733 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys; 2734 u_int32_t qtdstatus; 2735 int len, curlen, mps; 2736 int i, tog; 2737 usb_dma_t *dma = &xfer->dmabuf; 2738 u_int16_t flags = xfer->flags; 2739 2740 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2741 2742 len = alen; 2743 dataphys = DMAADDR(dma, 0); 2744 dataphyslastpage = EHCI_PAGE(dataphys + len - 1); 2745 qtdstatus = EHCI_QTD_ACTIVE | 2746 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2747 EHCI_QTD_SET_CERR(3) 2748 /* IOC set below */ 2749 /* BYTES set below */ 2750 ; 2751 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2752 tog = epipe->nexttoggle; 2753 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2754 2755 cur = ehci_alloc_sqtd(sc); 2756 *sp = cur; 2757 if (cur == NULL) 2758 goto nomem; 2759 2760 usb_syncmem(dma, 0, alen, 2761 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2762 for (;;) { 2763 dataphyspage = EHCI_PAGE(dataphys); 2764 /* The EHCI hardware can handle at most 5 pages. */ 2765 if (dataphyslastpage - dataphyspage < 2766 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) { 2767 /* we can handle it in this QTD */ 2768 curlen = len; 2769 } else { 2770 /* must use multiple TDs, fill as much as possible. */ 2771 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - 2772 EHCI_PAGE_OFFSET(dataphys); 2773 #ifdef DIAGNOSTIC 2774 if (curlen > len) { 2775 printf("ehci_alloc_sqtd_chain: curlen=0x%x " 2776 "len=0x%x offs=0x%x\n", curlen, len, 2777 EHCI_PAGE_OFFSET(dataphys)); 2778 printf("lastpage=0x%x page=0x%x phys=0x%x\n", 2779 dataphyslastpage, dataphyspage, 2780 dataphys); 2781 curlen = len; 2782 } 2783 #endif 2784 /* the length must be a multiple of the max size */ 2785 curlen -= curlen % mps; 2786 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2787 "curlen=%d\n", curlen)); 2788 #ifdef DIAGNOSTIC 2789 if (curlen == 0) 2790 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2791 #endif 2792 } 2793 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x " 2794 "dataphyslastpage=0x%08x len=%d curlen=%d\n", 2795 dataphys, dataphyslastpage, 2796 len, curlen)); 2797 len -= curlen; 2798 2799 /* 2800 * Allocate another transfer if there's more data left, 2801 * or if force last short transfer flag is set and we're 2802 * allocating a multiple of the max packet size. 2803 */ 2804 if (len != 0 || 2805 ((curlen % mps) == 0 && !rd && curlen != 0 && 2806 (flags & USBD_FORCE_SHORT_XFER))) { 2807 next = ehci_alloc_sqtd(sc); 2808 if (next == NULL) 2809 goto nomem; 2810 nextphys = htole32(next->physaddr); 2811 } else { 2812 next = NULL; 2813 nextphys = EHCI_NULL; 2814 } 2815 2816 for (i = 0; i * EHCI_PAGE_SIZE < 2817 curlen + EHCI_PAGE_OFFSET(dataphys); i++) { 2818 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE; 2819 if (i != 0) /* use offset only in first buffer */ 2820 a = EHCI_PAGE(a); 2821 if (i >= EHCI_QTD_NBUFFERS) { 2822 #ifdef DIAGNOSTIC 2823 printf("ehci_alloc_sqtd_chain: i=%d\n", i); 2824 #endif 2825 goto nomem; 2826 } 2827 cur->qtd.qtd_buffer[i] = htole32(a); 2828 cur->qtd.qtd_buffer_hi[i] = 0; 2829 } 2830 cur->nextqtd = next; 2831 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2832 cur->qtd.qtd_status = 2833 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2834 cur->xfer = xfer; 2835 cur->len = curlen; 2836 2837 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2838 dataphys, dataphys + curlen)); 2839 /* adjust the toggle based on the number of packets in this 2840 qtd */ 2841 if (((curlen + mps - 1) / mps) & 1) { 2842 tog ^= 1; 2843 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2844 } 2845 if (next == NULL) 2846 break; 2847 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2848 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2849 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2850 if (len) 2851 dataphys += curlen; 2852 cur = next; 2853 } 2854 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2855 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2856 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2857 *ep = cur; 2858 epipe->nexttoggle = tog; 2859 2860 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2861 *sp, *ep)); 2862 2863 return (USBD_NORMAL_COMPLETION); 2864 2865 nomem: 2866 /* XXX free chain */ 2867 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2868 return (USBD_NOMEM); 2869 } 2870 2871 Static void 2872 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2873 ehci_soft_qtd_t *sqtdend) 2874 { 2875 ehci_soft_qtd_t *p; 2876 int i; 2877 2878 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2879 sqtd, sqtdend)); 2880 2881 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2882 p = sqtd->nextqtd; 2883 ehci_free_sqtd(sc, sqtd); 2884 } 2885 } 2886 2887 Static ehci_soft_itd_t * 2888 ehci_alloc_itd(ehci_softc_t *sc) 2889 { 2890 struct ehci_soft_itd *itd, *freeitd; 2891 usbd_status err; 2892 int i, offs, frindex, previndex; 2893 usb_dma_t dma; 2894 2895 mutex_enter(&sc->sc_lock); 2896 2897 /* Find an itd that wasn't freed this frame or last frame. This can 2898 * discard itds that were freed before frindex wrapped around 2899 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2900 * interrupt and fiddling with list when that happens */ 2901 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2902 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2903 2904 freeitd = NULL; 2905 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2906 if (itd == NULL) 2907 break; 2908 if (itd->slot != frindex && itd->slot != previndex) { 2909 freeitd = itd; 2910 break; 2911 } 2912 } 2913 2914 if (freeitd == NULL) { 2915 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2916 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2917 EHCI_PAGE_SIZE, &dma); 2918 2919 if (err) { 2920 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2921 mutex_exit(&sc->sc_lock); 2922 return NULL; 2923 } 2924 2925 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2926 offs = i * EHCI_ITD_SIZE; 2927 itd = KERNADDR(&dma, offs); 2928 itd->physaddr = DMAADDR(&dma, offs); 2929 itd->dma = dma; 2930 itd->offs = offs; 2931 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2932 } 2933 freeitd = LIST_FIRST(&sc->sc_freeitds); 2934 } 2935 2936 itd = freeitd; 2937 LIST_REMOVE(itd, u.free_list); 2938 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2939 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2940 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2941 BUS_DMASYNC_PREREAD); 2942 2943 itd->u.frame_list.next = NULL; 2944 itd->u.frame_list.prev = NULL; 2945 itd->xfer_next = NULL; 2946 itd->slot = 0; 2947 2948 mutex_exit(&sc->sc_lock); 2949 2950 return itd; 2951 } 2952 2953 Static void 2954 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2955 { 2956 2957 KASSERT(mutex_owned(&sc->sc_lock)); 2958 2959 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2960 } 2961 2962 /****************/ 2963 2964 /* 2965 * Close a reqular pipe. 2966 * Assumes that there are no pending transactions. 2967 */ 2968 Static void 2969 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2970 { 2971 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2972 ehci_softc_t *sc = pipe->device->bus->hci_private; 2973 ehci_soft_qh_t *sqh = epipe->sqh; 2974 2975 KASSERT(mutex_owned(&sc->sc_lock)); 2976 2977 ehci_rem_qh(sc, sqh, head); 2978 ehci_free_sqh(sc, epipe->sqh); 2979 } 2980 2981 /* 2982 * Abort a device request. 2983 * If this routine is called at splusb() it guarantees that the request 2984 * will be removed from the hardware scheduling and that the callback 2985 * for it will be called with USBD_CANCELLED status. 2986 * It's impossible to guarantee that the requested transfer will not 2987 * have happened since the hardware runs concurrently. 2988 * If the transaction has already happened we rely on the ordinary 2989 * interrupt processing to process it. 2990 * XXX This is most probably wrong. 2991 * XXXMRG this doesn't make sense anymore. 2992 */ 2993 Static void 2994 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2995 { 2996 #define exfer EXFER(xfer) 2997 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2998 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2999 ehci_soft_qh_t *sqh = epipe->sqh; 3000 ehci_soft_qtd_t *sqtd; 3001 ehci_physaddr_t cur; 3002 u_int32_t qhstatus; 3003 int hit; 3004 int wake; 3005 3006 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 3007 3008 KASSERT(mutex_owned(&sc->sc_lock)); 3009 3010 if (sc->sc_dying) { 3011 /* If we're dying, just do the software part. */ 3012 xfer->status = status; /* make software ignore it */ 3013 callout_stop(&xfer->timeout_handle); 3014 usb_transfer_complete(xfer); 3015 return; 3016 } 3017 3018 if (cpu_intr_p() || cpu_softintr_p()) 3019 panic("ehci_abort_xfer: not in process context"); 3020 3021 /* 3022 * If an abort is already in progress then just wait for it to 3023 * complete and return. 3024 */ 3025 if (xfer->hcflags & UXFER_ABORTING) { 3026 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3027 #ifdef DIAGNOSTIC 3028 if (status == USBD_TIMEOUT) 3029 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3030 #endif 3031 /* Override the status which might be USBD_TIMEOUT. */ 3032 xfer->status = status; 3033 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3034 xfer->hcflags |= UXFER_ABORTWAIT; 3035 while (xfer->hcflags & UXFER_ABORTING) 3036 cv_wait(&xfer->hccv, &sc->sc_lock); 3037 return; 3038 } 3039 xfer->hcflags |= UXFER_ABORTING; 3040 3041 /* 3042 * Step 1: Make interrupt routine and hardware ignore xfer. 3043 */ 3044 xfer->status = status; /* make software ignore it */ 3045 callout_stop(&xfer->timeout_handle); 3046 3047 usb_syncmem(&sqh->dma, 3048 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3049 sizeof(sqh->qh.qh_qtd.qtd_status), 3050 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3051 qhstatus = sqh->qh.qh_qtd.qtd_status; 3052 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3053 usb_syncmem(&sqh->dma, 3054 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3055 sizeof(sqh->qh.qh_qtd.qtd_status), 3056 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3057 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3058 usb_syncmem(&sqtd->dma, 3059 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3060 sizeof(sqtd->qtd.qtd_status), 3061 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3062 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3063 usb_syncmem(&sqtd->dma, 3064 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3065 sizeof(sqtd->qtd.qtd_status), 3066 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3067 if (sqtd == exfer->sqtdend) 3068 break; 3069 } 3070 3071 /* 3072 * Step 2: Wait until we know hardware has finished any possible 3073 * use of the xfer. Also make sure the soft interrupt routine 3074 * has run. 3075 */ 3076 ehci_sync_hc(sc); 3077 sc->sc_softwake = 1; 3078 usb_schedsoftintr(&sc->sc_bus); 3079 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3080 3081 /* 3082 * Step 3: Remove any vestiges of the xfer from the hardware. 3083 * The complication here is that the hardware may have executed 3084 * beyond the xfer we're trying to abort. So as we're scanning 3085 * the TDs of this xfer we check if the hardware points to 3086 * any of them. 3087 */ 3088 3089 usb_syncmem(&sqh->dma, 3090 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3091 sizeof(sqh->qh.qh_curqtd), 3092 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3093 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3094 hit = 0; 3095 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3096 hit |= cur == sqtd->physaddr; 3097 if (sqtd == exfer->sqtdend) 3098 break; 3099 } 3100 sqtd = sqtd->nextqtd; 3101 /* Zap curqtd register if hardware pointed inside the xfer. */ 3102 if (hit && sqtd != NULL) { 3103 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3104 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3105 usb_syncmem(&sqh->dma, 3106 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3107 sizeof(sqh->qh.qh_curqtd), 3108 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3109 sqh->qh.qh_qtd.qtd_status = qhstatus; 3110 usb_syncmem(&sqh->dma, 3111 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3112 sizeof(sqh->qh.qh_qtd.qtd_status), 3113 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3114 } else { 3115 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3116 } 3117 3118 /* 3119 * Step 4: Execute callback. 3120 */ 3121 #ifdef DIAGNOSTIC 3122 exfer->isdone = 1; 3123 #endif 3124 wake = xfer->hcflags & UXFER_ABORTWAIT; 3125 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3126 usb_transfer_complete(xfer); 3127 if (wake) { 3128 cv_broadcast(&xfer->hccv); 3129 } 3130 3131 KASSERT(mutex_owned(&sc->sc_lock)); 3132 #undef exfer 3133 } 3134 3135 Static void 3136 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3137 { 3138 ehci_isoc_trans_t trans_status; 3139 struct ehci_pipe *epipe; 3140 struct ehci_xfer *exfer; 3141 ehci_softc_t *sc; 3142 struct ehci_soft_itd *itd; 3143 int i, wake; 3144 3145 epipe = (struct ehci_pipe *) xfer->pipe; 3146 exfer = EXFER(xfer); 3147 sc = epipe->pipe.device->bus->hci_private; 3148 3149 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3150 3151 KASSERT(mutex_owned(&sc->sc_lock)); 3152 3153 if (sc->sc_dying) { 3154 xfer->status = status; 3155 callout_stop(&xfer->timeout_handle); 3156 usb_transfer_complete(xfer); 3157 return; 3158 } 3159 3160 if (xfer->hcflags & UXFER_ABORTING) { 3161 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3162 3163 #ifdef DIAGNOSTIC 3164 if (status == USBD_TIMEOUT) 3165 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3166 #endif 3167 3168 xfer->status = status; 3169 DPRINTFN(2, ("ehci_abort_isoc_xfer: waiting for abort to finish\n")); 3170 xfer->hcflags |= UXFER_ABORTWAIT; 3171 while (xfer->hcflags & UXFER_ABORTING) 3172 cv_wait(&xfer->hccv, &sc->sc_lock); 3173 goto done; 3174 } 3175 xfer->hcflags |= UXFER_ABORTING; 3176 3177 xfer->status = status; 3178 callout_stop(&xfer->timeout_handle); 3179 3180 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3181 usb_syncmem(&itd->dma, 3182 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3183 sizeof(itd->itd.itd_ctl), 3184 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3185 3186 for (i = 0; i < 8; i++) { 3187 trans_status = le32toh(itd->itd.itd_ctl[i]); 3188 trans_status &= ~EHCI_ITD_ACTIVE; 3189 itd->itd.itd_ctl[i] = htole32(trans_status); 3190 } 3191 3192 usb_syncmem(&itd->dma, 3193 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3194 sizeof(itd->itd.itd_ctl), 3195 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3196 } 3197 3198 sc->sc_softwake = 1; 3199 usb_schedsoftintr(&sc->sc_bus); 3200 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3201 3202 #ifdef DIAGNOSTIC 3203 exfer->isdone = 1; 3204 #endif 3205 wake = xfer->hcflags & UXFER_ABORTWAIT; 3206 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3207 usb_transfer_complete(xfer); 3208 if (wake) { 3209 cv_broadcast(&xfer->hccv); 3210 } 3211 3212 done: 3213 KASSERT(mutex_owned(&sc->sc_lock)); 3214 return; 3215 } 3216 3217 Static void 3218 ehci_timeout(void *addr) 3219 { 3220 struct ehci_xfer *exfer = addr; 3221 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3222 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3223 3224 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3225 #ifdef EHCI_DEBUG 3226 if (ehcidebug > 1) 3227 usbd_dump_pipe(exfer->xfer.pipe); 3228 #endif 3229 3230 if (sc->sc_dying) { 3231 mutex_enter(&sc->sc_lock); 3232 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3233 mutex_exit(&sc->sc_lock); 3234 return; 3235 } 3236 3237 /* Execute the abort in a process context. */ 3238 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3239 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3240 USB_TASKQ_HC); 3241 } 3242 3243 Static void 3244 ehci_timeout_task(void *addr) 3245 { 3246 usbd_xfer_handle xfer = addr; 3247 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3248 3249 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3250 3251 mutex_enter(&sc->sc_lock); 3252 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3253 mutex_exit(&sc->sc_lock); 3254 } 3255 3256 /************************/ 3257 3258 Static usbd_status 3259 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3260 { 3261 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3262 usbd_status err; 3263 3264 /* Insert last in queue. */ 3265 mutex_enter(&sc->sc_lock); 3266 err = usb_insert_transfer(xfer); 3267 mutex_exit(&sc->sc_lock); 3268 if (err) 3269 return (err); 3270 3271 /* Pipe isn't running, start first */ 3272 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3273 } 3274 3275 Static usbd_status 3276 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3277 { 3278 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3279 usbd_status err; 3280 3281 if (sc->sc_dying) 3282 return (USBD_IOERROR); 3283 3284 #ifdef DIAGNOSTIC 3285 if (!(xfer->rqflags & URQ_REQUEST)) { 3286 /* XXX panic */ 3287 printf("ehci_device_ctrl_transfer: not a request\n"); 3288 return (USBD_INVAL); 3289 } 3290 #endif 3291 3292 err = ehci_device_request(xfer); 3293 if (err) { 3294 return (err); 3295 } 3296 3297 if (sc->sc_bus.use_polling) 3298 ehci_waitintr(sc, xfer); 3299 3300 return (USBD_IN_PROGRESS); 3301 } 3302 3303 Static void 3304 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3305 { 3306 struct ehci_xfer *ex = EXFER(xfer); 3307 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3308 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3309 usb_device_request_t *req = &xfer->request; 3310 int len = UGETW(req->wLength); 3311 int rd = req->bmRequestType & UT_READ; 3312 3313 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3314 3315 KASSERT(mutex_owned(&sc->sc_lock)); 3316 3317 #ifdef DIAGNOSTIC 3318 if (!(xfer->rqflags & URQ_REQUEST)) { 3319 panic("ehci_ctrl_done: not a request"); 3320 } 3321 #endif 3322 3323 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3324 ehci_del_intr_list(sc, ex); /* remove from active list */ 3325 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3326 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3327 BUS_DMASYNC_POSTWRITE); 3328 if (len) 3329 usb_syncmem(&xfer->dmabuf, 0, len, 3330 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3331 } 3332 3333 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3334 } 3335 3336 /* Abort a device control request. */ 3337 Static void 3338 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3339 { 3340 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3341 ehci_abort_xfer(xfer, USBD_CANCELLED); 3342 } 3343 3344 /* Close a device control pipe. */ 3345 Static void 3346 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3347 { 3348 ehci_softc_t *sc = pipe->device->bus->hci_private; 3349 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3350 3351 KASSERT(mutex_owned(&sc->sc_lock)); 3352 3353 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3354 3355 ehci_close_pipe(pipe, sc->sc_async_head); 3356 } 3357 3358 Static usbd_status 3359 ehci_device_request(usbd_xfer_handle xfer) 3360 { 3361 #define exfer EXFER(xfer) 3362 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3363 usb_device_request_t *req = &xfer->request; 3364 usbd_device_handle dev = epipe->pipe.device; 3365 ehci_softc_t *sc = dev->bus->hci_private; 3366 int addr = dev->address; 3367 ehci_soft_qtd_t *setup, *stat, *next; 3368 ehci_soft_qh_t *sqh; 3369 int isread; 3370 int len; 3371 usbd_status err; 3372 3373 isread = req->bmRequestType & UT_READ; 3374 len = UGETW(req->wLength); 3375 3376 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3377 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3378 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3379 UGETW(req->wIndex), len, addr, 3380 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3381 3382 setup = ehci_alloc_sqtd(sc); 3383 if (setup == NULL) { 3384 err = USBD_NOMEM; 3385 goto bad1; 3386 } 3387 stat = ehci_alloc_sqtd(sc); 3388 if (stat == NULL) { 3389 err = USBD_NOMEM; 3390 goto bad2; 3391 } 3392 3393 mutex_enter(&sc->sc_lock); 3394 3395 sqh = epipe->sqh; 3396 epipe->u.ctl.length = len; 3397 3398 /* Update device address and length since they may have changed 3399 during the setup of the control pipe in usbd_new_device(). */ 3400 /* XXX This only needs to be done once, but it's too early in open. */ 3401 /* XXXX Should not touch ED here! */ 3402 sqh->qh.qh_endp = 3403 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3404 htole32( 3405 EHCI_QH_SET_ADDR(addr) | 3406 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3407 ); 3408 3409 /* Set up data transaction */ 3410 if (len != 0) { 3411 ehci_soft_qtd_t *end; 3412 3413 /* Start toggle at 1. */ 3414 epipe->nexttoggle = 1; 3415 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3416 &next, &end); 3417 if (err) 3418 goto bad3; 3419 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3420 end->nextqtd = stat; 3421 end->qtd.qtd_next = 3422 end->qtd.qtd_altnext = htole32(stat->physaddr); 3423 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3424 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3425 } else { 3426 next = stat; 3427 } 3428 3429 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3430 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3431 3432 /* Clear toggle */ 3433 setup->qtd.qtd_status = htole32( 3434 EHCI_QTD_ACTIVE | 3435 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3436 EHCI_QTD_SET_CERR(3) | 3437 EHCI_QTD_SET_TOGGLE(0) | 3438 EHCI_QTD_SET_BYTES(sizeof *req) 3439 ); 3440 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3441 setup->qtd.qtd_buffer_hi[0] = 0; 3442 setup->nextqtd = next; 3443 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3444 setup->xfer = xfer; 3445 setup->len = sizeof *req; 3446 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3447 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3448 3449 stat->qtd.qtd_status = htole32( 3450 EHCI_QTD_ACTIVE | 3451 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3452 EHCI_QTD_SET_CERR(3) | 3453 EHCI_QTD_SET_TOGGLE(1) | 3454 EHCI_QTD_IOC 3455 ); 3456 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3457 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3458 stat->nextqtd = NULL; 3459 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3460 stat->xfer = xfer; 3461 stat->len = 0; 3462 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3463 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3464 3465 #ifdef EHCI_DEBUG 3466 if (ehcidebug > 5) { 3467 DPRINTF(("ehci_device_request:\n")); 3468 ehci_dump_sqh(sqh); 3469 ehci_dump_sqtds(setup); 3470 } 3471 #endif 3472 3473 exfer->sqtdstart = setup; 3474 exfer->sqtdend = stat; 3475 #ifdef DIAGNOSTIC 3476 if (!exfer->isdone) { 3477 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3478 } 3479 exfer->isdone = 0; 3480 #endif 3481 3482 /* Insert qTD in QH list. */ 3483 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3484 if (xfer->timeout && !sc->sc_bus.use_polling) { 3485 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3486 ehci_timeout, xfer); 3487 } 3488 ehci_add_intr_list(sc, exfer); 3489 xfer->status = USBD_IN_PROGRESS; 3490 mutex_exit(&sc->sc_lock); 3491 3492 #ifdef EHCI_DEBUG 3493 if (ehcidebug > 10) { 3494 DPRINTF(("ehci_device_request: status=%x\n", 3495 EOREAD4(sc, EHCI_USBSTS))); 3496 delay(10000); 3497 ehci_dump_regs(sc); 3498 ehci_dump_sqh(sc->sc_async_head); 3499 ehci_dump_sqh(sqh); 3500 ehci_dump_sqtds(setup); 3501 } 3502 #endif 3503 3504 return (USBD_NORMAL_COMPLETION); 3505 3506 bad3: 3507 mutex_exit(&sc->sc_lock); 3508 ehci_free_sqtd(sc, stat); 3509 bad2: 3510 ehci_free_sqtd(sc, setup); 3511 bad1: 3512 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3513 mutex_enter(&sc->sc_lock); 3514 xfer->status = err; 3515 usb_transfer_complete(xfer); 3516 mutex_exit(&sc->sc_lock); 3517 return (err); 3518 #undef exfer 3519 } 3520 3521 /* 3522 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3523 * qTD status, or miss signalling occasionally under heavy load. If the host 3524 * machine is too fast, we we can miss transaction completion - when we scan 3525 * the active list the transaction still seems to be active. This generally 3526 * exhibits itself as a umass stall that never recovers. 3527 * 3528 * We work around this behaviour by setting up this callback after any softintr 3529 * that completes with transactions still pending, giving us another chance to 3530 * check for completion after the writeback has taken place. 3531 */ 3532 Static void 3533 ehci_intrlist_timeout(void *arg) 3534 { 3535 ehci_softc_t *sc = arg; 3536 3537 DPRINTF(("ehci_intrlist_timeout\n")); 3538 usb_schedsoftintr(&sc->sc_bus); 3539 } 3540 3541 /************************/ 3542 3543 Static usbd_status 3544 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3545 { 3546 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3547 usbd_status err; 3548 3549 /* Insert last in queue. */ 3550 mutex_enter(&sc->sc_lock); 3551 err = usb_insert_transfer(xfer); 3552 mutex_exit(&sc->sc_lock); 3553 if (err) 3554 return (err); 3555 3556 /* Pipe isn't running, start first */ 3557 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3558 } 3559 3560 Static usbd_status 3561 ehci_device_bulk_start(usbd_xfer_handle xfer) 3562 { 3563 #define exfer EXFER(xfer) 3564 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3565 usbd_device_handle dev = epipe->pipe.device; 3566 ehci_softc_t *sc = dev->bus->hci_private; 3567 ehci_soft_qtd_t *data, *dataend; 3568 ehci_soft_qh_t *sqh; 3569 usbd_status err; 3570 int len, isread, endpt; 3571 3572 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3573 xfer, xfer->length, xfer->flags)); 3574 3575 if (sc->sc_dying) 3576 return (USBD_IOERROR); 3577 3578 #ifdef DIAGNOSTIC 3579 if (xfer->rqflags & URQ_REQUEST) 3580 panic("ehci_device_bulk_start: a request"); 3581 #endif 3582 3583 mutex_enter(&sc->sc_lock); 3584 3585 len = xfer->length; 3586 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3587 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3588 sqh = epipe->sqh; 3589 3590 epipe->u.bulk.length = len; 3591 3592 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3593 &dataend); 3594 if (err) { 3595 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3596 xfer->status = err; 3597 usb_transfer_complete(xfer); 3598 mutex_exit(&sc->sc_lock); 3599 return (err); 3600 } 3601 3602 #ifdef EHCI_DEBUG 3603 if (ehcidebug > 5) { 3604 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3605 ehci_dump_sqh(sqh); 3606 ehci_dump_sqtds(data); 3607 } 3608 #endif 3609 3610 /* Set up interrupt info. */ 3611 exfer->sqtdstart = data; 3612 exfer->sqtdend = dataend; 3613 #ifdef DIAGNOSTIC 3614 if (!exfer->isdone) { 3615 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3616 } 3617 exfer->isdone = 0; 3618 #endif 3619 3620 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3621 if (xfer->timeout && !sc->sc_bus.use_polling) { 3622 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3623 ehci_timeout, xfer); 3624 } 3625 ehci_add_intr_list(sc, exfer); 3626 xfer->status = USBD_IN_PROGRESS; 3627 mutex_exit(&sc->sc_lock); 3628 3629 #ifdef EHCI_DEBUG 3630 if (ehcidebug > 10) { 3631 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3632 delay(10000); 3633 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3634 ehci_dump_regs(sc); 3635 #if 0 3636 printf("async_head:\n"); 3637 ehci_dump_sqh(sc->sc_async_head); 3638 #endif 3639 printf("sqh:\n"); 3640 ehci_dump_sqh(sqh); 3641 ehci_dump_sqtds(data); 3642 } 3643 #endif 3644 3645 if (sc->sc_bus.use_polling) 3646 ehci_waitintr(sc, xfer); 3647 3648 return (USBD_IN_PROGRESS); 3649 #undef exfer 3650 } 3651 3652 Static void 3653 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3654 { 3655 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3656 ehci_abort_xfer(xfer, USBD_CANCELLED); 3657 } 3658 3659 /* 3660 * Close a device bulk pipe. 3661 */ 3662 Static void 3663 ehci_device_bulk_close(usbd_pipe_handle pipe) 3664 { 3665 ehci_softc_t *sc = pipe->device->bus->hci_private; 3666 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3667 3668 KASSERT(mutex_owned(&sc->sc_lock)); 3669 3670 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3671 pipe->endpoint->datatoggle = epipe->nexttoggle; 3672 ehci_close_pipe(pipe, sc->sc_async_head); 3673 } 3674 3675 Static void 3676 ehci_device_bulk_done(usbd_xfer_handle xfer) 3677 { 3678 struct ehci_xfer *ex = EXFER(xfer); 3679 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3680 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3681 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3682 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3683 3684 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3685 xfer, xfer->actlen)); 3686 3687 KASSERT(mutex_owned(&sc->sc_lock)); 3688 3689 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3690 ehci_del_intr_list(sc, ex); /* remove from active list */ 3691 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3692 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3693 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3694 } 3695 3696 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3697 } 3698 3699 /************************/ 3700 3701 Static usbd_status 3702 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3703 { 3704 struct ehci_soft_islot *isp; 3705 int islot, lev; 3706 3707 /* Find a poll rate that is large enough. */ 3708 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3709 if (EHCI_ILEV_IVAL(lev) <= ival) 3710 break; 3711 3712 /* Pick an interrupt slot at the right level. */ 3713 /* XXX could do better than picking at random */ 3714 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3715 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3716 3717 sqh->islot = islot; 3718 isp = &sc->sc_islots[islot]; 3719 mutex_enter(&sc->sc_lock); 3720 ehci_add_qh(sc, sqh, isp->sqh); 3721 mutex_exit(&sc->sc_lock); 3722 3723 return (USBD_NORMAL_COMPLETION); 3724 } 3725 3726 Static usbd_status 3727 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3728 { 3729 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3730 usbd_status err; 3731 3732 /* Insert last in queue. */ 3733 mutex_enter(&sc->sc_lock); 3734 err = usb_insert_transfer(xfer); 3735 mutex_exit(&sc->sc_lock); 3736 if (err) 3737 return (err); 3738 3739 /* 3740 * Pipe isn't running (otherwise err would be USBD_INPROG), 3741 * so start it first. 3742 */ 3743 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3744 } 3745 3746 Static usbd_status 3747 ehci_device_intr_start(usbd_xfer_handle xfer) 3748 { 3749 #define exfer EXFER(xfer) 3750 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3751 usbd_device_handle dev = xfer->pipe->device; 3752 ehci_softc_t *sc = dev->bus->hci_private; 3753 ehci_soft_qtd_t *data, *dataend; 3754 ehci_soft_qh_t *sqh; 3755 usbd_status err; 3756 int len, isread, endpt; 3757 3758 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3759 xfer, xfer->length, xfer->flags)); 3760 3761 if (sc->sc_dying) 3762 return (USBD_IOERROR); 3763 3764 #ifdef DIAGNOSTIC 3765 if (xfer->rqflags & URQ_REQUEST) 3766 panic("ehci_device_intr_start: a request"); 3767 #endif 3768 3769 mutex_enter(&sc->sc_lock); 3770 3771 len = xfer->length; 3772 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3773 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3774 sqh = epipe->sqh; 3775 3776 epipe->u.intr.length = len; 3777 3778 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3779 &dataend); 3780 if (err) { 3781 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3782 xfer->status = err; 3783 usb_transfer_complete(xfer); 3784 mutex_exit(&sc->sc_lock); 3785 return (err); 3786 } 3787 3788 #ifdef EHCI_DEBUG 3789 if (ehcidebug > 5) { 3790 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3791 ehci_dump_sqh(sqh); 3792 ehci_dump_sqtds(data); 3793 } 3794 #endif 3795 3796 /* Set up interrupt info. */ 3797 exfer->sqtdstart = data; 3798 exfer->sqtdend = dataend; 3799 #ifdef DIAGNOSTIC 3800 if (!exfer->isdone) { 3801 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3802 } 3803 exfer->isdone = 0; 3804 #endif 3805 3806 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3807 if (xfer->timeout && !sc->sc_bus.use_polling) { 3808 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3809 ehci_timeout, xfer); 3810 } 3811 ehci_add_intr_list(sc, exfer); 3812 xfer->status = USBD_IN_PROGRESS; 3813 mutex_exit(&sc->sc_lock); 3814 3815 #ifdef EHCI_DEBUG 3816 if (ehcidebug > 10) { 3817 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3818 delay(10000); 3819 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3820 ehci_dump_regs(sc); 3821 printf("sqh:\n"); 3822 ehci_dump_sqh(sqh); 3823 ehci_dump_sqtds(data); 3824 } 3825 #endif 3826 3827 if (sc->sc_bus.use_polling) 3828 ehci_waitintr(sc, xfer); 3829 3830 return (USBD_IN_PROGRESS); 3831 #undef exfer 3832 } 3833 3834 Static void 3835 ehci_device_intr_abort(usbd_xfer_handle xfer) 3836 { 3837 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3838 if (xfer->pipe->intrxfer == xfer) { 3839 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3840 xfer->pipe->intrxfer = NULL; 3841 } 3842 /* 3843 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3844 * async doorbell. That's dependent on the async list, wheras 3845 * intr xfers are periodic, should not use this? 3846 */ 3847 ehci_abort_xfer(xfer, USBD_CANCELLED); 3848 } 3849 3850 Static void 3851 ehci_device_intr_close(usbd_pipe_handle pipe) 3852 { 3853 ehci_softc_t *sc = pipe->device->bus->hci_private; 3854 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3855 struct ehci_soft_islot *isp; 3856 3857 KASSERT(mutex_owned(&sc->sc_lock)); 3858 3859 isp = &sc->sc_islots[epipe->sqh->islot]; 3860 ehci_close_pipe(pipe, isp->sqh); 3861 } 3862 3863 Static void 3864 ehci_device_intr_done(usbd_xfer_handle xfer) 3865 { 3866 #define exfer EXFER(xfer) 3867 struct ehci_xfer *ex = EXFER(xfer); 3868 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3869 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3870 ehci_soft_qtd_t *data, *dataend; 3871 ehci_soft_qh_t *sqh; 3872 usbd_status err; 3873 int len, isread, endpt; 3874 3875 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3876 xfer, xfer->actlen)); 3877 3878 KASSERT(mutex_owned(&sc->sc_lock)); 3879 3880 if (xfer->pipe->repeat) { 3881 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3882 3883 len = epipe->u.intr.length; 3884 xfer->length = len; 3885 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3886 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3887 usb_syncmem(&xfer->dmabuf, 0, len, 3888 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3889 sqh = epipe->sqh; 3890 3891 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3892 &data, &dataend); 3893 if (err) { 3894 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3895 xfer->status = err; 3896 return; 3897 } 3898 3899 /* Set up interrupt info. */ 3900 exfer->sqtdstart = data; 3901 exfer->sqtdend = dataend; 3902 #ifdef DIAGNOSTIC 3903 if (!exfer->isdone) { 3904 printf("ehci_device_intr_done: not done, ex=%p\n", 3905 exfer); 3906 } 3907 exfer->isdone = 0; 3908 #endif 3909 3910 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3911 if (xfer->timeout && !sc->sc_bus.use_polling) { 3912 callout_reset(&xfer->timeout_handle, 3913 mstohz(xfer->timeout), ehci_timeout, xfer); 3914 } 3915 3916 xfer->status = USBD_IN_PROGRESS; 3917 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3918 ehci_del_intr_list(sc, ex); /* remove from active list */ 3919 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3920 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3921 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3922 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3923 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3924 } 3925 #undef exfer 3926 } 3927 3928 /************************/ 3929 3930 Static usbd_status 3931 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3932 { 3933 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3934 usbd_status err; 3935 3936 mutex_enter(&sc->sc_lock); 3937 err = usb_insert_transfer(xfer); 3938 mutex_exit(&sc->sc_lock); 3939 if (err && err != USBD_IN_PROGRESS) 3940 return err; 3941 3942 return ehci_device_isoc_start(xfer); 3943 } 3944 3945 Static usbd_status 3946 ehci_device_isoc_start(usbd_xfer_handle xfer) 3947 { 3948 struct ehci_pipe *epipe; 3949 usbd_device_handle dev; 3950 ehci_softc_t *sc; 3951 struct ehci_xfer *exfer; 3952 ehci_soft_itd_t *itd, *prev, *start, *stop; 3953 usb_dma_t *dma_buf; 3954 int i, j, k, frames, uframes, ufrperframe; 3955 int trans_count, offs, total_length; 3956 int frindex; 3957 3958 start = NULL; 3959 prev = NULL; 3960 itd = NULL; 3961 trans_count = 0; 3962 total_length = 0; 3963 exfer = (struct ehci_xfer *) xfer; 3964 sc = xfer->pipe->device->bus->hci_private; 3965 dev = xfer->pipe->device; 3966 epipe = (struct ehci_pipe *)xfer->pipe; 3967 3968 /* 3969 * To allow continuous transfers, above we start all transfers 3970 * immediately. However, we're still going to get usbd_start_next call 3971 * this when another xfer completes. So, check if this is already 3972 * in progress or not 3973 */ 3974 3975 if (exfer->itdstart != NULL) 3976 return USBD_IN_PROGRESS; 3977 3978 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3979 xfer, xfer->length, xfer->flags)); 3980 3981 if (sc->sc_dying) 3982 return USBD_IOERROR; 3983 3984 /* 3985 * To avoid complication, don't allow a request right now that'll span 3986 * the entire frame table. To within 4 frames, to allow some leeway 3987 * on either side of where the hc currently is. 3988 */ 3989 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3990 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3991 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3992 return USBD_INVAL; 3993 } 3994 3995 #ifdef DIAGNOSTIC 3996 if (xfer->rqflags & URQ_REQUEST) 3997 panic("ehci_device_isoc_start: request\n"); 3998 3999 if (!exfer->isdone) 4000 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 4001 exfer->isdone = 0; 4002 #endif 4003 4004 /* 4005 * Step 1: Allocate and initialize itds, how many do we need? 4006 * One per transfer if interval >= 8 microframes, fewer if we use 4007 * multiple microframes per frame. 4008 */ 4009 4010 i = epipe->pipe.endpoint->edesc->bInterval; 4011 if (i > 16 || i == 0) { 4012 /* Spec page 271 says intervals > 16 are invalid */ 4013 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 4014 return USBD_INVAL; 4015 } 4016 4017 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4018 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4019 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4020 4021 if (frames == 0) { 4022 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 4023 return USBD_INVAL; 4024 } 4025 4026 dma_buf = &xfer->dmabuf; 4027 offs = 0; 4028 4029 for (i = 0; i < frames; i++) { 4030 int froffs = offs; 4031 itd = ehci_alloc_itd(sc); 4032 4033 if (prev != NULL) { 4034 prev->itd.itd_next = 4035 htole32(itd->physaddr | EHCI_LINK_ITD); 4036 usb_syncmem(&itd->dma, 4037 itd->offs + offsetof(ehci_itd_t, itd_next), 4038 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4039 4040 prev->xfer_next = itd; 4041 } else { 4042 start = itd; 4043 } 4044 4045 /* 4046 * Step 1.5, initialize uframes 4047 */ 4048 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4049 /* Calculate which page in the list this starts in */ 4050 int addr = DMAADDR(dma_buf, froffs); 4051 addr = EHCI_PAGE_OFFSET(addr); 4052 addr += (offs - froffs); 4053 addr = EHCI_PAGE(addr); 4054 addr /= EHCI_PAGE_SIZE; 4055 4056 /* This gets the initial offset into the first page, 4057 * looks how far further along the current uframe 4058 * offset is. Works out how many pages that is. 4059 */ 4060 4061 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4062 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4063 EHCI_ITD_SET_PG(addr) | 4064 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4065 4066 total_length += xfer->frlengths[trans_count]; 4067 offs += xfer->frlengths[trans_count]; 4068 trans_count++; 4069 4070 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4071 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4072 break; 4073 } 4074 } 4075 4076 /* Step 1.75, set buffer pointers. To simplify matters, all 4077 * pointers are filled out for the next 7 hardware pages in 4078 * the dma block, so no need to worry what pages to cover 4079 * and what to not. 4080 */ 4081 4082 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4083 /* 4084 * Don't try to lookup a page that's past the end 4085 * of buffer 4086 */ 4087 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4088 if (page_offs >= dma_buf->block->size) 4089 break; 4090 4091 unsigned long long page = DMAADDR(dma_buf, page_offs); 4092 page = EHCI_PAGE(page); 4093 itd->itd.itd_bufr[j] = 4094 htole32(EHCI_ITD_SET_BPTR(page)); 4095 itd->itd.itd_bufr_hi[j] = 4096 htole32(page >> 32); 4097 } 4098 4099 /* 4100 * Other special values 4101 */ 4102 4103 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4104 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4105 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4106 4107 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4108 ? 1 : 0; 4109 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4110 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4111 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4112 4113 /* FIXME: handle invalid trans */ 4114 itd->itd.itd_bufr[2] |= 4115 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4116 4117 usb_syncmem(&itd->dma, 4118 itd->offs + offsetof(ehci_itd_t, itd_next), 4119 sizeof(ehci_itd_t), 4120 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4121 4122 prev = itd; 4123 } /* End of frame */ 4124 4125 stop = itd; 4126 stop->xfer_next = NULL; 4127 exfer->isoc_len = total_length; 4128 4129 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4130 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4131 4132 /* 4133 * Part 2: Transfer descriptors have now been set up, now they must 4134 * be scheduled into the period frame list. Erk. Not wanting to 4135 * complicate matters, transfer is denied if the transfer spans 4136 * more than the period frame list. 4137 */ 4138 4139 mutex_enter(&sc->sc_lock); 4140 4141 /* Start inserting frames */ 4142 if (epipe->u.isoc.cur_xfers > 0) { 4143 frindex = epipe->u.isoc.next_frame; 4144 } else { 4145 frindex = EOREAD4(sc, EHCI_FRINDEX); 4146 frindex = frindex >> 3; /* Erase microframe index */ 4147 frindex += 2; 4148 } 4149 4150 if (frindex >= sc->sc_flsize) 4151 frindex &= (sc->sc_flsize - 1); 4152 4153 /* What's the frame interval? */ 4154 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4155 if (i / USB_UFRAMES_PER_FRAME == 0) 4156 i = 1; 4157 else 4158 i /= USB_UFRAMES_PER_FRAME; 4159 4160 itd = start; 4161 for (j = 0; j < frames; j++) { 4162 if (itd == NULL) 4163 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4164 4165 itd->itd.itd_next = sc->sc_flist[frindex]; 4166 if (itd->itd.itd_next == 0) 4167 /* FIXME: frindex table gets initialized to NULL 4168 * or EHCI_NULL? */ 4169 itd->itd.itd_next = EHCI_NULL; 4170 4171 usb_syncmem(&itd->dma, 4172 itd->offs + offsetof(ehci_itd_t, itd_next), 4173 sizeof(itd->itd.itd_next), 4174 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4175 4176 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4177 4178 usb_syncmem(&sc->sc_fldma, 4179 sizeof(ehci_link_t) * frindex, 4180 sizeof(ehci_link_t), 4181 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4182 4183 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4184 sc->sc_softitds[frindex] = itd; 4185 if (itd->u.frame_list.next != NULL) 4186 itd->u.frame_list.next->u.frame_list.prev = itd; 4187 itd->slot = frindex; 4188 itd->u.frame_list.prev = NULL; 4189 4190 frindex += i; 4191 if (frindex >= sc->sc_flsize) 4192 frindex -= sc->sc_flsize; 4193 4194 itd = itd->xfer_next; 4195 } 4196 4197 epipe->u.isoc.cur_xfers++; 4198 epipe->u.isoc.next_frame = frindex; 4199 4200 exfer->itdstart = start; 4201 exfer->itdend = stop; 4202 exfer->sqtdstart = NULL; 4203 exfer->sqtdstart = NULL; 4204 4205 ehci_add_intr_list(sc, exfer); 4206 xfer->status = USBD_IN_PROGRESS; 4207 xfer->done = 0; 4208 mutex_exit(&sc->sc_lock); 4209 4210 if (sc->sc_bus.use_polling) { 4211 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4212 ehci_waitintr(sc, xfer); 4213 } 4214 4215 return USBD_IN_PROGRESS; 4216 } 4217 4218 Static void 4219 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4220 { 4221 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4222 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4223 } 4224 4225 Static void 4226 ehci_device_isoc_close(usbd_pipe_handle pipe) 4227 { 4228 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4229 } 4230 4231 Static void 4232 ehci_device_isoc_done(usbd_xfer_handle xfer) 4233 { 4234 struct ehci_xfer *exfer; 4235 ehci_softc_t *sc; 4236 struct ehci_pipe *epipe; 4237 4238 exfer = EXFER(xfer); 4239 sc = xfer->pipe->device->bus->hci_private; 4240 epipe = (struct ehci_pipe *) xfer->pipe; 4241 4242 KASSERT(mutex_owned(&sc->sc_lock)); 4243 4244 epipe->u.isoc.cur_xfers--; 4245 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4246 ehci_del_intr_list(sc, exfer); 4247 ehci_rem_free_itd_chain(sc, exfer); 4248 } 4249 4250 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4251 BUS_DMASYNC_POSTREAD); 4252 4253 } 4254
Indexes created Tue Sep 23 14:10:03 GMT 2025