ehci.c revision 1.197
1 /* $NetBSD: ehci.c,v 1.197 2013/01/07 15:07:40 prlw1 Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.197 2013/01/07 15:07:40 prlw1 Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/kernel.h> 64 #include <sys/kmem.h> 65 #include <sys/device.h> 66 #include <sys/select.h> 67 #include <sys/proc.h> 68 #include <sys/queue.h> 69 #include <sys/mutex.h> 70 #include <sys/bus.h> 71 #include <sys/cpu.h> 72 73 #include <machine/endian.h> 74 75 #include <dev/usb/usb.h> 76 #include <dev/usb/usbdi.h> 77 #include <dev/usb/usbdivar.h> 78 #include <dev/usb/usb_mem.h> 79 #include <dev/usb/usb_quirks.h> 80 81 #include <dev/usb/ehcireg.h> 82 #include <dev/usb/ehcivar.h> 83 #include <dev/usb/usbroothub_subr.h> 84 85 #ifdef EHCI_DEBUG 86 #include <sys/kprintf.h> 87 static void 88 ehciprintf(const char *fmt, ...) 89 { 90 va_list ap; 91 92 va_start(ap, fmt); 93 kprintf(fmt, TOLOG|TOCONS, NULL, NULL, ap); 94 va_end(ap); 95 } 96 97 #define DPRINTF(x) do { if (ehcidebug) ehciprintf x; } while(0) 98 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) ehciprintf x; } while (0) 99 int ehcidebug = 0; 100 #else 101 #define DPRINTF(x) 102 #define DPRINTFN(n,x) 103 #endif 104 105 struct ehci_pipe { 106 struct usbd_pipe pipe; 107 int nexttoggle; 108 109 ehci_soft_qh_t *sqh; 110 union { 111 ehci_soft_qtd_t *qtd; 112 /* ehci_soft_itd_t *itd; */ 113 } tail; 114 union { 115 /* Control pipe */ 116 struct { 117 usb_dma_t reqdma; 118 u_int length; 119 } ctl; 120 /* Interrupt pipe */ 121 struct { 122 u_int length; 123 } intr; 124 /* Bulk pipe */ 125 struct { 126 u_int length; 127 } bulk; 128 /* Iso pipe */ 129 struct { 130 u_int next_frame; 131 u_int cur_xfers; 132 } isoc; 133 } u; 134 }; 135 136 Static usbd_status ehci_open(usbd_pipe_handle); 137 Static void ehci_poll(struct usbd_bus *); 138 Static void ehci_softintr(void *); 139 Static int ehci_intr1(ehci_softc_t *); 140 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 141 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 142 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 143 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 144 Static void ehci_idone(struct ehci_xfer *); 145 Static void ehci_timeout(void *); 146 Static void ehci_timeout_task(void *); 147 Static void ehci_intrlist_timeout(void *); 148 Static void ehci_doorbell(void *); 149 Static void ehci_pcd(void *); 150 151 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 152 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 153 154 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 155 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 156 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 157 158 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 159 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 160 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 161 Static void ehci_root_ctrl_close(usbd_pipe_handle); 162 Static void ehci_root_ctrl_done(usbd_xfer_handle); 163 164 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 165 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 166 Static void ehci_root_intr_abort(usbd_xfer_handle); 167 Static void ehci_root_intr_close(usbd_pipe_handle); 168 Static void ehci_root_intr_done(usbd_xfer_handle); 169 170 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 171 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 172 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 173 Static void ehci_device_ctrl_close(usbd_pipe_handle); 174 Static void ehci_device_ctrl_done(usbd_xfer_handle); 175 176 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 177 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 178 Static void ehci_device_bulk_abort(usbd_xfer_handle); 179 Static void ehci_device_bulk_close(usbd_pipe_handle); 180 Static void ehci_device_bulk_done(usbd_xfer_handle); 181 182 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 183 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 184 Static void ehci_device_intr_abort(usbd_xfer_handle); 185 Static void ehci_device_intr_close(usbd_pipe_handle); 186 Static void ehci_device_intr_done(usbd_xfer_handle); 187 188 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 189 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 190 Static void ehci_device_isoc_abort(usbd_xfer_handle); 191 Static void ehci_device_isoc_close(usbd_pipe_handle); 192 Static void ehci_device_isoc_done(usbd_xfer_handle); 193 194 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 195 Static void ehci_noop(usbd_pipe_handle pipe); 196 197 Static void ehci_disown(ehci_softc_t *, int, int); 198 199 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 200 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 201 202 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 203 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 204 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 205 ehci_softc_t *, int, int, usbd_xfer_handle, 206 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 207 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 208 ehci_soft_qtd_t *); 209 210 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 211 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 212 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 213 struct ehci_xfer *exfer); 214 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 215 usbd_status status); 216 217 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 218 219 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 220 int ival); 221 222 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 223 ehci_soft_qh_t *); 224 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 225 ehci_soft_qh_t *); 226 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 227 Static void ehci_sync_hc(ehci_softc_t *); 228 229 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 230 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 231 232 #ifdef EHCI_DEBUG 233 Static void ehci_dump_regs(ehci_softc_t *); 234 void ehci_dump(void); 235 Static ehci_softc_t *theehci; 236 Static void ehci_dump_link(ehci_link_t, int); 237 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 238 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 239 Static void ehci_dump_qtd(ehci_qtd_t *); 240 Static void ehci_dump_sqh(ehci_soft_qh_t *); 241 #if notyet 242 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 243 Static void ehci_dump_itd(struct ehci_soft_itd *); 244 #endif 245 #ifdef DIAGNOSTIC 246 Static void ehci_dump_exfer(struct ehci_xfer *); 247 #endif 248 #endif 249 250 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 251 252 #define EHCI_INTR_ENDPT 1 253 254 #define ehci_add_intr_list(sc, ex) \ 255 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 256 #define ehci_del_intr_list(sc, ex) \ 257 do { \ 258 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 259 (ex)->inext.tqe_prev = NULL; \ 260 } while (0) 261 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 262 263 Static const struct usbd_bus_methods ehci_bus_methods = { 264 .open_pipe = ehci_open, 265 .soft_intr = ehci_softintr, 266 .do_poll = ehci_poll, 267 .allocm = ehci_allocm, 268 .freem = ehci_freem, 269 .allocx = ehci_allocx, 270 .freex = ehci_freex, 271 .get_lock = ehci_get_lock, 272 }; 273 274 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 275 .transfer = ehci_root_ctrl_transfer, 276 .start = ehci_root_ctrl_start, 277 .abort = ehci_root_ctrl_abort, 278 .close = ehci_root_ctrl_close, 279 .cleartoggle = ehci_noop, 280 .done = ehci_root_ctrl_done, 281 }; 282 283 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 284 .transfer = ehci_root_intr_transfer, 285 .start = ehci_root_intr_start, 286 .abort = ehci_root_intr_abort, 287 .close = ehci_root_intr_close, 288 .cleartoggle = ehci_noop, 289 .done = ehci_root_intr_done, 290 }; 291 292 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 293 .transfer = ehci_device_ctrl_transfer, 294 .start = ehci_device_ctrl_start, 295 .abort = ehci_device_ctrl_abort, 296 .close = ehci_device_ctrl_close, 297 .cleartoggle = ehci_noop, 298 .done = ehci_device_ctrl_done, 299 }; 300 301 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 302 .transfer = ehci_device_intr_transfer, 303 .start = ehci_device_intr_start, 304 .abort = ehci_device_intr_abort, 305 .close = ehci_device_intr_close, 306 .cleartoggle = ehci_device_clear_toggle, 307 .done = ehci_device_intr_done, 308 }; 309 310 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 311 .transfer = ehci_device_bulk_transfer, 312 .start = ehci_device_bulk_start, 313 .abort = ehci_device_bulk_abort, 314 .close = ehci_device_bulk_close, 315 .cleartoggle = ehci_device_clear_toggle, 316 .done = ehci_device_bulk_done, 317 }; 318 319 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 320 .transfer = ehci_device_isoc_transfer, 321 .start = ehci_device_isoc_start, 322 .abort = ehci_device_isoc_abort, 323 .close = ehci_device_isoc_close, 324 .cleartoggle = ehci_noop, 325 .done = ehci_device_isoc_done, 326 }; 327 328 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 329 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 330 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 331 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 332 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 333 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 334 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 335 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 336 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 337 }; 338 339 usbd_status 340 ehci_init(ehci_softc_t *sc) 341 { 342 u_int32_t vers, sparams, cparams, hcr; 343 u_int i; 344 usbd_status err; 345 ehci_soft_qh_t *sqh; 346 u_int ncomp; 347 348 DPRINTF(("ehci_init: start\n")); 349 #ifdef EHCI_DEBUG 350 theehci = sc; 351 #endif 352 353 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 354 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 355 cv_init(&sc->sc_softwake_cv, "ehciab"); 356 cv_init(&sc->sc_doorbell, "ehcidi"); 357 358 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 359 ehci_doorbell, sc); 360 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 361 ehci_pcd, sc); 362 363 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 364 365 vers = EREAD2(sc, EHCI_HCIVERSION); 366 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 367 vers >> 8, vers & 0xff); 368 369 sparams = EREAD4(sc, EHCI_HCSPARAMS); 370 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 371 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 372 ncomp = EHCI_HCS_N_CC(sparams); 373 if (ncomp != sc->sc_ncomp) { 374 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 375 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 376 #if NOHCI == 0 || NUHCI == 0 377 aprint_error("%s: ohci or uhci probably not configured\n", 378 device_xname(sc->sc_dev)); 379 #endif 380 if (ncomp < sc->sc_ncomp) 381 sc->sc_ncomp = ncomp; 382 } 383 if (sc->sc_ncomp > 0) { 384 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 385 aprint_normal("%s: companion controller%s, %d port%s each:", 386 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 387 EHCI_HCS_N_PCC(sparams), 388 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 389 for (i = 0; i < sc->sc_ncomp; i++) 390 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 391 aprint_normal("\n"); 392 } 393 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 394 cparams = EREAD4(sc, EHCI_HCCPARAMS); 395 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 396 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 397 398 if (EHCI_HCC_64BIT(cparams)) { 399 /* MUST clear segment register if 64 bit capable. */ 400 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 401 } 402 403 sc->sc_bus.usbrev = USBREV_2_0; 404 405 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 406 USB_MEM_RESERVE); 407 408 /* Reset the controller */ 409 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 410 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 411 usb_delay_ms(&sc->sc_bus, 1); 412 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 413 for (i = 0; i < 100; i++) { 414 usb_delay_ms(&sc->sc_bus, 1); 415 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 416 if (!hcr) 417 break; 418 } 419 if (hcr) { 420 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 421 return (USBD_IOERROR); 422 } 423 if (sc->sc_vendor_init) 424 sc->sc_vendor_init(sc); 425 426 /* 427 * If we are doing embedded transaction translation function, force 428 * the controller to host mode. 429 */ 430 if (sc->sc_flags & EHCIF_ETTF) { 431 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 432 usbmode &= ~EHCI_USBMODE_CM; 433 usbmode |= EHCI_USBMODE_CM_HOST; 434 EWRITE4(sc, EHCI_USBMODE, usbmode); 435 } 436 437 /* XXX need proper intr scheduling */ 438 sc->sc_rand = 96; 439 440 /* frame list size at default, read back what we got and use that */ 441 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 442 case 0: sc->sc_flsize = 1024; break; 443 case 1: sc->sc_flsize = 512; break; 444 case 2: sc->sc_flsize = 256; break; 445 case 3: return (USBD_IOERROR); 446 } 447 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 448 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 449 if (err) 450 return (err); 451 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 452 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 453 454 for (i = 0; i < sc->sc_flsize; i++) { 455 sc->sc_flist[i] = EHCI_NULL; 456 } 457 458 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 459 460 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 461 KM_SLEEP); 462 if (sc->sc_softitds == NULL) 463 return ENOMEM; 464 LIST_INIT(&sc->sc_freeitds); 465 TAILQ_INIT(&sc->sc_intrhead); 466 467 /* Set up the bus struct. */ 468 sc->sc_bus.methods = &ehci_bus_methods; 469 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 470 471 sc->sc_eintrs = EHCI_NORMAL_INTRS; 472 473 /* 474 * Allocate the interrupt dummy QHs. These are arranged to give poll 475 * intervals that are powers of 2 times 1ms. 476 */ 477 for (i = 0; i < EHCI_INTRQHS; i++) { 478 sqh = ehci_alloc_sqh(sc); 479 if (sqh == NULL) { 480 err = USBD_NOMEM; 481 goto bad1; 482 } 483 sc->sc_islots[i].sqh = sqh; 484 } 485 for (i = 0; i < EHCI_INTRQHS; i++) { 486 sqh = sc->sc_islots[i].sqh; 487 if (i == 0) { 488 /* The last (1ms) QH terminates. */ 489 sqh->qh.qh_link = EHCI_NULL; 490 sqh->next = NULL; 491 } else { 492 /* Otherwise the next QH has half the poll interval */ 493 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 494 sqh->qh.qh_link = htole32(sqh->next->physaddr | 495 EHCI_LINK_QH); 496 } 497 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 498 sqh->qh.qh_curqtd = EHCI_NULL; 499 sqh->next = NULL; 500 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 501 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 502 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 503 sqh->sqtd = NULL; 504 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 505 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 506 } 507 /* Point the frame list at the last level (128ms). */ 508 for (i = 0; i < sc->sc_flsize; i++) { 509 int j; 510 511 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 512 revbits[i & (EHCI_MAX_POLLRATE-1)]; 513 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 514 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 515 i)].sqh->physaddr); 516 } 517 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 518 BUS_DMASYNC_PREWRITE); 519 520 /* Allocate dummy QH that starts the async list. */ 521 sqh = ehci_alloc_sqh(sc); 522 if (sqh == NULL) { 523 err = USBD_NOMEM; 524 goto bad1; 525 } 526 /* Fill the QH */ 527 sqh->qh.qh_endp = 528 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 529 sqh->qh.qh_link = 530 htole32(sqh->physaddr | EHCI_LINK_QH); 531 sqh->qh.qh_curqtd = EHCI_NULL; 532 sqh->next = NULL; 533 /* Fill the overlay qTD */ 534 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 535 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 536 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 537 sqh->sqtd = NULL; 538 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 539 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 540 #ifdef EHCI_DEBUG 541 if (ehcidebug) { 542 ehci_dump_sqh(sqh); 543 } 544 #endif 545 546 /* Point to async list */ 547 sc->sc_async_head = sqh; 548 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 549 550 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 551 552 /* Turn on controller */ 553 EOWRITE4(sc, EHCI_USBCMD, 554 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 555 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 556 EHCI_CMD_ASE | 557 EHCI_CMD_PSE | 558 EHCI_CMD_RS); 559 560 /* Take over port ownership */ 561 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 562 563 for (i = 0; i < 100; i++) { 564 usb_delay_ms(&sc->sc_bus, 1); 565 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 566 if (!hcr) 567 break; 568 } 569 if (hcr) { 570 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 571 return (USBD_IOERROR); 572 } 573 574 /* Enable interrupts */ 575 DPRINTFN(1,("ehci_init: enabling\n")); 576 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 577 578 return (USBD_NORMAL_COMPLETION); 579 580 #if 0 581 bad2: 582 ehci_free_sqh(sc, sc->sc_async_head); 583 #endif 584 bad1: 585 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 586 return (err); 587 } 588 589 int 590 ehci_intr(void *v) 591 { 592 ehci_softc_t *sc = v; 593 int ret = 0; 594 595 if (sc == NULL) 596 return 0; 597 598 mutex_spin_enter(&sc->sc_intr_lock); 599 600 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 601 goto done; 602 603 /* If we get an interrupt while polling, then just ignore it. */ 604 if (sc->sc_bus.use_polling) { 605 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 606 607 if (intrs) 608 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 609 #ifdef DIAGNOSTIC 610 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 611 #endif 612 goto done; 613 } 614 615 ret = ehci_intr1(sc); 616 617 done: 618 mutex_spin_exit(&sc->sc_intr_lock); 619 return ret; 620 } 621 622 Static int 623 ehci_intr1(ehci_softc_t *sc) 624 { 625 u_int32_t intrs, eintrs; 626 627 DPRINTFN(20,("ehci_intr1: enter\n")); 628 629 /* In case the interrupt occurs before initialization has completed. */ 630 if (sc == NULL) { 631 #ifdef DIAGNOSTIC 632 printf("ehci_intr1: sc == NULL\n"); 633 #endif 634 return (0); 635 } 636 637 KASSERT(mutex_owned(&sc->sc_intr_lock)); 638 639 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 640 if (!intrs) 641 return (0); 642 643 eintrs = intrs & sc->sc_eintrs; 644 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 645 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 646 (u_int)eintrs)); 647 if (!eintrs) 648 return (0); 649 650 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 651 sc->sc_bus.no_intrs++; 652 if (eintrs & EHCI_STS_IAA) { 653 DPRINTF(("ehci_intr1: door bell\n")); 654 kpreempt_disable(); 655 softint_schedule(sc->sc_doorbell_si); 656 kpreempt_enable(); 657 eintrs &= ~EHCI_STS_IAA; 658 } 659 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 660 DPRINTFN(5,("ehci_intr1: %s %s\n", 661 eintrs & EHCI_STS_INT ? "INT" : "", 662 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 663 usb_schedsoftintr(&sc->sc_bus); 664 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 665 } 666 if (eintrs & EHCI_STS_HSE) { 667 printf("%s: unrecoverable error, controller halted\n", 668 device_xname(sc->sc_dev)); 669 /* XXX what else */ 670 } 671 if (eintrs & EHCI_STS_PCD) { 672 kpreempt_disable(); 673 softint_schedule(sc->sc_pcd_si); 674 kpreempt_enable(); 675 eintrs &= ~EHCI_STS_PCD; 676 } 677 678 if (eintrs != 0) { 679 /* Block unprocessed interrupts. */ 680 sc->sc_eintrs &= ~eintrs; 681 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 682 printf("%s: blocking intrs 0x%x\n", 683 device_xname(sc->sc_dev), eintrs); 684 } 685 686 return (1); 687 } 688 689 Static void 690 ehci_doorbell(void *addr) 691 { 692 ehci_softc_t *sc = addr; 693 694 mutex_enter(&sc->sc_lock); 695 cv_broadcast(&sc->sc_doorbell); 696 mutex_exit(&sc->sc_lock); 697 } 698 699 Static void 700 ehci_pcd(void *addr) 701 { 702 ehci_softc_t *sc = addr; 703 usbd_xfer_handle xfer; 704 usbd_pipe_handle pipe; 705 u_char *p; 706 int i, m; 707 708 mutex_enter(&sc->sc_lock); 709 xfer = sc->sc_intrxfer; 710 711 if (xfer == NULL) { 712 /* Just ignore the change. */ 713 goto done; 714 } 715 716 pipe = xfer->pipe; 717 718 p = KERNADDR(&xfer->dmabuf, 0); 719 m = min(sc->sc_noport, xfer->length * 8 - 1); 720 memset(p, 0, xfer->length); 721 for (i = 1; i <= m; i++) { 722 /* Pick out CHANGE bits from the status reg. */ 723 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 724 p[i/8] |= 1 << (i%8); 725 } 726 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 727 xfer->actlen = xfer->length; 728 xfer->status = USBD_NORMAL_COMPLETION; 729 730 usb_transfer_complete(xfer); 731 732 done: 733 mutex_exit(&sc->sc_lock); 734 } 735 736 Static void 737 ehci_softintr(void *v) 738 { 739 struct usbd_bus *bus = v; 740 ehci_softc_t *sc = bus->hci_private; 741 struct ehci_xfer *ex, *nextex; 742 743 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 744 745 DPRINTFN(10,("%s: ehci_softintr\n", device_xname(sc->sc_dev))); 746 747 /* 748 * The only explanation I can think of for why EHCI is as brain dead 749 * as UHCI interrupt-wise is that Intel was involved in both. 750 * An interrupt just tells us that something is done, we have no 751 * clue what, so we need to scan through all active transfers. :-( 752 */ 753 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 754 nextex = TAILQ_NEXT(ex, inext); 755 ehci_check_intr(sc, ex); 756 } 757 758 /* Schedule a callout to catch any dropped transactions. */ 759 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 760 !TAILQ_EMPTY(&sc->sc_intrhead)) 761 callout_reset(&sc->sc_tmo_intrlist, 762 hz, ehci_intrlist_timeout, sc); 763 764 if (sc->sc_softwake) { 765 sc->sc_softwake = 0; 766 cv_broadcast(&sc->sc_softwake_cv); 767 } 768 } 769 770 /* Check for an interrupt. */ 771 Static void 772 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 773 { 774 int attr; 775 776 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 777 778 KASSERT(mutex_owned(&sc->sc_lock)); 779 780 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 781 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 782 ehci_check_itd_intr(sc, ex); 783 else 784 ehci_check_qh_intr(sc, ex); 785 786 return; 787 } 788 789 Static void 790 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 791 { 792 ehci_soft_qtd_t *sqtd, *lsqtd; 793 __uint32_t status; 794 795 KASSERT(mutex_owned(&sc->sc_lock)); 796 797 if (ex->sqtdstart == NULL) { 798 printf("ehci_check_qh_intr: not valid sqtd\n"); 799 return; 800 } 801 802 lsqtd = ex->sqtdend; 803 #ifdef DIAGNOSTIC 804 if (lsqtd == NULL) { 805 printf("ehci_check_qh_intr: lsqtd==0\n"); 806 return; 807 } 808 #endif 809 /* 810 * If the last TD is still active we need to check whether there 811 * is a an error somewhere in the middle, or whether there was a 812 * short packet (SPD and not ACTIVE). 813 */ 814 usb_syncmem(&lsqtd->dma, 815 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 816 sizeof(lsqtd->qtd.qtd_status), 817 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 818 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 819 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 820 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 821 usb_syncmem(&sqtd->dma, 822 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 823 sizeof(sqtd->qtd.qtd_status), 824 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 825 status = le32toh(sqtd->qtd.qtd_status); 826 usb_syncmem(&sqtd->dma, 827 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 828 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 829 /* If there's an active QTD the xfer isn't done. */ 830 if (status & EHCI_QTD_ACTIVE) 831 break; 832 /* Any kind of error makes the xfer done. */ 833 if (status & EHCI_QTD_HALTED) 834 goto done; 835 /* We want short packets, and it is short: it's done */ 836 if (EHCI_QTD_GET_BYTES(status) != 0) 837 goto done; 838 } 839 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 840 ex, ex->sqtdstart)); 841 usb_syncmem(&lsqtd->dma, 842 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 843 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 844 return; 845 } 846 done: 847 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 848 callout_stop(&ex->xfer.timeout_handle); 849 ehci_idone(ex); 850 } 851 852 Static void 853 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 854 { 855 ehci_soft_itd_t *itd; 856 int i; 857 858 KASSERT(mutex_owned(&sc->sc_lock)); 859 860 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 861 return; 862 863 if (ex->itdstart == NULL) { 864 printf("ehci_check_itd_intr: not valid itd\n"); 865 return; 866 } 867 868 itd = ex->itdend; 869 #ifdef DIAGNOSTIC 870 if (itd == NULL) { 871 printf("ehci_check_itd_intr: itdend == 0\n"); 872 return; 873 } 874 #endif 875 876 /* 877 * check no active transfers in last itd, meaning we're finished 878 */ 879 880 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 881 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 882 BUS_DMASYNC_POSTREAD); 883 884 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 885 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 886 break; 887 } 888 889 if (i == EHCI_ITD_NUFRAMES) { 890 goto done; /* All 8 descriptors inactive, it's done */ 891 } 892 893 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 894 ex->itdstart)); 895 return; 896 done: 897 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 898 callout_stop(&ex->xfer.timeout_handle); 899 ehci_idone(ex); 900 } 901 902 Static void 903 ehci_idone(struct ehci_xfer *ex) 904 { 905 usbd_xfer_handle xfer = &ex->xfer; 906 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 907 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 908 ehci_soft_qtd_t *sqtd, *lsqtd; 909 u_int32_t status = 0, nstatus = 0; 910 int actlen; 911 912 KASSERT(mutex_owned(&sc->sc_lock)); 913 914 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 915 916 #ifdef DIAGNOSTIC 917 { 918 if (ex->isdone) { 919 #ifdef EHCI_DEBUG 920 printf("ehci_idone: ex is done!\n "); 921 ehci_dump_exfer(ex); 922 #else 923 printf("ehci_idone: ex=%p is done!\n", ex); 924 #endif 925 return; 926 } 927 ex->isdone = 1; 928 } 929 #endif 930 if (xfer->status == USBD_CANCELLED || 931 xfer->status == USBD_TIMEOUT) { 932 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 933 return; 934 } 935 936 #ifdef EHCI_DEBUG 937 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 938 if (ehcidebug > 10) 939 ehci_dump_sqtds(ex->sqtdstart); 940 #endif 941 942 /* The transfer is done, compute actual length and status. */ 943 944 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 945 == UE_ISOCHRONOUS) { 946 /* Isoc transfer */ 947 struct ehci_soft_itd *itd; 948 int i, nframes, len, uframes; 949 950 nframes = 0; 951 actlen = 0; 952 953 i = xfer->pipe->endpoint->edesc->bInterval; 954 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 955 956 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 957 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 958 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 959 BUS_DMASYNC_POSTREAD); 960 961 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 962 /* XXX - driver didn't fill in the frame full 963 * of uframes. This leads to scheduling 964 * inefficiencies, but working around 965 * this doubles complexity of tracking 966 * an xfer. 967 */ 968 if (nframes >= xfer->nframes) 969 break; 970 971 status = le32toh(itd->itd.itd_ctl[i]); 972 len = EHCI_ITD_GET_LEN(status); 973 if (EHCI_ITD_GET_STATUS(status) != 0) 974 len = 0; /*No valid data on error*/ 975 976 xfer->frlengths[nframes++] = len; 977 actlen += len; 978 } 979 980 if (nframes >= xfer->nframes) 981 break; 982 } 983 984 xfer->actlen = actlen; 985 xfer->status = USBD_NORMAL_COMPLETION; 986 goto end; 987 } 988 989 /* Continue processing xfers using queue heads */ 990 991 lsqtd = ex->sqtdend; 992 actlen = 0; 993 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 994 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 995 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 996 nstatus = le32toh(sqtd->qtd.qtd_status); 997 if (nstatus & EHCI_QTD_ACTIVE) 998 break; 999 1000 status = nstatus; 1001 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1002 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1003 } 1004 1005 1006 /* 1007 * If there are left over TDs we need to update the toggle. 1008 * The default pipe doesn't need it since control transfers 1009 * start the toggle at 0 every time. 1010 * For a short transfer we need to update the toggle for the missing 1011 * packets within the qTD. 1012 */ 1013 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1014 xfer->pipe->device->default_pipe != xfer->pipe) { 1015 DPRINTFN(2, ("ehci_idone: need toggle update " 1016 "status=%08x nstatus=%08x\n", status, nstatus)); 1017 #if 0 1018 ehci_dump_sqh(epipe->sqh); 1019 ehci_dump_sqtds(ex->sqtdstart); 1020 #endif 1021 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1022 } 1023 1024 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 1025 xfer->length, actlen, status)); 1026 xfer->actlen = actlen; 1027 if (status & EHCI_QTD_HALTED) { 1028 #ifdef EHCI_DEBUG 1029 char sbuf[128]; 1030 1031 snprintb(sbuf, sizeof(sbuf), 1032 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 1033 (u_int32_t)status); 1034 1035 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 1036 "status 0x%s\n", 1037 xfer->pipe->device->address, 1038 xfer->pipe->endpoint->edesc->bEndpointAddress, 1039 sbuf)); 1040 if (ehcidebug > 2) { 1041 ehci_dump_sqh(epipe->sqh); 1042 ehci_dump_sqtds(ex->sqtdstart); 1043 } 1044 #endif 1045 /* low&full speed has an extra error flag */ 1046 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1047 EHCI_QH_SPEED_HIGH) 1048 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1049 else 1050 status &= EHCI_QTD_STATERRS; 1051 if (status == 0) /* no other errors means a stall */ { 1052 xfer->status = USBD_STALLED; 1053 } else { 1054 xfer->status = USBD_IOERROR; /* more info XXX */ 1055 } 1056 /* XXX need to reset TT on missed microframe */ 1057 if (status & EHCI_QTD_MISSEDMICRO) { 1058 printf("%s: missed microframe, TT reset not " 1059 "implemented, hub might be inoperational\n", 1060 device_xname(sc->sc_dev)); 1061 } 1062 } else { 1063 xfer->status = USBD_NORMAL_COMPLETION; 1064 } 1065 1066 end: 1067 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1068 * during this call, before methods->done is called: dma sync required 1069 * beforehand? */ 1070 usb_transfer_complete(xfer); 1071 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1072 } 1073 1074 /* 1075 * Wait here until controller claims to have an interrupt. 1076 * Then call ehci_intr and return. Use timeout to avoid waiting 1077 * too long. 1078 */ 1079 Static void 1080 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1081 { 1082 int timo; 1083 u_int32_t intrs; 1084 1085 xfer->status = USBD_IN_PROGRESS; 1086 for (timo = xfer->timeout; timo >= 0; timo--) { 1087 usb_delay_ms(&sc->sc_bus, 1); 1088 if (sc->sc_dying) 1089 break; 1090 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1091 sc->sc_eintrs; 1092 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1093 #ifdef EHCI_DEBUG 1094 if (ehcidebug > 15) 1095 ehci_dump_regs(sc); 1096 #endif 1097 if (intrs) { 1098 mutex_spin_enter(&sc->sc_intr_lock); 1099 ehci_intr1(sc); 1100 mutex_spin_exit(&sc->sc_intr_lock); 1101 if (xfer->status != USBD_IN_PROGRESS) 1102 return; 1103 } 1104 } 1105 1106 /* Timeout */ 1107 DPRINTF(("ehci_waitintr: timeout\n")); 1108 xfer->status = USBD_TIMEOUT; 1109 mutex_enter(&sc->sc_lock); 1110 usb_transfer_complete(xfer); 1111 mutex_exit(&sc->sc_lock); 1112 /* XXX should free TD */ 1113 } 1114 1115 Static void 1116 ehci_poll(struct usbd_bus *bus) 1117 { 1118 ehci_softc_t *sc = bus->hci_private; 1119 #ifdef EHCI_DEBUG 1120 static int last; 1121 int new; 1122 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1123 if (new != last) { 1124 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1125 last = new; 1126 } 1127 #endif 1128 1129 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1130 mutex_spin_enter(&sc->sc_intr_lock); 1131 ehci_intr1(sc); 1132 mutex_spin_exit(&sc->sc_intr_lock); 1133 } 1134 } 1135 1136 void 1137 ehci_childdet(device_t self, device_t child) 1138 { 1139 struct ehci_softc *sc = device_private(self); 1140 1141 KASSERT(sc->sc_child == child); 1142 sc->sc_child = NULL; 1143 } 1144 1145 int 1146 ehci_detach(struct ehci_softc *sc, int flags) 1147 { 1148 usbd_xfer_handle xfer; 1149 int rv = 0; 1150 1151 if (sc->sc_child != NULL) 1152 rv = config_detach(sc->sc_child, flags); 1153 1154 if (rv != 0) 1155 return (rv); 1156 1157 callout_halt(&sc->sc_tmo_intrlist, NULL); 1158 callout_destroy(&sc->sc_tmo_intrlist); 1159 1160 /* XXX free other data structures XXX */ 1161 if (sc->sc_softitds) 1162 kmem_free(sc->sc_softitds, 1163 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1164 cv_destroy(&sc->sc_doorbell); 1165 cv_destroy(&sc->sc_softwake_cv); 1166 1167 #if 0 1168 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1169 1170 softint_disestablish(sc->sc_doorbell_si); 1171 softint_disestablish(sc->sc_pcd_si); 1172 1173 mutex_destroy(&sc->sc_lock); 1174 mutex_destroy(&sc->sc_intr_lock); 1175 #endif 1176 1177 while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 1178 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1179 kmem_free(xfer, sizeof(struct ehci_xfer)); 1180 } 1181 1182 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1183 1184 return (rv); 1185 } 1186 1187 1188 int 1189 ehci_activate(device_t self, enum devact act) 1190 { 1191 struct ehci_softc *sc = device_private(self); 1192 1193 switch (act) { 1194 case DVACT_DEACTIVATE: 1195 sc->sc_dying = 1; 1196 return 0; 1197 default: 1198 return EOPNOTSUPP; 1199 } 1200 } 1201 1202 /* 1203 * Handle suspend/resume. 1204 * 1205 * We need to switch to polling mode here, because this routine is 1206 * called from an interrupt context. This is all right since we 1207 * are almost suspended anyway. 1208 * 1209 * Note that this power handler isn't to be registered directly; the 1210 * bus glue needs to call out to it. 1211 */ 1212 bool 1213 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1214 { 1215 ehci_softc_t *sc = device_private(dv); 1216 int i; 1217 uint32_t cmd, hcr; 1218 1219 mutex_spin_enter(&sc->sc_intr_lock); 1220 sc->sc_bus.use_polling++; 1221 mutex_spin_exit(&sc->sc_intr_lock); 1222 1223 for (i = 1; i <= sc->sc_noport; i++) { 1224 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1225 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1226 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1227 } 1228 1229 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1230 1231 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1232 EOWRITE4(sc, EHCI_USBCMD, cmd); 1233 1234 for (i = 0; i < 100; i++) { 1235 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1236 if (hcr == 0) 1237 break; 1238 1239 usb_delay_ms(&sc->sc_bus, 1); 1240 } 1241 if (hcr != 0) 1242 printf("%s: reset timeout\n", device_xname(dv)); 1243 1244 cmd &= ~EHCI_CMD_RS; 1245 EOWRITE4(sc, EHCI_USBCMD, cmd); 1246 1247 for (i = 0; i < 100; i++) { 1248 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1249 if (hcr == EHCI_STS_HCH) 1250 break; 1251 1252 usb_delay_ms(&sc->sc_bus, 1); 1253 } 1254 if (hcr != EHCI_STS_HCH) 1255 printf("%s: config timeout\n", device_xname(dv)); 1256 1257 mutex_spin_enter(&sc->sc_intr_lock); 1258 sc->sc_bus.use_polling--; 1259 mutex_spin_exit(&sc->sc_intr_lock); 1260 1261 return true; 1262 } 1263 1264 bool 1265 ehci_resume(device_t dv, const pmf_qual_t *qual) 1266 { 1267 ehci_softc_t *sc = device_private(dv); 1268 int i; 1269 uint32_t cmd, hcr; 1270 1271 /* restore things in case the bios sucks */ 1272 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1273 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1274 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1275 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1276 1277 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1278 1279 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1280 1281 hcr = 0; 1282 for (i = 1; i <= sc->sc_noport; i++) { 1283 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1284 if ((cmd & EHCI_PS_PO) == 0 && 1285 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1286 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1287 hcr = 1; 1288 } 1289 } 1290 1291 if (hcr) { 1292 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1293 1294 for (i = 1; i <= sc->sc_noport; i++) { 1295 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1296 if ((cmd & EHCI_PS_PO) == 0 && 1297 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1298 EOWRITE4(sc, EHCI_PORTSC(i), 1299 cmd & ~EHCI_PS_FPR); 1300 } 1301 } 1302 1303 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1304 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1305 1306 for (i = 0; i < 100; i++) { 1307 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1308 if (hcr != EHCI_STS_HCH) 1309 break; 1310 1311 usb_delay_ms(&sc->sc_bus, 1); 1312 } 1313 if (hcr == EHCI_STS_HCH) 1314 printf("%s: config timeout\n", device_xname(dv)); 1315 1316 return true; 1317 } 1318 1319 /* 1320 * Shut down the controller when the system is going down. 1321 */ 1322 bool 1323 ehci_shutdown(device_t self, int flags) 1324 { 1325 ehci_softc_t *sc = device_private(self); 1326 1327 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1328 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1329 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1330 return true; 1331 } 1332 1333 Static usbd_status 1334 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1335 { 1336 struct ehci_softc *sc = bus->hci_private; 1337 usbd_status err; 1338 1339 err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, USBMALLOC_MULTISEG); 1340 #ifdef EHCI_DEBUG 1341 if (err) 1342 printf("ehci_allocm: usb_allocmem_flags()= %s (%d)\n", 1343 usbd_errstr(err), err); 1344 #endif 1345 if (err == USBD_NOMEM) 1346 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1347 #ifdef EHCI_DEBUG 1348 if (err) 1349 printf("ehci_allocm: usb_reserve_allocm()= %s (%d)\n", 1350 usbd_errstr(err), err); 1351 #endif 1352 return (err); 1353 } 1354 1355 Static void 1356 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1357 { 1358 struct ehci_softc *sc = bus->hci_private; 1359 1360 if (dma->block->flags & USB_DMA_RESERVE) { 1361 usb_reserve_freem(&sc->sc_dma_reserve, 1362 dma); 1363 return; 1364 } 1365 usb_freemem(&sc->sc_bus, dma); 1366 } 1367 1368 Static usbd_xfer_handle 1369 ehci_allocx(struct usbd_bus *bus) 1370 { 1371 struct ehci_softc *sc = bus->hci_private; 1372 usbd_xfer_handle xfer; 1373 1374 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1375 if (xfer != NULL) { 1376 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1377 #ifdef DIAGNOSTIC 1378 if (xfer->busy_free != XFER_FREE) { 1379 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1380 xfer->busy_free); 1381 } 1382 #endif 1383 } else { 1384 xfer = kmem_alloc(sizeof(struct ehci_xfer), KM_SLEEP); 1385 } 1386 if (xfer != NULL) { 1387 memset(xfer, 0, sizeof(struct ehci_xfer)); 1388 #ifdef DIAGNOSTIC 1389 EXFER(xfer)->isdone = 1; 1390 xfer->busy_free = XFER_BUSY; 1391 #endif 1392 } 1393 return (xfer); 1394 } 1395 1396 Static void 1397 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1398 { 1399 struct ehci_softc *sc = bus->hci_private; 1400 1401 #ifdef DIAGNOSTIC 1402 if (xfer->busy_free != XFER_BUSY) { 1403 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1404 xfer->busy_free); 1405 } 1406 xfer->busy_free = XFER_FREE; 1407 if (!EXFER(xfer)->isdone) { 1408 printf("ehci_freex: !isdone\n"); 1409 } 1410 #endif 1411 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1412 } 1413 1414 Static void 1415 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1416 { 1417 struct ehci_softc *sc = bus->hci_private; 1418 1419 *lock = &sc->sc_lock; 1420 } 1421 1422 Static void 1423 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1424 { 1425 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1426 1427 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1428 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1429 #ifdef EHCI_DEBUG 1430 if (ehcidebug) 1431 usbd_dump_pipe(pipe); 1432 #endif 1433 epipe->nexttoggle = 0; 1434 } 1435 1436 Static void 1437 ehci_noop(usbd_pipe_handle pipe) 1438 { 1439 } 1440 1441 #ifdef EHCI_DEBUG 1442 Static void 1443 ehci_dump_regs(ehci_softc_t *sc) 1444 { 1445 int i; 1446 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1447 EOREAD4(sc, EHCI_USBCMD), 1448 EOREAD4(sc, EHCI_USBSTS), 1449 EOREAD4(sc, EHCI_USBINTR)); 1450 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1451 EOREAD4(sc, EHCI_FRINDEX), 1452 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1453 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1454 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1455 for (i = 1; i <= sc->sc_noport; i++) 1456 printf("port %d status=0x%08x\n", i, 1457 EOREAD4(sc, EHCI_PORTSC(i))); 1458 } 1459 1460 /* 1461 * Unused function - this is meant to be called from a kernel 1462 * debugger. 1463 */ 1464 void 1465 ehci_dump(void) 1466 { 1467 ehci_dump_regs(theehci); 1468 } 1469 1470 Static void 1471 ehci_dump_link(ehci_link_t link, int type) 1472 { 1473 link = le32toh(link); 1474 printf("0x%08x", link); 1475 if (link & EHCI_LINK_TERMINATE) 1476 printf("<T>"); 1477 else { 1478 printf("<"); 1479 if (type) { 1480 switch (EHCI_LINK_TYPE(link)) { 1481 case EHCI_LINK_ITD: printf("ITD"); break; 1482 case EHCI_LINK_QH: printf("QH"); break; 1483 case EHCI_LINK_SITD: printf("SITD"); break; 1484 case EHCI_LINK_FSTN: printf("FSTN"); break; 1485 } 1486 } 1487 printf(">"); 1488 } 1489 } 1490 1491 Static void 1492 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1493 { 1494 int i; 1495 u_int32_t stop; 1496 1497 stop = 0; 1498 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1499 ehci_dump_sqtd(sqtd); 1500 usb_syncmem(&sqtd->dma, 1501 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1502 sizeof(sqtd->qtd), 1503 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1504 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1505 usb_syncmem(&sqtd->dma, 1506 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1507 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1508 } 1509 if (sqtd) 1510 printf("dump aborted, too many TDs\n"); 1511 } 1512 1513 Static void 1514 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1515 { 1516 usb_syncmem(&sqtd->dma, sqtd->offs, 1517 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1518 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1519 ehci_dump_qtd(&sqtd->qtd); 1520 usb_syncmem(&sqtd->dma, sqtd->offs, 1521 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1522 } 1523 1524 Static void 1525 ehci_dump_qtd(ehci_qtd_t *qtd) 1526 { 1527 u_int32_t s; 1528 char sbuf[128]; 1529 1530 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1531 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1532 printf("\n"); 1533 s = le32toh(qtd->qtd_status); 1534 snprintb(sbuf, sizeof(sbuf), 1535 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1536 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1537 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1538 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1539 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1540 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1541 EHCI_QTD_GET_PID(s), sbuf); 1542 for (s = 0; s < 5; s++) 1543 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1544 } 1545 1546 Static void 1547 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1548 { 1549 ehci_qh_t *qh = &sqh->qh; 1550 u_int32_t endp, endphub; 1551 1552 usb_syncmem(&sqh->dma, sqh->offs, 1553 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1554 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1555 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1556 endp = le32toh(qh->qh_endp); 1557 printf(" endp=0x%08x\n", endp); 1558 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1559 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1560 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1561 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1562 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1563 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1564 EHCI_QH_GET_NRL(endp)); 1565 endphub = le32toh(qh->qh_endphub); 1566 printf(" endphub=0x%08x\n", endphub); 1567 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1568 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1569 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1570 EHCI_QH_GET_MULT(endphub)); 1571 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1572 printf("Overlay qTD:\n"); 1573 ehci_dump_qtd(&qh->qh_qtd); 1574 usb_syncmem(&sqh->dma, sqh->offs, 1575 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1576 } 1577 1578 #if notyet 1579 Static void 1580 ehci_dump_itd(struct ehci_soft_itd *itd) 1581 { 1582 ehci_isoc_trans_t t; 1583 ehci_isoc_bufr_ptr_t b, b2, b3; 1584 int i; 1585 1586 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1587 1588 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1589 t = le32toh(itd->itd.itd_ctl[i]); 1590 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1591 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1592 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1593 EHCI_ITD_GET_OFFS(t)); 1594 } 1595 printf("ITDbufr: "); 1596 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1597 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1598 1599 b = le32toh(itd->itd.itd_bufr[0]); 1600 b2 = le32toh(itd->itd.itd_bufr[1]); 1601 b3 = le32toh(itd->itd.itd_bufr[2]); 1602 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1603 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1604 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1605 } 1606 1607 Static void 1608 ehci_dump_sitd(struct ehci_soft_itd *itd) 1609 { 1610 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1611 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1612 itd->xfer_next, itd->physaddr, itd->slot); 1613 } 1614 #endif 1615 1616 #ifdef DIAGNOSTIC 1617 Static void 1618 ehci_dump_exfer(struct ehci_xfer *ex) 1619 { 1620 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1621 } 1622 #endif 1623 #endif 1624 1625 Static usbd_status 1626 ehci_open(usbd_pipe_handle pipe) 1627 { 1628 usbd_device_handle dev = pipe->device; 1629 ehci_softc_t *sc = dev->bus->hci_private; 1630 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1631 u_int8_t addr = dev->address; 1632 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1633 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1634 ehci_soft_qh_t *sqh; 1635 usbd_status err; 1636 int ival, speed, naks; 1637 int hshubaddr, hshubport; 1638 1639 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1640 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1641 1642 if (dev->myhsport) { 1643 /* 1644 * When directly attached FS/LS device while doing embedded 1645 * transaction translations and we are the hub, set the hub 1646 * address to 0 (us). 1647 */ 1648 if (!(sc->sc_flags & EHCIF_ETTF) 1649 || (dev->myhsport->parent->address != sc->sc_addr)) { 1650 hshubaddr = dev->myhsport->parent->address; 1651 } else { 1652 hshubaddr = 0; 1653 } 1654 hshubport = dev->myhsport->portno; 1655 } else { 1656 hshubaddr = 0; 1657 hshubport = 0; 1658 } 1659 1660 if (sc->sc_dying) 1661 return (USBD_IOERROR); 1662 1663 /* toggle state needed for bulk endpoints */ 1664 epipe->nexttoggle = pipe->endpoint->datatoggle; 1665 1666 if (addr == sc->sc_addr) { 1667 switch (ed->bEndpointAddress) { 1668 case USB_CONTROL_ENDPOINT: 1669 pipe->methods = &ehci_root_ctrl_methods; 1670 break; 1671 case UE_DIR_IN | EHCI_INTR_ENDPT: 1672 pipe->methods = &ehci_root_intr_methods; 1673 break; 1674 default: 1675 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1676 ed->bEndpointAddress)); 1677 return (USBD_INVAL); 1678 } 1679 return (USBD_NORMAL_COMPLETION); 1680 } 1681 1682 /* XXX All this stuff is only valid for async. */ 1683 switch (dev->speed) { 1684 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1685 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1686 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1687 default: panic("ehci_open: bad device speed %d", dev->speed); 1688 } 1689 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1690 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1691 "isoc endpoint.\n"); 1692 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1693 "attached to a USB2 hub, and transaction translations are " 1694 "not yet supported.\n"); 1695 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1696 "root hub instead.\n"); 1697 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1698 hshubaddr, hshubport)); 1699 return USBD_INVAL; 1700 } 1701 1702 /* 1703 * For interrupt transfer, nak throttling must be disabled, but for 1704 * the other transfer type, nak throttling should be enabled from the 1705 * viewpoint that avoids the memory thrashing. 1706 */ 1707 naks = (xfertype == UE_INTERRUPT) ? 0 1708 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1709 1710 /* Allocate sqh for everything, save isoc xfers */ 1711 if (xfertype != UE_ISOCHRONOUS) { 1712 sqh = ehci_alloc_sqh(sc); 1713 if (sqh == NULL) 1714 return (USBD_NOMEM); 1715 /* qh_link filled when the QH is added */ 1716 sqh->qh.qh_endp = htole32( 1717 EHCI_QH_SET_ADDR(addr) | 1718 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1719 EHCI_QH_SET_EPS(speed) | 1720 EHCI_QH_DTC | 1721 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1722 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1723 EHCI_QH_CTL : 0) | 1724 EHCI_QH_SET_NRL(naks) 1725 ); 1726 sqh->qh.qh_endphub = htole32( 1727 EHCI_QH_SET_MULT(1) | 1728 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1729 ); 1730 if (speed != EHCI_QH_SPEED_HIGH) 1731 sqh->qh.qh_endphub |= htole32( 1732 EHCI_QH_SET_PORT(hshubport) | 1733 EHCI_QH_SET_HUBA(hshubaddr) | 1734 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1735 ); 1736 sqh->qh.qh_curqtd = EHCI_NULL; 1737 /* Fill the overlay qTD */ 1738 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1739 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1740 sqh->qh.qh_qtd.qtd_status = htole32(0); 1741 1742 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1743 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1744 epipe->sqh = sqh; 1745 } else { 1746 sqh = NULL; 1747 } /*xfertype == UE_ISOC*/ 1748 1749 switch (xfertype) { 1750 case UE_CONTROL: 1751 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1752 0, &epipe->u.ctl.reqdma); 1753 #ifdef EHCI_DEBUG 1754 if (err) 1755 printf("ehci_open: usb_allocmem()=%d\n", err); 1756 #endif 1757 if (err) 1758 goto bad; 1759 pipe->methods = &ehci_device_ctrl_methods; 1760 mutex_enter(&sc->sc_lock); 1761 ehci_add_qh(sc, sqh, sc->sc_async_head); 1762 mutex_exit(&sc->sc_lock); 1763 break; 1764 case UE_BULK: 1765 pipe->methods = &ehci_device_bulk_methods; 1766 mutex_enter(&sc->sc_lock); 1767 ehci_add_qh(sc, sqh, sc->sc_async_head); 1768 mutex_exit(&sc->sc_lock); 1769 break; 1770 case UE_INTERRUPT: 1771 pipe->methods = &ehci_device_intr_methods; 1772 ival = pipe->interval; 1773 if (ival == USBD_DEFAULT_INTERVAL) { 1774 if (speed == EHCI_QH_SPEED_HIGH) { 1775 if (ed->bInterval > 16) { 1776 /* 1777 * illegal with high-speed, but there 1778 * were documentation bugs in the spec, 1779 * so be generous 1780 */ 1781 ival = 256; 1782 } else 1783 ival = (1 << (ed->bInterval - 1)) / 8; 1784 } else 1785 ival = ed->bInterval; 1786 } 1787 err = ehci_device_setintr(sc, sqh, ival); 1788 if (err) 1789 goto bad; 1790 break; 1791 case UE_ISOCHRONOUS: 1792 pipe->methods = &ehci_device_isoc_methods; 1793 if (ed->bInterval == 0 || ed->bInterval > 16) { 1794 printf("ehci: opening pipe with invalid bInterval\n"); 1795 err = USBD_INVAL; 1796 goto bad; 1797 } 1798 if (UGETW(ed->wMaxPacketSize) == 0) { 1799 printf("ehci: zero length endpoint open request\n"); 1800 err = USBD_INVAL; 1801 goto bad; 1802 } 1803 epipe->u.isoc.next_frame = 0; 1804 epipe->u.isoc.cur_xfers = 0; 1805 break; 1806 default: 1807 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1808 err = USBD_INVAL; 1809 goto bad; 1810 } 1811 return (USBD_NORMAL_COMPLETION); 1812 1813 bad: 1814 if (sqh != NULL) 1815 ehci_free_sqh(sc, sqh); 1816 return (err); 1817 } 1818 1819 /* 1820 * Add an ED to the schedule. Called with USB lock held. 1821 */ 1822 Static void 1823 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1824 { 1825 1826 KASSERT(mutex_owned(&sc->sc_lock)); 1827 1828 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1829 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1830 sqh->next = head->next; 1831 sqh->qh.qh_link = head->qh.qh_link; 1832 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1833 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1834 head->next = sqh; 1835 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1836 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1837 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1838 1839 #ifdef EHCI_DEBUG 1840 if (ehcidebug > 5) { 1841 printf("ehci_add_qh:\n"); 1842 ehci_dump_sqh(sqh); 1843 } 1844 #endif 1845 } 1846 1847 /* 1848 * Remove an ED from the schedule. Called with USB lock held. 1849 */ 1850 Static void 1851 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1852 { 1853 ehci_soft_qh_t *p; 1854 1855 KASSERT(mutex_owned(&sc->sc_lock)); 1856 1857 /* XXX */ 1858 for (p = head; p != NULL && p->next != sqh; p = p->next) 1859 ; 1860 if (p == NULL) 1861 panic("ehci_rem_qh: ED not found"); 1862 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1863 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1864 p->next = sqh->next; 1865 p->qh.qh_link = sqh->qh.qh_link; 1866 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1867 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1868 1869 ehci_sync_hc(sc); 1870 } 1871 1872 Static void 1873 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1874 { 1875 int i; 1876 u_int32_t status; 1877 1878 /* Save toggle bit and ping status. */ 1879 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1880 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1881 status = sqh->qh.qh_qtd.qtd_status & 1882 htole32(EHCI_QTD_TOGGLE_MASK | 1883 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1884 /* Set HALTED to make hw leave it alone. */ 1885 sqh->qh.qh_qtd.qtd_status = 1886 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1887 usb_syncmem(&sqh->dma, 1888 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1889 sizeof(sqh->qh.qh_qtd.qtd_status), 1890 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1891 sqh->qh.qh_curqtd = 0; 1892 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1893 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1894 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1895 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1896 sqh->sqtd = sqtd; 1897 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1898 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1899 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1900 sqh->qh.qh_qtd.qtd_status = status; 1901 usb_syncmem(&sqh->dma, 1902 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1903 sizeof(sqh->qh.qh_qtd.qtd_status), 1904 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1905 } 1906 1907 /* 1908 * Ensure that the HC has released all references to the QH. We do this 1909 * by asking for a Async Advance Doorbell interrupt and then we wait for 1910 * the interrupt. 1911 * To make this easier we first obtain exclusive use of the doorbell. 1912 */ 1913 Static void 1914 ehci_sync_hc(ehci_softc_t *sc) 1915 { 1916 int error; 1917 1918 KASSERT(mutex_owned(&sc->sc_lock)); 1919 1920 if (sc->sc_dying) { 1921 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1922 return; 1923 } 1924 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1925 /* ask for doorbell */ 1926 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1927 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1928 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1929 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 1930 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1931 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1932 #ifdef DIAGNOSTIC 1933 if (error) 1934 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 1935 #endif 1936 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1937 } 1938 1939 Static void 1940 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1941 { 1942 struct ehci_soft_itd *itd, *prev; 1943 1944 prev = NULL; 1945 1946 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1947 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1948 1949 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1950 prev = itd->u.frame_list.prev; 1951 /* Unlink itd from hardware chain, or frame array */ 1952 if (prev == NULL) { /* We're at the table head */ 1953 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1954 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1955 usb_syncmem(&sc->sc_fldma, 1956 sizeof(ehci_link_t) * itd->slot, 1957 sizeof(ehci_link_t), 1958 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1959 1960 if (itd->u.frame_list.next != NULL) 1961 itd->u.frame_list.next->u.frame_list.prev = NULL; 1962 } else { 1963 /* XXX this part is untested... */ 1964 prev->itd.itd_next = itd->itd.itd_next; 1965 usb_syncmem(&itd->dma, 1966 itd->offs + offsetof(ehci_itd_t, itd_next), 1967 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1968 1969 prev->u.frame_list.next = itd->u.frame_list.next; 1970 if (itd->u.frame_list.next != NULL) 1971 itd->u.frame_list.next->u.frame_list.prev = prev; 1972 } 1973 } 1974 1975 prev = NULL; 1976 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1977 if (prev != NULL) 1978 ehci_free_itd(sc, prev); 1979 prev = itd; 1980 } 1981 if (prev) 1982 ehci_free_itd(sc, prev); 1983 exfer->itdstart = NULL; 1984 exfer->itdend = NULL; 1985 } 1986 1987 /***********/ 1988 1989 /* 1990 * Data structures and routines to emulate the root hub. 1991 */ 1992 Static usb_device_descriptor_t ehci_devd = { 1993 USB_DEVICE_DESCRIPTOR_SIZE, 1994 UDESC_DEVICE, /* type */ 1995 {0x00, 0x02}, /* USB version */ 1996 UDCLASS_HUB, /* class */ 1997 UDSUBCLASS_HUB, /* subclass */ 1998 UDPROTO_HSHUBSTT, /* protocol */ 1999 64, /* max packet */ 2000 {0},{0},{0x00,0x01}, /* device id */ 2001 1,2,0, /* string indicies */ 2002 1 /* # of configurations */ 2003 }; 2004 2005 Static const usb_device_qualifier_t ehci_odevd = { 2006 USB_DEVICE_DESCRIPTOR_SIZE, 2007 UDESC_DEVICE_QUALIFIER, /* type */ 2008 {0x00, 0x02}, /* USB version */ 2009 UDCLASS_HUB, /* class */ 2010 UDSUBCLASS_HUB, /* subclass */ 2011 UDPROTO_FSHUB, /* protocol */ 2012 64, /* max packet */ 2013 1, /* # of configurations */ 2014 0 2015 }; 2016 2017 Static const usb_config_descriptor_t ehci_confd = { 2018 USB_CONFIG_DESCRIPTOR_SIZE, 2019 UDESC_CONFIG, 2020 {USB_CONFIG_DESCRIPTOR_SIZE + 2021 USB_INTERFACE_DESCRIPTOR_SIZE + 2022 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2023 1, 2024 1, 2025 0, 2026 UC_ATTR_MBO | UC_SELF_POWERED, 2027 0 /* max power */ 2028 }; 2029 2030 Static const usb_interface_descriptor_t ehci_ifcd = { 2031 USB_INTERFACE_DESCRIPTOR_SIZE, 2032 UDESC_INTERFACE, 2033 0, 2034 0, 2035 1, 2036 UICLASS_HUB, 2037 UISUBCLASS_HUB, 2038 UIPROTO_HSHUBSTT, 2039 0 2040 }; 2041 2042 Static const usb_endpoint_descriptor_t ehci_endpd = { 2043 USB_ENDPOINT_DESCRIPTOR_SIZE, 2044 UDESC_ENDPOINT, 2045 UE_DIR_IN | EHCI_INTR_ENDPT, 2046 UE_INTERRUPT, 2047 {8, 0}, /* max packet */ 2048 12 2049 }; 2050 2051 Static const usb_hub_descriptor_t ehci_hubd = { 2052 USB_HUB_DESCRIPTOR_SIZE, 2053 UDESC_HUB, 2054 0, 2055 {0,0}, 2056 0, 2057 0, 2058 {""}, 2059 {""}, 2060 }; 2061 2062 /* 2063 * Simulate a hardware hub by handling all the necessary requests. 2064 */ 2065 Static usbd_status 2066 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2067 { 2068 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2069 usbd_status err; 2070 2071 /* Insert last in queue. */ 2072 mutex_enter(&sc->sc_lock); 2073 err = usb_insert_transfer(xfer); 2074 mutex_exit(&sc->sc_lock); 2075 if (err) 2076 return (err); 2077 2078 /* Pipe isn't running, start first */ 2079 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2080 } 2081 2082 Static usbd_status 2083 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2084 { 2085 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2086 usb_device_request_t *req; 2087 void *buf = NULL; 2088 int port, i; 2089 int len, value, index, l, totlen = 0; 2090 usb_port_status_t ps; 2091 usb_hub_descriptor_t hubd; 2092 usbd_status err; 2093 u_int32_t v; 2094 2095 if (sc->sc_dying) 2096 return (USBD_IOERROR); 2097 2098 #ifdef DIAGNOSTIC 2099 if (!(xfer->rqflags & URQ_REQUEST)) 2100 /* XXX panic */ 2101 return (USBD_INVAL); 2102 #endif 2103 req = &xfer->request; 2104 2105 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2106 req->bmRequestType, req->bRequest)); 2107 2108 len = UGETW(req->wLength); 2109 value = UGETW(req->wValue); 2110 index = UGETW(req->wIndex); 2111 2112 if (len != 0) 2113 buf = KERNADDR(&xfer->dmabuf, 0); 2114 2115 #define C(x,y) ((x) | ((y) << 8)) 2116 switch(C(req->bRequest, req->bmRequestType)) { 2117 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2118 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2119 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2120 /* 2121 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2122 * for the integrated root hub. 2123 */ 2124 break; 2125 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2126 if (len > 0) { 2127 *(u_int8_t *)buf = sc->sc_conf; 2128 totlen = 1; 2129 } 2130 break; 2131 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2132 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2133 if (len == 0) 2134 break; 2135 switch(value >> 8) { 2136 case UDESC_DEVICE: 2137 if ((value & 0xff) != 0) { 2138 err = USBD_IOERROR; 2139 goto ret; 2140 } 2141 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2142 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2143 memcpy(buf, &ehci_devd, l); 2144 break; 2145 /* 2146 * We can't really operate at another speed, but the spec says 2147 * we need this descriptor. 2148 */ 2149 case UDESC_DEVICE_QUALIFIER: 2150 if ((value & 0xff) != 0) { 2151 err = USBD_IOERROR; 2152 goto ret; 2153 } 2154 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2155 memcpy(buf, &ehci_odevd, l); 2156 break; 2157 /* 2158 * We can't really operate at another speed, but the spec says 2159 * we need this descriptor. 2160 */ 2161 case UDESC_OTHER_SPEED_CONFIGURATION: 2162 case UDESC_CONFIG: 2163 if ((value & 0xff) != 0) { 2164 err = USBD_IOERROR; 2165 goto ret; 2166 } 2167 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2168 memcpy(buf, &ehci_confd, l); 2169 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2170 value >> 8; 2171 buf = (char *)buf + l; 2172 len -= l; 2173 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2174 totlen += l; 2175 memcpy(buf, &ehci_ifcd, l); 2176 buf = (char *)buf + l; 2177 len -= l; 2178 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2179 totlen += l; 2180 memcpy(buf, &ehci_endpd, l); 2181 break; 2182 case UDESC_STRING: 2183 #define sd ((usb_string_descriptor_t *)buf) 2184 switch (value & 0xff) { 2185 case 0: /* Language table */ 2186 totlen = usb_makelangtbl(sd, len); 2187 break; 2188 case 1: /* Vendor */ 2189 totlen = usb_makestrdesc(sd, len, 2190 sc->sc_vendor); 2191 break; 2192 case 2: /* Product */ 2193 totlen = usb_makestrdesc(sd, len, 2194 "EHCI root hub"); 2195 break; 2196 } 2197 #undef sd 2198 break; 2199 default: 2200 err = USBD_IOERROR; 2201 goto ret; 2202 } 2203 break; 2204 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2205 if (len > 0) { 2206 *(u_int8_t *)buf = 0; 2207 totlen = 1; 2208 } 2209 break; 2210 case C(UR_GET_STATUS, UT_READ_DEVICE): 2211 if (len > 1) { 2212 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2213 totlen = 2; 2214 } 2215 break; 2216 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2217 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2218 if (len > 1) { 2219 USETW(((usb_status_t *)buf)->wStatus, 0); 2220 totlen = 2; 2221 } 2222 break; 2223 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2224 if (value >= USB_MAX_DEVICES) { 2225 err = USBD_IOERROR; 2226 goto ret; 2227 } 2228 sc->sc_addr = value; 2229 break; 2230 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2231 if (value != 0 && value != 1) { 2232 err = USBD_IOERROR; 2233 goto ret; 2234 } 2235 sc->sc_conf = value; 2236 break; 2237 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2238 break; 2239 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2240 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2241 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2242 err = USBD_IOERROR; 2243 goto ret; 2244 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2245 break; 2246 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2247 break; 2248 /* Hub requests */ 2249 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2250 break; 2251 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2252 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2253 "port=%d feature=%d\n", 2254 index, value)); 2255 if (index < 1 || index > sc->sc_noport) { 2256 err = USBD_IOERROR; 2257 goto ret; 2258 } 2259 port = EHCI_PORTSC(index); 2260 v = EOREAD4(sc, port); 2261 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2262 v &= ~EHCI_PS_CLEAR; 2263 switch(value) { 2264 case UHF_PORT_ENABLE: 2265 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2266 break; 2267 case UHF_PORT_SUSPEND: 2268 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2269 break; 2270 v &= ~EHCI_PS_SUSP; 2271 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2272 /* see USB2 spec ch. 7.1.7.7 */ 2273 usb_delay_ms(&sc->sc_bus, 20); 2274 EOWRITE4(sc, port, v); 2275 usb_delay_ms(&sc->sc_bus, 2); 2276 #ifdef DEBUG 2277 v = EOREAD4(sc, port); 2278 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2279 printf("ehci: resume failed: %x\n", v); 2280 #endif 2281 break; 2282 case UHF_PORT_POWER: 2283 if (sc->sc_hasppc) 2284 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2285 break; 2286 case UHF_PORT_TEST: 2287 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2288 "%d\n", index)); 2289 break; 2290 case UHF_PORT_INDICATOR: 2291 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2292 "%d\n", index)); 2293 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2294 break; 2295 case UHF_C_PORT_CONNECTION: 2296 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2297 break; 2298 case UHF_C_PORT_ENABLE: 2299 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2300 break; 2301 case UHF_C_PORT_SUSPEND: 2302 /* how? */ 2303 break; 2304 case UHF_C_PORT_OVER_CURRENT: 2305 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2306 break; 2307 case UHF_C_PORT_RESET: 2308 sc->sc_isreset[index] = 0; 2309 break; 2310 default: 2311 err = USBD_IOERROR; 2312 goto ret; 2313 } 2314 #if 0 2315 switch(value) { 2316 case UHF_C_PORT_CONNECTION: 2317 case UHF_C_PORT_ENABLE: 2318 case UHF_C_PORT_SUSPEND: 2319 case UHF_C_PORT_OVER_CURRENT: 2320 case UHF_C_PORT_RESET: 2321 default: 2322 break; 2323 } 2324 #endif 2325 break; 2326 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2327 if (len == 0) 2328 break; 2329 if ((value & 0xff) != 0) { 2330 err = USBD_IOERROR; 2331 goto ret; 2332 } 2333 hubd = ehci_hubd; 2334 hubd.bNbrPorts = sc->sc_noport; 2335 v = EOREAD4(sc, EHCI_HCSPARAMS); 2336 USETW(hubd.wHubCharacteristics, 2337 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2338 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2339 ? UHD_PORT_IND : 0); 2340 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2341 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2342 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2343 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2344 l = min(len, hubd.bDescLength); 2345 totlen = l; 2346 memcpy(buf, &hubd, l); 2347 break; 2348 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2349 if (len != 4) { 2350 err = USBD_IOERROR; 2351 goto ret; 2352 } 2353 memset(buf, 0, len); /* ? XXX */ 2354 totlen = len; 2355 break; 2356 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2357 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2358 index)); 2359 if (index < 1 || index > sc->sc_noport) { 2360 err = USBD_IOERROR; 2361 goto ret; 2362 } 2363 if (len != 4) { 2364 err = USBD_IOERROR; 2365 goto ret; 2366 } 2367 v = EOREAD4(sc, EHCI_PORTSC(index)); 2368 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2369 2370 i = UPS_HIGH_SPEED; 2371 if (sc->sc_flags & EHCIF_ETTF) { 2372 /* 2373 * If we are doing embedded transaction translation, 2374 * then directly attached LS/FS devices are reset by 2375 * the EHCI controller itself. PSPD is encoded 2376 * the same way as in USBSTATUS. 2377 */ 2378 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2379 } 2380 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2381 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2382 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2383 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2384 if (v & EHCI_PS_PR) i |= UPS_RESET; 2385 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2386 if (sc->sc_vendor_port_status) 2387 i = sc->sc_vendor_port_status(sc, v, i); 2388 USETW(ps.wPortStatus, i); 2389 i = 0; 2390 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2391 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2392 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2393 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2394 USETW(ps.wPortChange, i); 2395 l = min(len, sizeof ps); 2396 memcpy(buf, &ps, l); 2397 totlen = l; 2398 break; 2399 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2400 err = USBD_IOERROR; 2401 goto ret; 2402 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2403 break; 2404 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2405 if (index < 1 || index > sc->sc_noport) { 2406 err = USBD_IOERROR; 2407 goto ret; 2408 } 2409 port = EHCI_PORTSC(index); 2410 v = EOREAD4(sc, port); 2411 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2412 v &= ~EHCI_PS_CLEAR; 2413 switch(value) { 2414 case UHF_PORT_ENABLE: 2415 EOWRITE4(sc, port, v | EHCI_PS_PE); 2416 break; 2417 case UHF_PORT_SUSPEND: 2418 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2419 break; 2420 case UHF_PORT_RESET: 2421 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2422 index)); 2423 if (EHCI_PS_IS_LOWSPEED(v) 2424 && sc->sc_ncomp > 0 2425 && !(sc->sc_flags & EHCIF_ETTF)) { 2426 /* 2427 * Low speed device on non-ETTF controller or 2428 * unaccompanied controller, give up ownership. 2429 */ 2430 ehci_disown(sc, index, 1); 2431 break; 2432 } 2433 /* Start reset sequence. */ 2434 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2435 EOWRITE4(sc, port, v | EHCI_PS_PR); 2436 /* Wait for reset to complete. */ 2437 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2438 if (sc->sc_dying) { 2439 err = USBD_IOERROR; 2440 goto ret; 2441 } 2442 /* 2443 * An embedded transaction translater will automatically 2444 * terminate the reset sequence so there's no need to 2445 * it. 2446 */ 2447 v = EOREAD4(sc, port); 2448 if (v & EHCI_PS_PR) { 2449 /* Terminate reset sequence. */ 2450 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2451 /* Wait for HC to complete reset. */ 2452 usb_delay_ms(&sc->sc_bus, 2453 EHCI_PORT_RESET_COMPLETE); 2454 if (sc->sc_dying) { 2455 err = USBD_IOERROR; 2456 goto ret; 2457 } 2458 } 2459 2460 v = EOREAD4(sc, port); 2461 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2462 if (v & EHCI_PS_PR) { 2463 printf("%s: port reset timeout\n", 2464 device_xname(sc->sc_dev)); 2465 return (USBD_TIMEOUT); 2466 } 2467 if (!(v & EHCI_PS_PE)) { 2468 /* Not a high speed device, give up ownership.*/ 2469 ehci_disown(sc, index, 0); 2470 break; 2471 } 2472 sc->sc_isreset[index] = 1; 2473 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2474 index, v)); 2475 break; 2476 case UHF_PORT_POWER: 2477 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2478 "%d (has PPC = %d)\n", index, 2479 sc->sc_hasppc)); 2480 if (sc->sc_hasppc) 2481 EOWRITE4(sc, port, v | EHCI_PS_PP); 2482 break; 2483 case UHF_PORT_TEST: 2484 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2485 "%d\n", index)); 2486 break; 2487 case UHF_PORT_INDICATOR: 2488 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2489 "%d\n", index)); 2490 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2491 break; 2492 default: 2493 err = USBD_IOERROR; 2494 goto ret; 2495 } 2496 break; 2497 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2498 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2499 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2500 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2501 break; 2502 default: 2503 err = USBD_IOERROR; 2504 goto ret; 2505 } 2506 xfer->actlen = totlen; 2507 err = USBD_NORMAL_COMPLETION; 2508 ret: 2509 mutex_enter(&sc->sc_lock); 2510 xfer->status = err; 2511 usb_transfer_complete(xfer); 2512 mutex_exit(&sc->sc_lock); 2513 return (USBD_IN_PROGRESS); 2514 } 2515 2516 Static void 2517 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2518 { 2519 int port; 2520 u_int32_t v; 2521 2522 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2523 #ifdef DIAGNOSTIC 2524 if (sc->sc_npcomp != 0) { 2525 int i = (index-1) / sc->sc_npcomp; 2526 if (i >= sc->sc_ncomp) 2527 printf("%s: strange port\n", 2528 device_xname(sc->sc_dev)); 2529 else 2530 printf("%s: handing over %s speed device on " 2531 "port %d to %s\n", 2532 device_xname(sc->sc_dev), 2533 lowspeed ? "low" : "full", 2534 index, device_xname(sc->sc_comps[i])); 2535 } else { 2536 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2537 } 2538 #endif 2539 port = EHCI_PORTSC(index); 2540 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2541 EOWRITE4(sc, port, v | EHCI_PS_PO); 2542 } 2543 2544 /* Abort a root control request. */ 2545 Static void 2546 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2547 { 2548 /* Nothing to do, all transfers are synchronous. */ 2549 } 2550 2551 /* Close the root pipe. */ 2552 Static void 2553 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2554 { 2555 DPRINTF(("ehci_root_ctrl_close\n")); 2556 /* Nothing to do. */ 2557 } 2558 2559 Static void 2560 ehci_root_intr_done(usbd_xfer_handle xfer) 2561 { 2562 xfer->hcpriv = NULL; 2563 } 2564 2565 Static usbd_status 2566 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2567 { 2568 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2569 usbd_status err; 2570 2571 /* Insert last in queue. */ 2572 mutex_enter(&sc->sc_lock); 2573 err = usb_insert_transfer(xfer); 2574 mutex_exit(&sc->sc_lock); 2575 if (err) 2576 return (err); 2577 2578 /* Pipe isn't running, start first */ 2579 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2580 } 2581 2582 Static usbd_status 2583 ehci_root_intr_start(usbd_xfer_handle xfer) 2584 { 2585 usbd_pipe_handle pipe = xfer->pipe; 2586 ehci_softc_t *sc = pipe->device->bus->hci_private; 2587 2588 if (sc->sc_dying) 2589 return (USBD_IOERROR); 2590 2591 mutex_enter(&sc->sc_lock); 2592 sc->sc_intrxfer = xfer; 2593 mutex_exit(&sc->sc_lock); 2594 2595 return (USBD_IN_PROGRESS); 2596 } 2597 2598 /* Abort a root interrupt request. */ 2599 Static void 2600 ehci_root_intr_abort(usbd_xfer_handle xfer) 2601 { 2602 #ifdef DIAGNOSTIC 2603 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2604 #endif 2605 2606 KASSERT(mutex_owned(&sc->sc_lock)); 2607 if (xfer->pipe->intrxfer == xfer) { 2608 DPRINTF(("ehci_root_intr_abort: remove\n")); 2609 xfer->pipe->intrxfer = NULL; 2610 } 2611 xfer->status = USBD_CANCELLED; 2612 usb_transfer_complete(xfer); 2613 } 2614 2615 /* Close the root pipe. */ 2616 Static void 2617 ehci_root_intr_close(usbd_pipe_handle pipe) 2618 { 2619 ehci_softc_t *sc = pipe->device->bus->hci_private; 2620 2621 KASSERT(mutex_owned(&sc->sc_lock)); 2622 2623 DPRINTF(("ehci_root_intr_close\n")); 2624 2625 sc->sc_intrxfer = NULL; 2626 } 2627 2628 Static void 2629 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2630 { 2631 xfer->hcpriv = NULL; 2632 } 2633 2634 /************************/ 2635 2636 Static ehci_soft_qh_t * 2637 ehci_alloc_sqh(ehci_softc_t *sc) 2638 { 2639 ehci_soft_qh_t *sqh; 2640 usbd_status err; 2641 int i, offs; 2642 usb_dma_t dma; 2643 2644 if (sc->sc_freeqhs == NULL) { 2645 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2646 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2647 EHCI_PAGE_SIZE, &dma); 2648 #ifdef EHCI_DEBUG 2649 if (err) 2650 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2651 #endif 2652 if (err) 2653 return (NULL); 2654 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2655 offs = i * EHCI_SQH_SIZE; 2656 sqh = KERNADDR(&dma, offs); 2657 sqh->physaddr = DMAADDR(&dma, offs); 2658 sqh->dma = dma; 2659 sqh->offs = offs; 2660 sqh->next = sc->sc_freeqhs; 2661 sc->sc_freeqhs = sqh; 2662 } 2663 } 2664 sqh = sc->sc_freeqhs; 2665 sc->sc_freeqhs = sqh->next; 2666 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2667 sqh->next = NULL; 2668 return (sqh); 2669 } 2670 2671 Static void 2672 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2673 { 2674 sqh->next = sc->sc_freeqhs; 2675 sc->sc_freeqhs = sqh; 2676 } 2677 2678 Static ehci_soft_qtd_t * 2679 ehci_alloc_sqtd(ehci_softc_t *sc) 2680 { 2681 ehci_soft_qtd_t *sqtd = NULL; 2682 usbd_status err; 2683 int i, offs; 2684 usb_dma_t dma; 2685 2686 if (sc->sc_freeqtds == NULL) { 2687 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2688 2689 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2690 EHCI_PAGE_SIZE, &dma); 2691 #ifdef EHCI_DEBUG 2692 if (err) 2693 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2694 #endif 2695 if (err) 2696 goto done; 2697 2698 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2699 offs = i * EHCI_SQTD_SIZE; 2700 sqtd = KERNADDR(&dma, offs); 2701 sqtd->physaddr = DMAADDR(&dma, offs); 2702 sqtd->dma = dma; 2703 sqtd->offs = offs; 2704 2705 sqtd->nextqtd = sc->sc_freeqtds; 2706 sc->sc_freeqtds = sqtd; 2707 } 2708 } 2709 2710 sqtd = sc->sc_freeqtds; 2711 sc->sc_freeqtds = sqtd->nextqtd; 2712 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2713 sqtd->nextqtd = NULL; 2714 sqtd->xfer = NULL; 2715 2716 done: 2717 return (sqtd); 2718 } 2719 2720 Static void 2721 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2722 { 2723 2724 KASSERT(mutex_owned(&sc->sc_lock)); 2725 2726 sqtd->nextqtd = sc->sc_freeqtds; 2727 sc->sc_freeqtds = sqtd; 2728 } 2729 2730 Static usbd_status 2731 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2732 int alen, int rd, usbd_xfer_handle xfer, 2733 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2734 { 2735 ehci_soft_qtd_t *next, *cur; 2736 ehci_physaddr_t nextphys; 2737 u_int32_t qtdstatus; 2738 int len, curlen, mps; 2739 int i, tog; 2740 int pages, pageoffs; 2741 bus_size_t curoffs; 2742 vaddr_t va, va_offs; 2743 usb_dma_t *dma = &xfer->dmabuf; 2744 u_int16_t flags = xfer->flags; 2745 paddr_t a; 2746 2747 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2748 2749 len = alen; 2750 qtdstatus = EHCI_QTD_ACTIVE | 2751 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2752 EHCI_QTD_SET_CERR(3) 2753 /* IOC set below */ 2754 /* BYTES set below */ 2755 ; 2756 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2757 tog = epipe->nexttoggle; 2758 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2759 2760 cur = ehci_alloc_sqtd(sc); 2761 *sp = cur; 2762 if (cur == NULL) 2763 goto nomem; 2764 2765 usb_syncmem(dma, 0, alen, 2766 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2767 curoffs = 0; 2768 for (;;) { 2769 /* The EHCI hardware can handle at most 5 pages. */ 2770 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2771 va_offs = EHCI_PAGE_OFFSET(va_offs); 2772 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 2773 /* we can handle it in this QTD */ 2774 curlen = len - curoffs; 2775 } else { 2776 /* must use multiple TDs, fill as much as possible. */ 2777 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 2778 2779 /* the length must be a multiple of the max size */ 2780 curlen -= curlen % mps; 2781 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2782 "curlen=%d\n", curlen)); 2783 #ifdef DIAGNOSTIC 2784 if (curlen == 0) 2785 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2786 #endif 2787 } 2788 DPRINTFN(4,("ehci_alloc_sqtd_chain: len=%d curlen=%d " 2789 "curoffs=%d\n", len, curlen, curoffs)); 2790 2791 /* 2792 * Allocate another transfer if there's more data left, 2793 * or if force last short transfer flag is set and we're 2794 * allocating a multiple of the max packet size. 2795 */ 2796 2797 if (curoffs + curlen != len || 2798 ((curlen % mps) == 0 && !rd && curlen != 0 && 2799 (flags & USBD_FORCE_SHORT_XFER))) { 2800 next = ehci_alloc_sqtd(sc); 2801 if (next == NULL) 2802 goto nomem; 2803 nextphys = htole32(next->physaddr); 2804 } else { 2805 next = NULL; 2806 nextphys = EHCI_NULL; 2807 } 2808 2809 /* Find number of pages we'll be using, insert dma addresses */ 2810 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2811 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2812 pageoffs = EHCI_PAGE(curoffs); 2813 for (i = 0; i < pages; i++) { 2814 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2815 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2816 /* Cast up to avoid compiler warnings */ 2817 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2818 } 2819 2820 /* First buffer pointer requires a page offset to start at */ 2821 va = (vaddr_t)KERNADDR(dma, curoffs); 2822 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2823 2824 cur->nextqtd = next; 2825 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2826 cur->qtd.qtd_status = 2827 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2828 cur->xfer = xfer; 2829 cur->len = curlen; 2830 2831 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n", 2832 curoffs, curoffs + curlen)); 2833 2834 /* adjust the toggle based on the number of packets in this 2835 qtd */ 2836 if (((curlen + mps - 1) / mps) & 1) { 2837 tog ^= 1; 2838 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2839 } 2840 if (next == NULL) 2841 break; 2842 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2843 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2844 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2845 if (len) 2846 curoffs += curlen; 2847 cur = next; 2848 } 2849 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2850 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2851 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2852 *ep = cur; 2853 epipe->nexttoggle = tog; 2854 2855 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2856 *sp, *ep)); 2857 2858 return (USBD_NORMAL_COMPLETION); 2859 2860 nomem: 2861 /* XXX free chain */ 2862 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2863 return (USBD_NOMEM); 2864 } 2865 2866 Static void 2867 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2868 ehci_soft_qtd_t *sqtdend) 2869 { 2870 ehci_soft_qtd_t *p; 2871 int i; 2872 2873 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2874 sqtd, sqtdend)); 2875 2876 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2877 p = sqtd->nextqtd; 2878 ehci_free_sqtd(sc, sqtd); 2879 } 2880 } 2881 2882 Static ehci_soft_itd_t * 2883 ehci_alloc_itd(ehci_softc_t *sc) 2884 { 2885 struct ehci_soft_itd *itd, *freeitd; 2886 usbd_status err; 2887 int i, offs, frindex, previndex; 2888 usb_dma_t dma; 2889 2890 mutex_enter(&sc->sc_lock); 2891 2892 /* Find an itd that wasn't freed this frame or last frame. This can 2893 * discard itds that were freed before frindex wrapped around 2894 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2895 * interrupt and fiddling with list when that happens */ 2896 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2897 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2898 2899 freeitd = NULL; 2900 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2901 if (itd == NULL) 2902 break; 2903 if (itd->slot != frindex && itd->slot != previndex) { 2904 freeitd = itd; 2905 break; 2906 } 2907 } 2908 2909 if (freeitd == NULL) { 2910 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2911 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2912 EHCI_PAGE_SIZE, &dma); 2913 2914 if (err) { 2915 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2916 mutex_exit(&sc->sc_lock); 2917 return NULL; 2918 } 2919 2920 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2921 offs = i * EHCI_ITD_SIZE; 2922 itd = KERNADDR(&dma, offs); 2923 itd->physaddr = DMAADDR(&dma, offs); 2924 itd->dma = dma; 2925 itd->offs = offs; 2926 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2927 } 2928 freeitd = LIST_FIRST(&sc->sc_freeitds); 2929 } 2930 2931 itd = freeitd; 2932 LIST_REMOVE(itd, u.free_list); 2933 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2934 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2935 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2936 BUS_DMASYNC_PREREAD); 2937 2938 itd->u.frame_list.next = NULL; 2939 itd->u.frame_list.prev = NULL; 2940 itd->xfer_next = NULL; 2941 itd->slot = 0; 2942 2943 mutex_exit(&sc->sc_lock); 2944 2945 return itd; 2946 } 2947 2948 Static void 2949 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2950 { 2951 2952 KASSERT(mutex_owned(&sc->sc_lock)); 2953 2954 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2955 } 2956 2957 /****************/ 2958 2959 /* 2960 * Close a reqular pipe. 2961 * Assumes that there are no pending transactions. 2962 */ 2963 Static void 2964 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2965 { 2966 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2967 ehci_softc_t *sc = pipe->device->bus->hci_private; 2968 ehci_soft_qh_t *sqh = epipe->sqh; 2969 2970 KASSERT(mutex_owned(&sc->sc_lock)); 2971 2972 ehci_rem_qh(sc, sqh, head); 2973 ehci_free_sqh(sc, epipe->sqh); 2974 } 2975 2976 /* 2977 * Abort a device request. 2978 * If this routine is called at splusb() it guarantees that the request 2979 * will be removed from the hardware scheduling and that the callback 2980 * for it will be called with USBD_CANCELLED status. 2981 * It's impossible to guarantee that the requested transfer will not 2982 * have happened since the hardware runs concurrently. 2983 * If the transaction has already happened we rely on the ordinary 2984 * interrupt processing to process it. 2985 * XXX This is most probably wrong. 2986 * XXXMRG this doesn't make sense anymore. 2987 */ 2988 Static void 2989 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2990 { 2991 #define exfer EXFER(xfer) 2992 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2993 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2994 ehci_soft_qh_t *sqh = epipe->sqh; 2995 ehci_soft_qtd_t *sqtd; 2996 ehci_physaddr_t cur; 2997 u_int32_t qhstatus; 2998 int hit; 2999 int wake; 3000 3001 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 3002 3003 KASSERT(mutex_owned(&sc->sc_lock)); 3004 3005 if (sc->sc_dying) { 3006 /* If we're dying, just do the software part. */ 3007 xfer->status = status; /* make software ignore it */ 3008 callout_stop(&xfer->timeout_handle); 3009 usb_transfer_complete(xfer); 3010 return; 3011 } 3012 3013 if (cpu_intr_p() || cpu_softintr_p()) 3014 panic("ehci_abort_xfer: not in process context"); 3015 3016 /* 3017 * If an abort is already in progress then just wait for it to 3018 * complete and return. 3019 */ 3020 if (xfer->hcflags & UXFER_ABORTING) { 3021 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3022 #ifdef DIAGNOSTIC 3023 if (status == USBD_TIMEOUT) 3024 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3025 #endif 3026 /* Override the status which might be USBD_TIMEOUT. */ 3027 xfer->status = status; 3028 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3029 xfer->hcflags |= UXFER_ABORTWAIT; 3030 while (xfer->hcflags & UXFER_ABORTING) 3031 cv_wait(&xfer->hccv, &sc->sc_lock); 3032 return; 3033 } 3034 xfer->hcflags |= UXFER_ABORTING; 3035 3036 /* 3037 * Step 1: Make interrupt routine and hardware ignore xfer. 3038 */ 3039 xfer->status = status; /* make software ignore it */ 3040 callout_stop(&xfer->timeout_handle); 3041 3042 usb_syncmem(&sqh->dma, 3043 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3044 sizeof(sqh->qh.qh_qtd.qtd_status), 3045 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3046 qhstatus = sqh->qh.qh_qtd.qtd_status; 3047 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3048 usb_syncmem(&sqh->dma, 3049 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3050 sizeof(sqh->qh.qh_qtd.qtd_status), 3051 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3052 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3053 usb_syncmem(&sqtd->dma, 3054 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3055 sizeof(sqtd->qtd.qtd_status), 3056 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3057 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3058 usb_syncmem(&sqtd->dma, 3059 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3060 sizeof(sqtd->qtd.qtd_status), 3061 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3062 if (sqtd == exfer->sqtdend) 3063 break; 3064 } 3065 3066 /* 3067 * Step 2: Wait until we know hardware has finished any possible 3068 * use of the xfer. Also make sure the soft interrupt routine 3069 * has run. 3070 */ 3071 ehci_sync_hc(sc); 3072 sc->sc_softwake = 1; 3073 usb_schedsoftintr(&sc->sc_bus); 3074 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3075 3076 /* 3077 * Step 3: Remove any vestiges of the xfer from the hardware. 3078 * The complication here is that the hardware may have executed 3079 * beyond the xfer we're trying to abort. So as we're scanning 3080 * the TDs of this xfer we check if the hardware points to 3081 * any of them. 3082 */ 3083 3084 usb_syncmem(&sqh->dma, 3085 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3086 sizeof(sqh->qh.qh_curqtd), 3087 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3088 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3089 hit = 0; 3090 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3091 hit |= cur == sqtd->physaddr; 3092 if (sqtd == exfer->sqtdend) 3093 break; 3094 } 3095 sqtd = sqtd->nextqtd; 3096 /* Zap curqtd register if hardware pointed inside the xfer. */ 3097 if (hit && sqtd != NULL) { 3098 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3099 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3100 usb_syncmem(&sqh->dma, 3101 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3102 sizeof(sqh->qh.qh_curqtd), 3103 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3104 sqh->qh.qh_qtd.qtd_status = qhstatus; 3105 usb_syncmem(&sqh->dma, 3106 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3107 sizeof(sqh->qh.qh_qtd.qtd_status), 3108 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3109 } else { 3110 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3111 } 3112 3113 /* 3114 * Step 4: Execute callback. 3115 */ 3116 #ifdef DIAGNOSTIC 3117 exfer->isdone = 1; 3118 #endif 3119 wake = xfer->hcflags & UXFER_ABORTWAIT; 3120 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3121 usb_transfer_complete(xfer); 3122 if (wake) { 3123 cv_broadcast(&xfer->hccv); 3124 } 3125 3126 KASSERT(mutex_owned(&sc->sc_lock)); 3127 #undef exfer 3128 } 3129 3130 Static void 3131 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3132 { 3133 ehci_isoc_trans_t trans_status; 3134 struct ehci_pipe *epipe; 3135 struct ehci_xfer *exfer; 3136 ehci_softc_t *sc; 3137 struct ehci_soft_itd *itd; 3138 int i, wake; 3139 3140 epipe = (struct ehci_pipe *) xfer->pipe; 3141 exfer = EXFER(xfer); 3142 sc = epipe->pipe.device->bus->hci_private; 3143 3144 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3145 3146 KASSERT(mutex_owned(&sc->sc_lock)); 3147 3148 if (sc->sc_dying) { 3149 xfer->status = status; 3150 callout_stop(&xfer->timeout_handle); 3151 usb_transfer_complete(xfer); 3152 return; 3153 } 3154 3155 if (xfer->hcflags & UXFER_ABORTING) { 3156 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3157 3158 #ifdef DIAGNOSTIC 3159 if (status == USBD_TIMEOUT) 3160 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3161 #endif 3162 3163 xfer->status = status; 3164 DPRINTFN(2, ("ehci_abort_isoc_xfer: waiting for abort to finish\n")); 3165 xfer->hcflags |= UXFER_ABORTWAIT; 3166 while (xfer->hcflags & UXFER_ABORTING) 3167 cv_wait(&xfer->hccv, &sc->sc_lock); 3168 goto done; 3169 } 3170 xfer->hcflags |= UXFER_ABORTING; 3171 3172 xfer->status = status; 3173 callout_stop(&xfer->timeout_handle); 3174 3175 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3176 usb_syncmem(&itd->dma, 3177 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3178 sizeof(itd->itd.itd_ctl), 3179 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3180 3181 for (i = 0; i < 8; i++) { 3182 trans_status = le32toh(itd->itd.itd_ctl[i]); 3183 trans_status &= ~EHCI_ITD_ACTIVE; 3184 itd->itd.itd_ctl[i] = htole32(trans_status); 3185 } 3186 3187 usb_syncmem(&itd->dma, 3188 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3189 sizeof(itd->itd.itd_ctl), 3190 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3191 } 3192 3193 sc->sc_softwake = 1; 3194 usb_schedsoftintr(&sc->sc_bus); 3195 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3196 3197 #ifdef DIAGNOSTIC 3198 exfer->isdone = 1; 3199 #endif 3200 wake = xfer->hcflags & UXFER_ABORTWAIT; 3201 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3202 usb_transfer_complete(xfer); 3203 if (wake) { 3204 cv_broadcast(&xfer->hccv); 3205 } 3206 3207 done: 3208 KASSERT(mutex_owned(&sc->sc_lock)); 3209 return; 3210 } 3211 3212 Static void 3213 ehci_timeout(void *addr) 3214 { 3215 struct ehci_xfer *exfer = addr; 3216 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3217 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3218 3219 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3220 #ifdef EHCI_DEBUG 3221 if (ehcidebug > 1) 3222 usbd_dump_pipe(exfer->xfer.pipe); 3223 #endif 3224 3225 if (sc->sc_dying) { 3226 mutex_enter(&sc->sc_lock); 3227 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3228 mutex_exit(&sc->sc_lock); 3229 return; 3230 } 3231 3232 /* Execute the abort in a process context. */ 3233 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3234 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3235 USB_TASKQ_HC); 3236 } 3237 3238 Static void 3239 ehci_timeout_task(void *addr) 3240 { 3241 usbd_xfer_handle xfer = addr; 3242 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3243 3244 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3245 3246 mutex_enter(&sc->sc_lock); 3247 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3248 mutex_exit(&sc->sc_lock); 3249 } 3250 3251 /************************/ 3252 3253 Static usbd_status 3254 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3255 { 3256 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3257 usbd_status err; 3258 3259 /* Insert last in queue. */ 3260 mutex_enter(&sc->sc_lock); 3261 err = usb_insert_transfer(xfer); 3262 mutex_exit(&sc->sc_lock); 3263 if (err) 3264 return (err); 3265 3266 /* Pipe isn't running, start first */ 3267 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3268 } 3269 3270 Static usbd_status 3271 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3272 { 3273 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3274 usbd_status err; 3275 3276 if (sc->sc_dying) 3277 return (USBD_IOERROR); 3278 3279 #ifdef DIAGNOSTIC 3280 if (!(xfer->rqflags & URQ_REQUEST)) { 3281 /* XXX panic */ 3282 printf("ehci_device_ctrl_transfer: not a request\n"); 3283 return (USBD_INVAL); 3284 } 3285 #endif 3286 3287 err = ehci_device_request(xfer); 3288 if (err) { 3289 return (err); 3290 } 3291 3292 if (sc->sc_bus.use_polling) 3293 ehci_waitintr(sc, xfer); 3294 3295 return (USBD_IN_PROGRESS); 3296 } 3297 3298 Static void 3299 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3300 { 3301 struct ehci_xfer *ex = EXFER(xfer); 3302 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3303 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3304 usb_device_request_t *req = &xfer->request; 3305 int len = UGETW(req->wLength); 3306 int rd = req->bmRequestType & UT_READ; 3307 3308 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3309 3310 KASSERT(mutex_owned(&sc->sc_lock)); 3311 3312 #ifdef DIAGNOSTIC 3313 if (!(xfer->rqflags & URQ_REQUEST)) { 3314 panic("ehci_ctrl_done: not a request"); 3315 } 3316 #endif 3317 3318 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3319 ehci_del_intr_list(sc, ex); /* remove from active list */ 3320 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3321 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3322 BUS_DMASYNC_POSTWRITE); 3323 if (len) 3324 usb_syncmem(&xfer->dmabuf, 0, len, 3325 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3326 } 3327 3328 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3329 } 3330 3331 /* Abort a device control request. */ 3332 Static void 3333 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3334 { 3335 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3336 ehci_abort_xfer(xfer, USBD_CANCELLED); 3337 } 3338 3339 /* Close a device control pipe. */ 3340 Static void 3341 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3342 { 3343 ehci_softc_t *sc = pipe->device->bus->hci_private; 3344 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3345 3346 KASSERT(mutex_owned(&sc->sc_lock)); 3347 3348 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3349 3350 ehci_close_pipe(pipe, sc->sc_async_head); 3351 } 3352 3353 Static usbd_status 3354 ehci_device_request(usbd_xfer_handle xfer) 3355 { 3356 #define exfer EXFER(xfer) 3357 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3358 usb_device_request_t *req = &xfer->request; 3359 usbd_device_handle dev = epipe->pipe.device; 3360 ehci_softc_t *sc = dev->bus->hci_private; 3361 int addr = dev->address; 3362 ehci_soft_qtd_t *setup, *stat, *next; 3363 ehci_soft_qh_t *sqh; 3364 int isread; 3365 int len; 3366 usbd_status err; 3367 3368 isread = req->bmRequestType & UT_READ; 3369 len = UGETW(req->wLength); 3370 3371 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3372 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3373 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3374 UGETW(req->wIndex), len, addr, 3375 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3376 3377 setup = ehci_alloc_sqtd(sc); 3378 if (setup == NULL) { 3379 err = USBD_NOMEM; 3380 goto bad1; 3381 } 3382 stat = ehci_alloc_sqtd(sc); 3383 if (stat == NULL) { 3384 err = USBD_NOMEM; 3385 goto bad2; 3386 } 3387 3388 mutex_enter(&sc->sc_lock); 3389 3390 sqh = epipe->sqh; 3391 epipe->u.ctl.length = len; 3392 3393 /* 3394 * Update device address and length since they may have changed 3395 * during the setup of the control pipe in usbd_new_device(). 3396 */ 3397 /* XXX This only needs to be done once, but it's too early in open. */ 3398 /* XXXX Should not touch ED here! */ 3399 sqh->qh.qh_endp = 3400 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3401 htole32( 3402 EHCI_QH_SET_ADDR(addr) | 3403 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3404 ); 3405 3406 /* Set up data transaction */ 3407 if (len != 0) { 3408 ehci_soft_qtd_t *end; 3409 3410 /* Start toggle at 1. */ 3411 epipe->nexttoggle = 1; 3412 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3413 &next, &end); 3414 if (err) 3415 goto bad3; 3416 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3417 end->nextqtd = stat; 3418 end->qtd.qtd_next = 3419 end->qtd.qtd_altnext = htole32(stat->physaddr); 3420 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3421 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3422 } else { 3423 next = stat; 3424 } 3425 3426 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3427 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3428 3429 /* Clear toggle */ 3430 setup->qtd.qtd_status = htole32( 3431 EHCI_QTD_ACTIVE | 3432 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3433 EHCI_QTD_SET_CERR(3) | 3434 EHCI_QTD_SET_TOGGLE(0) | 3435 EHCI_QTD_SET_BYTES(sizeof *req) 3436 ); 3437 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3438 setup->qtd.qtd_buffer_hi[0] = 0; 3439 setup->nextqtd = next; 3440 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3441 setup->xfer = xfer; 3442 setup->len = sizeof *req; 3443 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3444 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3445 3446 stat->qtd.qtd_status = htole32( 3447 EHCI_QTD_ACTIVE | 3448 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3449 EHCI_QTD_SET_CERR(3) | 3450 EHCI_QTD_SET_TOGGLE(1) | 3451 EHCI_QTD_IOC 3452 ); 3453 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3454 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3455 stat->nextqtd = NULL; 3456 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3457 stat->xfer = xfer; 3458 stat->len = 0; 3459 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3460 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3461 3462 #ifdef EHCI_DEBUG 3463 if (ehcidebug > 5) { 3464 DPRINTF(("ehci_device_request:\n")); 3465 ehci_dump_sqh(sqh); 3466 ehci_dump_sqtds(setup); 3467 } 3468 #endif 3469 3470 exfer->sqtdstart = setup; 3471 exfer->sqtdend = stat; 3472 #ifdef DIAGNOSTIC 3473 if (!exfer->isdone) { 3474 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3475 } 3476 exfer->isdone = 0; 3477 #endif 3478 3479 /* Insert qTD in QH list. */ 3480 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3481 if (xfer->timeout && !sc->sc_bus.use_polling) { 3482 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3483 ehci_timeout, xfer); 3484 } 3485 ehci_add_intr_list(sc, exfer); 3486 xfer->status = USBD_IN_PROGRESS; 3487 mutex_exit(&sc->sc_lock); 3488 3489 #ifdef EHCI_DEBUG 3490 if (ehcidebug > 10) { 3491 DPRINTF(("ehci_device_request: status=%x\n", 3492 EOREAD4(sc, EHCI_USBSTS))); 3493 delay(10000); 3494 ehci_dump_regs(sc); 3495 ehci_dump_sqh(sc->sc_async_head); 3496 ehci_dump_sqh(sqh); 3497 ehci_dump_sqtds(setup); 3498 } 3499 #endif 3500 3501 return (USBD_NORMAL_COMPLETION); 3502 3503 bad3: 3504 mutex_exit(&sc->sc_lock); 3505 ehci_free_sqtd(sc, stat); 3506 bad2: 3507 ehci_free_sqtd(sc, setup); 3508 bad1: 3509 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3510 mutex_enter(&sc->sc_lock); 3511 xfer->status = err; 3512 usb_transfer_complete(xfer); 3513 mutex_exit(&sc->sc_lock); 3514 return (err); 3515 #undef exfer 3516 } 3517 3518 /* 3519 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3520 * qTD status, or miss signalling occasionally under heavy load. If the host 3521 * machine is too fast, we we can miss transaction completion - when we scan 3522 * the active list the transaction still seems to be active. This generally 3523 * exhibits itself as a umass stall that never recovers. 3524 * 3525 * We work around this behaviour by setting up this callback after any softintr 3526 * that completes with transactions still pending, giving us another chance to 3527 * check for completion after the writeback has taken place. 3528 */ 3529 Static void 3530 ehci_intrlist_timeout(void *arg) 3531 { 3532 ehci_softc_t *sc = arg; 3533 3534 DPRINTF(("ehci_intrlist_timeout\n")); 3535 usb_schedsoftintr(&sc->sc_bus); 3536 } 3537 3538 /************************/ 3539 3540 Static usbd_status 3541 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3542 { 3543 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3544 usbd_status err; 3545 3546 /* Insert last in queue. */ 3547 mutex_enter(&sc->sc_lock); 3548 err = usb_insert_transfer(xfer); 3549 mutex_exit(&sc->sc_lock); 3550 if (err) 3551 return (err); 3552 3553 /* Pipe isn't running, start first */ 3554 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3555 } 3556 3557 Static usbd_status 3558 ehci_device_bulk_start(usbd_xfer_handle xfer) 3559 { 3560 #define exfer EXFER(xfer) 3561 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3562 usbd_device_handle dev = epipe->pipe.device; 3563 ehci_softc_t *sc = dev->bus->hci_private; 3564 ehci_soft_qtd_t *data, *dataend; 3565 ehci_soft_qh_t *sqh; 3566 usbd_status err; 3567 int len, isread, endpt; 3568 3569 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3570 xfer, xfer->length, xfer->flags)); 3571 3572 if (sc->sc_dying) 3573 return (USBD_IOERROR); 3574 3575 #ifdef DIAGNOSTIC 3576 if (xfer->rqflags & URQ_REQUEST) 3577 panic("ehci_device_bulk_start: a request"); 3578 #endif 3579 3580 mutex_enter(&sc->sc_lock); 3581 3582 len = xfer->length; 3583 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3584 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3585 sqh = epipe->sqh; 3586 3587 epipe->u.bulk.length = len; 3588 3589 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3590 &dataend); 3591 if (err) { 3592 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3593 xfer->status = err; 3594 usb_transfer_complete(xfer); 3595 mutex_exit(&sc->sc_lock); 3596 return (err); 3597 } 3598 3599 #ifdef EHCI_DEBUG 3600 if (ehcidebug > 5) { 3601 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3602 ehci_dump_sqh(sqh); 3603 ehci_dump_sqtds(data); 3604 } 3605 #endif 3606 3607 /* Set up interrupt info. */ 3608 exfer->sqtdstart = data; 3609 exfer->sqtdend = dataend; 3610 #ifdef DIAGNOSTIC 3611 if (!exfer->isdone) { 3612 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3613 } 3614 exfer->isdone = 0; 3615 #endif 3616 3617 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3618 if (xfer->timeout && !sc->sc_bus.use_polling) { 3619 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3620 ehci_timeout, xfer); 3621 } 3622 ehci_add_intr_list(sc, exfer); 3623 xfer->status = USBD_IN_PROGRESS; 3624 mutex_exit(&sc->sc_lock); 3625 3626 #ifdef EHCI_DEBUG 3627 if (ehcidebug > 10) { 3628 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3629 delay(10000); 3630 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3631 ehci_dump_regs(sc); 3632 #if 0 3633 printf("async_head:\n"); 3634 ehci_dump_sqh(sc->sc_async_head); 3635 #endif 3636 printf("sqh:\n"); 3637 ehci_dump_sqh(sqh); 3638 ehci_dump_sqtds(data); 3639 } 3640 #endif 3641 3642 if (sc->sc_bus.use_polling) 3643 ehci_waitintr(sc, xfer); 3644 3645 return (USBD_IN_PROGRESS); 3646 #undef exfer 3647 } 3648 3649 Static void 3650 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3651 { 3652 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3653 ehci_abort_xfer(xfer, USBD_CANCELLED); 3654 } 3655 3656 /* 3657 * Close a device bulk pipe. 3658 */ 3659 Static void 3660 ehci_device_bulk_close(usbd_pipe_handle pipe) 3661 { 3662 ehci_softc_t *sc = pipe->device->bus->hci_private; 3663 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3664 3665 KASSERT(mutex_owned(&sc->sc_lock)); 3666 3667 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3668 pipe->endpoint->datatoggle = epipe->nexttoggle; 3669 ehci_close_pipe(pipe, sc->sc_async_head); 3670 } 3671 3672 Static void 3673 ehci_device_bulk_done(usbd_xfer_handle xfer) 3674 { 3675 struct ehci_xfer *ex = EXFER(xfer); 3676 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3677 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3678 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3679 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3680 3681 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3682 xfer, xfer->actlen)); 3683 3684 KASSERT(mutex_owned(&sc->sc_lock)); 3685 3686 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3687 ehci_del_intr_list(sc, ex); /* remove from active list */ 3688 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3689 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3690 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3691 } 3692 3693 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3694 } 3695 3696 /************************/ 3697 3698 Static usbd_status 3699 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3700 { 3701 struct ehci_soft_islot *isp; 3702 int islot, lev; 3703 3704 /* Find a poll rate that is large enough. */ 3705 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3706 if (EHCI_ILEV_IVAL(lev) <= ival) 3707 break; 3708 3709 /* Pick an interrupt slot at the right level. */ 3710 /* XXX could do better than picking at random */ 3711 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3712 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3713 3714 sqh->islot = islot; 3715 isp = &sc->sc_islots[islot]; 3716 mutex_enter(&sc->sc_lock); 3717 ehci_add_qh(sc, sqh, isp->sqh); 3718 mutex_exit(&sc->sc_lock); 3719 3720 return (USBD_NORMAL_COMPLETION); 3721 } 3722 3723 Static usbd_status 3724 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3725 { 3726 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3727 usbd_status err; 3728 3729 /* Insert last in queue. */ 3730 mutex_enter(&sc->sc_lock); 3731 err = usb_insert_transfer(xfer); 3732 mutex_exit(&sc->sc_lock); 3733 if (err) 3734 return (err); 3735 3736 /* 3737 * Pipe isn't running (otherwise err would be USBD_INPROG), 3738 * so start it first. 3739 */ 3740 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3741 } 3742 3743 Static usbd_status 3744 ehci_device_intr_start(usbd_xfer_handle xfer) 3745 { 3746 #define exfer EXFER(xfer) 3747 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3748 usbd_device_handle dev = xfer->pipe->device; 3749 ehci_softc_t *sc = dev->bus->hci_private; 3750 ehci_soft_qtd_t *data, *dataend; 3751 ehci_soft_qh_t *sqh; 3752 usbd_status err; 3753 int len, isread, endpt; 3754 3755 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3756 xfer, xfer->length, xfer->flags)); 3757 3758 if (sc->sc_dying) 3759 return (USBD_IOERROR); 3760 3761 #ifdef DIAGNOSTIC 3762 if (xfer->rqflags & URQ_REQUEST) 3763 panic("ehci_device_intr_start: a request"); 3764 #endif 3765 3766 mutex_enter(&sc->sc_lock); 3767 3768 len = xfer->length; 3769 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3770 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3771 sqh = epipe->sqh; 3772 3773 epipe->u.intr.length = len; 3774 3775 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3776 &dataend); 3777 if (err) { 3778 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3779 xfer->status = err; 3780 usb_transfer_complete(xfer); 3781 mutex_exit(&sc->sc_lock); 3782 return (err); 3783 } 3784 3785 #ifdef EHCI_DEBUG 3786 if (ehcidebug > 5) { 3787 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3788 ehci_dump_sqh(sqh); 3789 ehci_dump_sqtds(data); 3790 } 3791 #endif 3792 3793 /* Set up interrupt info. */ 3794 exfer->sqtdstart = data; 3795 exfer->sqtdend = dataend; 3796 #ifdef DIAGNOSTIC 3797 if (!exfer->isdone) { 3798 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3799 } 3800 exfer->isdone = 0; 3801 #endif 3802 3803 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3804 if (xfer->timeout && !sc->sc_bus.use_polling) { 3805 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3806 ehci_timeout, xfer); 3807 } 3808 ehci_add_intr_list(sc, exfer); 3809 xfer->status = USBD_IN_PROGRESS; 3810 mutex_exit(&sc->sc_lock); 3811 3812 #ifdef EHCI_DEBUG 3813 if (ehcidebug > 10) { 3814 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3815 delay(10000); 3816 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3817 ehci_dump_regs(sc); 3818 printf("sqh:\n"); 3819 ehci_dump_sqh(sqh); 3820 ehci_dump_sqtds(data); 3821 } 3822 #endif 3823 3824 if (sc->sc_bus.use_polling) 3825 ehci_waitintr(sc, xfer); 3826 3827 return (USBD_IN_PROGRESS); 3828 #undef exfer 3829 } 3830 3831 Static void 3832 ehci_device_intr_abort(usbd_xfer_handle xfer) 3833 { 3834 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3835 if (xfer->pipe->intrxfer == xfer) { 3836 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3837 xfer->pipe->intrxfer = NULL; 3838 } 3839 /* 3840 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3841 * async doorbell. That's dependent on the async list, wheras 3842 * intr xfers are periodic, should not use this? 3843 */ 3844 ehci_abort_xfer(xfer, USBD_CANCELLED); 3845 } 3846 3847 Static void 3848 ehci_device_intr_close(usbd_pipe_handle pipe) 3849 { 3850 ehci_softc_t *sc = pipe->device->bus->hci_private; 3851 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3852 struct ehci_soft_islot *isp; 3853 3854 KASSERT(mutex_owned(&sc->sc_lock)); 3855 3856 isp = &sc->sc_islots[epipe->sqh->islot]; 3857 ehci_close_pipe(pipe, isp->sqh); 3858 } 3859 3860 Static void 3861 ehci_device_intr_done(usbd_xfer_handle xfer) 3862 { 3863 #define exfer EXFER(xfer) 3864 struct ehci_xfer *ex = EXFER(xfer); 3865 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3866 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3867 ehci_soft_qtd_t *data, *dataend; 3868 ehci_soft_qh_t *sqh; 3869 usbd_status err; 3870 int len, isread, endpt; 3871 3872 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3873 xfer, xfer->actlen)); 3874 3875 KASSERT(mutex_owned(&sc->sc_lock)); 3876 3877 if (xfer->pipe->repeat) { 3878 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3879 3880 len = epipe->u.intr.length; 3881 xfer->length = len; 3882 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3883 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3884 usb_syncmem(&xfer->dmabuf, 0, len, 3885 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3886 sqh = epipe->sqh; 3887 3888 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3889 &data, &dataend); 3890 if (err) { 3891 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3892 xfer->status = err; 3893 return; 3894 } 3895 3896 /* Set up interrupt info. */ 3897 exfer->sqtdstart = data; 3898 exfer->sqtdend = dataend; 3899 #ifdef DIAGNOSTIC 3900 if (!exfer->isdone) { 3901 printf("ehci_device_intr_done: not done, ex=%p\n", 3902 exfer); 3903 } 3904 exfer->isdone = 0; 3905 #endif 3906 3907 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3908 if (xfer->timeout && !sc->sc_bus.use_polling) { 3909 callout_reset(&xfer->timeout_handle, 3910 mstohz(xfer->timeout), ehci_timeout, xfer); 3911 } 3912 3913 xfer->status = USBD_IN_PROGRESS; 3914 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3915 ehci_del_intr_list(sc, ex); /* remove from active list */ 3916 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3917 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3918 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3919 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3920 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3921 } 3922 #undef exfer 3923 } 3924 3925 /************************/ 3926 3927 Static usbd_status 3928 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3929 { 3930 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3931 usbd_status err; 3932 3933 mutex_enter(&sc->sc_lock); 3934 err = usb_insert_transfer(xfer); 3935 mutex_exit(&sc->sc_lock); 3936 if (err && err != USBD_IN_PROGRESS) 3937 return err; 3938 3939 return ehci_device_isoc_start(xfer); 3940 } 3941 3942 Static usbd_status 3943 ehci_device_isoc_start(usbd_xfer_handle xfer) 3944 { 3945 struct ehci_pipe *epipe; 3946 usbd_device_handle dev; 3947 ehci_softc_t *sc; 3948 struct ehci_xfer *exfer; 3949 ehci_soft_itd_t *itd, *prev, *start, *stop; 3950 usb_dma_t *dma_buf; 3951 int i, j, k, frames, uframes, ufrperframe; 3952 int trans_count, offs, total_length; 3953 int frindex; 3954 3955 start = NULL; 3956 prev = NULL; 3957 itd = NULL; 3958 trans_count = 0; 3959 total_length = 0; 3960 exfer = (struct ehci_xfer *) xfer; 3961 sc = xfer->pipe->device->bus->hci_private; 3962 dev = xfer->pipe->device; 3963 epipe = (struct ehci_pipe *)xfer->pipe; 3964 3965 /* 3966 * To allow continuous transfers, above we start all transfers 3967 * immediately. However, we're still going to get usbd_start_next call 3968 * this when another xfer completes. So, check if this is already 3969 * in progress or not 3970 */ 3971 3972 if (exfer->itdstart != NULL) 3973 return USBD_IN_PROGRESS; 3974 3975 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3976 xfer, xfer->length, xfer->flags)); 3977 3978 if (sc->sc_dying) 3979 return USBD_IOERROR; 3980 3981 /* 3982 * To avoid complication, don't allow a request right now that'll span 3983 * the entire frame table. To within 4 frames, to allow some leeway 3984 * on either side of where the hc currently is. 3985 */ 3986 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3987 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3988 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3989 return USBD_INVAL; 3990 } 3991 3992 #ifdef DIAGNOSTIC 3993 if (xfer->rqflags & URQ_REQUEST) 3994 panic("ehci_device_isoc_start: request\n"); 3995 3996 if (!exfer->isdone) 3997 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3998 exfer->isdone = 0; 3999 #endif 4000 4001 /* 4002 * Step 1: Allocate and initialize itds, how many do we need? 4003 * One per transfer if interval >= 8 microframes, fewer if we use 4004 * multiple microframes per frame. 4005 */ 4006 4007 i = epipe->pipe.endpoint->edesc->bInterval; 4008 if (i > 16 || i == 0) { 4009 /* Spec page 271 says intervals > 16 are invalid */ 4010 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 4011 return USBD_INVAL; 4012 } 4013 4014 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4015 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4016 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4017 4018 if (frames == 0) { 4019 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 4020 return USBD_INVAL; 4021 } 4022 4023 dma_buf = &xfer->dmabuf; 4024 offs = 0; 4025 4026 for (i = 0; i < frames; i++) { 4027 int froffs = offs; 4028 itd = ehci_alloc_itd(sc); 4029 4030 if (prev != NULL) { 4031 prev->itd.itd_next = 4032 htole32(itd->physaddr | EHCI_LINK_ITD); 4033 usb_syncmem(&itd->dma, 4034 itd->offs + offsetof(ehci_itd_t, itd_next), 4035 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4036 4037 prev->xfer_next = itd; 4038 } else { 4039 start = itd; 4040 } 4041 4042 /* 4043 * Step 1.5, initialize uframes 4044 */ 4045 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4046 /* Calculate which page in the list this starts in */ 4047 int addr = DMAADDR(dma_buf, froffs); 4048 addr = EHCI_PAGE_OFFSET(addr); 4049 addr += (offs - froffs); 4050 addr = EHCI_PAGE(addr); 4051 addr /= EHCI_PAGE_SIZE; 4052 4053 /* This gets the initial offset into the first page, 4054 * looks how far further along the current uframe 4055 * offset is. Works out how many pages that is. 4056 */ 4057 4058 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4059 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4060 EHCI_ITD_SET_PG(addr) | 4061 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4062 4063 total_length += xfer->frlengths[trans_count]; 4064 offs += xfer->frlengths[trans_count]; 4065 trans_count++; 4066 4067 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4068 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4069 break; 4070 } 4071 } 4072 4073 /* Step 1.75, set buffer pointers. To simplify matters, all 4074 * pointers are filled out for the next 7 hardware pages in 4075 * the dma block, so no need to worry what pages to cover 4076 * and what to not. 4077 */ 4078 4079 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4080 /* 4081 * Don't try to lookup a page that's past the end 4082 * of buffer 4083 */ 4084 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4085 if (page_offs >= dma_buf->block->size) 4086 break; 4087 4088 unsigned long long page = DMAADDR(dma_buf, page_offs); 4089 page = EHCI_PAGE(page); 4090 itd->itd.itd_bufr[j] = 4091 htole32(EHCI_ITD_SET_BPTR(page)); 4092 itd->itd.itd_bufr_hi[j] = 4093 htole32(page >> 32); 4094 } 4095 4096 /* 4097 * Other special values 4098 */ 4099 4100 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4101 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4102 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4103 4104 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4105 ? 1 : 0; 4106 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4107 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4108 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4109 4110 /* FIXME: handle invalid trans */ 4111 itd->itd.itd_bufr[2] |= 4112 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4113 4114 usb_syncmem(&itd->dma, 4115 itd->offs + offsetof(ehci_itd_t, itd_next), 4116 sizeof(ehci_itd_t), 4117 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4118 4119 prev = itd; 4120 } /* End of frame */ 4121 4122 stop = itd; 4123 stop->xfer_next = NULL; 4124 exfer->isoc_len = total_length; 4125 4126 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4127 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4128 4129 /* 4130 * Part 2: Transfer descriptors have now been set up, now they must 4131 * be scheduled into the period frame list. Erk. Not wanting to 4132 * complicate matters, transfer is denied if the transfer spans 4133 * more than the period frame list. 4134 */ 4135 4136 mutex_enter(&sc->sc_lock); 4137 4138 /* Start inserting frames */ 4139 if (epipe->u.isoc.cur_xfers > 0) { 4140 frindex = epipe->u.isoc.next_frame; 4141 } else { 4142 frindex = EOREAD4(sc, EHCI_FRINDEX); 4143 frindex = frindex >> 3; /* Erase microframe index */ 4144 frindex += 2; 4145 } 4146 4147 if (frindex >= sc->sc_flsize) 4148 frindex &= (sc->sc_flsize - 1); 4149 4150 /* What's the frame interval? */ 4151 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4152 if (i / USB_UFRAMES_PER_FRAME == 0) 4153 i = 1; 4154 else 4155 i /= USB_UFRAMES_PER_FRAME; 4156 4157 itd = start; 4158 for (j = 0; j < frames; j++) { 4159 if (itd == NULL) 4160 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4161 4162 itd->itd.itd_next = sc->sc_flist[frindex]; 4163 if (itd->itd.itd_next == 0) 4164 /* FIXME: frindex table gets initialized to NULL 4165 * or EHCI_NULL? */ 4166 itd->itd.itd_next = EHCI_NULL; 4167 4168 usb_syncmem(&itd->dma, 4169 itd->offs + offsetof(ehci_itd_t, itd_next), 4170 sizeof(itd->itd.itd_next), 4171 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4172 4173 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4174 4175 usb_syncmem(&sc->sc_fldma, 4176 sizeof(ehci_link_t) * frindex, 4177 sizeof(ehci_link_t), 4178 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4179 4180 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4181 sc->sc_softitds[frindex] = itd; 4182 if (itd->u.frame_list.next != NULL) 4183 itd->u.frame_list.next->u.frame_list.prev = itd; 4184 itd->slot = frindex; 4185 itd->u.frame_list.prev = NULL; 4186 4187 frindex += i; 4188 if (frindex >= sc->sc_flsize) 4189 frindex -= sc->sc_flsize; 4190 4191 itd = itd->xfer_next; 4192 } 4193 4194 epipe->u.isoc.cur_xfers++; 4195 epipe->u.isoc.next_frame = frindex; 4196 4197 exfer->itdstart = start; 4198 exfer->itdend = stop; 4199 exfer->sqtdstart = NULL; 4200 exfer->sqtdstart = NULL; 4201 4202 ehci_add_intr_list(sc, exfer); 4203 xfer->status = USBD_IN_PROGRESS; 4204 xfer->done = 0; 4205 mutex_exit(&sc->sc_lock); 4206 4207 if (sc->sc_bus.use_polling) { 4208 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4209 ehci_waitintr(sc, xfer); 4210 } 4211 4212 return USBD_IN_PROGRESS; 4213 } 4214 4215 Static void 4216 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4217 { 4218 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4219 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4220 } 4221 4222 Static void 4223 ehci_device_isoc_close(usbd_pipe_handle pipe) 4224 { 4225 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4226 } 4227 4228 Static void 4229 ehci_device_isoc_done(usbd_xfer_handle xfer) 4230 { 4231 struct ehci_xfer *exfer; 4232 ehci_softc_t *sc; 4233 struct ehci_pipe *epipe; 4234 4235 exfer = EXFER(xfer); 4236 sc = xfer->pipe->device->bus->hci_private; 4237 epipe = (struct ehci_pipe *) xfer->pipe; 4238 4239 KASSERT(mutex_owned(&sc->sc_lock)); 4240 4241 epipe->u.isoc.cur_xfers--; 4242 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4243 ehci_del_intr_list(sc, exfer); 4244 ehci_rem_free_itd_chain(sc, exfer); 4245 } 4246 4247 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4248 BUS_DMASYNC_POSTREAD); 4249 4250 } 4251
Indexes created Tue Sep 23 07:09:52 GMT 2025