ehci.c revision 1.200
1 /* $NetBSD: ehci.c,v 1.200 2013/01/15 04:02:56 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.200 2013/01/15 04:02:56 christos Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/kernel.h> 64 #include <sys/kmem.h> 65 #include <sys/device.h> 66 #include <sys/select.h> 67 #include <sys/proc.h> 68 #include <sys/queue.h> 69 #include <sys/mutex.h> 70 #include <sys/bus.h> 71 #include <sys/cpu.h> 72 73 #include <machine/endian.h> 74 75 #include <dev/usb/usb.h> 76 #include <dev/usb/usbdi.h> 77 #include <dev/usb/usbdivar.h> 78 #include <dev/usb/usb_mem.h> 79 #include <dev/usb/usb_quirks.h> 80 81 #include <dev/usb/ehcireg.h> 82 #include <dev/usb/ehcivar.h> 83 #include <dev/usb/usbroothub_subr.h> 84 85 #ifdef EHCI_DEBUG 86 static void __printflike(1, 2) 87 ehciprintf(const char *fmt, ...) 88 { 89 va_list ap; 90 91 va_start(ap, fmt); 92 vprintf(fmt, ap); 93 va_end(ap); 94 } 95 96 #define DPRINTF(x) do { if (ehcidebug) ehciprintf x; } while(0) 97 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) ehciprintf x; } while (0) 98 int ehcidebug = 0; 99 #else 100 #define DPRINTF(x) 101 #define DPRINTFN(n,x) 102 #endif 103 104 struct ehci_pipe { 105 struct usbd_pipe pipe; 106 int nexttoggle; 107 108 ehci_soft_qh_t *sqh; 109 union { 110 ehci_soft_qtd_t *qtd; 111 /* ehci_soft_itd_t *itd; */ 112 } tail; 113 union { 114 /* Control pipe */ 115 struct { 116 usb_dma_t reqdma; 117 } ctl; 118 /* Interrupt pipe */ 119 struct { 120 u_int length; 121 } intr; 122 /* Bulk pipe */ 123 struct { 124 u_int length; 125 } bulk; 126 /* Iso pipe */ 127 struct { 128 u_int next_frame; 129 u_int cur_xfers; 130 } isoc; 131 } u; 132 }; 133 134 Static usbd_status ehci_open(usbd_pipe_handle); 135 Static void ehci_poll(struct usbd_bus *); 136 Static void ehci_softintr(void *); 137 Static int ehci_intr1(ehci_softc_t *); 138 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 139 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 140 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 141 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 142 Static void ehci_idone(struct ehci_xfer *); 143 Static void ehci_timeout(void *); 144 Static void ehci_timeout_task(void *); 145 Static void ehci_intrlist_timeout(void *); 146 Static void ehci_doorbell(void *); 147 Static void ehci_pcd(void *); 148 149 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 150 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 151 152 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 153 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 154 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 155 156 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 157 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 158 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 159 Static void ehci_root_ctrl_close(usbd_pipe_handle); 160 Static void ehci_root_ctrl_done(usbd_xfer_handle); 161 162 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 163 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 164 Static void ehci_root_intr_abort(usbd_xfer_handle); 165 Static void ehci_root_intr_close(usbd_pipe_handle); 166 Static void ehci_root_intr_done(usbd_xfer_handle); 167 168 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 169 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 170 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 171 Static void ehci_device_ctrl_close(usbd_pipe_handle); 172 Static void ehci_device_ctrl_done(usbd_xfer_handle); 173 174 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 175 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 176 Static void ehci_device_bulk_abort(usbd_xfer_handle); 177 Static void ehci_device_bulk_close(usbd_pipe_handle); 178 Static void ehci_device_bulk_done(usbd_xfer_handle); 179 180 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 181 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 182 Static void ehci_device_intr_abort(usbd_xfer_handle); 183 Static void ehci_device_intr_close(usbd_pipe_handle); 184 Static void ehci_device_intr_done(usbd_xfer_handle); 185 186 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 187 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 188 Static void ehci_device_isoc_abort(usbd_xfer_handle); 189 Static void ehci_device_isoc_close(usbd_pipe_handle); 190 Static void ehci_device_isoc_done(usbd_xfer_handle); 191 192 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 193 Static void ehci_noop(usbd_pipe_handle pipe); 194 195 Static void ehci_disown(ehci_softc_t *, int, int); 196 197 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 198 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 199 200 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 201 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 202 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 203 ehci_softc_t *, int, int, usbd_xfer_handle, 204 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 205 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 206 ehci_soft_qtd_t *); 207 208 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 209 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 210 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 211 struct ehci_xfer *exfer); 212 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 213 usbd_status status); 214 215 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 216 217 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 218 int ival); 219 220 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 221 ehci_soft_qh_t *); 222 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 223 ehci_soft_qh_t *); 224 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 225 Static void ehci_sync_hc(ehci_softc_t *); 226 227 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 228 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 229 230 #ifdef EHCI_DEBUG 231 Static void ehci_dump_regs(ehci_softc_t *); 232 void ehci_dump(void); 233 Static ehci_softc_t *theehci; 234 Static void ehci_dump_link(ehci_link_t, int); 235 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 236 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 237 Static void ehci_dump_qtd(ehci_qtd_t *); 238 Static void ehci_dump_sqh(ehci_soft_qh_t *); 239 #if notyet 240 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 241 Static void ehci_dump_itd(struct ehci_soft_itd *); 242 #endif 243 #ifdef DIAGNOSTIC 244 Static void ehci_dump_exfer(struct ehci_xfer *); 245 #endif 246 #endif 247 248 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 249 250 #define EHCI_INTR_ENDPT 1 251 252 #define ehci_add_intr_list(sc, ex) \ 253 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 254 #define ehci_del_intr_list(sc, ex) \ 255 do { \ 256 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 257 (ex)->inext.tqe_prev = NULL; \ 258 } while (0) 259 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 260 261 Static const struct usbd_bus_methods ehci_bus_methods = { 262 .open_pipe = ehci_open, 263 .soft_intr = ehci_softintr, 264 .do_poll = ehci_poll, 265 .allocm = ehci_allocm, 266 .freem = ehci_freem, 267 .allocx = ehci_allocx, 268 .freex = ehci_freex, 269 .get_lock = ehci_get_lock, 270 }; 271 272 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 273 .transfer = ehci_root_ctrl_transfer, 274 .start = ehci_root_ctrl_start, 275 .abort = ehci_root_ctrl_abort, 276 .close = ehci_root_ctrl_close, 277 .cleartoggle = ehci_noop, 278 .done = ehci_root_ctrl_done, 279 }; 280 281 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 282 .transfer = ehci_root_intr_transfer, 283 .start = ehci_root_intr_start, 284 .abort = ehci_root_intr_abort, 285 .close = ehci_root_intr_close, 286 .cleartoggle = ehci_noop, 287 .done = ehci_root_intr_done, 288 }; 289 290 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 291 .transfer = ehci_device_ctrl_transfer, 292 .start = ehci_device_ctrl_start, 293 .abort = ehci_device_ctrl_abort, 294 .close = ehci_device_ctrl_close, 295 .cleartoggle = ehci_noop, 296 .done = ehci_device_ctrl_done, 297 }; 298 299 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 300 .transfer = ehci_device_intr_transfer, 301 .start = ehci_device_intr_start, 302 .abort = ehci_device_intr_abort, 303 .close = ehci_device_intr_close, 304 .cleartoggle = ehci_device_clear_toggle, 305 .done = ehci_device_intr_done, 306 }; 307 308 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 309 .transfer = ehci_device_bulk_transfer, 310 .start = ehci_device_bulk_start, 311 .abort = ehci_device_bulk_abort, 312 .close = ehci_device_bulk_close, 313 .cleartoggle = ehci_device_clear_toggle, 314 .done = ehci_device_bulk_done, 315 }; 316 317 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 318 .transfer = ehci_device_isoc_transfer, 319 .start = ehci_device_isoc_start, 320 .abort = ehci_device_isoc_abort, 321 .close = ehci_device_isoc_close, 322 .cleartoggle = ehci_noop, 323 .done = ehci_device_isoc_done, 324 }; 325 326 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 327 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 328 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 329 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 330 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 331 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 332 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 333 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 334 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 335 }; 336 337 usbd_status 338 ehci_init(ehci_softc_t *sc) 339 { 340 u_int32_t vers, sparams, cparams, hcr; 341 u_int i; 342 usbd_status err; 343 ehci_soft_qh_t *sqh; 344 u_int ncomp; 345 346 DPRINTF(("ehci_init: start\n")); 347 #ifdef EHCI_DEBUG 348 theehci = sc; 349 #endif 350 351 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 352 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 353 cv_init(&sc->sc_softwake_cv, "ehciab"); 354 cv_init(&sc->sc_doorbell, "ehcidi"); 355 356 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 357 ehci_doorbell, sc); 358 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 359 ehci_pcd, sc); 360 361 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 362 363 vers = EREAD2(sc, EHCI_HCIVERSION); 364 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 365 vers >> 8, vers & 0xff); 366 367 sparams = EREAD4(sc, EHCI_HCSPARAMS); 368 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 369 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 370 ncomp = EHCI_HCS_N_CC(sparams); 371 if (ncomp != sc->sc_ncomp) { 372 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 373 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 374 #if NOHCI == 0 || NUHCI == 0 375 aprint_error("%s: ohci or uhci probably not configured\n", 376 device_xname(sc->sc_dev)); 377 #endif 378 if (ncomp < sc->sc_ncomp) 379 sc->sc_ncomp = ncomp; 380 } 381 if (sc->sc_ncomp > 0) { 382 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 383 aprint_normal("%s: companion controller%s, %d port%s each:", 384 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 385 EHCI_HCS_N_PCC(sparams), 386 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 387 for (i = 0; i < sc->sc_ncomp; i++) 388 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 389 aprint_normal("\n"); 390 } 391 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 392 cparams = EREAD4(sc, EHCI_HCCPARAMS); 393 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 394 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 395 396 if (EHCI_HCC_64BIT(cparams)) { 397 /* MUST clear segment register if 64 bit capable. */ 398 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 399 } 400 401 sc->sc_bus.usbrev = USBREV_2_0; 402 403 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 404 USB_MEM_RESERVE); 405 406 /* Reset the controller */ 407 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 408 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 409 usb_delay_ms(&sc->sc_bus, 1); 410 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 411 for (i = 0; i < 100; i++) { 412 usb_delay_ms(&sc->sc_bus, 1); 413 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 414 if (!hcr) 415 break; 416 } 417 if (hcr) { 418 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 419 return (USBD_IOERROR); 420 } 421 if (sc->sc_vendor_init) 422 sc->sc_vendor_init(sc); 423 424 /* 425 * If we are doing embedded transaction translation function, force 426 * the controller to host mode. 427 */ 428 if (sc->sc_flags & EHCIF_ETTF) { 429 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 430 usbmode &= ~EHCI_USBMODE_CM; 431 usbmode |= EHCI_USBMODE_CM_HOST; 432 EWRITE4(sc, EHCI_USBMODE, usbmode); 433 } 434 435 /* XXX need proper intr scheduling */ 436 sc->sc_rand = 96; 437 438 /* frame list size at default, read back what we got and use that */ 439 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 440 case 0: sc->sc_flsize = 1024; break; 441 case 1: sc->sc_flsize = 512; break; 442 case 2: sc->sc_flsize = 256; break; 443 case 3: return (USBD_IOERROR); 444 } 445 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 446 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 447 if (err) 448 return (err); 449 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 450 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 451 452 for (i = 0; i < sc->sc_flsize; i++) { 453 sc->sc_flist[i] = EHCI_NULL; 454 } 455 456 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 457 458 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 459 KM_SLEEP); 460 if (sc->sc_softitds == NULL) 461 return ENOMEM; 462 LIST_INIT(&sc->sc_freeitds); 463 TAILQ_INIT(&sc->sc_intrhead); 464 465 /* Set up the bus struct. */ 466 sc->sc_bus.methods = &ehci_bus_methods; 467 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 468 469 sc->sc_eintrs = EHCI_NORMAL_INTRS; 470 471 /* 472 * Allocate the interrupt dummy QHs. These are arranged to give poll 473 * intervals that are powers of 2 times 1ms. 474 */ 475 for (i = 0; i < EHCI_INTRQHS; i++) { 476 sqh = ehci_alloc_sqh(sc); 477 if (sqh == NULL) { 478 err = USBD_NOMEM; 479 goto bad1; 480 } 481 sc->sc_islots[i].sqh = sqh; 482 } 483 for (i = 0; i < EHCI_INTRQHS; i++) { 484 sqh = sc->sc_islots[i].sqh; 485 if (i == 0) { 486 /* The last (1ms) QH terminates. */ 487 sqh->qh.qh_link = EHCI_NULL; 488 sqh->next = NULL; 489 } else { 490 /* Otherwise the next QH has half the poll interval */ 491 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 492 sqh->qh.qh_link = htole32(sqh->next->physaddr | 493 EHCI_LINK_QH); 494 } 495 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 496 sqh->qh.qh_curqtd = EHCI_NULL; 497 sqh->next = NULL; 498 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 499 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 500 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 501 sqh->sqtd = NULL; 502 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 503 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 504 } 505 /* Point the frame list at the last level (128ms). */ 506 for (i = 0; i < sc->sc_flsize; i++) { 507 int j; 508 509 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 510 revbits[i & (EHCI_MAX_POLLRATE-1)]; 511 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 512 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 513 i)].sqh->physaddr); 514 } 515 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 516 BUS_DMASYNC_PREWRITE); 517 518 /* Allocate dummy QH that starts the async list. */ 519 sqh = ehci_alloc_sqh(sc); 520 if (sqh == NULL) { 521 err = USBD_NOMEM; 522 goto bad1; 523 } 524 /* Fill the QH */ 525 sqh->qh.qh_endp = 526 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 527 sqh->qh.qh_link = 528 htole32(sqh->physaddr | EHCI_LINK_QH); 529 sqh->qh.qh_curqtd = EHCI_NULL; 530 sqh->next = NULL; 531 /* Fill the overlay qTD */ 532 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 533 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 534 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 535 sqh->sqtd = NULL; 536 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 537 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 538 #ifdef EHCI_DEBUG 539 if (ehcidebug) { 540 ehci_dump_sqh(sqh); 541 } 542 #endif 543 544 /* Point to async list */ 545 sc->sc_async_head = sqh; 546 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 547 548 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 549 550 /* Turn on controller */ 551 EOWRITE4(sc, EHCI_USBCMD, 552 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 553 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 554 EHCI_CMD_ASE | 555 EHCI_CMD_PSE | 556 EHCI_CMD_RS); 557 558 /* Take over port ownership */ 559 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 560 561 for (i = 0; i < 100; i++) { 562 usb_delay_ms(&sc->sc_bus, 1); 563 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 564 if (!hcr) 565 break; 566 } 567 if (hcr) { 568 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 569 return (USBD_IOERROR); 570 } 571 572 /* Enable interrupts */ 573 DPRINTFN(1,("ehci_init: enabling\n")); 574 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 575 576 return (USBD_NORMAL_COMPLETION); 577 578 #if 0 579 bad2: 580 ehci_free_sqh(sc, sc->sc_async_head); 581 #endif 582 bad1: 583 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 584 return (err); 585 } 586 587 int 588 ehci_intr(void *v) 589 { 590 ehci_softc_t *sc = v; 591 int ret = 0; 592 593 if (sc == NULL) 594 return 0; 595 596 mutex_spin_enter(&sc->sc_intr_lock); 597 598 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 599 goto done; 600 601 /* If we get an interrupt while polling, then just ignore it. */ 602 if (sc->sc_bus.use_polling) { 603 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 604 605 if (intrs) 606 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 607 #ifdef DIAGNOSTIC 608 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 609 #endif 610 goto done; 611 } 612 613 ret = ehci_intr1(sc); 614 615 done: 616 mutex_spin_exit(&sc->sc_intr_lock); 617 return ret; 618 } 619 620 Static int 621 ehci_intr1(ehci_softc_t *sc) 622 { 623 u_int32_t intrs, eintrs; 624 625 DPRINTFN(20,("ehci_intr1: enter\n")); 626 627 /* In case the interrupt occurs before initialization has completed. */ 628 if (sc == NULL) { 629 #ifdef DIAGNOSTIC 630 printf("ehci_intr1: sc == NULL\n"); 631 #endif 632 return (0); 633 } 634 635 KASSERT(mutex_owned(&sc->sc_intr_lock)); 636 637 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 638 if (!intrs) 639 return (0); 640 641 eintrs = intrs & sc->sc_eintrs; 642 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 643 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 644 (u_int)eintrs)); 645 if (!eintrs) 646 return (0); 647 648 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 649 sc->sc_bus.no_intrs++; 650 if (eintrs & EHCI_STS_IAA) { 651 DPRINTF(("ehci_intr1: door bell\n")); 652 kpreempt_disable(); 653 softint_schedule(sc->sc_doorbell_si); 654 kpreempt_enable(); 655 eintrs &= ~EHCI_STS_IAA; 656 } 657 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 658 DPRINTFN(5,("ehci_intr1: %s %s\n", 659 eintrs & EHCI_STS_INT ? "INT" : "", 660 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 661 usb_schedsoftintr(&sc->sc_bus); 662 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 663 } 664 if (eintrs & EHCI_STS_HSE) { 665 printf("%s: unrecoverable error, controller halted\n", 666 device_xname(sc->sc_dev)); 667 /* XXX what else */ 668 } 669 if (eintrs & EHCI_STS_PCD) { 670 kpreempt_disable(); 671 softint_schedule(sc->sc_pcd_si); 672 kpreempt_enable(); 673 eintrs &= ~EHCI_STS_PCD; 674 } 675 676 if (eintrs != 0) { 677 /* Block unprocessed interrupts. */ 678 sc->sc_eintrs &= ~eintrs; 679 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 680 printf("%s: blocking intrs 0x%x\n", 681 device_xname(sc->sc_dev), eintrs); 682 } 683 684 return (1); 685 } 686 687 Static void 688 ehci_doorbell(void *addr) 689 { 690 ehci_softc_t *sc = addr; 691 692 mutex_enter(&sc->sc_lock); 693 cv_broadcast(&sc->sc_doorbell); 694 mutex_exit(&sc->sc_lock); 695 } 696 697 Static void 698 ehci_pcd(void *addr) 699 { 700 ehci_softc_t *sc = addr; 701 usbd_xfer_handle xfer; 702 usbd_pipe_handle pipe; 703 u_char *p; 704 int i, m; 705 706 mutex_enter(&sc->sc_lock); 707 xfer = sc->sc_intrxfer; 708 709 if (xfer == NULL) { 710 /* Just ignore the change. */ 711 goto done; 712 } 713 714 pipe = xfer->pipe; 715 716 p = KERNADDR(&xfer->dmabuf, 0); 717 m = min(sc->sc_noport, xfer->length * 8 - 1); 718 memset(p, 0, xfer->length); 719 for (i = 1; i <= m; i++) { 720 /* Pick out CHANGE bits from the status reg. */ 721 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 722 p[i/8] |= 1 << (i%8); 723 } 724 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 725 xfer->actlen = xfer->length; 726 xfer->status = USBD_NORMAL_COMPLETION; 727 728 usb_transfer_complete(xfer); 729 730 done: 731 mutex_exit(&sc->sc_lock); 732 } 733 734 Static void 735 ehci_softintr(void *v) 736 { 737 struct usbd_bus *bus = v; 738 ehci_softc_t *sc = bus->hci_private; 739 struct ehci_xfer *ex, *nextex; 740 741 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 742 743 DPRINTFN(10,("%s: ehci_softintr\n", device_xname(sc->sc_dev))); 744 745 /* 746 * The only explanation I can think of for why EHCI is as brain dead 747 * as UHCI interrupt-wise is that Intel was involved in both. 748 * An interrupt just tells us that something is done, we have no 749 * clue what, so we need to scan through all active transfers. :-( 750 */ 751 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 752 nextex = TAILQ_NEXT(ex, inext); 753 ehci_check_intr(sc, ex); 754 } 755 756 /* Schedule a callout to catch any dropped transactions. */ 757 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 758 !TAILQ_EMPTY(&sc->sc_intrhead)) 759 callout_reset(&sc->sc_tmo_intrlist, 760 hz, ehci_intrlist_timeout, sc); 761 762 if (sc->sc_softwake) { 763 sc->sc_softwake = 0; 764 cv_broadcast(&sc->sc_softwake_cv); 765 } 766 } 767 768 /* Check for an interrupt. */ 769 Static void 770 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 771 { 772 int attr; 773 774 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 775 776 KASSERT(mutex_owned(&sc->sc_lock)); 777 778 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 779 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 780 ehci_check_itd_intr(sc, ex); 781 else 782 ehci_check_qh_intr(sc, ex); 783 784 return; 785 } 786 787 Static void 788 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 789 { 790 ehci_soft_qtd_t *sqtd, *lsqtd; 791 __uint32_t status; 792 793 KASSERT(mutex_owned(&sc->sc_lock)); 794 795 if (ex->sqtdstart == NULL) { 796 printf("ehci_check_qh_intr: not valid sqtd\n"); 797 return; 798 } 799 800 lsqtd = ex->sqtdend; 801 #ifdef DIAGNOSTIC 802 if (lsqtd == NULL) { 803 printf("ehci_check_qh_intr: lsqtd==0\n"); 804 return; 805 } 806 #endif 807 /* 808 * If the last TD is still active we need to check whether there 809 * is a an error somewhere in the middle, or whether there was a 810 * short packet (SPD and not ACTIVE). 811 */ 812 usb_syncmem(&lsqtd->dma, 813 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 814 sizeof(lsqtd->qtd.qtd_status), 815 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 816 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) { 817 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 818 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 819 usb_syncmem(&sqtd->dma, 820 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 821 sizeof(sqtd->qtd.qtd_status), 822 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 823 status = le32toh(sqtd->qtd.qtd_status); 824 usb_syncmem(&sqtd->dma, 825 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 826 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 827 /* If there's an active QTD the xfer isn't done. */ 828 if (status & EHCI_QTD_ACTIVE) 829 break; 830 /* Any kind of error makes the xfer done. */ 831 if (status & EHCI_QTD_HALTED) 832 goto done; 833 /* We want short packets, and it is short: it's done */ 834 if (EHCI_QTD_GET_BYTES(status) != 0) 835 goto done; 836 } 837 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 838 ex, ex->sqtdstart)); 839 usb_syncmem(&lsqtd->dma, 840 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 841 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 842 return; 843 } 844 done: 845 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 846 callout_stop(&ex->xfer.timeout_handle); 847 ehci_idone(ex); 848 } 849 850 Static void 851 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 852 { 853 ehci_soft_itd_t *itd; 854 int i; 855 856 KASSERT(mutex_owned(&sc->sc_lock)); 857 858 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 859 return; 860 861 if (ex->itdstart == NULL) { 862 printf("ehci_check_itd_intr: not valid itd\n"); 863 return; 864 } 865 866 itd = ex->itdend; 867 #ifdef DIAGNOSTIC 868 if (itd == NULL) { 869 printf("ehci_check_itd_intr: itdend == 0\n"); 870 return; 871 } 872 #endif 873 874 /* 875 * check no active transfers in last itd, meaning we're finished 876 */ 877 878 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 879 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 880 BUS_DMASYNC_POSTREAD); 881 882 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 883 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 884 break; 885 } 886 887 if (i == EHCI_ITD_NUFRAMES) { 888 goto done; /* All 8 descriptors inactive, it's done */ 889 } 890 891 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 892 ex->itdstart)); 893 return; 894 done: 895 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 896 callout_stop(&ex->xfer.timeout_handle); 897 ehci_idone(ex); 898 } 899 900 Static void 901 ehci_idone(struct ehci_xfer *ex) 902 { 903 usbd_xfer_handle xfer = &ex->xfer; 904 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 905 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 906 ehci_soft_qtd_t *sqtd, *lsqtd; 907 u_int32_t status = 0, nstatus = 0; 908 int actlen; 909 910 KASSERT(mutex_owned(&sc->sc_lock)); 911 912 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 913 914 #ifdef DIAGNOSTIC 915 { 916 if (ex->isdone) { 917 #ifdef EHCI_DEBUG 918 printf("ehci_idone: ex is done!\n "); 919 ehci_dump_exfer(ex); 920 #else 921 printf("ehci_idone: ex=%p is done!\n", ex); 922 #endif 923 return; 924 } 925 ex->isdone = 1; 926 } 927 #endif 928 if (xfer->status == USBD_CANCELLED || 929 xfer->status == USBD_TIMEOUT) { 930 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 931 return; 932 } 933 934 #ifdef EHCI_DEBUG 935 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 936 if (ehcidebug > 10) 937 ehci_dump_sqtds(ex->sqtdstart); 938 #endif 939 940 /* The transfer is done, compute actual length and status. */ 941 942 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 943 == UE_ISOCHRONOUS) { 944 /* Isoc transfer */ 945 struct ehci_soft_itd *itd; 946 int i, nframes, len, uframes; 947 948 nframes = 0; 949 actlen = 0; 950 951 i = xfer->pipe->endpoint->edesc->bInterval; 952 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 953 954 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 955 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 956 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 957 BUS_DMASYNC_POSTREAD); 958 959 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 960 /* XXX - driver didn't fill in the frame full 961 * of uframes. This leads to scheduling 962 * inefficiencies, but working around 963 * this doubles complexity of tracking 964 * an xfer. 965 */ 966 if (nframes >= xfer->nframes) 967 break; 968 969 status = le32toh(itd->itd.itd_ctl[i]); 970 len = EHCI_ITD_GET_LEN(status); 971 if (EHCI_ITD_GET_STATUS(status) != 0) 972 len = 0; /*No valid data on error*/ 973 974 xfer->frlengths[nframes++] = len; 975 actlen += len; 976 } 977 978 if (nframes >= xfer->nframes) 979 break; 980 } 981 982 xfer->actlen = actlen; 983 xfer->status = USBD_NORMAL_COMPLETION; 984 goto end; 985 } 986 987 /* Continue processing xfers using queue heads */ 988 989 lsqtd = ex->sqtdend; 990 actlen = 0; 991 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 992 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 993 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 994 nstatus = le32toh(sqtd->qtd.qtd_status); 995 if (nstatus & EHCI_QTD_ACTIVE) 996 break; 997 998 status = nstatus; 999 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1000 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1001 } 1002 1003 1004 /* 1005 * If there are left over TDs we need to update the toggle. 1006 * The default pipe doesn't need it since control transfers 1007 * start the toggle at 0 every time. 1008 * For a short transfer we need to update the toggle for the missing 1009 * packets within the qTD. 1010 */ 1011 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1012 xfer->pipe->device->default_pipe != xfer->pipe) { 1013 DPRINTFN(2, ("ehci_idone: need toggle update " 1014 "status=%08x nstatus=%08x\n", status, nstatus)); 1015 #if 0 1016 ehci_dump_sqh(epipe->sqh); 1017 ehci_dump_sqtds(ex->sqtdstart); 1018 #endif 1019 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1020 } 1021 1022 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 1023 xfer->length, actlen, status)); 1024 xfer->actlen = actlen; 1025 if (status & EHCI_QTD_HALTED) { 1026 #ifdef EHCI_DEBUG 1027 char sbuf[128]; 1028 1029 snprintb(sbuf, sizeof(sbuf), 1030 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 1031 (u_int32_t)status); 1032 1033 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 1034 "status 0x%s\n", 1035 xfer->pipe->device->address, 1036 xfer->pipe->endpoint->edesc->bEndpointAddress, 1037 sbuf)); 1038 if (ehcidebug > 2) { 1039 ehci_dump_sqh(epipe->sqh); 1040 ehci_dump_sqtds(ex->sqtdstart); 1041 } 1042 #endif 1043 /* low&full speed has an extra error flag */ 1044 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1045 EHCI_QH_SPEED_HIGH) 1046 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1047 else 1048 status &= EHCI_QTD_STATERRS; 1049 if (status == 0) /* no other errors means a stall */ { 1050 xfer->status = USBD_STALLED; 1051 } else { 1052 xfer->status = USBD_IOERROR; /* more info XXX */ 1053 } 1054 /* XXX need to reset TT on missed microframe */ 1055 if (status & EHCI_QTD_MISSEDMICRO) { 1056 printf("%s: missed microframe, TT reset not " 1057 "implemented, hub might be inoperational\n", 1058 device_xname(sc->sc_dev)); 1059 } 1060 } else { 1061 xfer->status = USBD_NORMAL_COMPLETION; 1062 } 1063 1064 end: 1065 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1066 * during this call, before methods->done is called: dma sync required 1067 * beforehand? */ 1068 usb_transfer_complete(xfer); 1069 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1070 } 1071 1072 /* 1073 * Wait here until controller claims to have an interrupt. 1074 * Then call ehci_intr and return. Use timeout to avoid waiting 1075 * too long. 1076 */ 1077 Static void 1078 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1079 { 1080 int timo; 1081 u_int32_t intrs; 1082 1083 xfer->status = USBD_IN_PROGRESS; 1084 for (timo = xfer->timeout; timo >= 0; timo--) { 1085 usb_delay_ms(&sc->sc_bus, 1); 1086 if (sc->sc_dying) 1087 break; 1088 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1089 sc->sc_eintrs; 1090 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1091 #ifdef EHCI_DEBUG 1092 if (ehcidebug > 15) 1093 ehci_dump_regs(sc); 1094 #endif 1095 if (intrs) { 1096 mutex_spin_enter(&sc->sc_intr_lock); 1097 ehci_intr1(sc); 1098 mutex_spin_exit(&sc->sc_intr_lock); 1099 if (xfer->status != USBD_IN_PROGRESS) 1100 return; 1101 } 1102 } 1103 1104 /* Timeout */ 1105 DPRINTF(("ehci_waitintr: timeout\n")); 1106 xfer->status = USBD_TIMEOUT; 1107 mutex_enter(&sc->sc_lock); 1108 usb_transfer_complete(xfer); 1109 mutex_exit(&sc->sc_lock); 1110 /* XXX should free TD */ 1111 } 1112 1113 Static void 1114 ehci_poll(struct usbd_bus *bus) 1115 { 1116 ehci_softc_t *sc = bus->hci_private; 1117 #ifdef EHCI_DEBUG 1118 static int last; 1119 int new; 1120 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1121 if (new != last) { 1122 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1123 last = new; 1124 } 1125 #endif 1126 1127 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1128 mutex_spin_enter(&sc->sc_intr_lock); 1129 ehci_intr1(sc); 1130 mutex_spin_exit(&sc->sc_intr_lock); 1131 } 1132 } 1133 1134 void 1135 ehci_childdet(device_t self, device_t child) 1136 { 1137 struct ehci_softc *sc = device_private(self); 1138 1139 KASSERT(sc->sc_child == child); 1140 sc->sc_child = NULL; 1141 } 1142 1143 int 1144 ehci_detach(struct ehci_softc *sc, int flags) 1145 { 1146 usbd_xfer_handle xfer; 1147 int rv = 0; 1148 1149 if (sc->sc_child != NULL) 1150 rv = config_detach(sc->sc_child, flags); 1151 1152 if (rv != 0) 1153 return (rv); 1154 1155 callout_halt(&sc->sc_tmo_intrlist, NULL); 1156 callout_destroy(&sc->sc_tmo_intrlist); 1157 1158 /* XXX free other data structures XXX */ 1159 if (sc->sc_softitds) 1160 kmem_free(sc->sc_softitds, 1161 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1162 cv_destroy(&sc->sc_doorbell); 1163 cv_destroy(&sc->sc_softwake_cv); 1164 1165 #if 0 1166 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1167 1168 softint_disestablish(sc->sc_doorbell_si); 1169 softint_disestablish(sc->sc_pcd_si); 1170 1171 mutex_destroy(&sc->sc_lock); 1172 mutex_destroy(&sc->sc_intr_lock); 1173 #endif 1174 1175 while ((xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers)) != NULL) { 1176 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1177 kmem_free(xfer, sizeof(struct ehci_xfer)); 1178 } 1179 1180 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1181 1182 return (rv); 1183 } 1184 1185 1186 int 1187 ehci_activate(device_t self, enum devact act) 1188 { 1189 struct ehci_softc *sc = device_private(self); 1190 1191 switch (act) { 1192 case DVACT_DEACTIVATE: 1193 sc->sc_dying = 1; 1194 return 0; 1195 default: 1196 return EOPNOTSUPP; 1197 } 1198 } 1199 1200 /* 1201 * Handle suspend/resume. 1202 * 1203 * We need to switch to polling mode here, because this routine is 1204 * called from an interrupt context. This is all right since we 1205 * are almost suspended anyway. 1206 * 1207 * Note that this power handler isn't to be registered directly; the 1208 * bus glue needs to call out to it. 1209 */ 1210 bool 1211 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1212 { 1213 ehci_softc_t *sc = device_private(dv); 1214 int i; 1215 uint32_t cmd, hcr; 1216 1217 mutex_spin_enter(&sc->sc_intr_lock); 1218 sc->sc_bus.use_polling++; 1219 mutex_spin_exit(&sc->sc_intr_lock); 1220 1221 for (i = 1; i <= sc->sc_noport; i++) { 1222 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1223 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1224 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1225 } 1226 1227 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1228 1229 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1230 EOWRITE4(sc, EHCI_USBCMD, cmd); 1231 1232 for (i = 0; i < 100; i++) { 1233 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1234 if (hcr == 0) 1235 break; 1236 1237 usb_delay_ms(&sc->sc_bus, 1); 1238 } 1239 if (hcr != 0) 1240 printf("%s: reset timeout\n", device_xname(dv)); 1241 1242 cmd &= ~EHCI_CMD_RS; 1243 EOWRITE4(sc, EHCI_USBCMD, cmd); 1244 1245 for (i = 0; i < 100; i++) { 1246 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1247 if (hcr == EHCI_STS_HCH) 1248 break; 1249 1250 usb_delay_ms(&sc->sc_bus, 1); 1251 } 1252 if (hcr != EHCI_STS_HCH) 1253 printf("%s: config timeout\n", device_xname(dv)); 1254 1255 mutex_spin_enter(&sc->sc_intr_lock); 1256 sc->sc_bus.use_polling--; 1257 mutex_spin_exit(&sc->sc_intr_lock); 1258 1259 return true; 1260 } 1261 1262 bool 1263 ehci_resume(device_t dv, const pmf_qual_t *qual) 1264 { 1265 ehci_softc_t *sc = device_private(dv); 1266 int i; 1267 uint32_t cmd, hcr; 1268 1269 /* restore things in case the bios sucks */ 1270 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1271 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1272 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1273 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1274 1275 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1276 1277 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1278 1279 hcr = 0; 1280 for (i = 1; i <= sc->sc_noport; i++) { 1281 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1282 if ((cmd & EHCI_PS_PO) == 0 && 1283 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1284 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1285 hcr = 1; 1286 } 1287 } 1288 1289 if (hcr) { 1290 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1291 1292 for (i = 1; i <= sc->sc_noport; i++) { 1293 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1294 if ((cmd & EHCI_PS_PO) == 0 && 1295 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1296 EOWRITE4(sc, EHCI_PORTSC(i), 1297 cmd & ~EHCI_PS_FPR); 1298 } 1299 } 1300 1301 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1302 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1303 1304 for (i = 0; i < 100; i++) { 1305 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1306 if (hcr != EHCI_STS_HCH) 1307 break; 1308 1309 usb_delay_ms(&sc->sc_bus, 1); 1310 } 1311 if (hcr == EHCI_STS_HCH) 1312 printf("%s: config timeout\n", device_xname(dv)); 1313 1314 return true; 1315 } 1316 1317 /* 1318 * Shut down the controller when the system is going down. 1319 */ 1320 bool 1321 ehci_shutdown(device_t self, int flags) 1322 { 1323 ehci_softc_t *sc = device_private(self); 1324 1325 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1326 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1327 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1328 return true; 1329 } 1330 1331 Static usbd_status 1332 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1333 { 1334 struct ehci_softc *sc = bus->hci_private; 1335 usbd_status err; 1336 1337 err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, USBMALLOC_MULTISEG); 1338 #ifdef EHCI_DEBUG 1339 if (err) 1340 printf("ehci_allocm: usb_allocmem_flags()= %s (%d)\n", 1341 usbd_errstr(err), err); 1342 #endif 1343 if (err == USBD_NOMEM) 1344 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1345 #ifdef EHCI_DEBUG 1346 if (err) 1347 printf("ehci_allocm: usb_reserve_allocm()= %s (%d)\n", 1348 usbd_errstr(err), err); 1349 #endif 1350 return (err); 1351 } 1352 1353 Static void 1354 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1355 { 1356 struct ehci_softc *sc = bus->hci_private; 1357 1358 if (dma->block->flags & USB_DMA_RESERVE) { 1359 usb_reserve_freem(&sc->sc_dma_reserve, 1360 dma); 1361 return; 1362 } 1363 usb_freemem(&sc->sc_bus, dma); 1364 } 1365 1366 Static usbd_xfer_handle 1367 ehci_allocx(struct usbd_bus *bus) 1368 { 1369 struct ehci_softc *sc = bus->hci_private; 1370 usbd_xfer_handle xfer; 1371 1372 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers); 1373 if (xfer != NULL) { 1374 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next); 1375 #ifdef DIAGNOSTIC 1376 if (xfer->busy_free != XFER_FREE) { 1377 printf("ehci_allocx: xfer=%p not free, 0x%08x\n", xfer, 1378 xfer->busy_free); 1379 } 1380 #endif 1381 } else { 1382 xfer = kmem_alloc(sizeof(struct ehci_xfer), KM_SLEEP); 1383 } 1384 if (xfer != NULL) { 1385 memset(xfer, 0, sizeof(struct ehci_xfer)); 1386 #ifdef DIAGNOSTIC 1387 EXFER(xfer)->isdone = 1; 1388 xfer->busy_free = XFER_BUSY; 1389 #endif 1390 } 1391 return (xfer); 1392 } 1393 1394 Static void 1395 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1396 { 1397 struct ehci_softc *sc = bus->hci_private; 1398 1399 #ifdef DIAGNOSTIC 1400 if (xfer->busy_free != XFER_BUSY) { 1401 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1402 xfer->busy_free); 1403 } 1404 xfer->busy_free = XFER_FREE; 1405 if (!EXFER(xfer)->isdone) { 1406 printf("ehci_freex: !isdone\n"); 1407 } 1408 #endif 1409 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next); 1410 } 1411 1412 Static void 1413 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1414 { 1415 struct ehci_softc *sc = bus->hci_private; 1416 1417 *lock = &sc->sc_lock; 1418 } 1419 1420 Static void 1421 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1422 { 1423 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1424 1425 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1426 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1427 #ifdef EHCI_DEBUG 1428 if (ehcidebug) 1429 usbd_dump_pipe(pipe); 1430 #endif 1431 epipe->nexttoggle = 0; 1432 } 1433 1434 Static void 1435 ehci_noop(usbd_pipe_handle pipe) 1436 { 1437 } 1438 1439 #ifdef EHCI_DEBUG 1440 Static void 1441 ehci_dump_regs(ehci_softc_t *sc) 1442 { 1443 int i; 1444 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1445 EOREAD4(sc, EHCI_USBCMD), 1446 EOREAD4(sc, EHCI_USBSTS), 1447 EOREAD4(sc, EHCI_USBINTR)); 1448 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1449 EOREAD4(sc, EHCI_FRINDEX), 1450 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1451 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1452 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1453 for (i = 1; i <= sc->sc_noport; i++) 1454 printf("port %d status=0x%08x\n", i, 1455 EOREAD4(sc, EHCI_PORTSC(i))); 1456 } 1457 1458 /* 1459 * Unused function - this is meant to be called from a kernel 1460 * debugger. 1461 */ 1462 void 1463 ehci_dump(void) 1464 { 1465 ehci_dump_regs(theehci); 1466 } 1467 1468 Static void 1469 ehci_dump_link(ehci_link_t link, int type) 1470 { 1471 link = le32toh(link); 1472 printf("0x%08x", link); 1473 if (link & EHCI_LINK_TERMINATE) 1474 printf("<T>"); 1475 else { 1476 printf("<"); 1477 if (type) { 1478 switch (EHCI_LINK_TYPE(link)) { 1479 case EHCI_LINK_ITD: printf("ITD"); break; 1480 case EHCI_LINK_QH: printf("QH"); break; 1481 case EHCI_LINK_SITD: printf("SITD"); break; 1482 case EHCI_LINK_FSTN: printf("FSTN"); break; 1483 } 1484 } 1485 printf(">"); 1486 } 1487 } 1488 1489 Static void 1490 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1491 { 1492 int i; 1493 u_int32_t stop; 1494 1495 stop = 0; 1496 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1497 ehci_dump_sqtd(sqtd); 1498 usb_syncmem(&sqtd->dma, 1499 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1500 sizeof(sqtd->qtd), 1501 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1502 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1503 usb_syncmem(&sqtd->dma, 1504 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1505 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1506 } 1507 if (sqtd) 1508 printf("dump aborted, too many TDs\n"); 1509 } 1510 1511 Static void 1512 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1513 { 1514 usb_syncmem(&sqtd->dma, sqtd->offs, 1515 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1516 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1517 ehci_dump_qtd(&sqtd->qtd); 1518 usb_syncmem(&sqtd->dma, sqtd->offs, 1519 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1520 } 1521 1522 Static void 1523 ehci_dump_qtd(ehci_qtd_t *qtd) 1524 { 1525 u_int32_t s; 1526 char sbuf[128]; 1527 1528 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1529 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1530 printf("\n"); 1531 s = le32toh(qtd->qtd_status); 1532 snprintb(sbuf, sizeof(sbuf), 1533 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1534 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1535 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1536 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1537 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1538 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1539 EHCI_QTD_GET_PID(s), sbuf); 1540 for (s = 0; s < 5; s++) 1541 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1542 } 1543 1544 Static void 1545 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1546 { 1547 ehci_qh_t *qh = &sqh->qh; 1548 u_int32_t endp, endphub; 1549 1550 usb_syncmem(&sqh->dma, sqh->offs, 1551 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1552 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1553 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1554 endp = le32toh(qh->qh_endp); 1555 printf(" endp=0x%08x\n", endp); 1556 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1557 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1558 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1559 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1560 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1561 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1562 EHCI_QH_GET_NRL(endp)); 1563 endphub = le32toh(qh->qh_endphub); 1564 printf(" endphub=0x%08x\n", endphub); 1565 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1566 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1567 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1568 EHCI_QH_GET_MULT(endphub)); 1569 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1570 printf("Overlay qTD:\n"); 1571 ehci_dump_qtd(&qh->qh_qtd); 1572 usb_syncmem(&sqh->dma, sqh->offs, 1573 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1574 } 1575 1576 #if notyet 1577 Static void 1578 ehci_dump_itd(struct ehci_soft_itd *itd) 1579 { 1580 ehci_isoc_trans_t t; 1581 ehci_isoc_bufr_ptr_t b, b2, b3; 1582 int i; 1583 1584 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1585 1586 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1587 t = le32toh(itd->itd.itd_ctl[i]); 1588 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1589 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1590 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1591 EHCI_ITD_GET_OFFS(t)); 1592 } 1593 printf("ITDbufr: "); 1594 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1595 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1596 1597 b = le32toh(itd->itd.itd_bufr[0]); 1598 b2 = le32toh(itd->itd.itd_bufr[1]); 1599 b3 = le32toh(itd->itd.itd_bufr[2]); 1600 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1601 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1602 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1603 } 1604 1605 Static void 1606 ehci_dump_sitd(struct ehci_soft_itd *itd) 1607 { 1608 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1609 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1610 itd->xfer_next, itd->physaddr, itd->slot); 1611 } 1612 #endif 1613 1614 #ifdef DIAGNOSTIC 1615 Static void 1616 ehci_dump_exfer(struct ehci_xfer *ex) 1617 { 1618 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1619 } 1620 #endif 1621 #endif 1622 1623 Static usbd_status 1624 ehci_open(usbd_pipe_handle pipe) 1625 { 1626 usbd_device_handle dev = pipe->device; 1627 ehci_softc_t *sc = dev->bus->hci_private; 1628 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1629 u_int8_t addr = dev->address; 1630 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE; 1631 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1632 ehci_soft_qh_t *sqh; 1633 usbd_status err; 1634 int ival, speed, naks; 1635 int hshubaddr, hshubport; 1636 1637 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1638 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1639 1640 if (dev->myhsport) { 1641 /* 1642 * When directly attached FS/LS device while doing embedded 1643 * transaction translations and we are the hub, set the hub 1644 * address to 0 (us). 1645 */ 1646 if (!(sc->sc_flags & EHCIF_ETTF) 1647 || (dev->myhsport->parent->address != sc->sc_addr)) { 1648 hshubaddr = dev->myhsport->parent->address; 1649 } else { 1650 hshubaddr = 0; 1651 } 1652 hshubport = dev->myhsport->portno; 1653 } else { 1654 hshubaddr = 0; 1655 hshubport = 0; 1656 } 1657 1658 if (sc->sc_dying) 1659 return (USBD_IOERROR); 1660 1661 /* toggle state needed for bulk endpoints */ 1662 epipe->nexttoggle = pipe->endpoint->datatoggle; 1663 1664 if (addr == sc->sc_addr) { 1665 switch (ed->bEndpointAddress) { 1666 case USB_CONTROL_ENDPOINT: 1667 pipe->methods = &ehci_root_ctrl_methods; 1668 break; 1669 case UE_DIR_IN | EHCI_INTR_ENDPT: 1670 pipe->methods = &ehci_root_intr_methods; 1671 break; 1672 default: 1673 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1674 ed->bEndpointAddress)); 1675 return (USBD_INVAL); 1676 } 1677 return (USBD_NORMAL_COMPLETION); 1678 } 1679 1680 /* XXX All this stuff is only valid for async. */ 1681 switch (dev->speed) { 1682 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1683 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1684 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1685 default: panic("ehci_open: bad device speed %d", dev->speed); 1686 } 1687 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1688 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1689 "isoc endpoint.\n"); 1690 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1691 "attached to a USB2 hub, and transaction translations are " 1692 "not yet supported.\n"); 1693 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1694 "root hub instead.\n"); 1695 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1696 hshubaddr, hshubport)); 1697 return USBD_INVAL; 1698 } 1699 1700 /* 1701 * For interrupt transfer, nak throttling must be disabled, but for 1702 * the other transfer type, nak throttling should be enabled from the 1703 * viewpoint that avoids the memory thrashing. 1704 */ 1705 naks = (xfertype == UE_INTERRUPT) ? 0 1706 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1707 1708 /* Allocate sqh for everything, save isoc xfers */ 1709 if (xfertype != UE_ISOCHRONOUS) { 1710 sqh = ehci_alloc_sqh(sc); 1711 if (sqh == NULL) 1712 return (USBD_NOMEM); 1713 /* qh_link filled when the QH is added */ 1714 sqh->qh.qh_endp = htole32( 1715 EHCI_QH_SET_ADDR(addr) | 1716 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1717 EHCI_QH_SET_EPS(speed) | 1718 EHCI_QH_DTC | 1719 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1720 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1721 EHCI_QH_CTL : 0) | 1722 EHCI_QH_SET_NRL(naks) 1723 ); 1724 sqh->qh.qh_endphub = htole32( 1725 EHCI_QH_SET_MULT(1) | 1726 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1727 ); 1728 if (speed != EHCI_QH_SPEED_HIGH) 1729 sqh->qh.qh_endphub |= htole32( 1730 EHCI_QH_SET_PORT(hshubport) | 1731 EHCI_QH_SET_HUBA(hshubaddr) | 1732 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1733 ); 1734 sqh->qh.qh_curqtd = EHCI_NULL; 1735 /* Fill the overlay qTD */ 1736 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1737 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1738 sqh->qh.qh_qtd.qtd_status = htole32(0); 1739 1740 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1741 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1742 epipe->sqh = sqh; 1743 } else { 1744 sqh = NULL; 1745 } /*xfertype == UE_ISOC*/ 1746 1747 switch (xfertype) { 1748 case UE_CONTROL: 1749 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1750 0, &epipe->u.ctl.reqdma); 1751 #ifdef EHCI_DEBUG 1752 if (err) 1753 printf("ehci_open: usb_allocmem()=%d\n", err); 1754 #endif 1755 if (err) 1756 goto bad; 1757 pipe->methods = &ehci_device_ctrl_methods; 1758 mutex_enter(&sc->sc_lock); 1759 ehci_add_qh(sc, sqh, sc->sc_async_head); 1760 mutex_exit(&sc->sc_lock); 1761 break; 1762 case UE_BULK: 1763 pipe->methods = &ehci_device_bulk_methods; 1764 mutex_enter(&sc->sc_lock); 1765 ehci_add_qh(sc, sqh, sc->sc_async_head); 1766 mutex_exit(&sc->sc_lock); 1767 break; 1768 case UE_INTERRUPT: 1769 pipe->methods = &ehci_device_intr_methods; 1770 ival = pipe->interval; 1771 if (ival == USBD_DEFAULT_INTERVAL) { 1772 if (speed == EHCI_QH_SPEED_HIGH) { 1773 if (ed->bInterval > 16) { 1774 /* 1775 * illegal with high-speed, but there 1776 * were documentation bugs in the spec, 1777 * so be generous 1778 */ 1779 ival = 256; 1780 } else 1781 ival = (1 << (ed->bInterval - 1)) / 8; 1782 } else 1783 ival = ed->bInterval; 1784 } 1785 err = ehci_device_setintr(sc, sqh, ival); 1786 if (err) 1787 goto bad; 1788 break; 1789 case UE_ISOCHRONOUS: 1790 pipe->methods = &ehci_device_isoc_methods; 1791 if (ed->bInterval == 0 || ed->bInterval > 16) { 1792 printf("ehci: opening pipe with invalid bInterval\n"); 1793 err = USBD_INVAL; 1794 goto bad; 1795 } 1796 if (UGETW(ed->wMaxPacketSize) == 0) { 1797 printf("ehci: zero length endpoint open request\n"); 1798 err = USBD_INVAL; 1799 goto bad; 1800 } 1801 epipe->u.isoc.next_frame = 0; 1802 epipe->u.isoc.cur_xfers = 0; 1803 break; 1804 default: 1805 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1806 err = USBD_INVAL; 1807 goto bad; 1808 } 1809 return (USBD_NORMAL_COMPLETION); 1810 1811 bad: 1812 if (sqh != NULL) 1813 ehci_free_sqh(sc, sqh); 1814 return (err); 1815 } 1816 1817 /* 1818 * Add an ED to the schedule. Called with USB lock held. 1819 */ 1820 Static void 1821 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1822 { 1823 1824 KASSERT(mutex_owned(&sc->sc_lock)); 1825 1826 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1827 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1828 sqh->next = head->next; 1829 sqh->qh.qh_link = head->qh.qh_link; 1830 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1831 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1832 head->next = sqh; 1833 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1834 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1835 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1836 1837 #ifdef EHCI_DEBUG 1838 if (ehcidebug > 5) { 1839 printf("ehci_add_qh:\n"); 1840 ehci_dump_sqh(sqh); 1841 } 1842 #endif 1843 } 1844 1845 /* 1846 * Remove an ED from the schedule. Called with USB lock held. 1847 */ 1848 Static void 1849 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1850 { 1851 ehci_soft_qh_t *p; 1852 1853 KASSERT(mutex_owned(&sc->sc_lock)); 1854 1855 /* XXX */ 1856 for (p = head; p != NULL && p->next != sqh; p = p->next) 1857 ; 1858 if (p == NULL) 1859 panic("ehci_rem_qh: ED not found"); 1860 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1861 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1862 p->next = sqh->next; 1863 p->qh.qh_link = sqh->qh.qh_link; 1864 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1865 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1866 1867 ehci_sync_hc(sc); 1868 } 1869 1870 Static void 1871 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1872 { 1873 int i; 1874 u_int32_t status; 1875 1876 /* Save toggle bit and ping status. */ 1877 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1878 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1879 status = sqh->qh.qh_qtd.qtd_status & 1880 htole32(EHCI_QTD_TOGGLE_MASK | 1881 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1882 /* Set HALTED to make hw leave it alone. */ 1883 sqh->qh.qh_qtd.qtd_status = 1884 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1885 usb_syncmem(&sqh->dma, 1886 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1887 sizeof(sqh->qh.qh_qtd.qtd_status), 1888 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1889 sqh->qh.qh_curqtd = 0; 1890 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1891 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1892 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1893 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1894 sqh->sqtd = sqtd; 1895 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1896 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1897 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1898 sqh->qh.qh_qtd.qtd_status = status; 1899 usb_syncmem(&sqh->dma, 1900 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1901 sizeof(sqh->qh.qh_qtd.qtd_status), 1902 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1903 } 1904 1905 /* 1906 * Ensure that the HC has released all references to the QH. We do this 1907 * by asking for a Async Advance Doorbell interrupt and then we wait for 1908 * the interrupt. 1909 * To make this easier we first obtain exclusive use of the doorbell. 1910 */ 1911 Static void 1912 ehci_sync_hc(ehci_softc_t *sc) 1913 { 1914 int error; 1915 1916 KASSERT(mutex_owned(&sc->sc_lock)); 1917 1918 if (sc->sc_dying) { 1919 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1920 return; 1921 } 1922 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1923 /* ask for doorbell */ 1924 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1925 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1926 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1927 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 1928 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1929 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1930 #ifdef DIAGNOSTIC 1931 if (error) 1932 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 1933 #endif 1934 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1935 } 1936 1937 Static void 1938 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1939 { 1940 struct ehci_soft_itd *itd, *prev; 1941 1942 prev = NULL; 1943 1944 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1945 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1946 1947 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1948 prev = itd->u.frame_list.prev; 1949 /* Unlink itd from hardware chain, or frame array */ 1950 if (prev == NULL) { /* We're at the table head */ 1951 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1952 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1953 usb_syncmem(&sc->sc_fldma, 1954 sizeof(ehci_link_t) * itd->slot, 1955 sizeof(ehci_link_t), 1956 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1957 1958 if (itd->u.frame_list.next != NULL) 1959 itd->u.frame_list.next->u.frame_list.prev = NULL; 1960 } else { 1961 /* XXX this part is untested... */ 1962 prev->itd.itd_next = itd->itd.itd_next; 1963 usb_syncmem(&itd->dma, 1964 itd->offs + offsetof(ehci_itd_t, itd_next), 1965 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1966 1967 prev->u.frame_list.next = itd->u.frame_list.next; 1968 if (itd->u.frame_list.next != NULL) 1969 itd->u.frame_list.next->u.frame_list.prev = prev; 1970 } 1971 } 1972 1973 prev = NULL; 1974 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1975 if (prev != NULL) 1976 ehci_free_itd(sc, prev); 1977 prev = itd; 1978 } 1979 if (prev) 1980 ehci_free_itd(sc, prev); 1981 exfer->itdstart = NULL; 1982 exfer->itdend = NULL; 1983 } 1984 1985 /***********/ 1986 1987 /* 1988 * Data structures and routines to emulate the root hub. 1989 */ 1990 Static usb_device_descriptor_t ehci_devd = { 1991 USB_DEVICE_DESCRIPTOR_SIZE, 1992 UDESC_DEVICE, /* type */ 1993 {0x00, 0x02}, /* USB version */ 1994 UDCLASS_HUB, /* class */ 1995 UDSUBCLASS_HUB, /* subclass */ 1996 UDPROTO_HSHUBSTT, /* protocol */ 1997 64, /* max packet */ 1998 {0},{0},{0x00,0x01}, /* device id */ 1999 1,2,0, /* string indicies */ 2000 1 /* # of configurations */ 2001 }; 2002 2003 Static const usb_device_qualifier_t ehci_odevd = { 2004 USB_DEVICE_DESCRIPTOR_SIZE, 2005 UDESC_DEVICE_QUALIFIER, /* type */ 2006 {0x00, 0x02}, /* USB version */ 2007 UDCLASS_HUB, /* class */ 2008 UDSUBCLASS_HUB, /* subclass */ 2009 UDPROTO_FSHUB, /* protocol */ 2010 64, /* max packet */ 2011 1, /* # of configurations */ 2012 0 2013 }; 2014 2015 Static const usb_config_descriptor_t ehci_confd = { 2016 USB_CONFIG_DESCRIPTOR_SIZE, 2017 UDESC_CONFIG, 2018 {USB_CONFIG_DESCRIPTOR_SIZE + 2019 USB_INTERFACE_DESCRIPTOR_SIZE + 2020 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2021 1, 2022 1, 2023 0, 2024 UC_ATTR_MBO | UC_SELF_POWERED, 2025 0 /* max power */ 2026 }; 2027 2028 Static const usb_interface_descriptor_t ehci_ifcd = { 2029 USB_INTERFACE_DESCRIPTOR_SIZE, 2030 UDESC_INTERFACE, 2031 0, 2032 0, 2033 1, 2034 UICLASS_HUB, 2035 UISUBCLASS_HUB, 2036 UIPROTO_HSHUBSTT, 2037 0 2038 }; 2039 2040 Static const usb_endpoint_descriptor_t ehci_endpd = { 2041 USB_ENDPOINT_DESCRIPTOR_SIZE, 2042 UDESC_ENDPOINT, 2043 UE_DIR_IN | EHCI_INTR_ENDPT, 2044 UE_INTERRUPT, 2045 {8, 0}, /* max packet */ 2046 12 2047 }; 2048 2049 Static const usb_hub_descriptor_t ehci_hubd = { 2050 USB_HUB_DESCRIPTOR_SIZE, 2051 UDESC_HUB, 2052 0, 2053 {0,0}, 2054 0, 2055 0, 2056 {""}, 2057 {""}, 2058 }; 2059 2060 /* 2061 * Simulate a hardware hub by handling all the necessary requests. 2062 */ 2063 Static usbd_status 2064 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2065 { 2066 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2067 usbd_status err; 2068 2069 /* Insert last in queue. */ 2070 mutex_enter(&sc->sc_lock); 2071 err = usb_insert_transfer(xfer); 2072 mutex_exit(&sc->sc_lock); 2073 if (err) 2074 return (err); 2075 2076 /* Pipe isn't running, start first */ 2077 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2078 } 2079 2080 Static usbd_status 2081 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2082 { 2083 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2084 usb_device_request_t *req; 2085 void *buf = NULL; 2086 int port, i; 2087 int len, value, index, l, totlen = 0; 2088 usb_port_status_t ps; 2089 usb_hub_descriptor_t hubd; 2090 usbd_status err; 2091 u_int32_t v; 2092 2093 if (sc->sc_dying) 2094 return (USBD_IOERROR); 2095 2096 #ifdef DIAGNOSTIC 2097 if (!(xfer->rqflags & URQ_REQUEST)) 2098 /* XXX panic */ 2099 return (USBD_INVAL); 2100 #endif 2101 req = &xfer->request; 2102 2103 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2104 req->bmRequestType, req->bRequest)); 2105 2106 len = UGETW(req->wLength); 2107 value = UGETW(req->wValue); 2108 index = UGETW(req->wIndex); 2109 2110 if (len != 0) 2111 buf = KERNADDR(&xfer->dmabuf, 0); 2112 2113 #define C(x,y) ((x) | ((y) << 8)) 2114 switch(C(req->bRequest, req->bmRequestType)) { 2115 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2116 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2117 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2118 /* 2119 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2120 * for the integrated root hub. 2121 */ 2122 break; 2123 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2124 if (len > 0) { 2125 *(u_int8_t *)buf = sc->sc_conf; 2126 totlen = 1; 2127 } 2128 break; 2129 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2130 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2131 if (len == 0) 2132 break; 2133 switch(value >> 8) { 2134 case UDESC_DEVICE: 2135 if ((value & 0xff) != 0) { 2136 err = USBD_IOERROR; 2137 goto ret; 2138 } 2139 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2140 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2141 memcpy(buf, &ehci_devd, l); 2142 break; 2143 /* 2144 * We can't really operate at another speed, but the spec says 2145 * we need this descriptor. 2146 */ 2147 case UDESC_DEVICE_QUALIFIER: 2148 if ((value & 0xff) != 0) { 2149 err = USBD_IOERROR; 2150 goto ret; 2151 } 2152 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2153 memcpy(buf, &ehci_odevd, l); 2154 break; 2155 /* 2156 * We can't really operate at another speed, but the spec says 2157 * we need this descriptor. 2158 */ 2159 case UDESC_OTHER_SPEED_CONFIGURATION: 2160 case UDESC_CONFIG: 2161 if ((value & 0xff) != 0) { 2162 err = USBD_IOERROR; 2163 goto ret; 2164 } 2165 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2166 memcpy(buf, &ehci_confd, l); 2167 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2168 value >> 8; 2169 buf = (char *)buf + l; 2170 len -= l; 2171 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2172 totlen += l; 2173 memcpy(buf, &ehci_ifcd, l); 2174 buf = (char *)buf + l; 2175 len -= l; 2176 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2177 totlen += l; 2178 memcpy(buf, &ehci_endpd, l); 2179 break; 2180 case UDESC_STRING: 2181 #define sd ((usb_string_descriptor_t *)buf) 2182 switch (value & 0xff) { 2183 case 0: /* Language table */ 2184 totlen = usb_makelangtbl(sd, len); 2185 break; 2186 case 1: /* Vendor */ 2187 totlen = usb_makestrdesc(sd, len, 2188 sc->sc_vendor); 2189 break; 2190 case 2: /* Product */ 2191 totlen = usb_makestrdesc(sd, len, 2192 "EHCI root hub"); 2193 break; 2194 } 2195 #undef sd 2196 break; 2197 default: 2198 err = USBD_IOERROR; 2199 goto ret; 2200 } 2201 break; 2202 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2203 if (len > 0) { 2204 *(u_int8_t *)buf = 0; 2205 totlen = 1; 2206 } 2207 break; 2208 case C(UR_GET_STATUS, UT_READ_DEVICE): 2209 if (len > 1) { 2210 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2211 totlen = 2; 2212 } 2213 break; 2214 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2215 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2216 if (len > 1) { 2217 USETW(((usb_status_t *)buf)->wStatus, 0); 2218 totlen = 2; 2219 } 2220 break; 2221 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2222 if (value >= USB_MAX_DEVICES) { 2223 err = USBD_IOERROR; 2224 goto ret; 2225 } 2226 sc->sc_addr = value; 2227 break; 2228 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2229 if (value != 0 && value != 1) { 2230 err = USBD_IOERROR; 2231 goto ret; 2232 } 2233 sc->sc_conf = value; 2234 break; 2235 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2236 break; 2237 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2238 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2239 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2240 err = USBD_IOERROR; 2241 goto ret; 2242 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2243 break; 2244 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2245 break; 2246 /* Hub requests */ 2247 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2248 break; 2249 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2250 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2251 "port=%d feature=%d\n", 2252 index, value)); 2253 if (index < 1 || index > sc->sc_noport) { 2254 err = USBD_IOERROR; 2255 goto ret; 2256 } 2257 port = EHCI_PORTSC(index); 2258 v = EOREAD4(sc, port); 2259 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2260 v &= ~EHCI_PS_CLEAR; 2261 switch(value) { 2262 case UHF_PORT_ENABLE: 2263 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2264 break; 2265 case UHF_PORT_SUSPEND: 2266 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2267 break; 2268 v &= ~EHCI_PS_SUSP; 2269 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2270 /* see USB2 spec ch. 7.1.7.7 */ 2271 usb_delay_ms(&sc->sc_bus, 20); 2272 EOWRITE4(sc, port, v); 2273 usb_delay_ms(&sc->sc_bus, 2); 2274 #ifdef DEBUG 2275 v = EOREAD4(sc, port); 2276 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2277 printf("ehci: resume failed: %x\n", v); 2278 #endif 2279 break; 2280 case UHF_PORT_POWER: 2281 if (sc->sc_hasppc) 2282 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2283 break; 2284 case UHF_PORT_TEST: 2285 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2286 "%d\n", index)); 2287 break; 2288 case UHF_PORT_INDICATOR: 2289 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2290 "%d\n", index)); 2291 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2292 break; 2293 case UHF_C_PORT_CONNECTION: 2294 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2295 break; 2296 case UHF_C_PORT_ENABLE: 2297 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2298 break; 2299 case UHF_C_PORT_SUSPEND: 2300 /* how? */ 2301 break; 2302 case UHF_C_PORT_OVER_CURRENT: 2303 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2304 break; 2305 case UHF_C_PORT_RESET: 2306 sc->sc_isreset[index] = 0; 2307 break; 2308 default: 2309 err = USBD_IOERROR; 2310 goto ret; 2311 } 2312 #if 0 2313 switch(value) { 2314 case UHF_C_PORT_CONNECTION: 2315 case UHF_C_PORT_ENABLE: 2316 case UHF_C_PORT_SUSPEND: 2317 case UHF_C_PORT_OVER_CURRENT: 2318 case UHF_C_PORT_RESET: 2319 default: 2320 break; 2321 } 2322 #endif 2323 break; 2324 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2325 if (len == 0) 2326 break; 2327 if ((value & 0xff) != 0) { 2328 err = USBD_IOERROR; 2329 goto ret; 2330 } 2331 hubd = ehci_hubd; 2332 hubd.bNbrPorts = sc->sc_noport; 2333 v = EOREAD4(sc, EHCI_HCSPARAMS); 2334 USETW(hubd.wHubCharacteristics, 2335 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2336 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2337 ? UHD_PORT_IND : 0); 2338 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2339 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2340 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2341 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2342 l = min(len, hubd.bDescLength); 2343 totlen = l; 2344 memcpy(buf, &hubd, l); 2345 break; 2346 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2347 if (len != 4) { 2348 err = USBD_IOERROR; 2349 goto ret; 2350 } 2351 memset(buf, 0, len); /* ? XXX */ 2352 totlen = len; 2353 break; 2354 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2355 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2356 index)); 2357 if (index < 1 || index > sc->sc_noport) { 2358 err = USBD_IOERROR; 2359 goto ret; 2360 } 2361 if (len != 4) { 2362 err = USBD_IOERROR; 2363 goto ret; 2364 } 2365 v = EOREAD4(sc, EHCI_PORTSC(index)); 2366 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2367 2368 i = UPS_HIGH_SPEED; 2369 if (sc->sc_flags & EHCIF_ETTF) { 2370 /* 2371 * If we are doing embedded transaction translation, 2372 * then directly attached LS/FS devices are reset by 2373 * the EHCI controller itself. PSPD is encoded 2374 * the same way as in USBSTATUS. 2375 */ 2376 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2377 } 2378 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2379 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2380 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2381 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2382 if (v & EHCI_PS_PR) i |= UPS_RESET; 2383 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2384 if (sc->sc_vendor_port_status) 2385 i = sc->sc_vendor_port_status(sc, v, i); 2386 USETW(ps.wPortStatus, i); 2387 i = 0; 2388 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2389 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2390 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2391 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2392 USETW(ps.wPortChange, i); 2393 l = min(len, sizeof ps); 2394 memcpy(buf, &ps, l); 2395 totlen = l; 2396 break; 2397 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2398 err = USBD_IOERROR; 2399 goto ret; 2400 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2401 break; 2402 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2403 if (index < 1 || index > sc->sc_noport) { 2404 err = USBD_IOERROR; 2405 goto ret; 2406 } 2407 port = EHCI_PORTSC(index); 2408 v = EOREAD4(sc, port); 2409 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2410 v &= ~EHCI_PS_CLEAR; 2411 switch(value) { 2412 case UHF_PORT_ENABLE: 2413 EOWRITE4(sc, port, v | EHCI_PS_PE); 2414 break; 2415 case UHF_PORT_SUSPEND: 2416 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2417 break; 2418 case UHF_PORT_RESET: 2419 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2420 index)); 2421 if (EHCI_PS_IS_LOWSPEED(v) 2422 && sc->sc_ncomp > 0 2423 && !(sc->sc_flags & EHCIF_ETTF)) { 2424 /* 2425 * Low speed device on non-ETTF controller or 2426 * unaccompanied controller, give up ownership. 2427 */ 2428 ehci_disown(sc, index, 1); 2429 break; 2430 } 2431 /* Start reset sequence. */ 2432 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2433 EOWRITE4(sc, port, v | EHCI_PS_PR); 2434 /* Wait for reset to complete. */ 2435 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2436 if (sc->sc_dying) { 2437 err = USBD_IOERROR; 2438 goto ret; 2439 } 2440 /* 2441 * An embedded transaction translater will automatically 2442 * terminate the reset sequence so there's no need to 2443 * it. 2444 */ 2445 v = EOREAD4(sc, port); 2446 if (v & EHCI_PS_PR) { 2447 /* Terminate reset sequence. */ 2448 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2449 /* Wait for HC to complete reset. */ 2450 usb_delay_ms(&sc->sc_bus, 2451 EHCI_PORT_RESET_COMPLETE); 2452 if (sc->sc_dying) { 2453 err = USBD_IOERROR; 2454 goto ret; 2455 } 2456 } 2457 2458 v = EOREAD4(sc, port); 2459 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2460 if (v & EHCI_PS_PR) { 2461 printf("%s: port reset timeout\n", 2462 device_xname(sc->sc_dev)); 2463 return (USBD_TIMEOUT); 2464 } 2465 if (!(v & EHCI_PS_PE)) { 2466 /* Not a high speed device, give up ownership.*/ 2467 ehci_disown(sc, index, 0); 2468 break; 2469 } 2470 sc->sc_isreset[index] = 1; 2471 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2472 index, v)); 2473 break; 2474 case UHF_PORT_POWER: 2475 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2476 "%d (has PPC = %d)\n", index, 2477 sc->sc_hasppc)); 2478 if (sc->sc_hasppc) 2479 EOWRITE4(sc, port, v | EHCI_PS_PP); 2480 break; 2481 case UHF_PORT_TEST: 2482 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2483 "%d\n", index)); 2484 break; 2485 case UHF_PORT_INDICATOR: 2486 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2487 "%d\n", index)); 2488 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2489 break; 2490 default: 2491 err = USBD_IOERROR; 2492 goto ret; 2493 } 2494 break; 2495 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2496 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2497 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2498 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2499 break; 2500 default: 2501 err = USBD_IOERROR; 2502 goto ret; 2503 } 2504 xfer->actlen = totlen; 2505 err = USBD_NORMAL_COMPLETION; 2506 ret: 2507 mutex_enter(&sc->sc_lock); 2508 xfer->status = err; 2509 usb_transfer_complete(xfer); 2510 mutex_exit(&sc->sc_lock); 2511 return (USBD_IN_PROGRESS); 2512 } 2513 2514 Static void 2515 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2516 { 2517 int port; 2518 u_int32_t v; 2519 2520 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2521 #ifdef DIAGNOSTIC 2522 if (sc->sc_npcomp != 0) { 2523 int i = (index-1) / sc->sc_npcomp; 2524 if (i >= sc->sc_ncomp) 2525 printf("%s: strange port\n", 2526 device_xname(sc->sc_dev)); 2527 else 2528 printf("%s: handing over %s speed device on " 2529 "port %d to %s\n", 2530 device_xname(sc->sc_dev), 2531 lowspeed ? "low" : "full", 2532 index, device_xname(sc->sc_comps[i])); 2533 } else { 2534 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2535 } 2536 #endif 2537 port = EHCI_PORTSC(index); 2538 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2539 EOWRITE4(sc, port, v | EHCI_PS_PO); 2540 } 2541 2542 /* Abort a root control request. */ 2543 Static void 2544 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2545 { 2546 /* Nothing to do, all transfers are synchronous. */ 2547 } 2548 2549 /* Close the root pipe. */ 2550 Static void 2551 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2552 { 2553 DPRINTF(("ehci_root_ctrl_close\n")); 2554 /* Nothing to do. */ 2555 } 2556 2557 Static void 2558 ehci_root_intr_done(usbd_xfer_handle xfer) 2559 { 2560 xfer->hcpriv = NULL; 2561 } 2562 2563 Static usbd_status 2564 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2565 { 2566 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2567 usbd_status err; 2568 2569 /* Insert last in queue. */ 2570 mutex_enter(&sc->sc_lock); 2571 err = usb_insert_transfer(xfer); 2572 mutex_exit(&sc->sc_lock); 2573 if (err) 2574 return (err); 2575 2576 /* Pipe isn't running, start first */ 2577 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2578 } 2579 2580 Static usbd_status 2581 ehci_root_intr_start(usbd_xfer_handle xfer) 2582 { 2583 usbd_pipe_handle pipe = xfer->pipe; 2584 ehci_softc_t *sc = pipe->device->bus->hci_private; 2585 2586 if (sc->sc_dying) 2587 return (USBD_IOERROR); 2588 2589 mutex_enter(&sc->sc_lock); 2590 sc->sc_intrxfer = xfer; 2591 mutex_exit(&sc->sc_lock); 2592 2593 return (USBD_IN_PROGRESS); 2594 } 2595 2596 /* Abort a root interrupt request. */ 2597 Static void 2598 ehci_root_intr_abort(usbd_xfer_handle xfer) 2599 { 2600 #ifdef DIAGNOSTIC 2601 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2602 #endif 2603 2604 KASSERT(mutex_owned(&sc->sc_lock)); 2605 if (xfer->pipe->intrxfer == xfer) { 2606 DPRINTF(("ehci_root_intr_abort: remove\n")); 2607 xfer->pipe->intrxfer = NULL; 2608 } 2609 xfer->status = USBD_CANCELLED; 2610 usb_transfer_complete(xfer); 2611 } 2612 2613 /* Close the root pipe. */ 2614 Static void 2615 ehci_root_intr_close(usbd_pipe_handle pipe) 2616 { 2617 ehci_softc_t *sc = pipe->device->bus->hci_private; 2618 2619 KASSERT(mutex_owned(&sc->sc_lock)); 2620 2621 DPRINTF(("ehci_root_intr_close\n")); 2622 2623 sc->sc_intrxfer = NULL; 2624 } 2625 2626 Static void 2627 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2628 { 2629 xfer->hcpriv = NULL; 2630 } 2631 2632 /************************/ 2633 2634 Static ehci_soft_qh_t * 2635 ehci_alloc_sqh(ehci_softc_t *sc) 2636 { 2637 ehci_soft_qh_t *sqh; 2638 usbd_status err; 2639 int i, offs; 2640 usb_dma_t dma; 2641 2642 if (sc->sc_freeqhs == NULL) { 2643 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2644 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2645 EHCI_PAGE_SIZE, &dma); 2646 #ifdef EHCI_DEBUG 2647 if (err) 2648 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2649 #endif 2650 if (err) 2651 return (NULL); 2652 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2653 offs = i * EHCI_SQH_SIZE; 2654 sqh = KERNADDR(&dma, offs); 2655 sqh->physaddr = DMAADDR(&dma, offs); 2656 sqh->dma = dma; 2657 sqh->offs = offs; 2658 sqh->next = sc->sc_freeqhs; 2659 sc->sc_freeqhs = sqh; 2660 } 2661 } 2662 sqh = sc->sc_freeqhs; 2663 sc->sc_freeqhs = sqh->next; 2664 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2665 sqh->next = NULL; 2666 return (sqh); 2667 } 2668 2669 Static void 2670 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2671 { 2672 sqh->next = sc->sc_freeqhs; 2673 sc->sc_freeqhs = sqh; 2674 } 2675 2676 Static ehci_soft_qtd_t * 2677 ehci_alloc_sqtd(ehci_softc_t *sc) 2678 { 2679 ehci_soft_qtd_t *sqtd = NULL; 2680 usbd_status err; 2681 int i, offs; 2682 usb_dma_t dma; 2683 2684 if (sc->sc_freeqtds == NULL) { 2685 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2686 2687 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2688 EHCI_PAGE_SIZE, &dma); 2689 #ifdef EHCI_DEBUG 2690 if (err) 2691 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2692 #endif 2693 if (err) 2694 goto done; 2695 2696 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2697 offs = i * EHCI_SQTD_SIZE; 2698 sqtd = KERNADDR(&dma, offs); 2699 sqtd->physaddr = DMAADDR(&dma, offs); 2700 sqtd->dma = dma; 2701 sqtd->offs = offs; 2702 2703 sqtd->nextqtd = sc->sc_freeqtds; 2704 sc->sc_freeqtds = sqtd; 2705 } 2706 } 2707 2708 sqtd = sc->sc_freeqtds; 2709 sc->sc_freeqtds = sqtd->nextqtd; 2710 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2711 sqtd->nextqtd = NULL; 2712 sqtd->xfer = NULL; 2713 2714 done: 2715 return (sqtd); 2716 } 2717 2718 Static void 2719 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2720 { 2721 2722 KASSERT(mutex_owned(&sc->sc_lock)); 2723 2724 sqtd->nextqtd = sc->sc_freeqtds; 2725 sc->sc_freeqtds = sqtd; 2726 } 2727 2728 Static usbd_status 2729 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2730 int alen, int rd, usbd_xfer_handle xfer, 2731 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2732 { 2733 ehci_soft_qtd_t *next, *cur; 2734 ehci_physaddr_t nextphys; 2735 u_int32_t qtdstatus; 2736 int len, curlen, mps; 2737 int i, tog; 2738 int pages, pageoffs; 2739 bus_size_t curoffs; 2740 vaddr_t va, va_offs; 2741 usb_dma_t *dma = &xfer->dmabuf; 2742 u_int16_t flags = xfer->flags; 2743 paddr_t a; 2744 2745 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2746 2747 len = alen; 2748 qtdstatus = EHCI_QTD_ACTIVE | 2749 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2750 EHCI_QTD_SET_CERR(3) 2751 /* IOC set below */ 2752 /* BYTES set below */ 2753 ; 2754 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2755 tog = epipe->nexttoggle; 2756 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2757 2758 cur = ehci_alloc_sqtd(sc); 2759 *sp = cur; 2760 if (cur == NULL) 2761 goto nomem; 2762 2763 usb_syncmem(dma, 0, alen, 2764 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2765 curoffs = 0; 2766 for (;;) { 2767 /* The EHCI hardware can handle at most 5 pages. */ 2768 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2769 va_offs = EHCI_PAGE_OFFSET(va_offs); 2770 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 2771 /* we can handle it in this QTD */ 2772 curlen = len - curoffs; 2773 } else { 2774 /* must use multiple TDs, fill as much as possible. */ 2775 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 2776 2777 /* the length must be a multiple of the max size */ 2778 curlen -= curlen % mps; 2779 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2780 "curlen=%d\n", curlen)); 2781 #ifdef DIAGNOSTIC 2782 if (curlen == 0) 2783 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2784 #endif 2785 } 2786 DPRINTFN(4,("ehci_alloc_sqtd_chain: len=%d curlen=%zu " 2787 "curoffs=%d\n", len, curlen, (size_t)curoffs)); 2788 2789 /* 2790 * Allocate another transfer if there's more data left, 2791 * or if force last short transfer flag is set and we're 2792 * allocating a multiple of the max packet size. 2793 */ 2794 2795 if (curoffs + curlen != len || 2796 ((curlen % mps) == 0 && !rd && curlen != 0 && 2797 (flags & USBD_FORCE_SHORT_XFER))) { 2798 next = ehci_alloc_sqtd(sc); 2799 if (next == NULL) 2800 goto nomem; 2801 nextphys = htole32(next->physaddr); 2802 } else { 2803 next = NULL; 2804 nextphys = EHCI_NULL; 2805 } 2806 2807 /* Find number of pages we'll be using, insert dma addresses */ 2808 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2809 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2810 pageoffs = EHCI_PAGE(curoffs); 2811 for (i = 0; i < pages; i++) { 2812 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2813 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2814 /* Cast up to avoid compiler warnings */ 2815 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2816 } 2817 2818 /* First buffer pointer requires a page offset to start at */ 2819 va = (vaddr_t)KERNADDR(dma, curoffs); 2820 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2821 2822 cur->nextqtd = next; 2823 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2824 cur->qtd.qtd_status = 2825 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2826 cur->xfer = xfer; 2827 cur->len = curlen; 2828 2829 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08zx end=0x%08zx\n", 2830 (size_t)curoffs, (size_t)(curoffs + curlen))); 2831 2832 /* adjust the toggle based on the number of packets in this 2833 qtd */ 2834 if (((curlen + mps - 1) / mps) & 1) { 2835 tog ^= 1; 2836 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2837 } 2838 if (next == NULL) 2839 break; 2840 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2841 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2842 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2843 if (len) 2844 curoffs += curlen; 2845 cur = next; 2846 } 2847 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2848 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2849 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2850 *ep = cur; 2851 epipe->nexttoggle = tog; 2852 2853 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2854 *sp, *ep)); 2855 2856 return (USBD_NORMAL_COMPLETION); 2857 2858 nomem: 2859 /* XXX free chain */ 2860 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2861 return (USBD_NOMEM); 2862 } 2863 2864 Static void 2865 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2866 ehci_soft_qtd_t *sqtdend) 2867 { 2868 ehci_soft_qtd_t *p; 2869 int i; 2870 2871 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2872 sqtd, sqtdend)); 2873 2874 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2875 p = sqtd->nextqtd; 2876 ehci_free_sqtd(sc, sqtd); 2877 } 2878 } 2879 2880 Static ehci_soft_itd_t * 2881 ehci_alloc_itd(ehci_softc_t *sc) 2882 { 2883 struct ehci_soft_itd *itd, *freeitd; 2884 usbd_status err; 2885 int i, offs, frindex, previndex; 2886 usb_dma_t dma; 2887 2888 mutex_enter(&sc->sc_lock); 2889 2890 /* Find an itd that wasn't freed this frame or last frame. This can 2891 * discard itds that were freed before frindex wrapped around 2892 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2893 * interrupt and fiddling with list when that happens */ 2894 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2895 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2896 2897 freeitd = NULL; 2898 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2899 if (itd == NULL) 2900 break; 2901 if (itd->slot != frindex && itd->slot != previndex) { 2902 freeitd = itd; 2903 break; 2904 } 2905 } 2906 2907 if (freeitd == NULL) { 2908 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2909 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2910 EHCI_PAGE_SIZE, &dma); 2911 2912 if (err) { 2913 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2914 mutex_exit(&sc->sc_lock); 2915 return NULL; 2916 } 2917 2918 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2919 offs = i * EHCI_ITD_SIZE; 2920 itd = KERNADDR(&dma, offs); 2921 itd->physaddr = DMAADDR(&dma, offs); 2922 itd->dma = dma; 2923 itd->offs = offs; 2924 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2925 } 2926 freeitd = LIST_FIRST(&sc->sc_freeitds); 2927 } 2928 2929 itd = freeitd; 2930 LIST_REMOVE(itd, u.free_list); 2931 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2932 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2933 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2934 BUS_DMASYNC_PREREAD); 2935 2936 itd->u.frame_list.next = NULL; 2937 itd->u.frame_list.prev = NULL; 2938 itd->xfer_next = NULL; 2939 itd->slot = 0; 2940 2941 mutex_exit(&sc->sc_lock); 2942 2943 return itd; 2944 } 2945 2946 Static void 2947 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2948 { 2949 2950 KASSERT(mutex_owned(&sc->sc_lock)); 2951 2952 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2953 } 2954 2955 /****************/ 2956 2957 /* 2958 * Close a reqular pipe. 2959 * Assumes that there are no pending transactions. 2960 */ 2961 Static void 2962 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2963 { 2964 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2965 ehci_softc_t *sc = pipe->device->bus->hci_private; 2966 ehci_soft_qh_t *sqh = epipe->sqh; 2967 2968 KASSERT(mutex_owned(&sc->sc_lock)); 2969 2970 ehci_rem_qh(sc, sqh, head); 2971 ehci_free_sqh(sc, epipe->sqh); 2972 } 2973 2974 /* 2975 * Abort a device request. 2976 * If this routine is called at splusb() it guarantees that the request 2977 * will be removed from the hardware scheduling and that the callback 2978 * for it will be called with USBD_CANCELLED status. 2979 * It's impossible to guarantee that the requested transfer will not 2980 * have happened since the hardware runs concurrently. 2981 * If the transaction has already happened we rely on the ordinary 2982 * interrupt processing to process it. 2983 * XXX This is most probably wrong. 2984 * XXXMRG this doesn't make sense anymore. 2985 */ 2986 Static void 2987 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2988 { 2989 #define exfer EXFER(xfer) 2990 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2991 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2992 ehci_soft_qh_t *sqh = epipe->sqh; 2993 ehci_soft_qtd_t *sqtd; 2994 ehci_physaddr_t cur; 2995 u_int32_t qhstatus; 2996 int hit; 2997 int wake; 2998 2999 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 3000 3001 KASSERT(mutex_owned(&sc->sc_lock)); 3002 3003 if (sc->sc_dying) { 3004 /* If we're dying, just do the software part. */ 3005 xfer->status = status; /* make software ignore it */ 3006 callout_stop(&xfer->timeout_handle); 3007 usb_transfer_complete(xfer); 3008 return; 3009 } 3010 3011 if (cpu_intr_p() || cpu_softintr_p()) 3012 panic("ehci_abort_xfer: not in process context"); 3013 3014 /* 3015 * If an abort is already in progress then just wait for it to 3016 * complete and return. 3017 */ 3018 if (xfer->hcflags & UXFER_ABORTING) { 3019 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3020 #ifdef DIAGNOSTIC 3021 if (status == USBD_TIMEOUT) 3022 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3023 #endif 3024 /* Override the status which might be USBD_TIMEOUT. */ 3025 xfer->status = status; 3026 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3027 xfer->hcflags |= UXFER_ABORTWAIT; 3028 while (xfer->hcflags & UXFER_ABORTING) 3029 cv_wait(&xfer->hccv, &sc->sc_lock); 3030 return; 3031 } 3032 xfer->hcflags |= UXFER_ABORTING; 3033 3034 /* 3035 * Step 1: Make interrupt routine and hardware ignore xfer. 3036 */ 3037 xfer->status = status; /* make software ignore it */ 3038 callout_stop(&xfer->timeout_handle); 3039 3040 usb_syncmem(&sqh->dma, 3041 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3042 sizeof(sqh->qh.qh_qtd.qtd_status), 3043 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3044 qhstatus = sqh->qh.qh_qtd.qtd_status; 3045 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3046 usb_syncmem(&sqh->dma, 3047 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3048 sizeof(sqh->qh.qh_qtd.qtd_status), 3049 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3050 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3051 usb_syncmem(&sqtd->dma, 3052 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3053 sizeof(sqtd->qtd.qtd_status), 3054 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3055 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3056 usb_syncmem(&sqtd->dma, 3057 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3058 sizeof(sqtd->qtd.qtd_status), 3059 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3060 if (sqtd == exfer->sqtdend) 3061 break; 3062 } 3063 3064 /* 3065 * Step 2: Wait until we know hardware has finished any possible 3066 * use of the xfer. Also make sure the soft interrupt routine 3067 * has run. 3068 */ 3069 ehci_sync_hc(sc); 3070 sc->sc_softwake = 1; 3071 usb_schedsoftintr(&sc->sc_bus); 3072 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3073 3074 /* 3075 * Step 3: Remove any vestiges of the xfer from the hardware. 3076 * The complication here is that the hardware may have executed 3077 * beyond the xfer we're trying to abort. So as we're scanning 3078 * the TDs of this xfer we check if the hardware points to 3079 * any of them. 3080 */ 3081 3082 usb_syncmem(&sqh->dma, 3083 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3084 sizeof(sqh->qh.qh_curqtd), 3085 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3086 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3087 hit = 0; 3088 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3089 hit |= cur == sqtd->physaddr; 3090 if (sqtd == exfer->sqtdend) 3091 break; 3092 } 3093 sqtd = sqtd->nextqtd; 3094 /* Zap curqtd register if hardware pointed inside the xfer. */ 3095 if (hit && sqtd != NULL) { 3096 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3097 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3098 usb_syncmem(&sqh->dma, 3099 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3100 sizeof(sqh->qh.qh_curqtd), 3101 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3102 sqh->qh.qh_qtd.qtd_status = qhstatus; 3103 usb_syncmem(&sqh->dma, 3104 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3105 sizeof(sqh->qh.qh_qtd.qtd_status), 3106 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3107 } else { 3108 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3109 } 3110 3111 /* 3112 * Step 4: Execute callback. 3113 */ 3114 #ifdef DIAGNOSTIC 3115 exfer->isdone = 1; 3116 #endif 3117 wake = xfer->hcflags & UXFER_ABORTWAIT; 3118 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3119 usb_transfer_complete(xfer); 3120 if (wake) { 3121 cv_broadcast(&xfer->hccv); 3122 } 3123 3124 KASSERT(mutex_owned(&sc->sc_lock)); 3125 #undef exfer 3126 } 3127 3128 Static void 3129 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3130 { 3131 ehci_isoc_trans_t trans_status; 3132 struct ehci_pipe *epipe; 3133 struct ehci_xfer *exfer; 3134 ehci_softc_t *sc; 3135 struct ehci_soft_itd *itd; 3136 int i, wake; 3137 3138 epipe = (struct ehci_pipe *) xfer->pipe; 3139 exfer = EXFER(xfer); 3140 sc = epipe->pipe.device->bus->hci_private; 3141 3142 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3143 3144 KASSERT(mutex_owned(&sc->sc_lock)); 3145 3146 if (sc->sc_dying) { 3147 xfer->status = status; 3148 callout_stop(&xfer->timeout_handle); 3149 usb_transfer_complete(xfer); 3150 return; 3151 } 3152 3153 if (xfer->hcflags & UXFER_ABORTING) { 3154 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3155 3156 #ifdef DIAGNOSTIC 3157 if (status == USBD_TIMEOUT) 3158 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3159 #endif 3160 3161 xfer->status = status; 3162 DPRINTFN(2, ("ehci_abort_isoc_xfer: waiting for abort to finish\n")); 3163 xfer->hcflags |= UXFER_ABORTWAIT; 3164 while (xfer->hcflags & UXFER_ABORTING) 3165 cv_wait(&xfer->hccv, &sc->sc_lock); 3166 goto done; 3167 } 3168 xfer->hcflags |= UXFER_ABORTING; 3169 3170 xfer->status = status; 3171 callout_stop(&xfer->timeout_handle); 3172 3173 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3174 usb_syncmem(&itd->dma, 3175 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3176 sizeof(itd->itd.itd_ctl), 3177 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3178 3179 for (i = 0; i < 8; i++) { 3180 trans_status = le32toh(itd->itd.itd_ctl[i]); 3181 trans_status &= ~EHCI_ITD_ACTIVE; 3182 itd->itd.itd_ctl[i] = htole32(trans_status); 3183 } 3184 3185 usb_syncmem(&itd->dma, 3186 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3187 sizeof(itd->itd.itd_ctl), 3188 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3189 } 3190 3191 sc->sc_softwake = 1; 3192 usb_schedsoftintr(&sc->sc_bus); 3193 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3194 3195 #ifdef DIAGNOSTIC 3196 exfer->isdone = 1; 3197 #endif 3198 wake = xfer->hcflags & UXFER_ABORTWAIT; 3199 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3200 usb_transfer_complete(xfer); 3201 if (wake) { 3202 cv_broadcast(&xfer->hccv); 3203 } 3204 3205 done: 3206 KASSERT(mutex_owned(&sc->sc_lock)); 3207 return; 3208 } 3209 3210 Static void 3211 ehci_timeout(void *addr) 3212 { 3213 struct ehci_xfer *exfer = addr; 3214 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3215 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3216 3217 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3218 #ifdef EHCI_DEBUG 3219 if (ehcidebug > 1) 3220 usbd_dump_pipe(exfer->xfer.pipe); 3221 #endif 3222 3223 if (sc->sc_dying) { 3224 mutex_enter(&sc->sc_lock); 3225 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3226 mutex_exit(&sc->sc_lock); 3227 return; 3228 } 3229 3230 /* Execute the abort in a process context. */ 3231 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr); 3232 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3233 USB_TASKQ_HC); 3234 } 3235 3236 Static void 3237 ehci_timeout_task(void *addr) 3238 { 3239 usbd_xfer_handle xfer = addr; 3240 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3241 3242 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3243 3244 mutex_enter(&sc->sc_lock); 3245 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3246 mutex_exit(&sc->sc_lock); 3247 } 3248 3249 /************************/ 3250 3251 Static usbd_status 3252 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3253 { 3254 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3255 usbd_status err; 3256 3257 /* Insert last in queue. */ 3258 mutex_enter(&sc->sc_lock); 3259 err = usb_insert_transfer(xfer); 3260 mutex_exit(&sc->sc_lock); 3261 if (err) 3262 return (err); 3263 3264 /* Pipe isn't running, start first */ 3265 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3266 } 3267 3268 Static usbd_status 3269 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3270 { 3271 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3272 usbd_status err; 3273 3274 if (sc->sc_dying) 3275 return (USBD_IOERROR); 3276 3277 #ifdef DIAGNOSTIC 3278 if (!(xfer->rqflags & URQ_REQUEST)) { 3279 /* XXX panic */ 3280 printf("ehci_device_ctrl_transfer: not a request\n"); 3281 return (USBD_INVAL); 3282 } 3283 #endif 3284 3285 err = ehci_device_request(xfer); 3286 if (err) { 3287 return (err); 3288 } 3289 3290 if (sc->sc_bus.use_polling) 3291 ehci_waitintr(sc, xfer); 3292 3293 return (USBD_IN_PROGRESS); 3294 } 3295 3296 Static void 3297 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3298 { 3299 struct ehci_xfer *ex = EXFER(xfer); 3300 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3301 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3302 usb_device_request_t *req = &xfer->request; 3303 int len = UGETW(req->wLength); 3304 int rd = req->bmRequestType & UT_READ; 3305 3306 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3307 3308 KASSERT(mutex_owned(&sc->sc_lock)); 3309 3310 #ifdef DIAGNOSTIC 3311 if (!(xfer->rqflags & URQ_REQUEST)) { 3312 panic("ehci_ctrl_done: not a request"); 3313 } 3314 #endif 3315 3316 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3317 ehci_del_intr_list(sc, ex); /* remove from active list */ 3318 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3319 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3320 BUS_DMASYNC_POSTWRITE); 3321 if (len) 3322 usb_syncmem(&xfer->dmabuf, 0, len, 3323 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3324 } 3325 3326 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3327 } 3328 3329 /* Abort a device control request. */ 3330 Static void 3331 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3332 { 3333 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3334 ehci_abort_xfer(xfer, USBD_CANCELLED); 3335 } 3336 3337 /* Close a device control pipe. */ 3338 Static void 3339 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3340 { 3341 ehci_softc_t *sc = pipe->device->bus->hci_private; 3342 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3343 3344 KASSERT(mutex_owned(&sc->sc_lock)); 3345 3346 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3347 3348 ehci_close_pipe(pipe, sc->sc_async_head); 3349 } 3350 3351 Static usbd_status 3352 ehci_device_request(usbd_xfer_handle xfer) 3353 { 3354 #define exfer EXFER(xfer) 3355 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3356 usb_device_request_t *req = &xfer->request; 3357 usbd_device_handle dev = epipe->pipe.device; 3358 ehci_softc_t *sc = dev->bus->hci_private; 3359 int addr = dev->address; 3360 ehci_soft_qtd_t *setup, *stat, *next; 3361 ehci_soft_qh_t *sqh; 3362 int isread; 3363 int len; 3364 usbd_status err; 3365 3366 isread = req->bmRequestType & UT_READ; 3367 len = UGETW(req->wLength); 3368 3369 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3370 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3371 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3372 UGETW(req->wIndex), len, addr, 3373 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3374 3375 setup = ehci_alloc_sqtd(sc); 3376 if (setup == NULL) { 3377 err = USBD_NOMEM; 3378 goto bad1; 3379 } 3380 stat = ehci_alloc_sqtd(sc); 3381 if (stat == NULL) { 3382 err = USBD_NOMEM; 3383 goto bad2; 3384 } 3385 3386 mutex_enter(&sc->sc_lock); 3387 3388 sqh = epipe->sqh; 3389 3390 /* 3391 * Update device address and length since they may have changed 3392 * during the setup of the control pipe in usbd_new_device(). 3393 */ 3394 /* XXX This only needs to be done once, but it's too early in open. */ 3395 /* XXXX Should not touch ED here! */ 3396 sqh->qh.qh_endp = 3397 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3398 htole32( 3399 EHCI_QH_SET_ADDR(addr) | 3400 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3401 ); 3402 3403 /* Set up data transaction */ 3404 if (len != 0) { 3405 ehci_soft_qtd_t *end; 3406 3407 /* Start toggle at 1. */ 3408 epipe->nexttoggle = 1; 3409 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3410 &next, &end); 3411 if (err) 3412 goto bad3; 3413 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3414 end->nextqtd = stat; 3415 end->qtd.qtd_next = 3416 end->qtd.qtd_altnext = htole32(stat->physaddr); 3417 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3418 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3419 } else { 3420 next = stat; 3421 } 3422 3423 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3424 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3425 3426 /* Clear toggle */ 3427 setup->qtd.qtd_status = htole32( 3428 EHCI_QTD_ACTIVE | 3429 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3430 EHCI_QTD_SET_CERR(3) | 3431 EHCI_QTD_SET_TOGGLE(0) | 3432 EHCI_QTD_SET_BYTES(sizeof *req) 3433 ); 3434 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3435 setup->qtd.qtd_buffer_hi[0] = 0; 3436 setup->nextqtd = next; 3437 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3438 setup->xfer = xfer; 3439 setup->len = sizeof *req; 3440 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3441 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3442 3443 stat->qtd.qtd_status = htole32( 3444 EHCI_QTD_ACTIVE | 3445 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3446 EHCI_QTD_SET_CERR(3) | 3447 EHCI_QTD_SET_TOGGLE(1) | 3448 EHCI_QTD_IOC 3449 ); 3450 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3451 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3452 stat->nextqtd = NULL; 3453 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3454 stat->xfer = xfer; 3455 stat->len = 0; 3456 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3457 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3458 3459 #ifdef EHCI_DEBUG 3460 if (ehcidebug > 5) { 3461 DPRINTF(("ehci_device_request:\n")); 3462 ehci_dump_sqh(sqh); 3463 ehci_dump_sqtds(setup); 3464 } 3465 #endif 3466 3467 exfer->sqtdstart = setup; 3468 exfer->sqtdend = stat; 3469 #ifdef DIAGNOSTIC 3470 if (!exfer->isdone) { 3471 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3472 } 3473 exfer->isdone = 0; 3474 #endif 3475 3476 /* Insert qTD in QH list. */ 3477 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3478 if (xfer->timeout && !sc->sc_bus.use_polling) { 3479 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3480 ehci_timeout, xfer); 3481 } 3482 ehci_add_intr_list(sc, exfer); 3483 xfer->status = USBD_IN_PROGRESS; 3484 mutex_exit(&sc->sc_lock); 3485 3486 #ifdef EHCI_DEBUG 3487 if (ehcidebug > 10) { 3488 DPRINTF(("ehci_device_request: status=%x\n", 3489 EOREAD4(sc, EHCI_USBSTS))); 3490 delay(10000); 3491 ehci_dump_regs(sc); 3492 ehci_dump_sqh(sc->sc_async_head); 3493 ehci_dump_sqh(sqh); 3494 ehci_dump_sqtds(setup); 3495 } 3496 #endif 3497 3498 return (USBD_NORMAL_COMPLETION); 3499 3500 bad3: 3501 mutex_exit(&sc->sc_lock); 3502 ehci_free_sqtd(sc, stat); 3503 bad2: 3504 ehci_free_sqtd(sc, setup); 3505 bad1: 3506 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3507 mutex_enter(&sc->sc_lock); 3508 xfer->status = err; 3509 usb_transfer_complete(xfer); 3510 mutex_exit(&sc->sc_lock); 3511 return (err); 3512 #undef exfer 3513 } 3514 3515 /* 3516 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3517 * qTD status, or miss signalling occasionally under heavy load. If the host 3518 * machine is too fast, we we can miss transaction completion - when we scan 3519 * the active list the transaction still seems to be active. This generally 3520 * exhibits itself as a umass stall that never recovers. 3521 * 3522 * We work around this behaviour by setting up this callback after any softintr 3523 * that completes with transactions still pending, giving us another chance to 3524 * check for completion after the writeback has taken place. 3525 */ 3526 Static void 3527 ehci_intrlist_timeout(void *arg) 3528 { 3529 ehci_softc_t *sc = arg; 3530 3531 DPRINTF(("ehci_intrlist_timeout\n")); 3532 usb_schedsoftintr(&sc->sc_bus); 3533 } 3534 3535 /************************/ 3536 3537 Static usbd_status 3538 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3539 { 3540 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3541 usbd_status err; 3542 3543 /* Insert last in queue. */ 3544 mutex_enter(&sc->sc_lock); 3545 err = usb_insert_transfer(xfer); 3546 mutex_exit(&sc->sc_lock); 3547 if (err) 3548 return (err); 3549 3550 /* Pipe isn't running, start first */ 3551 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3552 } 3553 3554 Static usbd_status 3555 ehci_device_bulk_start(usbd_xfer_handle xfer) 3556 { 3557 #define exfer EXFER(xfer) 3558 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3559 usbd_device_handle dev = epipe->pipe.device; 3560 ehci_softc_t *sc = dev->bus->hci_private; 3561 ehci_soft_qtd_t *data, *dataend; 3562 ehci_soft_qh_t *sqh; 3563 usbd_status err; 3564 int len, isread, endpt; 3565 3566 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3567 xfer, xfer->length, xfer->flags)); 3568 3569 if (sc->sc_dying) 3570 return (USBD_IOERROR); 3571 3572 #ifdef DIAGNOSTIC 3573 if (xfer->rqflags & URQ_REQUEST) 3574 panic("ehci_device_bulk_start: a request"); 3575 #endif 3576 3577 mutex_enter(&sc->sc_lock); 3578 3579 len = xfer->length; 3580 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3581 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3582 sqh = epipe->sqh; 3583 3584 epipe->u.bulk.length = len; 3585 3586 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3587 &dataend); 3588 if (err) { 3589 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3590 xfer->status = err; 3591 usb_transfer_complete(xfer); 3592 mutex_exit(&sc->sc_lock); 3593 return (err); 3594 } 3595 3596 #ifdef EHCI_DEBUG 3597 if (ehcidebug > 5) { 3598 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3599 ehci_dump_sqh(sqh); 3600 ehci_dump_sqtds(data); 3601 } 3602 #endif 3603 3604 /* Set up interrupt info. */ 3605 exfer->sqtdstart = data; 3606 exfer->sqtdend = dataend; 3607 #ifdef DIAGNOSTIC 3608 if (!exfer->isdone) { 3609 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3610 } 3611 exfer->isdone = 0; 3612 #endif 3613 3614 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3615 if (xfer->timeout && !sc->sc_bus.use_polling) { 3616 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3617 ehci_timeout, xfer); 3618 } 3619 ehci_add_intr_list(sc, exfer); 3620 xfer->status = USBD_IN_PROGRESS; 3621 mutex_exit(&sc->sc_lock); 3622 3623 #ifdef EHCI_DEBUG 3624 if (ehcidebug > 10) { 3625 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3626 delay(10000); 3627 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3628 ehci_dump_regs(sc); 3629 #if 0 3630 printf("async_head:\n"); 3631 ehci_dump_sqh(sc->sc_async_head); 3632 #endif 3633 printf("sqh:\n"); 3634 ehci_dump_sqh(sqh); 3635 ehci_dump_sqtds(data); 3636 } 3637 #endif 3638 3639 if (sc->sc_bus.use_polling) 3640 ehci_waitintr(sc, xfer); 3641 3642 return (USBD_IN_PROGRESS); 3643 #undef exfer 3644 } 3645 3646 Static void 3647 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3648 { 3649 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3650 ehci_abort_xfer(xfer, USBD_CANCELLED); 3651 } 3652 3653 /* 3654 * Close a device bulk pipe. 3655 */ 3656 Static void 3657 ehci_device_bulk_close(usbd_pipe_handle pipe) 3658 { 3659 ehci_softc_t *sc = pipe->device->bus->hci_private; 3660 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3661 3662 KASSERT(mutex_owned(&sc->sc_lock)); 3663 3664 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3665 pipe->endpoint->datatoggle = epipe->nexttoggle; 3666 ehci_close_pipe(pipe, sc->sc_async_head); 3667 } 3668 3669 Static void 3670 ehci_device_bulk_done(usbd_xfer_handle xfer) 3671 { 3672 struct ehci_xfer *ex = EXFER(xfer); 3673 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3674 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3675 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3676 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3677 3678 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3679 xfer, xfer->actlen)); 3680 3681 KASSERT(mutex_owned(&sc->sc_lock)); 3682 3683 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3684 ehci_del_intr_list(sc, ex); /* remove from active list */ 3685 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3686 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3687 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3688 } 3689 3690 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3691 } 3692 3693 /************************/ 3694 3695 Static usbd_status 3696 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3697 { 3698 struct ehci_soft_islot *isp; 3699 int islot, lev; 3700 3701 /* Find a poll rate that is large enough. */ 3702 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3703 if (EHCI_ILEV_IVAL(lev) <= ival) 3704 break; 3705 3706 /* Pick an interrupt slot at the right level. */ 3707 /* XXX could do better than picking at random */ 3708 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3709 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3710 3711 sqh->islot = islot; 3712 isp = &sc->sc_islots[islot]; 3713 mutex_enter(&sc->sc_lock); 3714 ehci_add_qh(sc, sqh, isp->sqh); 3715 mutex_exit(&sc->sc_lock); 3716 3717 return (USBD_NORMAL_COMPLETION); 3718 } 3719 3720 Static usbd_status 3721 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3722 { 3723 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3724 usbd_status err; 3725 3726 /* Insert last in queue. */ 3727 mutex_enter(&sc->sc_lock); 3728 err = usb_insert_transfer(xfer); 3729 mutex_exit(&sc->sc_lock); 3730 if (err) 3731 return (err); 3732 3733 /* 3734 * Pipe isn't running (otherwise err would be USBD_INPROG), 3735 * so start it first. 3736 */ 3737 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3738 } 3739 3740 Static usbd_status 3741 ehci_device_intr_start(usbd_xfer_handle xfer) 3742 { 3743 #define exfer EXFER(xfer) 3744 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3745 usbd_device_handle dev = xfer->pipe->device; 3746 ehci_softc_t *sc = dev->bus->hci_private; 3747 ehci_soft_qtd_t *data, *dataend; 3748 ehci_soft_qh_t *sqh; 3749 usbd_status err; 3750 int len, isread, endpt; 3751 3752 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3753 xfer, xfer->length, xfer->flags)); 3754 3755 if (sc->sc_dying) 3756 return (USBD_IOERROR); 3757 3758 #ifdef DIAGNOSTIC 3759 if (xfer->rqflags & URQ_REQUEST) 3760 panic("ehci_device_intr_start: a request"); 3761 #endif 3762 3763 mutex_enter(&sc->sc_lock); 3764 3765 len = xfer->length; 3766 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3767 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3768 sqh = epipe->sqh; 3769 3770 epipe->u.intr.length = len; 3771 3772 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3773 &dataend); 3774 if (err) { 3775 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3776 xfer->status = err; 3777 usb_transfer_complete(xfer); 3778 mutex_exit(&sc->sc_lock); 3779 return (err); 3780 } 3781 3782 #ifdef EHCI_DEBUG 3783 if (ehcidebug > 5) { 3784 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3785 ehci_dump_sqh(sqh); 3786 ehci_dump_sqtds(data); 3787 } 3788 #endif 3789 3790 /* Set up interrupt info. */ 3791 exfer->sqtdstart = data; 3792 exfer->sqtdend = dataend; 3793 #ifdef DIAGNOSTIC 3794 if (!exfer->isdone) { 3795 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3796 } 3797 exfer->isdone = 0; 3798 #endif 3799 3800 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3801 if (xfer->timeout && !sc->sc_bus.use_polling) { 3802 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3803 ehci_timeout, xfer); 3804 } 3805 ehci_add_intr_list(sc, exfer); 3806 xfer->status = USBD_IN_PROGRESS; 3807 mutex_exit(&sc->sc_lock); 3808 3809 #ifdef EHCI_DEBUG 3810 if (ehcidebug > 10) { 3811 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3812 delay(10000); 3813 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3814 ehci_dump_regs(sc); 3815 printf("sqh:\n"); 3816 ehci_dump_sqh(sqh); 3817 ehci_dump_sqtds(data); 3818 } 3819 #endif 3820 3821 if (sc->sc_bus.use_polling) 3822 ehci_waitintr(sc, xfer); 3823 3824 return (USBD_IN_PROGRESS); 3825 #undef exfer 3826 } 3827 3828 Static void 3829 ehci_device_intr_abort(usbd_xfer_handle xfer) 3830 { 3831 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3832 if (xfer->pipe->intrxfer == xfer) { 3833 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3834 xfer->pipe->intrxfer = NULL; 3835 } 3836 /* 3837 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3838 * async doorbell. That's dependent on the async list, wheras 3839 * intr xfers are periodic, should not use this? 3840 */ 3841 ehci_abort_xfer(xfer, USBD_CANCELLED); 3842 } 3843 3844 Static void 3845 ehci_device_intr_close(usbd_pipe_handle pipe) 3846 { 3847 ehci_softc_t *sc = pipe->device->bus->hci_private; 3848 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3849 struct ehci_soft_islot *isp; 3850 3851 KASSERT(mutex_owned(&sc->sc_lock)); 3852 3853 isp = &sc->sc_islots[epipe->sqh->islot]; 3854 ehci_close_pipe(pipe, isp->sqh); 3855 } 3856 3857 Static void 3858 ehci_device_intr_done(usbd_xfer_handle xfer) 3859 { 3860 #define exfer EXFER(xfer) 3861 struct ehci_xfer *ex = EXFER(xfer); 3862 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3863 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3864 ehci_soft_qtd_t *data, *dataend; 3865 ehci_soft_qh_t *sqh; 3866 usbd_status err; 3867 int len, isread, endpt; 3868 3869 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3870 xfer, xfer->actlen)); 3871 3872 KASSERT(mutex_owned(&sc->sc_lock)); 3873 3874 if (xfer->pipe->repeat) { 3875 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3876 3877 len = epipe->u.intr.length; 3878 xfer->length = len; 3879 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3880 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3881 usb_syncmem(&xfer->dmabuf, 0, len, 3882 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3883 sqh = epipe->sqh; 3884 3885 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3886 &data, &dataend); 3887 if (err) { 3888 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3889 xfer->status = err; 3890 return; 3891 } 3892 3893 /* Set up interrupt info. */ 3894 exfer->sqtdstart = data; 3895 exfer->sqtdend = dataend; 3896 #ifdef DIAGNOSTIC 3897 if (!exfer->isdone) { 3898 printf("ehci_device_intr_done: not done, ex=%p\n", 3899 exfer); 3900 } 3901 exfer->isdone = 0; 3902 #endif 3903 3904 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3905 if (xfer->timeout && !sc->sc_bus.use_polling) { 3906 callout_reset(&xfer->timeout_handle, 3907 mstohz(xfer->timeout), ehci_timeout, xfer); 3908 } 3909 3910 xfer->status = USBD_IN_PROGRESS; 3911 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3912 ehci_del_intr_list(sc, ex); /* remove from active list */ 3913 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3914 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3915 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3916 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3917 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3918 } 3919 #undef exfer 3920 } 3921 3922 /************************/ 3923 3924 Static usbd_status 3925 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3926 { 3927 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3928 usbd_status err; 3929 3930 mutex_enter(&sc->sc_lock); 3931 err = usb_insert_transfer(xfer); 3932 mutex_exit(&sc->sc_lock); 3933 if (err && err != USBD_IN_PROGRESS) 3934 return err; 3935 3936 return ehci_device_isoc_start(xfer); 3937 } 3938 3939 Static usbd_status 3940 ehci_device_isoc_start(usbd_xfer_handle xfer) 3941 { 3942 struct ehci_pipe *epipe; 3943 usbd_device_handle dev; 3944 ehci_softc_t *sc; 3945 struct ehci_xfer *exfer; 3946 ehci_soft_itd_t *itd, *prev, *start, *stop; 3947 usb_dma_t *dma_buf; 3948 int i, j, k, frames, uframes, ufrperframe; 3949 int trans_count, offs, total_length; 3950 int frindex; 3951 3952 start = NULL; 3953 prev = NULL; 3954 itd = NULL; 3955 trans_count = 0; 3956 total_length = 0; 3957 exfer = (struct ehci_xfer *) xfer; 3958 sc = xfer->pipe->device->bus->hci_private; 3959 dev = xfer->pipe->device; 3960 epipe = (struct ehci_pipe *)xfer->pipe; 3961 3962 /* 3963 * To allow continuous transfers, above we start all transfers 3964 * immediately. However, we're still going to get usbd_start_next call 3965 * this when another xfer completes. So, check if this is already 3966 * in progress or not 3967 */ 3968 3969 if (exfer->itdstart != NULL) 3970 return USBD_IN_PROGRESS; 3971 3972 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3973 xfer, xfer->length, xfer->flags)); 3974 3975 if (sc->sc_dying) 3976 return USBD_IOERROR; 3977 3978 /* 3979 * To avoid complication, don't allow a request right now that'll span 3980 * the entire frame table. To within 4 frames, to allow some leeway 3981 * on either side of where the hc currently is. 3982 */ 3983 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3984 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3985 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3986 return USBD_INVAL; 3987 } 3988 3989 #ifdef DIAGNOSTIC 3990 if (xfer->rqflags & URQ_REQUEST) 3991 panic("ehci_device_isoc_start: request\n"); 3992 3993 if (!exfer->isdone) 3994 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3995 exfer->isdone = 0; 3996 #endif 3997 3998 /* 3999 * Step 1: Allocate and initialize itds, how many do we need? 4000 * One per transfer if interval >= 8 microframes, fewer if we use 4001 * multiple microframes per frame. 4002 */ 4003 4004 i = epipe->pipe.endpoint->edesc->bInterval; 4005 if (i > 16 || i == 0) { 4006 /* Spec page 271 says intervals > 16 are invalid */ 4007 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 4008 return USBD_INVAL; 4009 } 4010 4011 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4012 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4013 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4014 4015 if (frames == 0) { 4016 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 4017 return USBD_INVAL; 4018 } 4019 4020 dma_buf = &xfer->dmabuf; 4021 offs = 0; 4022 4023 for (i = 0; i < frames; i++) { 4024 int froffs = offs; 4025 itd = ehci_alloc_itd(sc); 4026 4027 if (prev != NULL) { 4028 prev->itd.itd_next = 4029 htole32(itd->physaddr | EHCI_LINK_ITD); 4030 usb_syncmem(&itd->dma, 4031 itd->offs + offsetof(ehci_itd_t, itd_next), 4032 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4033 4034 prev->xfer_next = itd; 4035 } else { 4036 start = itd; 4037 } 4038 4039 /* 4040 * Step 1.5, initialize uframes 4041 */ 4042 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4043 /* Calculate which page in the list this starts in */ 4044 int addr = DMAADDR(dma_buf, froffs); 4045 addr = EHCI_PAGE_OFFSET(addr); 4046 addr += (offs - froffs); 4047 addr = EHCI_PAGE(addr); 4048 addr /= EHCI_PAGE_SIZE; 4049 4050 /* This gets the initial offset into the first page, 4051 * looks how far further along the current uframe 4052 * offset is. Works out how many pages that is. 4053 */ 4054 4055 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4056 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4057 EHCI_ITD_SET_PG(addr) | 4058 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4059 4060 total_length += xfer->frlengths[trans_count]; 4061 offs += xfer->frlengths[trans_count]; 4062 trans_count++; 4063 4064 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4065 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4066 break; 4067 } 4068 } 4069 4070 /* Step 1.75, set buffer pointers. To simplify matters, all 4071 * pointers are filled out for the next 7 hardware pages in 4072 * the dma block, so no need to worry what pages to cover 4073 * and what to not. 4074 */ 4075 4076 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4077 /* 4078 * Don't try to lookup a page that's past the end 4079 * of buffer 4080 */ 4081 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4082 if (page_offs >= dma_buf->block->size) 4083 break; 4084 4085 unsigned long long page = DMAADDR(dma_buf, page_offs); 4086 page = EHCI_PAGE(page); 4087 itd->itd.itd_bufr[j] = 4088 htole32(EHCI_ITD_SET_BPTR(page)); 4089 itd->itd.itd_bufr_hi[j] = 4090 htole32(page >> 32); 4091 } 4092 4093 /* 4094 * Other special values 4095 */ 4096 4097 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4098 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4099 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4100 4101 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4102 ? 1 : 0; 4103 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4104 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4105 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4106 4107 /* FIXME: handle invalid trans */ 4108 itd->itd.itd_bufr[2] |= 4109 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4110 4111 usb_syncmem(&itd->dma, 4112 itd->offs + offsetof(ehci_itd_t, itd_next), 4113 sizeof(ehci_itd_t), 4114 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4115 4116 prev = itd; 4117 } /* End of frame */ 4118 4119 stop = itd; 4120 stop->xfer_next = NULL; 4121 exfer->isoc_len = total_length; 4122 4123 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4124 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4125 4126 /* 4127 * Part 2: Transfer descriptors have now been set up, now they must 4128 * be scheduled into the period frame list. Erk. Not wanting to 4129 * complicate matters, transfer is denied if the transfer spans 4130 * more than the period frame list. 4131 */ 4132 4133 mutex_enter(&sc->sc_lock); 4134 4135 /* Start inserting frames */ 4136 if (epipe->u.isoc.cur_xfers > 0) { 4137 frindex = epipe->u.isoc.next_frame; 4138 } else { 4139 frindex = EOREAD4(sc, EHCI_FRINDEX); 4140 frindex = frindex >> 3; /* Erase microframe index */ 4141 frindex += 2; 4142 } 4143 4144 if (frindex >= sc->sc_flsize) 4145 frindex &= (sc->sc_flsize - 1); 4146 4147 /* What's the frame interval? */ 4148 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4149 if (i / USB_UFRAMES_PER_FRAME == 0) 4150 i = 1; 4151 else 4152 i /= USB_UFRAMES_PER_FRAME; 4153 4154 itd = start; 4155 for (j = 0; j < frames; j++) { 4156 if (itd == NULL) 4157 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4158 4159 itd->itd.itd_next = sc->sc_flist[frindex]; 4160 if (itd->itd.itd_next == 0) 4161 /* FIXME: frindex table gets initialized to NULL 4162 * or EHCI_NULL? */ 4163 itd->itd.itd_next = EHCI_NULL; 4164 4165 usb_syncmem(&itd->dma, 4166 itd->offs + offsetof(ehci_itd_t, itd_next), 4167 sizeof(itd->itd.itd_next), 4168 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4169 4170 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4171 4172 usb_syncmem(&sc->sc_fldma, 4173 sizeof(ehci_link_t) * frindex, 4174 sizeof(ehci_link_t), 4175 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4176 4177 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4178 sc->sc_softitds[frindex] = itd; 4179 if (itd->u.frame_list.next != NULL) 4180 itd->u.frame_list.next->u.frame_list.prev = itd; 4181 itd->slot = frindex; 4182 itd->u.frame_list.prev = NULL; 4183 4184 frindex += i; 4185 if (frindex >= sc->sc_flsize) 4186 frindex -= sc->sc_flsize; 4187 4188 itd = itd->xfer_next; 4189 } 4190 4191 epipe->u.isoc.cur_xfers++; 4192 epipe->u.isoc.next_frame = frindex; 4193 4194 exfer->itdstart = start; 4195 exfer->itdend = stop; 4196 exfer->sqtdstart = NULL; 4197 exfer->sqtdstart = NULL; 4198 4199 ehci_add_intr_list(sc, exfer); 4200 xfer->status = USBD_IN_PROGRESS; 4201 xfer->done = 0; 4202 mutex_exit(&sc->sc_lock); 4203 4204 if (sc->sc_bus.use_polling) { 4205 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4206 ehci_waitintr(sc, xfer); 4207 } 4208 4209 return USBD_IN_PROGRESS; 4210 } 4211 4212 Static void 4213 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4214 { 4215 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4216 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4217 } 4218 4219 Static void 4220 ehci_device_isoc_close(usbd_pipe_handle pipe) 4221 { 4222 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4223 } 4224 4225 Static void 4226 ehci_device_isoc_done(usbd_xfer_handle xfer) 4227 { 4228 struct ehci_xfer *exfer; 4229 ehci_softc_t *sc; 4230 struct ehci_pipe *epipe; 4231 4232 exfer = EXFER(xfer); 4233 sc = xfer->pipe->device->bus->hci_private; 4234 epipe = (struct ehci_pipe *) xfer->pipe; 4235 4236 KASSERT(mutex_owned(&sc->sc_lock)); 4237 4238 epipe->u.isoc.cur_xfers--; 4239 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4240 ehci_del_intr_list(sc, exfer); 4241 ehci_rem_free_itd_chain(sc, exfer); 4242 } 4243 4244 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4245 BUS_DMASYNC_POSTREAD); 4246 4247 } 4248
Indexes created Tue Sep 23 14:10:03 GMT 2025