ehci.c revision 1.211
1 /* $NetBSD: ehci.c,v 1.211 2013/09/07 19:53:24 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.211 2013/09/07 19:53:24 matt Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/kernel.h> 64 #include <sys/kmem.h> 65 #include <sys/device.h> 66 #include <sys/select.h> 67 #include <sys/proc.h> 68 #include <sys/queue.h> 69 #include <sys/mutex.h> 70 #include <sys/bus.h> 71 #include <sys/cpu.h> 72 73 #include <machine/endian.h> 74 75 #include <dev/usb/usb.h> 76 #include <dev/usb/usbdi.h> 77 #include <dev/usb/usbdivar.h> 78 #include <dev/usb/usb_mem.h> 79 #include <dev/usb/usb_quirks.h> 80 81 #include <dev/usb/ehcireg.h> 82 #include <dev/usb/ehcivar.h> 83 #include <dev/usb/usbroothub_subr.h> 84 85 #ifdef EHCI_DEBUG 86 static void __printflike(1, 2) 87 ehciprintf(const char *fmt, ...) 88 { 89 va_list ap; 90 91 va_start(ap, fmt); 92 vprintf(fmt, ap); 93 va_end(ap); 94 } 95 96 #define DPRINTF(x) do { if (ehcidebug) ehciprintf x; } while(0) 97 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) ehciprintf x; } while (0) 98 int ehcidebug = 0; 99 #else 100 #define DPRINTF(x) 101 #define DPRINTFN(n,x) 102 #endif 103 104 struct ehci_pipe { 105 struct usbd_pipe pipe; 106 int nexttoggle; 107 108 ehci_soft_qh_t *sqh; 109 union { 110 ehci_soft_qtd_t *qtd; 111 /* ehci_soft_itd_t *itd; */ 112 } tail; 113 union { 114 /* Control pipe */ 115 struct { 116 usb_dma_t reqdma; 117 } ctl; 118 /* Interrupt pipe */ 119 struct { 120 u_int length; 121 } intr; 122 /* Bulk pipe */ 123 struct { 124 u_int length; 125 } bulk; 126 /* Iso pipe */ 127 struct { 128 u_int next_frame; 129 u_int cur_xfers; 130 } isoc; 131 } u; 132 }; 133 134 Static usbd_status ehci_open(usbd_pipe_handle); 135 Static void ehci_poll(struct usbd_bus *); 136 Static void ehci_softintr(void *); 137 Static int ehci_intr1(ehci_softc_t *); 138 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 139 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 140 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 141 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 142 Static void ehci_idone(struct ehci_xfer *); 143 Static void ehci_timeout(void *); 144 Static void ehci_timeout_task(void *); 145 Static void ehci_intrlist_timeout(void *); 146 Static void ehci_doorbell(void *); 147 Static void ehci_pcd(void *); 148 149 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 150 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 151 152 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 153 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 154 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 155 156 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 157 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 158 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 159 Static void ehci_root_ctrl_close(usbd_pipe_handle); 160 Static void ehci_root_ctrl_done(usbd_xfer_handle); 161 162 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 163 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 164 Static void ehci_root_intr_abort(usbd_xfer_handle); 165 Static void ehci_root_intr_close(usbd_pipe_handle); 166 Static void ehci_root_intr_done(usbd_xfer_handle); 167 168 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 169 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 170 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 171 Static void ehci_device_ctrl_close(usbd_pipe_handle); 172 Static void ehci_device_ctrl_done(usbd_xfer_handle); 173 174 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 175 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 176 Static void ehci_device_bulk_abort(usbd_xfer_handle); 177 Static void ehci_device_bulk_close(usbd_pipe_handle); 178 Static void ehci_device_bulk_done(usbd_xfer_handle); 179 180 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 181 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 182 Static void ehci_device_intr_abort(usbd_xfer_handle); 183 Static void ehci_device_intr_close(usbd_pipe_handle); 184 Static void ehci_device_intr_done(usbd_xfer_handle); 185 186 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 187 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 188 Static void ehci_device_isoc_abort(usbd_xfer_handle); 189 Static void ehci_device_isoc_close(usbd_pipe_handle); 190 Static void ehci_device_isoc_done(usbd_xfer_handle); 191 192 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 193 Static void ehci_noop(usbd_pipe_handle pipe); 194 195 Static void ehci_disown(ehci_softc_t *, int, int); 196 197 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 198 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 199 200 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 201 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 202 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 203 ehci_softc_t *, int, int, usbd_xfer_handle, 204 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 205 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 206 ehci_soft_qtd_t *); 207 208 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 209 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 210 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 211 struct ehci_xfer *exfer); 212 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 213 usbd_status status); 214 215 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 216 217 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 218 int ival); 219 220 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 221 ehci_soft_qh_t *); 222 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 223 ehci_soft_qh_t *); 224 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 225 Static void ehci_sync_hc(ehci_softc_t *); 226 227 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 228 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 229 230 #ifdef EHCI_DEBUG 231 Static void ehci_dump_regs(ehci_softc_t *); 232 void ehci_dump(void); 233 Static ehci_softc_t *theehci; 234 Static void ehci_dump_link(ehci_link_t, int); 235 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 236 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 237 Static void ehci_dump_qtd(ehci_qtd_t *); 238 Static void ehci_dump_sqh(ehci_soft_qh_t *); 239 #if notyet 240 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 241 Static void ehci_dump_itd(struct ehci_soft_itd *); 242 #endif 243 #ifdef DIAGNOSTIC 244 Static void ehci_dump_exfer(struct ehci_xfer *); 245 #endif 246 #endif 247 248 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 249 250 #define EHCI_INTR_ENDPT 1 251 252 #define ehci_add_intr_list(sc, ex) \ 253 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 254 #define ehci_del_intr_list(sc, ex) \ 255 do { \ 256 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 257 (ex)->inext.tqe_prev = NULL; \ 258 } while (0) 259 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 260 261 Static const struct usbd_bus_methods ehci_bus_methods = { 262 .open_pipe = ehci_open, 263 .soft_intr = ehci_softintr, 264 .do_poll = ehci_poll, 265 .allocm = ehci_allocm, 266 .freem = ehci_freem, 267 .allocx = ehci_allocx, 268 .freex = ehci_freex, 269 .get_lock = ehci_get_lock, 270 }; 271 272 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 273 .transfer = ehci_root_ctrl_transfer, 274 .start = ehci_root_ctrl_start, 275 .abort = ehci_root_ctrl_abort, 276 .close = ehci_root_ctrl_close, 277 .cleartoggle = ehci_noop, 278 .done = ehci_root_ctrl_done, 279 }; 280 281 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 282 .transfer = ehci_root_intr_transfer, 283 .start = ehci_root_intr_start, 284 .abort = ehci_root_intr_abort, 285 .close = ehci_root_intr_close, 286 .cleartoggle = ehci_noop, 287 .done = ehci_root_intr_done, 288 }; 289 290 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 291 .transfer = ehci_device_ctrl_transfer, 292 .start = ehci_device_ctrl_start, 293 .abort = ehci_device_ctrl_abort, 294 .close = ehci_device_ctrl_close, 295 .cleartoggle = ehci_noop, 296 .done = ehci_device_ctrl_done, 297 }; 298 299 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 300 .transfer = ehci_device_intr_transfer, 301 .start = ehci_device_intr_start, 302 .abort = ehci_device_intr_abort, 303 .close = ehci_device_intr_close, 304 .cleartoggle = ehci_device_clear_toggle, 305 .done = ehci_device_intr_done, 306 }; 307 308 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 309 .transfer = ehci_device_bulk_transfer, 310 .start = ehci_device_bulk_start, 311 .abort = ehci_device_bulk_abort, 312 .close = ehci_device_bulk_close, 313 .cleartoggle = ehci_device_clear_toggle, 314 .done = ehci_device_bulk_done, 315 }; 316 317 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 318 .transfer = ehci_device_isoc_transfer, 319 .start = ehci_device_isoc_start, 320 .abort = ehci_device_isoc_abort, 321 .close = ehci_device_isoc_close, 322 .cleartoggle = ehci_noop, 323 .done = ehci_device_isoc_done, 324 }; 325 326 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 327 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 328 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 329 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 330 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 331 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 332 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 333 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 334 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 335 }; 336 337 usbd_status 338 ehci_init(ehci_softc_t *sc) 339 { 340 u_int32_t vers, sparams, cparams, hcr; 341 u_int i; 342 usbd_status err; 343 ehci_soft_qh_t *sqh; 344 u_int ncomp; 345 346 DPRINTF(("ehci_init: start\n")); 347 #ifdef EHCI_DEBUG 348 theehci = sc; 349 #endif 350 351 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 352 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 353 cv_init(&sc->sc_softwake_cv, "ehciab"); 354 cv_init(&sc->sc_doorbell, "ehcidi"); 355 356 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 357 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 358 359 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 360 ehci_doorbell, sc); 361 KASSERT(sc->sc_doorbell_si != NULL); 362 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 363 ehci_pcd, sc); 364 KASSERT(sc->sc_pcd_si != NULL); 365 366 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 367 368 vers = EREAD2(sc, EHCI_HCIVERSION); 369 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 370 vers >> 8, vers & 0xff); 371 372 sparams = EREAD4(sc, EHCI_HCSPARAMS); 373 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 374 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 375 ncomp = EHCI_HCS_N_CC(sparams); 376 if (ncomp != sc->sc_ncomp) { 377 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 378 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 379 #if NOHCI == 0 || NUHCI == 0 380 aprint_error("%s: ohci or uhci probably not configured\n", 381 device_xname(sc->sc_dev)); 382 #endif 383 if (ncomp < sc->sc_ncomp) 384 sc->sc_ncomp = ncomp; 385 } 386 if (sc->sc_ncomp > 0) { 387 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 388 aprint_normal("%s: companion controller%s, %d port%s each:", 389 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 390 EHCI_HCS_N_PCC(sparams), 391 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 392 for (i = 0; i < sc->sc_ncomp; i++) 393 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 394 aprint_normal("\n"); 395 } 396 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 397 cparams = EREAD4(sc, EHCI_HCCPARAMS); 398 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 399 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 400 401 if (EHCI_HCC_64BIT(cparams)) { 402 /* MUST clear segment register if 64 bit capable. */ 403 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 404 } 405 406 sc->sc_bus.usbrev = USBREV_2_0; 407 408 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 409 USB_MEM_RESERVE); 410 411 /* Reset the controller */ 412 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 413 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 414 usb_delay_ms(&sc->sc_bus, 1); 415 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 416 for (i = 0; i < 100; i++) { 417 usb_delay_ms(&sc->sc_bus, 1); 418 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 419 if (!hcr) 420 break; 421 } 422 if (hcr) { 423 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 424 return (USBD_IOERROR); 425 } 426 if (sc->sc_vendor_init) 427 sc->sc_vendor_init(sc); 428 429 /* 430 * If we are doing embedded transaction translation function, force 431 * the controller to host mode. 432 */ 433 if (sc->sc_flags & EHCIF_ETTF) { 434 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 435 usbmode &= ~EHCI_USBMODE_CM; 436 usbmode |= EHCI_USBMODE_CM_HOST; 437 EWRITE4(sc, EHCI_USBMODE, usbmode); 438 } 439 440 /* XXX need proper intr scheduling */ 441 sc->sc_rand = 96; 442 443 /* frame list size at default, read back what we got and use that */ 444 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 445 case 0: sc->sc_flsize = 1024; break; 446 case 1: sc->sc_flsize = 512; break; 447 case 2: sc->sc_flsize = 256; break; 448 case 3: return (USBD_IOERROR); 449 } 450 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 451 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 452 if (err) 453 return (err); 454 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 455 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 456 457 for (i = 0; i < sc->sc_flsize; i++) { 458 sc->sc_flist[i] = EHCI_NULL; 459 } 460 461 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 462 463 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 464 KM_SLEEP); 465 if (sc->sc_softitds == NULL) 466 return ENOMEM; 467 LIST_INIT(&sc->sc_freeitds); 468 TAILQ_INIT(&sc->sc_intrhead); 469 470 /* Set up the bus struct. */ 471 sc->sc_bus.methods = &ehci_bus_methods; 472 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 473 474 sc->sc_eintrs = EHCI_NORMAL_INTRS; 475 476 /* 477 * Allocate the interrupt dummy QHs. These are arranged to give poll 478 * intervals that are powers of 2 times 1ms. 479 */ 480 for (i = 0; i < EHCI_INTRQHS; i++) { 481 sqh = ehci_alloc_sqh(sc); 482 if (sqh == NULL) { 483 err = USBD_NOMEM; 484 goto bad1; 485 } 486 sc->sc_islots[i].sqh = sqh; 487 } 488 for (i = 0; i < EHCI_INTRQHS; i++) { 489 sqh = sc->sc_islots[i].sqh; 490 if (i == 0) { 491 /* The last (1ms) QH terminates. */ 492 sqh->qh.qh_link = EHCI_NULL; 493 sqh->next = NULL; 494 } else { 495 /* Otherwise the next QH has half the poll interval */ 496 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 497 sqh->qh.qh_link = htole32(sqh->next->physaddr | 498 EHCI_LINK_QH); 499 } 500 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 501 sqh->qh.qh_curqtd = EHCI_NULL; 502 sqh->next = NULL; 503 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 504 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 505 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 506 sqh->sqtd = NULL; 507 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 508 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 509 } 510 /* Point the frame list at the last level (128ms). */ 511 for (i = 0; i < sc->sc_flsize; i++) { 512 int j; 513 514 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 515 revbits[i & (EHCI_MAX_POLLRATE-1)]; 516 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 517 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 518 i)].sqh->physaddr); 519 } 520 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 521 BUS_DMASYNC_PREWRITE); 522 523 /* Allocate dummy QH that starts the async list. */ 524 sqh = ehci_alloc_sqh(sc); 525 if (sqh == NULL) { 526 err = USBD_NOMEM; 527 goto bad1; 528 } 529 /* Fill the QH */ 530 sqh->qh.qh_endp = 531 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 532 sqh->qh.qh_link = 533 htole32(sqh->physaddr | EHCI_LINK_QH); 534 sqh->qh.qh_curqtd = EHCI_NULL; 535 sqh->next = NULL; 536 /* Fill the overlay qTD */ 537 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 538 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 539 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 540 sqh->sqtd = NULL; 541 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 542 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 543 #ifdef EHCI_DEBUG 544 if (ehcidebug) { 545 ehci_dump_sqh(sqh); 546 } 547 #endif 548 549 /* Point to async list */ 550 sc->sc_async_head = sqh; 551 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 552 553 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 554 555 /* Turn on controller */ 556 EOWRITE4(sc, EHCI_USBCMD, 557 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 558 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 559 EHCI_CMD_ASE | 560 EHCI_CMD_PSE | 561 EHCI_CMD_RS); 562 563 /* Take over port ownership */ 564 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 565 566 for (i = 0; i < 100; i++) { 567 usb_delay_ms(&sc->sc_bus, 1); 568 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 569 if (!hcr) 570 break; 571 } 572 if (hcr) { 573 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 574 return (USBD_IOERROR); 575 } 576 577 /* Enable interrupts */ 578 DPRINTFN(1,("ehci_init: enabling\n")); 579 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 580 581 return (USBD_NORMAL_COMPLETION); 582 583 #if 0 584 bad2: 585 ehci_free_sqh(sc, sc->sc_async_head); 586 #endif 587 bad1: 588 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 589 return (err); 590 } 591 592 int 593 ehci_intr(void *v) 594 { 595 ehci_softc_t *sc = v; 596 int ret = 0; 597 598 if (sc == NULL) 599 return 0; 600 601 mutex_spin_enter(&sc->sc_intr_lock); 602 603 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 604 goto done; 605 606 /* If we get an interrupt while polling, then just ignore it. */ 607 if (sc->sc_bus.use_polling) { 608 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 609 610 if (intrs) 611 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 612 #ifdef DIAGNOSTIC 613 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 614 #endif 615 goto done; 616 } 617 618 ret = ehci_intr1(sc); 619 620 done: 621 mutex_spin_exit(&sc->sc_intr_lock); 622 return ret; 623 } 624 625 Static int 626 ehci_intr1(ehci_softc_t *sc) 627 { 628 u_int32_t intrs, eintrs; 629 630 DPRINTFN(20,("ehci_intr1: enter\n")); 631 632 /* In case the interrupt occurs before initialization has completed. */ 633 if (sc == NULL) { 634 #ifdef DIAGNOSTIC 635 printf("ehci_intr1: sc == NULL\n"); 636 #endif 637 return (0); 638 } 639 640 KASSERT(mutex_owned(&sc->sc_intr_lock)); 641 642 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 643 if (!intrs) 644 return (0); 645 646 eintrs = intrs & sc->sc_eintrs; 647 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 648 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 649 (u_int)eintrs)); 650 if (!eintrs) 651 return (0); 652 653 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 654 sc->sc_bus.no_intrs++; 655 if (eintrs & EHCI_STS_IAA) { 656 DPRINTF(("ehci_intr1: door bell\n")); 657 kpreempt_disable(); 658 KASSERT(sc->sc_doorbell_si != NULL); 659 softint_schedule(sc->sc_doorbell_si); 660 kpreempt_enable(); 661 eintrs &= ~EHCI_STS_IAA; 662 } 663 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 664 DPRINTFN(5,("ehci_intr1: %s %s\n", 665 eintrs & EHCI_STS_INT ? "INT" : "", 666 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 667 usb_schedsoftintr(&sc->sc_bus); 668 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 669 } 670 if (eintrs & EHCI_STS_HSE) { 671 printf("%s: unrecoverable error, controller halted\n", 672 device_xname(sc->sc_dev)); 673 /* XXX what else */ 674 } 675 if (eintrs & EHCI_STS_PCD) { 676 kpreempt_disable(); 677 KASSERT(sc->sc_pcd_si != NULL); 678 softint_schedule(sc->sc_pcd_si); 679 kpreempt_enable(); 680 eintrs &= ~EHCI_STS_PCD; 681 } 682 683 if (eintrs != 0) { 684 /* Block unprocessed interrupts. */ 685 sc->sc_eintrs &= ~eintrs; 686 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 687 printf("%s: blocking intrs 0x%x\n", 688 device_xname(sc->sc_dev), eintrs); 689 } 690 691 return (1); 692 } 693 694 Static void 695 ehci_doorbell(void *addr) 696 { 697 ehci_softc_t *sc = addr; 698 699 mutex_enter(&sc->sc_lock); 700 cv_broadcast(&sc->sc_doorbell); 701 mutex_exit(&sc->sc_lock); 702 } 703 704 Static void 705 ehci_pcd(void *addr) 706 { 707 ehci_softc_t *sc = addr; 708 usbd_xfer_handle xfer; 709 usbd_pipe_handle pipe; 710 u_char *p; 711 int i, m; 712 713 mutex_enter(&sc->sc_lock); 714 xfer = sc->sc_intrxfer; 715 716 if (xfer == NULL) { 717 /* Just ignore the change. */ 718 goto done; 719 } 720 721 pipe = xfer->pipe; 722 723 p = KERNADDR(&xfer->dmabuf, 0); 724 m = min(sc->sc_noport, xfer->length * 8 - 1); 725 memset(p, 0, xfer->length); 726 for (i = 1; i <= m; i++) { 727 /* Pick out CHANGE bits from the status reg. */ 728 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 729 p[i/8] |= 1 << (i%8); 730 } 731 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 732 xfer->actlen = xfer->length; 733 xfer->status = USBD_NORMAL_COMPLETION; 734 735 usb_transfer_complete(xfer); 736 737 done: 738 mutex_exit(&sc->sc_lock); 739 } 740 741 Static void 742 ehci_softintr(void *v) 743 { 744 struct usbd_bus *bus = v; 745 ehci_softc_t *sc = bus->hci_private; 746 struct ehci_xfer *ex, *nextex; 747 748 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 749 750 DPRINTFN(10,("%s: ehci_softintr\n", device_xname(sc->sc_dev))); 751 752 /* 753 * The only explanation I can think of for why EHCI is as brain dead 754 * as UHCI interrupt-wise is that Intel was involved in both. 755 * An interrupt just tells us that something is done, we have no 756 * clue what, so we need to scan through all active transfers. :-( 757 */ 758 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 759 nextex = TAILQ_NEXT(ex, inext); 760 ehci_check_intr(sc, ex); 761 } 762 763 /* Schedule a callout to catch any dropped transactions. */ 764 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 765 !TAILQ_EMPTY(&sc->sc_intrhead)) 766 callout_reset(&sc->sc_tmo_intrlist, 767 hz, ehci_intrlist_timeout, sc); 768 769 if (sc->sc_softwake) { 770 sc->sc_softwake = 0; 771 cv_broadcast(&sc->sc_softwake_cv); 772 } 773 } 774 775 /* Check for an interrupt. */ 776 Static void 777 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 778 { 779 int attr; 780 781 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 782 783 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 784 785 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 786 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 787 ehci_check_itd_intr(sc, ex); 788 else 789 ehci_check_qh_intr(sc, ex); 790 791 return; 792 } 793 794 Static void 795 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 796 { 797 ehci_soft_qtd_t *sqtd, *lsqtd; 798 __uint32_t status; 799 800 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 801 802 if (ex->sqtdstart == NULL) { 803 printf("ehci_check_qh_intr: not valid sqtd\n"); 804 return; 805 } 806 807 lsqtd = ex->sqtdend; 808 #ifdef DIAGNOSTIC 809 if (lsqtd == NULL) { 810 printf("ehci_check_qh_intr: lsqtd==0\n"); 811 return; 812 } 813 #endif 814 /* 815 * If the last TD is still active we need to check whether there 816 * is an error somewhere in the middle, or whether there was a 817 * short packet (SPD and not ACTIVE). 818 */ 819 usb_syncmem(&lsqtd->dma, 820 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 821 sizeof(lsqtd->qtd.qtd_status), 822 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 823 status = le32toh(lsqtd->qtd.qtd_status); 824 usb_syncmem(&lsqtd->dma, 825 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 826 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 827 if (status & EHCI_QTD_ACTIVE) { 828 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 829 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 830 usb_syncmem(&sqtd->dma, 831 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 832 sizeof(sqtd->qtd.qtd_status), 833 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 834 status = le32toh(sqtd->qtd.qtd_status); 835 usb_syncmem(&sqtd->dma, 836 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 837 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 838 /* If there's an active QTD the xfer isn't done. */ 839 if (status & EHCI_QTD_ACTIVE) 840 break; 841 /* Any kind of error makes the xfer done. */ 842 if (status & EHCI_QTD_HALTED) 843 goto done; 844 /* We want short packets, and it is short: it's done */ 845 if (EHCI_QTD_GET_BYTES(status) != 0) 846 goto done; 847 } 848 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 849 ex, ex->sqtdstart)); 850 return; 851 } 852 done: 853 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 854 callout_stop(&ex->xfer.timeout_handle); 855 ehci_idone(ex); 856 } 857 858 Static void 859 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 860 { 861 ehci_soft_itd_t *itd; 862 int i; 863 864 KASSERT(mutex_owned(&sc->sc_lock)); 865 866 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 867 return; 868 869 if (ex->itdstart == NULL) { 870 printf("ehci_check_itd_intr: not valid itd\n"); 871 return; 872 } 873 874 itd = ex->itdend; 875 #ifdef DIAGNOSTIC 876 if (itd == NULL) { 877 printf("ehci_check_itd_intr: itdend == 0\n"); 878 return; 879 } 880 #endif 881 882 /* 883 * check no active transfers in last itd, meaning we're finished 884 */ 885 886 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 887 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 888 BUS_DMASYNC_POSTREAD); 889 890 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 891 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 892 break; 893 } 894 895 if (i == EHCI_ITD_NUFRAMES) { 896 goto done; /* All 8 descriptors inactive, it's done */ 897 } 898 899 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 900 ex->itdstart)); 901 return; 902 done: 903 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 904 callout_stop(&ex->xfer.timeout_handle); 905 ehci_idone(ex); 906 } 907 908 Static void 909 ehci_idone(struct ehci_xfer *ex) 910 { 911 usbd_xfer_handle xfer = &ex->xfer; 912 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 913 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 914 ehci_soft_qtd_t *sqtd, *lsqtd; 915 u_int32_t status = 0, nstatus = 0; 916 int actlen; 917 918 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 919 920 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 921 922 #ifdef DIAGNOSTIC 923 { 924 if (ex->isdone) { 925 #ifdef EHCI_DEBUG 926 printf("ehci_idone: ex is done!\n "); 927 ehci_dump_exfer(ex); 928 #else 929 printf("ehci_idone: ex=%p is done!\n", ex); 930 #endif 931 return; 932 } 933 ex->isdone = 1; 934 } 935 #endif 936 if (xfer->status == USBD_CANCELLED || 937 xfer->status == USBD_TIMEOUT) { 938 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 939 return; 940 } 941 942 #ifdef EHCI_DEBUG 943 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 944 if (ehcidebug > 10) 945 ehci_dump_sqtds(ex->sqtdstart); 946 #endif 947 948 /* The transfer is done, compute actual length and status. */ 949 950 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 951 == UE_ISOCHRONOUS) { 952 /* Isoc transfer */ 953 struct ehci_soft_itd *itd; 954 int i, nframes, len, uframes; 955 956 nframes = 0; 957 actlen = 0; 958 959 i = xfer->pipe->endpoint->edesc->bInterval; 960 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 961 962 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 963 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 964 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 965 BUS_DMASYNC_POSTREAD); 966 967 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 968 /* XXX - driver didn't fill in the frame full 969 * of uframes. This leads to scheduling 970 * inefficiencies, but working around 971 * this doubles complexity of tracking 972 * an xfer. 973 */ 974 if (nframes >= xfer->nframes) 975 break; 976 977 status = le32toh(itd->itd.itd_ctl[i]); 978 len = EHCI_ITD_GET_LEN(status); 979 if (EHCI_ITD_GET_STATUS(status) != 0) 980 len = 0; /*No valid data on error*/ 981 982 xfer->frlengths[nframes++] = len; 983 actlen += len; 984 } 985 986 if (nframes >= xfer->nframes) 987 break; 988 } 989 990 xfer->actlen = actlen; 991 xfer->status = USBD_NORMAL_COMPLETION; 992 goto end; 993 } 994 995 /* Continue processing xfers using queue heads */ 996 997 lsqtd = ex->sqtdend; 998 actlen = 0; 999 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1000 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1001 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1002 nstatus = le32toh(sqtd->qtd.qtd_status); 1003 if (nstatus & EHCI_QTD_ACTIVE) 1004 break; 1005 1006 status = nstatus; 1007 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1008 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1009 } 1010 1011 1012 /* 1013 * If there are left over TDs we need to update the toggle. 1014 * The default pipe doesn't need it since control transfers 1015 * start the toggle at 0 every time. 1016 * For a short transfer we need to update the toggle for the missing 1017 * packets within the qTD. 1018 */ 1019 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1020 xfer->pipe->device->default_pipe != xfer->pipe) { 1021 DPRINTFN(2, ("ehci_idone: need toggle update " 1022 "status=%08x nstatus=%08x\n", status, nstatus)); 1023 #if 0 1024 ehci_dump_sqh(epipe->sqh); 1025 ehci_dump_sqtds(ex->sqtdstart); 1026 #endif 1027 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1028 } 1029 1030 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 1031 xfer->length, actlen, status)); 1032 xfer->actlen = actlen; 1033 if (status & EHCI_QTD_HALTED) { 1034 #ifdef EHCI_DEBUG 1035 char sbuf[128]; 1036 1037 snprintb(sbuf, sizeof(sbuf), 1038 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 1039 (u_int32_t)status); 1040 1041 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 1042 "status 0x%s\n", 1043 xfer->pipe->device->address, 1044 xfer->pipe->endpoint->edesc->bEndpointAddress, 1045 sbuf)); 1046 if (ehcidebug > 2) { 1047 ehci_dump_sqh(epipe->sqh); 1048 ehci_dump_sqtds(ex->sqtdstart); 1049 } 1050 #endif 1051 /* low&full speed has an extra error flag */ 1052 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1053 EHCI_QH_SPEED_HIGH) 1054 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1055 else 1056 status &= EHCI_QTD_STATERRS; 1057 if (status == 0) /* no other errors means a stall */ { 1058 xfer->status = USBD_STALLED; 1059 } else { 1060 xfer->status = USBD_IOERROR; /* more info XXX */ 1061 } 1062 /* XXX need to reset TT on missed microframe */ 1063 if (status & EHCI_QTD_MISSEDMICRO) { 1064 printf("%s: missed microframe, TT reset not " 1065 "implemented, hub might be inoperational\n", 1066 device_xname(sc->sc_dev)); 1067 } 1068 } else { 1069 xfer->status = USBD_NORMAL_COMPLETION; 1070 } 1071 1072 end: 1073 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1074 * during this call, before methods->done is called: dma sync required 1075 * beforehand? */ 1076 usb_transfer_complete(xfer); 1077 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1078 } 1079 1080 /* 1081 * Wait here until controller claims to have an interrupt. 1082 * Then call ehci_intr and return. Use timeout to avoid waiting 1083 * too long. 1084 */ 1085 Static void 1086 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1087 { 1088 int timo; 1089 u_int32_t intrs; 1090 1091 xfer->status = USBD_IN_PROGRESS; 1092 for (timo = xfer->timeout; timo >= 0; timo--) { 1093 usb_delay_ms(&sc->sc_bus, 1); 1094 if (sc->sc_dying) 1095 break; 1096 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1097 sc->sc_eintrs; 1098 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1099 #ifdef EHCI_DEBUG 1100 if (ehcidebug > 15) 1101 ehci_dump_regs(sc); 1102 #endif 1103 if (intrs) { 1104 mutex_spin_enter(&sc->sc_intr_lock); 1105 ehci_intr1(sc); 1106 mutex_spin_exit(&sc->sc_intr_lock); 1107 if (xfer->status != USBD_IN_PROGRESS) 1108 return; 1109 } 1110 } 1111 1112 /* Timeout */ 1113 DPRINTF(("ehci_waitintr: timeout\n")); 1114 xfer->status = USBD_TIMEOUT; 1115 mutex_enter(&sc->sc_lock); 1116 usb_transfer_complete(xfer); 1117 mutex_exit(&sc->sc_lock); 1118 /* XXX should free TD */ 1119 } 1120 1121 Static void 1122 ehci_poll(struct usbd_bus *bus) 1123 { 1124 ehci_softc_t *sc = bus->hci_private; 1125 #ifdef EHCI_DEBUG 1126 static int last; 1127 int new; 1128 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1129 if (new != last) { 1130 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1131 last = new; 1132 } 1133 #endif 1134 1135 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1136 mutex_spin_enter(&sc->sc_intr_lock); 1137 ehci_intr1(sc); 1138 mutex_spin_exit(&sc->sc_intr_lock); 1139 } 1140 } 1141 1142 void 1143 ehci_childdet(device_t self, device_t child) 1144 { 1145 struct ehci_softc *sc = device_private(self); 1146 1147 KASSERT(sc->sc_child == child); 1148 sc->sc_child = NULL; 1149 } 1150 1151 int 1152 ehci_detach(struct ehci_softc *sc, int flags) 1153 { 1154 int rv = 0; 1155 1156 if (sc->sc_child != NULL) 1157 rv = config_detach(sc->sc_child, flags); 1158 1159 if (rv != 0) 1160 return (rv); 1161 1162 callout_halt(&sc->sc_tmo_intrlist, NULL); 1163 callout_destroy(&sc->sc_tmo_intrlist); 1164 1165 /* XXX free other data structures XXX */ 1166 if (sc->sc_softitds) 1167 kmem_free(sc->sc_softitds, 1168 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1169 cv_destroy(&sc->sc_doorbell); 1170 cv_destroy(&sc->sc_softwake_cv); 1171 1172 #if 0 1173 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1174 1175 softint_disestablish(sc->sc_doorbell_si); 1176 softint_disestablish(sc->sc_pcd_si); 1177 1178 mutex_destroy(&sc->sc_lock); 1179 mutex_destroy(&sc->sc_intr_lock); 1180 #endif 1181 1182 pool_cache_destroy(sc->sc_xferpool); 1183 1184 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1185 1186 return (rv); 1187 } 1188 1189 1190 int 1191 ehci_activate(device_t self, enum devact act) 1192 { 1193 struct ehci_softc *sc = device_private(self); 1194 1195 switch (act) { 1196 case DVACT_DEACTIVATE: 1197 sc->sc_dying = 1; 1198 return 0; 1199 default: 1200 return EOPNOTSUPP; 1201 } 1202 } 1203 1204 /* 1205 * Handle suspend/resume. 1206 * 1207 * We need to switch to polling mode here, because this routine is 1208 * called from an interrupt context. This is all right since we 1209 * are almost suspended anyway. 1210 * 1211 * Note that this power handler isn't to be registered directly; the 1212 * bus glue needs to call out to it. 1213 */ 1214 bool 1215 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1216 { 1217 ehci_softc_t *sc = device_private(dv); 1218 int i; 1219 uint32_t cmd, hcr; 1220 1221 mutex_spin_enter(&sc->sc_intr_lock); 1222 sc->sc_bus.use_polling++; 1223 mutex_spin_exit(&sc->sc_intr_lock); 1224 1225 for (i = 1; i <= sc->sc_noport; i++) { 1226 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1227 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1228 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1229 } 1230 1231 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1232 1233 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1234 EOWRITE4(sc, EHCI_USBCMD, cmd); 1235 1236 for (i = 0; i < 100; i++) { 1237 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1238 if (hcr == 0) 1239 break; 1240 1241 usb_delay_ms(&sc->sc_bus, 1); 1242 } 1243 if (hcr != 0) 1244 printf("%s: reset timeout\n", device_xname(dv)); 1245 1246 cmd &= ~EHCI_CMD_RS; 1247 EOWRITE4(sc, EHCI_USBCMD, cmd); 1248 1249 for (i = 0; i < 100; i++) { 1250 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1251 if (hcr == EHCI_STS_HCH) 1252 break; 1253 1254 usb_delay_ms(&sc->sc_bus, 1); 1255 } 1256 if (hcr != EHCI_STS_HCH) 1257 printf("%s: config timeout\n", device_xname(dv)); 1258 1259 mutex_spin_enter(&sc->sc_intr_lock); 1260 sc->sc_bus.use_polling--; 1261 mutex_spin_exit(&sc->sc_intr_lock); 1262 1263 return true; 1264 } 1265 1266 bool 1267 ehci_resume(device_t dv, const pmf_qual_t *qual) 1268 { 1269 ehci_softc_t *sc = device_private(dv); 1270 int i; 1271 uint32_t cmd, hcr; 1272 1273 /* restore things in case the bios sucks */ 1274 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1275 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1276 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1277 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1278 1279 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1280 1281 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1282 1283 hcr = 0; 1284 for (i = 1; i <= sc->sc_noport; i++) { 1285 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1286 if ((cmd & EHCI_PS_PO) == 0 && 1287 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1288 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1289 hcr = 1; 1290 } 1291 } 1292 1293 if (hcr) { 1294 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1295 1296 for (i = 1; i <= sc->sc_noport; i++) { 1297 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1298 if ((cmd & EHCI_PS_PO) == 0 && 1299 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1300 EOWRITE4(sc, EHCI_PORTSC(i), 1301 cmd & ~EHCI_PS_FPR); 1302 } 1303 } 1304 1305 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1306 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1307 1308 for (i = 0; i < 100; i++) { 1309 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1310 if (hcr != EHCI_STS_HCH) 1311 break; 1312 1313 usb_delay_ms(&sc->sc_bus, 1); 1314 } 1315 if (hcr == EHCI_STS_HCH) 1316 printf("%s: config timeout\n", device_xname(dv)); 1317 1318 return true; 1319 } 1320 1321 /* 1322 * Shut down the controller when the system is going down. 1323 */ 1324 bool 1325 ehci_shutdown(device_t self, int flags) 1326 { 1327 ehci_softc_t *sc = device_private(self); 1328 1329 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1330 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1331 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1332 return true; 1333 } 1334 1335 Static usbd_status 1336 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1337 { 1338 struct ehci_softc *sc = bus->hci_private; 1339 usbd_status err; 1340 1341 err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, USBMALLOC_MULTISEG); 1342 #ifdef EHCI_DEBUG 1343 if (err) 1344 printf("ehci_allocm: usb_allocmem_flags()= %s (%d)\n", 1345 usbd_errstr(err), err); 1346 #endif 1347 if (err == USBD_NOMEM) 1348 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1349 #ifdef EHCI_DEBUG 1350 if (err) 1351 printf("ehci_allocm: usb_reserve_allocm()= %s (%d)\n", 1352 usbd_errstr(err), err); 1353 #endif 1354 return (err); 1355 } 1356 1357 Static void 1358 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1359 { 1360 struct ehci_softc *sc = bus->hci_private; 1361 1362 if (dma->block->flags & USB_DMA_RESERVE) { 1363 usb_reserve_freem(&sc->sc_dma_reserve, 1364 dma); 1365 return; 1366 } 1367 usb_freemem(&sc->sc_bus, dma); 1368 } 1369 1370 Static usbd_xfer_handle 1371 ehci_allocx(struct usbd_bus *bus) 1372 { 1373 struct ehci_softc *sc = bus->hci_private; 1374 usbd_xfer_handle xfer; 1375 1376 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1377 if (xfer != NULL) { 1378 memset(xfer, 0, sizeof(struct ehci_xfer)); 1379 #ifdef DIAGNOSTIC 1380 EXFER(xfer)->isdone = 1; 1381 xfer->busy_free = XFER_BUSY; 1382 #endif 1383 } 1384 return (xfer); 1385 } 1386 1387 Static void 1388 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1389 { 1390 struct ehci_softc *sc = bus->hci_private; 1391 1392 #ifdef DIAGNOSTIC 1393 if (xfer->busy_free != XFER_BUSY) { 1394 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1395 xfer->busy_free); 1396 } 1397 xfer->busy_free = XFER_FREE; 1398 if (!EXFER(xfer)->isdone) { 1399 printf("ehci_freex: !isdone\n"); 1400 } 1401 #endif 1402 pool_cache_put(sc->sc_xferpool, xfer); 1403 } 1404 1405 Static void 1406 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1407 { 1408 struct ehci_softc *sc = bus->hci_private; 1409 1410 *lock = &sc->sc_lock; 1411 } 1412 1413 Static void 1414 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1415 { 1416 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1417 1418 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1419 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1420 #ifdef EHCI_DEBUG 1421 if (ehcidebug) 1422 usbd_dump_pipe(pipe); 1423 #endif 1424 epipe->nexttoggle = 0; 1425 } 1426 1427 Static void 1428 ehci_noop(usbd_pipe_handle pipe) 1429 { 1430 } 1431 1432 #ifdef EHCI_DEBUG 1433 Static void 1434 ehci_dump_regs(ehci_softc_t *sc) 1435 { 1436 int i; 1437 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1438 EOREAD4(sc, EHCI_USBCMD), 1439 EOREAD4(sc, EHCI_USBSTS), 1440 EOREAD4(sc, EHCI_USBINTR)); 1441 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1442 EOREAD4(sc, EHCI_FRINDEX), 1443 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1444 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1445 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1446 for (i = 1; i <= sc->sc_noport; i++) 1447 printf("port %d status=0x%08x\n", i, 1448 EOREAD4(sc, EHCI_PORTSC(i))); 1449 } 1450 1451 /* 1452 * Unused function - this is meant to be called from a kernel 1453 * debugger. 1454 */ 1455 void 1456 ehci_dump(void) 1457 { 1458 ehci_dump_regs(theehci); 1459 } 1460 1461 Static void 1462 ehci_dump_link(ehci_link_t link, int type) 1463 { 1464 link = le32toh(link); 1465 printf("0x%08x", link); 1466 if (link & EHCI_LINK_TERMINATE) 1467 printf("<T>"); 1468 else { 1469 printf("<"); 1470 if (type) { 1471 switch (EHCI_LINK_TYPE(link)) { 1472 case EHCI_LINK_ITD: printf("ITD"); break; 1473 case EHCI_LINK_QH: printf("QH"); break; 1474 case EHCI_LINK_SITD: printf("SITD"); break; 1475 case EHCI_LINK_FSTN: printf("FSTN"); break; 1476 } 1477 } 1478 printf(">"); 1479 } 1480 } 1481 1482 Static void 1483 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1484 { 1485 int i; 1486 u_int32_t stop; 1487 1488 stop = 0; 1489 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1490 ehci_dump_sqtd(sqtd); 1491 usb_syncmem(&sqtd->dma, 1492 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1493 sizeof(sqtd->qtd), 1494 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1495 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1496 usb_syncmem(&sqtd->dma, 1497 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1498 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1499 } 1500 if (sqtd) 1501 printf("dump aborted, too many TDs\n"); 1502 } 1503 1504 Static void 1505 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1506 { 1507 usb_syncmem(&sqtd->dma, sqtd->offs, 1508 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1509 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1510 ehci_dump_qtd(&sqtd->qtd); 1511 usb_syncmem(&sqtd->dma, sqtd->offs, 1512 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1513 } 1514 1515 Static void 1516 ehci_dump_qtd(ehci_qtd_t *qtd) 1517 { 1518 u_int32_t s; 1519 char sbuf[128]; 1520 1521 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1522 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1523 printf("\n"); 1524 s = le32toh(qtd->qtd_status); 1525 snprintb(sbuf, sizeof(sbuf), 1526 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1527 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1528 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1529 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1530 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1531 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1532 EHCI_QTD_GET_PID(s), sbuf); 1533 for (s = 0; s < 5; s++) 1534 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1535 } 1536 1537 Static void 1538 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1539 { 1540 ehci_qh_t *qh = &sqh->qh; 1541 u_int32_t endp, endphub; 1542 1543 usb_syncmem(&sqh->dma, sqh->offs, 1544 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1545 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1546 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1547 endp = le32toh(qh->qh_endp); 1548 printf(" endp=0x%08x\n", endp); 1549 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1550 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1551 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1552 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1553 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1554 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1555 EHCI_QH_GET_NRL(endp)); 1556 endphub = le32toh(qh->qh_endphub); 1557 printf(" endphub=0x%08x\n", endphub); 1558 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1559 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1560 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1561 EHCI_QH_GET_MULT(endphub)); 1562 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1563 printf("Overlay qTD:\n"); 1564 ehci_dump_qtd(&qh->qh_qtd); 1565 usb_syncmem(&sqh->dma, sqh->offs, 1566 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1567 } 1568 1569 #if notyet 1570 Static void 1571 ehci_dump_itd(struct ehci_soft_itd *itd) 1572 { 1573 ehci_isoc_trans_t t; 1574 ehci_isoc_bufr_ptr_t b, b2, b3; 1575 int i; 1576 1577 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1578 1579 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1580 t = le32toh(itd->itd.itd_ctl[i]); 1581 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1582 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1583 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1584 EHCI_ITD_GET_OFFS(t)); 1585 } 1586 printf("ITDbufr: "); 1587 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1588 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1589 1590 b = le32toh(itd->itd.itd_bufr[0]); 1591 b2 = le32toh(itd->itd.itd_bufr[1]); 1592 b3 = le32toh(itd->itd.itd_bufr[2]); 1593 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1594 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1595 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1596 } 1597 1598 Static void 1599 ehci_dump_sitd(struct ehci_soft_itd *itd) 1600 { 1601 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1602 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1603 itd->xfer_next, itd->physaddr, itd->slot); 1604 } 1605 #endif 1606 1607 #ifdef DIAGNOSTIC 1608 Static void 1609 ehci_dump_exfer(struct ehci_xfer *ex) 1610 { 1611 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1612 } 1613 #endif 1614 #endif 1615 1616 Static usbd_status 1617 ehci_open(usbd_pipe_handle pipe) 1618 { 1619 usbd_device_handle dev = pipe->device; 1620 ehci_softc_t *sc = dev->bus->hci_private; 1621 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1622 u_int8_t addr = dev->address; 1623 u_int8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1624 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1625 ehci_soft_qh_t *sqh; 1626 usbd_status err; 1627 int ival, speed, naks; 1628 int hshubaddr, hshubport; 1629 1630 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1631 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1632 1633 if (dev->myhsport) { 1634 /* 1635 * When directly attached FS/LS device while doing embedded 1636 * transaction translations and we are the hub, set the hub 1637 * address to 0 (us). 1638 */ 1639 if (!(sc->sc_flags & EHCIF_ETTF) 1640 || (dev->myhsport->parent->address != sc->sc_addr)) { 1641 hshubaddr = dev->myhsport->parent->address; 1642 } else { 1643 hshubaddr = 0; 1644 } 1645 hshubport = dev->myhsport->portno; 1646 } else { 1647 hshubaddr = 0; 1648 hshubport = 0; 1649 } 1650 1651 if (sc->sc_dying) 1652 return (USBD_IOERROR); 1653 1654 /* toggle state needed for bulk endpoints */ 1655 epipe->nexttoggle = pipe->endpoint->datatoggle; 1656 1657 if (addr == sc->sc_addr) { 1658 switch (ed->bEndpointAddress) { 1659 case USB_CONTROL_ENDPOINT: 1660 pipe->methods = &ehci_root_ctrl_methods; 1661 break; 1662 case UE_DIR_IN | EHCI_INTR_ENDPT: 1663 pipe->methods = &ehci_root_intr_methods; 1664 break; 1665 default: 1666 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1667 ed->bEndpointAddress)); 1668 return (USBD_INVAL); 1669 } 1670 return (USBD_NORMAL_COMPLETION); 1671 } 1672 1673 /* XXX All this stuff is only valid for async. */ 1674 switch (dev->speed) { 1675 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1676 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1677 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1678 default: panic("ehci_open: bad device speed %d", dev->speed); 1679 } 1680 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1681 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1682 "isoc endpoint.\n"); 1683 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1684 "attached to a USB2 hub, and transaction translations are " 1685 "not yet supported.\n"); 1686 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1687 "root hub instead.\n"); 1688 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1689 hshubaddr, hshubport)); 1690 return USBD_INVAL; 1691 } 1692 1693 /* 1694 * For interrupt transfer, nak throttling must be disabled, but for 1695 * the other transfer type, nak throttling should be enabled from the 1696 * viewpoint that avoids the memory thrashing. 1697 */ 1698 naks = (xfertype == UE_INTERRUPT) ? 0 1699 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1700 1701 /* Allocate sqh for everything, save isoc xfers */ 1702 if (xfertype != UE_ISOCHRONOUS) { 1703 sqh = ehci_alloc_sqh(sc); 1704 if (sqh == NULL) 1705 return (USBD_NOMEM); 1706 /* qh_link filled when the QH is added */ 1707 sqh->qh.qh_endp = htole32( 1708 EHCI_QH_SET_ADDR(addr) | 1709 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1710 EHCI_QH_SET_EPS(speed) | 1711 EHCI_QH_DTC | 1712 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1713 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1714 EHCI_QH_CTL : 0) | 1715 EHCI_QH_SET_NRL(naks) 1716 ); 1717 sqh->qh.qh_endphub = htole32( 1718 EHCI_QH_SET_MULT(1) | 1719 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1720 ); 1721 if (speed != EHCI_QH_SPEED_HIGH) 1722 sqh->qh.qh_endphub |= htole32( 1723 EHCI_QH_SET_PORT(hshubport) | 1724 EHCI_QH_SET_HUBA(hshubaddr) | 1725 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1726 ); 1727 sqh->qh.qh_curqtd = EHCI_NULL; 1728 /* Fill the overlay qTD */ 1729 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1730 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1731 sqh->qh.qh_qtd.qtd_status = htole32(0); 1732 1733 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1734 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1735 epipe->sqh = sqh; 1736 } else { 1737 sqh = NULL; 1738 } /*xfertype == UE_ISOC*/ 1739 1740 switch (xfertype) { 1741 case UE_CONTROL: 1742 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1743 0, &epipe->u.ctl.reqdma); 1744 #ifdef EHCI_DEBUG 1745 if (err) 1746 printf("ehci_open: usb_allocmem()=%d\n", err); 1747 #endif 1748 if (err) 1749 goto bad; 1750 pipe->methods = &ehci_device_ctrl_methods; 1751 mutex_enter(&sc->sc_lock); 1752 ehci_add_qh(sc, sqh, sc->sc_async_head); 1753 mutex_exit(&sc->sc_lock); 1754 break; 1755 case UE_BULK: 1756 pipe->methods = &ehci_device_bulk_methods; 1757 mutex_enter(&sc->sc_lock); 1758 ehci_add_qh(sc, sqh, sc->sc_async_head); 1759 mutex_exit(&sc->sc_lock); 1760 break; 1761 case UE_INTERRUPT: 1762 pipe->methods = &ehci_device_intr_methods; 1763 ival = pipe->interval; 1764 if (ival == USBD_DEFAULT_INTERVAL) { 1765 if (speed == EHCI_QH_SPEED_HIGH) { 1766 if (ed->bInterval > 16) { 1767 /* 1768 * illegal with high-speed, but there 1769 * were documentation bugs in the spec, 1770 * so be generous 1771 */ 1772 ival = 256; 1773 } else 1774 ival = (1 << (ed->bInterval - 1)) / 8; 1775 } else 1776 ival = ed->bInterval; 1777 } 1778 err = ehci_device_setintr(sc, sqh, ival); 1779 if (err) 1780 goto bad; 1781 break; 1782 case UE_ISOCHRONOUS: 1783 pipe->methods = &ehci_device_isoc_methods; 1784 if (ed->bInterval == 0 || ed->bInterval > 16) { 1785 printf("ehci: opening pipe with invalid bInterval\n"); 1786 err = USBD_INVAL; 1787 goto bad; 1788 } 1789 if (UGETW(ed->wMaxPacketSize) == 0) { 1790 printf("ehci: zero length endpoint open request\n"); 1791 err = USBD_INVAL; 1792 goto bad; 1793 } 1794 epipe->u.isoc.next_frame = 0; 1795 epipe->u.isoc.cur_xfers = 0; 1796 break; 1797 default: 1798 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1799 err = USBD_INVAL; 1800 goto bad; 1801 } 1802 return (USBD_NORMAL_COMPLETION); 1803 1804 bad: 1805 if (sqh != NULL) 1806 ehci_free_sqh(sc, sqh); 1807 return (err); 1808 } 1809 1810 /* 1811 * Add an ED to the schedule. Called with USB lock held. 1812 */ 1813 Static void 1814 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1815 { 1816 1817 KASSERT(mutex_owned(&sc->sc_lock)); 1818 1819 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1820 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1821 sqh->next = head->next; 1822 sqh->qh.qh_link = head->qh.qh_link; 1823 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1824 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1825 head->next = sqh; 1826 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1827 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1828 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1829 1830 #ifdef EHCI_DEBUG 1831 if (ehcidebug > 5) { 1832 printf("ehci_add_qh:\n"); 1833 ehci_dump_sqh(sqh); 1834 } 1835 #endif 1836 } 1837 1838 /* 1839 * Remove an ED from the schedule. Called with USB lock held. 1840 */ 1841 Static void 1842 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1843 { 1844 ehci_soft_qh_t *p; 1845 1846 KASSERT(mutex_owned(&sc->sc_lock)); 1847 1848 /* XXX */ 1849 for (p = head; p != NULL && p->next != sqh; p = p->next) 1850 ; 1851 if (p == NULL) 1852 panic("ehci_rem_qh: ED not found"); 1853 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1854 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1855 p->next = sqh->next; 1856 p->qh.qh_link = sqh->qh.qh_link; 1857 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1858 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1859 1860 ehci_sync_hc(sc); 1861 } 1862 1863 Static void 1864 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1865 { 1866 int i; 1867 u_int32_t status; 1868 1869 /* Save toggle bit and ping status. */ 1870 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1871 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1872 status = sqh->qh.qh_qtd.qtd_status & 1873 htole32(EHCI_QTD_TOGGLE_MASK | 1874 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1875 /* Set HALTED to make hw leave it alone. */ 1876 sqh->qh.qh_qtd.qtd_status = 1877 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1878 usb_syncmem(&sqh->dma, 1879 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1880 sizeof(sqh->qh.qh_qtd.qtd_status), 1881 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1882 sqh->qh.qh_curqtd = 0; 1883 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1884 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1885 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1886 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1887 sqh->sqtd = sqtd; 1888 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1889 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1890 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1891 sqh->qh.qh_qtd.qtd_status = status; 1892 usb_syncmem(&sqh->dma, 1893 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1894 sizeof(sqh->qh.qh_qtd.qtd_status), 1895 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1896 } 1897 1898 /* 1899 * Ensure that the HC has released all references to the QH. We do this 1900 * by asking for a Async Advance Doorbell interrupt and then we wait for 1901 * the interrupt. 1902 * To make this easier we first obtain exclusive use of the doorbell. 1903 */ 1904 Static void 1905 ehci_sync_hc(ehci_softc_t *sc) 1906 { 1907 int error; 1908 1909 KASSERT(mutex_owned(&sc->sc_lock)); 1910 1911 if (sc->sc_dying) { 1912 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1913 return; 1914 } 1915 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1916 /* ask for doorbell */ 1917 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1918 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1919 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1920 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 1921 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1922 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1923 #ifdef DIAGNOSTIC 1924 if (error) 1925 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 1926 #endif 1927 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1928 } 1929 1930 Static void 1931 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1932 { 1933 struct ehci_soft_itd *itd, *prev; 1934 1935 prev = NULL; 1936 1937 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1938 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1939 1940 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1941 prev = itd->u.frame_list.prev; 1942 /* Unlink itd from hardware chain, or frame array */ 1943 if (prev == NULL) { /* We're at the table head */ 1944 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1945 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1946 usb_syncmem(&sc->sc_fldma, 1947 sizeof(ehci_link_t) * itd->slot, 1948 sizeof(ehci_link_t), 1949 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1950 1951 if (itd->u.frame_list.next != NULL) 1952 itd->u.frame_list.next->u.frame_list.prev = NULL; 1953 } else { 1954 /* XXX this part is untested... */ 1955 prev->itd.itd_next = itd->itd.itd_next; 1956 usb_syncmem(&itd->dma, 1957 itd->offs + offsetof(ehci_itd_t, itd_next), 1958 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1959 1960 prev->u.frame_list.next = itd->u.frame_list.next; 1961 if (itd->u.frame_list.next != NULL) 1962 itd->u.frame_list.next->u.frame_list.prev = prev; 1963 } 1964 } 1965 1966 prev = NULL; 1967 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1968 if (prev != NULL) 1969 ehci_free_itd(sc, prev); 1970 prev = itd; 1971 } 1972 if (prev) 1973 ehci_free_itd(sc, prev); 1974 exfer->itdstart = NULL; 1975 exfer->itdend = NULL; 1976 } 1977 1978 /***********/ 1979 1980 /* 1981 * Data structures and routines to emulate the root hub. 1982 */ 1983 Static usb_device_descriptor_t ehci_devd = { 1984 USB_DEVICE_DESCRIPTOR_SIZE, 1985 UDESC_DEVICE, /* type */ 1986 {0x00, 0x02}, /* USB version */ 1987 UDCLASS_HUB, /* class */ 1988 UDSUBCLASS_HUB, /* subclass */ 1989 UDPROTO_HSHUBSTT, /* protocol */ 1990 64, /* max packet */ 1991 {0},{0},{0x00,0x01}, /* device id */ 1992 1,2,0, /* string indicies */ 1993 1 /* # of configurations */ 1994 }; 1995 1996 Static const usb_device_qualifier_t ehci_odevd = { 1997 USB_DEVICE_DESCRIPTOR_SIZE, 1998 UDESC_DEVICE_QUALIFIER, /* type */ 1999 {0x00, 0x02}, /* USB version */ 2000 UDCLASS_HUB, /* class */ 2001 UDSUBCLASS_HUB, /* subclass */ 2002 UDPROTO_FSHUB, /* protocol */ 2003 64, /* max packet */ 2004 1, /* # of configurations */ 2005 0 2006 }; 2007 2008 Static const usb_config_descriptor_t ehci_confd = { 2009 USB_CONFIG_DESCRIPTOR_SIZE, 2010 UDESC_CONFIG, 2011 {USB_CONFIG_DESCRIPTOR_SIZE + 2012 USB_INTERFACE_DESCRIPTOR_SIZE + 2013 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2014 1, 2015 1, 2016 0, 2017 UC_ATTR_MBO | UC_SELF_POWERED, 2018 0 /* max power */ 2019 }; 2020 2021 Static const usb_interface_descriptor_t ehci_ifcd = { 2022 USB_INTERFACE_DESCRIPTOR_SIZE, 2023 UDESC_INTERFACE, 2024 0, 2025 0, 2026 1, 2027 UICLASS_HUB, 2028 UISUBCLASS_HUB, 2029 UIPROTO_HSHUBSTT, 2030 0 2031 }; 2032 2033 Static const usb_endpoint_descriptor_t ehci_endpd = { 2034 USB_ENDPOINT_DESCRIPTOR_SIZE, 2035 UDESC_ENDPOINT, 2036 UE_DIR_IN | EHCI_INTR_ENDPT, 2037 UE_INTERRUPT, 2038 {8, 0}, /* max packet */ 2039 12 2040 }; 2041 2042 Static const usb_hub_descriptor_t ehci_hubd = { 2043 USB_HUB_DESCRIPTOR_SIZE, 2044 UDESC_HUB, 2045 0, 2046 {0,0}, 2047 0, 2048 0, 2049 {""}, 2050 {""}, 2051 }; 2052 2053 /* 2054 * Simulate a hardware hub by handling all the necessary requests. 2055 */ 2056 Static usbd_status 2057 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2058 { 2059 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2060 usbd_status err; 2061 2062 /* Insert last in queue. */ 2063 mutex_enter(&sc->sc_lock); 2064 err = usb_insert_transfer(xfer); 2065 mutex_exit(&sc->sc_lock); 2066 if (err) 2067 return (err); 2068 2069 /* Pipe isn't running, start first */ 2070 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2071 } 2072 2073 Static usbd_status 2074 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2075 { 2076 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2077 usb_device_request_t *req; 2078 void *buf = NULL; 2079 int port, i; 2080 int len, value, index, l, totlen = 0; 2081 usb_port_status_t ps; 2082 usb_hub_descriptor_t hubd; 2083 usbd_status err; 2084 u_int32_t v; 2085 2086 if (sc->sc_dying) 2087 return (USBD_IOERROR); 2088 2089 #ifdef DIAGNOSTIC 2090 if (!(xfer->rqflags & URQ_REQUEST)) 2091 /* XXX panic */ 2092 return (USBD_INVAL); 2093 #endif 2094 req = &xfer->request; 2095 2096 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2097 req->bmRequestType, req->bRequest)); 2098 2099 len = UGETW(req->wLength); 2100 value = UGETW(req->wValue); 2101 index = UGETW(req->wIndex); 2102 2103 if (len != 0) 2104 buf = KERNADDR(&xfer->dmabuf, 0); 2105 2106 #define C(x,y) ((x) | ((y) << 8)) 2107 switch(C(req->bRequest, req->bmRequestType)) { 2108 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2109 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2110 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2111 /* 2112 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2113 * for the integrated root hub. 2114 */ 2115 break; 2116 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2117 if (len > 0) { 2118 *(u_int8_t *)buf = sc->sc_conf; 2119 totlen = 1; 2120 } 2121 break; 2122 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2123 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2124 if (len == 0) 2125 break; 2126 switch(value >> 8) { 2127 case UDESC_DEVICE: 2128 if ((value & 0xff) != 0) { 2129 err = USBD_IOERROR; 2130 goto ret; 2131 } 2132 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2133 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2134 memcpy(buf, &ehci_devd, l); 2135 break; 2136 /* 2137 * We can't really operate at another speed, but the spec says 2138 * we need this descriptor. 2139 */ 2140 case UDESC_DEVICE_QUALIFIER: 2141 if ((value & 0xff) != 0) { 2142 err = USBD_IOERROR; 2143 goto ret; 2144 } 2145 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2146 memcpy(buf, &ehci_odevd, l); 2147 break; 2148 /* 2149 * We can't really operate at another speed, but the spec says 2150 * we need this descriptor. 2151 */ 2152 case UDESC_OTHER_SPEED_CONFIGURATION: 2153 case UDESC_CONFIG: 2154 if ((value & 0xff) != 0) { 2155 err = USBD_IOERROR; 2156 goto ret; 2157 } 2158 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2159 memcpy(buf, &ehci_confd, l); 2160 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2161 value >> 8; 2162 buf = (char *)buf + l; 2163 len -= l; 2164 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2165 totlen += l; 2166 memcpy(buf, &ehci_ifcd, l); 2167 buf = (char *)buf + l; 2168 len -= l; 2169 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2170 totlen += l; 2171 memcpy(buf, &ehci_endpd, l); 2172 break; 2173 case UDESC_STRING: 2174 #define sd ((usb_string_descriptor_t *)buf) 2175 switch (value & 0xff) { 2176 case 0: /* Language table */ 2177 totlen = usb_makelangtbl(sd, len); 2178 break; 2179 case 1: /* Vendor */ 2180 totlen = usb_makestrdesc(sd, len, 2181 sc->sc_vendor); 2182 break; 2183 case 2: /* Product */ 2184 totlen = usb_makestrdesc(sd, len, 2185 "EHCI root hub"); 2186 break; 2187 } 2188 #undef sd 2189 break; 2190 default: 2191 err = USBD_IOERROR; 2192 goto ret; 2193 } 2194 break; 2195 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2196 if (len > 0) { 2197 *(u_int8_t *)buf = 0; 2198 totlen = 1; 2199 } 2200 break; 2201 case C(UR_GET_STATUS, UT_READ_DEVICE): 2202 if (len > 1) { 2203 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2204 totlen = 2; 2205 } 2206 break; 2207 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2208 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2209 if (len > 1) { 2210 USETW(((usb_status_t *)buf)->wStatus, 0); 2211 totlen = 2; 2212 } 2213 break; 2214 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2215 if (value >= USB_MAX_DEVICES) { 2216 err = USBD_IOERROR; 2217 goto ret; 2218 } 2219 sc->sc_addr = value; 2220 break; 2221 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2222 if (value != 0 && value != 1) { 2223 err = USBD_IOERROR; 2224 goto ret; 2225 } 2226 sc->sc_conf = value; 2227 break; 2228 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2229 break; 2230 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2231 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2232 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2233 err = USBD_IOERROR; 2234 goto ret; 2235 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2236 break; 2237 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2238 break; 2239 /* Hub requests */ 2240 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2241 break; 2242 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2243 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2244 "port=%d feature=%d\n", 2245 index, value)); 2246 if (index < 1 || index > sc->sc_noport) { 2247 err = USBD_IOERROR; 2248 goto ret; 2249 } 2250 port = EHCI_PORTSC(index); 2251 v = EOREAD4(sc, port); 2252 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2253 v &= ~EHCI_PS_CLEAR; 2254 switch(value) { 2255 case UHF_PORT_ENABLE: 2256 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2257 break; 2258 case UHF_PORT_SUSPEND: 2259 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2260 break; 2261 v &= ~EHCI_PS_SUSP; 2262 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2263 /* see USB2 spec ch. 7.1.7.7 */ 2264 usb_delay_ms(&sc->sc_bus, 20); 2265 EOWRITE4(sc, port, v); 2266 usb_delay_ms(&sc->sc_bus, 2); 2267 #ifdef DEBUG 2268 v = EOREAD4(sc, port); 2269 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2270 printf("ehci: resume failed: %x\n", v); 2271 #endif 2272 break; 2273 case UHF_PORT_POWER: 2274 if (sc->sc_hasppc) 2275 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2276 break; 2277 case UHF_PORT_TEST: 2278 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2279 "%d\n", index)); 2280 break; 2281 case UHF_PORT_INDICATOR: 2282 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2283 "%d\n", index)); 2284 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2285 break; 2286 case UHF_C_PORT_CONNECTION: 2287 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2288 break; 2289 case UHF_C_PORT_ENABLE: 2290 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2291 break; 2292 case UHF_C_PORT_SUSPEND: 2293 /* how? */ 2294 break; 2295 case UHF_C_PORT_OVER_CURRENT: 2296 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2297 break; 2298 case UHF_C_PORT_RESET: 2299 sc->sc_isreset[index] = 0; 2300 break; 2301 default: 2302 err = USBD_IOERROR; 2303 goto ret; 2304 } 2305 #if 0 2306 switch(value) { 2307 case UHF_C_PORT_CONNECTION: 2308 case UHF_C_PORT_ENABLE: 2309 case UHF_C_PORT_SUSPEND: 2310 case UHF_C_PORT_OVER_CURRENT: 2311 case UHF_C_PORT_RESET: 2312 default: 2313 break; 2314 } 2315 #endif 2316 break; 2317 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2318 if (len == 0) 2319 break; 2320 if ((value & 0xff) != 0) { 2321 err = USBD_IOERROR; 2322 goto ret; 2323 } 2324 hubd = ehci_hubd; 2325 hubd.bNbrPorts = sc->sc_noport; 2326 v = EOREAD4(sc, EHCI_HCSPARAMS); 2327 USETW(hubd.wHubCharacteristics, 2328 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2329 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2330 ? UHD_PORT_IND : 0); 2331 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2332 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2333 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2334 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2335 l = min(len, hubd.bDescLength); 2336 totlen = l; 2337 memcpy(buf, &hubd, l); 2338 break; 2339 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2340 if (len != 4) { 2341 err = USBD_IOERROR; 2342 goto ret; 2343 } 2344 memset(buf, 0, len); /* ? XXX */ 2345 totlen = len; 2346 break; 2347 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2348 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2349 index)); 2350 if (index < 1 || index > sc->sc_noport) { 2351 err = USBD_IOERROR; 2352 goto ret; 2353 } 2354 if (len != 4) { 2355 err = USBD_IOERROR; 2356 goto ret; 2357 } 2358 v = EOREAD4(sc, EHCI_PORTSC(index)); 2359 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2360 2361 i = UPS_HIGH_SPEED; 2362 if (sc->sc_flags & EHCIF_ETTF) { 2363 /* 2364 * If we are doing embedded transaction translation, 2365 * then directly attached LS/FS devices are reset by 2366 * the EHCI controller itself. PSPD is encoded 2367 * the same way as in USBSTATUS. 2368 */ 2369 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2370 } 2371 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2372 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2373 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2374 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2375 if (v & EHCI_PS_PR) i |= UPS_RESET; 2376 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2377 if (sc->sc_vendor_port_status) 2378 i = sc->sc_vendor_port_status(sc, v, i); 2379 USETW(ps.wPortStatus, i); 2380 i = 0; 2381 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2382 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2383 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2384 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2385 USETW(ps.wPortChange, i); 2386 l = min(len, sizeof ps); 2387 memcpy(buf, &ps, l); 2388 totlen = l; 2389 break; 2390 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2391 err = USBD_IOERROR; 2392 goto ret; 2393 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2394 break; 2395 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2396 if (index < 1 || index > sc->sc_noport) { 2397 err = USBD_IOERROR; 2398 goto ret; 2399 } 2400 port = EHCI_PORTSC(index); 2401 v = EOREAD4(sc, port); 2402 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2403 v &= ~EHCI_PS_CLEAR; 2404 switch(value) { 2405 case UHF_PORT_ENABLE: 2406 EOWRITE4(sc, port, v | EHCI_PS_PE); 2407 break; 2408 case UHF_PORT_SUSPEND: 2409 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2410 break; 2411 case UHF_PORT_RESET: 2412 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2413 index)); 2414 if (EHCI_PS_IS_LOWSPEED(v) 2415 && sc->sc_ncomp > 0 2416 && !(sc->sc_flags & EHCIF_ETTF)) { 2417 /* 2418 * Low speed device on non-ETTF controller or 2419 * unaccompanied controller, give up ownership. 2420 */ 2421 ehci_disown(sc, index, 1); 2422 break; 2423 } 2424 /* Start reset sequence. */ 2425 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2426 EOWRITE4(sc, port, v | EHCI_PS_PR); 2427 /* Wait for reset to complete. */ 2428 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2429 if (sc->sc_dying) { 2430 err = USBD_IOERROR; 2431 goto ret; 2432 } 2433 /* 2434 * An embedded transaction translator will automatically 2435 * terminate the reset sequence so there's no need to 2436 * it. 2437 */ 2438 v = EOREAD4(sc, port); 2439 if (v & EHCI_PS_PR) { 2440 /* Terminate reset sequence. */ 2441 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2442 /* Wait for HC to complete reset. */ 2443 usb_delay_ms(&sc->sc_bus, 2444 EHCI_PORT_RESET_COMPLETE); 2445 if (sc->sc_dying) { 2446 err = USBD_IOERROR; 2447 goto ret; 2448 } 2449 } 2450 2451 v = EOREAD4(sc, port); 2452 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2453 if (v & EHCI_PS_PR) { 2454 printf("%s: port reset timeout\n", 2455 device_xname(sc->sc_dev)); 2456 return (USBD_TIMEOUT); 2457 } 2458 if (!(v & EHCI_PS_PE)) { 2459 /* Not a high speed device, give up ownership.*/ 2460 ehci_disown(sc, index, 0); 2461 break; 2462 } 2463 sc->sc_isreset[index] = 1; 2464 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2465 index, v)); 2466 break; 2467 case UHF_PORT_POWER: 2468 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2469 "%d (has PPC = %d)\n", index, 2470 sc->sc_hasppc)); 2471 if (sc->sc_hasppc) 2472 EOWRITE4(sc, port, v | EHCI_PS_PP); 2473 break; 2474 case UHF_PORT_TEST: 2475 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2476 "%d\n", index)); 2477 break; 2478 case UHF_PORT_INDICATOR: 2479 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2480 "%d\n", index)); 2481 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2482 break; 2483 default: 2484 err = USBD_IOERROR; 2485 goto ret; 2486 } 2487 break; 2488 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2489 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2490 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2491 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2492 break; 2493 default: 2494 err = USBD_IOERROR; 2495 goto ret; 2496 } 2497 xfer->actlen = totlen; 2498 err = USBD_NORMAL_COMPLETION; 2499 ret: 2500 mutex_enter(&sc->sc_lock); 2501 xfer->status = err; 2502 usb_transfer_complete(xfer); 2503 mutex_exit(&sc->sc_lock); 2504 return (USBD_IN_PROGRESS); 2505 } 2506 2507 Static void 2508 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2509 { 2510 int port; 2511 u_int32_t v; 2512 2513 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2514 #ifdef DIAGNOSTIC 2515 if (sc->sc_npcomp != 0) { 2516 int i = (index-1) / sc->sc_npcomp; 2517 if (i >= sc->sc_ncomp) 2518 printf("%s: strange port\n", 2519 device_xname(sc->sc_dev)); 2520 else 2521 printf("%s: handing over %s speed device on " 2522 "port %d to %s\n", 2523 device_xname(sc->sc_dev), 2524 lowspeed ? "low" : "full", 2525 index, device_xname(sc->sc_comps[i])); 2526 } else { 2527 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2528 } 2529 #endif 2530 port = EHCI_PORTSC(index); 2531 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2532 EOWRITE4(sc, port, v | EHCI_PS_PO); 2533 } 2534 2535 /* Abort a root control request. */ 2536 Static void 2537 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2538 { 2539 /* Nothing to do, all transfers are synchronous. */ 2540 } 2541 2542 /* Close the root pipe. */ 2543 Static void 2544 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2545 { 2546 DPRINTF(("ehci_root_ctrl_close\n")); 2547 /* Nothing to do. */ 2548 } 2549 2550 Static void 2551 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2552 { 2553 xfer->hcpriv = NULL; 2554 } 2555 2556 Static usbd_status 2557 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2558 { 2559 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2560 usbd_status err; 2561 2562 /* Insert last in queue. */ 2563 mutex_enter(&sc->sc_lock); 2564 err = usb_insert_transfer(xfer); 2565 mutex_exit(&sc->sc_lock); 2566 if (err) 2567 return (err); 2568 2569 /* Pipe isn't running, start first */ 2570 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2571 } 2572 2573 Static usbd_status 2574 ehci_root_intr_start(usbd_xfer_handle xfer) 2575 { 2576 usbd_pipe_handle pipe = xfer->pipe; 2577 ehci_softc_t *sc = pipe->device->bus->hci_private; 2578 2579 if (sc->sc_dying) 2580 return (USBD_IOERROR); 2581 2582 mutex_enter(&sc->sc_lock); 2583 sc->sc_intrxfer = xfer; 2584 mutex_exit(&sc->sc_lock); 2585 2586 return (USBD_IN_PROGRESS); 2587 } 2588 2589 /* Abort a root interrupt request. */ 2590 Static void 2591 ehci_root_intr_abort(usbd_xfer_handle xfer) 2592 { 2593 #ifdef DIAGNOSTIC 2594 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2595 #endif 2596 2597 KASSERT(mutex_owned(&sc->sc_lock)); 2598 if (xfer->pipe->intrxfer == xfer) { 2599 DPRINTF(("ehci_root_intr_abort: remove\n")); 2600 xfer->pipe->intrxfer = NULL; 2601 } 2602 xfer->status = USBD_CANCELLED; 2603 usb_transfer_complete(xfer); 2604 } 2605 2606 /* Close the root pipe. */ 2607 Static void 2608 ehci_root_intr_close(usbd_pipe_handle pipe) 2609 { 2610 ehci_softc_t *sc = pipe->device->bus->hci_private; 2611 2612 KASSERT(mutex_owned(&sc->sc_lock)); 2613 2614 DPRINTF(("ehci_root_intr_close\n")); 2615 2616 sc->sc_intrxfer = NULL; 2617 } 2618 2619 Static void 2620 ehci_root_intr_done(usbd_xfer_handle xfer) 2621 { 2622 xfer->hcpriv = NULL; 2623 } 2624 2625 /************************/ 2626 2627 Static ehci_soft_qh_t * 2628 ehci_alloc_sqh(ehci_softc_t *sc) 2629 { 2630 ehci_soft_qh_t *sqh; 2631 usbd_status err; 2632 int i, offs; 2633 usb_dma_t dma; 2634 2635 if (sc->sc_freeqhs == NULL) { 2636 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2637 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2638 EHCI_PAGE_SIZE, &dma); 2639 #ifdef EHCI_DEBUG 2640 if (err) 2641 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2642 #endif 2643 if (err) 2644 return (NULL); 2645 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2646 offs = i * EHCI_SQH_SIZE; 2647 sqh = KERNADDR(&dma, offs); 2648 sqh->physaddr = DMAADDR(&dma, offs); 2649 sqh->dma = dma; 2650 sqh->offs = offs; 2651 sqh->next = sc->sc_freeqhs; 2652 sc->sc_freeqhs = sqh; 2653 } 2654 } 2655 sqh = sc->sc_freeqhs; 2656 sc->sc_freeqhs = sqh->next; 2657 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2658 sqh->next = NULL; 2659 return (sqh); 2660 } 2661 2662 Static void 2663 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2664 { 2665 sqh->next = sc->sc_freeqhs; 2666 sc->sc_freeqhs = sqh; 2667 } 2668 2669 Static ehci_soft_qtd_t * 2670 ehci_alloc_sqtd(ehci_softc_t *sc) 2671 { 2672 ehci_soft_qtd_t *sqtd = NULL; 2673 usbd_status err; 2674 int i, offs; 2675 usb_dma_t dma; 2676 2677 if (sc->sc_freeqtds == NULL) { 2678 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2679 2680 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2681 EHCI_PAGE_SIZE, &dma); 2682 #ifdef EHCI_DEBUG 2683 if (err) 2684 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2685 #endif 2686 if (err) 2687 goto done; 2688 2689 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2690 offs = i * EHCI_SQTD_SIZE; 2691 sqtd = KERNADDR(&dma, offs); 2692 sqtd->physaddr = DMAADDR(&dma, offs); 2693 sqtd->dma = dma; 2694 sqtd->offs = offs; 2695 2696 sqtd->nextqtd = sc->sc_freeqtds; 2697 sc->sc_freeqtds = sqtd; 2698 } 2699 } 2700 2701 sqtd = sc->sc_freeqtds; 2702 sc->sc_freeqtds = sqtd->nextqtd; 2703 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2704 sqtd->nextqtd = NULL; 2705 sqtd->xfer = NULL; 2706 2707 done: 2708 return (sqtd); 2709 } 2710 2711 Static void 2712 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2713 { 2714 2715 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 2716 2717 sqtd->nextqtd = sc->sc_freeqtds; 2718 sc->sc_freeqtds = sqtd; 2719 } 2720 2721 Static usbd_status 2722 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2723 int alen, int rd, usbd_xfer_handle xfer, 2724 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2725 { 2726 ehci_soft_qtd_t *next, *cur; 2727 ehci_physaddr_t nextphys; 2728 u_int32_t qtdstatus; 2729 int len, curlen, mps; 2730 int i, tog; 2731 int pages, pageoffs; 2732 bus_size_t curoffs; 2733 vaddr_t va, va_offs; 2734 usb_dma_t *dma = &xfer->dmabuf; 2735 u_int16_t flags = xfer->flags; 2736 paddr_t a; 2737 2738 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2739 2740 len = alen; 2741 qtdstatus = EHCI_QTD_ACTIVE | 2742 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2743 EHCI_QTD_SET_CERR(3) 2744 /* IOC set below */ 2745 /* BYTES set below */ 2746 ; 2747 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2748 tog = epipe->nexttoggle; 2749 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2750 2751 cur = ehci_alloc_sqtd(sc); 2752 *sp = cur; 2753 if (cur == NULL) 2754 goto nomem; 2755 2756 usb_syncmem(dma, 0, alen, 2757 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2758 curoffs = 0; 2759 for (;;) { 2760 /* The EHCI hardware can handle at most 5 pages. */ 2761 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2762 va_offs = EHCI_PAGE_OFFSET(va_offs); 2763 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 2764 /* we can handle it in this QTD */ 2765 curlen = len - curoffs; 2766 } else { 2767 /* must use multiple TDs, fill as much as possible. */ 2768 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 2769 2770 /* the length must be a multiple of the max size */ 2771 curlen -= curlen % mps; 2772 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2773 "curlen=%d\n", curlen)); 2774 #ifdef DIAGNOSTIC 2775 if (curlen == 0) 2776 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2777 #endif 2778 } 2779 DPRINTFN(4,("ehci_alloc_sqtd_chain: len=%d curlen=%d " 2780 "curoffs=%zu\n", len, curlen, (size_t)curoffs)); 2781 2782 /* 2783 * Allocate another transfer if there's more data left, 2784 * or if force last short transfer flag is set and we're 2785 * allocating a multiple of the max packet size. 2786 */ 2787 2788 if (curoffs + curlen != len || 2789 ((curlen % mps) == 0 && !rd && curlen != 0 && 2790 (flags & USBD_FORCE_SHORT_XFER))) { 2791 next = ehci_alloc_sqtd(sc); 2792 if (next == NULL) 2793 goto nomem; 2794 nextphys = htole32(next->physaddr); 2795 } else { 2796 next = NULL; 2797 nextphys = EHCI_NULL; 2798 } 2799 2800 /* Find number of pages we'll be using, insert dma addresses */ 2801 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2802 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2803 pageoffs = EHCI_PAGE(curoffs); 2804 for (i = 0; i < pages; i++) { 2805 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2806 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2807 /* Cast up to avoid compiler warnings */ 2808 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2809 } 2810 2811 /* First buffer pointer requires a page offset to start at */ 2812 va = (vaddr_t)KERNADDR(dma, curoffs); 2813 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2814 2815 cur->nextqtd = next; 2816 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2817 cur->qtd.qtd_status = 2818 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2819 cur->xfer = xfer; 2820 cur->len = curlen; 2821 2822 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08zx end=0x%08zx\n", 2823 (size_t)curoffs, (size_t)(curoffs + curlen))); 2824 2825 /* adjust the toggle based on the number of packets in this 2826 qtd */ 2827 if (((curlen + mps - 1) / mps) & 1) { 2828 tog ^= 1; 2829 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2830 } 2831 if (next == NULL) 2832 break; 2833 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2834 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2835 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2836 if (len) 2837 curoffs += curlen; 2838 cur = next; 2839 } 2840 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2841 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2842 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2843 *ep = cur; 2844 epipe->nexttoggle = tog; 2845 2846 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2847 *sp, *ep)); 2848 2849 return (USBD_NORMAL_COMPLETION); 2850 2851 nomem: 2852 /* XXX free chain */ 2853 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2854 return (USBD_NOMEM); 2855 } 2856 2857 Static void 2858 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2859 ehci_soft_qtd_t *sqtdend) 2860 { 2861 ehci_soft_qtd_t *p; 2862 int i; 2863 2864 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2865 sqtd, sqtdend)); 2866 2867 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2868 p = sqtd->nextqtd; 2869 ehci_free_sqtd(sc, sqtd); 2870 } 2871 } 2872 2873 Static ehci_soft_itd_t * 2874 ehci_alloc_itd(ehci_softc_t *sc) 2875 { 2876 struct ehci_soft_itd *itd, *freeitd; 2877 usbd_status err; 2878 int i, offs, frindex, previndex; 2879 usb_dma_t dma; 2880 2881 mutex_enter(&sc->sc_lock); 2882 2883 /* Find an itd that wasn't freed this frame or last frame. This can 2884 * discard itds that were freed before frindex wrapped around 2885 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2886 * interrupt and fiddling with list when that happens */ 2887 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2888 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2889 2890 freeitd = NULL; 2891 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2892 if (itd == NULL) 2893 break; 2894 if (itd->slot != frindex && itd->slot != previndex) { 2895 freeitd = itd; 2896 break; 2897 } 2898 } 2899 2900 if (freeitd == NULL) { 2901 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2902 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2903 EHCI_PAGE_SIZE, &dma); 2904 2905 if (err) { 2906 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2907 mutex_exit(&sc->sc_lock); 2908 return NULL; 2909 } 2910 2911 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2912 offs = i * EHCI_ITD_SIZE; 2913 itd = KERNADDR(&dma, offs); 2914 itd->physaddr = DMAADDR(&dma, offs); 2915 itd->dma = dma; 2916 itd->offs = offs; 2917 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2918 } 2919 freeitd = LIST_FIRST(&sc->sc_freeitds); 2920 } 2921 2922 itd = freeitd; 2923 LIST_REMOVE(itd, u.free_list); 2924 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2925 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2926 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2927 BUS_DMASYNC_PREREAD); 2928 2929 itd->u.frame_list.next = NULL; 2930 itd->u.frame_list.prev = NULL; 2931 itd->xfer_next = NULL; 2932 itd->slot = 0; 2933 2934 mutex_exit(&sc->sc_lock); 2935 2936 return itd; 2937 } 2938 2939 Static void 2940 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2941 { 2942 2943 KASSERT(mutex_owned(&sc->sc_lock)); 2944 2945 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2946 } 2947 2948 /****************/ 2949 2950 /* 2951 * Close a reqular pipe. 2952 * Assumes that there are no pending transactions. 2953 */ 2954 Static void 2955 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2956 { 2957 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2958 ehci_softc_t *sc = pipe->device->bus->hci_private; 2959 ehci_soft_qh_t *sqh = epipe->sqh; 2960 2961 KASSERT(mutex_owned(&sc->sc_lock)); 2962 2963 ehci_rem_qh(sc, sqh, head); 2964 ehci_free_sqh(sc, epipe->sqh); 2965 } 2966 2967 /* 2968 * Abort a device request. 2969 * If this routine is called at splusb() it guarantees that the request 2970 * will be removed from the hardware scheduling and that the callback 2971 * for it will be called with USBD_CANCELLED status. 2972 * It's impossible to guarantee that the requested transfer will not 2973 * have happened since the hardware runs concurrently. 2974 * If the transaction has already happened we rely on the ordinary 2975 * interrupt processing to process it. 2976 * XXX This is most probably wrong. 2977 * XXXMRG this doesn't make sense anymore. 2978 */ 2979 Static void 2980 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2981 { 2982 #define exfer EXFER(xfer) 2983 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2984 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2985 ehci_soft_qh_t *sqh = epipe->sqh; 2986 ehci_soft_qtd_t *sqtd; 2987 ehci_physaddr_t cur; 2988 u_int32_t qhstatus; 2989 int hit; 2990 int wake; 2991 2992 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2993 2994 KASSERT(mutex_owned(&sc->sc_lock)); 2995 2996 if (sc->sc_dying) { 2997 /* If we're dying, just do the software part. */ 2998 xfer->status = status; /* make software ignore it */ 2999 callout_stop(&xfer->timeout_handle); 3000 usb_transfer_complete(xfer); 3001 return; 3002 } 3003 3004 if (cpu_intr_p() || cpu_softintr_p()) 3005 panic("ehci_abort_xfer: not in process context"); 3006 3007 /* 3008 * If an abort is already in progress then just wait for it to 3009 * complete and return. 3010 */ 3011 if (xfer->hcflags & UXFER_ABORTING) { 3012 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3013 #ifdef DIAGNOSTIC 3014 if (status == USBD_TIMEOUT) 3015 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3016 #endif 3017 /* Override the status which might be USBD_TIMEOUT. */ 3018 xfer->status = status; 3019 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3020 xfer->hcflags |= UXFER_ABORTWAIT; 3021 while (xfer->hcflags & UXFER_ABORTING) 3022 cv_wait(&xfer->hccv, &sc->sc_lock); 3023 return; 3024 } 3025 xfer->hcflags |= UXFER_ABORTING; 3026 3027 /* 3028 * Step 1: Make interrupt routine and hardware ignore xfer. 3029 */ 3030 xfer->status = status; /* make software ignore it */ 3031 callout_stop(&xfer->timeout_handle); 3032 3033 usb_syncmem(&sqh->dma, 3034 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3035 sizeof(sqh->qh.qh_qtd.qtd_status), 3036 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3037 qhstatus = sqh->qh.qh_qtd.qtd_status; 3038 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3039 usb_syncmem(&sqh->dma, 3040 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3041 sizeof(sqh->qh.qh_qtd.qtd_status), 3042 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3043 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3044 usb_syncmem(&sqtd->dma, 3045 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3046 sizeof(sqtd->qtd.qtd_status), 3047 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3048 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3049 usb_syncmem(&sqtd->dma, 3050 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3051 sizeof(sqtd->qtd.qtd_status), 3052 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3053 if (sqtd == exfer->sqtdend) 3054 break; 3055 } 3056 3057 /* 3058 * Step 2: Wait until we know hardware has finished any possible 3059 * use of the xfer. Also make sure the soft interrupt routine 3060 * has run. 3061 */ 3062 ehci_sync_hc(sc); 3063 sc->sc_softwake = 1; 3064 usb_schedsoftintr(&sc->sc_bus); 3065 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3066 3067 /* 3068 * Step 3: Remove any vestiges of the xfer from the hardware. 3069 * The complication here is that the hardware may have executed 3070 * beyond the xfer we're trying to abort. So as we're scanning 3071 * the TDs of this xfer we check if the hardware points to 3072 * any of them. 3073 */ 3074 3075 usb_syncmem(&sqh->dma, 3076 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3077 sizeof(sqh->qh.qh_curqtd), 3078 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3079 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3080 hit = 0; 3081 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3082 hit |= cur == sqtd->physaddr; 3083 if (sqtd == exfer->sqtdend) 3084 break; 3085 } 3086 sqtd = sqtd->nextqtd; 3087 /* Zap curqtd register if hardware pointed inside the xfer. */ 3088 if (hit && sqtd != NULL) { 3089 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3090 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3091 usb_syncmem(&sqh->dma, 3092 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3093 sizeof(sqh->qh.qh_curqtd), 3094 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3095 sqh->qh.qh_qtd.qtd_status = qhstatus; 3096 usb_syncmem(&sqh->dma, 3097 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3098 sizeof(sqh->qh.qh_qtd.qtd_status), 3099 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3100 } else { 3101 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3102 } 3103 3104 /* 3105 * Step 4: Execute callback. 3106 */ 3107 #ifdef DIAGNOSTIC 3108 exfer->isdone = 1; 3109 #endif 3110 wake = xfer->hcflags & UXFER_ABORTWAIT; 3111 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3112 usb_transfer_complete(xfer); 3113 if (wake) { 3114 cv_broadcast(&xfer->hccv); 3115 } 3116 3117 KASSERT(mutex_owned(&sc->sc_lock)); 3118 #undef exfer 3119 } 3120 3121 Static void 3122 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3123 { 3124 ehci_isoc_trans_t trans_status; 3125 struct ehci_pipe *epipe; 3126 struct ehci_xfer *exfer; 3127 ehci_softc_t *sc; 3128 struct ehci_soft_itd *itd; 3129 int i, wake; 3130 3131 epipe = (struct ehci_pipe *) xfer->pipe; 3132 exfer = EXFER(xfer); 3133 sc = epipe->pipe.device->bus->hci_private; 3134 3135 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3136 3137 KASSERT(mutex_owned(&sc->sc_lock)); 3138 3139 if (sc->sc_dying) { 3140 xfer->status = status; 3141 callout_stop(&xfer->timeout_handle); 3142 usb_transfer_complete(xfer); 3143 return; 3144 } 3145 3146 if (xfer->hcflags & UXFER_ABORTING) { 3147 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3148 3149 #ifdef DIAGNOSTIC 3150 if (status == USBD_TIMEOUT) 3151 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3152 #endif 3153 3154 xfer->status = status; 3155 DPRINTFN(2, ("ehci_abort_isoc_xfer: waiting for abort to finish\n")); 3156 xfer->hcflags |= UXFER_ABORTWAIT; 3157 while (xfer->hcflags & UXFER_ABORTING) 3158 cv_wait(&xfer->hccv, &sc->sc_lock); 3159 goto done; 3160 } 3161 xfer->hcflags |= UXFER_ABORTING; 3162 3163 xfer->status = status; 3164 callout_stop(&xfer->timeout_handle); 3165 3166 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3167 usb_syncmem(&itd->dma, 3168 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3169 sizeof(itd->itd.itd_ctl), 3170 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3171 3172 for (i = 0; i < 8; i++) { 3173 trans_status = le32toh(itd->itd.itd_ctl[i]); 3174 trans_status &= ~EHCI_ITD_ACTIVE; 3175 itd->itd.itd_ctl[i] = htole32(trans_status); 3176 } 3177 3178 usb_syncmem(&itd->dma, 3179 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3180 sizeof(itd->itd.itd_ctl), 3181 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3182 } 3183 3184 sc->sc_softwake = 1; 3185 usb_schedsoftintr(&sc->sc_bus); 3186 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3187 3188 #ifdef DIAGNOSTIC 3189 exfer->isdone = 1; 3190 #endif 3191 wake = xfer->hcflags & UXFER_ABORTWAIT; 3192 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3193 usb_transfer_complete(xfer); 3194 if (wake) { 3195 cv_broadcast(&xfer->hccv); 3196 } 3197 3198 done: 3199 KASSERT(mutex_owned(&sc->sc_lock)); 3200 return; 3201 } 3202 3203 Static void 3204 ehci_timeout(void *addr) 3205 { 3206 struct ehci_xfer *exfer = addr; 3207 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3208 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3209 3210 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3211 #ifdef EHCI_DEBUG 3212 if (ehcidebug > 1) 3213 usbd_dump_pipe(exfer->xfer.pipe); 3214 #endif 3215 3216 if (sc->sc_dying) { 3217 mutex_enter(&sc->sc_lock); 3218 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3219 mutex_exit(&sc->sc_lock); 3220 return; 3221 } 3222 3223 /* Execute the abort in a process context. */ 3224 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr, 3225 USB_TASKQ_MPSAFE); 3226 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3227 USB_TASKQ_HC); 3228 } 3229 3230 Static void 3231 ehci_timeout_task(void *addr) 3232 { 3233 usbd_xfer_handle xfer = addr; 3234 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3235 3236 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3237 3238 mutex_enter(&sc->sc_lock); 3239 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3240 mutex_exit(&sc->sc_lock); 3241 } 3242 3243 /************************/ 3244 3245 Static usbd_status 3246 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3247 { 3248 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3249 usbd_status err; 3250 3251 /* Insert last in queue. */ 3252 mutex_enter(&sc->sc_lock); 3253 err = usb_insert_transfer(xfer); 3254 mutex_exit(&sc->sc_lock); 3255 if (err) 3256 return (err); 3257 3258 /* Pipe isn't running, start first */ 3259 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3260 } 3261 3262 Static usbd_status 3263 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3264 { 3265 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3266 usbd_status err; 3267 3268 if (sc->sc_dying) 3269 return (USBD_IOERROR); 3270 3271 #ifdef DIAGNOSTIC 3272 if (!(xfer->rqflags & URQ_REQUEST)) { 3273 /* XXX panic */ 3274 printf("ehci_device_ctrl_transfer: not a request\n"); 3275 return (USBD_INVAL); 3276 } 3277 #endif 3278 3279 err = ehci_device_request(xfer); 3280 if (err) { 3281 return (err); 3282 } 3283 3284 if (sc->sc_bus.use_polling) 3285 ehci_waitintr(sc, xfer); 3286 3287 return (USBD_IN_PROGRESS); 3288 } 3289 3290 Static void 3291 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3292 { 3293 struct ehci_xfer *ex = EXFER(xfer); 3294 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3295 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3296 usb_device_request_t *req = &xfer->request; 3297 int len = UGETW(req->wLength); 3298 int rd = req->bmRequestType & UT_READ; 3299 3300 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3301 3302 KASSERT(mutex_owned(&sc->sc_lock)); 3303 3304 #ifdef DIAGNOSTIC 3305 if (!(xfer->rqflags & URQ_REQUEST)) { 3306 panic("ehci_ctrl_done: not a request"); 3307 } 3308 #endif 3309 3310 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3311 ehci_del_intr_list(sc, ex); /* remove from active list */ 3312 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3313 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3314 BUS_DMASYNC_POSTWRITE); 3315 if (len) 3316 usb_syncmem(&xfer->dmabuf, 0, len, 3317 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3318 } 3319 3320 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3321 } 3322 3323 /* Abort a device control request. */ 3324 Static void 3325 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3326 { 3327 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3328 ehci_abort_xfer(xfer, USBD_CANCELLED); 3329 } 3330 3331 /* Close a device control pipe. */ 3332 Static void 3333 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3334 { 3335 ehci_softc_t *sc = pipe->device->bus->hci_private; 3336 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3337 3338 KASSERT(mutex_owned(&sc->sc_lock)); 3339 3340 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3341 3342 ehci_close_pipe(pipe, sc->sc_async_head); 3343 } 3344 3345 Static usbd_status 3346 ehci_device_request(usbd_xfer_handle xfer) 3347 { 3348 #define exfer EXFER(xfer) 3349 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3350 usb_device_request_t *req = &xfer->request; 3351 usbd_device_handle dev = epipe->pipe.device; 3352 ehci_softc_t *sc = dev->bus->hci_private; 3353 int addr = dev->address; 3354 ehci_soft_qtd_t *setup, *stat, *next; 3355 ehci_soft_qh_t *sqh; 3356 int isread; 3357 int len; 3358 usbd_status err; 3359 3360 isread = req->bmRequestType & UT_READ; 3361 len = UGETW(req->wLength); 3362 3363 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3364 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3365 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3366 UGETW(req->wIndex), len, addr, 3367 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3368 3369 setup = ehci_alloc_sqtd(sc); 3370 if (setup == NULL) { 3371 err = USBD_NOMEM; 3372 goto bad1; 3373 } 3374 stat = ehci_alloc_sqtd(sc); 3375 if (stat == NULL) { 3376 err = USBD_NOMEM; 3377 goto bad2; 3378 } 3379 3380 mutex_enter(&sc->sc_lock); 3381 3382 sqh = epipe->sqh; 3383 3384 /* 3385 * Update device address and length since they may have changed 3386 * during the setup of the control pipe in usbd_new_device(). 3387 */ 3388 /* XXX This only needs to be done once, but it's too early in open. */ 3389 /* XXXX Should not touch ED here! */ 3390 sqh->qh.qh_endp = 3391 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3392 htole32( 3393 EHCI_QH_SET_ADDR(addr) | 3394 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3395 ); 3396 3397 /* Set up data transaction */ 3398 if (len != 0) { 3399 ehci_soft_qtd_t *end; 3400 3401 /* Start toggle at 1. */ 3402 epipe->nexttoggle = 1; 3403 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3404 &next, &end); 3405 if (err) 3406 goto bad3; 3407 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3408 end->nextqtd = stat; 3409 end->qtd.qtd_next = 3410 end->qtd.qtd_altnext = htole32(stat->physaddr); 3411 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3412 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3413 } else { 3414 next = stat; 3415 } 3416 3417 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3418 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3419 3420 /* Clear toggle */ 3421 setup->qtd.qtd_status = htole32( 3422 EHCI_QTD_ACTIVE | 3423 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3424 EHCI_QTD_SET_CERR(3) | 3425 EHCI_QTD_SET_TOGGLE(0) | 3426 EHCI_QTD_SET_BYTES(sizeof *req) 3427 ); 3428 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3429 setup->qtd.qtd_buffer_hi[0] = 0; 3430 setup->nextqtd = next; 3431 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3432 setup->xfer = xfer; 3433 setup->len = sizeof *req; 3434 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3435 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3436 3437 stat->qtd.qtd_status = htole32( 3438 EHCI_QTD_ACTIVE | 3439 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3440 EHCI_QTD_SET_CERR(3) | 3441 EHCI_QTD_SET_TOGGLE(1) | 3442 EHCI_QTD_IOC 3443 ); 3444 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3445 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3446 stat->nextqtd = NULL; 3447 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3448 stat->xfer = xfer; 3449 stat->len = 0; 3450 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3451 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3452 3453 #ifdef EHCI_DEBUG 3454 if (ehcidebug > 5) { 3455 DPRINTF(("ehci_device_request:\n")); 3456 ehci_dump_sqh(sqh); 3457 ehci_dump_sqtds(setup); 3458 } 3459 #endif 3460 3461 exfer->sqtdstart = setup; 3462 exfer->sqtdend = stat; 3463 #ifdef DIAGNOSTIC 3464 if (!exfer->isdone) { 3465 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3466 } 3467 exfer->isdone = 0; 3468 #endif 3469 3470 /* Insert qTD in QH list. */ 3471 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3472 if (xfer->timeout && !sc->sc_bus.use_polling) { 3473 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3474 ehci_timeout, xfer); 3475 } 3476 ehci_add_intr_list(sc, exfer); 3477 xfer->status = USBD_IN_PROGRESS; 3478 mutex_exit(&sc->sc_lock); 3479 3480 #ifdef EHCI_DEBUG 3481 if (ehcidebug > 10) { 3482 DPRINTF(("ehci_device_request: status=%x\n", 3483 EOREAD4(sc, EHCI_USBSTS))); 3484 delay(10000); 3485 ehci_dump_regs(sc); 3486 ehci_dump_sqh(sc->sc_async_head); 3487 ehci_dump_sqh(sqh); 3488 ehci_dump_sqtds(setup); 3489 } 3490 #endif 3491 3492 return (USBD_NORMAL_COMPLETION); 3493 3494 bad3: 3495 mutex_exit(&sc->sc_lock); 3496 ehci_free_sqtd(sc, stat); 3497 bad2: 3498 ehci_free_sqtd(sc, setup); 3499 bad1: 3500 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3501 mutex_enter(&sc->sc_lock); 3502 xfer->status = err; 3503 usb_transfer_complete(xfer); 3504 mutex_exit(&sc->sc_lock); 3505 return (err); 3506 #undef exfer 3507 } 3508 3509 /* 3510 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3511 * qTD status, or miss signalling occasionally under heavy load. If the host 3512 * machine is too fast, we we can miss transaction completion - when we scan 3513 * the active list the transaction still seems to be active. This generally 3514 * exhibits itself as a umass stall that never recovers. 3515 * 3516 * We work around this behaviour by setting up this callback after any softintr 3517 * that completes with transactions still pending, giving us another chance to 3518 * check for completion after the writeback has taken place. 3519 */ 3520 Static void 3521 ehci_intrlist_timeout(void *arg) 3522 { 3523 ehci_softc_t *sc = arg; 3524 3525 DPRINTF(("ehci_intrlist_timeout\n")); 3526 usb_schedsoftintr(&sc->sc_bus); 3527 } 3528 3529 /************************/ 3530 3531 Static usbd_status 3532 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3533 { 3534 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3535 usbd_status err; 3536 3537 /* Insert last in queue. */ 3538 mutex_enter(&sc->sc_lock); 3539 err = usb_insert_transfer(xfer); 3540 mutex_exit(&sc->sc_lock); 3541 if (err) 3542 return (err); 3543 3544 /* Pipe isn't running, start first */ 3545 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3546 } 3547 3548 Static usbd_status 3549 ehci_device_bulk_start(usbd_xfer_handle xfer) 3550 { 3551 #define exfer EXFER(xfer) 3552 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3553 usbd_device_handle dev = epipe->pipe.device; 3554 ehci_softc_t *sc = dev->bus->hci_private; 3555 ehci_soft_qtd_t *data, *dataend; 3556 ehci_soft_qh_t *sqh; 3557 usbd_status err; 3558 int len, isread, endpt; 3559 3560 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3561 xfer, xfer->length, xfer->flags)); 3562 3563 if (sc->sc_dying) 3564 return (USBD_IOERROR); 3565 3566 #ifdef DIAGNOSTIC 3567 if (xfer->rqflags & URQ_REQUEST) 3568 panic("ehci_device_bulk_start: a request"); 3569 #endif 3570 3571 mutex_enter(&sc->sc_lock); 3572 3573 len = xfer->length; 3574 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3575 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3576 sqh = epipe->sqh; 3577 3578 epipe->u.bulk.length = len; 3579 3580 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3581 &dataend); 3582 if (err) { 3583 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3584 xfer->status = err; 3585 usb_transfer_complete(xfer); 3586 mutex_exit(&sc->sc_lock); 3587 return (err); 3588 } 3589 3590 #ifdef EHCI_DEBUG 3591 if (ehcidebug > 5) { 3592 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3593 ehci_dump_sqh(sqh); 3594 ehci_dump_sqtds(data); 3595 } 3596 #endif 3597 3598 /* Set up interrupt info. */ 3599 exfer->sqtdstart = data; 3600 exfer->sqtdend = dataend; 3601 #ifdef DIAGNOSTIC 3602 if (!exfer->isdone) { 3603 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3604 } 3605 exfer->isdone = 0; 3606 #endif 3607 3608 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3609 if (xfer->timeout && !sc->sc_bus.use_polling) { 3610 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3611 ehci_timeout, xfer); 3612 } 3613 ehci_add_intr_list(sc, exfer); 3614 xfer->status = USBD_IN_PROGRESS; 3615 mutex_exit(&sc->sc_lock); 3616 3617 #ifdef EHCI_DEBUG 3618 if (ehcidebug > 10) { 3619 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3620 delay(10000); 3621 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3622 ehci_dump_regs(sc); 3623 #if 0 3624 printf("async_head:\n"); 3625 ehci_dump_sqh(sc->sc_async_head); 3626 #endif 3627 printf("sqh:\n"); 3628 ehci_dump_sqh(sqh); 3629 ehci_dump_sqtds(data); 3630 } 3631 #endif 3632 3633 if (sc->sc_bus.use_polling) 3634 ehci_waitintr(sc, xfer); 3635 3636 return (USBD_IN_PROGRESS); 3637 #undef exfer 3638 } 3639 3640 Static void 3641 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3642 { 3643 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3644 ehci_abort_xfer(xfer, USBD_CANCELLED); 3645 } 3646 3647 /* 3648 * Close a device bulk pipe. 3649 */ 3650 Static void 3651 ehci_device_bulk_close(usbd_pipe_handle pipe) 3652 { 3653 ehci_softc_t *sc = pipe->device->bus->hci_private; 3654 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3655 3656 KASSERT(mutex_owned(&sc->sc_lock)); 3657 3658 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3659 pipe->endpoint->datatoggle = epipe->nexttoggle; 3660 ehci_close_pipe(pipe, sc->sc_async_head); 3661 } 3662 3663 Static void 3664 ehci_device_bulk_done(usbd_xfer_handle xfer) 3665 { 3666 struct ehci_xfer *ex = EXFER(xfer); 3667 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3668 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3669 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3670 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3671 3672 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3673 xfer, xfer->actlen)); 3674 3675 KASSERT(mutex_owned(&sc->sc_lock)); 3676 3677 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3678 ehci_del_intr_list(sc, ex); /* remove from active list */ 3679 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3680 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3681 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3682 } 3683 3684 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3685 } 3686 3687 /************************/ 3688 3689 Static usbd_status 3690 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3691 { 3692 struct ehci_soft_islot *isp; 3693 int islot, lev; 3694 3695 /* Find a poll rate that is large enough. */ 3696 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3697 if (EHCI_ILEV_IVAL(lev) <= ival) 3698 break; 3699 3700 /* Pick an interrupt slot at the right level. */ 3701 /* XXX could do better than picking at random */ 3702 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3703 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3704 3705 sqh->islot = islot; 3706 isp = &sc->sc_islots[islot]; 3707 mutex_enter(&sc->sc_lock); 3708 ehci_add_qh(sc, sqh, isp->sqh); 3709 mutex_exit(&sc->sc_lock); 3710 3711 return (USBD_NORMAL_COMPLETION); 3712 } 3713 3714 Static usbd_status 3715 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3716 { 3717 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3718 usbd_status err; 3719 3720 /* Insert last in queue. */ 3721 mutex_enter(&sc->sc_lock); 3722 err = usb_insert_transfer(xfer); 3723 mutex_exit(&sc->sc_lock); 3724 if (err) 3725 return (err); 3726 3727 /* 3728 * Pipe isn't running (otherwise err would be USBD_INPROG), 3729 * so start it first. 3730 */ 3731 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3732 } 3733 3734 Static usbd_status 3735 ehci_device_intr_start(usbd_xfer_handle xfer) 3736 { 3737 #define exfer EXFER(xfer) 3738 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3739 usbd_device_handle dev = xfer->pipe->device; 3740 ehci_softc_t *sc = dev->bus->hci_private; 3741 ehci_soft_qtd_t *data, *dataend; 3742 ehci_soft_qh_t *sqh; 3743 usbd_status err; 3744 int len, isread, endpt; 3745 3746 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3747 xfer, xfer->length, xfer->flags)); 3748 3749 if (sc->sc_dying) 3750 return (USBD_IOERROR); 3751 3752 #ifdef DIAGNOSTIC 3753 if (xfer->rqflags & URQ_REQUEST) 3754 panic("ehci_device_intr_start: a request"); 3755 #endif 3756 3757 mutex_enter(&sc->sc_lock); 3758 3759 len = xfer->length; 3760 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3761 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3762 sqh = epipe->sqh; 3763 3764 epipe->u.intr.length = len; 3765 3766 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3767 &dataend); 3768 if (err) { 3769 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3770 xfer->status = err; 3771 usb_transfer_complete(xfer); 3772 mutex_exit(&sc->sc_lock); 3773 return (err); 3774 } 3775 3776 #ifdef EHCI_DEBUG 3777 if (ehcidebug > 5) { 3778 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3779 ehci_dump_sqh(sqh); 3780 ehci_dump_sqtds(data); 3781 } 3782 #endif 3783 3784 /* Set up interrupt info. */ 3785 exfer->sqtdstart = data; 3786 exfer->sqtdend = dataend; 3787 #ifdef DIAGNOSTIC 3788 if (!exfer->isdone) { 3789 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3790 } 3791 exfer->isdone = 0; 3792 #endif 3793 3794 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3795 if (xfer->timeout && !sc->sc_bus.use_polling) { 3796 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3797 ehci_timeout, xfer); 3798 } 3799 ehci_add_intr_list(sc, exfer); 3800 xfer->status = USBD_IN_PROGRESS; 3801 mutex_exit(&sc->sc_lock); 3802 3803 #ifdef EHCI_DEBUG 3804 if (ehcidebug > 10) { 3805 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3806 delay(10000); 3807 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3808 ehci_dump_regs(sc); 3809 printf("sqh:\n"); 3810 ehci_dump_sqh(sqh); 3811 ehci_dump_sqtds(data); 3812 } 3813 #endif 3814 3815 if (sc->sc_bus.use_polling) 3816 ehci_waitintr(sc, xfer); 3817 3818 return (USBD_IN_PROGRESS); 3819 #undef exfer 3820 } 3821 3822 Static void 3823 ehci_device_intr_abort(usbd_xfer_handle xfer) 3824 { 3825 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3826 if (xfer->pipe->intrxfer == xfer) { 3827 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3828 xfer->pipe->intrxfer = NULL; 3829 } 3830 /* 3831 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3832 * async doorbell. That's dependent on the async list, wheras 3833 * intr xfers are periodic, should not use this? 3834 */ 3835 ehci_abort_xfer(xfer, USBD_CANCELLED); 3836 } 3837 3838 Static void 3839 ehci_device_intr_close(usbd_pipe_handle pipe) 3840 { 3841 ehci_softc_t *sc = pipe->device->bus->hci_private; 3842 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3843 struct ehci_soft_islot *isp; 3844 3845 KASSERT(mutex_owned(&sc->sc_lock)); 3846 3847 isp = &sc->sc_islots[epipe->sqh->islot]; 3848 ehci_close_pipe(pipe, isp->sqh); 3849 } 3850 3851 Static void 3852 ehci_device_intr_done(usbd_xfer_handle xfer) 3853 { 3854 #define exfer EXFER(xfer) 3855 struct ehci_xfer *ex = EXFER(xfer); 3856 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3857 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3858 ehci_soft_qtd_t *data, *dataend; 3859 ehci_soft_qh_t *sqh; 3860 usbd_status err; 3861 int len, isread, endpt; 3862 3863 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3864 xfer, xfer->actlen)); 3865 3866 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 3867 3868 if (xfer->pipe->repeat) { 3869 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3870 3871 len = epipe->u.intr.length; 3872 xfer->length = len; 3873 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3874 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3875 usb_syncmem(&xfer->dmabuf, 0, len, 3876 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3877 sqh = epipe->sqh; 3878 3879 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3880 &data, &dataend); 3881 if (err) { 3882 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3883 xfer->status = err; 3884 return; 3885 } 3886 3887 /* Set up interrupt info. */ 3888 exfer->sqtdstart = data; 3889 exfer->sqtdend = dataend; 3890 #ifdef DIAGNOSTIC 3891 if (!exfer->isdone) { 3892 printf("ehci_device_intr_done: not done, ex=%p\n", 3893 exfer); 3894 } 3895 exfer->isdone = 0; 3896 #endif 3897 3898 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3899 if (xfer->timeout && !sc->sc_bus.use_polling) { 3900 callout_reset(&xfer->timeout_handle, 3901 mstohz(xfer->timeout), ehci_timeout, xfer); 3902 } 3903 3904 xfer->status = USBD_IN_PROGRESS; 3905 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3906 ehci_del_intr_list(sc, ex); /* remove from active list */ 3907 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3908 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3909 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3910 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3911 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3912 } 3913 #undef exfer 3914 } 3915 3916 /************************/ 3917 3918 Static usbd_status 3919 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3920 { 3921 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3922 usbd_status err; 3923 3924 mutex_enter(&sc->sc_lock); 3925 err = usb_insert_transfer(xfer); 3926 mutex_exit(&sc->sc_lock); 3927 if (err && err != USBD_IN_PROGRESS) 3928 return err; 3929 3930 return ehci_device_isoc_start(xfer); 3931 } 3932 3933 Static usbd_status 3934 ehci_device_isoc_start(usbd_xfer_handle xfer) 3935 { 3936 struct ehci_pipe *epipe; 3937 usbd_device_handle dev; 3938 ehci_softc_t *sc; 3939 struct ehci_xfer *exfer; 3940 ehci_soft_itd_t *itd, *prev, *start, *stop; 3941 usb_dma_t *dma_buf; 3942 int i, j, k, frames, uframes, ufrperframe; 3943 int trans_count, offs, total_length; 3944 int frindex; 3945 3946 start = NULL; 3947 prev = NULL; 3948 itd = NULL; 3949 trans_count = 0; 3950 total_length = 0; 3951 exfer = (struct ehci_xfer *) xfer; 3952 sc = xfer->pipe->device->bus->hci_private; 3953 dev = xfer->pipe->device; 3954 epipe = (struct ehci_pipe *)xfer->pipe; 3955 3956 /* 3957 * To allow continuous transfers, above we start all transfers 3958 * immediately. However, we're still going to get usbd_start_next call 3959 * this when another xfer completes. So, check if this is already 3960 * in progress or not 3961 */ 3962 3963 if (exfer->itdstart != NULL) 3964 return USBD_IN_PROGRESS; 3965 3966 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3967 xfer, xfer->length, xfer->flags)); 3968 3969 if (sc->sc_dying) 3970 return USBD_IOERROR; 3971 3972 /* 3973 * To avoid complication, don't allow a request right now that'll span 3974 * the entire frame table. To within 4 frames, to allow some leeway 3975 * on either side of where the hc currently is. 3976 */ 3977 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3978 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3979 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3980 return USBD_INVAL; 3981 } 3982 3983 #ifdef DIAGNOSTIC 3984 if (xfer->rqflags & URQ_REQUEST) 3985 panic("ehci_device_isoc_start: request\n"); 3986 3987 if (!exfer->isdone) 3988 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3989 exfer->isdone = 0; 3990 #endif 3991 3992 /* 3993 * Step 1: Allocate and initialize itds, how many do we need? 3994 * One per transfer if interval >= 8 microframes, fewer if we use 3995 * multiple microframes per frame. 3996 */ 3997 3998 i = epipe->pipe.endpoint->edesc->bInterval; 3999 if (i > 16 || i == 0) { 4000 /* Spec page 271 says intervals > 16 are invalid */ 4001 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 4002 return USBD_INVAL; 4003 } 4004 4005 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4006 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4007 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4008 4009 if (frames == 0) { 4010 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 4011 return USBD_INVAL; 4012 } 4013 4014 dma_buf = &xfer->dmabuf; 4015 offs = 0; 4016 4017 for (i = 0; i < frames; i++) { 4018 int froffs = offs; 4019 itd = ehci_alloc_itd(sc); 4020 4021 if (prev != NULL) { 4022 prev->itd.itd_next = 4023 htole32(itd->physaddr | EHCI_LINK_ITD); 4024 usb_syncmem(&itd->dma, 4025 itd->offs + offsetof(ehci_itd_t, itd_next), 4026 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4027 4028 prev->xfer_next = itd; 4029 } else { 4030 start = itd; 4031 } 4032 4033 /* 4034 * Step 1.5, initialize uframes 4035 */ 4036 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4037 /* Calculate which page in the list this starts in */ 4038 int addr = DMAADDR(dma_buf, froffs); 4039 addr = EHCI_PAGE_OFFSET(addr); 4040 addr += (offs - froffs); 4041 addr = EHCI_PAGE(addr); 4042 addr /= EHCI_PAGE_SIZE; 4043 4044 /* This gets the initial offset into the first page, 4045 * looks how far further along the current uframe 4046 * offset is. Works out how many pages that is. 4047 */ 4048 4049 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4050 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4051 EHCI_ITD_SET_PG(addr) | 4052 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4053 4054 total_length += xfer->frlengths[trans_count]; 4055 offs += xfer->frlengths[trans_count]; 4056 trans_count++; 4057 4058 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4059 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4060 break; 4061 } 4062 } 4063 4064 /* Step 1.75, set buffer pointers. To simplify matters, all 4065 * pointers are filled out for the next 7 hardware pages in 4066 * the dma block, so no need to worry what pages to cover 4067 * and what to not. 4068 */ 4069 4070 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4071 /* 4072 * Don't try to lookup a page that's past the end 4073 * of buffer 4074 */ 4075 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4076 if (page_offs >= dma_buf->block->size) 4077 break; 4078 4079 unsigned long long page = DMAADDR(dma_buf, page_offs); 4080 page = EHCI_PAGE(page); 4081 itd->itd.itd_bufr[j] = 4082 htole32(EHCI_ITD_SET_BPTR(page)); 4083 itd->itd.itd_bufr_hi[j] = 4084 htole32(page >> 32); 4085 } 4086 4087 /* 4088 * Other special values 4089 */ 4090 4091 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4092 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4093 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4094 4095 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4096 ? 1 : 0; 4097 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4098 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4099 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4100 4101 /* FIXME: handle invalid trans */ 4102 itd->itd.itd_bufr[2] |= 4103 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4104 4105 usb_syncmem(&itd->dma, 4106 itd->offs + offsetof(ehci_itd_t, itd_next), 4107 sizeof(ehci_itd_t), 4108 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4109 4110 prev = itd; 4111 } /* End of frame */ 4112 4113 stop = itd; 4114 stop->xfer_next = NULL; 4115 exfer->isoc_len = total_length; 4116 4117 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4118 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4119 4120 /* 4121 * Part 2: Transfer descriptors have now been set up, now they must 4122 * be scheduled into the period frame list. Erk. Not wanting to 4123 * complicate matters, transfer is denied if the transfer spans 4124 * more than the period frame list. 4125 */ 4126 4127 mutex_enter(&sc->sc_lock); 4128 4129 /* Start inserting frames */ 4130 if (epipe->u.isoc.cur_xfers > 0) { 4131 frindex = epipe->u.isoc.next_frame; 4132 } else { 4133 frindex = EOREAD4(sc, EHCI_FRINDEX); 4134 frindex = frindex >> 3; /* Erase microframe index */ 4135 frindex += 2; 4136 } 4137 4138 if (frindex >= sc->sc_flsize) 4139 frindex &= (sc->sc_flsize - 1); 4140 4141 /* What's the frame interval? */ 4142 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4143 if (i / USB_UFRAMES_PER_FRAME == 0) 4144 i = 1; 4145 else 4146 i /= USB_UFRAMES_PER_FRAME; 4147 4148 itd = start; 4149 for (j = 0; j < frames; j++) { 4150 if (itd == NULL) 4151 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4152 4153 itd->itd.itd_next = sc->sc_flist[frindex]; 4154 if (itd->itd.itd_next == 0) 4155 /* FIXME: frindex table gets initialized to NULL 4156 * or EHCI_NULL? */ 4157 itd->itd.itd_next = EHCI_NULL; 4158 4159 usb_syncmem(&itd->dma, 4160 itd->offs + offsetof(ehci_itd_t, itd_next), 4161 sizeof(itd->itd.itd_next), 4162 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4163 4164 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4165 4166 usb_syncmem(&sc->sc_fldma, 4167 sizeof(ehci_link_t) * frindex, 4168 sizeof(ehci_link_t), 4169 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4170 4171 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4172 sc->sc_softitds[frindex] = itd; 4173 if (itd->u.frame_list.next != NULL) 4174 itd->u.frame_list.next->u.frame_list.prev = itd; 4175 itd->slot = frindex; 4176 itd->u.frame_list.prev = NULL; 4177 4178 frindex += i; 4179 if (frindex >= sc->sc_flsize) 4180 frindex -= sc->sc_flsize; 4181 4182 itd = itd->xfer_next; 4183 } 4184 4185 epipe->u.isoc.cur_xfers++; 4186 epipe->u.isoc.next_frame = frindex; 4187 4188 exfer->itdstart = start; 4189 exfer->itdend = stop; 4190 exfer->sqtdstart = NULL; 4191 exfer->sqtdstart = NULL; 4192 4193 ehci_add_intr_list(sc, exfer); 4194 xfer->status = USBD_IN_PROGRESS; 4195 xfer->done = 0; 4196 mutex_exit(&sc->sc_lock); 4197 4198 if (sc->sc_bus.use_polling) { 4199 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4200 ehci_waitintr(sc, xfer); 4201 } 4202 4203 return USBD_IN_PROGRESS; 4204 } 4205 4206 Static void 4207 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4208 { 4209 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4210 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4211 } 4212 4213 Static void 4214 ehci_device_isoc_close(usbd_pipe_handle pipe) 4215 { 4216 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4217 } 4218 4219 Static void 4220 ehci_device_isoc_done(usbd_xfer_handle xfer) 4221 { 4222 struct ehci_xfer *exfer; 4223 ehci_softc_t *sc; 4224 struct ehci_pipe *epipe; 4225 4226 exfer = EXFER(xfer); 4227 sc = xfer->pipe->device->bus->hci_private; 4228 epipe = (struct ehci_pipe *) xfer->pipe; 4229 4230 KASSERT(mutex_owned(&sc->sc_lock)); 4231 4232 epipe->u.isoc.cur_xfers--; 4233 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4234 ehci_del_intr_list(sc, exfer); 4235 ehci_rem_free_itd_chain(sc, exfer); 4236 } 4237 4238 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4239 BUS_DMASYNC_POSTREAD); 4240 4241 } 4242
Indexes created Thu Sep 25 16:09:42 GMT 2025