ehci.c revision 1.212
1 /* $NetBSD: ehci.c,v 1.212 2013/09/12 19:53:41 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.212 2013/09/12 19:53:41 martin Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/kernel.h> 64 #include <sys/kmem.h> 65 #include <sys/device.h> 66 #include <sys/select.h> 67 #include <sys/proc.h> 68 #include <sys/queue.h> 69 #include <sys/mutex.h> 70 #include <sys/bus.h> 71 #include <sys/cpu.h> 72 73 #include <machine/endian.h> 74 75 #include <dev/usb/usb.h> 76 #include <dev/usb/usbdi.h> 77 #include <dev/usb/usbdivar.h> 78 #include <dev/usb/usb_mem.h> 79 #include <dev/usb/usb_quirks.h> 80 81 #include <dev/usb/ehcireg.h> 82 #include <dev/usb/ehcivar.h> 83 #include <dev/usb/usbroothub_subr.h> 84 85 #ifdef EHCI_DEBUG 86 static void __printflike(1, 2) 87 ehciprintf(const char *fmt, ...) 88 { 89 va_list ap; 90 91 va_start(ap, fmt); 92 vprintf(fmt, ap); 93 va_end(ap); 94 } 95 96 #define DPRINTF(x) do { if (ehcidebug) ehciprintf x; } while(0) 97 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) ehciprintf x; } while (0) 98 int ehcidebug = 0; 99 #else 100 #define DPRINTF(x) 101 #define DPRINTFN(n,x) 102 #endif 103 104 struct ehci_pipe { 105 struct usbd_pipe pipe; 106 int nexttoggle; 107 108 ehci_soft_qh_t *sqh; 109 union { 110 ehci_soft_qtd_t *qtd; 111 /* ehci_soft_itd_t *itd; */ 112 } tail; 113 union { 114 /* Control pipe */ 115 struct { 116 usb_dma_t reqdma; 117 } ctl; 118 /* Interrupt pipe */ 119 struct { 120 u_int length; 121 } intr; 122 /* Bulk pipe */ 123 struct { 124 u_int length; 125 } bulk; 126 /* Iso pipe */ 127 struct { 128 u_int next_frame; 129 u_int cur_xfers; 130 } isoc; 131 } u; 132 }; 133 134 Static usbd_status ehci_open(usbd_pipe_handle); 135 Static void ehci_poll(struct usbd_bus *); 136 Static void ehci_softintr(void *); 137 Static int ehci_intr1(ehci_softc_t *); 138 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 139 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 140 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 141 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 142 Static void ehci_idone(struct ehci_xfer *); 143 Static void ehci_timeout(void *); 144 Static void ehci_timeout_task(void *); 145 Static void ehci_intrlist_timeout(void *); 146 Static void ehci_doorbell(void *); 147 Static void ehci_pcd(void *); 148 149 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 150 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 151 152 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 153 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 154 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 155 156 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 157 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 158 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 159 Static void ehci_root_ctrl_close(usbd_pipe_handle); 160 Static void ehci_root_ctrl_done(usbd_xfer_handle); 161 162 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 163 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 164 Static void ehci_root_intr_abort(usbd_xfer_handle); 165 Static void ehci_root_intr_close(usbd_pipe_handle); 166 Static void ehci_root_intr_done(usbd_xfer_handle); 167 168 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 169 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 170 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 171 Static void ehci_device_ctrl_close(usbd_pipe_handle); 172 Static void ehci_device_ctrl_done(usbd_xfer_handle); 173 174 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 175 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 176 Static void ehci_device_bulk_abort(usbd_xfer_handle); 177 Static void ehci_device_bulk_close(usbd_pipe_handle); 178 Static void ehci_device_bulk_done(usbd_xfer_handle); 179 180 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 181 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 182 Static void ehci_device_intr_abort(usbd_xfer_handle); 183 Static void ehci_device_intr_close(usbd_pipe_handle); 184 Static void ehci_device_intr_done(usbd_xfer_handle); 185 186 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 187 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 188 Static void ehci_device_isoc_abort(usbd_xfer_handle); 189 Static void ehci_device_isoc_close(usbd_pipe_handle); 190 Static void ehci_device_isoc_done(usbd_xfer_handle); 191 192 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 193 Static void ehci_noop(usbd_pipe_handle pipe); 194 195 Static void ehci_disown(ehci_softc_t *, int, int); 196 197 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 198 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 199 200 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 201 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 202 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 203 ehci_softc_t *, int, int, usbd_xfer_handle, 204 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 205 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 206 ehci_soft_qtd_t *); 207 208 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 209 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 210 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 211 struct ehci_xfer *exfer); 212 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 213 usbd_status status); 214 215 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 216 217 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 218 int ival); 219 220 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 221 ehci_soft_qh_t *); 222 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 223 ehci_soft_qh_t *); 224 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 225 Static void ehci_sync_hc(ehci_softc_t *); 226 227 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 228 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 229 230 #ifdef EHCI_DEBUG 231 Static void ehci_dump_regs(ehci_softc_t *); 232 void ehci_dump(void); 233 Static ehci_softc_t *theehci; 234 Static void ehci_dump_link(ehci_link_t, int); 235 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 236 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 237 Static void ehci_dump_qtd(ehci_qtd_t *); 238 Static void ehci_dump_sqh(ehci_soft_qh_t *); 239 #if notyet 240 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 241 Static void ehci_dump_itd(struct ehci_soft_itd *); 242 #endif 243 #ifdef DIAGNOSTIC 244 Static void ehci_dump_exfer(struct ehci_xfer *); 245 #endif 246 #endif 247 248 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 249 250 #define EHCI_INTR_ENDPT 1 251 252 #define ehci_add_intr_list(sc, ex) \ 253 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 254 #define ehci_del_intr_list(sc, ex) \ 255 do { \ 256 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 257 (ex)->inext.tqe_prev = NULL; \ 258 } while (0) 259 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 260 261 Static const struct usbd_bus_methods ehci_bus_methods = { 262 .open_pipe = ehci_open, 263 .soft_intr = ehci_softintr, 264 .do_poll = ehci_poll, 265 .allocm = ehci_allocm, 266 .freem = ehci_freem, 267 .allocx = ehci_allocx, 268 .freex = ehci_freex, 269 .get_lock = ehci_get_lock, 270 }; 271 272 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 273 .transfer = ehci_root_ctrl_transfer, 274 .start = ehci_root_ctrl_start, 275 .abort = ehci_root_ctrl_abort, 276 .close = ehci_root_ctrl_close, 277 .cleartoggle = ehci_noop, 278 .done = ehci_root_ctrl_done, 279 }; 280 281 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 282 .transfer = ehci_root_intr_transfer, 283 .start = ehci_root_intr_start, 284 .abort = ehci_root_intr_abort, 285 .close = ehci_root_intr_close, 286 .cleartoggle = ehci_noop, 287 .done = ehci_root_intr_done, 288 }; 289 290 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 291 .transfer = ehci_device_ctrl_transfer, 292 .start = ehci_device_ctrl_start, 293 .abort = ehci_device_ctrl_abort, 294 .close = ehci_device_ctrl_close, 295 .cleartoggle = ehci_noop, 296 .done = ehci_device_ctrl_done, 297 }; 298 299 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 300 .transfer = ehci_device_intr_transfer, 301 .start = ehci_device_intr_start, 302 .abort = ehci_device_intr_abort, 303 .close = ehci_device_intr_close, 304 .cleartoggle = ehci_device_clear_toggle, 305 .done = ehci_device_intr_done, 306 }; 307 308 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 309 .transfer = ehci_device_bulk_transfer, 310 .start = ehci_device_bulk_start, 311 .abort = ehci_device_bulk_abort, 312 .close = ehci_device_bulk_close, 313 .cleartoggle = ehci_device_clear_toggle, 314 .done = ehci_device_bulk_done, 315 }; 316 317 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 318 .transfer = ehci_device_isoc_transfer, 319 .start = ehci_device_isoc_start, 320 .abort = ehci_device_isoc_abort, 321 .close = ehci_device_isoc_close, 322 .cleartoggle = ehci_noop, 323 .done = ehci_device_isoc_done, 324 }; 325 326 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 327 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 328 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 329 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 330 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 331 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 332 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 333 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 334 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 335 }; 336 337 usbd_status 338 ehci_init(ehci_softc_t *sc) 339 { 340 u_int32_t vers, sparams, cparams, hcr; 341 u_int i; 342 usbd_status err; 343 ehci_soft_qh_t *sqh; 344 u_int ncomp; 345 346 DPRINTF(("ehci_init: start\n")); 347 #ifdef EHCI_DEBUG 348 theehci = sc; 349 #endif 350 351 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 352 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 353 cv_init(&sc->sc_softwake_cv, "ehciab"); 354 cv_init(&sc->sc_doorbell, "ehcidi"); 355 356 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 357 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 358 359 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 360 ehci_doorbell, sc); 361 KASSERT(sc->sc_doorbell_si != NULL); 362 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 363 ehci_pcd, sc); 364 KASSERT(sc->sc_pcd_si != NULL); 365 366 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 367 368 vers = EREAD2(sc, EHCI_HCIVERSION); 369 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 370 vers >> 8, vers & 0xff); 371 372 sparams = EREAD4(sc, EHCI_HCSPARAMS); 373 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 374 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 375 ncomp = EHCI_HCS_N_CC(sparams); 376 if (ncomp != sc->sc_ncomp) { 377 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 378 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 379 #if NOHCI == 0 || NUHCI == 0 380 aprint_error("%s: ohci or uhci probably not configured\n", 381 device_xname(sc->sc_dev)); 382 #endif 383 if (ncomp < sc->sc_ncomp) 384 sc->sc_ncomp = ncomp; 385 } 386 if (sc->sc_ncomp > 0) { 387 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 388 aprint_normal("%s: companion controller%s, %d port%s each:", 389 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 390 EHCI_HCS_N_PCC(sparams), 391 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 392 for (i = 0; i < sc->sc_ncomp; i++) 393 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 394 aprint_normal("\n"); 395 } 396 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 397 cparams = EREAD4(sc, EHCI_HCCPARAMS); 398 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 399 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 400 401 if (EHCI_HCC_64BIT(cparams)) { 402 /* MUST clear segment register if 64 bit capable. */ 403 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 404 } 405 406 sc->sc_bus.usbrev = USBREV_2_0; 407 408 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 409 USB_MEM_RESERVE); 410 411 /* Reset the controller */ 412 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 413 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 414 usb_delay_ms(&sc->sc_bus, 1); 415 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 416 for (i = 0; i < 100; i++) { 417 usb_delay_ms(&sc->sc_bus, 1); 418 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 419 if (!hcr) 420 break; 421 } 422 if (hcr) { 423 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 424 return (USBD_IOERROR); 425 } 426 if (sc->sc_vendor_init) 427 sc->sc_vendor_init(sc); 428 429 /* 430 * If we are doing embedded transaction translation function, force 431 * the controller to host mode. 432 */ 433 if (sc->sc_flags & EHCIF_ETTF) { 434 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 435 usbmode &= ~EHCI_USBMODE_CM; 436 usbmode |= EHCI_USBMODE_CM_HOST; 437 EWRITE4(sc, EHCI_USBMODE, usbmode); 438 } 439 440 /* XXX need proper intr scheduling */ 441 sc->sc_rand = 96; 442 443 /* frame list size at default, read back what we got and use that */ 444 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 445 case 0: sc->sc_flsize = 1024; break; 446 case 1: sc->sc_flsize = 512; break; 447 case 2: sc->sc_flsize = 256; break; 448 case 3: return (USBD_IOERROR); 449 } 450 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 451 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 452 if (err) 453 return (err); 454 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 455 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 456 457 for (i = 0; i < sc->sc_flsize; i++) { 458 sc->sc_flist[i] = EHCI_NULL; 459 } 460 461 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 462 463 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 464 KM_SLEEP); 465 if (sc->sc_softitds == NULL) 466 return ENOMEM; 467 LIST_INIT(&sc->sc_freeitds); 468 TAILQ_INIT(&sc->sc_intrhead); 469 470 /* Set up the bus struct. */ 471 sc->sc_bus.methods = &ehci_bus_methods; 472 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 473 474 sc->sc_eintrs = EHCI_NORMAL_INTRS; 475 476 /* 477 * Allocate the interrupt dummy QHs. These are arranged to give poll 478 * intervals that are powers of 2 times 1ms. 479 */ 480 for (i = 0; i < EHCI_INTRQHS; i++) { 481 sqh = ehci_alloc_sqh(sc); 482 if (sqh == NULL) { 483 err = USBD_NOMEM; 484 goto bad1; 485 } 486 sc->sc_islots[i].sqh = sqh; 487 } 488 for (i = 0; i < EHCI_INTRQHS; i++) { 489 sqh = sc->sc_islots[i].sqh; 490 if (i == 0) { 491 /* The last (1ms) QH terminates. */ 492 sqh->qh.qh_link = EHCI_NULL; 493 sqh->next = NULL; 494 } else { 495 /* Otherwise the next QH has half the poll interval */ 496 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 497 sqh->qh.qh_link = htole32(sqh->next->physaddr | 498 EHCI_LINK_QH); 499 } 500 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 501 sqh->qh.qh_curqtd = EHCI_NULL; 502 sqh->next = NULL; 503 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 504 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 505 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 506 sqh->sqtd = NULL; 507 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 508 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 509 } 510 /* Point the frame list at the last level (128ms). */ 511 for (i = 0; i < sc->sc_flsize; i++) { 512 int j; 513 514 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 515 revbits[i & (EHCI_MAX_POLLRATE-1)]; 516 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 517 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 518 i)].sqh->physaddr); 519 } 520 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 521 BUS_DMASYNC_PREWRITE); 522 523 /* Allocate dummy QH that starts the async list. */ 524 sqh = ehci_alloc_sqh(sc); 525 if (sqh == NULL) { 526 err = USBD_NOMEM; 527 goto bad1; 528 } 529 /* Fill the QH */ 530 sqh->qh.qh_endp = 531 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 532 sqh->qh.qh_link = 533 htole32(sqh->physaddr | EHCI_LINK_QH); 534 sqh->qh.qh_curqtd = EHCI_NULL; 535 sqh->next = NULL; 536 /* Fill the overlay qTD */ 537 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 538 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 539 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 540 sqh->sqtd = NULL; 541 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 542 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 543 #ifdef EHCI_DEBUG 544 if (ehcidebug) { 545 ehci_dump_sqh(sqh); 546 } 547 #endif 548 549 /* Point to async list */ 550 sc->sc_async_head = sqh; 551 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 552 553 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 554 555 /* Turn on controller */ 556 EOWRITE4(sc, EHCI_USBCMD, 557 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 558 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 559 EHCI_CMD_ASE | 560 EHCI_CMD_PSE | 561 EHCI_CMD_RS); 562 563 /* Take over port ownership */ 564 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 565 566 for (i = 0; i < 100; i++) { 567 usb_delay_ms(&sc->sc_bus, 1); 568 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 569 if (!hcr) 570 break; 571 } 572 if (hcr) { 573 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 574 return (USBD_IOERROR); 575 } 576 577 /* Enable interrupts */ 578 DPRINTFN(1,("ehci_init: enabling\n")); 579 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 580 581 return (USBD_NORMAL_COMPLETION); 582 583 #if 0 584 bad2: 585 ehci_free_sqh(sc, sc->sc_async_head); 586 #endif 587 bad1: 588 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 589 return (err); 590 } 591 592 int 593 ehci_intr(void *v) 594 { 595 ehci_softc_t *sc = v; 596 int ret = 0; 597 598 if (sc == NULL) 599 return 0; 600 601 mutex_spin_enter(&sc->sc_intr_lock); 602 603 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 604 goto done; 605 606 /* If we get an interrupt while polling, then just ignore it. */ 607 if (sc->sc_bus.use_polling) { 608 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 609 610 if (intrs) 611 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 612 #ifdef DIAGNOSTIC 613 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 614 #endif 615 goto done; 616 } 617 618 ret = ehci_intr1(sc); 619 620 done: 621 mutex_spin_exit(&sc->sc_intr_lock); 622 return ret; 623 } 624 625 Static int 626 ehci_intr1(ehci_softc_t *sc) 627 { 628 u_int32_t intrs, eintrs; 629 630 DPRINTFN(20,("ehci_intr1: enter\n")); 631 632 /* In case the interrupt occurs before initialization has completed. */ 633 if (sc == NULL) { 634 #ifdef DIAGNOSTIC 635 printf("ehci_intr1: sc == NULL\n"); 636 #endif 637 return (0); 638 } 639 640 KASSERT(mutex_owned(&sc->sc_intr_lock)); 641 642 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 643 if (!intrs) 644 return (0); 645 646 eintrs = intrs & sc->sc_eintrs; 647 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 648 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 649 (u_int)eintrs)); 650 if (!eintrs) 651 return (0); 652 653 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 654 sc->sc_bus.no_intrs++; 655 if (eintrs & EHCI_STS_IAA) { 656 DPRINTF(("ehci_intr1: door bell\n")); 657 kpreempt_disable(); 658 KASSERT(sc->sc_doorbell_si != NULL); 659 softint_schedule(sc->sc_doorbell_si); 660 kpreempt_enable(); 661 eintrs &= ~EHCI_STS_IAA; 662 } 663 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 664 DPRINTFN(5,("ehci_intr1: %s %s\n", 665 eintrs & EHCI_STS_INT ? "INT" : "", 666 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 667 usb_schedsoftintr(&sc->sc_bus); 668 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 669 } 670 if (eintrs & EHCI_STS_HSE) { 671 printf("%s: unrecoverable error, controller halted\n", 672 device_xname(sc->sc_dev)); 673 /* XXX what else */ 674 } 675 if (eintrs & EHCI_STS_PCD) { 676 kpreempt_disable(); 677 KASSERT(sc->sc_pcd_si != NULL); 678 softint_schedule(sc->sc_pcd_si); 679 kpreempt_enable(); 680 eintrs &= ~EHCI_STS_PCD; 681 } 682 683 if (eintrs != 0) { 684 /* Block unprocessed interrupts. */ 685 sc->sc_eintrs &= ~eintrs; 686 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 687 printf("%s: blocking intrs 0x%x\n", 688 device_xname(sc->sc_dev), eintrs); 689 } 690 691 return (1); 692 } 693 694 Static void 695 ehci_doorbell(void *addr) 696 { 697 ehci_softc_t *sc = addr; 698 699 mutex_enter(&sc->sc_lock); 700 cv_broadcast(&sc->sc_doorbell); 701 mutex_exit(&sc->sc_lock); 702 } 703 704 Static void 705 ehci_pcd(void *addr) 706 { 707 ehci_softc_t *sc = addr; 708 usbd_xfer_handle xfer; 709 u_char *p; 710 int i, m; 711 712 mutex_enter(&sc->sc_lock); 713 xfer = sc->sc_intrxfer; 714 715 if (xfer == NULL) { 716 /* Just ignore the change. */ 717 goto done; 718 } 719 720 p = KERNADDR(&xfer->dmabuf, 0); 721 m = min(sc->sc_noport, xfer->length * 8 - 1); 722 memset(p, 0, xfer->length); 723 for (i = 1; i <= m; i++) { 724 /* Pick out CHANGE bits from the status reg. */ 725 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 726 p[i/8] |= 1 << (i%8); 727 } 728 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 729 xfer->actlen = xfer->length; 730 xfer->status = USBD_NORMAL_COMPLETION; 731 732 usb_transfer_complete(xfer); 733 734 done: 735 mutex_exit(&sc->sc_lock); 736 } 737 738 Static void 739 ehci_softintr(void *v) 740 { 741 struct usbd_bus *bus = v; 742 ehci_softc_t *sc = bus->hci_private; 743 struct ehci_xfer *ex, *nextex; 744 745 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 746 747 DPRINTFN(10,("%s: ehci_softintr\n", device_xname(sc->sc_dev))); 748 749 /* 750 * The only explanation I can think of for why EHCI is as brain dead 751 * as UHCI interrupt-wise is that Intel was involved in both. 752 * An interrupt just tells us that something is done, we have no 753 * clue what, so we need to scan through all active transfers. :-( 754 */ 755 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 756 nextex = TAILQ_NEXT(ex, inext); 757 ehci_check_intr(sc, ex); 758 } 759 760 /* Schedule a callout to catch any dropped transactions. */ 761 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 762 !TAILQ_EMPTY(&sc->sc_intrhead)) 763 callout_reset(&sc->sc_tmo_intrlist, 764 hz, ehci_intrlist_timeout, sc); 765 766 if (sc->sc_softwake) { 767 sc->sc_softwake = 0; 768 cv_broadcast(&sc->sc_softwake_cv); 769 } 770 } 771 772 /* Check for an interrupt. */ 773 Static void 774 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 775 { 776 int attr; 777 778 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 779 780 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 781 782 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 783 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 784 ehci_check_itd_intr(sc, ex); 785 else 786 ehci_check_qh_intr(sc, ex); 787 788 return; 789 } 790 791 Static void 792 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 793 { 794 ehci_soft_qtd_t *sqtd, *lsqtd; 795 __uint32_t status; 796 797 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 798 799 if (ex->sqtdstart == NULL) { 800 printf("ehci_check_qh_intr: not valid sqtd\n"); 801 return; 802 } 803 804 lsqtd = ex->sqtdend; 805 #ifdef DIAGNOSTIC 806 if (lsqtd == NULL) { 807 printf("ehci_check_qh_intr: lsqtd==0\n"); 808 return; 809 } 810 #endif 811 /* 812 * If the last TD is still active we need to check whether there 813 * is an error somewhere in the middle, or whether there was a 814 * short packet (SPD and not ACTIVE). 815 */ 816 usb_syncmem(&lsqtd->dma, 817 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 818 sizeof(lsqtd->qtd.qtd_status), 819 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 820 status = le32toh(lsqtd->qtd.qtd_status); 821 usb_syncmem(&lsqtd->dma, 822 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 823 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 824 if (status & EHCI_QTD_ACTIVE) { 825 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 826 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 827 usb_syncmem(&sqtd->dma, 828 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 829 sizeof(sqtd->qtd.qtd_status), 830 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 831 status = le32toh(sqtd->qtd.qtd_status); 832 usb_syncmem(&sqtd->dma, 833 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 834 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 835 /* If there's an active QTD the xfer isn't done. */ 836 if (status & EHCI_QTD_ACTIVE) 837 break; 838 /* Any kind of error makes the xfer done. */ 839 if (status & EHCI_QTD_HALTED) 840 goto done; 841 /* We want short packets, and it is short: it's done */ 842 if (EHCI_QTD_GET_BYTES(status) != 0) 843 goto done; 844 } 845 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 846 ex, ex->sqtdstart)); 847 return; 848 } 849 done: 850 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 851 callout_stop(&ex->xfer.timeout_handle); 852 ehci_idone(ex); 853 } 854 855 Static void 856 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 857 { 858 ehci_soft_itd_t *itd; 859 int i; 860 861 KASSERT(mutex_owned(&sc->sc_lock)); 862 863 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 864 return; 865 866 if (ex->itdstart == NULL) { 867 printf("ehci_check_itd_intr: not valid itd\n"); 868 return; 869 } 870 871 itd = ex->itdend; 872 #ifdef DIAGNOSTIC 873 if (itd == NULL) { 874 printf("ehci_check_itd_intr: itdend == 0\n"); 875 return; 876 } 877 #endif 878 879 /* 880 * check no active transfers in last itd, meaning we're finished 881 */ 882 883 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 884 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 885 BUS_DMASYNC_POSTREAD); 886 887 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 888 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 889 break; 890 } 891 892 if (i == EHCI_ITD_NUFRAMES) { 893 goto done; /* All 8 descriptors inactive, it's done */ 894 } 895 896 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 897 ex->itdstart)); 898 return; 899 done: 900 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 901 callout_stop(&ex->xfer.timeout_handle); 902 ehci_idone(ex); 903 } 904 905 Static void 906 ehci_idone(struct ehci_xfer *ex) 907 { 908 usbd_xfer_handle xfer = &ex->xfer; 909 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 910 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 911 ehci_soft_qtd_t *sqtd, *lsqtd; 912 u_int32_t status = 0, nstatus = 0; 913 int actlen; 914 915 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 916 917 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 918 919 #ifdef DIAGNOSTIC 920 { 921 if (ex->isdone) { 922 #ifdef EHCI_DEBUG 923 printf("ehci_idone: ex is done!\n "); 924 ehci_dump_exfer(ex); 925 #else 926 printf("ehci_idone: ex=%p is done!\n", ex); 927 #endif 928 return; 929 } 930 ex->isdone = 1; 931 } 932 #endif 933 if (xfer->status == USBD_CANCELLED || 934 xfer->status == USBD_TIMEOUT) { 935 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 936 return; 937 } 938 939 #ifdef EHCI_DEBUG 940 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 941 if (ehcidebug > 10) 942 ehci_dump_sqtds(ex->sqtdstart); 943 #endif 944 945 /* The transfer is done, compute actual length and status. */ 946 947 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 948 == UE_ISOCHRONOUS) { 949 /* Isoc transfer */ 950 struct ehci_soft_itd *itd; 951 int i, nframes, len, uframes; 952 953 nframes = 0; 954 actlen = 0; 955 956 i = xfer->pipe->endpoint->edesc->bInterval; 957 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 958 959 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 960 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 961 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 962 BUS_DMASYNC_POSTREAD); 963 964 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 965 /* XXX - driver didn't fill in the frame full 966 * of uframes. This leads to scheduling 967 * inefficiencies, but working around 968 * this doubles complexity of tracking 969 * an xfer. 970 */ 971 if (nframes >= xfer->nframes) 972 break; 973 974 status = le32toh(itd->itd.itd_ctl[i]); 975 len = EHCI_ITD_GET_LEN(status); 976 if (EHCI_ITD_GET_STATUS(status) != 0) 977 len = 0; /*No valid data on error*/ 978 979 xfer->frlengths[nframes++] = len; 980 actlen += len; 981 } 982 983 if (nframes >= xfer->nframes) 984 break; 985 } 986 987 xfer->actlen = actlen; 988 xfer->status = USBD_NORMAL_COMPLETION; 989 goto end; 990 } 991 992 /* Continue processing xfers using queue heads */ 993 994 lsqtd = ex->sqtdend; 995 actlen = 0; 996 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 997 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 998 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 999 nstatus = le32toh(sqtd->qtd.qtd_status); 1000 if (nstatus & EHCI_QTD_ACTIVE) 1001 break; 1002 1003 status = nstatus; 1004 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1005 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1006 } 1007 1008 1009 /* 1010 * If there are left over TDs we need to update the toggle. 1011 * The default pipe doesn't need it since control transfers 1012 * start the toggle at 0 every time. 1013 * For a short transfer we need to update the toggle for the missing 1014 * packets within the qTD. 1015 */ 1016 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1017 xfer->pipe->device->default_pipe != xfer->pipe) { 1018 DPRINTFN(2, ("ehci_idone: need toggle update " 1019 "status=%08x nstatus=%08x\n", status, nstatus)); 1020 #if 0 1021 ehci_dump_sqh(epipe->sqh); 1022 ehci_dump_sqtds(ex->sqtdstart); 1023 #endif 1024 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1025 } 1026 1027 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 1028 xfer->length, actlen, status)); 1029 xfer->actlen = actlen; 1030 if (status & EHCI_QTD_HALTED) { 1031 #ifdef EHCI_DEBUG 1032 char sbuf[128]; 1033 1034 snprintb(sbuf, sizeof(sbuf), 1035 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 1036 (u_int32_t)status); 1037 1038 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 1039 "status 0x%s\n", 1040 xfer->pipe->device->address, 1041 xfer->pipe->endpoint->edesc->bEndpointAddress, 1042 sbuf)); 1043 if (ehcidebug > 2) { 1044 ehci_dump_sqh(epipe->sqh); 1045 ehci_dump_sqtds(ex->sqtdstart); 1046 } 1047 #endif 1048 /* low&full speed has an extra error flag */ 1049 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1050 EHCI_QH_SPEED_HIGH) 1051 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1052 else 1053 status &= EHCI_QTD_STATERRS; 1054 if (status == 0) /* no other errors means a stall */ { 1055 xfer->status = USBD_STALLED; 1056 } else { 1057 xfer->status = USBD_IOERROR; /* more info XXX */ 1058 } 1059 /* XXX need to reset TT on missed microframe */ 1060 if (status & EHCI_QTD_MISSEDMICRO) { 1061 printf("%s: missed microframe, TT reset not " 1062 "implemented, hub might be inoperational\n", 1063 device_xname(sc->sc_dev)); 1064 } 1065 } else { 1066 xfer->status = USBD_NORMAL_COMPLETION; 1067 } 1068 1069 end: 1070 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1071 * during this call, before methods->done is called: dma sync required 1072 * beforehand? */ 1073 usb_transfer_complete(xfer); 1074 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1075 } 1076 1077 /* 1078 * Wait here until controller claims to have an interrupt. 1079 * Then call ehci_intr and return. Use timeout to avoid waiting 1080 * too long. 1081 */ 1082 Static void 1083 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1084 { 1085 int timo; 1086 u_int32_t intrs; 1087 1088 xfer->status = USBD_IN_PROGRESS; 1089 for (timo = xfer->timeout; timo >= 0; timo--) { 1090 usb_delay_ms(&sc->sc_bus, 1); 1091 if (sc->sc_dying) 1092 break; 1093 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1094 sc->sc_eintrs; 1095 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1096 #ifdef EHCI_DEBUG 1097 if (ehcidebug > 15) 1098 ehci_dump_regs(sc); 1099 #endif 1100 if (intrs) { 1101 mutex_spin_enter(&sc->sc_intr_lock); 1102 ehci_intr1(sc); 1103 mutex_spin_exit(&sc->sc_intr_lock); 1104 if (xfer->status != USBD_IN_PROGRESS) 1105 return; 1106 } 1107 } 1108 1109 /* Timeout */ 1110 DPRINTF(("ehci_waitintr: timeout\n")); 1111 xfer->status = USBD_TIMEOUT; 1112 mutex_enter(&sc->sc_lock); 1113 usb_transfer_complete(xfer); 1114 mutex_exit(&sc->sc_lock); 1115 /* XXX should free TD */ 1116 } 1117 1118 Static void 1119 ehci_poll(struct usbd_bus *bus) 1120 { 1121 ehci_softc_t *sc = bus->hci_private; 1122 #ifdef EHCI_DEBUG 1123 static int last; 1124 int new; 1125 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1126 if (new != last) { 1127 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1128 last = new; 1129 } 1130 #endif 1131 1132 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1133 mutex_spin_enter(&sc->sc_intr_lock); 1134 ehci_intr1(sc); 1135 mutex_spin_exit(&sc->sc_intr_lock); 1136 } 1137 } 1138 1139 void 1140 ehci_childdet(device_t self, device_t child) 1141 { 1142 struct ehci_softc *sc = device_private(self); 1143 1144 KASSERT(sc->sc_child == child); 1145 sc->sc_child = NULL; 1146 } 1147 1148 int 1149 ehci_detach(struct ehci_softc *sc, int flags) 1150 { 1151 int rv = 0; 1152 1153 if (sc->sc_child != NULL) 1154 rv = config_detach(sc->sc_child, flags); 1155 1156 if (rv != 0) 1157 return (rv); 1158 1159 callout_halt(&sc->sc_tmo_intrlist, NULL); 1160 callout_destroy(&sc->sc_tmo_intrlist); 1161 1162 /* XXX free other data structures XXX */ 1163 if (sc->sc_softitds) 1164 kmem_free(sc->sc_softitds, 1165 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1166 cv_destroy(&sc->sc_doorbell); 1167 cv_destroy(&sc->sc_softwake_cv); 1168 1169 #if 0 1170 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1171 1172 softint_disestablish(sc->sc_doorbell_si); 1173 softint_disestablish(sc->sc_pcd_si); 1174 1175 mutex_destroy(&sc->sc_lock); 1176 mutex_destroy(&sc->sc_intr_lock); 1177 #endif 1178 1179 pool_cache_destroy(sc->sc_xferpool); 1180 1181 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1182 1183 return (rv); 1184 } 1185 1186 1187 int 1188 ehci_activate(device_t self, enum devact act) 1189 { 1190 struct ehci_softc *sc = device_private(self); 1191 1192 switch (act) { 1193 case DVACT_DEACTIVATE: 1194 sc->sc_dying = 1; 1195 return 0; 1196 default: 1197 return EOPNOTSUPP; 1198 } 1199 } 1200 1201 /* 1202 * Handle suspend/resume. 1203 * 1204 * We need to switch to polling mode here, because this routine is 1205 * called from an interrupt context. This is all right since we 1206 * are almost suspended anyway. 1207 * 1208 * Note that this power handler isn't to be registered directly; the 1209 * bus glue needs to call out to it. 1210 */ 1211 bool 1212 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1213 { 1214 ehci_softc_t *sc = device_private(dv); 1215 int i; 1216 uint32_t cmd, hcr; 1217 1218 mutex_spin_enter(&sc->sc_intr_lock); 1219 sc->sc_bus.use_polling++; 1220 mutex_spin_exit(&sc->sc_intr_lock); 1221 1222 for (i = 1; i <= sc->sc_noport; i++) { 1223 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1224 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1225 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1226 } 1227 1228 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1229 1230 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1231 EOWRITE4(sc, EHCI_USBCMD, cmd); 1232 1233 for (i = 0; i < 100; i++) { 1234 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1235 if (hcr == 0) 1236 break; 1237 1238 usb_delay_ms(&sc->sc_bus, 1); 1239 } 1240 if (hcr != 0) 1241 printf("%s: reset timeout\n", device_xname(dv)); 1242 1243 cmd &= ~EHCI_CMD_RS; 1244 EOWRITE4(sc, EHCI_USBCMD, cmd); 1245 1246 for (i = 0; i < 100; i++) { 1247 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1248 if (hcr == EHCI_STS_HCH) 1249 break; 1250 1251 usb_delay_ms(&sc->sc_bus, 1); 1252 } 1253 if (hcr != EHCI_STS_HCH) 1254 printf("%s: config timeout\n", device_xname(dv)); 1255 1256 mutex_spin_enter(&sc->sc_intr_lock); 1257 sc->sc_bus.use_polling--; 1258 mutex_spin_exit(&sc->sc_intr_lock); 1259 1260 return true; 1261 } 1262 1263 bool 1264 ehci_resume(device_t dv, const pmf_qual_t *qual) 1265 { 1266 ehci_softc_t *sc = device_private(dv); 1267 int i; 1268 uint32_t cmd, hcr; 1269 1270 /* restore things in case the bios sucks */ 1271 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1272 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1273 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1274 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1275 1276 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1277 1278 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1279 1280 hcr = 0; 1281 for (i = 1; i <= sc->sc_noport; i++) { 1282 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1283 if ((cmd & EHCI_PS_PO) == 0 && 1284 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1285 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1286 hcr = 1; 1287 } 1288 } 1289 1290 if (hcr) { 1291 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1292 1293 for (i = 1; i <= sc->sc_noport; i++) { 1294 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1295 if ((cmd & EHCI_PS_PO) == 0 && 1296 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1297 EOWRITE4(sc, EHCI_PORTSC(i), 1298 cmd & ~EHCI_PS_FPR); 1299 } 1300 } 1301 1302 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1303 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1304 1305 for (i = 0; i < 100; i++) { 1306 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1307 if (hcr != EHCI_STS_HCH) 1308 break; 1309 1310 usb_delay_ms(&sc->sc_bus, 1); 1311 } 1312 if (hcr == EHCI_STS_HCH) 1313 printf("%s: config timeout\n", device_xname(dv)); 1314 1315 return true; 1316 } 1317 1318 /* 1319 * Shut down the controller when the system is going down. 1320 */ 1321 bool 1322 ehci_shutdown(device_t self, int flags) 1323 { 1324 ehci_softc_t *sc = device_private(self); 1325 1326 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1327 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1328 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1329 return true; 1330 } 1331 1332 Static usbd_status 1333 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1334 { 1335 struct ehci_softc *sc = bus->hci_private; 1336 usbd_status err; 1337 1338 err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, USBMALLOC_MULTISEG); 1339 #ifdef EHCI_DEBUG 1340 if (err) 1341 printf("ehci_allocm: usb_allocmem_flags()= %s (%d)\n", 1342 usbd_errstr(err), err); 1343 #endif 1344 if (err == USBD_NOMEM) 1345 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1346 #ifdef EHCI_DEBUG 1347 if (err) 1348 printf("ehci_allocm: usb_reserve_allocm()= %s (%d)\n", 1349 usbd_errstr(err), err); 1350 #endif 1351 return (err); 1352 } 1353 1354 Static void 1355 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1356 { 1357 struct ehci_softc *sc = bus->hci_private; 1358 1359 if (dma->block->flags & USB_DMA_RESERVE) { 1360 usb_reserve_freem(&sc->sc_dma_reserve, 1361 dma); 1362 return; 1363 } 1364 usb_freemem(&sc->sc_bus, dma); 1365 } 1366 1367 Static usbd_xfer_handle 1368 ehci_allocx(struct usbd_bus *bus) 1369 { 1370 struct ehci_softc *sc = bus->hci_private; 1371 usbd_xfer_handle xfer; 1372 1373 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1374 if (xfer != NULL) { 1375 memset(xfer, 0, sizeof(struct ehci_xfer)); 1376 #ifdef DIAGNOSTIC 1377 EXFER(xfer)->isdone = 1; 1378 xfer->busy_free = XFER_BUSY; 1379 #endif 1380 } 1381 return (xfer); 1382 } 1383 1384 Static void 1385 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1386 { 1387 struct ehci_softc *sc = bus->hci_private; 1388 1389 #ifdef DIAGNOSTIC 1390 if (xfer->busy_free != XFER_BUSY) { 1391 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1392 xfer->busy_free); 1393 } 1394 xfer->busy_free = XFER_FREE; 1395 if (!EXFER(xfer)->isdone) { 1396 printf("ehci_freex: !isdone\n"); 1397 } 1398 #endif 1399 pool_cache_put(sc->sc_xferpool, xfer); 1400 } 1401 1402 Static void 1403 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1404 { 1405 struct ehci_softc *sc = bus->hci_private; 1406 1407 *lock = &sc->sc_lock; 1408 } 1409 1410 Static void 1411 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1412 { 1413 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1414 1415 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1416 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1417 #ifdef EHCI_DEBUG 1418 if (ehcidebug) 1419 usbd_dump_pipe(pipe); 1420 #endif 1421 epipe->nexttoggle = 0; 1422 } 1423 1424 Static void 1425 ehci_noop(usbd_pipe_handle pipe) 1426 { 1427 } 1428 1429 #ifdef EHCI_DEBUG 1430 Static void 1431 ehci_dump_regs(ehci_softc_t *sc) 1432 { 1433 int i; 1434 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1435 EOREAD4(sc, EHCI_USBCMD), 1436 EOREAD4(sc, EHCI_USBSTS), 1437 EOREAD4(sc, EHCI_USBINTR)); 1438 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1439 EOREAD4(sc, EHCI_FRINDEX), 1440 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1441 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1442 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1443 for (i = 1; i <= sc->sc_noport; i++) 1444 printf("port %d status=0x%08x\n", i, 1445 EOREAD4(sc, EHCI_PORTSC(i))); 1446 } 1447 1448 /* 1449 * Unused function - this is meant to be called from a kernel 1450 * debugger. 1451 */ 1452 void 1453 ehci_dump(void) 1454 { 1455 ehci_dump_regs(theehci); 1456 } 1457 1458 Static void 1459 ehci_dump_link(ehci_link_t link, int type) 1460 { 1461 link = le32toh(link); 1462 printf("0x%08x", link); 1463 if (link & EHCI_LINK_TERMINATE) 1464 printf("<T>"); 1465 else { 1466 printf("<"); 1467 if (type) { 1468 switch (EHCI_LINK_TYPE(link)) { 1469 case EHCI_LINK_ITD: printf("ITD"); break; 1470 case EHCI_LINK_QH: printf("QH"); break; 1471 case EHCI_LINK_SITD: printf("SITD"); break; 1472 case EHCI_LINK_FSTN: printf("FSTN"); break; 1473 } 1474 } 1475 printf(">"); 1476 } 1477 } 1478 1479 Static void 1480 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1481 { 1482 int i; 1483 u_int32_t stop; 1484 1485 stop = 0; 1486 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1487 ehci_dump_sqtd(sqtd); 1488 usb_syncmem(&sqtd->dma, 1489 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1490 sizeof(sqtd->qtd), 1491 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1492 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1493 usb_syncmem(&sqtd->dma, 1494 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1495 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1496 } 1497 if (sqtd) 1498 printf("dump aborted, too many TDs\n"); 1499 } 1500 1501 Static void 1502 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1503 { 1504 usb_syncmem(&sqtd->dma, sqtd->offs, 1505 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1506 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1507 ehci_dump_qtd(&sqtd->qtd); 1508 usb_syncmem(&sqtd->dma, sqtd->offs, 1509 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1510 } 1511 1512 Static void 1513 ehci_dump_qtd(ehci_qtd_t *qtd) 1514 { 1515 u_int32_t s; 1516 char sbuf[128]; 1517 1518 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1519 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1520 printf("\n"); 1521 s = le32toh(qtd->qtd_status); 1522 snprintb(sbuf, sizeof(sbuf), 1523 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1524 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1525 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1526 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1527 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1528 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1529 EHCI_QTD_GET_PID(s), sbuf); 1530 for (s = 0; s < 5; s++) 1531 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1532 } 1533 1534 Static void 1535 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1536 { 1537 ehci_qh_t *qh = &sqh->qh; 1538 u_int32_t endp, endphub; 1539 1540 usb_syncmem(&sqh->dma, sqh->offs, 1541 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1542 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1543 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1544 endp = le32toh(qh->qh_endp); 1545 printf(" endp=0x%08x\n", endp); 1546 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1547 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1548 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1549 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1550 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1551 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1552 EHCI_QH_GET_NRL(endp)); 1553 endphub = le32toh(qh->qh_endphub); 1554 printf(" endphub=0x%08x\n", endphub); 1555 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1556 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1557 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1558 EHCI_QH_GET_MULT(endphub)); 1559 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1560 printf("Overlay qTD:\n"); 1561 ehci_dump_qtd(&qh->qh_qtd); 1562 usb_syncmem(&sqh->dma, sqh->offs, 1563 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1564 } 1565 1566 #if notyet 1567 Static void 1568 ehci_dump_itd(struct ehci_soft_itd *itd) 1569 { 1570 ehci_isoc_trans_t t; 1571 ehci_isoc_bufr_ptr_t b, b2, b3; 1572 int i; 1573 1574 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1575 1576 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1577 t = le32toh(itd->itd.itd_ctl[i]); 1578 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1579 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1580 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1581 EHCI_ITD_GET_OFFS(t)); 1582 } 1583 printf("ITDbufr: "); 1584 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1585 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1586 1587 b = le32toh(itd->itd.itd_bufr[0]); 1588 b2 = le32toh(itd->itd.itd_bufr[1]); 1589 b3 = le32toh(itd->itd.itd_bufr[2]); 1590 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1591 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1592 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1593 } 1594 1595 Static void 1596 ehci_dump_sitd(struct ehci_soft_itd *itd) 1597 { 1598 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1599 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1600 itd->xfer_next, itd->physaddr, itd->slot); 1601 } 1602 #endif 1603 1604 #ifdef DIAGNOSTIC 1605 Static void 1606 ehci_dump_exfer(struct ehci_xfer *ex) 1607 { 1608 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1609 } 1610 #endif 1611 #endif 1612 1613 Static usbd_status 1614 ehci_open(usbd_pipe_handle pipe) 1615 { 1616 usbd_device_handle dev = pipe->device; 1617 ehci_softc_t *sc = dev->bus->hci_private; 1618 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1619 u_int8_t addr = dev->address; 1620 u_int8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1621 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1622 ehci_soft_qh_t *sqh; 1623 usbd_status err; 1624 int ival, speed, naks; 1625 int hshubaddr, hshubport; 1626 1627 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1628 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1629 1630 if (dev->myhsport) { 1631 /* 1632 * When directly attached FS/LS device while doing embedded 1633 * transaction translations and we are the hub, set the hub 1634 * address to 0 (us). 1635 */ 1636 if (!(sc->sc_flags & EHCIF_ETTF) 1637 || (dev->myhsport->parent->address != sc->sc_addr)) { 1638 hshubaddr = dev->myhsport->parent->address; 1639 } else { 1640 hshubaddr = 0; 1641 } 1642 hshubport = dev->myhsport->portno; 1643 } else { 1644 hshubaddr = 0; 1645 hshubport = 0; 1646 } 1647 1648 if (sc->sc_dying) 1649 return (USBD_IOERROR); 1650 1651 /* toggle state needed for bulk endpoints */ 1652 epipe->nexttoggle = pipe->endpoint->datatoggle; 1653 1654 if (addr == sc->sc_addr) { 1655 switch (ed->bEndpointAddress) { 1656 case USB_CONTROL_ENDPOINT: 1657 pipe->methods = &ehci_root_ctrl_methods; 1658 break; 1659 case UE_DIR_IN | EHCI_INTR_ENDPT: 1660 pipe->methods = &ehci_root_intr_methods; 1661 break; 1662 default: 1663 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1664 ed->bEndpointAddress)); 1665 return (USBD_INVAL); 1666 } 1667 return (USBD_NORMAL_COMPLETION); 1668 } 1669 1670 /* XXX All this stuff is only valid for async. */ 1671 switch (dev->speed) { 1672 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1673 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1674 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1675 default: panic("ehci_open: bad device speed %d", dev->speed); 1676 } 1677 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1678 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1679 "isoc endpoint.\n"); 1680 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1681 "attached to a USB2 hub, and transaction translations are " 1682 "not yet supported.\n"); 1683 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1684 "root hub instead.\n"); 1685 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1686 hshubaddr, hshubport)); 1687 return USBD_INVAL; 1688 } 1689 1690 /* 1691 * For interrupt transfer, nak throttling must be disabled, but for 1692 * the other transfer type, nak throttling should be enabled from the 1693 * viewpoint that avoids the memory thrashing. 1694 */ 1695 naks = (xfertype == UE_INTERRUPT) ? 0 1696 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1697 1698 /* Allocate sqh for everything, save isoc xfers */ 1699 if (xfertype != UE_ISOCHRONOUS) { 1700 sqh = ehci_alloc_sqh(sc); 1701 if (sqh == NULL) 1702 return (USBD_NOMEM); 1703 /* qh_link filled when the QH is added */ 1704 sqh->qh.qh_endp = htole32( 1705 EHCI_QH_SET_ADDR(addr) | 1706 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1707 EHCI_QH_SET_EPS(speed) | 1708 EHCI_QH_DTC | 1709 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1710 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1711 EHCI_QH_CTL : 0) | 1712 EHCI_QH_SET_NRL(naks) 1713 ); 1714 sqh->qh.qh_endphub = htole32( 1715 EHCI_QH_SET_MULT(1) | 1716 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1717 ); 1718 if (speed != EHCI_QH_SPEED_HIGH) 1719 sqh->qh.qh_endphub |= htole32( 1720 EHCI_QH_SET_PORT(hshubport) | 1721 EHCI_QH_SET_HUBA(hshubaddr) | 1722 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1723 ); 1724 sqh->qh.qh_curqtd = EHCI_NULL; 1725 /* Fill the overlay qTD */ 1726 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1727 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1728 sqh->qh.qh_qtd.qtd_status = htole32(0); 1729 1730 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1731 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1732 epipe->sqh = sqh; 1733 } else { 1734 sqh = NULL; 1735 } /*xfertype == UE_ISOC*/ 1736 1737 switch (xfertype) { 1738 case UE_CONTROL: 1739 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1740 0, &epipe->u.ctl.reqdma); 1741 #ifdef EHCI_DEBUG 1742 if (err) 1743 printf("ehci_open: usb_allocmem()=%d\n", err); 1744 #endif 1745 if (err) 1746 goto bad; 1747 pipe->methods = &ehci_device_ctrl_methods; 1748 mutex_enter(&sc->sc_lock); 1749 ehci_add_qh(sc, sqh, sc->sc_async_head); 1750 mutex_exit(&sc->sc_lock); 1751 break; 1752 case UE_BULK: 1753 pipe->methods = &ehci_device_bulk_methods; 1754 mutex_enter(&sc->sc_lock); 1755 ehci_add_qh(sc, sqh, sc->sc_async_head); 1756 mutex_exit(&sc->sc_lock); 1757 break; 1758 case UE_INTERRUPT: 1759 pipe->methods = &ehci_device_intr_methods; 1760 ival = pipe->interval; 1761 if (ival == USBD_DEFAULT_INTERVAL) { 1762 if (speed == EHCI_QH_SPEED_HIGH) { 1763 if (ed->bInterval > 16) { 1764 /* 1765 * illegal with high-speed, but there 1766 * were documentation bugs in the spec, 1767 * so be generous 1768 */ 1769 ival = 256; 1770 } else 1771 ival = (1 << (ed->bInterval - 1)) / 8; 1772 } else 1773 ival = ed->bInterval; 1774 } 1775 err = ehci_device_setintr(sc, sqh, ival); 1776 if (err) 1777 goto bad; 1778 break; 1779 case UE_ISOCHRONOUS: 1780 pipe->methods = &ehci_device_isoc_methods; 1781 if (ed->bInterval == 0 || ed->bInterval > 16) { 1782 printf("ehci: opening pipe with invalid bInterval\n"); 1783 err = USBD_INVAL; 1784 goto bad; 1785 } 1786 if (UGETW(ed->wMaxPacketSize) == 0) { 1787 printf("ehci: zero length endpoint open request\n"); 1788 err = USBD_INVAL; 1789 goto bad; 1790 } 1791 epipe->u.isoc.next_frame = 0; 1792 epipe->u.isoc.cur_xfers = 0; 1793 break; 1794 default: 1795 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1796 err = USBD_INVAL; 1797 goto bad; 1798 } 1799 return (USBD_NORMAL_COMPLETION); 1800 1801 bad: 1802 if (sqh != NULL) 1803 ehci_free_sqh(sc, sqh); 1804 return (err); 1805 } 1806 1807 /* 1808 * Add an ED to the schedule. Called with USB lock held. 1809 */ 1810 Static void 1811 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1812 { 1813 1814 KASSERT(mutex_owned(&sc->sc_lock)); 1815 1816 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1817 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1818 sqh->next = head->next; 1819 sqh->qh.qh_link = head->qh.qh_link; 1820 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1821 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1822 head->next = sqh; 1823 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1824 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1825 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1826 1827 #ifdef EHCI_DEBUG 1828 if (ehcidebug > 5) { 1829 printf("ehci_add_qh:\n"); 1830 ehci_dump_sqh(sqh); 1831 } 1832 #endif 1833 } 1834 1835 /* 1836 * Remove an ED from the schedule. Called with USB lock held. 1837 */ 1838 Static void 1839 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1840 { 1841 ehci_soft_qh_t *p; 1842 1843 KASSERT(mutex_owned(&sc->sc_lock)); 1844 1845 /* XXX */ 1846 for (p = head; p != NULL && p->next != sqh; p = p->next) 1847 ; 1848 if (p == NULL) 1849 panic("ehci_rem_qh: ED not found"); 1850 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1851 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1852 p->next = sqh->next; 1853 p->qh.qh_link = sqh->qh.qh_link; 1854 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1855 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1856 1857 ehci_sync_hc(sc); 1858 } 1859 1860 Static void 1861 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1862 { 1863 int i; 1864 u_int32_t status; 1865 1866 /* Save toggle bit and ping status. */ 1867 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1868 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1869 status = sqh->qh.qh_qtd.qtd_status & 1870 htole32(EHCI_QTD_TOGGLE_MASK | 1871 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1872 /* Set HALTED to make hw leave it alone. */ 1873 sqh->qh.qh_qtd.qtd_status = 1874 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1875 usb_syncmem(&sqh->dma, 1876 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1877 sizeof(sqh->qh.qh_qtd.qtd_status), 1878 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1879 sqh->qh.qh_curqtd = 0; 1880 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1881 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1882 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1883 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1884 sqh->sqtd = sqtd; 1885 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1886 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1887 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1888 sqh->qh.qh_qtd.qtd_status = status; 1889 usb_syncmem(&sqh->dma, 1890 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1891 sizeof(sqh->qh.qh_qtd.qtd_status), 1892 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1893 } 1894 1895 /* 1896 * Ensure that the HC has released all references to the QH. We do this 1897 * by asking for a Async Advance Doorbell interrupt and then we wait for 1898 * the interrupt. 1899 * To make this easier we first obtain exclusive use of the doorbell. 1900 */ 1901 Static void 1902 ehci_sync_hc(ehci_softc_t *sc) 1903 { 1904 int error; 1905 1906 KASSERT(mutex_owned(&sc->sc_lock)); 1907 1908 if (sc->sc_dying) { 1909 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1910 return; 1911 } 1912 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1913 /* ask for doorbell */ 1914 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1915 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1916 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1917 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 1918 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1919 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1920 #ifdef DIAGNOSTIC 1921 if (error) 1922 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 1923 #endif 1924 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1925 } 1926 1927 Static void 1928 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1929 { 1930 struct ehci_soft_itd *itd, *prev; 1931 1932 prev = NULL; 1933 1934 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1935 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1936 1937 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1938 prev = itd->u.frame_list.prev; 1939 /* Unlink itd from hardware chain, or frame array */ 1940 if (prev == NULL) { /* We're at the table head */ 1941 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1942 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1943 usb_syncmem(&sc->sc_fldma, 1944 sizeof(ehci_link_t) * itd->slot, 1945 sizeof(ehci_link_t), 1946 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1947 1948 if (itd->u.frame_list.next != NULL) 1949 itd->u.frame_list.next->u.frame_list.prev = NULL; 1950 } else { 1951 /* XXX this part is untested... */ 1952 prev->itd.itd_next = itd->itd.itd_next; 1953 usb_syncmem(&itd->dma, 1954 itd->offs + offsetof(ehci_itd_t, itd_next), 1955 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1956 1957 prev->u.frame_list.next = itd->u.frame_list.next; 1958 if (itd->u.frame_list.next != NULL) 1959 itd->u.frame_list.next->u.frame_list.prev = prev; 1960 } 1961 } 1962 1963 prev = NULL; 1964 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1965 if (prev != NULL) 1966 ehci_free_itd(sc, prev); 1967 prev = itd; 1968 } 1969 if (prev) 1970 ehci_free_itd(sc, prev); 1971 exfer->itdstart = NULL; 1972 exfer->itdend = NULL; 1973 } 1974 1975 /***********/ 1976 1977 /* 1978 * Data structures and routines to emulate the root hub. 1979 */ 1980 Static usb_device_descriptor_t ehci_devd = { 1981 USB_DEVICE_DESCRIPTOR_SIZE, 1982 UDESC_DEVICE, /* type */ 1983 {0x00, 0x02}, /* USB version */ 1984 UDCLASS_HUB, /* class */ 1985 UDSUBCLASS_HUB, /* subclass */ 1986 UDPROTO_HSHUBSTT, /* protocol */ 1987 64, /* max packet */ 1988 {0},{0},{0x00,0x01}, /* device id */ 1989 1,2,0, /* string indicies */ 1990 1 /* # of configurations */ 1991 }; 1992 1993 Static const usb_device_qualifier_t ehci_odevd = { 1994 USB_DEVICE_DESCRIPTOR_SIZE, 1995 UDESC_DEVICE_QUALIFIER, /* type */ 1996 {0x00, 0x02}, /* USB version */ 1997 UDCLASS_HUB, /* class */ 1998 UDSUBCLASS_HUB, /* subclass */ 1999 UDPROTO_FSHUB, /* protocol */ 2000 64, /* max packet */ 2001 1, /* # of configurations */ 2002 0 2003 }; 2004 2005 Static const usb_config_descriptor_t ehci_confd = { 2006 USB_CONFIG_DESCRIPTOR_SIZE, 2007 UDESC_CONFIG, 2008 {USB_CONFIG_DESCRIPTOR_SIZE + 2009 USB_INTERFACE_DESCRIPTOR_SIZE + 2010 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2011 1, 2012 1, 2013 0, 2014 UC_ATTR_MBO | UC_SELF_POWERED, 2015 0 /* max power */ 2016 }; 2017 2018 Static const usb_interface_descriptor_t ehci_ifcd = { 2019 USB_INTERFACE_DESCRIPTOR_SIZE, 2020 UDESC_INTERFACE, 2021 0, 2022 0, 2023 1, 2024 UICLASS_HUB, 2025 UISUBCLASS_HUB, 2026 UIPROTO_HSHUBSTT, 2027 0 2028 }; 2029 2030 Static const usb_endpoint_descriptor_t ehci_endpd = { 2031 USB_ENDPOINT_DESCRIPTOR_SIZE, 2032 UDESC_ENDPOINT, 2033 UE_DIR_IN | EHCI_INTR_ENDPT, 2034 UE_INTERRUPT, 2035 {8, 0}, /* max packet */ 2036 12 2037 }; 2038 2039 Static const usb_hub_descriptor_t ehci_hubd = { 2040 USB_HUB_DESCRIPTOR_SIZE, 2041 UDESC_HUB, 2042 0, 2043 {0,0}, 2044 0, 2045 0, 2046 {""}, 2047 {""}, 2048 }; 2049 2050 /* 2051 * Simulate a hardware hub by handling all the necessary requests. 2052 */ 2053 Static usbd_status 2054 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2055 { 2056 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2057 usbd_status err; 2058 2059 /* Insert last in queue. */ 2060 mutex_enter(&sc->sc_lock); 2061 err = usb_insert_transfer(xfer); 2062 mutex_exit(&sc->sc_lock); 2063 if (err) 2064 return (err); 2065 2066 /* Pipe isn't running, start first */ 2067 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2068 } 2069 2070 Static usbd_status 2071 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2072 { 2073 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2074 usb_device_request_t *req; 2075 void *buf = NULL; 2076 int port, i; 2077 int len, value, index, l, totlen = 0; 2078 usb_port_status_t ps; 2079 usb_hub_descriptor_t hubd; 2080 usbd_status err; 2081 u_int32_t v; 2082 2083 if (sc->sc_dying) 2084 return (USBD_IOERROR); 2085 2086 #ifdef DIAGNOSTIC 2087 if (!(xfer->rqflags & URQ_REQUEST)) 2088 /* XXX panic */ 2089 return (USBD_INVAL); 2090 #endif 2091 req = &xfer->request; 2092 2093 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2094 req->bmRequestType, req->bRequest)); 2095 2096 len = UGETW(req->wLength); 2097 value = UGETW(req->wValue); 2098 index = UGETW(req->wIndex); 2099 2100 if (len != 0) 2101 buf = KERNADDR(&xfer->dmabuf, 0); 2102 2103 #define C(x,y) ((x) | ((y) << 8)) 2104 switch(C(req->bRequest, req->bmRequestType)) { 2105 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2106 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2107 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2108 /* 2109 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2110 * for the integrated root hub. 2111 */ 2112 break; 2113 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2114 if (len > 0) { 2115 *(u_int8_t *)buf = sc->sc_conf; 2116 totlen = 1; 2117 } 2118 break; 2119 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2120 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2121 if (len == 0) 2122 break; 2123 switch(value >> 8) { 2124 case UDESC_DEVICE: 2125 if ((value & 0xff) != 0) { 2126 err = USBD_IOERROR; 2127 goto ret; 2128 } 2129 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2130 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2131 memcpy(buf, &ehci_devd, l); 2132 break; 2133 /* 2134 * We can't really operate at another speed, but the spec says 2135 * we need this descriptor. 2136 */ 2137 case UDESC_DEVICE_QUALIFIER: 2138 if ((value & 0xff) != 0) { 2139 err = USBD_IOERROR; 2140 goto ret; 2141 } 2142 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2143 memcpy(buf, &ehci_odevd, l); 2144 break; 2145 /* 2146 * We can't really operate at another speed, but the spec says 2147 * we need this descriptor. 2148 */ 2149 case UDESC_OTHER_SPEED_CONFIGURATION: 2150 case UDESC_CONFIG: 2151 if ((value & 0xff) != 0) { 2152 err = USBD_IOERROR; 2153 goto ret; 2154 } 2155 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2156 memcpy(buf, &ehci_confd, l); 2157 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2158 value >> 8; 2159 buf = (char *)buf + l; 2160 len -= l; 2161 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2162 totlen += l; 2163 memcpy(buf, &ehci_ifcd, l); 2164 buf = (char *)buf + l; 2165 len -= l; 2166 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2167 totlen += l; 2168 memcpy(buf, &ehci_endpd, l); 2169 break; 2170 case UDESC_STRING: 2171 #define sd ((usb_string_descriptor_t *)buf) 2172 switch (value & 0xff) { 2173 case 0: /* Language table */ 2174 totlen = usb_makelangtbl(sd, len); 2175 break; 2176 case 1: /* Vendor */ 2177 totlen = usb_makestrdesc(sd, len, 2178 sc->sc_vendor); 2179 break; 2180 case 2: /* Product */ 2181 totlen = usb_makestrdesc(sd, len, 2182 "EHCI root hub"); 2183 break; 2184 } 2185 #undef sd 2186 break; 2187 default: 2188 err = USBD_IOERROR; 2189 goto ret; 2190 } 2191 break; 2192 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2193 if (len > 0) { 2194 *(u_int8_t *)buf = 0; 2195 totlen = 1; 2196 } 2197 break; 2198 case C(UR_GET_STATUS, UT_READ_DEVICE): 2199 if (len > 1) { 2200 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2201 totlen = 2; 2202 } 2203 break; 2204 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2205 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2206 if (len > 1) { 2207 USETW(((usb_status_t *)buf)->wStatus, 0); 2208 totlen = 2; 2209 } 2210 break; 2211 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2212 if (value >= USB_MAX_DEVICES) { 2213 err = USBD_IOERROR; 2214 goto ret; 2215 } 2216 sc->sc_addr = value; 2217 break; 2218 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2219 if (value != 0 && value != 1) { 2220 err = USBD_IOERROR; 2221 goto ret; 2222 } 2223 sc->sc_conf = value; 2224 break; 2225 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2226 break; 2227 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2228 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2229 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2230 err = USBD_IOERROR; 2231 goto ret; 2232 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2233 break; 2234 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2235 break; 2236 /* Hub requests */ 2237 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2238 break; 2239 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2240 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2241 "port=%d feature=%d\n", 2242 index, value)); 2243 if (index < 1 || index > sc->sc_noport) { 2244 err = USBD_IOERROR; 2245 goto ret; 2246 } 2247 port = EHCI_PORTSC(index); 2248 v = EOREAD4(sc, port); 2249 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2250 v &= ~EHCI_PS_CLEAR; 2251 switch(value) { 2252 case UHF_PORT_ENABLE: 2253 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2254 break; 2255 case UHF_PORT_SUSPEND: 2256 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2257 break; 2258 v &= ~EHCI_PS_SUSP; 2259 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2260 /* see USB2 spec ch. 7.1.7.7 */ 2261 usb_delay_ms(&sc->sc_bus, 20); 2262 EOWRITE4(sc, port, v); 2263 usb_delay_ms(&sc->sc_bus, 2); 2264 #ifdef DEBUG 2265 v = EOREAD4(sc, port); 2266 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2267 printf("ehci: resume failed: %x\n", v); 2268 #endif 2269 break; 2270 case UHF_PORT_POWER: 2271 if (sc->sc_hasppc) 2272 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2273 break; 2274 case UHF_PORT_TEST: 2275 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2276 "%d\n", index)); 2277 break; 2278 case UHF_PORT_INDICATOR: 2279 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2280 "%d\n", index)); 2281 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2282 break; 2283 case UHF_C_PORT_CONNECTION: 2284 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2285 break; 2286 case UHF_C_PORT_ENABLE: 2287 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2288 break; 2289 case UHF_C_PORT_SUSPEND: 2290 /* how? */ 2291 break; 2292 case UHF_C_PORT_OVER_CURRENT: 2293 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2294 break; 2295 case UHF_C_PORT_RESET: 2296 sc->sc_isreset[index] = 0; 2297 break; 2298 default: 2299 err = USBD_IOERROR; 2300 goto ret; 2301 } 2302 #if 0 2303 switch(value) { 2304 case UHF_C_PORT_CONNECTION: 2305 case UHF_C_PORT_ENABLE: 2306 case UHF_C_PORT_SUSPEND: 2307 case UHF_C_PORT_OVER_CURRENT: 2308 case UHF_C_PORT_RESET: 2309 default: 2310 break; 2311 } 2312 #endif 2313 break; 2314 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2315 if (len == 0) 2316 break; 2317 if ((value & 0xff) != 0) { 2318 err = USBD_IOERROR; 2319 goto ret; 2320 } 2321 hubd = ehci_hubd; 2322 hubd.bNbrPorts = sc->sc_noport; 2323 v = EOREAD4(sc, EHCI_HCSPARAMS); 2324 USETW(hubd.wHubCharacteristics, 2325 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2326 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2327 ? UHD_PORT_IND : 0); 2328 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2329 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2330 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2331 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2332 l = min(len, hubd.bDescLength); 2333 totlen = l; 2334 memcpy(buf, &hubd, l); 2335 break; 2336 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2337 if (len != 4) { 2338 err = USBD_IOERROR; 2339 goto ret; 2340 } 2341 memset(buf, 0, len); /* ? XXX */ 2342 totlen = len; 2343 break; 2344 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2345 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2346 index)); 2347 if (index < 1 || index > sc->sc_noport) { 2348 err = USBD_IOERROR; 2349 goto ret; 2350 } 2351 if (len != 4) { 2352 err = USBD_IOERROR; 2353 goto ret; 2354 } 2355 v = EOREAD4(sc, EHCI_PORTSC(index)); 2356 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2357 2358 i = UPS_HIGH_SPEED; 2359 if (sc->sc_flags & EHCIF_ETTF) { 2360 /* 2361 * If we are doing embedded transaction translation, 2362 * then directly attached LS/FS devices are reset by 2363 * the EHCI controller itself. PSPD is encoded 2364 * the same way as in USBSTATUS. 2365 */ 2366 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2367 } 2368 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2369 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2370 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2371 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2372 if (v & EHCI_PS_PR) i |= UPS_RESET; 2373 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2374 if (sc->sc_vendor_port_status) 2375 i = sc->sc_vendor_port_status(sc, v, i); 2376 USETW(ps.wPortStatus, i); 2377 i = 0; 2378 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2379 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2380 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2381 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2382 USETW(ps.wPortChange, i); 2383 l = min(len, sizeof ps); 2384 memcpy(buf, &ps, l); 2385 totlen = l; 2386 break; 2387 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2388 err = USBD_IOERROR; 2389 goto ret; 2390 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2391 break; 2392 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2393 if (index < 1 || index > sc->sc_noport) { 2394 err = USBD_IOERROR; 2395 goto ret; 2396 } 2397 port = EHCI_PORTSC(index); 2398 v = EOREAD4(sc, port); 2399 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2400 v &= ~EHCI_PS_CLEAR; 2401 switch(value) { 2402 case UHF_PORT_ENABLE: 2403 EOWRITE4(sc, port, v | EHCI_PS_PE); 2404 break; 2405 case UHF_PORT_SUSPEND: 2406 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2407 break; 2408 case UHF_PORT_RESET: 2409 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2410 index)); 2411 if (EHCI_PS_IS_LOWSPEED(v) 2412 && sc->sc_ncomp > 0 2413 && !(sc->sc_flags & EHCIF_ETTF)) { 2414 /* 2415 * Low speed device on non-ETTF controller or 2416 * unaccompanied controller, give up ownership. 2417 */ 2418 ehci_disown(sc, index, 1); 2419 break; 2420 } 2421 /* Start reset sequence. */ 2422 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2423 EOWRITE4(sc, port, v | EHCI_PS_PR); 2424 /* Wait for reset to complete. */ 2425 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2426 if (sc->sc_dying) { 2427 err = USBD_IOERROR; 2428 goto ret; 2429 } 2430 /* 2431 * An embedded transaction translator will automatically 2432 * terminate the reset sequence so there's no need to 2433 * it. 2434 */ 2435 v = EOREAD4(sc, port); 2436 if (v & EHCI_PS_PR) { 2437 /* Terminate reset sequence. */ 2438 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2439 /* Wait for HC to complete reset. */ 2440 usb_delay_ms(&sc->sc_bus, 2441 EHCI_PORT_RESET_COMPLETE); 2442 if (sc->sc_dying) { 2443 err = USBD_IOERROR; 2444 goto ret; 2445 } 2446 } 2447 2448 v = EOREAD4(sc, port); 2449 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2450 if (v & EHCI_PS_PR) { 2451 printf("%s: port reset timeout\n", 2452 device_xname(sc->sc_dev)); 2453 return (USBD_TIMEOUT); 2454 } 2455 if (!(v & EHCI_PS_PE)) { 2456 /* Not a high speed device, give up ownership.*/ 2457 ehci_disown(sc, index, 0); 2458 break; 2459 } 2460 sc->sc_isreset[index] = 1; 2461 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2462 index, v)); 2463 break; 2464 case UHF_PORT_POWER: 2465 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2466 "%d (has PPC = %d)\n", index, 2467 sc->sc_hasppc)); 2468 if (sc->sc_hasppc) 2469 EOWRITE4(sc, port, v | EHCI_PS_PP); 2470 break; 2471 case UHF_PORT_TEST: 2472 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2473 "%d\n", index)); 2474 break; 2475 case UHF_PORT_INDICATOR: 2476 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2477 "%d\n", index)); 2478 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2479 break; 2480 default: 2481 err = USBD_IOERROR; 2482 goto ret; 2483 } 2484 break; 2485 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2486 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2487 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2488 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2489 break; 2490 default: 2491 err = USBD_IOERROR; 2492 goto ret; 2493 } 2494 xfer->actlen = totlen; 2495 err = USBD_NORMAL_COMPLETION; 2496 ret: 2497 mutex_enter(&sc->sc_lock); 2498 xfer->status = err; 2499 usb_transfer_complete(xfer); 2500 mutex_exit(&sc->sc_lock); 2501 return (USBD_IN_PROGRESS); 2502 } 2503 2504 Static void 2505 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2506 { 2507 int port; 2508 u_int32_t v; 2509 2510 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2511 #ifdef DIAGNOSTIC 2512 if (sc->sc_npcomp != 0) { 2513 int i = (index-1) / sc->sc_npcomp; 2514 if (i >= sc->sc_ncomp) 2515 printf("%s: strange port\n", 2516 device_xname(sc->sc_dev)); 2517 else 2518 printf("%s: handing over %s speed device on " 2519 "port %d to %s\n", 2520 device_xname(sc->sc_dev), 2521 lowspeed ? "low" : "full", 2522 index, device_xname(sc->sc_comps[i])); 2523 } else { 2524 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2525 } 2526 #endif 2527 port = EHCI_PORTSC(index); 2528 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2529 EOWRITE4(sc, port, v | EHCI_PS_PO); 2530 } 2531 2532 /* Abort a root control request. */ 2533 Static void 2534 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2535 { 2536 /* Nothing to do, all transfers are synchronous. */ 2537 } 2538 2539 /* Close the root pipe. */ 2540 Static void 2541 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2542 { 2543 DPRINTF(("ehci_root_ctrl_close\n")); 2544 /* Nothing to do. */ 2545 } 2546 2547 Static void 2548 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2549 { 2550 xfer->hcpriv = NULL; 2551 } 2552 2553 Static usbd_status 2554 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2555 { 2556 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2557 usbd_status err; 2558 2559 /* Insert last in queue. */ 2560 mutex_enter(&sc->sc_lock); 2561 err = usb_insert_transfer(xfer); 2562 mutex_exit(&sc->sc_lock); 2563 if (err) 2564 return (err); 2565 2566 /* Pipe isn't running, start first */ 2567 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2568 } 2569 2570 Static usbd_status 2571 ehci_root_intr_start(usbd_xfer_handle xfer) 2572 { 2573 usbd_pipe_handle pipe = xfer->pipe; 2574 ehci_softc_t *sc = pipe->device->bus->hci_private; 2575 2576 if (sc->sc_dying) 2577 return (USBD_IOERROR); 2578 2579 mutex_enter(&sc->sc_lock); 2580 sc->sc_intrxfer = xfer; 2581 mutex_exit(&sc->sc_lock); 2582 2583 return (USBD_IN_PROGRESS); 2584 } 2585 2586 /* Abort a root interrupt request. */ 2587 Static void 2588 ehci_root_intr_abort(usbd_xfer_handle xfer) 2589 { 2590 #ifdef DIAGNOSTIC 2591 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2592 #endif 2593 2594 KASSERT(mutex_owned(&sc->sc_lock)); 2595 if (xfer->pipe->intrxfer == xfer) { 2596 DPRINTF(("ehci_root_intr_abort: remove\n")); 2597 xfer->pipe->intrxfer = NULL; 2598 } 2599 xfer->status = USBD_CANCELLED; 2600 usb_transfer_complete(xfer); 2601 } 2602 2603 /* Close the root pipe. */ 2604 Static void 2605 ehci_root_intr_close(usbd_pipe_handle pipe) 2606 { 2607 ehci_softc_t *sc = pipe->device->bus->hci_private; 2608 2609 KASSERT(mutex_owned(&sc->sc_lock)); 2610 2611 DPRINTF(("ehci_root_intr_close\n")); 2612 2613 sc->sc_intrxfer = NULL; 2614 } 2615 2616 Static void 2617 ehci_root_intr_done(usbd_xfer_handle xfer) 2618 { 2619 xfer->hcpriv = NULL; 2620 } 2621 2622 /************************/ 2623 2624 Static ehci_soft_qh_t * 2625 ehci_alloc_sqh(ehci_softc_t *sc) 2626 { 2627 ehci_soft_qh_t *sqh; 2628 usbd_status err; 2629 int i, offs; 2630 usb_dma_t dma; 2631 2632 if (sc->sc_freeqhs == NULL) { 2633 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2634 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2635 EHCI_PAGE_SIZE, &dma); 2636 #ifdef EHCI_DEBUG 2637 if (err) 2638 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2639 #endif 2640 if (err) 2641 return (NULL); 2642 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2643 offs = i * EHCI_SQH_SIZE; 2644 sqh = KERNADDR(&dma, offs); 2645 sqh->physaddr = DMAADDR(&dma, offs); 2646 sqh->dma = dma; 2647 sqh->offs = offs; 2648 sqh->next = sc->sc_freeqhs; 2649 sc->sc_freeqhs = sqh; 2650 } 2651 } 2652 sqh = sc->sc_freeqhs; 2653 sc->sc_freeqhs = sqh->next; 2654 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2655 sqh->next = NULL; 2656 return (sqh); 2657 } 2658 2659 Static void 2660 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2661 { 2662 sqh->next = sc->sc_freeqhs; 2663 sc->sc_freeqhs = sqh; 2664 } 2665 2666 Static ehci_soft_qtd_t * 2667 ehci_alloc_sqtd(ehci_softc_t *sc) 2668 { 2669 ehci_soft_qtd_t *sqtd = NULL; 2670 usbd_status err; 2671 int i, offs; 2672 usb_dma_t dma; 2673 2674 if (sc->sc_freeqtds == NULL) { 2675 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2676 2677 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2678 EHCI_PAGE_SIZE, &dma); 2679 #ifdef EHCI_DEBUG 2680 if (err) 2681 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2682 #endif 2683 if (err) 2684 goto done; 2685 2686 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2687 offs = i * EHCI_SQTD_SIZE; 2688 sqtd = KERNADDR(&dma, offs); 2689 sqtd->physaddr = DMAADDR(&dma, offs); 2690 sqtd->dma = dma; 2691 sqtd->offs = offs; 2692 2693 sqtd->nextqtd = sc->sc_freeqtds; 2694 sc->sc_freeqtds = sqtd; 2695 } 2696 } 2697 2698 sqtd = sc->sc_freeqtds; 2699 sc->sc_freeqtds = sqtd->nextqtd; 2700 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2701 sqtd->nextqtd = NULL; 2702 sqtd->xfer = NULL; 2703 2704 done: 2705 return (sqtd); 2706 } 2707 2708 Static void 2709 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2710 { 2711 2712 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 2713 2714 sqtd->nextqtd = sc->sc_freeqtds; 2715 sc->sc_freeqtds = sqtd; 2716 } 2717 2718 Static usbd_status 2719 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2720 int alen, int rd, usbd_xfer_handle xfer, 2721 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2722 { 2723 ehci_soft_qtd_t *next, *cur; 2724 ehci_physaddr_t nextphys; 2725 u_int32_t qtdstatus; 2726 int len, curlen, mps; 2727 int i, tog; 2728 int pages, pageoffs; 2729 bus_size_t curoffs; 2730 vaddr_t va, va_offs; 2731 usb_dma_t *dma = &xfer->dmabuf; 2732 u_int16_t flags = xfer->flags; 2733 paddr_t a; 2734 2735 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2736 2737 len = alen; 2738 qtdstatus = EHCI_QTD_ACTIVE | 2739 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2740 EHCI_QTD_SET_CERR(3) 2741 /* IOC set below */ 2742 /* BYTES set below */ 2743 ; 2744 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2745 tog = epipe->nexttoggle; 2746 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2747 2748 cur = ehci_alloc_sqtd(sc); 2749 *sp = cur; 2750 if (cur == NULL) 2751 goto nomem; 2752 2753 usb_syncmem(dma, 0, alen, 2754 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2755 curoffs = 0; 2756 for (;;) { 2757 /* The EHCI hardware can handle at most 5 pages. */ 2758 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2759 va_offs = EHCI_PAGE_OFFSET(va_offs); 2760 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 2761 /* we can handle it in this QTD */ 2762 curlen = len - curoffs; 2763 } else { 2764 /* must use multiple TDs, fill as much as possible. */ 2765 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 2766 2767 /* the length must be a multiple of the max size */ 2768 curlen -= curlen % mps; 2769 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2770 "curlen=%d\n", curlen)); 2771 #ifdef DIAGNOSTIC 2772 if (curlen == 0) 2773 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2774 #endif 2775 } 2776 DPRINTFN(4,("ehci_alloc_sqtd_chain: len=%d curlen=%d " 2777 "curoffs=%zu\n", len, curlen, (size_t)curoffs)); 2778 2779 /* 2780 * Allocate another transfer if there's more data left, 2781 * or if force last short transfer flag is set and we're 2782 * allocating a multiple of the max packet size. 2783 */ 2784 2785 if (curoffs + curlen != len || 2786 ((curlen % mps) == 0 && !rd && curlen != 0 && 2787 (flags & USBD_FORCE_SHORT_XFER))) { 2788 next = ehci_alloc_sqtd(sc); 2789 if (next == NULL) 2790 goto nomem; 2791 nextphys = htole32(next->physaddr); 2792 } else { 2793 next = NULL; 2794 nextphys = EHCI_NULL; 2795 } 2796 2797 /* Find number of pages we'll be using, insert dma addresses */ 2798 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2799 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2800 pageoffs = EHCI_PAGE(curoffs); 2801 for (i = 0; i < pages; i++) { 2802 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2803 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2804 /* Cast up to avoid compiler warnings */ 2805 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2806 } 2807 2808 /* First buffer pointer requires a page offset to start at */ 2809 va = (vaddr_t)KERNADDR(dma, curoffs); 2810 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2811 2812 cur->nextqtd = next; 2813 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2814 cur->qtd.qtd_status = 2815 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2816 cur->xfer = xfer; 2817 cur->len = curlen; 2818 2819 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08zx end=0x%08zx\n", 2820 (size_t)curoffs, (size_t)(curoffs + curlen))); 2821 2822 /* adjust the toggle based on the number of packets in this 2823 qtd */ 2824 if (((curlen + mps - 1) / mps) & 1) { 2825 tog ^= 1; 2826 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2827 } 2828 if (next == NULL) 2829 break; 2830 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2831 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2832 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2833 if (len) 2834 curoffs += curlen; 2835 cur = next; 2836 } 2837 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2838 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2839 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2840 *ep = cur; 2841 epipe->nexttoggle = tog; 2842 2843 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2844 *sp, *ep)); 2845 2846 return (USBD_NORMAL_COMPLETION); 2847 2848 nomem: 2849 /* XXX free chain */ 2850 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2851 return (USBD_NOMEM); 2852 } 2853 2854 Static void 2855 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2856 ehci_soft_qtd_t *sqtdend) 2857 { 2858 ehci_soft_qtd_t *p; 2859 int i; 2860 2861 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2862 sqtd, sqtdend)); 2863 2864 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2865 p = sqtd->nextqtd; 2866 ehci_free_sqtd(sc, sqtd); 2867 } 2868 } 2869 2870 Static ehci_soft_itd_t * 2871 ehci_alloc_itd(ehci_softc_t *sc) 2872 { 2873 struct ehci_soft_itd *itd, *freeitd; 2874 usbd_status err; 2875 int i, offs, frindex, previndex; 2876 usb_dma_t dma; 2877 2878 mutex_enter(&sc->sc_lock); 2879 2880 /* Find an itd that wasn't freed this frame or last frame. This can 2881 * discard itds that were freed before frindex wrapped around 2882 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2883 * interrupt and fiddling with list when that happens */ 2884 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2885 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2886 2887 freeitd = NULL; 2888 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2889 if (itd == NULL) 2890 break; 2891 if (itd->slot != frindex && itd->slot != previndex) { 2892 freeitd = itd; 2893 break; 2894 } 2895 } 2896 2897 if (freeitd == NULL) { 2898 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2899 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2900 EHCI_PAGE_SIZE, &dma); 2901 2902 if (err) { 2903 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2904 mutex_exit(&sc->sc_lock); 2905 return NULL; 2906 } 2907 2908 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2909 offs = i * EHCI_ITD_SIZE; 2910 itd = KERNADDR(&dma, offs); 2911 itd->physaddr = DMAADDR(&dma, offs); 2912 itd->dma = dma; 2913 itd->offs = offs; 2914 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2915 } 2916 freeitd = LIST_FIRST(&sc->sc_freeitds); 2917 } 2918 2919 itd = freeitd; 2920 LIST_REMOVE(itd, u.free_list); 2921 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2922 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2923 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2924 BUS_DMASYNC_PREREAD); 2925 2926 itd->u.frame_list.next = NULL; 2927 itd->u.frame_list.prev = NULL; 2928 itd->xfer_next = NULL; 2929 itd->slot = 0; 2930 2931 mutex_exit(&sc->sc_lock); 2932 2933 return itd; 2934 } 2935 2936 Static void 2937 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2938 { 2939 2940 KASSERT(mutex_owned(&sc->sc_lock)); 2941 2942 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2943 } 2944 2945 /****************/ 2946 2947 /* 2948 * Close a reqular pipe. 2949 * Assumes that there are no pending transactions. 2950 */ 2951 Static void 2952 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2953 { 2954 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2955 ehci_softc_t *sc = pipe->device->bus->hci_private; 2956 ehci_soft_qh_t *sqh = epipe->sqh; 2957 2958 KASSERT(mutex_owned(&sc->sc_lock)); 2959 2960 ehci_rem_qh(sc, sqh, head); 2961 ehci_free_sqh(sc, epipe->sqh); 2962 } 2963 2964 /* 2965 * Abort a device request. 2966 * If this routine is called at splusb() it guarantees that the request 2967 * will be removed from the hardware scheduling and that the callback 2968 * for it will be called with USBD_CANCELLED status. 2969 * It's impossible to guarantee that the requested transfer will not 2970 * have happened since the hardware runs concurrently. 2971 * If the transaction has already happened we rely on the ordinary 2972 * interrupt processing to process it. 2973 * XXX This is most probably wrong. 2974 * XXXMRG this doesn't make sense anymore. 2975 */ 2976 Static void 2977 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2978 { 2979 #define exfer EXFER(xfer) 2980 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2981 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2982 ehci_soft_qh_t *sqh = epipe->sqh; 2983 ehci_soft_qtd_t *sqtd; 2984 ehci_physaddr_t cur; 2985 u_int32_t qhstatus; 2986 int hit; 2987 int wake; 2988 2989 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2990 2991 KASSERT(mutex_owned(&sc->sc_lock)); 2992 2993 if (sc->sc_dying) { 2994 /* If we're dying, just do the software part. */ 2995 xfer->status = status; /* make software ignore it */ 2996 callout_stop(&xfer->timeout_handle); 2997 usb_transfer_complete(xfer); 2998 return; 2999 } 3000 3001 if (cpu_intr_p() || cpu_softintr_p()) 3002 panic("ehci_abort_xfer: not in process context"); 3003 3004 /* 3005 * If an abort is already in progress then just wait for it to 3006 * complete and return. 3007 */ 3008 if (xfer->hcflags & UXFER_ABORTING) { 3009 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3010 #ifdef DIAGNOSTIC 3011 if (status == USBD_TIMEOUT) 3012 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3013 #endif 3014 /* Override the status which might be USBD_TIMEOUT. */ 3015 xfer->status = status; 3016 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3017 xfer->hcflags |= UXFER_ABORTWAIT; 3018 while (xfer->hcflags & UXFER_ABORTING) 3019 cv_wait(&xfer->hccv, &sc->sc_lock); 3020 return; 3021 } 3022 xfer->hcflags |= UXFER_ABORTING; 3023 3024 /* 3025 * Step 1: Make interrupt routine and hardware ignore xfer. 3026 */ 3027 xfer->status = status; /* make software ignore it */ 3028 callout_stop(&xfer->timeout_handle); 3029 3030 usb_syncmem(&sqh->dma, 3031 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3032 sizeof(sqh->qh.qh_qtd.qtd_status), 3033 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3034 qhstatus = sqh->qh.qh_qtd.qtd_status; 3035 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3036 usb_syncmem(&sqh->dma, 3037 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3038 sizeof(sqh->qh.qh_qtd.qtd_status), 3039 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3040 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3041 usb_syncmem(&sqtd->dma, 3042 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3043 sizeof(sqtd->qtd.qtd_status), 3044 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3045 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3046 usb_syncmem(&sqtd->dma, 3047 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3048 sizeof(sqtd->qtd.qtd_status), 3049 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3050 if (sqtd == exfer->sqtdend) 3051 break; 3052 } 3053 3054 /* 3055 * Step 2: Wait until we know hardware has finished any possible 3056 * use of the xfer. Also make sure the soft interrupt routine 3057 * has run. 3058 */ 3059 ehci_sync_hc(sc); 3060 sc->sc_softwake = 1; 3061 usb_schedsoftintr(&sc->sc_bus); 3062 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3063 3064 /* 3065 * Step 3: Remove any vestiges of the xfer from the hardware. 3066 * The complication here is that the hardware may have executed 3067 * beyond the xfer we're trying to abort. So as we're scanning 3068 * the TDs of this xfer we check if the hardware points to 3069 * any of them. 3070 */ 3071 3072 usb_syncmem(&sqh->dma, 3073 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3074 sizeof(sqh->qh.qh_curqtd), 3075 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3076 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3077 hit = 0; 3078 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3079 hit |= cur == sqtd->physaddr; 3080 if (sqtd == exfer->sqtdend) 3081 break; 3082 } 3083 sqtd = sqtd->nextqtd; 3084 /* Zap curqtd register if hardware pointed inside the xfer. */ 3085 if (hit && sqtd != NULL) { 3086 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3087 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3088 usb_syncmem(&sqh->dma, 3089 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3090 sizeof(sqh->qh.qh_curqtd), 3091 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3092 sqh->qh.qh_qtd.qtd_status = qhstatus; 3093 usb_syncmem(&sqh->dma, 3094 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3095 sizeof(sqh->qh.qh_qtd.qtd_status), 3096 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3097 } else { 3098 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3099 } 3100 3101 /* 3102 * Step 4: Execute callback. 3103 */ 3104 #ifdef DIAGNOSTIC 3105 exfer->isdone = 1; 3106 #endif 3107 wake = xfer->hcflags & UXFER_ABORTWAIT; 3108 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3109 usb_transfer_complete(xfer); 3110 if (wake) { 3111 cv_broadcast(&xfer->hccv); 3112 } 3113 3114 KASSERT(mutex_owned(&sc->sc_lock)); 3115 #undef exfer 3116 } 3117 3118 Static void 3119 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3120 { 3121 ehci_isoc_trans_t trans_status; 3122 struct ehci_pipe *epipe; 3123 struct ehci_xfer *exfer; 3124 ehci_softc_t *sc; 3125 struct ehci_soft_itd *itd; 3126 int i, wake; 3127 3128 epipe = (struct ehci_pipe *) xfer->pipe; 3129 exfer = EXFER(xfer); 3130 sc = epipe->pipe.device->bus->hci_private; 3131 3132 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3133 3134 KASSERT(mutex_owned(&sc->sc_lock)); 3135 3136 if (sc->sc_dying) { 3137 xfer->status = status; 3138 callout_stop(&xfer->timeout_handle); 3139 usb_transfer_complete(xfer); 3140 return; 3141 } 3142 3143 if (xfer->hcflags & UXFER_ABORTING) { 3144 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3145 3146 #ifdef DIAGNOSTIC 3147 if (status == USBD_TIMEOUT) 3148 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3149 #endif 3150 3151 xfer->status = status; 3152 DPRINTFN(2, ("ehci_abort_isoc_xfer: waiting for abort to finish\n")); 3153 xfer->hcflags |= UXFER_ABORTWAIT; 3154 while (xfer->hcflags & UXFER_ABORTING) 3155 cv_wait(&xfer->hccv, &sc->sc_lock); 3156 goto done; 3157 } 3158 xfer->hcflags |= UXFER_ABORTING; 3159 3160 xfer->status = status; 3161 callout_stop(&xfer->timeout_handle); 3162 3163 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3164 usb_syncmem(&itd->dma, 3165 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3166 sizeof(itd->itd.itd_ctl), 3167 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3168 3169 for (i = 0; i < 8; i++) { 3170 trans_status = le32toh(itd->itd.itd_ctl[i]); 3171 trans_status &= ~EHCI_ITD_ACTIVE; 3172 itd->itd.itd_ctl[i] = htole32(trans_status); 3173 } 3174 3175 usb_syncmem(&itd->dma, 3176 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3177 sizeof(itd->itd.itd_ctl), 3178 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3179 } 3180 3181 sc->sc_softwake = 1; 3182 usb_schedsoftintr(&sc->sc_bus); 3183 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3184 3185 #ifdef DIAGNOSTIC 3186 exfer->isdone = 1; 3187 #endif 3188 wake = xfer->hcflags & UXFER_ABORTWAIT; 3189 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3190 usb_transfer_complete(xfer); 3191 if (wake) { 3192 cv_broadcast(&xfer->hccv); 3193 } 3194 3195 done: 3196 KASSERT(mutex_owned(&sc->sc_lock)); 3197 return; 3198 } 3199 3200 Static void 3201 ehci_timeout(void *addr) 3202 { 3203 struct ehci_xfer *exfer = addr; 3204 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3205 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3206 3207 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3208 #ifdef EHCI_DEBUG 3209 if (ehcidebug > 1) 3210 usbd_dump_pipe(exfer->xfer.pipe); 3211 #endif 3212 3213 if (sc->sc_dying) { 3214 mutex_enter(&sc->sc_lock); 3215 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3216 mutex_exit(&sc->sc_lock); 3217 return; 3218 } 3219 3220 /* Execute the abort in a process context. */ 3221 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr, 3222 USB_TASKQ_MPSAFE); 3223 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3224 USB_TASKQ_HC); 3225 } 3226 3227 Static void 3228 ehci_timeout_task(void *addr) 3229 { 3230 usbd_xfer_handle xfer = addr; 3231 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3232 3233 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3234 3235 mutex_enter(&sc->sc_lock); 3236 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3237 mutex_exit(&sc->sc_lock); 3238 } 3239 3240 /************************/ 3241 3242 Static usbd_status 3243 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3244 { 3245 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3246 usbd_status err; 3247 3248 /* Insert last in queue. */ 3249 mutex_enter(&sc->sc_lock); 3250 err = usb_insert_transfer(xfer); 3251 mutex_exit(&sc->sc_lock); 3252 if (err) 3253 return (err); 3254 3255 /* Pipe isn't running, start first */ 3256 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3257 } 3258 3259 Static usbd_status 3260 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3261 { 3262 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3263 usbd_status err; 3264 3265 if (sc->sc_dying) 3266 return (USBD_IOERROR); 3267 3268 #ifdef DIAGNOSTIC 3269 if (!(xfer->rqflags & URQ_REQUEST)) { 3270 /* XXX panic */ 3271 printf("ehci_device_ctrl_transfer: not a request\n"); 3272 return (USBD_INVAL); 3273 } 3274 #endif 3275 3276 err = ehci_device_request(xfer); 3277 if (err) { 3278 return (err); 3279 } 3280 3281 if (sc->sc_bus.use_polling) 3282 ehci_waitintr(sc, xfer); 3283 3284 return (USBD_IN_PROGRESS); 3285 } 3286 3287 Static void 3288 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3289 { 3290 struct ehci_xfer *ex = EXFER(xfer); 3291 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3292 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3293 usb_device_request_t *req = &xfer->request; 3294 int len = UGETW(req->wLength); 3295 int rd = req->bmRequestType & UT_READ; 3296 3297 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3298 3299 KASSERT(mutex_owned(&sc->sc_lock)); 3300 3301 #ifdef DIAGNOSTIC 3302 if (!(xfer->rqflags & URQ_REQUEST)) { 3303 panic("ehci_ctrl_done: not a request"); 3304 } 3305 #endif 3306 3307 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3308 ehci_del_intr_list(sc, ex); /* remove from active list */ 3309 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3310 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3311 BUS_DMASYNC_POSTWRITE); 3312 if (len) 3313 usb_syncmem(&xfer->dmabuf, 0, len, 3314 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3315 } 3316 3317 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3318 } 3319 3320 /* Abort a device control request. */ 3321 Static void 3322 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3323 { 3324 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3325 ehci_abort_xfer(xfer, USBD_CANCELLED); 3326 } 3327 3328 /* Close a device control pipe. */ 3329 Static void 3330 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3331 { 3332 ehci_softc_t *sc = pipe->device->bus->hci_private; 3333 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3334 3335 KASSERT(mutex_owned(&sc->sc_lock)); 3336 3337 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3338 3339 ehci_close_pipe(pipe, sc->sc_async_head); 3340 } 3341 3342 Static usbd_status 3343 ehci_device_request(usbd_xfer_handle xfer) 3344 { 3345 #define exfer EXFER(xfer) 3346 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3347 usb_device_request_t *req = &xfer->request; 3348 usbd_device_handle dev = epipe->pipe.device; 3349 ehci_softc_t *sc = dev->bus->hci_private; 3350 int addr = dev->address; 3351 ehci_soft_qtd_t *setup, *stat, *next; 3352 ehci_soft_qh_t *sqh; 3353 int isread; 3354 int len; 3355 usbd_status err; 3356 3357 isread = req->bmRequestType & UT_READ; 3358 len = UGETW(req->wLength); 3359 3360 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3361 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3362 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3363 UGETW(req->wIndex), len, addr, 3364 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3365 3366 setup = ehci_alloc_sqtd(sc); 3367 if (setup == NULL) { 3368 err = USBD_NOMEM; 3369 goto bad1; 3370 } 3371 stat = ehci_alloc_sqtd(sc); 3372 if (stat == NULL) { 3373 err = USBD_NOMEM; 3374 goto bad2; 3375 } 3376 3377 mutex_enter(&sc->sc_lock); 3378 3379 sqh = epipe->sqh; 3380 3381 /* 3382 * Update device address and length since they may have changed 3383 * during the setup of the control pipe in usbd_new_device(). 3384 */ 3385 /* XXX This only needs to be done once, but it's too early in open. */ 3386 /* XXXX Should not touch ED here! */ 3387 sqh->qh.qh_endp = 3388 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3389 htole32( 3390 EHCI_QH_SET_ADDR(addr) | 3391 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3392 ); 3393 3394 /* Set up data transaction */ 3395 if (len != 0) { 3396 ehci_soft_qtd_t *end; 3397 3398 /* Start toggle at 1. */ 3399 epipe->nexttoggle = 1; 3400 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3401 &next, &end); 3402 if (err) 3403 goto bad3; 3404 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3405 end->nextqtd = stat; 3406 end->qtd.qtd_next = 3407 end->qtd.qtd_altnext = htole32(stat->physaddr); 3408 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3409 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3410 } else { 3411 next = stat; 3412 } 3413 3414 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3415 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3416 3417 /* Clear toggle */ 3418 setup->qtd.qtd_status = htole32( 3419 EHCI_QTD_ACTIVE | 3420 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3421 EHCI_QTD_SET_CERR(3) | 3422 EHCI_QTD_SET_TOGGLE(0) | 3423 EHCI_QTD_SET_BYTES(sizeof *req) 3424 ); 3425 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3426 setup->qtd.qtd_buffer_hi[0] = 0; 3427 setup->nextqtd = next; 3428 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3429 setup->xfer = xfer; 3430 setup->len = sizeof *req; 3431 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3432 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3433 3434 stat->qtd.qtd_status = htole32( 3435 EHCI_QTD_ACTIVE | 3436 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3437 EHCI_QTD_SET_CERR(3) | 3438 EHCI_QTD_SET_TOGGLE(1) | 3439 EHCI_QTD_IOC 3440 ); 3441 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3442 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3443 stat->nextqtd = NULL; 3444 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3445 stat->xfer = xfer; 3446 stat->len = 0; 3447 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3448 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3449 3450 #ifdef EHCI_DEBUG 3451 if (ehcidebug > 5) { 3452 DPRINTF(("ehci_device_request:\n")); 3453 ehci_dump_sqh(sqh); 3454 ehci_dump_sqtds(setup); 3455 } 3456 #endif 3457 3458 exfer->sqtdstart = setup; 3459 exfer->sqtdend = stat; 3460 #ifdef DIAGNOSTIC 3461 if (!exfer->isdone) { 3462 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3463 } 3464 exfer->isdone = 0; 3465 #endif 3466 3467 /* Insert qTD in QH list. */ 3468 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3469 if (xfer->timeout && !sc->sc_bus.use_polling) { 3470 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3471 ehci_timeout, xfer); 3472 } 3473 ehci_add_intr_list(sc, exfer); 3474 xfer->status = USBD_IN_PROGRESS; 3475 mutex_exit(&sc->sc_lock); 3476 3477 #ifdef EHCI_DEBUG 3478 if (ehcidebug > 10) { 3479 DPRINTF(("ehci_device_request: status=%x\n", 3480 EOREAD4(sc, EHCI_USBSTS))); 3481 delay(10000); 3482 ehci_dump_regs(sc); 3483 ehci_dump_sqh(sc->sc_async_head); 3484 ehci_dump_sqh(sqh); 3485 ehci_dump_sqtds(setup); 3486 } 3487 #endif 3488 3489 return (USBD_NORMAL_COMPLETION); 3490 3491 bad3: 3492 mutex_exit(&sc->sc_lock); 3493 ehci_free_sqtd(sc, stat); 3494 bad2: 3495 ehci_free_sqtd(sc, setup); 3496 bad1: 3497 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3498 mutex_enter(&sc->sc_lock); 3499 xfer->status = err; 3500 usb_transfer_complete(xfer); 3501 mutex_exit(&sc->sc_lock); 3502 return (err); 3503 #undef exfer 3504 } 3505 3506 /* 3507 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3508 * qTD status, or miss signalling occasionally under heavy load. If the host 3509 * machine is too fast, we we can miss transaction completion - when we scan 3510 * the active list the transaction still seems to be active. This generally 3511 * exhibits itself as a umass stall that never recovers. 3512 * 3513 * We work around this behaviour by setting up this callback after any softintr 3514 * that completes with transactions still pending, giving us another chance to 3515 * check for completion after the writeback has taken place. 3516 */ 3517 Static void 3518 ehci_intrlist_timeout(void *arg) 3519 { 3520 ehci_softc_t *sc = arg; 3521 3522 DPRINTF(("ehci_intrlist_timeout\n")); 3523 usb_schedsoftintr(&sc->sc_bus); 3524 } 3525 3526 /************************/ 3527 3528 Static usbd_status 3529 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3530 { 3531 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3532 usbd_status err; 3533 3534 /* Insert last in queue. */ 3535 mutex_enter(&sc->sc_lock); 3536 err = usb_insert_transfer(xfer); 3537 mutex_exit(&sc->sc_lock); 3538 if (err) 3539 return (err); 3540 3541 /* Pipe isn't running, start first */ 3542 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3543 } 3544 3545 Static usbd_status 3546 ehci_device_bulk_start(usbd_xfer_handle xfer) 3547 { 3548 #define exfer EXFER(xfer) 3549 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3550 usbd_device_handle dev = epipe->pipe.device; 3551 ehci_softc_t *sc = dev->bus->hci_private; 3552 ehci_soft_qtd_t *data, *dataend; 3553 ehci_soft_qh_t *sqh; 3554 usbd_status err; 3555 int len, isread, endpt; 3556 3557 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3558 xfer, xfer->length, xfer->flags)); 3559 3560 if (sc->sc_dying) 3561 return (USBD_IOERROR); 3562 3563 #ifdef DIAGNOSTIC 3564 if (xfer->rqflags & URQ_REQUEST) 3565 panic("ehci_device_bulk_start: a request"); 3566 #endif 3567 3568 mutex_enter(&sc->sc_lock); 3569 3570 len = xfer->length; 3571 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3572 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3573 sqh = epipe->sqh; 3574 3575 epipe->u.bulk.length = len; 3576 3577 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3578 &dataend); 3579 if (err) { 3580 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3581 xfer->status = err; 3582 usb_transfer_complete(xfer); 3583 mutex_exit(&sc->sc_lock); 3584 return (err); 3585 } 3586 3587 #ifdef EHCI_DEBUG 3588 if (ehcidebug > 5) { 3589 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3590 ehci_dump_sqh(sqh); 3591 ehci_dump_sqtds(data); 3592 } 3593 #endif 3594 3595 /* Set up interrupt info. */ 3596 exfer->sqtdstart = data; 3597 exfer->sqtdend = dataend; 3598 #ifdef DIAGNOSTIC 3599 if (!exfer->isdone) { 3600 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3601 } 3602 exfer->isdone = 0; 3603 #endif 3604 3605 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3606 if (xfer->timeout && !sc->sc_bus.use_polling) { 3607 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3608 ehci_timeout, xfer); 3609 } 3610 ehci_add_intr_list(sc, exfer); 3611 xfer->status = USBD_IN_PROGRESS; 3612 mutex_exit(&sc->sc_lock); 3613 3614 #ifdef EHCI_DEBUG 3615 if (ehcidebug > 10) { 3616 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3617 delay(10000); 3618 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3619 ehci_dump_regs(sc); 3620 #if 0 3621 printf("async_head:\n"); 3622 ehci_dump_sqh(sc->sc_async_head); 3623 #endif 3624 printf("sqh:\n"); 3625 ehci_dump_sqh(sqh); 3626 ehci_dump_sqtds(data); 3627 } 3628 #endif 3629 3630 if (sc->sc_bus.use_polling) 3631 ehci_waitintr(sc, xfer); 3632 3633 return (USBD_IN_PROGRESS); 3634 #undef exfer 3635 } 3636 3637 Static void 3638 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3639 { 3640 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3641 ehci_abort_xfer(xfer, USBD_CANCELLED); 3642 } 3643 3644 /* 3645 * Close a device bulk pipe. 3646 */ 3647 Static void 3648 ehci_device_bulk_close(usbd_pipe_handle pipe) 3649 { 3650 ehci_softc_t *sc = pipe->device->bus->hci_private; 3651 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3652 3653 KASSERT(mutex_owned(&sc->sc_lock)); 3654 3655 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3656 pipe->endpoint->datatoggle = epipe->nexttoggle; 3657 ehci_close_pipe(pipe, sc->sc_async_head); 3658 } 3659 3660 Static void 3661 ehci_device_bulk_done(usbd_xfer_handle xfer) 3662 { 3663 struct ehci_xfer *ex = EXFER(xfer); 3664 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3665 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3666 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3667 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3668 3669 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3670 xfer, xfer->actlen)); 3671 3672 KASSERT(mutex_owned(&sc->sc_lock)); 3673 3674 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3675 ehci_del_intr_list(sc, ex); /* remove from active list */ 3676 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3677 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3678 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3679 } 3680 3681 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3682 } 3683 3684 /************************/ 3685 3686 Static usbd_status 3687 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3688 { 3689 struct ehci_soft_islot *isp; 3690 int islot, lev; 3691 3692 /* Find a poll rate that is large enough. */ 3693 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3694 if (EHCI_ILEV_IVAL(lev) <= ival) 3695 break; 3696 3697 /* Pick an interrupt slot at the right level. */ 3698 /* XXX could do better than picking at random */ 3699 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3700 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3701 3702 sqh->islot = islot; 3703 isp = &sc->sc_islots[islot]; 3704 mutex_enter(&sc->sc_lock); 3705 ehci_add_qh(sc, sqh, isp->sqh); 3706 mutex_exit(&sc->sc_lock); 3707 3708 return (USBD_NORMAL_COMPLETION); 3709 } 3710 3711 Static usbd_status 3712 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3713 { 3714 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3715 usbd_status err; 3716 3717 /* Insert last in queue. */ 3718 mutex_enter(&sc->sc_lock); 3719 err = usb_insert_transfer(xfer); 3720 mutex_exit(&sc->sc_lock); 3721 if (err) 3722 return (err); 3723 3724 /* 3725 * Pipe isn't running (otherwise err would be USBD_INPROG), 3726 * so start it first. 3727 */ 3728 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3729 } 3730 3731 Static usbd_status 3732 ehci_device_intr_start(usbd_xfer_handle xfer) 3733 { 3734 #define exfer EXFER(xfer) 3735 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3736 usbd_device_handle dev = xfer->pipe->device; 3737 ehci_softc_t *sc = dev->bus->hci_private; 3738 ehci_soft_qtd_t *data, *dataend; 3739 ehci_soft_qh_t *sqh; 3740 usbd_status err; 3741 int len, isread, endpt; 3742 3743 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3744 xfer, xfer->length, xfer->flags)); 3745 3746 if (sc->sc_dying) 3747 return (USBD_IOERROR); 3748 3749 #ifdef DIAGNOSTIC 3750 if (xfer->rqflags & URQ_REQUEST) 3751 panic("ehci_device_intr_start: a request"); 3752 #endif 3753 3754 mutex_enter(&sc->sc_lock); 3755 3756 len = xfer->length; 3757 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3758 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3759 sqh = epipe->sqh; 3760 3761 epipe->u.intr.length = len; 3762 3763 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3764 &dataend); 3765 if (err) { 3766 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3767 xfer->status = err; 3768 usb_transfer_complete(xfer); 3769 mutex_exit(&sc->sc_lock); 3770 return (err); 3771 } 3772 3773 #ifdef EHCI_DEBUG 3774 if (ehcidebug > 5) { 3775 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3776 ehci_dump_sqh(sqh); 3777 ehci_dump_sqtds(data); 3778 } 3779 #endif 3780 3781 /* Set up interrupt info. */ 3782 exfer->sqtdstart = data; 3783 exfer->sqtdend = dataend; 3784 #ifdef DIAGNOSTIC 3785 if (!exfer->isdone) { 3786 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3787 } 3788 exfer->isdone = 0; 3789 #endif 3790 3791 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3792 if (xfer->timeout && !sc->sc_bus.use_polling) { 3793 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3794 ehci_timeout, xfer); 3795 } 3796 ehci_add_intr_list(sc, exfer); 3797 xfer->status = USBD_IN_PROGRESS; 3798 mutex_exit(&sc->sc_lock); 3799 3800 #ifdef EHCI_DEBUG 3801 if (ehcidebug > 10) { 3802 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3803 delay(10000); 3804 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3805 ehci_dump_regs(sc); 3806 printf("sqh:\n"); 3807 ehci_dump_sqh(sqh); 3808 ehci_dump_sqtds(data); 3809 } 3810 #endif 3811 3812 if (sc->sc_bus.use_polling) 3813 ehci_waitintr(sc, xfer); 3814 3815 return (USBD_IN_PROGRESS); 3816 #undef exfer 3817 } 3818 3819 Static void 3820 ehci_device_intr_abort(usbd_xfer_handle xfer) 3821 { 3822 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3823 if (xfer->pipe->intrxfer == xfer) { 3824 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3825 xfer->pipe->intrxfer = NULL; 3826 } 3827 /* 3828 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3829 * async doorbell. That's dependent on the async list, wheras 3830 * intr xfers are periodic, should not use this? 3831 */ 3832 ehci_abort_xfer(xfer, USBD_CANCELLED); 3833 } 3834 3835 Static void 3836 ehci_device_intr_close(usbd_pipe_handle pipe) 3837 { 3838 ehci_softc_t *sc = pipe->device->bus->hci_private; 3839 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3840 struct ehci_soft_islot *isp; 3841 3842 KASSERT(mutex_owned(&sc->sc_lock)); 3843 3844 isp = &sc->sc_islots[epipe->sqh->islot]; 3845 ehci_close_pipe(pipe, isp->sqh); 3846 } 3847 3848 Static void 3849 ehci_device_intr_done(usbd_xfer_handle xfer) 3850 { 3851 #define exfer EXFER(xfer) 3852 struct ehci_xfer *ex = EXFER(xfer); 3853 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3854 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3855 ehci_soft_qtd_t *data, *dataend; 3856 ehci_soft_qh_t *sqh; 3857 usbd_status err; 3858 int len, isread, endpt; 3859 3860 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3861 xfer, xfer->actlen)); 3862 3863 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 3864 3865 if (xfer->pipe->repeat) { 3866 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3867 3868 len = epipe->u.intr.length; 3869 xfer->length = len; 3870 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3871 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3872 usb_syncmem(&xfer->dmabuf, 0, len, 3873 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3874 sqh = epipe->sqh; 3875 3876 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3877 &data, &dataend); 3878 if (err) { 3879 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3880 xfer->status = err; 3881 return; 3882 } 3883 3884 /* Set up interrupt info. */ 3885 exfer->sqtdstart = data; 3886 exfer->sqtdend = dataend; 3887 #ifdef DIAGNOSTIC 3888 if (!exfer->isdone) { 3889 printf("ehci_device_intr_done: not done, ex=%p\n", 3890 exfer); 3891 } 3892 exfer->isdone = 0; 3893 #endif 3894 3895 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3896 if (xfer->timeout && !sc->sc_bus.use_polling) { 3897 callout_reset(&xfer->timeout_handle, 3898 mstohz(xfer->timeout), ehci_timeout, xfer); 3899 } 3900 3901 xfer->status = USBD_IN_PROGRESS; 3902 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3903 ehci_del_intr_list(sc, ex); /* remove from active list */ 3904 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3905 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3906 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3907 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3908 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3909 } 3910 #undef exfer 3911 } 3912 3913 /************************/ 3914 3915 Static usbd_status 3916 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3917 { 3918 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3919 usbd_status err; 3920 3921 mutex_enter(&sc->sc_lock); 3922 err = usb_insert_transfer(xfer); 3923 mutex_exit(&sc->sc_lock); 3924 if (err && err != USBD_IN_PROGRESS) 3925 return err; 3926 3927 return ehci_device_isoc_start(xfer); 3928 } 3929 3930 Static usbd_status 3931 ehci_device_isoc_start(usbd_xfer_handle xfer) 3932 { 3933 struct ehci_pipe *epipe; 3934 ehci_softc_t *sc; 3935 struct ehci_xfer *exfer; 3936 ehci_soft_itd_t *itd, *prev, *start, *stop; 3937 usb_dma_t *dma_buf; 3938 int i, j, k, frames, uframes, ufrperframe; 3939 int trans_count, offs, total_length; 3940 int frindex; 3941 3942 start = NULL; 3943 prev = NULL; 3944 itd = NULL; 3945 trans_count = 0; 3946 total_length = 0; 3947 exfer = (struct ehci_xfer *) xfer; 3948 sc = xfer->pipe->device->bus->hci_private; 3949 epipe = (struct ehci_pipe *)xfer->pipe; 3950 3951 /* 3952 * To allow continuous transfers, above we start all transfers 3953 * immediately. However, we're still going to get usbd_start_next call 3954 * this when another xfer completes. So, check if this is already 3955 * in progress or not 3956 */ 3957 3958 if (exfer->itdstart != NULL) 3959 return USBD_IN_PROGRESS; 3960 3961 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3962 xfer, xfer->length, xfer->flags)); 3963 3964 if (sc->sc_dying) 3965 return USBD_IOERROR; 3966 3967 /* 3968 * To avoid complication, don't allow a request right now that'll span 3969 * the entire frame table. To within 4 frames, to allow some leeway 3970 * on either side of where the hc currently is. 3971 */ 3972 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3973 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3974 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3975 return USBD_INVAL; 3976 } 3977 3978 #ifdef DIAGNOSTIC 3979 if (xfer->rqflags & URQ_REQUEST) 3980 panic("ehci_device_isoc_start: request\n"); 3981 3982 if (!exfer->isdone) 3983 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3984 exfer->isdone = 0; 3985 #endif 3986 3987 /* 3988 * Step 1: Allocate and initialize itds, how many do we need? 3989 * One per transfer if interval >= 8 microframes, fewer if we use 3990 * multiple microframes per frame. 3991 */ 3992 3993 i = epipe->pipe.endpoint->edesc->bInterval; 3994 if (i > 16 || i == 0) { 3995 /* Spec page 271 says intervals > 16 are invalid */ 3996 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3997 return USBD_INVAL; 3998 } 3999 4000 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4001 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4002 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4003 4004 if (frames == 0) { 4005 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 4006 return USBD_INVAL; 4007 } 4008 4009 dma_buf = &xfer->dmabuf; 4010 offs = 0; 4011 4012 for (i = 0; i < frames; i++) { 4013 int froffs = offs; 4014 itd = ehci_alloc_itd(sc); 4015 4016 if (prev != NULL) { 4017 prev->itd.itd_next = 4018 htole32(itd->physaddr | EHCI_LINK_ITD); 4019 usb_syncmem(&itd->dma, 4020 itd->offs + offsetof(ehci_itd_t, itd_next), 4021 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4022 4023 prev->xfer_next = itd; 4024 } else { 4025 start = itd; 4026 } 4027 4028 /* 4029 * Step 1.5, initialize uframes 4030 */ 4031 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4032 /* Calculate which page in the list this starts in */ 4033 int addr = DMAADDR(dma_buf, froffs); 4034 addr = EHCI_PAGE_OFFSET(addr); 4035 addr += (offs - froffs); 4036 addr = EHCI_PAGE(addr); 4037 addr /= EHCI_PAGE_SIZE; 4038 4039 /* This gets the initial offset into the first page, 4040 * looks how far further along the current uframe 4041 * offset is. Works out how many pages that is. 4042 */ 4043 4044 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4045 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4046 EHCI_ITD_SET_PG(addr) | 4047 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4048 4049 total_length += xfer->frlengths[trans_count]; 4050 offs += xfer->frlengths[trans_count]; 4051 trans_count++; 4052 4053 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4054 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4055 break; 4056 } 4057 } 4058 4059 /* Step 1.75, set buffer pointers. To simplify matters, all 4060 * pointers are filled out for the next 7 hardware pages in 4061 * the dma block, so no need to worry what pages to cover 4062 * and what to not. 4063 */ 4064 4065 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4066 /* 4067 * Don't try to lookup a page that's past the end 4068 * of buffer 4069 */ 4070 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4071 if (page_offs >= dma_buf->block->size) 4072 break; 4073 4074 unsigned long long page = DMAADDR(dma_buf, page_offs); 4075 page = EHCI_PAGE(page); 4076 itd->itd.itd_bufr[j] = 4077 htole32(EHCI_ITD_SET_BPTR(page)); 4078 itd->itd.itd_bufr_hi[j] = 4079 htole32(page >> 32); 4080 } 4081 4082 /* 4083 * Other special values 4084 */ 4085 4086 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4087 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4088 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4089 4090 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4091 ? 1 : 0; 4092 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4093 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4094 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4095 4096 /* FIXME: handle invalid trans */ 4097 itd->itd.itd_bufr[2] |= 4098 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4099 4100 usb_syncmem(&itd->dma, 4101 itd->offs + offsetof(ehci_itd_t, itd_next), 4102 sizeof(ehci_itd_t), 4103 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4104 4105 prev = itd; 4106 } /* End of frame */ 4107 4108 stop = itd; 4109 stop->xfer_next = NULL; 4110 exfer->isoc_len = total_length; 4111 4112 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4113 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4114 4115 /* 4116 * Part 2: Transfer descriptors have now been set up, now they must 4117 * be scheduled into the period frame list. Erk. Not wanting to 4118 * complicate matters, transfer is denied if the transfer spans 4119 * more than the period frame list. 4120 */ 4121 4122 mutex_enter(&sc->sc_lock); 4123 4124 /* Start inserting frames */ 4125 if (epipe->u.isoc.cur_xfers > 0) { 4126 frindex = epipe->u.isoc.next_frame; 4127 } else { 4128 frindex = EOREAD4(sc, EHCI_FRINDEX); 4129 frindex = frindex >> 3; /* Erase microframe index */ 4130 frindex += 2; 4131 } 4132 4133 if (frindex >= sc->sc_flsize) 4134 frindex &= (sc->sc_flsize - 1); 4135 4136 /* What's the frame interval? */ 4137 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4138 if (i / USB_UFRAMES_PER_FRAME == 0) 4139 i = 1; 4140 else 4141 i /= USB_UFRAMES_PER_FRAME; 4142 4143 itd = start; 4144 for (j = 0; j < frames; j++) { 4145 if (itd == NULL) 4146 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4147 4148 itd->itd.itd_next = sc->sc_flist[frindex]; 4149 if (itd->itd.itd_next == 0) 4150 /* FIXME: frindex table gets initialized to NULL 4151 * or EHCI_NULL? */ 4152 itd->itd.itd_next = EHCI_NULL; 4153 4154 usb_syncmem(&itd->dma, 4155 itd->offs + offsetof(ehci_itd_t, itd_next), 4156 sizeof(itd->itd.itd_next), 4157 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4158 4159 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4160 4161 usb_syncmem(&sc->sc_fldma, 4162 sizeof(ehci_link_t) * frindex, 4163 sizeof(ehci_link_t), 4164 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4165 4166 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4167 sc->sc_softitds[frindex] = itd; 4168 if (itd->u.frame_list.next != NULL) 4169 itd->u.frame_list.next->u.frame_list.prev = itd; 4170 itd->slot = frindex; 4171 itd->u.frame_list.prev = NULL; 4172 4173 frindex += i; 4174 if (frindex >= sc->sc_flsize) 4175 frindex -= sc->sc_flsize; 4176 4177 itd = itd->xfer_next; 4178 } 4179 4180 epipe->u.isoc.cur_xfers++; 4181 epipe->u.isoc.next_frame = frindex; 4182 4183 exfer->itdstart = start; 4184 exfer->itdend = stop; 4185 exfer->sqtdstart = NULL; 4186 exfer->sqtdstart = NULL; 4187 4188 ehci_add_intr_list(sc, exfer); 4189 xfer->status = USBD_IN_PROGRESS; 4190 xfer->done = 0; 4191 mutex_exit(&sc->sc_lock); 4192 4193 if (sc->sc_bus.use_polling) { 4194 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4195 ehci_waitintr(sc, xfer); 4196 } 4197 4198 return USBD_IN_PROGRESS; 4199 } 4200 4201 Static void 4202 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4203 { 4204 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4205 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4206 } 4207 4208 Static void 4209 ehci_device_isoc_close(usbd_pipe_handle pipe) 4210 { 4211 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4212 } 4213 4214 Static void 4215 ehci_device_isoc_done(usbd_xfer_handle xfer) 4216 { 4217 struct ehci_xfer *exfer; 4218 ehci_softc_t *sc; 4219 struct ehci_pipe *epipe; 4220 4221 exfer = EXFER(xfer); 4222 sc = xfer->pipe->device->bus->hci_private; 4223 epipe = (struct ehci_pipe *) xfer->pipe; 4224 4225 KASSERT(mutex_owned(&sc->sc_lock)); 4226 4227 epipe->u.isoc.cur_xfers--; 4228 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4229 ehci_del_intr_list(sc, exfer); 4230 ehci_rem_free_itd_chain(sc, exfer); 4231 } 4232 4233 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4234 BUS_DMASYNC_POSTREAD); 4235 4236 } 4237
Indexes created Thu Oct 02 01:09:59 GMT 2025