ehci.c revision 1.215
1 /* $NetBSD: ehci.c,v 1.215 2013/11/04 16:54:36 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.215 2013/11/04 16:54:36 christos Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/kernel.h> 64 #include <sys/kmem.h> 65 #include <sys/device.h> 66 #include <sys/select.h> 67 #include <sys/proc.h> 68 #include <sys/queue.h> 69 #include <sys/mutex.h> 70 #include <sys/bus.h> 71 #include <sys/cpu.h> 72 73 #include <machine/endian.h> 74 75 #include <dev/usb/usb.h> 76 #include <dev/usb/usbdi.h> 77 #include <dev/usb/usbdivar.h> 78 #include <dev/usb/usb_mem.h> 79 #include <dev/usb/usb_quirks.h> 80 81 #include <dev/usb/ehcireg.h> 82 #include <dev/usb/ehcivar.h> 83 #include <dev/usb/usbroothub_subr.h> 84 85 #ifdef EHCI_DEBUG 86 static void __printflike(1, 2) 87 ehciprintf(const char *fmt, ...) 88 { 89 va_list ap; 90 91 va_start(ap, fmt); 92 vprintf(fmt, ap); 93 va_end(ap); 94 } 95 96 #define DPRINTF(x) do { if (ehcidebug) ehciprintf x; } while(0) 97 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) ehciprintf x; } while (0) 98 int ehcidebug = 0; 99 #else 100 #define DPRINTF(x) 101 #define DPRINTFN(n,x) 102 #endif 103 104 struct ehci_pipe { 105 struct usbd_pipe pipe; 106 int nexttoggle; 107 108 ehci_soft_qh_t *sqh; 109 union { 110 ehci_soft_qtd_t *qtd; 111 /* ehci_soft_itd_t *itd; */ 112 } tail; 113 union { 114 /* Control pipe */ 115 struct { 116 usb_dma_t reqdma; 117 } ctl; 118 /* Interrupt pipe */ 119 struct { 120 u_int length; 121 } intr; 122 /* Bulk pipe */ 123 struct { 124 u_int length; 125 } bulk; 126 /* Iso pipe */ 127 struct { 128 u_int next_frame; 129 u_int cur_xfers; 130 } isoc; 131 } u; 132 }; 133 134 Static usbd_status ehci_open(usbd_pipe_handle); 135 Static void ehci_poll(struct usbd_bus *); 136 Static void ehci_softintr(void *); 137 Static int ehci_intr1(ehci_softc_t *); 138 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 139 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 140 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 141 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 142 Static void ehci_idone(struct ehci_xfer *); 143 Static void ehci_timeout(void *); 144 Static void ehci_timeout_task(void *); 145 Static void ehci_intrlist_timeout(void *); 146 Static void ehci_doorbell(void *); 147 Static void ehci_pcd(void *); 148 149 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 150 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 151 152 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 153 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 154 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 155 156 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 157 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 158 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 159 Static void ehci_root_ctrl_close(usbd_pipe_handle); 160 Static void ehci_root_ctrl_done(usbd_xfer_handle); 161 162 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 163 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 164 Static void ehci_root_intr_abort(usbd_xfer_handle); 165 Static void ehci_root_intr_close(usbd_pipe_handle); 166 Static void ehci_root_intr_done(usbd_xfer_handle); 167 168 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 169 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 170 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 171 Static void ehci_device_ctrl_close(usbd_pipe_handle); 172 Static void ehci_device_ctrl_done(usbd_xfer_handle); 173 174 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 175 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 176 Static void ehci_device_bulk_abort(usbd_xfer_handle); 177 Static void ehci_device_bulk_close(usbd_pipe_handle); 178 Static void ehci_device_bulk_done(usbd_xfer_handle); 179 180 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 181 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 182 Static void ehci_device_intr_abort(usbd_xfer_handle); 183 Static void ehci_device_intr_close(usbd_pipe_handle); 184 Static void ehci_device_intr_done(usbd_xfer_handle); 185 186 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 187 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 188 Static void ehci_device_isoc_abort(usbd_xfer_handle); 189 Static void ehci_device_isoc_close(usbd_pipe_handle); 190 Static void ehci_device_isoc_done(usbd_xfer_handle); 191 192 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 193 Static void ehci_noop(usbd_pipe_handle pipe); 194 195 Static void ehci_disown(ehci_softc_t *, int, int); 196 197 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 198 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 199 200 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 201 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 202 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 203 ehci_softc_t *, int, int, usbd_xfer_handle, 204 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 205 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 206 ehci_soft_qtd_t *); 207 208 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 209 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 210 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 211 struct ehci_xfer *exfer); 212 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 213 usbd_status status); 214 215 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 216 217 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 218 int ival); 219 220 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 221 ehci_soft_qh_t *); 222 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 223 ehci_soft_qh_t *); 224 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 225 Static void ehci_sync_hc(ehci_softc_t *); 226 227 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 228 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 229 230 #ifdef EHCI_DEBUG 231 Static void ehci_dump_regs(ehci_softc_t *); 232 void ehci_dump(void); 233 Static ehci_softc_t *theehci; 234 Static void ehci_dump_link(ehci_link_t, int); 235 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 236 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 237 Static void ehci_dump_qtd(ehci_qtd_t *); 238 Static void ehci_dump_sqh(ehci_soft_qh_t *); 239 #if notyet 240 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 241 Static void ehci_dump_itd(struct ehci_soft_itd *); 242 #endif 243 #ifdef DIAGNOSTIC 244 Static void ehci_dump_exfer(struct ehci_xfer *); 245 #endif 246 #endif 247 248 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 249 250 #define EHCI_INTR_ENDPT 1 251 252 #define ehci_add_intr_list(sc, ex) \ 253 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 254 #define ehci_del_intr_list(sc, ex) \ 255 do { \ 256 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 257 (ex)->inext.tqe_prev = NULL; \ 258 } while (0) 259 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 260 261 Static const struct usbd_bus_methods ehci_bus_methods = { 262 .open_pipe = ehci_open, 263 .soft_intr = ehci_softintr, 264 .do_poll = ehci_poll, 265 .allocm = ehci_allocm, 266 .freem = ehci_freem, 267 .allocx = ehci_allocx, 268 .freex = ehci_freex, 269 .get_lock = ehci_get_lock, 270 .new_device = NULL, 271 }; 272 273 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 274 .transfer = ehci_root_ctrl_transfer, 275 .start = ehci_root_ctrl_start, 276 .abort = ehci_root_ctrl_abort, 277 .close = ehci_root_ctrl_close, 278 .cleartoggle = ehci_noop, 279 .done = ehci_root_ctrl_done, 280 }; 281 282 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 283 .transfer = ehci_root_intr_transfer, 284 .start = ehci_root_intr_start, 285 .abort = ehci_root_intr_abort, 286 .close = ehci_root_intr_close, 287 .cleartoggle = ehci_noop, 288 .done = ehci_root_intr_done, 289 }; 290 291 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 292 .transfer = ehci_device_ctrl_transfer, 293 .start = ehci_device_ctrl_start, 294 .abort = ehci_device_ctrl_abort, 295 .close = ehci_device_ctrl_close, 296 .cleartoggle = ehci_noop, 297 .done = ehci_device_ctrl_done, 298 }; 299 300 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 301 .transfer = ehci_device_intr_transfer, 302 .start = ehci_device_intr_start, 303 .abort = ehci_device_intr_abort, 304 .close = ehci_device_intr_close, 305 .cleartoggle = ehci_device_clear_toggle, 306 .done = ehci_device_intr_done, 307 }; 308 309 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 310 .transfer = ehci_device_bulk_transfer, 311 .start = ehci_device_bulk_start, 312 .abort = ehci_device_bulk_abort, 313 .close = ehci_device_bulk_close, 314 .cleartoggle = ehci_device_clear_toggle, 315 .done = ehci_device_bulk_done, 316 }; 317 318 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 319 .transfer = ehci_device_isoc_transfer, 320 .start = ehci_device_isoc_start, 321 .abort = ehci_device_isoc_abort, 322 .close = ehci_device_isoc_close, 323 .cleartoggle = ehci_noop, 324 .done = ehci_device_isoc_done, 325 }; 326 327 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 328 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 329 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 330 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 331 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 332 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 333 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 334 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 335 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 336 }; 337 338 usbd_status 339 ehci_init(ehci_softc_t *sc) 340 { 341 u_int32_t vers, sparams, cparams, hcr; 342 u_int i; 343 usbd_status err; 344 ehci_soft_qh_t *sqh; 345 u_int ncomp; 346 347 DPRINTF(("ehci_init: start\n")); 348 #ifdef EHCI_DEBUG 349 theehci = sc; 350 #endif 351 352 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 353 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 354 cv_init(&sc->sc_softwake_cv, "ehciab"); 355 cv_init(&sc->sc_doorbell, "ehcidi"); 356 357 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 358 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 359 360 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 361 ehci_doorbell, sc); 362 KASSERT(sc->sc_doorbell_si != NULL); 363 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 364 ehci_pcd, sc); 365 KASSERT(sc->sc_pcd_si != NULL); 366 367 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 368 369 vers = EREAD2(sc, EHCI_HCIVERSION); 370 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 371 vers >> 8, vers & 0xff); 372 373 sparams = EREAD4(sc, EHCI_HCSPARAMS); 374 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 375 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 376 ncomp = EHCI_HCS_N_CC(sparams); 377 if (ncomp != sc->sc_ncomp) { 378 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 379 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 380 #if NOHCI == 0 || NUHCI == 0 381 aprint_error("%s: ohci or uhci probably not configured\n", 382 device_xname(sc->sc_dev)); 383 #endif 384 if (ncomp < sc->sc_ncomp) 385 sc->sc_ncomp = ncomp; 386 } 387 if (sc->sc_ncomp > 0) { 388 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 389 aprint_normal("%s: companion controller%s, %d port%s each:", 390 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 391 EHCI_HCS_N_PCC(sparams), 392 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 393 for (i = 0; i < sc->sc_ncomp; i++) 394 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 395 aprint_normal("\n"); 396 } 397 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 398 cparams = EREAD4(sc, EHCI_HCCPARAMS); 399 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 400 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 401 402 if (EHCI_HCC_64BIT(cparams)) { 403 /* MUST clear segment register if 64 bit capable. */ 404 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 405 } 406 407 sc->sc_bus.usbrev = USBREV_2_0; 408 409 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 410 USB_MEM_RESERVE); 411 412 /* Reset the controller */ 413 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 414 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 415 usb_delay_ms(&sc->sc_bus, 1); 416 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 417 for (i = 0; i < 100; i++) { 418 usb_delay_ms(&sc->sc_bus, 1); 419 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 420 if (!hcr) 421 break; 422 } 423 if (hcr) { 424 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 425 return (USBD_IOERROR); 426 } 427 if (sc->sc_vendor_init) 428 sc->sc_vendor_init(sc); 429 430 /* 431 * If we are doing embedded transaction translation function, force 432 * the controller to host mode. 433 */ 434 if (sc->sc_flags & EHCIF_ETTF) { 435 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 436 usbmode &= ~EHCI_USBMODE_CM; 437 usbmode |= EHCI_USBMODE_CM_HOST; 438 EWRITE4(sc, EHCI_USBMODE, usbmode); 439 } 440 441 /* XXX need proper intr scheduling */ 442 sc->sc_rand = 96; 443 444 /* frame list size at default, read back what we got and use that */ 445 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 446 case 0: sc->sc_flsize = 1024; break; 447 case 1: sc->sc_flsize = 512; break; 448 case 2: sc->sc_flsize = 256; break; 449 case 3: return (USBD_IOERROR); 450 } 451 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 452 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 453 if (err) 454 return (err); 455 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 456 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 457 458 for (i = 0; i < sc->sc_flsize; i++) { 459 sc->sc_flist[i] = EHCI_NULL; 460 } 461 462 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 463 464 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 465 KM_SLEEP); 466 if (sc->sc_softitds == NULL) 467 return ENOMEM; 468 LIST_INIT(&sc->sc_freeitds); 469 TAILQ_INIT(&sc->sc_intrhead); 470 471 /* Set up the bus struct. */ 472 sc->sc_bus.methods = &ehci_bus_methods; 473 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 474 475 sc->sc_eintrs = EHCI_NORMAL_INTRS; 476 477 /* 478 * Allocate the interrupt dummy QHs. These are arranged to give poll 479 * intervals that are powers of 2 times 1ms. 480 */ 481 for (i = 0; i < EHCI_INTRQHS; i++) { 482 sqh = ehci_alloc_sqh(sc); 483 if (sqh == NULL) { 484 err = USBD_NOMEM; 485 goto bad1; 486 } 487 sc->sc_islots[i].sqh = sqh; 488 } 489 for (i = 0; i < EHCI_INTRQHS; i++) { 490 sqh = sc->sc_islots[i].sqh; 491 if (i == 0) { 492 /* The last (1ms) QH terminates. */ 493 sqh->qh.qh_link = EHCI_NULL; 494 sqh->next = NULL; 495 } else { 496 /* Otherwise the next QH has half the poll interval */ 497 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 498 sqh->qh.qh_link = htole32(sqh->next->physaddr | 499 EHCI_LINK_QH); 500 } 501 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 502 sqh->qh.qh_curqtd = EHCI_NULL; 503 sqh->next = NULL; 504 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 505 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 506 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 507 sqh->sqtd = NULL; 508 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 509 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 510 } 511 /* Point the frame list at the last level (128ms). */ 512 for (i = 0; i < sc->sc_flsize; i++) { 513 int j; 514 515 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 516 revbits[i & (EHCI_MAX_POLLRATE-1)]; 517 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 518 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 519 i)].sqh->physaddr); 520 } 521 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 522 BUS_DMASYNC_PREWRITE); 523 524 /* Allocate dummy QH that starts the async list. */ 525 sqh = ehci_alloc_sqh(sc); 526 if (sqh == NULL) { 527 err = USBD_NOMEM; 528 goto bad1; 529 } 530 /* Fill the QH */ 531 sqh->qh.qh_endp = 532 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 533 sqh->qh.qh_link = 534 htole32(sqh->physaddr | EHCI_LINK_QH); 535 sqh->qh.qh_curqtd = EHCI_NULL; 536 sqh->next = NULL; 537 /* Fill the overlay qTD */ 538 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 539 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 540 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 541 sqh->sqtd = NULL; 542 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 543 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 544 #ifdef EHCI_DEBUG 545 if (ehcidebug) { 546 ehci_dump_sqh(sqh); 547 } 548 #endif 549 550 /* Point to async list */ 551 sc->sc_async_head = sqh; 552 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 553 554 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 555 556 /* Turn on controller */ 557 EOWRITE4(sc, EHCI_USBCMD, 558 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 559 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 560 EHCI_CMD_ASE | 561 EHCI_CMD_PSE | 562 EHCI_CMD_RS); 563 564 /* Take over port ownership */ 565 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 566 567 for (i = 0; i < 100; i++) { 568 usb_delay_ms(&sc->sc_bus, 1); 569 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 570 if (!hcr) 571 break; 572 } 573 if (hcr) { 574 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 575 return (USBD_IOERROR); 576 } 577 578 /* Enable interrupts */ 579 DPRINTFN(1,("ehci_init: enabling\n")); 580 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 581 582 return (USBD_NORMAL_COMPLETION); 583 584 #if 0 585 bad2: 586 ehci_free_sqh(sc, sc->sc_async_head); 587 #endif 588 bad1: 589 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 590 return (err); 591 } 592 593 int 594 ehci_intr(void *v) 595 { 596 ehci_softc_t *sc = v; 597 int ret = 0; 598 599 if (sc == NULL) 600 return 0; 601 602 mutex_spin_enter(&sc->sc_intr_lock); 603 604 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 605 goto done; 606 607 /* If we get an interrupt while polling, then just ignore it. */ 608 if (sc->sc_bus.use_polling) { 609 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 610 611 if (intrs) 612 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 613 #ifdef DIAGNOSTIC 614 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 615 #endif 616 goto done; 617 } 618 619 ret = ehci_intr1(sc); 620 621 done: 622 mutex_spin_exit(&sc->sc_intr_lock); 623 return ret; 624 } 625 626 Static int 627 ehci_intr1(ehci_softc_t *sc) 628 { 629 u_int32_t intrs, eintrs; 630 631 DPRINTFN(20,("ehci_intr1: enter\n")); 632 633 /* In case the interrupt occurs before initialization has completed. */ 634 if (sc == NULL) { 635 #ifdef DIAGNOSTIC 636 printf("ehci_intr1: sc == NULL\n"); 637 #endif 638 return (0); 639 } 640 641 KASSERT(mutex_owned(&sc->sc_intr_lock)); 642 643 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 644 if (!intrs) 645 return (0); 646 647 eintrs = intrs & sc->sc_eintrs; 648 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 649 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 650 (u_int)eintrs)); 651 if (!eintrs) 652 return (0); 653 654 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 655 sc->sc_bus.no_intrs++; 656 if (eintrs & EHCI_STS_IAA) { 657 DPRINTF(("ehci_intr1: door bell\n")); 658 kpreempt_disable(); 659 KASSERT(sc->sc_doorbell_si != NULL); 660 softint_schedule(sc->sc_doorbell_si); 661 kpreempt_enable(); 662 eintrs &= ~EHCI_STS_IAA; 663 } 664 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 665 DPRINTFN(5,("ehci_intr1: %s %s\n", 666 eintrs & EHCI_STS_INT ? "INT" : "", 667 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 668 usb_schedsoftintr(&sc->sc_bus); 669 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 670 } 671 if (eintrs & EHCI_STS_HSE) { 672 printf("%s: unrecoverable error, controller halted\n", 673 device_xname(sc->sc_dev)); 674 /* XXX what else */ 675 } 676 if (eintrs & EHCI_STS_PCD) { 677 kpreempt_disable(); 678 KASSERT(sc->sc_pcd_si != NULL); 679 softint_schedule(sc->sc_pcd_si); 680 kpreempt_enable(); 681 eintrs &= ~EHCI_STS_PCD; 682 } 683 684 if (eintrs != 0) { 685 /* Block unprocessed interrupts. */ 686 sc->sc_eintrs &= ~eintrs; 687 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 688 printf("%s: blocking intrs 0x%x\n", 689 device_xname(sc->sc_dev), eintrs); 690 } 691 692 return (1); 693 } 694 695 Static void 696 ehci_doorbell(void *addr) 697 { 698 ehci_softc_t *sc = addr; 699 700 mutex_enter(&sc->sc_lock); 701 cv_broadcast(&sc->sc_doorbell); 702 mutex_exit(&sc->sc_lock); 703 } 704 705 Static void 706 ehci_pcd(void *addr) 707 { 708 ehci_softc_t *sc = addr; 709 usbd_xfer_handle xfer; 710 u_char *p; 711 int i, m; 712 713 mutex_enter(&sc->sc_lock); 714 xfer = sc->sc_intrxfer; 715 716 if (xfer == NULL) { 717 /* Just ignore the change. */ 718 goto done; 719 } 720 721 p = KERNADDR(&xfer->dmabuf, 0); 722 m = min(sc->sc_noport, xfer->length * 8 - 1); 723 memset(p, 0, xfer->length); 724 for (i = 1; i <= m; i++) { 725 /* Pick out CHANGE bits from the status reg. */ 726 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 727 p[i/8] |= 1 << (i%8); 728 } 729 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 730 xfer->actlen = xfer->length; 731 xfer->status = USBD_NORMAL_COMPLETION; 732 733 usb_transfer_complete(xfer); 734 735 done: 736 mutex_exit(&sc->sc_lock); 737 } 738 739 Static void 740 ehci_softintr(void *v) 741 { 742 struct usbd_bus *bus = v; 743 ehci_softc_t *sc = bus->hci_private; 744 struct ehci_xfer *ex, *nextex; 745 746 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 747 748 DPRINTFN(10,("%s: ehci_softintr\n", device_xname(sc->sc_dev))); 749 750 /* 751 * The only explanation I can think of for why EHCI is as brain dead 752 * as UHCI interrupt-wise is that Intel was involved in both. 753 * An interrupt just tells us that something is done, we have no 754 * clue what, so we need to scan through all active transfers. :-( 755 */ 756 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 757 nextex = TAILQ_NEXT(ex, inext); 758 ehci_check_intr(sc, ex); 759 } 760 761 /* Schedule a callout to catch any dropped transactions. */ 762 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 763 !TAILQ_EMPTY(&sc->sc_intrhead)) 764 callout_reset(&sc->sc_tmo_intrlist, 765 hz, ehci_intrlist_timeout, sc); 766 767 if (sc->sc_softwake) { 768 sc->sc_softwake = 0; 769 cv_broadcast(&sc->sc_softwake_cv); 770 } 771 } 772 773 /* Check for an interrupt. */ 774 Static void 775 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 776 { 777 int attr; 778 779 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 780 781 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 782 783 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 784 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 785 ehci_check_itd_intr(sc, ex); 786 else 787 ehci_check_qh_intr(sc, ex); 788 789 return; 790 } 791 792 Static void 793 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 794 { 795 ehci_soft_qtd_t *sqtd, *lsqtd; 796 __uint32_t status; 797 798 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 799 800 if (ex->sqtdstart == NULL) { 801 printf("ehci_check_qh_intr: not valid sqtd\n"); 802 return; 803 } 804 805 lsqtd = ex->sqtdend; 806 #ifdef DIAGNOSTIC 807 if (lsqtd == NULL) { 808 printf("ehci_check_qh_intr: lsqtd==0\n"); 809 return; 810 } 811 #endif 812 /* 813 * If the last TD is still active we need to check whether there 814 * is an error somewhere in the middle, or whether there was a 815 * short packet (SPD and not ACTIVE). 816 */ 817 usb_syncmem(&lsqtd->dma, 818 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 819 sizeof(lsqtd->qtd.qtd_status), 820 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 821 status = le32toh(lsqtd->qtd.qtd_status); 822 usb_syncmem(&lsqtd->dma, 823 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 824 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 825 if (status & EHCI_QTD_ACTIVE) { 826 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 827 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 828 usb_syncmem(&sqtd->dma, 829 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 830 sizeof(sqtd->qtd.qtd_status), 831 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 832 status = le32toh(sqtd->qtd.qtd_status); 833 usb_syncmem(&sqtd->dma, 834 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 835 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 836 /* If there's an active QTD the xfer isn't done. */ 837 if (status & EHCI_QTD_ACTIVE) 838 break; 839 /* Any kind of error makes the xfer done. */ 840 if (status & EHCI_QTD_HALTED) 841 goto done; 842 /* We want short packets, and it is short: it's done */ 843 if (EHCI_QTD_GET_BYTES(status) != 0) 844 goto done; 845 } 846 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 847 ex, ex->sqtdstart)); 848 return; 849 } 850 done: 851 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 852 callout_stop(&ex->xfer.timeout_handle); 853 ehci_idone(ex); 854 } 855 856 Static void 857 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 858 { 859 ehci_soft_itd_t *itd; 860 int i; 861 862 KASSERT(mutex_owned(&sc->sc_lock)); 863 864 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 865 return; 866 867 if (ex->itdstart == NULL) { 868 printf("ehci_check_itd_intr: not valid itd\n"); 869 return; 870 } 871 872 itd = ex->itdend; 873 #ifdef DIAGNOSTIC 874 if (itd == NULL) { 875 printf("ehci_check_itd_intr: itdend == 0\n"); 876 return; 877 } 878 #endif 879 880 /* 881 * check no active transfers in last itd, meaning we're finished 882 */ 883 884 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 885 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 886 BUS_DMASYNC_POSTREAD); 887 888 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 889 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 890 break; 891 } 892 893 if (i == EHCI_ITD_NUFRAMES) { 894 goto done; /* All 8 descriptors inactive, it's done */ 895 } 896 897 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 898 ex->itdstart)); 899 return; 900 done: 901 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 902 callout_stop(&ex->xfer.timeout_handle); 903 ehci_idone(ex); 904 } 905 906 Static void 907 ehci_idone(struct ehci_xfer *ex) 908 { 909 usbd_xfer_handle xfer = &ex->xfer; 910 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 911 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 912 ehci_soft_qtd_t *sqtd, *lsqtd; 913 u_int32_t status = 0, nstatus = 0; 914 int actlen; 915 916 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 917 918 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 919 920 #ifdef DIAGNOSTIC 921 { 922 if (ex->isdone) { 923 #ifdef EHCI_DEBUG 924 printf("ehci_idone: ex is done!\n "); 925 ehci_dump_exfer(ex); 926 #else 927 printf("ehci_idone: ex=%p is done!\n", ex); 928 #endif 929 return; 930 } 931 ex->isdone = 1; 932 } 933 #endif 934 if (xfer->status == USBD_CANCELLED || 935 xfer->status == USBD_TIMEOUT) { 936 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 937 return; 938 } 939 940 #ifdef EHCI_DEBUG 941 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 942 if (ehcidebug > 10) 943 ehci_dump_sqtds(ex->sqtdstart); 944 #endif 945 946 /* The transfer is done, compute actual length and status. */ 947 948 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 949 == UE_ISOCHRONOUS) { 950 /* Isoc transfer */ 951 struct ehci_soft_itd *itd; 952 int i, nframes, len, uframes; 953 954 nframes = 0; 955 actlen = 0; 956 957 i = xfer->pipe->endpoint->edesc->bInterval; 958 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 959 960 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 961 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 962 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 963 BUS_DMASYNC_POSTREAD); 964 965 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 966 /* XXX - driver didn't fill in the frame full 967 * of uframes. This leads to scheduling 968 * inefficiencies, but working around 969 * this doubles complexity of tracking 970 * an xfer. 971 */ 972 if (nframes >= xfer->nframes) 973 break; 974 975 status = le32toh(itd->itd.itd_ctl[i]); 976 len = EHCI_ITD_GET_LEN(status); 977 if (EHCI_ITD_GET_STATUS(status) != 0) 978 len = 0; /*No valid data on error*/ 979 980 xfer->frlengths[nframes++] = len; 981 actlen += len; 982 } 983 984 if (nframes >= xfer->nframes) 985 break; 986 } 987 988 xfer->actlen = actlen; 989 xfer->status = USBD_NORMAL_COMPLETION; 990 goto end; 991 } 992 993 /* Continue processing xfers using queue heads */ 994 995 lsqtd = ex->sqtdend; 996 actlen = 0; 997 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 998 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 999 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1000 nstatus = le32toh(sqtd->qtd.qtd_status); 1001 if (nstatus & EHCI_QTD_ACTIVE) 1002 break; 1003 1004 status = nstatus; 1005 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1006 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1007 } 1008 1009 1010 /* 1011 * If there are left over TDs we need to update the toggle. 1012 * The default pipe doesn't need it since control transfers 1013 * start the toggle at 0 every time. 1014 * For a short transfer we need to update the toggle for the missing 1015 * packets within the qTD. 1016 */ 1017 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1018 xfer->pipe->device->default_pipe != xfer->pipe) { 1019 DPRINTFN(2, ("ehci_idone: need toggle update " 1020 "status=%08x nstatus=%08x\n", status, nstatus)); 1021 #if 0 1022 ehci_dump_sqh(epipe->sqh); 1023 ehci_dump_sqtds(ex->sqtdstart); 1024 #endif 1025 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1026 } 1027 1028 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 1029 xfer->length, actlen, status)); 1030 xfer->actlen = actlen; 1031 if (status & EHCI_QTD_HALTED) { 1032 #ifdef EHCI_DEBUG 1033 char sbuf[128]; 1034 1035 snprintb(sbuf, sizeof(sbuf), 1036 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 1037 (u_int32_t)status); 1038 1039 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 1040 "status 0x%s\n", 1041 xfer->pipe->device->address, 1042 xfer->pipe->endpoint->edesc->bEndpointAddress, 1043 sbuf)); 1044 if (ehcidebug > 2) { 1045 ehci_dump_sqh(epipe->sqh); 1046 ehci_dump_sqtds(ex->sqtdstart); 1047 } 1048 #endif 1049 /* low&full speed has an extra error flag */ 1050 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1051 EHCI_QH_SPEED_HIGH) 1052 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1053 else 1054 status &= EHCI_QTD_STATERRS; 1055 if (status == 0) /* no other errors means a stall */ { 1056 xfer->status = USBD_STALLED; 1057 } else { 1058 xfer->status = USBD_IOERROR; /* more info XXX */ 1059 } 1060 /* XXX need to reset TT on missed microframe */ 1061 if (status & EHCI_QTD_MISSEDMICRO) { 1062 printf("%s: missed microframe, TT reset not " 1063 "implemented, hub might be inoperational\n", 1064 device_xname(sc->sc_dev)); 1065 } 1066 } else { 1067 xfer->status = USBD_NORMAL_COMPLETION; 1068 } 1069 1070 end: 1071 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1072 * during this call, before methods->done is called: dma sync required 1073 * beforehand? */ 1074 usb_transfer_complete(xfer); 1075 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1076 } 1077 1078 /* 1079 * Wait here until controller claims to have an interrupt. 1080 * Then call ehci_intr and return. Use timeout to avoid waiting 1081 * too long. 1082 */ 1083 Static void 1084 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1085 { 1086 int timo; 1087 u_int32_t intrs; 1088 1089 xfer->status = USBD_IN_PROGRESS; 1090 for (timo = xfer->timeout; timo >= 0; timo--) { 1091 usb_delay_ms(&sc->sc_bus, 1); 1092 if (sc->sc_dying) 1093 break; 1094 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1095 sc->sc_eintrs; 1096 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1097 #ifdef EHCI_DEBUG 1098 if (ehcidebug > 15) 1099 ehci_dump_regs(sc); 1100 #endif 1101 if (intrs) { 1102 mutex_spin_enter(&sc->sc_intr_lock); 1103 ehci_intr1(sc); 1104 mutex_spin_exit(&sc->sc_intr_lock); 1105 if (xfer->status != USBD_IN_PROGRESS) 1106 return; 1107 } 1108 } 1109 1110 /* Timeout */ 1111 DPRINTF(("ehci_waitintr: timeout\n")); 1112 xfer->status = USBD_TIMEOUT; 1113 mutex_enter(&sc->sc_lock); 1114 usb_transfer_complete(xfer); 1115 mutex_exit(&sc->sc_lock); 1116 /* XXX should free TD */ 1117 } 1118 1119 Static void 1120 ehci_poll(struct usbd_bus *bus) 1121 { 1122 ehci_softc_t *sc = bus->hci_private; 1123 #ifdef EHCI_DEBUG 1124 static int last; 1125 int new; 1126 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1127 if (new != last) { 1128 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1129 last = new; 1130 } 1131 #endif 1132 1133 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1134 mutex_spin_enter(&sc->sc_intr_lock); 1135 ehci_intr1(sc); 1136 mutex_spin_exit(&sc->sc_intr_lock); 1137 } 1138 } 1139 1140 void 1141 ehci_childdet(device_t self, device_t child) 1142 { 1143 struct ehci_softc *sc = device_private(self); 1144 1145 KASSERT(sc->sc_child == child); 1146 sc->sc_child = NULL; 1147 } 1148 1149 int 1150 ehci_detach(struct ehci_softc *sc, int flags) 1151 { 1152 int rv = 0; 1153 1154 if (sc->sc_child != NULL) 1155 rv = config_detach(sc->sc_child, flags); 1156 1157 if (rv != 0) 1158 return (rv); 1159 1160 callout_halt(&sc->sc_tmo_intrlist, NULL); 1161 callout_destroy(&sc->sc_tmo_intrlist); 1162 1163 /* XXX free other data structures XXX */ 1164 if (sc->sc_softitds) 1165 kmem_free(sc->sc_softitds, 1166 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1167 cv_destroy(&sc->sc_doorbell); 1168 cv_destroy(&sc->sc_softwake_cv); 1169 1170 #if 0 1171 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1172 1173 softint_disestablish(sc->sc_doorbell_si); 1174 softint_disestablish(sc->sc_pcd_si); 1175 1176 mutex_destroy(&sc->sc_lock); 1177 mutex_destroy(&sc->sc_intr_lock); 1178 #endif 1179 1180 pool_cache_destroy(sc->sc_xferpool); 1181 1182 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1183 1184 return (rv); 1185 } 1186 1187 1188 int 1189 ehci_activate(device_t self, enum devact act) 1190 { 1191 struct ehci_softc *sc = device_private(self); 1192 1193 switch (act) { 1194 case DVACT_DEACTIVATE: 1195 sc->sc_dying = 1; 1196 return 0; 1197 default: 1198 return EOPNOTSUPP; 1199 } 1200 } 1201 1202 /* 1203 * Handle suspend/resume. 1204 * 1205 * We need to switch to polling mode here, because this routine is 1206 * called from an interrupt context. This is all right since we 1207 * are almost suspended anyway. 1208 * 1209 * Note that this power handler isn't to be registered directly; the 1210 * bus glue needs to call out to it. 1211 */ 1212 bool 1213 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1214 { 1215 ehci_softc_t *sc = device_private(dv); 1216 int i; 1217 uint32_t cmd, hcr; 1218 1219 mutex_spin_enter(&sc->sc_intr_lock); 1220 sc->sc_bus.use_polling++; 1221 mutex_spin_exit(&sc->sc_intr_lock); 1222 1223 for (i = 1; i <= sc->sc_noport; i++) { 1224 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1225 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1226 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1227 } 1228 1229 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1230 1231 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1232 EOWRITE4(sc, EHCI_USBCMD, cmd); 1233 1234 for (i = 0; i < 100; i++) { 1235 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1236 if (hcr == 0) 1237 break; 1238 1239 usb_delay_ms(&sc->sc_bus, 1); 1240 } 1241 if (hcr != 0) 1242 printf("%s: reset timeout\n", device_xname(dv)); 1243 1244 cmd &= ~EHCI_CMD_RS; 1245 EOWRITE4(sc, EHCI_USBCMD, cmd); 1246 1247 for (i = 0; i < 100; i++) { 1248 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1249 if (hcr == EHCI_STS_HCH) 1250 break; 1251 1252 usb_delay_ms(&sc->sc_bus, 1); 1253 } 1254 if (hcr != EHCI_STS_HCH) 1255 printf("%s: config timeout\n", device_xname(dv)); 1256 1257 mutex_spin_enter(&sc->sc_intr_lock); 1258 sc->sc_bus.use_polling--; 1259 mutex_spin_exit(&sc->sc_intr_lock); 1260 1261 return true; 1262 } 1263 1264 bool 1265 ehci_resume(device_t dv, const pmf_qual_t *qual) 1266 { 1267 ehci_softc_t *sc = device_private(dv); 1268 int i; 1269 uint32_t cmd, hcr; 1270 1271 /* restore things in case the bios sucks */ 1272 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1273 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1274 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1275 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1276 1277 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1278 1279 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1280 1281 hcr = 0; 1282 for (i = 1; i <= sc->sc_noport; i++) { 1283 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1284 if ((cmd & EHCI_PS_PO) == 0 && 1285 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1286 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1287 hcr = 1; 1288 } 1289 } 1290 1291 if (hcr) { 1292 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1293 1294 for (i = 1; i <= sc->sc_noport; i++) { 1295 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1296 if ((cmd & EHCI_PS_PO) == 0 && 1297 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1298 EOWRITE4(sc, EHCI_PORTSC(i), 1299 cmd & ~EHCI_PS_FPR); 1300 } 1301 } 1302 1303 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1304 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1305 1306 for (i = 0; i < 100; i++) { 1307 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1308 if (hcr != EHCI_STS_HCH) 1309 break; 1310 1311 usb_delay_ms(&sc->sc_bus, 1); 1312 } 1313 if (hcr == EHCI_STS_HCH) 1314 printf("%s: config timeout\n", device_xname(dv)); 1315 1316 return true; 1317 } 1318 1319 /* 1320 * Shut down the controller when the system is going down. 1321 */ 1322 bool 1323 ehci_shutdown(device_t self, int flags) 1324 { 1325 ehci_softc_t *sc = device_private(self); 1326 1327 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1328 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1329 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1330 return true; 1331 } 1332 1333 Static usbd_status 1334 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1335 { 1336 struct ehci_softc *sc = bus->hci_private; 1337 usbd_status err; 1338 1339 err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, USBMALLOC_MULTISEG); 1340 #ifdef EHCI_DEBUG 1341 if (err) 1342 printf("ehci_allocm: usb_allocmem_flags()= %s (%d)\n", 1343 usbd_errstr(err), err); 1344 #endif 1345 if (err == USBD_NOMEM) 1346 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1347 #ifdef EHCI_DEBUG 1348 if (err) 1349 printf("ehci_allocm: usb_reserve_allocm()= %s (%d)\n", 1350 usbd_errstr(err), err); 1351 #endif 1352 return (err); 1353 } 1354 1355 Static void 1356 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1357 { 1358 struct ehci_softc *sc = bus->hci_private; 1359 1360 if (dma->block->flags & USB_DMA_RESERVE) { 1361 usb_reserve_freem(&sc->sc_dma_reserve, 1362 dma); 1363 return; 1364 } 1365 usb_freemem(&sc->sc_bus, dma); 1366 } 1367 1368 Static usbd_xfer_handle 1369 ehci_allocx(struct usbd_bus *bus) 1370 { 1371 struct ehci_softc *sc = bus->hci_private; 1372 usbd_xfer_handle xfer; 1373 1374 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1375 if (xfer != NULL) { 1376 memset(xfer, 0, sizeof(struct ehci_xfer)); 1377 #ifdef DIAGNOSTIC 1378 EXFER(xfer)->isdone = 1; 1379 xfer->busy_free = XFER_BUSY; 1380 #endif 1381 } 1382 return (xfer); 1383 } 1384 1385 Static void 1386 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1387 { 1388 struct ehci_softc *sc = bus->hci_private; 1389 1390 #ifdef DIAGNOSTIC 1391 if (xfer->busy_free != XFER_BUSY) { 1392 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1393 xfer->busy_free); 1394 } 1395 xfer->busy_free = XFER_FREE; 1396 if (!EXFER(xfer)->isdone) { 1397 printf("ehci_freex: !isdone\n"); 1398 } 1399 #endif 1400 pool_cache_put(sc->sc_xferpool, xfer); 1401 } 1402 1403 Static void 1404 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1405 { 1406 struct ehci_softc *sc = bus->hci_private; 1407 1408 *lock = &sc->sc_lock; 1409 } 1410 1411 Static void 1412 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1413 { 1414 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1415 1416 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1417 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1418 #ifdef EHCI_DEBUG 1419 if (ehcidebug) 1420 usbd_dump_pipe(pipe); 1421 #endif 1422 epipe->nexttoggle = 0; 1423 } 1424 1425 Static void 1426 ehci_noop(usbd_pipe_handle pipe) 1427 { 1428 } 1429 1430 #ifdef EHCI_DEBUG 1431 Static void 1432 ehci_dump_regs(ehci_softc_t *sc) 1433 { 1434 int i; 1435 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1436 EOREAD4(sc, EHCI_USBCMD), 1437 EOREAD4(sc, EHCI_USBSTS), 1438 EOREAD4(sc, EHCI_USBINTR)); 1439 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1440 EOREAD4(sc, EHCI_FRINDEX), 1441 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1442 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1443 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1444 for (i = 1; i <= sc->sc_noport; i++) 1445 printf("port %d status=0x%08x\n", i, 1446 EOREAD4(sc, EHCI_PORTSC(i))); 1447 } 1448 1449 /* 1450 * Unused function - this is meant to be called from a kernel 1451 * debugger. 1452 */ 1453 void 1454 ehci_dump(void) 1455 { 1456 ehci_dump_regs(theehci); 1457 } 1458 1459 Static void 1460 ehci_dump_link(ehci_link_t link, int type) 1461 { 1462 link = le32toh(link); 1463 printf("0x%08x", link); 1464 if (link & EHCI_LINK_TERMINATE) 1465 printf("<T>"); 1466 else { 1467 printf("<"); 1468 if (type) { 1469 switch (EHCI_LINK_TYPE(link)) { 1470 case EHCI_LINK_ITD: printf("ITD"); break; 1471 case EHCI_LINK_QH: printf("QH"); break; 1472 case EHCI_LINK_SITD: printf("SITD"); break; 1473 case EHCI_LINK_FSTN: printf("FSTN"); break; 1474 } 1475 } 1476 printf(">"); 1477 } 1478 } 1479 1480 Static void 1481 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1482 { 1483 int i; 1484 u_int32_t stop; 1485 1486 stop = 0; 1487 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1488 ehci_dump_sqtd(sqtd); 1489 usb_syncmem(&sqtd->dma, 1490 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1491 sizeof(sqtd->qtd), 1492 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1493 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1494 usb_syncmem(&sqtd->dma, 1495 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1496 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1497 } 1498 if (sqtd) 1499 printf("dump aborted, too many TDs\n"); 1500 } 1501 1502 Static void 1503 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1504 { 1505 usb_syncmem(&sqtd->dma, sqtd->offs, 1506 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1507 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1508 ehci_dump_qtd(&sqtd->qtd); 1509 usb_syncmem(&sqtd->dma, sqtd->offs, 1510 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1511 } 1512 1513 Static void 1514 ehci_dump_qtd(ehci_qtd_t *qtd) 1515 { 1516 u_int32_t s; 1517 char sbuf[128]; 1518 1519 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1520 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1521 printf("\n"); 1522 s = le32toh(qtd->qtd_status); 1523 snprintb(sbuf, sizeof(sbuf), 1524 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1525 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1526 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1527 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1528 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1529 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1530 EHCI_QTD_GET_PID(s), sbuf); 1531 for (s = 0; s < 5; s++) 1532 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1533 } 1534 1535 Static void 1536 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1537 { 1538 ehci_qh_t *qh = &sqh->qh; 1539 u_int32_t endp, endphub; 1540 1541 usb_syncmem(&sqh->dma, sqh->offs, 1542 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1543 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1544 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1545 endp = le32toh(qh->qh_endp); 1546 printf(" endp=0x%08x\n", endp); 1547 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1548 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1549 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1550 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1551 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1552 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1553 EHCI_QH_GET_NRL(endp)); 1554 endphub = le32toh(qh->qh_endphub); 1555 printf(" endphub=0x%08x\n", endphub); 1556 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1557 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1558 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1559 EHCI_QH_GET_MULT(endphub)); 1560 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1561 printf("Overlay qTD:\n"); 1562 ehci_dump_qtd(&qh->qh_qtd); 1563 usb_syncmem(&sqh->dma, sqh->offs, 1564 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1565 } 1566 1567 #if notyet 1568 Static void 1569 ehci_dump_itd(struct ehci_soft_itd *itd) 1570 { 1571 ehci_isoc_trans_t t; 1572 ehci_isoc_bufr_ptr_t b, b2, b3; 1573 int i; 1574 1575 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1576 1577 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1578 t = le32toh(itd->itd.itd_ctl[i]); 1579 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1580 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1581 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1582 EHCI_ITD_GET_OFFS(t)); 1583 } 1584 printf("ITDbufr: "); 1585 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1586 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1587 1588 b = le32toh(itd->itd.itd_bufr[0]); 1589 b2 = le32toh(itd->itd.itd_bufr[1]); 1590 b3 = le32toh(itd->itd.itd_bufr[2]); 1591 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1592 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1593 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1594 } 1595 1596 Static void 1597 ehci_dump_sitd(struct ehci_soft_itd *itd) 1598 { 1599 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1600 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1601 itd->xfer_next, itd->physaddr, itd->slot); 1602 } 1603 #endif 1604 1605 #ifdef DIAGNOSTIC 1606 Static void 1607 ehci_dump_exfer(struct ehci_xfer *ex) 1608 { 1609 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1610 } 1611 #endif 1612 #endif 1613 1614 Static usbd_status 1615 ehci_open(usbd_pipe_handle pipe) 1616 { 1617 usbd_device_handle dev = pipe->device; 1618 ehci_softc_t *sc = dev->bus->hci_private; 1619 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1620 u_int8_t addr = dev->address; 1621 u_int8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1622 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1623 ehci_soft_qh_t *sqh; 1624 usbd_status err; 1625 int ival, speed, naks; 1626 int hshubaddr, hshubport; 1627 1628 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1629 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1630 1631 if (dev->myhsport) { 1632 /* 1633 * When directly attached FS/LS device while doing embedded 1634 * transaction translations and we are the hub, set the hub 1635 * address to 0 (us). 1636 */ 1637 if (!(sc->sc_flags & EHCIF_ETTF) 1638 || (dev->myhsport->parent->address != sc->sc_addr)) { 1639 hshubaddr = dev->myhsport->parent->address; 1640 } else { 1641 hshubaddr = 0; 1642 } 1643 hshubport = dev->myhsport->portno; 1644 } else { 1645 hshubaddr = 0; 1646 hshubport = 0; 1647 } 1648 1649 if (sc->sc_dying) 1650 return (USBD_IOERROR); 1651 1652 /* toggle state needed for bulk endpoints */ 1653 epipe->nexttoggle = pipe->endpoint->datatoggle; 1654 1655 if (addr == sc->sc_addr) { 1656 switch (ed->bEndpointAddress) { 1657 case USB_CONTROL_ENDPOINT: 1658 pipe->methods = &ehci_root_ctrl_methods; 1659 break; 1660 case UE_DIR_IN | EHCI_INTR_ENDPT: 1661 pipe->methods = &ehci_root_intr_methods; 1662 break; 1663 default: 1664 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1665 ed->bEndpointAddress)); 1666 return (USBD_INVAL); 1667 } 1668 return (USBD_NORMAL_COMPLETION); 1669 } 1670 1671 /* XXX All this stuff is only valid for async. */ 1672 switch (dev->speed) { 1673 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1674 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1675 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1676 default: panic("ehci_open: bad device speed %d", dev->speed); 1677 } 1678 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1679 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1680 "isoc endpoint.\n"); 1681 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1682 "attached to a USB2 hub, and transaction translations are " 1683 "not yet supported.\n"); 1684 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1685 "root hub instead.\n"); 1686 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1687 hshubaddr, hshubport)); 1688 return USBD_INVAL; 1689 } 1690 1691 /* 1692 * For interrupt transfer, nak throttling must be disabled, but for 1693 * the other transfer type, nak throttling should be enabled from the 1694 * viewpoint that avoids the memory thrashing. 1695 */ 1696 naks = (xfertype == UE_INTERRUPT) ? 0 1697 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1698 1699 /* Allocate sqh for everything, save isoc xfers */ 1700 if (xfertype != UE_ISOCHRONOUS) { 1701 sqh = ehci_alloc_sqh(sc); 1702 if (sqh == NULL) 1703 return (USBD_NOMEM); 1704 /* qh_link filled when the QH is added */ 1705 sqh->qh.qh_endp = htole32( 1706 EHCI_QH_SET_ADDR(addr) | 1707 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1708 EHCI_QH_SET_EPS(speed) | 1709 EHCI_QH_DTC | 1710 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1711 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1712 EHCI_QH_CTL : 0) | 1713 EHCI_QH_SET_NRL(naks) 1714 ); 1715 sqh->qh.qh_endphub = htole32( 1716 EHCI_QH_SET_MULT(1) | 1717 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1718 ); 1719 if (speed != EHCI_QH_SPEED_HIGH) 1720 sqh->qh.qh_endphub |= htole32( 1721 EHCI_QH_SET_PORT(hshubport) | 1722 EHCI_QH_SET_HUBA(hshubaddr) | 1723 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1724 ); 1725 sqh->qh.qh_curqtd = EHCI_NULL; 1726 /* Fill the overlay qTD */ 1727 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1728 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1729 sqh->qh.qh_qtd.qtd_status = htole32(0); 1730 1731 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1732 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1733 epipe->sqh = sqh; 1734 } else { 1735 sqh = NULL; 1736 } /*xfertype == UE_ISOC*/ 1737 1738 switch (xfertype) { 1739 case UE_CONTROL: 1740 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1741 0, &epipe->u.ctl.reqdma); 1742 #ifdef EHCI_DEBUG 1743 if (err) 1744 printf("ehci_open: usb_allocmem()=%d\n", err); 1745 #endif 1746 if (err) 1747 goto bad; 1748 pipe->methods = &ehci_device_ctrl_methods; 1749 mutex_enter(&sc->sc_lock); 1750 ehci_add_qh(sc, sqh, sc->sc_async_head); 1751 mutex_exit(&sc->sc_lock); 1752 break; 1753 case UE_BULK: 1754 pipe->methods = &ehci_device_bulk_methods; 1755 mutex_enter(&sc->sc_lock); 1756 ehci_add_qh(sc, sqh, sc->sc_async_head); 1757 mutex_exit(&sc->sc_lock); 1758 break; 1759 case UE_INTERRUPT: 1760 pipe->methods = &ehci_device_intr_methods; 1761 ival = pipe->interval; 1762 if (ival == USBD_DEFAULT_INTERVAL) { 1763 if (speed == EHCI_QH_SPEED_HIGH) { 1764 if (ed->bInterval > 16) { 1765 /* 1766 * illegal with high-speed, but there 1767 * were documentation bugs in the spec, 1768 * so be generous 1769 */ 1770 ival = 256; 1771 } else 1772 ival = (1 << (ed->bInterval - 1)) / 8; 1773 } else 1774 ival = ed->bInterval; 1775 } 1776 err = ehci_device_setintr(sc, sqh, ival); 1777 if (err) 1778 goto bad; 1779 break; 1780 case UE_ISOCHRONOUS: 1781 pipe->methods = &ehci_device_isoc_methods; 1782 if (ed->bInterval == 0 || ed->bInterval > 16) { 1783 printf("ehci: opening pipe with invalid bInterval\n"); 1784 err = USBD_INVAL; 1785 goto bad; 1786 } 1787 if (UGETW(ed->wMaxPacketSize) == 0) { 1788 printf("ehci: zero length endpoint open request\n"); 1789 err = USBD_INVAL; 1790 goto bad; 1791 } 1792 epipe->u.isoc.next_frame = 0; 1793 epipe->u.isoc.cur_xfers = 0; 1794 break; 1795 default: 1796 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1797 err = USBD_INVAL; 1798 goto bad; 1799 } 1800 return (USBD_NORMAL_COMPLETION); 1801 1802 bad: 1803 if (sqh != NULL) 1804 ehci_free_sqh(sc, sqh); 1805 return (err); 1806 } 1807 1808 /* 1809 * Add an ED to the schedule. Called with USB lock held. 1810 */ 1811 Static void 1812 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1813 { 1814 1815 KASSERT(mutex_owned(&sc->sc_lock)); 1816 1817 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1818 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1819 sqh->next = head->next; 1820 sqh->qh.qh_link = head->qh.qh_link; 1821 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1822 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1823 head->next = sqh; 1824 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1825 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1826 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1827 1828 #ifdef EHCI_DEBUG 1829 if (ehcidebug > 5) { 1830 printf("ehci_add_qh:\n"); 1831 ehci_dump_sqh(sqh); 1832 } 1833 #endif 1834 } 1835 1836 /* 1837 * Remove an ED from the schedule. Called with USB lock held. 1838 */ 1839 Static void 1840 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1841 { 1842 ehci_soft_qh_t *p; 1843 1844 KASSERT(mutex_owned(&sc->sc_lock)); 1845 1846 /* XXX */ 1847 for (p = head; p != NULL && p->next != sqh; p = p->next) 1848 ; 1849 if (p == NULL) 1850 panic("ehci_rem_qh: ED not found"); 1851 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1852 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1853 p->next = sqh->next; 1854 p->qh.qh_link = sqh->qh.qh_link; 1855 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1856 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1857 1858 ehci_sync_hc(sc); 1859 } 1860 1861 Static void 1862 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1863 { 1864 int i; 1865 u_int32_t status; 1866 1867 /* Save toggle bit and ping status. */ 1868 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1869 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1870 status = sqh->qh.qh_qtd.qtd_status & 1871 htole32(EHCI_QTD_TOGGLE_MASK | 1872 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1873 /* Set HALTED to make hw leave it alone. */ 1874 sqh->qh.qh_qtd.qtd_status = 1875 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1876 usb_syncmem(&sqh->dma, 1877 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1878 sizeof(sqh->qh.qh_qtd.qtd_status), 1879 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1880 sqh->qh.qh_curqtd = 0; 1881 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1882 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1883 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1884 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1885 sqh->sqtd = sqtd; 1886 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1887 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1888 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1889 sqh->qh.qh_qtd.qtd_status = status; 1890 usb_syncmem(&sqh->dma, 1891 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1892 sizeof(sqh->qh.qh_qtd.qtd_status), 1893 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1894 } 1895 1896 /* 1897 * Ensure that the HC has released all references to the QH. We do this 1898 * by asking for a Async Advance Doorbell interrupt and then we wait for 1899 * the interrupt. 1900 * To make this easier we first obtain exclusive use of the doorbell. 1901 */ 1902 Static void 1903 ehci_sync_hc(ehci_softc_t *sc) 1904 { 1905 int error __diagused; 1906 1907 KASSERT(mutex_owned(&sc->sc_lock)); 1908 1909 if (sc->sc_dying) { 1910 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1911 return; 1912 } 1913 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1914 /* ask for doorbell */ 1915 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1916 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1917 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1918 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 1919 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1920 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1921 #ifdef DIAGNOSTIC 1922 if (error) 1923 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 1924 #endif 1925 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1926 } 1927 1928 Static void 1929 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1930 { 1931 struct ehci_soft_itd *itd, *prev; 1932 1933 prev = NULL; 1934 1935 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1936 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1937 1938 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1939 prev = itd->u.frame_list.prev; 1940 /* Unlink itd from hardware chain, or frame array */ 1941 if (prev == NULL) { /* We're at the table head */ 1942 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1943 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1944 usb_syncmem(&sc->sc_fldma, 1945 sizeof(ehci_link_t) * itd->slot, 1946 sizeof(ehci_link_t), 1947 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1948 1949 if (itd->u.frame_list.next != NULL) 1950 itd->u.frame_list.next->u.frame_list.prev = NULL; 1951 } else { 1952 /* XXX this part is untested... */ 1953 prev->itd.itd_next = itd->itd.itd_next; 1954 usb_syncmem(&itd->dma, 1955 itd->offs + offsetof(ehci_itd_t, itd_next), 1956 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1957 1958 prev->u.frame_list.next = itd->u.frame_list.next; 1959 if (itd->u.frame_list.next != NULL) 1960 itd->u.frame_list.next->u.frame_list.prev = prev; 1961 } 1962 } 1963 1964 prev = NULL; 1965 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1966 if (prev != NULL) 1967 ehci_free_itd(sc, prev); 1968 prev = itd; 1969 } 1970 if (prev) 1971 ehci_free_itd(sc, prev); 1972 exfer->itdstart = NULL; 1973 exfer->itdend = NULL; 1974 } 1975 1976 /***********/ 1977 1978 /* 1979 * Data structures and routines to emulate the root hub. 1980 */ 1981 Static usb_device_descriptor_t ehci_devd = { 1982 USB_DEVICE_DESCRIPTOR_SIZE, 1983 UDESC_DEVICE, /* type */ 1984 {0x00, 0x02}, /* USB version */ 1985 UDCLASS_HUB, /* class */ 1986 UDSUBCLASS_HUB, /* subclass */ 1987 UDPROTO_HSHUBSTT, /* protocol */ 1988 64, /* max packet */ 1989 {0},{0},{0x00,0x01}, /* device id */ 1990 1,2,0, /* string indicies */ 1991 1 /* # of configurations */ 1992 }; 1993 1994 Static const usb_device_qualifier_t ehci_odevd = { 1995 USB_DEVICE_DESCRIPTOR_SIZE, 1996 UDESC_DEVICE_QUALIFIER, /* type */ 1997 {0x00, 0x02}, /* USB version */ 1998 UDCLASS_HUB, /* class */ 1999 UDSUBCLASS_HUB, /* subclass */ 2000 UDPROTO_FSHUB, /* protocol */ 2001 64, /* max packet */ 2002 1, /* # of configurations */ 2003 0 2004 }; 2005 2006 Static const usb_config_descriptor_t ehci_confd = { 2007 USB_CONFIG_DESCRIPTOR_SIZE, 2008 UDESC_CONFIG, 2009 {USB_CONFIG_DESCRIPTOR_SIZE + 2010 USB_INTERFACE_DESCRIPTOR_SIZE + 2011 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2012 1, 2013 1, 2014 0, 2015 UC_ATTR_MBO | UC_SELF_POWERED, 2016 0 /* max power */ 2017 }; 2018 2019 Static const usb_interface_descriptor_t ehci_ifcd = { 2020 USB_INTERFACE_DESCRIPTOR_SIZE, 2021 UDESC_INTERFACE, 2022 0, 2023 0, 2024 1, 2025 UICLASS_HUB, 2026 UISUBCLASS_HUB, 2027 UIPROTO_HSHUBSTT, 2028 0 2029 }; 2030 2031 Static const usb_endpoint_descriptor_t ehci_endpd = { 2032 USB_ENDPOINT_DESCRIPTOR_SIZE, 2033 UDESC_ENDPOINT, 2034 UE_DIR_IN | EHCI_INTR_ENDPT, 2035 UE_INTERRUPT, 2036 {8, 0}, /* max packet */ 2037 12 2038 }; 2039 2040 Static const usb_hub_descriptor_t ehci_hubd = { 2041 USB_HUB_DESCRIPTOR_SIZE, 2042 UDESC_HUB, 2043 0, 2044 {0,0}, 2045 0, 2046 0, 2047 {""}, 2048 {""}, 2049 }; 2050 2051 /* 2052 * Simulate a hardware hub by handling all the necessary requests. 2053 */ 2054 Static usbd_status 2055 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2056 { 2057 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2058 usbd_status err; 2059 2060 /* Insert last in queue. */ 2061 mutex_enter(&sc->sc_lock); 2062 err = usb_insert_transfer(xfer); 2063 mutex_exit(&sc->sc_lock); 2064 if (err) 2065 return (err); 2066 2067 /* Pipe isn't running, start first */ 2068 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2069 } 2070 2071 Static usbd_status 2072 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2073 { 2074 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2075 usb_device_request_t *req; 2076 void *buf = NULL; 2077 int port, i; 2078 int len, value, index, l, totlen = 0; 2079 usb_port_status_t ps; 2080 usb_hub_descriptor_t hubd; 2081 usbd_status err; 2082 u_int32_t v; 2083 2084 if (sc->sc_dying) 2085 return (USBD_IOERROR); 2086 2087 #ifdef DIAGNOSTIC 2088 if (!(xfer->rqflags & URQ_REQUEST)) 2089 /* XXX panic */ 2090 return (USBD_INVAL); 2091 #endif 2092 req = &xfer->request; 2093 2094 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2095 req->bmRequestType, req->bRequest)); 2096 2097 len = UGETW(req->wLength); 2098 value = UGETW(req->wValue); 2099 index = UGETW(req->wIndex); 2100 2101 if (len != 0) 2102 buf = KERNADDR(&xfer->dmabuf, 0); 2103 2104 #define C(x,y) ((x) | ((y) << 8)) 2105 switch(C(req->bRequest, req->bmRequestType)) { 2106 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2107 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2108 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2109 /* 2110 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2111 * for the integrated root hub. 2112 */ 2113 break; 2114 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2115 if (len > 0) { 2116 *(u_int8_t *)buf = sc->sc_conf; 2117 totlen = 1; 2118 } 2119 break; 2120 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2121 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2122 if (len == 0) 2123 break; 2124 switch(value >> 8) { 2125 case UDESC_DEVICE: 2126 if ((value & 0xff) != 0) { 2127 err = USBD_IOERROR; 2128 goto ret; 2129 } 2130 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2131 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2132 memcpy(buf, &ehci_devd, l); 2133 break; 2134 /* 2135 * We can't really operate at another speed, but the spec says 2136 * we need this descriptor. 2137 */ 2138 case UDESC_DEVICE_QUALIFIER: 2139 if ((value & 0xff) != 0) { 2140 err = USBD_IOERROR; 2141 goto ret; 2142 } 2143 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2144 memcpy(buf, &ehci_odevd, l); 2145 break; 2146 /* 2147 * We can't really operate at another speed, but the spec says 2148 * we need this descriptor. 2149 */ 2150 case UDESC_OTHER_SPEED_CONFIGURATION: 2151 case UDESC_CONFIG: 2152 if ((value & 0xff) != 0) { 2153 err = USBD_IOERROR; 2154 goto ret; 2155 } 2156 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2157 memcpy(buf, &ehci_confd, l); 2158 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2159 value >> 8; 2160 buf = (char *)buf + l; 2161 len -= l; 2162 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2163 totlen += l; 2164 memcpy(buf, &ehci_ifcd, l); 2165 buf = (char *)buf + l; 2166 len -= l; 2167 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2168 totlen += l; 2169 memcpy(buf, &ehci_endpd, l); 2170 break; 2171 case UDESC_STRING: 2172 #define sd ((usb_string_descriptor_t *)buf) 2173 switch (value & 0xff) { 2174 case 0: /* Language table */ 2175 totlen = usb_makelangtbl(sd, len); 2176 break; 2177 case 1: /* Vendor */ 2178 totlen = usb_makestrdesc(sd, len, 2179 sc->sc_vendor); 2180 break; 2181 case 2: /* Product */ 2182 totlen = usb_makestrdesc(sd, len, 2183 "EHCI root hub"); 2184 break; 2185 } 2186 #undef sd 2187 break; 2188 default: 2189 err = USBD_IOERROR; 2190 goto ret; 2191 } 2192 break; 2193 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2194 if (len > 0) { 2195 *(u_int8_t *)buf = 0; 2196 totlen = 1; 2197 } 2198 break; 2199 case C(UR_GET_STATUS, UT_READ_DEVICE): 2200 if (len > 1) { 2201 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2202 totlen = 2; 2203 } 2204 break; 2205 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2206 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2207 if (len > 1) { 2208 USETW(((usb_status_t *)buf)->wStatus, 0); 2209 totlen = 2; 2210 } 2211 break; 2212 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2213 if (value >= USB_MAX_DEVICES) { 2214 err = USBD_IOERROR; 2215 goto ret; 2216 } 2217 sc->sc_addr = value; 2218 break; 2219 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2220 if (value != 0 && value != 1) { 2221 err = USBD_IOERROR; 2222 goto ret; 2223 } 2224 sc->sc_conf = value; 2225 break; 2226 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2227 break; 2228 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2229 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2230 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2231 err = USBD_IOERROR; 2232 goto ret; 2233 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2234 break; 2235 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2236 break; 2237 /* Hub requests */ 2238 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2239 break; 2240 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2241 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2242 "port=%d feature=%d\n", 2243 index, value)); 2244 if (index < 1 || index > sc->sc_noport) { 2245 err = USBD_IOERROR; 2246 goto ret; 2247 } 2248 port = EHCI_PORTSC(index); 2249 v = EOREAD4(sc, port); 2250 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2251 v &= ~EHCI_PS_CLEAR; 2252 switch(value) { 2253 case UHF_PORT_ENABLE: 2254 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2255 break; 2256 case UHF_PORT_SUSPEND: 2257 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2258 break; 2259 v &= ~EHCI_PS_SUSP; 2260 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2261 /* see USB2 spec ch. 7.1.7.7 */ 2262 usb_delay_ms(&sc->sc_bus, 20); 2263 EOWRITE4(sc, port, v); 2264 usb_delay_ms(&sc->sc_bus, 2); 2265 #ifdef DEBUG 2266 v = EOREAD4(sc, port); 2267 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2268 printf("ehci: resume failed: %x\n", v); 2269 #endif 2270 break; 2271 case UHF_PORT_POWER: 2272 if (sc->sc_hasppc) 2273 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2274 break; 2275 case UHF_PORT_TEST: 2276 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2277 "%d\n", index)); 2278 break; 2279 case UHF_PORT_INDICATOR: 2280 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2281 "%d\n", index)); 2282 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2283 break; 2284 case UHF_C_PORT_CONNECTION: 2285 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2286 break; 2287 case UHF_C_PORT_ENABLE: 2288 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2289 break; 2290 case UHF_C_PORT_SUSPEND: 2291 /* how? */ 2292 break; 2293 case UHF_C_PORT_OVER_CURRENT: 2294 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2295 break; 2296 case UHF_C_PORT_RESET: 2297 sc->sc_isreset[index] = 0; 2298 break; 2299 default: 2300 err = USBD_IOERROR; 2301 goto ret; 2302 } 2303 #if 0 2304 switch(value) { 2305 case UHF_C_PORT_CONNECTION: 2306 case UHF_C_PORT_ENABLE: 2307 case UHF_C_PORT_SUSPEND: 2308 case UHF_C_PORT_OVER_CURRENT: 2309 case UHF_C_PORT_RESET: 2310 default: 2311 break; 2312 } 2313 #endif 2314 break; 2315 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2316 if (len == 0) 2317 break; 2318 if ((value & 0xff) != 0) { 2319 err = USBD_IOERROR; 2320 goto ret; 2321 } 2322 hubd = ehci_hubd; 2323 hubd.bNbrPorts = sc->sc_noport; 2324 v = EOREAD4(sc, EHCI_HCSPARAMS); 2325 USETW(hubd.wHubCharacteristics, 2326 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2327 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2328 ? UHD_PORT_IND : 0); 2329 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2330 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2331 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2332 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2333 l = min(len, hubd.bDescLength); 2334 totlen = l; 2335 memcpy(buf, &hubd, l); 2336 break; 2337 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2338 if (len != 4) { 2339 err = USBD_IOERROR; 2340 goto ret; 2341 } 2342 memset(buf, 0, len); /* ? XXX */ 2343 totlen = len; 2344 break; 2345 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2346 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2347 index)); 2348 if (index < 1 || index > sc->sc_noport) { 2349 err = USBD_IOERROR; 2350 goto ret; 2351 } 2352 if (len != 4) { 2353 err = USBD_IOERROR; 2354 goto ret; 2355 } 2356 v = EOREAD4(sc, EHCI_PORTSC(index)); 2357 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2358 2359 i = UPS_HIGH_SPEED; 2360 if (sc->sc_flags & EHCIF_ETTF) { 2361 /* 2362 * If we are doing embedded transaction translation, 2363 * then directly attached LS/FS devices are reset by 2364 * the EHCI controller itself. PSPD is encoded 2365 * the same way as in USBSTATUS. 2366 */ 2367 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2368 } 2369 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2370 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2371 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2372 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2373 if (v & EHCI_PS_PR) i |= UPS_RESET; 2374 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2375 if (sc->sc_vendor_port_status) 2376 i = sc->sc_vendor_port_status(sc, v, i); 2377 USETW(ps.wPortStatus, i); 2378 i = 0; 2379 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2380 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2381 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2382 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2383 USETW(ps.wPortChange, i); 2384 l = min(len, sizeof ps); 2385 memcpy(buf, &ps, l); 2386 totlen = l; 2387 break; 2388 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2389 err = USBD_IOERROR; 2390 goto ret; 2391 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2392 break; 2393 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2394 if (index < 1 || index > sc->sc_noport) { 2395 err = USBD_IOERROR; 2396 goto ret; 2397 } 2398 port = EHCI_PORTSC(index); 2399 v = EOREAD4(sc, port); 2400 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2401 v &= ~EHCI_PS_CLEAR; 2402 switch(value) { 2403 case UHF_PORT_ENABLE: 2404 EOWRITE4(sc, port, v | EHCI_PS_PE); 2405 break; 2406 case UHF_PORT_SUSPEND: 2407 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2408 break; 2409 case UHF_PORT_RESET: 2410 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2411 index)); 2412 if (EHCI_PS_IS_LOWSPEED(v) 2413 && sc->sc_ncomp > 0 2414 && !(sc->sc_flags & EHCIF_ETTF)) { 2415 /* 2416 * Low speed device on non-ETTF controller or 2417 * unaccompanied controller, give up ownership. 2418 */ 2419 ehci_disown(sc, index, 1); 2420 break; 2421 } 2422 /* Start reset sequence. */ 2423 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2424 EOWRITE4(sc, port, v | EHCI_PS_PR); 2425 /* Wait for reset to complete. */ 2426 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2427 if (sc->sc_dying) { 2428 err = USBD_IOERROR; 2429 goto ret; 2430 } 2431 /* 2432 * An embedded transaction translator will automatically 2433 * terminate the reset sequence so there's no need to 2434 * it. 2435 */ 2436 v = EOREAD4(sc, port); 2437 if (v & EHCI_PS_PR) { 2438 /* Terminate reset sequence. */ 2439 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2440 /* Wait for HC to complete reset. */ 2441 usb_delay_ms(&sc->sc_bus, 2442 EHCI_PORT_RESET_COMPLETE); 2443 if (sc->sc_dying) { 2444 err = USBD_IOERROR; 2445 goto ret; 2446 } 2447 } 2448 2449 v = EOREAD4(sc, port); 2450 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2451 if (v & EHCI_PS_PR) { 2452 printf("%s: port reset timeout\n", 2453 device_xname(sc->sc_dev)); 2454 return (USBD_TIMEOUT); 2455 } 2456 if (!(v & EHCI_PS_PE)) { 2457 /* Not a high speed device, give up ownership.*/ 2458 ehci_disown(sc, index, 0); 2459 break; 2460 } 2461 sc->sc_isreset[index] = 1; 2462 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2463 index, v)); 2464 break; 2465 case UHF_PORT_POWER: 2466 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2467 "%d (has PPC = %d)\n", index, 2468 sc->sc_hasppc)); 2469 if (sc->sc_hasppc) 2470 EOWRITE4(sc, port, v | EHCI_PS_PP); 2471 break; 2472 case UHF_PORT_TEST: 2473 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2474 "%d\n", index)); 2475 break; 2476 case UHF_PORT_INDICATOR: 2477 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2478 "%d\n", index)); 2479 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2480 break; 2481 default: 2482 err = USBD_IOERROR; 2483 goto ret; 2484 } 2485 break; 2486 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2487 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2488 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2489 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2490 break; 2491 default: 2492 err = USBD_IOERROR; 2493 goto ret; 2494 } 2495 xfer->actlen = totlen; 2496 err = USBD_NORMAL_COMPLETION; 2497 ret: 2498 mutex_enter(&sc->sc_lock); 2499 xfer->status = err; 2500 usb_transfer_complete(xfer); 2501 mutex_exit(&sc->sc_lock); 2502 return (USBD_IN_PROGRESS); 2503 } 2504 2505 Static void 2506 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2507 { 2508 int port; 2509 u_int32_t v; 2510 2511 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2512 #ifdef DIAGNOSTIC 2513 if (sc->sc_npcomp != 0) { 2514 int i = (index-1) / sc->sc_npcomp; 2515 if (i >= sc->sc_ncomp) 2516 printf("%s: strange port\n", 2517 device_xname(sc->sc_dev)); 2518 else 2519 printf("%s: handing over %s speed device on " 2520 "port %d to %s\n", 2521 device_xname(sc->sc_dev), 2522 lowspeed ? "low" : "full", 2523 index, device_xname(sc->sc_comps[i])); 2524 } else { 2525 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2526 } 2527 #endif 2528 port = EHCI_PORTSC(index); 2529 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2530 EOWRITE4(sc, port, v | EHCI_PS_PO); 2531 } 2532 2533 /* Abort a root control request. */ 2534 Static void 2535 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2536 { 2537 /* Nothing to do, all transfers are synchronous. */ 2538 } 2539 2540 /* Close the root pipe. */ 2541 Static void 2542 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2543 { 2544 DPRINTF(("ehci_root_ctrl_close\n")); 2545 /* Nothing to do. */ 2546 } 2547 2548 Static void 2549 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2550 { 2551 xfer->hcpriv = NULL; 2552 } 2553 2554 Static usbd_status 2555 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2556 { 2557 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2558 usbd_status err; 2559 2560 /* Insert last in queue. */ 2561 mutex_enter(&sc->sc_lock); 2562 err = usb_insert_transfer(xfer); 2563 mutex_exit(&sc->sc_lock); 2564 if (err) 2565 return (err); 2566 2567 /* Pipe isn't running, start first */ 2568 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2569 } 2570 2571 Static usbd_status 2572 ehci_root_intr_start(usbd_xfer_handle xfer) 2573 { 2574 usbd_pipe_handle pipe = xfer->pipe; 2575 ehci_softc_t *sc = pipe->device->bus->hci_private; 2576 2577 if (sc->sc_dying) 2578 return (USBD_IOERROR); 2579 2580 mutex_enter(&sc->sc_lock); 2581 sc->sc_intrxfer = xfer; 2582 mutex_exit(&sc->sc_lock); 2583 2584 return (USBD_IN_PROGRESS); 2585 } 2586 2587 /* Abort a root interrupt request. */ 2588 Static void 2589 ehci_root_intr_abort(usbd_xfer_handle xfer) 2590 { 2591 #ifdef DIAGNOSTIC 2592 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2593 #endif 2594 2595 KASSERT(mutex_owned(&sc->sc_lock)); 2596 if (xfer->pipe->intrxfer == xfer) { 2597 DPRINTF(("ehci_root_intr_abort: remove\n")); 2598 xfer->pipe->intrxfer = NULL; 2599 } 2600 xfer->status = USBD_CANCELLED; 2601 usb_transfer_complete(xfer); 2602 } 2603 2604 /* Close the root pipe. */ 2605 Static void 2606 ehci_root_intr_close(usbd_pipe_handle pipe) 2607 { 2608 ehci_softc_t *sc = pipe->device->bus->hci_private; 2609 2610 KASSERT(mutex_owned(&sc->sc_lock)); 2611 2612 DPRINTF(("ehci_root_intr_close\n")); 2613 2614 sc->sc_intrxfer = NULL; 2615 } 2616 2617 Static void 2618 ehci_root_intr_done(usbd_xfer_handle xfer) 2619 { 2620 xfer->hcpriv = NULL; 2621 } 2622 2623 /************************/ 2624 2625 Static ehci_soft_qh_t * 2626 ehci_alloc_sqh(ehci_softc_t *sc) 2627 { 2628 ehci_soft_qh_t *sqh; 2629 usbd_status err; 2630 int i, offs; 2631 usb_dma_t dma; 2632 2633 if (sc->sc_freeqhs == NULL) { 2634 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2635 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2636 EHCI_PAGE_SIZE, &dma); 2637 #ifdef EHCI_DEBUG 2638 if (err) 2639 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2640 #endif 2641 if (err) 2642 return (NULL); 2643 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2644 offs = i * EHCI_SQH_SIZE; 2645 sqh = KERNADDR(&dma, offs); 2646 sqh->physaddr = DMAADDR(&dma, offs); 2647 sqh->dma = dma; 2648 sqh->offs = offs; 2649 sqh->next = sc->sc_freeqhs; 2650 sc->sc_freeqhs = sqh; 2651 } 2652 } 2653 sqh = sc->sc_freeqhs; 2654 sc->sc_freeqhs = sqh->next; 2655 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2656 sqh->next = NULL; 2657 return (sqh); 2658 } 2659 2660 Static void 2661 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2662 { 2663 sqh->next = sc->sc_freeqhs; 2664 sc->sc_freeqhs = sqh; 2665 } 2666 2667 Static ehci_soft_qtd_t * 2668 ehci_alloc_sqtd(ehci_softc_t *sc) 2669 { 2670 ehci_soft_qtd_t *sqtd = NULL; 2671 usbd_status err; 2672 int i, offs; 2673 usb_dma_t dma; 2674 2675 if (sc->sc_freeqtds == NULL) { 2676 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2677 2678 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2679 EHCI_PAGE_SIZE, &dma); 2680 #ifdef EHCI_DEBUG 2681 if (err) 2682 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2683 #endif 2684 if (err) 2685 goto done; 2686 2687 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2688 offs = i * EHCI_SQTD_SIZE; 2689 sqtd = KERNADDR(&dma, offs); 2690 sqtd->physaddr = DMAADDR(&dma, offs); 2691 sqtd->dma = dma; 2692 sqtd->offs = offs; 2693 2694 sqtd->nextqtd = sc->sc_freeqtds; 2695 sc->sc_freeqtds = sqtd; 2696 } 2697 } 2698 2699 sqtd = sc->sc_freeqtds; 2700 sc->sc_freeqtds = sqtd->nextqtd; 2701 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2702 sqtd->nextqtd = NULL; 2703 sqtd->xfer = NULL; 2704 2705 done: 2706 return (sqtd); 2707 } 2708 2709 Static void 2710 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2711 { 2712 2713 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 2714 2715 sqtd->nextqtd = sc->sc_freeqtds; 2716 sc->sc_freeqtds = sqtd; 2717 } 2718 2719 Static usbd_status 2720 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2721 int alen, int rd, usbd_xfer_handle xfer, 2722 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2723 { 2724 ehci_soft_qtd_t *next, *cur; 2725 ehci_physaddr_t nextphys; 2726 u_int32_t qtdstatus; 2727 int len, curlen, mps; 2728 int i, tog; 2729 int pages, pageoffs; 2730 bus_size_t curoffs; 2731 vaddr_t va, va_offs; 2732 usb_dma_t *dma = &xfer->dmabuf; 2733 u_int16_t flags = xfer->flags; 2734 paddr_t a; 2735 2736 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2737 2738 len = alen; 2739 qtdstatus = EHCI_QTD_ACTIVE | 2740 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2741 EHCI_QTD_SET_CERR(3) 2742 /* IOC set below */ 2743 /* BYTES set below */ 2744 ; 2745 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2746 tog = epipe->nexttoggle; 2747 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2748 2749 cur = ehci_alloc_sqtd(sc); 2750 *sp = cur; 2751 if (cur == NULL) 2752 goto nomem; 2753 2754 usb_syncmem(dma, 0, alen, 2755 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2756 curoffs = 0; 2757 for (;;) { 2758 /* The EHCI hardware can handle at most 5 pages. */ 2759 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2760 va_offs = EHCI_PAGE_OFFSET(va_offs); 2761 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 2762 /* we can handle it in this QTD */ 2763 curlen = len - curoffs; 2764 } else { 2765 /* must use multiple TDs, fill as much as possible. */ 2766 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 2767 2768 /* the length must be a multiple of the max size */ 2769 curlen -= curlen % mps; 2770 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2771 "curlen=%d\n", curlen)); 2772 #ifdef DIAGNOSTIC 2773 if (curlen == 0) 2774 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2775 #endif 2776 } 2777 DPRINTFN(4,("ehci_alloc_sqtd_chain: len=%d curlen=%d " 2778 "curoffs=%zu\n", len, curlen, (size_t)curoffs)); 2779 2780 /* 2781 * Allocate another transfer if there's more data left, 2782 * or if force last short transfer flag is set and we're 2783 * allocating a multiple of the max packet size. 2784 */ 2785 2786 if (curoffs + curlen != len || 2787 ((curlen % mps) == 0 && !rd && curlen != 0 && 2788 (flags & USBD_FORCE_SHORT_XFER))) { 2789 next = ehci_alloc_sqtd(sc); 2790 if (next == NULL) 2791 goto nomem; 2792 nextphys = htole32(next->physaddr); 2793 } else { 2794 next = NULL; 2795 nextphys = EHCI_NULL; 2796 } 2797 2798 /* Find number of pages we'll be using, insert dma addresses */ 2799 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2800 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2801 pageoffs = EHCI_PAGE(curoffs); 2802 for (i = 0; i < pages; i++) { 2803 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2804 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2805 /* Cast up to avoid compiler warnings */ 2806 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2807 } 2808 2809 /* First buffer pointer requires a page offset to start at */ 2810 va = (vaddr_t)KERNADDR(dma, curoffs); 2811 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2812 2813 cur->nextqtd = next; 2814 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2815 cur->qtd.qtd_status = 2816 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2817 cur->xfer = xfer; 2818 cur->len = curlen; 2819 2820 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08zx end=0x%08zx\n", 2821 (size_t)curoffs, (size_t)(curoffs + curlen))); 2822 2823 /* adjust the toggle based on the number of packets in this 2824 qtd */ 2825 if (((curlen + mps - 1) / mps) & 1) { 2826 tog ^= 1; 2827 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2828 } 2829 if (next == NULL) 2830 break; 2831 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2832 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2833 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2834 if (len) 2835 curoffs += curlen; 2836 cur = next; 2837 } 2838 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2839 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2840 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2841 *ep = cur; 2842 epipe->nexttoggle = tog; 2843 2844 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2845 *sp, *ep)); 2846 2847 return (USBD_NORMAL_COMPLETION); 2848 2849 nomem: 2850 /* XXX free chain */ 2851 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2852 return (USBD_NOMEM); 2853 } 2854 2855 Static void 2856 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2857 ehci_soft_qtd_t *sqtdend) 2858 { 2859 ehci_soft_qtd_t *p; 2860 int i; 2861 2862 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2863 sqtd, sqtdend)); 2864 2865 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2866 p = sqtd->nextqtd; 2867 ehci_free_sqtd(sc, sqtd); 2868 } 2869 } 2870 2871 Static ehci_soft_itd_t * 2872 ehci_alloc_itd(ehci_softc_t *sc) 2873 { 2874 struct ehci_soft_itd *itd, *freeitd; 2875 usbd_status err; 2876 int i, offs, frindex, previndex; 2877 usb_dma_t dma; 2878 2879 mutex_enter(&sc->sc_lock); 2880 2881 /* Find an itd that wasn't freed this frame or last frame. This can 2882 * discard itds that were freed before frindex wrapped around 2883 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2884 * interrupt and fiddling with list when that happens */ 2885 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2886 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2887 2888 freeitd = NULL; 2889 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2890 if (itd == NULL) 2891 break; 2892 if (itd->slot != frindex && itd->slot != previndex) { 2893 freeitd = itd; 2894 break; 2895 } 2896 } 2897 2898 if (freeitd == NULL) { 2899 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2900 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2901 EHCI_PAGE_SIZE, &dma); 2902 2903 if (err) { 2904 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2905 mutex_exit(&sc->sc_lock); 2906 return NULL; 2907 } 2908 2909 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2910 offs = i * EHCI_ITD_SIZE; 2911 itd = KERNADDR(&dma, offs); 2912 itd->physaddr = DMAADDR(&dma, offs); 2913 itd->dma = dma; 2914 itd->offs = offs; 2915 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2916 } 2917 freeitd = LIST_FIRST(&sc->sc_freeitds); 2918 } 2919 2920 itd = freeitd; 2921 LIST_REMOVE(itd, u.free_list); 2922 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2923 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2924 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2925 BUS_DMASYNC_PREREAD); 2926 2927 itd->u.frame_list.next = NULL; 2928 itd->u.frame_list.prev = NULL; 2929 itd->xfer_next = NULL; 2930 itd->slot = 0; 2931 2932 mutex_exit(&sc->sc_lock); 2933 2934 return itd; 2935 } 2936 2937 Static void 2938 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2939 { 2940 2941 KASSERT(mutex_owned(&sc->sc_lock)); 2942 2943 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2944 } 2945 2946 /****************/ 2947 2948 /* 2949 * Close a reqular pipe. 2950 * Assumes that there are no pending transactions. 2951 */ 2952 Static void 2953 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2954 { 2955 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2956 ehci_softc_t *sc = pipe->device->bus->hci_private; 2957 ehci_soft_qh_t *sqh = epipe->sqh; 2958 2959 KASSERT(mutex_owned(&sc->sc_lock)); 2960 2961 ehci_rem_qh(sc, sqh, head); 2962 ehci_free_sqh(sc, epipe->sqh); 2963 } 2964 2965 /* 2966 * Abort a device request. 2967 * If this routine is called at splusb() it guarantees that the request 2968 * will be removed from the hardware scheduling and that the callback 2969 * for it will be called with USBD_CANCELLED status. 2970 * It's impossible to guarantee that the requested transfer will not 2971 * have happened since the hardware runs concurrently. 2972 * If the transaction has already happened we rely on the ordinary 2973 * interrupt processing to process it. 2974 * XXX This is most probably wrong. 2975 * XXXMRG this doesn't make sense anymore. 2976 */ 2977 Static void 2978 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2979 { 2980 #define exfer EXFER(xfer) 2981 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2982 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2983 ehci_soft_qh_t *sqh = epipe->sqh; 2984 ehci_soft_qtd_t *sqtd; 2985 ehci_physaddr_t cur; 2986 u_int32_t qhstatus; 2987 int hit; 2988 int wake; 2989 2990 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2991 2992 KASSERT(mutex_owned(&sc->sc_lock)); 2993 2994 if (sc->sc_dying) { 2995 /* If we're dying, just do the software part. */ 2996 xfer->status = status; /* make software ignore it */ 2997 callout_stop(&xfer->timeout_handle); 2998 usb_transfer_complete(xfer); 2999 return; 3000 } 3001 3002 if (cpu_intr_p() || cpu_softintr_p()) 3003 panic("ehci_abort_xfer: not in process context"); 3004 3005 /* 3006 * If an abort is already in progress then just wait for it to 3007 * complete and return. 3008 */ 3009 if (xfer->hcflags & UXFER_ABORTING) { 3010 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3011 #ifdef DIAGNOSTIC 3012 if (status == USBD_TIMEOUT) 3013 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3014 #endif 3015 /* Override the status which might be USBD_TIMEOUT. */ 3016 xfer->status = status; 3017 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3018 xfer->hcflags |= UXFER_ABORTWAIT; 3019 while (xfer->hcflags & UXFER_ABORTING) 3020 cv_wait(&xfer->hccv, &sc->sc_lock); 3021 return; 3022 } 3023 xfer->hcflags |= UXFER_ABORTING; 3024 3025 /* 3026 * Step 1: Make interrupt routine and hardware ignore xfer. 3027 */ 3028 xfer->status = status; /* make software ignore it */ 3029 callout_stop(&xfer->timeout_handle); 3030 3031 usb_syncmem(&sqh->dma, 3032 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3033 sizeof(sqh->qh.qh_qtd.qtd_status), 3034 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3035 qhstatus = sqh->qh.qh_qtd.qtd_status; 3036 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3037 usb_syncmem(&sqh->dma, 3038 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3039 sizeof(sqh->qh.qh_qtd.qtd_status), 3040 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3041 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3042 usb_syncmem(&sqtd->dma, 3043 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3044 sizeof(sqtd->qtd.qtd_status), 3045 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3046 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3047 usb_syncmem(&sqtd->dma, 3048 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3049 sizeof(sqtd->qtd.qtd_status), 3050 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3051 if (sqtd == exfer->sqtdend) 3052 break; 3053 } 3054 3055 /* 3056 * Step 2: Wait until we know hardware has finished any possible 3057 * use of the xfer. Also make sure the soft interrupt routine 3058 * has run. 3059 */ 3060 ehci_sync_hc(sc); 3061 sc->sc_softwake = 1; 3062 usb_schedsoftintr(&sc->sc_bus); 3063 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3064 3065 /* 3066 * Step 3: Remove any vestiges of the xfer from the hardware. 3067 * The complication here is that the hardware may have executed 3068 * beyond the xfer we're trying to abort. So as we're scanning 3069 * the TDs of this xfer we check if the hardware points to 3070 * any of them. 3071 */ 3072 3073 usb_syncmem(&sqh->dma, 3074 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3075 sizeof(sqh->qh.qh_curqtd), 3076 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3077 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3078 hit = 0; 3079 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3080 hit |= cur == sqtd->physaddr; 3081 if (sqtd == exfer->sqtdend) 3082 break; 3083 } 3084 sqtd = sqtd->nextqtd; 3085 /* Zap curqtd register if hardware pointed inside the xfer. */ 3086 if (hit && sqtd != NULL) { 3087 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3088 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3089 usb_syncmem(&sqh->dma, 3090 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3091 sizeof(sqh->qh.qh_curqtd), 3092 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3093 sqh->qh.qh_qtd.qtd_status = qhstatus; 3094 usb_syncmem(&sqh->dma, 3095 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3096 sizeof(sqh->qh.qh_qtd.qtd_status), 3097 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3098 } else { 3099 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3100 } 3101 3102 /* 3103 * Step 4: Execute callback. 3104 */ 3105 #ifdef DIAGNOSTIC 3106 exfer->isdone = 1; 3107 #endif 3108 wake = xfer->hcflags & UXFER_ABORTWAIT; 3109 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3110 usb_transfer_complete(xfer); 3111 if (wake) { 3112 cv_broadcast(&xfer->hccv); 3113 } 3114 3115 KASSERT(mutex_owned(&sc->sc_lock)); 3116 #undef exfer 3117 } 3118 3119 Static void 3120 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3121 { 3122 ehci_isoc_trans_t trans_status; 3123 struct ehci_pipe *epipe; 3124 struct ehci_xfer *exfer; 3125 ehci_softc_t *sc; 3126 struct ehci_soft_itd *itd; 3127 int i, wake; 3128 3129 epipe = (struct ehci_pipe *) xfer->pipe; 3130 exfer = EXFER(xfer); 3131 sc = epipe->pipe.device->bus->hci_private; 3132 3133 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3134 3135 KASSERT(mutex_owned(&sc->sc_lock)); 3136 3137 if (sc->sc_dying) { 3138 xfer->status = status; 3139 callout_stop(&xfer->timeout_handle); 3140 usb_transfer_complete(xfer); 3141 return; 3142 } 3143 3144 if (xfer->hcflags & UXFER_ABORTING) { 3145 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3146 3147 #ifdef DIAGNOSTIC 3148 if (status == USBD_TIMEOUT) 3149 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3150 #endif 3151 3152 xfer->status = status; 3153 DPRINTFN(2, ("ehci_abort_isoc_xfer: waiting for abort to finish\n")); 3154 xfer->hcflags |= UXFER_ABORTWAIT; 3155 while (xfer->hcflags & UXFER_ABORTING) 3156 cv_wait(&xfer->hccv, &sc->sc_lock); 3157 goto done; 3158 } 3159 xfer->hcflags |= UXFER_ABORTING; 3160 3161 xfer->status = status; 3162 callout_stop(&xfer->timeout_handle); 3163 3164 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3165 usb_syncmem(&itd->dma, 3166 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3167 sizeof(itd->itd.itd_ctl), 3168 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3169 3170 for (i = 0; i < 8; i++) { 3171 trans_status = le32toh(itd->itd.itd_ctl[i]); 3172 trans_status &= ~EHCI_ITD_ACTIVE; 3173 itd->itd.itd_ctl[i] = htole32(trans_status); 3174 } 3175 3176 usb_syncmem(&itd->dma, 3177 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3178 sizeof(itd->itd.itd_ctl), 3179 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3180 } 3181 3182 sc->sc_softwake = 1; 3183 usb_schedsoftintr(&sc->sc_bus); 3184 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3185 3186 #ifdef DIAGNOSTIC 3187 exfer->isdone = 1; 3188 #endif 3189 wake = xfer->hcflags & UXFER_ABORTWAIT; 3190 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3191 usb_transfer_complete(xfer); 3192 if (wake) { 3193 cv_broadcast(&xfer->hccv); 3194 } 3195 3196 done: 3197 KASSERT(mutex_owned(&sc->sc_lock)); 3198 return; 3199 } 3200 3201 Static void 3202 ehci_timeout(void *addr) 3203 { 3204 struct ehci_xfer *exfer = addr; 3205 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3206 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3207 3208 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3209 #ifdef EHCI_DEBUG 3210 if (ehcidebug > 1) 3211 usbd_dump_pipe(exfer->xfer.pipe); 3212 #endif 3213 3214 if (sc->sc_dying) { 3215 mutex_enter(&sc->sc_lock); 3216 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3217 mutex_exit(&sc->sc_lock); 3218 return; 3219 } 3220 3221 /* Execute the abort in a process context. */ 3222 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr, 3223 USB_TASKQ_MPSAFE); 3224 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3225 USB_TASKQ_HC); 3226 } 3227 3228 Static void 3229 ehci_timeout_task(void *addr) 3230 { 3231 usbd_xfer_handle xfer = addr; 3232 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3233 3234 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3235 3236 mutex_enter(&sc->sc_lock); 3237 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3238 mutex_exit(&sc->sc_lock); 3239 } 3240 3241 /************************/ 3242 3243 Static usbd_status 3244 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3245 { 3246 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3247 usbd_status err; 3248 3249 /* Insert last in queue. */ 3250 mutex_enter(&sc->sc_lock); 3251 err = usb_insert_transfer(xfer); 3252 mutex_exit(&sc->sc_lock); 3253 if (err) 3254 return (err); 3255 3256 /* Pipe isn't running, start first */ 3257 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3258 } 3259 3260 Static usbd_status 3261 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3262 { 3263 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3264 usbd_status err; 3265 3266 if (sc->sc_dying) 3267 return (USBD_IOERROR); 3268 3269 #ifdef DIAGNOSTIC 3270 if (!(xfer->rqflags & URQ_REQUEST)) { 3271 /* XXX panic */ 3272 printf("ehci_device_ctrl_transfer: not a request\n"); 3273 return (USBD_INVAL); 3274 } 3275 #endif 3276 3277 err = ehci_device_request(xfer); 3278 if (err) { 3279 return (err); 3280 } 3281 3282 if (sc->sc_bus.use_polling) 3283 ehci_waitintr(sc, xfer); 3284 3285 return (USBD_IN_PROGRESS); 3286 } 3287 3288 Static void 3289 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3290 { 3291 struct ehci_xfer *ex = EXFER(xfer); 3292 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3293 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3294 usb_device_request_t *req = &xfer->request; 3295 int len = UGETW(req->wLength); 3296 int rd = req->bmRequestType & UT_READ; 3297 3298 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3299 3300 KASSERT(mutex_owned(&sc->sc_lock)); 3301 3302 #ifdef DIAGNOSTIC 3303 if (!(xfer->rqflags & URQ_REQUEST)) { 3304 panic("ehci_ctrl_done: not a request"); 3305 } 3306 #endif 3307 3308 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3309 ehci_del_intr_list(sc, ex); /* remove from active list */ 3310 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3311 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3312 BUS_DMASYNC_POSTWRITE); 3313 if (len) 3314 usb_syncmem(&xfer->dmabuf, 0, len, 3315 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3316 } 3317 3318 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3319 } 3320 3321 /* Abort a device control request. */ 3322 Static void 3323 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3324 { 3325 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3326 ehci_abort_xfer(xfer, USBD_CANCELLED); 3327 } 3328 3329 /* Close a device control pipe. */ 3330 Static void 3331 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3332 { 3333 ehci_softc_t *sc = pipe->device->bus->hci_private; 3334 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3335 3336 KASSERT(mutex_owned(&sc->sc_lock)); 3337 3338 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3339 3340 ehci_close_pipe(pipe, sc->sc_async_head); 3341 } 3342 3343 Static usbd_status 3344 ehci_device_request(usbd_xfer_handle xfer) 3345 { 3346 #define exfer EXFER(xfer) 3347 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3348 usb_device_request_t *req = &xfer->request; 3349 usbd_device_handle dev = epipe->pipe.device; 3350 ehci_softc_t *sc = dev->bus->hci_private; 3351 int addr = dev->address; 3352 ehci_soft_qtd_t *setup, *stat, *next; 3353 ehci_soft_qh_t *sqh; 3354 int isread; 3355 int len; 3356 usbd_status err; 3357 3358 isread = req->bmRequestType & UT_READ; 3359 len = UGETW(req->wLength); 3360 3361 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3362 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3363 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3364 UGETW(req->wIndex), len, addr, 3365 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3366 3367 setup = ehci_alloc_sqtd(sc); 3368 if (setup == NULL) { 3369 err = USBD_NOMEM; 3370 goto bad1; 3371 } 3372 stat = ehci_alloc_sqtd(sc); 3373 if (stat == NULL) { 3374 err = USBD_NOMEM; 3375 goto bad2; 3376 } 3377 3378 mutex_enter(&sc->sc_lock); 3379 3380 sqh = epipe->sqh; 3381 3382 /* 3383 * Update device address and length since they may have changed 3384 * during the setup of the control pipe in usbd_new_device(). 3385 */ 3386 /* XXX This only needs to be done once, but it's too early in open. */ 3387 /* XXXX Should not touch ED here! */ 3388 sqh->qh.qh_endp = 3389 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3390 htole32( 3391 EHCI_QH_SET_ADDR(addr) | 3392 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3393 ); 3394 3395 /* Set up data transaction */ 3396 if (len != 0) { 3397 ehci_soft_qtd_t *end; 3398 3399 /* Start toggle at 1. */ 3400 epipe->nexttoggle = 1; 3401 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3402 &next, &end); 3403 if (err) 3404 goto bad3; 3405 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3406 end->nextqtd = stat; 3407 end->qtd.qtd_next = end->qtd.qtd_altnext = 3408 htole32(stat->physaddr); 3409 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3410 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3411 } else { 3412 next = stat; 3413 } 3414 3415 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3416 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3417 3418 /* Clear toggle */ 3419 setup->qtd.qtd_status = htole32( 3420 EHCI_QTD_ACTIVE | 3421 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3422 EHCI_QTD_SET_CERR(3) | 3423 EHCI_QTD_SET_TOGGLE(0) | 3424 EHCI_QTD_SET_BYTES(sizeof *req) 3425 ); 3426 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3427 setup->qtd.qtd_buffer_hi[0] = 0; 3428 setup->nextqtd = next; 3429 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3430 setup->xfer = xfer; 3431 setup->len = sizeof *req; 3432 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3433 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3434 3435 stat->qtd.qtd_status = htole32( 3436 EHCI_QTD_ACTIVE | 3437 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3438 EHCI_QTD_SET_CERR(3) | 3439 EHCI_QTD_SET_TOGGLE(1) | 3440 EHCI_QTD_IOC 3441 ); 3442 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3443 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3444 stat->nextqtd = NULL; 3445 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3446 stat->xfer = xfer; 3447 stat->len = 0; 3448 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3449 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3450 3451 #ifdef EHCI_DEBUG 3452 if (ehcidebug > 5) { 3453 DPRINTF(("ehci_device_request:\n")); 3454 ehci_dump_sqh(sqh); 3455 ehci_dump_sqtds(setup); 3456 } 3457 #endif 3458 3459 exfer->sqtdstart = setup; 3460 exfer->sqtdend = stat; 3461 #ifdef DIAGNOSTIC 3462 if (!exfer->isdone) { 3463 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3464 } 3465 exfer->isdone = 0; 3466 #endif 3467 3468 /* Insert qTD in QH list. */ 3469 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3470 if (xfer->timeout && !sc->sc_bus.use_polling) { 3471 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3472 ehci_timeout, xfer); 3473 } 3474 ehci_add_intr_list(sc, exfer); 3475 xfer->status = USBD_IN_PROGRESS; 3476 mutex_exit(&sc->sc_lock); 3477 3478 #ifdef EHCI_DEBUG 3479 if (ehcidebug > 10) { 3480 DPRINTF(("ehci_device_request: status=%x\n", 3481 EOREAD4(sc, EHCI_USBSTS))); 3482 delay(10000); 3483 ehci_dump_regs(sc); 3484 ehci_dump_sqh(sc->sc_async_head); 3485 ehci_dump_sqh(sqh); 3486 ehci_dump_sqtds(setup); 3487 } 3488 #endif 3489 3490 return (USBD_NORMAL_COMPLETION); 3491 3492 bad3: 3493 mutex_exit(&sc->sc_lock); 3494 ehci_free_sqtd(sc, stat); 3495 bad2: 3496 ehci_free_sqtd(sc, setup); 3497 bad1: 3498 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3499 mutex_enter(&sc->sc_lock); 3500 xfer->status = err; 3501 usb_transfer_complete(xfer); 3502 mutex_exit(&sc->sc_lock); 3503 return (err); 3504 #undef exfer 3505 } 3506 3507 /* 3508 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3509 * qTD status, or miss signalling occasionally under heavy load. If the host 3510 * machine is too fast, we we can miss transaction completion - when we scan 3511 * the active list the transaction still seems to be active. This generally 3512 * exhibits itself as a umass stall that never recovers. 3513 * 3514 * We work around this behaviour by setting up this callback after any softintr 3515 * that completes with transactions still pending, giving us another chance to 3516 * check for completion after the writeback has taken place. 3517 */ 3518 Static void 3519 ehci_intrlist_timeout(void *arg) 3520 { 3521 ehci_softc_t *sc = arg; 3522 3523 DPRINTF(("ehci_intrlist_timeout\n")); 3524 usb_schedsoftintr(&sc->sc_bus); 3525 } 3526 3527 /************************/ 3528 3529 Static usbd_status 3530 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3531 { 3532 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3533 usbd_status err; 3534 3535 /* Insert last in queue. */ 3536 mutex_enter(&sc->sc_lock); 3537 err = usb_insert_transfer(xfer); 3538 mutex_exit(&sc->sc_lock); 3539 if (err) 3540 return (err); 3541 3542 /* Pipe isn't running, start first */ 3543 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3544 } 3545 3546 Static usbd_status 3547 ehci_device_bulk_start(usbd_xfer_handle xfer) 3548 { 3549 #define exfer EXFER(xfer) 3550 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3551 usbd_device_handle dev = epipe->pipe.device; 3552 ehci_softc_t *sc = dev->bus->hci_private; 3553 ehci_soft_qtd_t *data, *dataend; 3554 ehci_soft_qh_t *sqh; 3555 usbd_status err; 3556 int len, isread, endpt; 3557 3558 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3559 xfer, xfer->length, xfer->flags)); 3560 3561 if (sc->sc_dying) 3562 return (USBD_IOERROR); 3563 3564 #ifdef DIAGNOSTIC 3565 if (xfer->rqflags & URQ_REQUEST) 3566 panic("ehci_device_bulk_start: a request"); 3567 #endif 3568 3569 mutex_enter(&sc->sc_lock); 3570 3571 len = xfer->length; 3572 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3573 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3574 sqh = epipe->sqh; 3575 3576 epipe->u.bulk.length = len; 3577 3578 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3579 &dataend); 3580 if (err) { 3581 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3582 xfer->status = err; 3583 usb_transfer_complete(xfer); 3584 mutex_exit(&sc->sc_lock); 3585 return (err); 3586 } 3587 3588 #ifdef EHCI_DEBUG 3589 if (ehcidebug > 5) { 3590 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3591 ehci_dump_sqh(sqh); 3592 ehci_dump_sqtds(data); 3593 } 3594 #endif 3595 3596 /* Set up interrupt info. */ 3597 exfer->sqtdstart = data; 3598 exfer->sqtdend = dataend; 3599 #ifdef DIAGNOSTIC 3600 if (!exfer->isdone) { 3601 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3602 } 3603 exfer->isdone = 0; 3604 #endif 3605 3606 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3607 if (xfer->timeout && !sc->sc_bus.use_polling) { 3608 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3609 ehci_timeout, xfer); 3610 } 3611 ehci_add_intr_list(sc, exfer); 3612 xfer->status = USBD_IN_PROGRESS; 3613 mutex_exit(&sc->sc_lock); 3614 3615 #ifdef EHCI_DEBUG 3616 if (ehcidebug > 10) { 3617 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3618 delay(10000); 3619 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3620 ehci_dump_regs(sc); 3621 #if 0 3622 printf("async_head:\n"); 3623 ehci_dump_sqh(sc->sc_async_head); 3624 #endif 3625 printf("sqh:\n"); 3626 ehci_dump_sqh(sqh); 3627 ehci_dump_sqtds(data); 3628 } 3629 #endif 3630 3631 if (sc->sc_bus.use_polling) 3632 ehci_waitintr(sc, xfer); 3633 3634 return (USBD_IN_PROGRESS); 3635 #undef exfer 3636 } 3637 3638 Static void 3639 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3640 { 3641 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3642 ehci_abort_xfer(xfer, USBD_CANCELLED); 3643 } 3644 3645 /* 3646 * Close a device bulk pipe. 3647 */ 3648 Static void 3649 ehci_device_bulk_close(usbd_pipe_handle pipe) 3650 { 3651 ehci_softc_t *sc = pipe->device->bus->hci_private; 3652 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3653 3654 KASSERT(mutex_owned(&sc->sc_lock)); 3655 3656 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3657 pipe->endpoint->datatoggle = epipe->nexttoggle; 3658 ehci_close_pipe(pipe, sc->sc_async_head); 3659 } 3660 3661 Static void 3662 ehci_device_bulk_done(usbd_xfer_handle xfer) 3663 { 3664 struct ehci_xfer *ex = EXFER(xfer); 3665 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3666 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3667 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3668 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3669 3670 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3671 xfer, xfer->actlen)); 3672 3673 KASSERT(mutex_owned(&sc->sc_lock)); 3674 3675 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3676 ehci_del_intr_list(sc, ex); /* remove from active list */ 3677 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3678 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3679 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3680 } 3681 3682 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3683 } 3684 3685 /************************/ 3686 3687 Static usbd_status 3688 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3689 { 3690 struct ehci_soft_islot *isp; 3691 int islot, lev; 3692 3693 /* Find a poll rate that is large enough. */ 3694 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3695 if (EHCI_ILEV_IVAL(lev) <= ival) 3696 break; 3697 3698 /* Pick an interrupt slot at the right level. */ 3699 /* XXX could do better than picking at random */ 3700 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3701 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3702 3703 sqh->islot = islot; 3704 isp = &sc->sc_islots[islot]; 3705 mutex_enter(&sc->sc_lock); 3706 ehci_add_qh(sc, sqh, isp->sqh); 3707 mutex_exit(&sc->sc_lock); 3708 3709 return (USBD_NORMAL_COMPLETION); 3710 } 3711 3712 Static usbd_status 3713 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3714 { 3715 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3716 usbd_status err; 3717 3718 /* Insert last in queue. */ 3719 mutex_enter(&sc->sc_lock); 3720 err = usb_insert_transfer(xfer); 3721 mutex_exit(&sc->sc_lock); 3722 if (err) 3723 return (err); 3724 3725 /* 3726 * Pipe isn't running (otherwise err would be USBD_INPROG), 3727 * so start it first. 3728 */ 3729 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3730 } 3731 3732 Static usbd_status 3733 ehci_device_intr_start(usbd_xfer_handle xfer) 3734 { 3735 #define exfer EXFER(xfer) 3736 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3737 usbd_device_handle dev = xfer->pipe->device; 3738 ehci_softc_t *sc = dev->bus->hci_private; 3739 ehci_soft_qtd_t *data, *dataend; 3740 ehci_soft_qh_t *sqh; 3741 usbd_status err; 3742 int len, isread, endpt; 3743 3744 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3745 xfer, xfer->length, xfer->flags)); 3746 3747 if (sc->sc_dying) 3748 return (USBD_IOERROR); 3749 3750 #ifdef DIAGNOSTIC 3751 if (xfer->rqflags & URQ_REQUEST) 3752 panic("ehci_device_intr_start: a request"); 3753 #endif 3754 3755 mutex_enter(&sc->sc_lock); 3756 3757 len = xfer->length; 3758 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3759 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3760 sqh = epipe->sqh; 3761 3762 epipe->u.intr.length = len; 3763 3764 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3765 &dataend); 3766 if (err) { 3767 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3768 xfer->status = err; 3769 usb_transfer_complete(xfer); 3770 mutex_exit(&sc->sc_lock); 3771 return (err); 3772 } 3773 3774 #ifdef EHCI_DEBUG 3775 if (ehcidebug > 5) { 3776 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3777 ehci_dump_sqh(sqh); 3778 ehci_dump_sqtds(data); 3779 } 3780 #endif 3781 3782 /* Set up interrupt info. */ 3783 exfer->sqtdstart = data; 3784 exfer->sqtdend = dataend; 3785 #ifdef DIAGNOSTIC 3786 if (!exfer->isdone) { 3787 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3788 } 3789 exfer->isdone = 0; 3790 #endif 3791 3792 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3793 if (xfer->timeout && !sc->sc_bus.use_polling) { 3794 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3795 ehci_timeout, xfer); 3796 } 3797 ehci_add_intr_list(sc, exfer); 3798 xfer->status = USBD_IN_PROGRESS; 3799 mutex_exit(&sc->sc_lock); 3800 3801 #ifdef EHCI_DEBUG 3802 if (ehcidebug > 10) { 3803 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3804 delay(10000); 3805 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3806 ehci_dump_regs(sc); 3807 printf("sqh:\n"); 3808 ehci_dump_sqh(sqh); 3809 ehci_dump_sqtds(data); 3810 } 3811 #endif 3812 3813 if (sc->sc_bus.use_polling) 3814 ehci_waitintr(sc, xfer); 3815 3816 return (USBD_IN_PROGRESS); 3817 #undef exfer 3818 } 3819 3820 Static void 3821 ehci_device_intr_abort(usbd_xfer_handle xfer) 3822 { 3823 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3824 if (xfer->pipe->intrxfer == xfer) { 3825 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3826 xfer->pipe->intrxfer = NULL; 3827 } 3828 /* 3829 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3830 * async doorbell. That's dependent on the async list, wheras 3831 * intr xfers are periodic, should not use this? 3832 */ 3833 ehci_abort_xfer(xfer, USBD_CANCELLED); 3834 } 3835 3836 Static void 3837 ehci_device_intr_close(usbd_pipe_handle pipe) 3838 { 3839 ehci_softc_t *sc = pipe->device->bus->hci_private; 3840 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3841 struct ehci_soft_islot *isp; 3842 3843 KASSERT(mutex_owned(&sc->sc_lock)); 3844 3845 isp = &sc->sc_islots[epipe->sqh->islot]; 3846 ehci_close_pipe(pipe, isp->sqh); 3847 } 3848 3849 Static void 3850 ehci_device_intr_done(usbd_xfer_handle xfer) 3851 { 3852 #define exfer EXFER(xfer) 3853 struct ehci_xfer *ex = EXFER(xfer); 3854 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3855 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3856 ehci_soft_qtd_t *data, *dataend; 3857 ehci_soft_qh_t *sqh; 3858 usbd_status err; 3859 int len, isread, endpt; 3860 3861 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3862 xfer, xfer->actlen)); 3863 3864 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 3865 3866 if (xfer->pipe->repeat) { 3867 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3868 3869 len = epipe->u.intr.length; 3870 xfer->length = len; 3871 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3872 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3873 usb_syncmem(&xfer->dmabuf, 0, len, 3874 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3875 sqh = epipe->sqh; 3876 3877 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3878 &data, &dataend); 3879 if (err) { 3880 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3881 xfer->status = err; 3882 return; 3883 } 3884 3885 /* Set up interrupt info. */ 3886 exfer->sqtdstart = data; 3887 exfer->sqtdend = dataend; 3888 #ifdef DIAGNOSTIC 3889 if (!exfer->isdone) { 3890 printf("ehci_device_intr_done: not done, ex=%p\n", 3891 exfer); 3892 } 3893 exfer->isdone = 0; 3894 #endif 3895 3896 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3897 if (xfer->timeout && !sc->sc_bus.use_polling) { 3898 callout_reset(&xfer->timeout_handle, 3899 mstohz(xfer->timeout), ehci_timeout, xfer); 3900 } 3901 3902 xfer->status = USBD_IN_PROGRESS; 3903 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3904 ehci_del_intr_list(sc, ex); /* remove from active list */ 3905 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3906 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3907 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3908 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3909 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3910 } 3911 #undef exfer 3912 } 3913 3914 /************************/ 3915 3916 Static usbd_status 3917 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3918 { 3919 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3920 usbd_status err; 3921 3922 mutex_enter(&sc->sc_lock); 3923 err = usb_insert_transfer(xfer); 3924 mutex_exit(&sc->sc_lock); 3925 if (err && err != USBD_IN_PROGRESS) 3926 return err; 3927 3928 return ehci_device_isoc_start(xfer); 3929 } 3930 3931 Static usbd_status 3932 ehci_device_isoc_start(usbd_xfer_handle xfer) 3933 { 3934 struct ehci_pipe *epipe; 3935 ehci_softc_t *sc; 3936 struct ehci_xfer *exfer; 3937 ehci_soft_itd_t *itd, *prev, *start, *stop; 3938 usb_dma_t *dma_buf; 3939 int i, j, k, frames, uframes, ufrperframe; 3940 int trans_count, offs, total_length; 3941 int frindex; 3942 3943 start = NULL; 3944 prev = NULL; 3945 itd = NULL; 3946 trans_count = 0; 3947 total_length = 0; 3948 exfer = (struct ehci_xfer *) xfer; 3949 sc = xfer->pipe->device->bus->hci_private; 3950 epipe = (struct ehci_pipe *)xfer->pipe; 3951 3952 /* 3953 * To allow continuous transfers, above we start all transfers 3954 * immediately. However, we're still going to get usbd_start_next call 3955 * this when another xfer completes. So, check if this is already 3956 * in progress or not 3957 */ 3958 3959 if (exfer->itdstart != NULL) 3960 return USBD_IN_PROGRESS; 3961 3962 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3963 xfer, xfer->length, xfer->flags)); 3964 3965 if (sc->sc_dying) 3966 return USBD_IOERROR; 3967 3968 /* 3969 * To avoid complication, don't allow a request right now that'll span 3970 * the entire frame table. To within 4 frames, to allow some leeway 3971 * on either side of where the hc currently is. 3972 */ 3973 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3974 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3975 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3976 return USBD_INVAL; 3977 } 3978 3979 #ifdef DIAGNOSTIC 3980 if (xfer->rqflags & URQ_REQUEST) 3981 panic("ehci_device_isoc_start: request\n"); 3982 3983 if (!exfer->isdone) 3984 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3985 exfer->isdone = 0; 3986 #endif 3987 3988 /* 3989 * Step 1: Allocate and initialize itds, how many do we need? 3990 * One per transfer if interval >= 8 microframes, fewer if we use 3991 * multiple microframes per frame. 3992 */ 3993 3994 i = epipe->pipe.endpoint->edesc->bInterval; 3995 if (i > 16 || i == 0) { 3996 /* Spec page 271 says intervals > 16 are invalid */ 3997 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3998 return USBD_INVAL; 3999 } 4000 4001 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4002 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4003 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4004 4005 if (frames == 0) { 4006 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 4007 return USBD_INVAL; 4008 } 4009 4010 dma_buf = &xfer->dmabuf; 4011 offs = 0; 4012 4013 for (i = 0; i < frames; i++) { 4014 int froffs = offs; 4015 itd = ehci_alloc_itd(sc); 4016 4017 if (prev != NULL) { 4018 prev->itd.itd_next = 4019 htole32(itd->physaddr | EHCI_LINK_ITD); 4020 usb_syncmem(&itd->dma, 4021 itd->offs + offsetof(ehci_itd_t, itd_next), 4022 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4023 4024 prev->xfer_next = itd; 4025 } else { 4026 start = itd; 4027 } 4028 4029 /* 4030 * Step 1.5, initialize uframes 4031 */ 4032 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4033 /* Calculate which page in the list this starts in */ 4034 int addr = DMAADDR(dma_buf, froffs); 4035 addr = EHCI_PAGE_OFFSET(addr); 4036 addr += (offs - froffs); 4037 addr = EHCI_PAGE(addr); 4038 addr /= EHCI_PAGE_SIZE; 4039 4040 /* This gets the initial offset into the first page, 4041 * looks how far further along the current uframe 4042 * offset is. Works out how many pages that is. 4043 */ 4044 4045 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4046 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4047 EHCI_ITD_SET_PG(addr) | 4048 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4049 4050 total_length += xfer->frlengths[trans_count]; 4051 offs += xfer->frlengths[trans_count]; 4052 trans_count++; 4053 4054 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4055 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4056 break; 4057 } 4058 } 4059 4060 /* Step 1.75, set buffer pointers. To simplify matters, all 4061 * pointers are filled out for the next 7 hardware pages in 4062 * the dma block, so no need to worry what pages to cover 4063 * and what to not. 4064 */ 4065 4066 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4067 /* 4068 * Don't try to lookup a page that's past the end 4069 * of buffer 4070 */ 4071 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4072 if (page_offs >= dma_buf->block->size) 4073 break; 4074 4075 unsigned long long page = DMAADDR(dma_buf, page_offs); 4076 page = EHCI_PAGE(page); 4077 itd->itd.itd_bufr[j] = 4078 htole32(EHCI_ITD_SET_BPTR(page)); 4079 itd->itd.itd_bufr_hi[j] = 4080 htole32(page >> 32); 4081 } 4082 4083 /* 4084 * Other special values 4085 */ 4086 4087 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4088 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4089 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4090 4091 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4092 ? 1 : 0; 4093 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4094 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4095 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4096 4097 /* FIXME: handle invalid trans */ 4098 itd->itd.itd_bufr[2] |= 4099 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4100 4101 usb_syncmem(&itd->dma, 4102 itd->offs + offsetof(ehci_itd_t, itd_next), 4103 sizeof(ehci_itd_t), 4104 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4105 4106 prev = itd; 4107 } /* End of frame */ 4108 4109 stop = itd; 4110 stop->xfer_next = NULL; 4111 exfer->isoc_len = total_length; 4112 4113 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4114 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4115 4116 /* 4117 * Part 2: Transfer descriptors have now been set up, now they must 4118 * be scheduled into the period frame list. Erk. Not wanting to 4119 * complicate matters, transfer is denied if the transfer spans 4120 * more than the period frame list. 4121 */ 4122 4123 mutex_enter(&sc->sc_lock); 4124 4125 /* Start inserting frames */ 4126 if (epipe->u.isoc.cur_xfers > 0) { 4127 frindex = epipe->u.isoc.next_frame; 4128 } else { 4129 frindex = EOREAD4(sc, EHCI_FRINDEX); 4130 frindex = frindex >> 3; /* Erase microframe index */ 4131 frindex += 2; 4132 } 4133 4134 if (frindex >= sc->sc_flsize) 4135 frindex &= (sc->sc_flsize - 1); 4136 4137 /* What's the frame interval? */ 4138 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4139 if (i / USB_UFRAMES_PER_FRAME == 0) 4140 i = 1; 4141 else 4142 i /= USB_UFRAMES_PER_FRAME; 4143 4144 itd = start; 4145 for (j = 0; j < frames; j++) { 4146 if (itd == NULL) 4147 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4148 4149 itd->itd.itd_next = sc->sc_flist[frindex]; 4150 if (itd->itd.itd_next == 0) 4151 /* FIXME: frindex table gets initialized to NULL 4152 * or EHCI_NULL? */ 4153 itd->itd.itd_next = EHCI_NULL; 4154 4155 usb_syncmem(&itd->dma, 4156 itd->offs + offsetof(ehci_itd_t, itd_next), 4157 sizeof(itd->itd.itd_next), 4158 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4159 4160 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4161 4162 usb_syncmem(&sc->sc_fldma, 4163 sizeof(ehci_link_t) * frindex, 4164 sizeof(ehci_link_t), 4165 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4166 4167 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4168 sc->sc_softitds[frindex] = itd; 4169 if (itd->u.frame_list.next != NULL) 4170 itd->u.frame_list.next->u.frame_list.prev = itd; 4171 itd->slot = frindex; 4172 itd->u.frame_list.prev = NULL; 4173 4174 frindex += i; 4175 if (frindex >= sc->sc_flsize) 4176 frindex -= sc->sc_flsize; 4177 4178 itd = itd->xfer_next; 4179 } 4180 4181 epipe->u.isoc.cur_xfers++; 4182 epipe->u.isoc.next_frame = frindex; 4183 4184 exfer->itdstart = start; 4185 exfer->itdend = stop; 4186 exfer->sqtdstart = NULL; 4187 exfer->sqtdstart = NULL; 4188 4189 ehci_add_intr_list(sc, exfer); 4190 xfer->status = USBD_IN_PROGRESS; 4191 xfer->done = 0; 4192 mutex_exit(&sc->sc_lock); 4193 4194 if (sc->sc_bus.use_polling) { 4195 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4196 ehci_waitintr(sc, xfer); 4197 } 4198 4199 return USBD_IN_PROGRESS; 4200 } 4201 4202 Static void 4203 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4204 { 4205 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4206 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4207 } 4208 4209 Static void 4210 ehci_device_isoc_close(usbd_pipe_handle pipe) 4211 { 4212 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4213 } 4214 4215 Static void 4216 ehci_device_isoc_done(usbd_xfer_handle xfer) 4217 { 4218 struct ehci_xfer *exfer; 4219 ehci_softc_t *sc; 4220 struct ehci_pipe *epipe; 4221 4222 exfer = EXFER(xfer); 4223 sc = xfer->pipe->device->bus->hci_private; 4224 epipe = (struct ehci_pipe *) xfer->pipe; 4225 4226 KASSERT(mutex_owned(&sc->sc_lock)); 4227 4228 epipe->u.isoc.cur_xfers--; 4229 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4230 ehci_del_intr_list(sc, exfer); 4231 ehci_rem_free_itd_chain(sc, exfer); 4232 } 4233 4234 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4235 BUS_DMASYNC_POSTREAD); 4236 4237 } 4238
Indexes created Mon Sep 22 21:09:42 GMT 2025