ehci.c revision 1.217
1 /* $NetBSD: ehci.c,v 1.217 2013/11/23 12:41:13 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.217 2013/11/23 12:41:13 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/kernel.h> 64 #include <sys/kmem.h> 65 #include <sys/device.h> 66 #include <sys/select.h> 67 #include <sys/proc.h> 68 #include <sys/queue.h> 69 #include <sys/mutex.h> 70 #include <sys/bus.h> 71 #include <sys/cpu.h> 72 73 #include <machine/endian.h> 74 75 #include <dev/usb/usb.h> 76 #include <dev/usb/usbdi.h> 77 #include <dev/usb/usbdivar.h> 78 #include <dev/usb/usb_mem.h> 79 #include <dev/usb/usb_quirks.h> 80 81 #include <dev/usb/ehcireg.h> 82 #include <dev/usb/ehcivar.h> 83 #include <dev/usb/usbroothub_subr.h> 84 85 #ifdef EHCI_DEBUG 86 static void __printflike(1, 2) 87 ehciprintf(const char *fmt, ...) 88 { 89 va_list ap; 90 91 va_start(ap, fmt); 92 vprintf(fmt, ap); 93 va_end(ap); 94 } 95 96 #define DPRINTF(x) do { if (ehcidebug) ehciprintf x; } while(0) 97 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) ehciprintf x; } while (0) 98 int ehcidebug = 0; 99 #else 100 #define DPRINTF(x) 101 #define DPRINTFN(n,x) 102 #endif 103 104 struct ehci_pipe { 105 struct usbd_pipe pipe; 106 int nexttoggle; 107 108 ehci_soft_qh_t *sqh; 109 union { 110 ehci_soft_qtd_t *qtd; 111 /* ehci_soft_itd_t *itd; */ 112 } tail; 113 union { 114 /* Control pipe */ 115 struct { 116 usb_dma_t reqdma; 117 } ctl; 118 /* Interrupt pipe */ 119 struct { 120 u_int length; 121 } intr; 122 /* Bulk pipe */ 123 struct { 124 u_int length; 125 } bulk; 126 /* Iso pipe */ 127 struct { 128 u_int next_frame; 129 u_int cur_xfers; 130 } isoc; 131 } u; 132 }; 133 134 Static usbd_status ehci_open(usbd_pipe_handle); 135 Static void ehci_poll(struct usbd_bus *); 136 Static void ehci_softintr(void *); 137 Static int ehci_intr1(ehci_softc_t *); 138 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 139 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 140 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 141 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 142 Static void ehci_idone(struct ehci_xfer *); 143 Static void ehci_timeout(void *); 144 Static void ehci_timeout_task(void *); 145 Static void ehci_intrlist_timeout(void *); 146 Static void ehci_doorbell(void *); 147 Static void ehci_pcd(void *); 148 149 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 150 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 151 152 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 153 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 154 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 155 156 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 157 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 158 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 159 Static void ehci_root_ctrl_close(usbd_pipe_handle); 160 Static void ehci_root_ctrl_done(usbd_xfer_handle); 161 162 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 163 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 164 Static void ehci_root_intr_abort(usbd_xfer_handle); 165 Static void ehci_root_intr_close(usbd_pipe_handle); 166 Static void ehci_root_intr_done(usbd_xfer_handle); 167 168 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 169 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 170 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 171 Static void ehci_device_ctrl_close(usbd_pipe_handle); 172 Static void ehci_device_ctrl_done(usbd_xfer_handle); 173 174 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 175 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 176 Static void ehci_device_bulk_abort(usbd_xfer_handle); 177 Static void ehci_device_bulk_close(usbd_pipe_handle); 178 Static void ehci_device_bulk_done(usbd_xfer_handle); 179 180 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 181 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 182 Static void ehci_device_intr_abort(usbd_xfer_handle); 183 Static void ehci_device_intr_close(usbd_pipe_handle); 184 Static void ehci_device_intr_done(usbd_xfer_handle); 185 186 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 187 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 188 Static void ehci_device_isoc_abort(usbd_xfer_handle); 189 Static void ehci_device_isoc_close(usbd_pipe_handle); 190 Static void ehci_device_isoc_done(usbd_xfer_handle); 191 192 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 193 Static void ehci_noop(usbd_pipe_handle pipe); 194 195 Static void ehci_disown(ehci_softc_t *, int, int); 196 197 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 198 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 199 200 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 201 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 202 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 203 ehci_softc_t *, int, int, usbd_xfer_handle, 204 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 205 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 206 ehci_soft_qtd_t *); 207 208 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 209 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 210 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 211 struct ehci_xfer *exfer); 212 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 213 usbd_status status); 214 215 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 216 217 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 218 int ival); 219 220 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 221 ehci_soft_qh_t *); 222 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 223 ehci_soft_qh_t *); 224 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 225 Static void ehci_sync_hc(ehci_softc_t *); 226 227 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 228 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 229 230 #ifdef EHCI_DEBUG 231 Static void ehci_dump_regs(ehci_softc_t *); 232 void ehci_dump(void); 233 Static ehci_softc_t *theehci; 234 Static void ehci_dump_link(ehci_link_t, int); 235 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 236 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 237 Static void ehci_dump_qtd(ehci_qtd_t *); 238 Static void ehci_dump_sqh(ehci_soft_qh_t *); 239 #if notyet 240 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 241 Static void ehci_dump_itd(struct ehci_soft_itd *); 242 #endif 243 #ifdef DIAGNOSTIC 244 Static void ehci_dump_exfer(struct ehci_xfer *); 245 #endif 246 #endif 247 248 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 249 250 #define EHCI_INTR_ENDPT 1 251 252 #define ehci_add_intr_list(sc, ex) \ 253 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 254 #define ehci_del_intr_list(sc, ex) \ 255 do { \ 256 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 257 (ex)->inext.tqe_prev = NULL; \ 258 } while (0) 259 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 260 261 Static const struct usbd_bus_methods ehci_bus_methods = { 262 .open_pipe = ehci_open, 263 .soft_intr = ehci_softintr, 264 .do_poll = ehci_poll, 265 .allocm = ehci_allocm, 266 .freem = ehci_freem, 267 .allocx = ehci_allocx, 268 .freex = ehci_freex, 269 .get_lock = ehci_get_lock, 270 .new_device = NULL, 271 }; 272 273 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 274 .transfer = ehci_root_ctrl_transfer, 275 .start = ehci_root_ctrl_start, 276 .abort = ehci_root_ctrl_abort, 277 .close = ehci_root_ctrl_close, 278 .cleartoggle = ehci_noop, 279 .done = ehci_root_ctrl_done, 280 }; 281 282 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 283 .transfer = ehci_root_intr_transfer, 284 .start = ehci_root_intr_start, 285 .abort = ehci_root_intr_abort, 286 .close = ehci_root_intr_close, 287 .cleartoggle = ehci_noop, 288 .done = ehci_root_intr_done, 289 }; 290 291 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 292 .transfer = ehci_device_ctrl_transfer, 293 .start = ehci_device_ctrl_start, 294 .abort = ehci_device_ctrl_abort, 295 .close = ehci_device_ctrl_close, 296 .cleartoggle = ehci_noop, 297 .done = ehci_device_ctrl_done, 298 }; 299 300 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 301 .transfer = ehci_device_intr_transfer, 302 .start = ehci_device_intr_start, 303 .abort = ehci_device_intr_abort, 304 .close = ehci_device_intr_close, 305 .cleartoggle = ehci_device_clear_toggle, 306 .done = ehci_device_intr_done, 307 }; 308 309 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 310 .transfer = ehci_device_bulk_transfer, 311 .start = ehci_device_bulk_start, 312 .abort = ehci_device_bulk_abort, 313 .close = ehci_device_bulk_close, 314 .cleartoggle = ehci_device_clear_toggle, 315 .done = ehci_device_bulk_done, 316 }; 317 318 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 319 .transfer = ehci_device_isoc_transfer, 320 .start = ehci_device_isoc_start, 321 .abort = ehci_device_isoc_abort, 322 .close = ehci_device_isoc_close, 323 .cleartoggle = ehci_noop, 324 .done = ehci_device_isoc_done, 325 }; 326 327 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 328 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 329 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 330 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 331 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 332 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 333 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 334 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 335 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 336 }; 337 338 usbd_status 339 ehci_init(ehci_softc_t *sc) 340 { 341 u_int32_t vers, sparams, cparams, hcr; 342 u_int i; 343 usbd_status err; 344 ehci_soft_qh_t *sqh; 345 u_int ncomp; 346 347 DPRINTF(("ehci_init: start\n")); 348 #ifdef EHCI_DEBUG 349 theehci = sc; 350 #endif 351 352 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 353 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 354 cv_init(&sc->sc_softwake_cv, "ehciab"); 355 cv_init(&sc->sc_doorbell, "ehcidi"); 356 357 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 358 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 359 360 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 361 ehci_doorbell, sc); 362 KASSERT(sc->sc_doorbell_si != NULL); 363 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 364 ehci_pcd, sc); 365 KASSERT(sc->sc_pcd_si != NULL); 366 367 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 368 369 vers = EREAD2(sc, EHCI_HCIVERSION); 370 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 371 vers >> 8, vers & 0xff); 372 373 sparams = EREAD4(sc, EHCI_HCSPARAMS); 374 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 375 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 376 ncomp = EHCI_HCS_N_CC(sparams); 377 if (ncomp != sc->sc_ncomp) { 378 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 379 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 380 #if NOHCI == 0 || NUHCI == 0 381 aprint_error("%s: ohci or uhci probably not configured\n", 382 device_xname(sc->sc_dev)); 383 #endif 384 if (ncomp < sc->sc_ncomp) 385 sc->sc_ncomp = ncomp; 386 } 387 if (sc->sc_ncomp > 0) { 388 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 389 aprint_normal("%s: companion controller%s, %d port%s each:", 390 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 391 EHCI_HCS_N_PCC(sparams), 392 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 393 for (i = 0; i < sc->sc_ncomp; i++) 394 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 395 aprint_normal("\n"); 396 } 397 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 398 cparams = EREAD4(sc, EHCI_HCCPARAMS); 399 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 400 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 401 402 if (EHCI_HCC_64BIT(cparams)) { 403 /* MUST clear segment register if 64 bit capable. */ 404 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 405 } 406 407 sc->sc_bus.usbrev = USBREV_2_0; 408 409 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 410 USB_MEM_RESERVE); 411 412 /* Reset the controller */ 413 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 414 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 415 usb_delay_ms(&sc->sc_bus, 1); 416 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 417 for (i = 0; i < 100; i++) { 418 usb_delay_ms(&sc->sc_bus, 1); 419 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 420 if (!hcr) 421 break; 422 } 423 if (hcr) { 424 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 425 return (USBD_IOERROR); 426 } 427 if (sc->sc_vendor_init) 428 sc->sc_vendor_init(sc); 429 430 /* 431 * If we are doing embedded transaction translation function, force 432 * the controller to host mode. 433 */ 434 if (sc->sc_flags & EHCIF_ETTF) { 435 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 436 usbmode &= ~EHCI_USBMODE_CM; 437 usbmode |= EHCI_USBMODE_CM_HOST; 438 EWRITE4(sc, EHCI_USBMODE, usbmode); 439 } 440 441 /* XXX need proper intr scheduling */ 442 sc->sc_rand = 96; 443 444 /* frame list size at default, read back what we got and use that */ 445 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 446 case 0: sc->sc_flsize = 1024; break; 447 case 1: sc->sc_flsize = 512; break; 448 case 2: sc->sc_flsize = 256; break; 449 case 3: return (USBD_IOERROR); 450 } 451 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 452 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 453 if (err) 454 return (err); 455 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 456 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 457 458 for (i = 0; i < sc->sc_flsize; i++) { 459 sc->sc_flist[i] = EHCI_NULL; 460 } 461 462 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 463 464 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 465 KM_SLEEP); 466 if (sc->sc_softitds == NULL) 467 return ENOMEM; 468 LIST_INIT(&sc->sc_freeitds); 469 TAILQ_INIT(&sc->sc_intrhead); 470 471 /* Set up the bus struct. */ 472 sc->sc_bus.methods = &ehci_bus_methods; 473 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 474 475 sc->sc_eintrs = EHCI_NORMAL_INTRS; 476 477 /* 478 * Allocate the interrupt dummy QHs. These are arranged to give poll 479 * intervals that are powers of 2 times 1ms. 480 */ 481 for (i = 0; i < EHCI_INTRQHS; i++) { 482 sqh = ehci_alloc_sqh(sc); 483 if (sqh == NULL) { 484 err = USBD_NOMEM; 485 goto bad1; 486 } 487 sc->sc_islots[i].sqh = sqh; 488 } 489 for (i = 0; i < EHCI_INTRQHS; i++) { 490 sqh = sc->sc_islots[i].sqh; 491 if (i == 0) { 492 /* The last (1ms) QH terminates. */ 493 sqh->qh.qh_link = EHCI_NULL; 494 sqh->next = NULL; 495 } else { 496 /* Otherwise the next QH has half the poll interval */ 497 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 498 sqh->qh.qh_link = htole32(sqh->next->physaddr | 499 EHCI_LINK_QH); 500 } 501 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 502 sqh->qh.qh_curqtd = EHCI_NULL; 503 sqh->next = NULL; 504 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 505 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 506 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 507 sqh->sqtd = NULL; 508 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 509 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 510 } 511 /* Point the frame list at the last level (128ms). */ 512 for (i = 0; i < sc->sc_flsize; i++) { 513 int j; 514 515 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 516 revbits[i & (EHCI_MAX_POLLRATE-1)]; 517 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 518 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 519 i)].sqh->physaddr); 520 } 521 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 522 BUS_DMASYNC_PREWRITE); 523 524 /* Allocate dummy QH that starts the async list. */ 525 sqh = ehci_alloc_sqh(sc); 526 if (sqh == NULL) { 527 err = USBD_NOMEM; 528 goto bad1; 529 } 530 /* Fill the QH */ 531 sqh->qh.qh_endp = 532 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 533 sqh->qh.qh_link = 534 htole32(sqh->physaddr | EHCI_LINK_QH); 535 sqh->qh.qh_curqtd = EHCI_NULL; 536 sqh->next = NULL; 537 /* Fill the overlay qTD */ 538 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 539 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 540 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 541 sqh->sqtd = NULL; 542 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 543 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 544 #ifdef EHCI_DEBUG 545 if (ehcidebug) { 546 ehci_dump_sqh(sqh); 547 } 548 #endif 549 550 /* Point to async list */ 551 sc->sc_async_head = sqh; 552 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 553 554 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 555 556 /* Turn on controller */ 557 EOWRITE4(sc, EHCI_USBCMD, 558 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 559 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 560 EHCI_CMD_ASE | 561 EHCI_CMD_PSE | 562 EHCI_CMD_RS); 563 564 /* Take over port ownership */ 565 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 566 567 for (i = 0; i < 100; i++) { 568 usb_delay_ms(&sc->sc_bus, 1); 569 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 570 if (!hcr) 571 break; 572 } 573 if (hcr) { 574 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 575 return (USBD_IOERROR); 576 } 577 578 /* Enable interrupts */ 579 DPRINTFN(1,("ehci_init: enabling\n")); 580 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 581 582 return (USBD_NORMAL_COMPLETION); 583 584 #if 0 585 bad2: 586 ehci_free_sqh(sc, sc->sc_async_head); 587 #endif 588 bad1: 589 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 590 return (err); 591 } 592 593 int 594 ehci_intr(void *v) 595 { 596 ehci_softc_t *sc = v; 597 int ret = 0; 598 599 if (sc == NULL) 600 return 0; 601 602 mutex_spin_enter(&sc->sc_intr_lock); 603 604 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 605 goto done; 606 607 /* If we get an interrupt while polling, then just ignore it. */ 608 if (sc->sc_bus.use_polling) { 609 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 610 611 if (intrs) 612 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 613 #ifdef DIAGNOSTIC 614 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 615 #endif 616 goto done; 617 } 618 619 ret = ehci_intr1(sc); 620 621 done: 622 mutex_spin_exit(&sc->sc_intr_lock); 623 return ret; 624 } 625 626 Static int 627 ehci_intr1(ehci_softc_t *sc) 628 { 629 u_int32_t intrs, eintrs; 630 631 DPRINTFN(20,("ehci_intr1: enter\n")); 632 633 /* In case the interrupt occurs before initialization has completed. */ 634 if (sc == NULL) { 635 #ifdef DIAGNOSTIC 636 printf("ehci_intr1: sc == NULL\n"); 637 #endif 638 return (0); 639 } 640 641 KASSERT(mutex_owned(&sc->sc_intr_lock)); 642 643 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 644 if (!intrs) 645 return (0); 646 647 eintrs = intrs & sc->sc_eintrs; 648 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 649 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 650 (u_int)eintrs)); 651 if (!eintrs) 652 return (0); 653 654 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 655 sc->sc_bus.no_intrs++; 656 if (eintrs & EHCI_STS_IAA) { 657 DPRINTF(("ehci_intr1: door bell\n")); 658 kpreempt_disable(); 659 KASSERT(sc->sc_doorbell_si != NULL); 660 softint_schedule(sc->sc_doorbell_si); 661 kpreempt_enable(); 662 eintrs &= ~EHCI_STS_IAA; 663 } 664 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 665 DPRINTFN(5,("ehci_intr1: %s %s\n", 666 eintrs & EHCI_STS_INT ? "INT" : "", 667 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 668 usb_schedsoftintr(&sc->sc_bus); 669 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 670 } 671 if (eintrs & EHCI_STS_HSE) { 672 printf("%s: unrecoverable error, controller halted\n", 673 device_xname(sc->sc_dev)); 674 /* XXX what else */ 675 } 676 if (eintrs & EHCI_STS_PCD) { 677 kpreempt_disable(); 678 KASSERT(sc->sc_pcd_si != NULL); 679 softint_schedule(sc->sc_pcd_si); 680 kpreempt_enable(); 681 eintrs &= ~EHCI_STS_PCD; 682 } 683 684 if (eintrs != 0) { 685 /* Block unprocessed interrupts. */ 686 sc->sc_eintrs &= ~eintrs; 687 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 688 printf("%s: blocking intrs 0x%x\n", 689 device_xname(sc->sc_dev), eintrs); 690 } 691 692 return (1); 693 } 694 695 Static void 696 ehci_doorbell(void *addr) 697 { 698 ehci_softc_t *sc = addr; 699 700 mutex_enter(&sc->sc_lock); 701 cv_broadcast(&sc->sc_doorbell); 702 mutex_exit(&sc->sc_lock); 703 } 704 705 Static void 706 ehci_pcd(void *addr) 707 { 708 ehci_softc_t *sc = addr; 709 usbd_xfer_handle xfer; 710 u_char *p; 711 int i, m; 712 713 mutex_enter(&sc->sc_lock); 714 xfer = sc->sc_intrxfer; 715 716 if (xfer == NULL) { 717 /* Just ignore the change. */ 718 goto done; 719 } 720 721 p = KERNADDR(&xfer->dmabuf, 0); 722 m = min(sc->sc_noport, xfer->length * 8 - 1); 723 memset(p, 0, xfer->length); 724 for (i = 1; i <= m; i++) { 725 /* Pick out CHANGE bits from the status reg. */ 726 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 727 p[i/8] |= 1 << (i%8); 728 } 729 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 730 xfer->actlen = xfer->length; 731 xfer->status = USBD_NORMAL_COMPLETION; 732 733 usb_transfer_complete(xfer); 734 735 done: 736 mutex_exit(&sc->sc_lock); 737 } 738 739 Static void 740 ehci_softintr(void *v) 741 { 742 struct usbd_bus *bus = v; 743 ehci_softc_t *sc = bus->hci_private; 744 struct ehci_xfer *ex, *nextex; 745 746 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 747 748 DPRINTFN(10,("%s: ehci_softintr\n", device_xname(sc->sc_dev))); 749 750 /* 751 * The only explanation I can think of for why EHCI is as brain dead 752 * as UHCI interrupt-wise is that Intel was involved in both. 753 * An interrupt just tells us that something is done, we have no 754 * clue what, so we need to scan through all active transfers. :-( 755 */ 756 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 757 nextex = TAILQ_NEXT(ex, inext); 758 ehci_check_intr(sc, ex); 759 } 760 761 /* Schedule a callout to catch any dropped transactions. */ 762 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 763 !TAILQ_EMPTY(&sc->sc_intrhead)) 764 callout_reset(&sc->sc_tmo_intrlist, 765 hz, ehci_intrlist_timeout, sc); 766 767 if (sc->sc_softwake) { 768 sc->sc_softwake = 0; 769 cv_broadcast(&sc->sc_softwake_cv); 770 } 771 } 772 773 /* Check for an interrupt. */ 774 Static void 775 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 776 { 777 int attr; 778 779 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 780 781 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 782 783 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 784 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 785 ehci_check_itd_intr(sc, ex); 786 else 787 ehci_check_qh_intr(sc, ex); 788 789 return; 790 } 791 792 Static void 793 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 794 { 795 ehci_soft_qtd_t *sqtd, *lsqtd; 796 __uint32_t status; 797 798 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 799 800 if (ex->sqtdstart == NULL) { 801 printf("ehci_check_qh_intr: not valid sqtd\n"); 802 return; 803 } 804 805 lsqtd = ex->sqtdend; 806 #ifdef DIAGNOSTIC 807 if (lsqtd == NULL) { 808 printf("ehci_check_qh_intr: lsqtd==0\n"); 809 return; 810 } 811 #endif 812 /* 813 * If the last TD is still active we need to check whether there 814 * is an error somewhere in the middle, or whether there was a 815 * short packet (SPD and not ACTIVE). 816 */ 817 usb_syncmem(&lsqtd->dma, 818 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 819 sizeof(lsqtd->qtd.qtd_status), 820 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 821 status = le32toh(lsqtd->qtd.qtd_status); 822 usb_syncmem(&lsqtd->dma, 823 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 824 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 825 if (status & EHCI_QTD_ACTIVE) { 826 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 827 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 828 usb_syncmem(&sqtd->dma, 829 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 830 sizeof(sqtd->qtd.qtd_status), 831 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 832 status = le32toh(sqtd->qtd.qtd_status); 833 usb_syncmem(&sqtd->dma, 834 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 835 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 836 /* If there's an active QTD the xfer isn't done. */ 837 if (status & EHCI_QTD_ACTIVE) 838 break; 839 /* Any kind of error makes the xfer done. */ 840 if (status & EHCI_QTD_HALTED) 841 goto done; 842 /* We want short packets, and it is short: it's done */ 843 if (EHCI_QTD_GET_BYTES(status) != 0) 844 goto done; 845 } 846 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 847 ex, ex->sqtdstart)); 848 return; 849 } 850 done: 851 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 852 callout_stop(&ex->xfer.timeout_handle); 853 ehci_idone(ex); 854 } 855 856 Static void 857 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 858 { 859 ehci_soft_itd_t *itd; 860 int i; 861 862 KASSERT(mutex_owned(&sc->sc_lock)); 863 864 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 865 return; 866 867 if (ex->itdstart == NULL) { 868 printf("ehci_check_itd_intr: not valid itd\n"); 869 return; 870 } 871 872 itd = ex->itdend; 873 #ifdef DIAGNOSTIC 874 if (itd == NULL) { 875 printf("ehci_check_itd_intr: itdend == 0\n"); 876 return; 877 } 878 #endif 879 880 /* 881 * check no active transfers in last itd, meaning we're finished 882 */ 883 884 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 885 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 886 BUS_DMASYNC_POSTREAD); 887 888 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 889 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 890 break; 891 } 892 893 if (i == EHCI_ITD_NUFRAMES) { 894 goto done; /* All 8 descriptors inactive, it's done */ 895 } 896 897 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 898 ex->itdstart)); 899 return; 900 done: 901 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 902 callout_stop(&ex->xfer.timeout_handle); 903 ehci_idone(ex); 904 } 905 906 Static void 907 ehci_idone(struct ehci_xfer *ex) 908 { 909 usbd_xfer_handle xfer = &ex->xfer; 910 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 911 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 912 ehci_soft_qtd_t *sqtd, *lsqtd; 913 u_int32_t status = 0, nstatus = 0; 914 int actlen; 915 916 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 917 918 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 919 920 #ifdef DIAGNOSTIC 921 if (ex->isdone) { 922 printf("ehci_idone: ex=%p is done!\n", ex); 923 #ifdef EHCI_DEBUG 924 ehci_dump_exfer(ex); 925 #endif 926 return; 927 } 928 ex->isdone = 1; 929 #endif 930 931 if (xfer->status == USBD_CANCELLED || 932 xfer->status == USBD_TIMEOUT) { 933 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 934 return; 935 } 936 937 #ifdef EHCI_DEBUG 938 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 939 if (ehcidebug > 10) 940 ehci_dump_sqtds(ex->sqtdstart); 941 #endif 942 943 /* The transfer is done, compute actual length and status. */ 944 945 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 946 == UE_ISOCHRONOUS) { 947 /* Isoc transfer */ 948 struct ehci_soft_itd *itd; 949 int i, nframes, len, uframes; 950 951 nframes = 0; 952 actlen = 0; 953 954 i = xfer->pipe->endpoint->edesc->bInterval; 955 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 956 957 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 958 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 959 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 960 BUS_DMASYNC_POSTREAD); 961 962 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 963 /* XXX - driver didn't fill in the frame full 964 * of uframes. This leads to scheduling 965 * inefficiencies, but working around 966 * this doubles complexity of tracking 967 * an xfer. 968 */ 969 if (nframes >= xfer->nframes) 970 break; 971 972 status = le32toh(itd->itd.itd_ctl[i]); 973 len = EHCI_ITD_GET_LEN(status); 974 if (EHCI_ITD_GET_STATUS(status) != 0) 975 len = 0; /*No valid data on error*/ 976 977 xfer->frlengths[nframes++] = len; 978 actlen += len; 979 } 980 981 if (nframes >= xfer->nframes) 982 break; 983 } 984 985 xfer->actlen = actlen; 986 xfer->status = USBD_NORMAL_COMPLETION; 987 goto end; 988 } 989 990 /* Continue processing xfers using queue heads */ 991 992 lsqtd = ex->sqtdend; 993 actlen = 0; 994 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 995 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 996 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 997 nstatus = le32toh(sqtd->qtd.qtd_status); 998 if (nstatus & EHCI_QTD_ACTIVE) 999 break; 1000 1001 status = nstatus; 1002 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1003 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1004 } 1005 1006 1007 /* 1008 * If there are left over TDs we need to update the toggle. 1009 * The default pipe doesn't need it since control transfers 1010 * start the toggle at 0 every time. 1011 * For a short transfer we need to update the toggle for the missing 1012 * packets within the qTD. 1013 */ 1014 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1015 xfer->pipe->device->default_pipe != xfer->pipe) { 1016 DPRINTFN(2, ("ehci_idone: need toggle update " 1017 "status=%08x nstatus=%08x\n", status, nstatus)); 1018 #if 0 1019 ehci_dump_sqh(epipe->sqh); 1020 ehci_dump_sqtds(ex->sqtdstart); 1021 #endif 1022 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1023 } 1024 1025 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 1026 xfer->length, actlen, status)); 1027 xfer->actlen = actlen; 1028 if (status & EHCI_QTD_HALTED) { 1029 #ifdef EHCI_DEBUG 1030 char sbuf[128]; 1031 1032 snprintb(sbuf, sizeof(sbuf), 1033 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR\3MISSED\1PINGSTATE", 1034 (u_int32_t)status); 1035 1036 DPRINTFN(2, ("ehci_idone: error, addr=%d, endpt=0x%02x, " 1037 "status 0x%s\n", 1038 xfer->pipe->device->address, 1039 xfer->pipe->endpoint->edesc->bEndpointAddress, 1040 sbuf)); 1041 if (ehcidebug > 2) { 1042 ehci_dump_sqh(epipe->sqh); 1043 ehci_dump_sqtds(ex->sqtdstart); 1044 } 1045 #endif 1046 /* low&full speed has an extra error flag */ 1047 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1048 EHCI_QH_SPEED_HIGH) 1049 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1050 else 1051 status &= EHCI_QTD_STATERRS; 1052 if (status == 0) /* no other errors means a stall */ { 1053 xfer->status = USBD_STALLED; 1054 } else { 1055 xfer->status = USBD_IOERROR; /* more info XXX */ 1056 } 1057 /* XXX need to reset TT on missed microframe */ 1058 if (status & EHCI_QTD_MISSEDMICRO) { 1059 printf("%s: missed microframe, TT reset not " 1060 "implemented, hub might be inoperational\n", 1061 device_xname(sc->sc_dev)); 1062 } 1063 } else { 1064 xfer->status = USBD_NORMAL_COMPLETION; 1065 } 1066 1067 end: 1068 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1069 * during this call, before methods->done is called: dma sync required 1070 * beforehand? */ 1071 usb_transfer_complete(xfer); 1072 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1073 } 1074 1075 /* 1076 * Wait here until controller claims to have an interrupt. 1077 * Then call ehci_intr and return. Use timeout to avoid waiting 1078 * too long. 1079 */ 1080 Static void 1081 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1082 { 1083 int timo; 1084 u_int32_t intrs; 1085 1086 xfer->status = USBD_IN_PROGRESS; 1087 for (timo = xfer->timeout; timo >= 0; timo--) { 1088 usb_delay_ms(&sc->sc_bus, 1); 1089 if (sc->sc_dying) 1090 break; 1091 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1092 sc->sc_eintrs; 1093 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1094 #ifdef EHCI_DEBUG 1095 if (ehcidebug > 15) 1096 ehci_dump_regs(sc); 1097 #endif 1098 if (intrs) { 1099 mutex_spin_enter(&sc->sc_intr_lock); 1100 ehci_intr1(sc); 1101 mutex_spin_exit(&sc->sc_intr_lock); 1102 if (xfer->status != USBD_IN_PROGRESS) 1103 return; 1104 } 1105 } 1106 1107 /* Timeout */ 1108 DPRINTF(("ehci_waitintr: timeout\n")); 1109 xfer->status = USBD_TIMEOUT; 1110 mutex_enter(&sc->sc_lock); 1111 usb_transfer_complete(xfer); 1112 mutex_exit(&sc->sc_lock); 1113 /* XXX should free TD */ 1114 } 1115 1116 Static void 1117 ehci_poll(struct usbd_bus *bus) 1118 { 1119 ehci_softc_t *sc = bus->hci_private; 1120 #ifdef EHCI_DEBUG 1121 static int last; 1122 int new; 1123 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1124 if (new != last) { 1125 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1126 last = new; 1127 } 1128 #endif 1129 1130 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1131 mutex_spin_enter(&sc->sc_intr_lock); 1132 ehci_intr1(sc); 1133 mutex_spin_exit(&sc->sc_intr_lock); 1134 } 1135 } 1136 1137 void 1138 ehci_childdet(device_t self, device_t child) 1139 { 1140 struct ehci_softc *sc = device_private(self); 1141 1142 KASSERT(sc->sc_child == child); 1143 sc->sc_child = NULL; 1144 } 1145 1146 int 1147 ehci_detach(struct ehci_softc *sc, int flags) 1148 { 1149 int rv = 0; 1150 1151 if (sc->sc_child != NULL) 1152 rv = config_detach(sc->sc_child, flags); 1153 1154 if (rv != 0) 1155 return (rv); 1156 1157 callout_halt(&sc->sc_tmo_intrlist, NULL); 1158 callout_destroy(&sc->sc_tmo_intrlist); 1159 1160 /* XXX free other data structures XXX */ 1161 if (sc->sc_softitds) 1162 kmem_free(sc->sc_softitds, 1163 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1164 cv_destroy(&sc->sc_doorbell); 1165 cv_destroy(&sc->sc_softwake_cv); 1166 1167 #if 0 1168 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1169 1170 softint_disestablish(sc->sc_doorbell_si); 1171 softint_disestablish(sc->sc_pcd_si); 1172 1173 mutex_destroy(&sc->sc_lock); 1174 mutex_destroy(&sc->sc_intr_lock); 1175 #endif 1176 1177 pool_cache_destroy(sc->sc_xferpool); 1178 1179 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1180 1181 return (rv); 1182 } 1183 1184 1185 int 1186 ehci_activate(device_t self, enum devact act) 1187 { 1188 struct ehci_softc *sc = device_private(self); 1189 1190 switch (act) { 1191 case DVACT_DEACTIVATE: 1192 sc->sc_dying = 1; 1193 return 0; 1194 default: 1195 return EOPNOTSUPP; 1196 } 1197 } 1198 1199 /* 1200 * Handle suspend/resume. 1201 * 1202 * We need to switch to polling mode here, because this routine is 1203 * called from an interrupt context. This is all right since we 1204 * are almost suspended anyway. 1205 * 1206 * Note that this power handler isn't to be registered directly; the 1207 * bus glue needs to call out to it. 1208 */ 1209 bool 1210 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1211 { 1212 ehci_softc_t *sc = device_private(dv); 1213 int i; 1214 uint32_t cmd, hcr; 1215 1216 mutex_spin_enter(&sc->sc_intr_lock); 1217 sc->sc_bus.use_polling++; 1218 mutex_spin_exit(&sc->sc_intr_lock); 1219 1220 for (i = 1; i <= sc->sc_noport; i++) { 1221 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1222 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1223 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1224 } 1225 1226 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1227 1228 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1229 EOWRITE4(sc, EHCI_USBCMD, cmd); 1230 1231 for (i = 0; i < 100; i++) { 1232 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1233 if (hcr == 0) 1234 break; 1235 1236 usb_delay_ms(&sc->sc_bus, 1); 1237 } 1238 if (hcr != 0) 1239 printf("%s: reset timeout\n", device_xname(dv)); 1240 1241 cmd &= ~EHCI_CMD_RS; 1242 EOWRITE4(sc, EHCI_USBCMD, cmd); 1243 1244 for (i = 0; i < 100; i++) { 1245 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1246 if (hcr == EHCI_STS_HCH) 1247 break; 1248 1249 usb_delay_ms(&sc->sc_bus, 1); 1250 } 1251 if (hcr != EHCI_STS_HCH) 1252 printf("%s: config timeout\n", device_xname(dv)); 1253 1254 mutex_spin_enter(&sc->sc_intr_lock); 1255 sc->sc_bus.use_polling--; 1256 mutex_spin_exit(&sc->sc_intr_lock); 1257 1258 return true; 1259 } 1260 1261 bool 1262 ehci_resume(device_t dv, const pmf_qual_t *qual) 1263 { 1264 ehci_softc_t *sc = device_private(dv); 1265 int i; 1266 uint32_t cmd, hcr; 1267 1268 /* restore things in case the bios sucks */ 1269 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1270 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1271 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1272 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1273 1274 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1275 1276 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1277 1278 hcr = 0; 1279 for (i = 1; i <= sc->sc_noport; i++) { 1280 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1281 if ((cmd & EHCI_PS_PO) == 0 && 1282 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1283 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1284 hcr = 1; 1285 } 1286 } 1287 1288 if (hcr) { 1289 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1290 1291 for (i = 1; i <= sc->sc_noport; i++) { 1292 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1293 if ((cmd & EHCI_PS_PO) == 0 && 1294 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1295 EOWRITE4(sc, EHCI_PORTSC(i), 1296 cmd & ~EHCI_PS_FPR); 1297 } 1298 } 1299 1300 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1301 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1302 1303 for (i = 0; i < 100; i++) { 1304 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1305 if (hcr != EHCI_STS_HCH) 1306 break; 1307 1308 usb_delay_ms(&sc->sc_bus, 1); 1309 } 1310 if (hcr == EHCI_STS_HCH) 1311 printf("%s: config timeout\n", device_xname(dv)); 1312 1313 return true; 1314 } 1315 1316 /* 1317 * Shut down the controller when the system is going down. 1318 */ 1319 bool 1320 ehci_shutdown(device_t self, int flags) 1321 { 1322 ehci_softc_t *sc = device_private(self); 1323 1324 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1325 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1326 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1327 return true; 1328 } 1329 1330 Static usbd_status 1331 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1332 { 1333 struct ehci_softc *sc = bus->hci_private; 1334 usbd_status err; 1335 1336 err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, USBMALLOC_MULTISEG); 1337 #ifdef EHCI_DEBUG 1338 if (err) 1339 printf("ehci_allocm: usb_allocmem_flags()= %s (%d)\n", 1340 usbd_errstr(err), err); 1341 #endif 1342 if (err == USBD_NOMEM) 1343 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1344 #ifdef EHCI_DEBUG 1345 if (err) 1346 printf("ehci_allocm: usb_reserve_allocm()= %s (%d)\n", 1347 usbd_errstr(err), err); 1348 #endif 1349 return (err); 1350 } 1351 1352 Static void 1353 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1354 { 1355 struct ehci_softc *sc = bus->hci_private; 1356 1357 if (dma->block->flags & USB_DMA_RESERVE) { 1358 usb_reserve_freem(&sc->sc_dma_reserve, 1359 dma); 1360 return; 1361 } 1362 usb_freemem(&sc->sc_bus, dma); 1363 } 1364 1365 Static usbd_xfer_handle 1366 ehci_allocx(struct usbd_bus *bus) 1367 { 1368 struct ehci_softc *sc = bus->hci_private; 1369 usbd_xfer_handle xfer; 1370 1371 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1372 if (xfer != NULL) { 1373 memset(xfer, 0, sizeof(struct ehci_xfer)); 1374 #ifdef DIAGNOSTIC 1375 EXFER(xfer)->isdone = 1; 1376 xfer->busy_free = XFER_BUSY; 1377 #endif 1378 } 1379 return (xfer); 1380 } 1381 1382 Static void 1383 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1384 { 1385 struct ehci_softc *sc = bus->hci_private; 1386 1387 #ifdef DIAGNOSTIC 1388 if (xfer->busy_free != XFER_BUSY) { 1389 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1390 xfer->busy_free); 1391 } 1392 xfer->busy_free = XFER_FREE; 1393 if (!EXFER(xfer)->isdone) { 1394 printf("ehci_freex: !isdone\n"); 1395 } 1396 #endif 1397 pool_cache_put(sc->sc_xferpool, xfer); 1398 } 1399 1400 Static void 1401 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1402 { 1403 struct ehci_softc *sc = bus->hci_private; 1404 1405 *lock = &sc->sc_lock; 1406 } 1407 1408 Static void 1409 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1410 { 1411 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1412 1413 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1414 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1415 #ifdef EHCI_DEBUG 1416 if (ehcidebug) 1417 usbd_dump_pipe(pipe); 1418 #endif 1419 epipe->nexttoggle = 0; 1420 } 1421 1422 Static void 1423 ehci_noop(usbd_pipe_handle pipe) 1424 { 1425 } 1426 1427 #ifdef EHCI_DEBUG 1428 Static void 1429 ehci_dump_regs(ehci_softc_t *sc) 1430 { 1431 int i; 1432 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1433 EOREAD4(sc, EHCI_USBCMD), 1434 EOREAD4(sc, EHCI_USBSTS), 1435 EOREAD4(sc, EHCI_USBINTR)); 1436 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1437 EOREAD4(sc, EHCI_FRINDEX), 1438 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1439 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1440 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1441 for (i = 1; i <= sc->sc_noport; i++) 1442 printf("port %d status=0x%08x\n", i, 1443 EOREAD4(sc, EHCI_PORTSC(i))); 1444 } 1445 1446 /* 1447 * Unused function - this is meant to be called from a kernel 1448 * debugger. 1449 */ 1450 void 1451 ehci_dump(void) 1452 { 1453 ehci_dump_regs(theehci); 1454 } 1455 1456 Static void 1457 ehci_dump_link(ehci_link_t link, int type) 1458 { 1459 link = le32toh(link); 1460 printf("0x%08x", link); 1461 if (link & EHCI_LINK_TERMINATE) 1462 printf("<T>"); 1463 else { 1464 printf("<"); 1465 if (type) { 1466 switch (EHCI_LINK_TYPE(link)) { 1467 case EHCI_LINK_ITD: printf("ITD"); break; 1468 case EHCI_LINK_QH: printf("QH"); break; 1469 case EHCI_LINK_SITD: printf("SITD"); break; 1470 case EHCI_LINK_FSTN: printf("FSTN"); break; 1471 } 1472 } 1473 printf(">"); 1474 } 1475 } 1476 1477 Static void 1478 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1479 { 1480 int i; 1481 u_int32_t stop; 1482 1483 stop = 0; 1484 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1485 ehci_dump_sqtd(sqtd); 1486 usb_syncmem(&sqtd->dma, 1487 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1488 sizeof(sqtd->qtd), 1489 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1490 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1491 usb_syncmem(&sqtd->dma, 1492 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1493 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1494 } 1495 if (sqtd) 1496 printf("dump aborted, too many TDs\n"); 1497 } 1498 1499 Static void 1500 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1501 { 1502 usb_syncmem(&sqtd->dma, sqtd->offs, 1503 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1504 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1505 ehci_dump_qtd(&sqtd->qtd); 1506 usb_syncmem(&sqtd->dma, sqtd->offs, 1507 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1508 } 1509 1510 Static void 1511 ehci_dump_qtd(ehci_qtd_t *qtd) 1512 { 1513 u_int32_t s; 1514 char sbuf[128]; 1515 1516 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1517 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1518 printf("\n"); 1519 s = le32toh(qtd->qtd_status); 1520 snprintb(sbuf, sizeof(sbuf), 1521 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1522 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1523 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1524 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1525 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1526 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s), 1527 EHCI_QTD_GET_PID(s), sbuf); 1528 for (s = 0; s < 5; s++) 1529 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1530 } 1531 1532 Static void 1533 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1534 { 1535 ehci_qh_t *qh = &sqh->qh; 1536 u_int32_t endp, endphub; 1537 1538 usb_syncmem(&sqh->dma, sqh->offs, 1539 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1540 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1541 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1542 endp = le32toh(qh->qh_endp); 1543 printf(" endp=0x%08x\n", endp); 1544 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1545 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1546 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1547 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1548 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1549 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1550 EHCI_QH_GET_NRL(endp)); 1551 endphub = le32toh(qh->qh_endphub); 1552 printf(" endphub=0x%08x\n", endphub); 1553 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1554 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1555 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1556 EHCI_QH_GET_MULT(endphub)); 1557 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1558 printf("Overlay qTD:\n"); 1559 ehci_dump_qtd(&qh->qh_qtd); 1560 usb_syncmem(&sqh->dma, sqh->offs, 1561 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1562 } 1563 1564 #if notyet 1565 Static void 1566 ehci_dump_itd(struct ehci_soft_itd *itd) 1567 { 1568 ehci_isoc_trans_t t; 1569 ehci_isoc_bufr_ptr_t b, b2, b3; 1570 int i; 1571 1572 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1573 1574 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1575 t = le32toh(itd->itd.itd_ctl[i]); 1576 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1577 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1578 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1579 EHCI_ITD_GET_OFFS(t)); 1580 } 1581 printf("ITDbufr: "); 1582 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1583 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1584 1585 b = le32toh(itd->itd.itd_bufr[0]); 1586 b2 = le32toh(itd->itd.itd_bufr[1]); 1587 b3 = le32toh(itd->itd.itd_bufr[2]); 1588 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1589 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1590 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1591 } 1592 1593 Static void 1594 ehci_dump_sitd(struct ehci_soft_itd *itd) 1595 { 1596 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1597 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1598 itd->xfer_next, itd->physaddr, itd->slot); 1599 } 1600 #endif 1601 1602 #ifdef DIAGNOSTIC 1603 Static void 1604 ehci_dump_exfer(struct ehci_xfer *ex) 1605 { 1606 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1607 } 1608 #endif 1609 #endif 1610 1611 Static usbd_status 1612 ehci_open(usbd_pipe_handle pipe) 1613 { 1614 usbd_device_handle dev = pipe->device; 1615 ehci_softc_t *sc = dev->bus->hci_private; 1616 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1617 u_int8_t addr = dev->address; 1618 u_int8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1619 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1620 ehci_soft_qh_t *sqh; 1621 usbd_status err; 1622 int ival, speed, naks; 1623 int hshubaddr, hshubport; 1624 1625 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1626 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1627 1628 if (dev->myhsport) { 1629 /* 1630 * When directly attached FS/LS device while doing embedded 1631 * transaction translations and we are the hub, set the hub 1632 * address to 0 (us). 1633 */ 1634 if (!(sc->sc_flags & EHCIF_ETTF) 1635 || (dev->myhsport->parent->address != sc->sc_addr)) { 1636 hshubaddr = dev->myhsport->parent->address; 1637 } else { 1638 hshubaddr = 0; 1639 } 1640 hshubport = dev->myhsport->portno; 1641 } else { 1642 hshubaddr = 0; 1643 hshubport = 0; 1644 } 1645 1646 if (sc->sc_dying) 1647 return (USBD_IOERROR); 1648 1649 /* toggle state needed for bulk endpoints */ 1650 epipe->nexttoggle = pipe->endpoint->datatoggle; 1651 1652 if (addr == sc->sc_addr) { 1653 switch (ed->bEndpointAddress) { 1654 case USB_CONTROL_ENDPOINT: 1655 pipe->methods = &ehci_root_ctrl_methods; 1656 break; 1657 case UE_DIR_IN | EHCI_INTR_ENDPT: 1658 pipe->methods = &ehci_root_intr_methods; 1659 break; 1660 default: 1661 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1662 ed->bEndpointAddress)); 1663 return (USBD_INVAL); 1664 } 1665 return (USBD_NORMAL_COMPLETION); 1666 } 1667 1668 /* XXX All this stuff is only valid for async. */ 1669 switch (dev->speed) { 1670 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1671 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1672 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1673 default: panic("ehci_open: bad device speed %d", dev->speed); 1674 } 1675 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1676 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1677 "isoc endpoint.\n"); 1678 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1679 "attached to a USB2 hub, and transaction translations are " 1680 "not yet supported.\n"); 1681 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1682 "root hub instead.\n"); 1683 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1684 hshubaddr, hshubport)); 1685 return USBD_INVAL; 1686 } 1687 1688 /* 1689 * For interrupt transfer, nak throttling must be disabled, but for 1690 * the other transfer type, nak throttling should be enabled from the 1691 * viewpoint that avoids the memory thrashing. 1692 */ 1693 naks = (xfertype == UE_INTERRUPT) ? 0 1694 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1695 1696 /* Allocate sqh for everything, save isoc xfers */ 1697 if (xfertype != UE_ISOCHRONOUS) { 1698 sqh = ehci_alloc_sqh(sc); 1699 if (sqh == NULL) 1700 return (USBD_NOMEM); 1701 /* qh_link filled when the QH is added */ 1702 sqh->qh.qh_endp = htole32( 1703 EHCI_QH_SET_ADDR(addr) | 1704 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1705 EHCI_QH_SET_EPS(speed) | 1706 EHCI_QH_DTC | 1707 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1708 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1709 EHCI_QH_CTL : 0) | 1710 EHCI_QH_SET_NRL(naks) 1711 ); 1712 sqh->qh.qh_endphub = htole32( 1713 EHCI_QH_SET_MULT(1) | 1714 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1715 ); 1716 if (speed != EHCI_QH_SPEED_HIGH) 1717 sqh->qh.qh_endphub |= htole32( 1718 EHCI_QH_SET_PORT(hshubport) | 1719 EHCI_QH_SET_HUBA(hshubaddr) | 1720 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1721 ); 1722 sqh->qh.qh_curqtd = EHCI_NULL; 1723 /* Fill the overlay qTD */ 1724 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1725 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1726 sqh->qh.qh_qtd.qtd_status = htole32(0); 1727 1728 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1729 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1730 epipe->sqh = sqh; 1731 } else { 1732 sqh = NULL; 1733 } /*xfertype == UE_ISOC*/ 1734 1735 switch (xfertype) { 1736 case UE_CONTROL: 1737 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1738 0, &epipe->u.ctl.reqdma); 1739 #ifdef EHCI_DEBUG 1740 if (err) 1741 printf("ehci_open: usb_allocmem()=%d\n", err); 1742 #endif 1743 if (err) 1744 goto bad; 1745 pipe->methods = &ehci_device_ctrl_methods; 1746 mutex_enter(&sc->sc_lock); 1747 ehci_add_qh(sc, sqh, sc->sc_async_head); 1748 mutex_exit(&sc->sc_lock); 1749 break; 1750 case UE_BULK: 1751 pipe->methods = &ehci_device_bulk_methods; 1752 mutex_enter(&sc->sc_lock); 1753 ehci_add_qh(sc, sqh, sc->sc_async_head); 1754 mutex_exit(&sc->sc_lock); 1755 break; 1756 case UE_INTERRUPT: 1757 pipe->methods = &ehci_device_intr_methods; 1758 ival = pipe->interval; 1759 if (ival == USBD_DEFAULT_INTERVAL) { 1760 if (speed == EHCI_QH_SPEED_HIGH) { 1761 if (ed->bInterval > 16) { 1762 /* 1763 * illegal with high-speed, but there 1764 * were documentation bugs in the spec, 1765 * so be generous 1766 */ 1767 ival = 256; 1768 } else 1769 ival = (1 << (ed->bInterval - 1)) / 8; 1770 } else 1771 ival = ed->bInterval; 1772 } 1773 err = ehci_device_setintr(sc, sqh, ival); 1774 if (err) 1775 goto bad; 1776 break; 1777 case UE_ISOCHRONOUS: 1778 pipe->methods = &ehci_device_isoc_methods; 1779 if (ed->bInterval == 0 || ed->bInterval > 16) { 1780 printf("ehci: opening pipe with invalid bInterval\n"); 1781 err = USBD_INVAL; 1782 goto bad; 1783 } 1784 if (UGETW(ed->wMaxPacketSize) == 0) { 1785 printf("ehci: zero length endpoint open request\n"); 1786 err = USBD_INVAL; 1787 goto bad; 1788 } 1789 epipe->u.isoc.next_frame = 0; 1790 epipe->u.isoc.cur_xfers = 0; 1791 break; 1792 default: 1793 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1794 err = USBD_INVAL; 1795 goto bad; 1796 } 1797 return (USBD_NORMAL_COMPLETION); 1798 1799 bad: 1800 if (sqh != NULL) 1801 ehci_free_sqh(sc, sqh); 1802 return (err); 1803 } 1804 1805 /* 1806 * Add an ED to the schedule. Called with USB lock held. 1807 */ 1808 Static void 1809 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1810 { 1811 1812 KASSERT(mutex_owned(&sc->sc_lock)); 1813 1814 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1815 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1816 sqh->next = head->next; 1817 sqh->qh.qh_link = head->qh.qh_link; 1818 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1819 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1820 head->next = sqh; 1821 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1822 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1823 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1824 1825 #ifdef EHCI_DEBUG 1826 if (ehcidebug > 5) { 1827 printf("ehci_add_qh:\n"); 1828 ehci_dump_sqh(sqh); 1829 } 1830 #endif 1831 } 1832 1833 /* 1834 * Remove an ED from the schedule. Called with USB lock held. 1835 */ 1836 Static void 1837 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1838 { 1839 ehci_soft_qh_t *p; 1840 1841 KASSERT(mutex_owned(&sc->sc_lock)); 1842 1843 /* XXX */ 1844 for (p = head; p != NULL && p->next != sqh; p = p->next) 1845 ; 1846 if (p == NULL) 1847 panic("ehci_rem_qh: ED not found"); 1848 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1849 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1850 p->next = sqh->next; 1851 p->qh.qh_link = sqh->qh.qh_link; 1852 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1853 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1854 1855 ehci_sync_hc(sc); 1856 } 1857 1858 Static void 1859 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1860 { 1861 int i; 1862 u_int32_t status; 1863 1864 /* Save toggle bit and ping status. */ 1865 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1866 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1867 status = sqh->qh.qh_qtd.qtd_status & 1868 htole32(EHCI_QTD_TOGGLE_MASK | 1869 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1870 /* Set HALTED to make hw leave it alone. */ 1871 sqh->qh.qh_qtd.qtd_status = 1872 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1873 usb_syncmem(&sqh->dma, 1874 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1875 sizeof(sqh->qh.qh_qtd.qtd_status), 1876 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1877 sqh->qh.qh_curqtd = 0; 1878 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1879 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1880 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1881 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1882 sqh->sqtd = sqtd; 1883 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1884 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1885 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1886 sqh->qh.qh_qtd.qtd_status = status; 1887 usb_syncmem(&sqh->dma, 1888 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1889 sizeof(sqh->qh.qh_qtd.qtd_status), 1890 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1891 } 1892 1893 /* 1894 * Ensure that the HC has released all references to the QH. We do this 1895 * by asking for a Async Advance Doorbell interrupt and then we wait for 1896 * the interrupt. 1897 * To make this easier we first obtain exclusive use of the doorbell. 1898 */ 1899 Static void 1900 ehci_sync_hc(ehci_softc_t *sc) 1901 { 1902 int error __diagused; 1903 1904 KASSERT(mutex_owned(&sc->sc_lock)); 1905 1906 if (sc->sc_dying) { 1907 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1908 return; 1909 } 1910 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1911 /* ask for doorbell */ 1912 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1913 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1914 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1915 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 1916 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1917 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1918 #ifdef DIAGNOSTIC 1919 if (error) 1920 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 1921 #endif 1922 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1923 } 1924 1925 Static void 1926 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1927 { 1928 struct ehci_soft_itd *itd, *prev; 1929 1930 prev = NULL; 1931 1932 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1933 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1934 1935 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1936 prev = itd->u.frame_list.prev; 1937 /* Unlink itd from hardware chain, or frame array */ 1938 if (prev == NULL) { /* We're at the table head */ 1939 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1940 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1941 usb_syncmem(&sc->sc_fldma, 1942 sizeof(ehci_link_t) * itd->slot, 1943 sizeof(ehci_link_t), 1944 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1945 1946 if (itd->u.frame_list.next != NULL) 1947 itd->u.frame_list.next->u.frame_list.prev = NULL; 1948 } else { 1949 /* XXX this part is untested... */ 1950 prev->itd.itd_next = itd->itd.itd_next; 1951 usb_syncmem(&itd->dma, 1952 itd->offs + offsetof(ehci_itd_t, itd_next), 1953 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1954 1955 prev->u.frame_list.next = itd->u.frame_list.next; 1956 if (itd->u.frame_list.next != NULL) 1957 itd->u.frame_list.next->u.frame_list.prev = prev; 1958 } 1959 } 1960 1961 prev = NULL; 1962 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1963 if (prev != NULL) 1964 ehci_free_itd(sc, prev); 1965 prev = itd; 1966 } 1967 if (prev) 1968 ehci_free_itd(sc, prev); 1969 exfer->itdstart = NULL; 1970 exfer->itdend = NULL; 1971 } 1972 1973 /***********/ 1974 1975 /* 1976 * Data structures and routines to emulate the root hub. 1977 */ 1978 Static usb_device_descriptor_t ehci_devd = { 1979 USB_DEVICE_DESCRIPTOR_SIZE, 1980 UDESC_DEVICE, /* type */ 1981 {0x00, 0x02}, /* USB version */ 1982 UDCLASS_HUB, /* class */ 1983 UDSUBCLASS_HUB, /* subclass */ 1984 UDPROTO_HSHUBSTT, /* protocol */ 1985 64, /* max packet */ 1986 {0},{0},{0x00,0x01}, /* device id */ 1987 1,2,0, /* string indicies */ 1988 1 /* # of configurations */ 1989 }; 1990 1991 Static const usb_device_qualifier_t ehci_odevd = { 1992 USB_DEVICE_DESCRIPTOR_SIZE, 1993 UDESC_DEVICE_QUALIFIER, /* type */ 1994 {0x00, 0x02}, /* USB version */ 1995 UDCLASS_HUB, /* class */ 1996 UDSUBCLASS_HUB, /* subclass */ 1997 UDPROTO_FSHUB, /* protocol */ 1998 64, /* max packet */ 1999 1, /* # of configurations */ 2000 0 2001 }; 2002 2003 Static const usb_config_descriptor_t ehci_confd = { 2004 USB_CONFIG_DESCRIPTOR_SIZE, 2005 UDESC_CONFIG, 2006 {USB_CONFIG_DESCRIPTOR_SIZE + 2007 USB_INTERFACE_DESCRIPTOR_SIZE + 2008 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2009 1, 2010 1, 2011 0, 2012 UC_ATTR_MBO | UC_SELF_POWERED, 2013 0 /* max power */ 2014 }; 2015 2016 Static const usb_interface_descriptor_t ehci_ifcd = { 2017 USB_INTERFACE_DESCRIPTOR_SIZE, 2018 UDESC_INTERFACE, 2019 0, 2020 0, 2021 1, 2022 UICLASS_HUB, 2023 UISUBCLASS_HUB, 2024 UIPROTO_HSHUBSTT, 2025 0 2026 }; 2027 2028 Static const usb_endpoint_descriptor_t ehci_endpd = { 2029 USB_ENDPOINT_DESCRIPTOR_SIZE, 2030 UDESC_ENDPOINT, 2031 UE_DIR_IN | EHCI_INTR_ENDPT, 2032 UE_INTERRUPT, 2033 {8, 0}, /* max packet */ 2034 12 2035 }; 2036 2037 Static const usb_hub_descriptor_t ehci_hubd = { 2038 USB_HUB_DESCRIPTOR_SIZE, 2039 UDESC_HUB, 2040 0, 2041 {0,0}, 2042 0, 2043 0, 2044 {""}, 2045 {""}, 2046 }; 2047 2048 /* 2049 * Simulate a hardware hub by handling all the necessary requests. 2050 */ 2051 Static usbd_status 2052 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2053 { 2054 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2055 usbd_status err; 2056 2057 /* Insert last in queue. */ 2058 mutex_enter(&sc->sc_lock); 2059 err = usb_insert_transfer(xfer); 2060 mutex_exit(&sc->sc_lock); 2061 if (err) 2062 return (err); 2063 2064 /* Pipe isn't running, start first */ 2065 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2066 } 2067 2068 Static usbd_status 2069 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2070 { 2071 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2072 usb_device_request_t *req; 2073 void *buf = NULL; 2074 int port, i; 2075 int len, value, index, l, totlen = 0; 2076 usb_port_status_t ps; 2077 usb_hub_descriptor_t hubd; 2078 usbd_status err; 2079 u_int32_t v; 2080 2081 if (sc->sc_dying) 2082 return (USBD_IOERROR); 2083 2084 #ifdef DIAGNOSTIC 2085 if (!(xfer->rqflags & URQ_REQUEST)) 2086 /* XXX panic */ 2087 return (USBD_INVAL); 2088 #endif 2089 req = &xfer->request; 2090 2091 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2092 req->bmRequestType, req->bRequest)); 2093 2094 len = UGETW(req->wLength); 2095 value = UGETW(req->wValue); 2096 index = UGETW(req->wIndex); 2097 2098 if (len != 0) 2099 buf = KERNADDR(&xfer->dmabuf, 0); 2100 2101 #define C(x,y) ((x) | ((y) << 8)) 2102 switch(C(req->bRequest, req->bmRequestType)) { 2103 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2104 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2105 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2106 /* 2107 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2108 * for the integrated root hub. 2109 */ 2110 break; 2111 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2112 if (len > 0) { 2113 *(u_int8_t *)buf = sc->sc_conf; 2114 totlen = 1; 2115 } 2116 break; 2117 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2118 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2119 if (len == 0) 2120 break; 2121 switch(value >> 8) { 2122 case UDESC_DEVICE: 2123 if ((value & 0xff) != 0) { 2124 err = USBD_IOERROR; 2125 goto ret; 2126 } 2127 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2128 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2129 memcpy(buf, &ehci_devd, l); 2130 break; 2131 /* 2132 * We can't really operate at another speed, but the spec says 2133 * we need this descriptor. 2134 */ 2135 case UDESC_DEVICE_QUALIFIER: 2136 if ((value & 0xff) != 0) { 2137 err = USBD_IOERROR; 2138 goto ret; 2139 } 2140 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2141 memcpy(buf, &ehci_odevd, l); 2142 break; 2143 /* 2144 * We can't really operate at another speed, but the spec says 2145 * we need this descriptor. 2146 */ 2147 case UDESC_OTHER_SPEED_CONFIGURATION: 2148 case UDESC_CONFIG: 2149 if ((value & 0xff) != 0) { 2150 err = USBD_IOERROR; 2151 goto ret; 2152 } 2153 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2154 memcpy(buf, &ehci_confd, l); 2155 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2156 value >> 8; 2157 buf = (char *)buf + l; 2158 len -= l; 2159 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2160 totlen += l; 2161 memcpy(buf, &ehci_ifcd, l); 2162 buf = (char *)buf + l; 2163 len -= l; 2164 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2165 totlen += l; 2166 memcpy(buf, &ehci_endpd, l); 2167 break; 2168 case UDESC_STRING: 2169 #define sd ((usb_string_descriptor_t *)buf) 2170 switch (value & 0xff) { 2171 case 0: /* Language table */ 2172 totlen = usb_makelangtbl(sd, len); 2173 break; 2174 case 1: /* Vendor */ 2175 totlen = usb_makestrdesc(sd, len, 2176 sc->sc_vendor); 2177 break; 2178 case 2: /* Product */ 2179 totlen = usb_makestrdesc(sd, len, 2180 "EHCI root hub"); 2181 break; 2182 } 2183 #undef sd 2184 break; 2185 default: 2186 err = USBD_IOERROR; 2187 goto ret; 2188 } 2189 break; 2190 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2191 if (len > 0) { 2192 *(u_int8_t *)buf = 0; 2193 totlen = 1; 2194 } 2195 break; 2196 case C(UR_GET_STATUS, UT_READ_DEVICE): 2197 if (len > 1) { 2198 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2199 totlen = 2; 2200 } 2201 break; 2202 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2203 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2204 if (len > 1) { 2205 USETW(((usb_status_t *)buf)->wStatus, 0); 2206 totlen = 2; 2207 } 2208 break; 2209 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2210 if (value >= USB_MAX_DEVICES) { 2211 err = USBD_IOERROR; 2212 goto ret; 2213 } 2214 sc->sc_addr = value; 2215 break; 2216 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2217 if (value != 0 && value != 1) { 2218 err = USBD_IOERROR; 2219 goto ret; 2220 } 2221 sc->sc_conf = value; 2222 break; 2223 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2224 break; 2225 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2226 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2227 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2228 err = USBD_IOERROR; 2229 goto ret; 2230 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2231 break; 2232 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2233 break; 2234 /* Hub requests */ 2235 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2236 break; 2237 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2238 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2239 "port=%d feature=%d\n", 2240 index, value)); 2241 if (index < 1 || index > sc->sc_noport) { 2242 err = USBD_IOERROR; 2243 goto ret; 2244 } 2245 port = EHCI_PORTSC(index); 2246 v = EOREAD4(sc, port); 2247 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2248 v &= ~EHCI_PS_CLEAR; 2249 switch(value) { 2250 case UHF_PORT_ENABLE: 2251 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2252 break; 2253 case UHF_PORT_SUSPEND: 2254 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2255 break; 2256 v &= ~EHCI_PS_SUSP; 2257 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2258 /* see USB2 spec ch. 7.1.7.7 */ 2259 usb_delay_ms(&sc->sc_bus, 20); 2260 EOWRITE4(sc, port, v); 2261 usb_delay_ms(&sc->sc_bus, 2); 2262 #ifdef DEBUG 2263 v = EOREAD4(sc, port); 2264 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2265 printf("ehci: resume failed: %x\n", v); 2266 #endif 2267 break; 2268 case UHF_PORT_POWER: 2269 if (sc->sc_hasppc) 2270 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2271 break; 2272 case UHF_PORT_TEST: 2273 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2274 "%d\n", index)); 2275 break; 2276 case UHF_PORT_INDICATOR: 2277 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2278 "%d\n", index)); 2279 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2280 break; 2281 case UHF_C_PORT_CONNECTION: 2282 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2283 break; 2284 case UHF_C_PORT_ENABLE: 2285 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2286 break; 2287 case UHF_C_PORT_SUSPEND: 2288 /* how? */ 2289 break; 2290 case UHF_C_PORT_OVER_CURRENT: 2291 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2292 break; 2293 case UHF_C_PORT_RESET: 2294 sc->sc_isreset[index] = 0; 2295 break; 2296 default: 2297 err = USBD_IOERROR; 2298 goto ret; 2299 } 2300 #if 0 2301 switch(value) { 2302 case UHF_C_PORT_CONNECTION: 2303 case UHF_C_PORT_ENABLE: 2304 case UHF_C_PORT_SUSPEND: 2305 case UHF_C_PORT_OVER_CURRENT: 2306 case UHF_C_PORT_RESET: 2307 default: 2308 break; 2309 } 2310 #endif 2311 break; 2312 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2313 if (len == 0) 2314 break; 2315 if ((value & 0xff) != 0) { 2316 err = USBD_IOERROR; 2317 goto ret; 2318 } 2319 hubd = ehci_hubd; 2320 hubd.bNbrPorts = sc->sc_noport; 2321 v = EOREAD4(sc, EHCI_HCSPARAMS); 2322 USETW(hubd.wHubCharacteristics, 2323 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2324 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2325 ? UHD_PORT_IND : 0); 2326 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2327 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2328 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2329 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2330 l = min(len, hubd.bDescLength); 2331 totlen = l; 2332 memcpy(buf, &hubd, l); 2333 break; 2334 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2335 if (len != 4) { 2336 err = USBD_IOERROR; 2337 goto ret; 2338 } 2339 memset(buf, 0, len); /* ? XXX */ 2340 totlen = len; 2341 break; 2342 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2343 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2344 index)); 2345 if (index < 1 || index > sc->sc_noport) { 2346 err = USBD_IOERROR; 2347 goto ret; 2348 } 2349 if (len != 4) { 2350 err = USBD_IOERROR; 2351 goto ret; 2352 } 2353 v = EOREAD4(sc, EHCI_PORTSC(index)); 2354 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2355 2356 i = UPS_HIGH_SPEED; 2357 if (sc->sc_flags & EHCIF_ETTF) { 2358 /* 2359 * If we are doing embedded transaction translation, 2360 * then directly attached LS/FS devices are reset by 2361 * the EHCI controller itself. PSPD is encoded 2362 * the same way as in USBSTATUS. 2363 */ 2364 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2365 } 2366 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2367 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2368 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2369 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2370 if (v & EHCI_PS_PR) i |= UPS_RESET; 2371 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2372 if (sc->sc_vendor_port_status) 2373 i = sc->sc_vendor_port_status(sc, v, i); 2374 USETW(ps.wPortStatus, i); 2375 i = 0; 2376 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2377 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2378 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2379 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2380 USETW(ps.wPortChange, i); 2381 l = min(len, sizeof ps); 2382 memcpy(buf, &ps, l); 2383 totlen = l; 2384 break; 2385 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2386 err = USBD_IOERROR; 2387 goto ret; 2388 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2389 break; 2390 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2391 if (index < 1 || index > sc->sc_noport) { 2392 err = USBD_IOERROR; 2393 goto ret; 2394 } 2395 port = EHCI_PORTSC(index); 2396 v = EOREAD4(sc, port); 2397 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2398 v &= ~EHCI_PS_CLEAR; 2399 switch(value) { 2400 case UHF_PORT_ENABLE: 2401 EOWRITE4(sc, port, v | EHCI_PS_PE); 2402 break; 2403 case UHF_PORT_SUSPEND: 2404 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2405 break; 2406 case UHF_PORT_RESET: 2407 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2408 index)); 2409 if (EHCI_PS_IS_LOWSPEED(v) 2410 && sc->sc_ncomp > 0 2411 && !(sc->sc_flags & EHCIF_ETTF)) { 2412 /* 2413 * Low speed device on non-ETTF controller or 2414 * unaccompanied controller, give up ownership. 2415 */ 2416 ehci_disown(sc, index, 1); 2417 break; 2418 } 2419 /* Start reset sequence. */ 2420 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2421 EOWRITE4(sc, port, v | EHCI_PS_PR); 2422 /* Wait for reset to complete. */ 2423 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2424 if (sc->sc_dying) { 2425 err = USBD_IOERROR; 2426 goto ret; 2427 } 2428 /* 2429 * An embedded transaction translator will automatically 2430 * terminate the reset sequence so there's no need to 2431 * it. 2432 */ 2433 v = EOREAD4(sc, port); 2434 if (v & EHCI_PS_PR) { 2435 /* Terminate reset sequence. */ 2436 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2437 /* Wait for HC to complete reset. */ 2438 usb_delay_ms(&sc->sc_bus, 2439 EHCI_PORT_RESET_COMPLETE); 2440 if (sc->sc_dying) { 2441 err = USBD_IOERROR; 2442 goto ret; 2443 } 2444 } 2445 2446 v = EOREAD4(sc, port); 2447 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2448 if (v & EHCI_PS_PR) { 2449 printf("%s: port reset timeout\n", 2450 device_xname(sc->sc_dev)); 2451 return (USBD_TIMEOUT); 2452 } 2453 if (!(v & EHCI_PS_PE)) { 2454 /* Not a high speed device, give up ownership.*/ 2455 ehci_disown(sc, index, 0); 2456 break; 2457 } 2458 sc->sc_isreset[index] = 1; 2459 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2460 index, v)); 2461 break; 2462 case UHF_PORT_POWER: 2463 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2464 "%d (has PPC = %d)\n", index, 2465 sc->sc_hasppc)); 2466 if (sc->sc_hasppc) 2467 EOWRITE4(sc, port, v | EHCI_PS_PP); 2468 break; 2469 case UHF_PORT_TEST: 2470 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2471 "%d\n", index)); 2472 break; 2473 case UHF_PORT_INDICATOR: 2474 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2475 "%d\n", index)); 2476 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2477 break; 2478 default: 2479 err = USBD_IOERROR; 2480 goto ret; 2481 } 2482 break; 2483 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2484 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2485 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2486 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2487 break; 2488 default: 2489 err = USBD_IOERROR; 2490 goto ret; 2491 } 2492 xfer->actlen = totlen; 2493 err = USBD_NORMAL_COMPLETION; 2494 ret: 2495 mutex_enter(&sc->sc_lock); 2496 xfer->status = err; 2497 usb_transfer_complete(xfer); 2498 mutex_exit(&sc->sc_lock); 2499 return (USBD_IN_PROGRESS); 2500 } 2501 2502 Static void 2503 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2504 { 2505 int port; 2506 u_int32_t v; 2507 2508 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2509 #ifdef DIAGNOSTIC 2510 if (sc->sc_npcomp != 0) { 2511 int i = (index-1) / sc->sc_npcomp; 2512 if (i >= sc->sc_ncomp) 2513 printf("%s: strange port\n", 2514 device_xname(sc->sc_dev)); 2515 else 2516 printf("%s: handing over %s speed device on " 2517 "port %d to %s\n", 2518 device_xname(sc->sc_dev), 2519 lowspeed ? "low" : "full", 2520 index, device_xname(sc->sc_comps[i])); 2521 } else { 2522 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2523 } 2524 #endif 2525 port = EHCI_PORTSC(index); 2526 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2527 EOWRITE4(sc, port, v | EHCI_PS_PO); 2528 } 2529 2530 /* Abort a root control request. */ 2531 Static void 2532 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2533 { 2534 /* Nothing to do, all transfers are synchronous. */ 2535 } 2536 2537 /* Close the root pipe. */ 2538 Static void 2539 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2540 { 2541 DPRINTF(("ehci_root_ctrl_close\n")); 2542 /* Nothing to do. */ 2543 } 2544 2545 Static void 2546 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2547 { 2548 xfer->hcpriv = NULL; 2549 } 2550 2551 Static usbd_status 2552 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2553 { 2554 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2555 usbd_status err; 2556 2557 /* Insert last in queue. */ 2558 mutex_enter(&sc->sc_lock); 2559 err = usb_insert_transfer(xfer); 2560 mutex_exit(&sc->sc_lock); 2561 if (err) 2562 return (err); 2563 2564 /* Pipe isn't running, start first */ 2565 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2566 } 2567 2568 Static usbd_status 2569 ehci_root_intr_start(usbd_xfer_handle xfer) 2570 { 2571 usbd_pipe_handle pipe = xfer->pipe; 2572 ehci_softc_t *sc = pipe->device->bus->hci_private; 2573 2574 if (sc->sc_dying) 2575 return (USBD_IOERROR); 2576 2577 mutex_enter(&sc->sc_lock); 2578 sc->sc_intrxfer = xfer; 2579 mutex_exit(&sc->sc_lock); 2580 2581 return (USBD_IN_PROGRESS); 2582 } 2583 2584 /* Abort a root interrupt request. */ 2585 Static void 2586 ehci_root_intr_abort(usbd_xfer_handle xfer) 2587 { 2588 #ifdef DIAGNOSTIC 2589 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2590 #endif 2591 2592 KASSERT(mutex_owned(&sc->sc_lock)); 2593 if (xfer->pipe->intrxfer == xfer) { 2594 DPRINTF(("ehci_root_intr_abort: remove\n")); 2595 xfer->pipe->intrxfer = NULL; 2596 } 2597 xfer->status = USBD_CANCELLED; 2598 usb_transfer_complete(xfer); 2599 } 2600 2601 /* Close the root pipe. */ 2602 Static void 2603 ehci_root_intr_close(usbd_pipe_handle pipe) 2604 { 2605 ehci_softc_t *sc = pipe->device->bus->hci_private; 2606 2607 KASSERT(mutex_owned(&sc->sc_lock)); 2608 2609 DPRINTF(("ehci_root_intr_close\n")); 2610 2611 sc->sc_intrxfer = NULL; 2612 } 2613 2614 Static void 2615 ehci_root_intr_done(usbd_xfer_handle xfer) 2616 { 2617 xfer->hcpriv = NULL; 2618 } 2619 2620 /************************/ 2621 2622 Static ehci_soft_qh_t * 2623 ehci_alloc_sqh(ehci_softc_t *sc) 2624 { 2625 ehci_soft_qh_t *sqh; 2626 usbd_status err; 2627 int i, offs; 2628 usb_dma_t dma; 2629 2630 if (sc->sc_freeqhs == NULL) { 2631 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2632 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2633 EHCI_PAGE_SIZE, &dma); 2634 #ifdef EHCI_DEBUG 2635 if (err) 2636 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2637 #endif 2638 if (err) 2639 return (NULL); 2640 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2641 offs = i * EHCI_SQH_SIZE; 2642 sqh = KERNADDR(&dma, offs); 2643 sqh->physaddr = DMAADDR(&dma, offs); 2644 sqh->dma = dma; 2645 sqh->offs = offs; 2646 sqh->next = sc->sc_freeqhs; 2647 sc->sc_freeqhs = sqh; 2648 } 2649 } 2650 sqh = sc->sc_freeqhs; 2651 sc->sc_freeqhs = sqh->next; 2652 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2653 sqh->next = NULL; 2654 return (sqh); 2655 } 2656 2657 Static void 2658 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2659 { 2660 sqh->next = sc->sc_freeqhs; 2661 sc->sc_freeqhs = sqh; 2662 } 2663 2664 Static ehci_soft_qtd_t * 2665 ehci_alloc_sqtd(ehci_softc_t *sc) 2666 { 2667 ehci_soft_qtd_t *sqtd = NULL; 2668 usbd_status err; 2669 int i, offs; 2670 usb_dma_t dma; 2671 2672 if (sc->sc_freeqtds == NULL) { 2673 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2674 2675 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2676 EHCI_PAGE_SIZE, &dma); 2677 #ifdef EHCI_DEBUG 2678 if (err) 2679 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2680 #endif 2681 if (err) 2682 goto done; 2683 2684 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2685 offs = i * EHCI_SQTD_SIZE; 2686 sqtd = KERNADDR(&dma, offs); 2687 sqtd->physaddr = DMAADDR(&dma, offs); 2688 sqtd->dma = dma; 2689 sqtd->offs = offs; 2690 2691 sqtd->nextqtd = sc->sc_freeqtds; 2692 sc->sc_freeqtds = sqtd; 2693 } 2694 } 2695 2696 sqtd = sc->sc_freeqtds; 2697 sc->sc_freeqtds = sqtd->nextqtd; 2698 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2699 sqtd->nextqtd = NULL; 2700 sqtd->xfer = NULL; 2701 2702 done: 2703 return (sqtd); 2704 } 2705 2706 Static void 2707 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2708 { 2709 2710 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 2711 2712 sqtd->nextqtd = sc->sc_freeqtds; 2713 sc->sc_freeqtds = sqtd; 2714 } 2715 2716 Static usbd_status 2717 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2718 int alen, int rd, usbd_xfer_handle xfer, 2719 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2720 { 2721 ehci_soft_qtd_t *next, *cur; 2722 ehci_physaddr_t nextphys; 2723 u_int32_t qtdstatus; 2724 int len, curlen, mps; 2725 int i, tog; 2726 int pages, pageoffs; 2727 bus_size_t curoffs; 2728 vaddr_t va, va_offs; 2729 usb_dma_t *dma = &xfer->dmabuf; 2730 u_int16_t flags = xfer->flags; 2731 paddr_t a; 2732 2733 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2734 2735 len = alen; 2736 qtdstatus = EHCI_QTD_ACTIVE | 2737 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2738 EHCI_QTD_SET_CERR(3) 2739 /* IOC set below */ 2740 /* BYTES set below */ 2741 ; 2742 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2743 tog = epipe->nexttoggle; 2744 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2745 2746 cur = ehci_alloc_sqtd(sc); 2747 *sp = cur; 2748 if (cur == NULL) 2749 goto nomem; 2750 2751 usb_syncmem(dma, 0, alen, 2752 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2753 curoffs = 0; 2754 for (;;) { 2755 /* The EHCI hardware can handle at most 5 pages. */ 2756 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2757 va_offs = EHCI_PAGE_OFFSET(va_offs); 2758 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 2759 /* we can handle it in this QTD */ 2760 curlen = len - curoffs; 2761 } else { 2762 /* must use multiple TDs, fill as much as possible. */ 2763 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 2764 2765 /* the length must be a multiple of the max size */ 2766 curlen -= curlen % mps; 2767 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2768 "curlen=%d\n", curlen)); 2769 #ifdef DIAGNOSTIC 2770 if (curlen == 0) 2771 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2772 #endif 2773 } 2774 DPRINTFN(4,("ehci_alloc_sqtd_chain: len=%d curlen=%d " 2775 "curoffs=%zu\n", len, curlen, (size_t)curoffs)); 2776 2777 /* 2778 * Allocate another transfer if there's more data left, 2779 * or if force last short transfer flag is set and we're 2780 * allocating a multiple of the max packet size. 2781 */ 2782 2783 if (curoffs + curlen != len || 2784 ((curlen % mps) == 0 && !rd && curlen != 0 && 2785 (flags & USBD_FORCE_SHORT_XFER))) { 2786 next = ehci_alloc_sqtd(sc); 2787 if (next == NULL) 2788 goto nomem; 2789 nextphys = htole32(next->physaddr); 2790 } else { 2791 next = NULL; 2792 nextphys = EHCI_NULL; 2793 } 2794 2795 /* Find number of pages we'll be using, insert dma addresses */ 2796 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2797 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2798 pageoffs = EHCI_PAGE(curoffs); 2799 for (i = 0; i < pages; i++) { 2800 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2801 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2802 /* Cast up to avoid compiler warnings */ 2803 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2804 } 2805 2806 /* First buffer pointer requires a page offset to start at */ 2807 va = (vaddr_t)KERNADDR(dma, curoffs); 2808 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2809 2810 cur->nextqtd = next; 2811 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2812 cur->qtd.qtd_status = 2813 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2814 cur->xfer = xfer; 2815 cur->len = curlen; 2816 2817 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08zx end=0x%08zx\n", 2818 (size_t)curoffs, (size_t)(curoffs + curlen))); 2819 2820 /* adjust the toggle based on the number of packets in this 2821 qtd */ 2822 if (((curlen + mps - 1) / mps) & 1) { 2823 tog ^= 1; 2824 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2825 } 2826 if (next == NULL) 2827 break; 2828 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2829 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2830 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2831 if (len) 2832 curoffs += curlen; 2833 cur = next; 2834 } 2835 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2836 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2837 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2838 *ep = cur; 2839 epipe->nexttoggle = tog; 2840 2841 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2842 *sp, *ep)); 2843 2844 return (USBD_NORMAL_COMPLETION); 2845 2846 nomem: 2847 /* XXX free chain */ 2848 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2849 return (USBD_NOMEM); 2850 } 2851 2852 Static void 2853 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2854 ehci_soft_qtd_t *sqtdend) 2855 { 2856 ehci_soft_qtd_t *p; 2857 int i; 2858 2859 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2860 sqtd, sqtdend)); 2861 2862 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2863 p = sqtd->nextqtd; 2864 ehci_free_sqtd(sc, sqtd); 2865 } 2866 } 2867 2868 Static ehci_soft_itd_t * 2869 ehci_alloc_itd(ehci_softc_t *sc) 2870 { 2871 struct ehci_soft_itd *itd, *freeitd; 2872 usbd_status err; 2873 int i, offs, frindex, previndex; 2874 usb_dma_t dma; 2875 2876 mutex_enter(&sc->sc_lock); 2877 2878 /* Find an itd that wasn't freed this frame or last frame. This can 2879 * discard itds that were freed before frindex wrapped around 2880 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2881 * interrupt and fiddling with list when that happens */ 2882 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2883 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2884 2885 freeitd = NULL; 2886 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2887 if (itd == NULL) 2888 break; 2889 if (itd->slot != frindex && itd->slot != previndex) { 2890 freeitd = itd; 2891 break; 2892 } 2893 } 2894 2895 if (freeitd == NULL) { 2896 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2897 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2898 EHCI_PAGE_SIZE, &dma); 2899 2900 if (err) { 2901 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2902 mutex_exit(&sc->sc_lock); 2903 return NULL; 2904 } 2905 2906 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2907 offs = i * EHCI_ITD_SIZE; 2908 itd = KERNADDR(&dma, offs); 2909 itd->physaddr = DMAADDR(&dma, offs); 2910 itd->dma = dma; 2911 itd->offs = offs; 2912 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2913 } 2914 freeitd = LIST_FIRST(&sc->sc_freeitds); 2915 } 2916 2917 itd = freeitd; 2918 LIST_REMOVE(itd, u.free_list); 2919 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2920 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2921 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2922 BUS_DMASYNC_PREREAD); 2923 2924 itd->u.frame_list.next = NULL; 2925 itd->u.frame_list.prev = NULL; 2926 itd->xfer_next = NULL; 2927 itd->slot = 0; 2928 2929 mutex_exit(&sc->sc_lock); 2930 2931 return itd; 2932 } 2933 2934 Static void 2935 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2936 { 2937 2938 KASSERT(mutex_owned(&sc->sc_lock)); 2939 2940 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2941 } 2942 2943 /****************/ 2944 2945 /* 2946 * Close a reqular pipe. 2947 * Assumes that there are no pending transactions. 2948 */ 2949 Static void 2950 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2951 { 2952 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2953 ehci_softc_t *sc = pipe->device->bus->hci_private; 2954 ehci_soft_qh_t *sqh = epipe->sqh; 2955 2956 KASSERT(mutex_owned(&sc->sc_lock)); 2957 2958 ehci_rem_qh(sc, sqh, head); 2959 ehci_free_sqh(sc, epipe->sqh); 2960 } 2961 2962 /* 2963 * Abort a device request. 2964 * If this routine is called at splusb() it guarantees that the request 2965 * will be removed from the hardware scheduling and that the callback 2966 * for it will be called with USBD_CANCELLED status. 2967 * It's impossible to guarantee that the requested transfer will not 2968 * have happened since the hardware runs concurrently. 2969 * If the transaction has already happened we rely on the ordinary 2970 * interrupt processing to process it. 2971 * XXX This is most probably wrong. 2972 * XXXMRG this doesn't make sense anymore. 2973 */ 2974 Static void 2975 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2976 { 2977 #define exfer EXFER(xfer) 2978 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2979 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2980 ehci_soft_qh_t *sqh = epipe->sqh; 2981 ehci_soft_qtd_t *sqtd; 2982 ehci_physaddr_t cur; 2983 u_int32_t qhstatus; 2984 int hit; 2985 int wake; 2986 2987 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 2988 2989 KASSERT(mutex_owned(&sc->sc_lock)); 2990 2991 if (sc->sc_dying) { 2992 /* If we're dying, just do the software part. */ 2993 xfer->status = status; /* make software ignore it */ 2994 callout_stop(&xfer->timeout_handle); 2995 usb_transfer_complete(xfer); 2996 return; 2997 } 2998 2999 if (cpu_intr_p() || cpu_softintr_p()) 3000 panic("ehci_abort_xfer: not in process context"); 3001 3002 /* 3003 * If an abort is already in progress then just wait for it to 3004 * complete and return. 3005 */ 3006 if (xfer->hcflags & UXFER_ABORTING) { 3007 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3008 #ifdef DIAGNOSTIC 3009 if (status == USBD_TIMEOUT) 3010 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3011 #endif 3012 /* Override the status which might be USBD_TIMEOUT. */ 3013 xfer->status = status; 3014 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3015 xfer->hcflags |= UXFER_ABORTWAIT; 3016 while (xfer->hcflags & UXFER_ABORTING) 3017 cv_wait(&xfer->hccv, &sc->sc_lock); 3018 return; 3019 } 3020 xfer->hcflags |= UXFER_ABORTING; 3021 3022 /* 3023 * Step 1: Make interrupt routine and hardware ignore xfer. 3024 */ 3025 xfer->status = status; /* make software ignore it */ 3026 callout_stop(&xfer->timeout_handle); 3027 3028 usb_syncmem(&sqh->dma, 3029 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3030 sizeof(sqh->qh.qh_qtd.qtd_status), 3031 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3032 qhstatus = sqh->qh.qh_qtd.qtd_status; 3033 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3034 usb_syncmem(&sqh->dma, 3035 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3036 sizeof(sqh->qh.qh_qtd.qtd_status), 3037 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3038 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3039 usb_syncmem(&sqtd->dma, 3040 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3041 sizeof(sqtd->qtd.qtd_status), 3042 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3043 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3044 usb_syncmem(&sqtd->dma, 3045 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3046 sizeof(sqtd->qtd.qtd_status), 3047 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3048 if (sqtd == exfer->sqtdend) 3049 break; 3050 } 3051 3052 /* 3053 * Step 2: Wait until we know hardware has finished any possible 3054 * use of the xfer. Also make sure the soft interrupt routine 3055 * has run. 3056 */ 3057 ehci_sync_hc(sc); 3058 sc->sc_softwake = 1; 3059 usb_schedsoftintr(&sc->sc_bus); 3060 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3061 3062 /* 3063 * Step 3: Remove any vestiges of the xfer from the hardware. 3064 * The complication here is that the hardware may have executed 3065 * beyond the xfer we're trying to abort. So as we're scanning 3066 * the TDs of this xfer we check if the hardware points to 3067 * any of them. 3068 */ 3069 3070 usb_syncmem(&sqh->dma, 3071 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3072 sizeof(sqh->qh.qh_curqtd), 3073 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3074 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3075 hit = 0; 3076 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3077 hit |= cur == sqtd->physaddr; 3078 if (sqtd == exfer->sqtdend) 3079 break; 3080 } 3081 sqtd = sqtd->nextqtd; 3082 /* Zap curqtd register if hardware pointed inside the xfer. */ 3083 if (hit && sqtd != NULL) { 3084 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3085 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3086 usb_syncmem(&sqh->dma, 3087 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3088 sizeof(sqh->qh.qh_curqtd), 3089 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3090 sqh->qh.qh_qtd.qtd_status = qhstatus; 3091 usb_syncmem(&sqh->dma, 3092 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3093 sizeof(sqh->qh.qh_qtd.qtd_status), 3094 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3095 } else { 3096 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3097 } 3098 3099 /* 3100 * Step 4: Execute callback. 3101 */ 3102 #ifdef DIAGNOSTIC 3103 exfer->isdone = 1; 3104 #endif 3105 wake = xfer->hcflags & UXFER_ABORTWAIT; 3106 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3107 usb_transfer_complete(xfer); 3108 if (wake) { 3109 cv_broadcast(&xfer->hccv); 3110 } 3111 3112 KASSERT(mutex_owned(&sc->sc_lock)); 3113 #undef exfer 3114 } 3115 3116 Static void 3117 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3118 { 3119 ehci_isoc_trans_t trans_status; 3120 struct ehci_pipe *epipe; 3121 struct ehci_xfer *exfer; 3122 ehci_softc_t *sc; 3123 struct ehci_soft_itd *itd; 3124 int i, wake; 3125 3126 epipe = (struct ehci_pipe *) xfer->pipe; 3127 exfer = EXFER(xfer); 3128 sc = epipe->pipe.device->bus->hci_private; 3129 3130 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3131 3132 KASSERT(mutex_owned(&sc->sc_lock)); 3133 3134 if (sc->sc_dying) { 3135 xfer->status = status; 3136 callout_stop(&xfer->timeout_handle); 3137 usb_transfer_complete(xfer); 3138 return; 3139 } 3140 3141 if (xfer->hcflags & UXFER_ABORTING) { 3142 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3143 3144 #ifdef DIAGNOSTIC 3145 if (status == USBD_TIMEOUT) 3146 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3147 #endif 3148 3149 xfer->status = status; 3150 DPRINTFN(2, ("ehci_abort_isoc_xfer: waiting for abort to finish\n")); 3151 xfer->hcflags |= UXFER_ABORTWAIT; 3152 while (xfer->hcflags & UXFER_ABORTING) 3153 cv_wait(&xfer->hccv, &sc->sc_lock); 3154 goto done; 3155 } 3156 xfer->hcflags |= UXFER_ABORTING; 3157 3158 xfer->status = status; 3159 callout_stop(&xfer->timeout_handle); 3160 3161 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3162 usb_syncmem(&itd->dma, 3163 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3164 sizeof(itd->itd.itd_ctl), 3165 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3166 3167 for (i = 0; i < 8; i++) { 3168 trans_status = le32toh(itd->itd.itd_ctl[i]); 3169 trans_status &= ~EHCI_ITD_ACTIVE; 3170 itd->itd.itd_ctl[i] = htole32(trans_status); 3171 } 3172 3173 usb_syncmem(&itd->dma, 3174 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3175 sizeof(itd->itd.itd_ctl), 3176 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3177 } 3178 3179 sc->sc_softwake = 1; 3180 usb_schedsoftintr(&sc->sc_bus); 3181 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3182 3183 #ifdef DIAGNOSTIC 3184 exfer->isdone = 1; 3185 #endif 3186 wake = xfer->hcflags & UXFER_ABORTWAIT; 3187 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3188 usb_transfer_complete(xfer); 3189 if (wake) { 3190 cv_broadcast(&xfer->hccv); 3191 } 3192 3193 done: 3194 KASSERT(mutex_owned(&sc->sc_lock)); 3195 return; 3196 } 3197 3198 Static void 3199 ehci_timeout(void *addr) 3200 { 3201 struct ehci_xfer *exfer = addr; 3202 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3203 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3204 3205 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3206 #ifdef EHCI_DEBUG 3207 if (ehcidebug > 1) 3208 usbd_dump_pipe(exfer->xfer.pipe); 3209 #endif 3210 3211 if (sc->sc_dying) { 3212 mutex_enter(&sc->sc_lock); 3213 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3214 mutex_exit(&sc->sc_lock); 3215 return; 3216 } 3217 3218 /* Execute the abort in a process context. */ 3219 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr, 3220 USB_TASKQ_MPSAFE); 3221 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3222 USB_TASKQ_HC); 3223 } 3224 3225 Static void 3226 ehci_timeout_task(void *addr) 3227 { 3228 usbd_xfer_handle xfer = addr; 3229 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3230 3231 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3232 3233 mutex_enter(&sc->sc_lock); 3234 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3235 mutex_exit(&sc->sc_lock); 3236 } 3237 3238 /************************/ 3239 3240 Static usbd_status 3241 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3242 { 3243 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3244 usbd_status err; 3245 3246 /* Insert last in queue. */ 3247 mutex_enter(&sc->sc_lock); 3248 err = usb_insert_transfer(xfer); 3249 mutex_exit(&sc->sc_lock); 3250 if (err) 3251 return (err); 3252 3253 /* Pipe isn't running, start first */ 3254 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3255 } 3256 3257 Static usbd_status 3258 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3259 { 3260 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3261 usbd_status err; 3262 3263 if (sc->sc_dying) 3264 return (USBD_IOERROR); 3265 3266 #ifdef DIAGNOSTIC 3267 if (!(xfer->rqflags & URQ_REQUEST)) { 3268 /* XXX panic */ 3269 printf("ehci_device_ctrl_transfer: not a request\n"); 3270 return (USBD_INVAL); 3271 } 3272 #endif 3273 3274 err = ehci_device_request(xfer); 3275 if (err) { 3276 return (err); 3277 } 3278 3279 if (sc->sc_bus.use_polling) 3280 ehci_waitintr(sc, xfer); 3281 3282 return (USBD_IN_PROGRESS); 3283 } 3284 3285 Static void 3286 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3287 { 3288 struct ehci_xfer *ex = EXFER(xfer); 3289 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3290 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3291 usb_device_request_t *req = &xfer->request; 3292 int len = UGETW(req->wLength); 3293 int rd = req->bmRequestType & UT_READ; 3294 3295 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3296 3297 KASSERT(mutex_owned(&sc->sc_lock)); 3298 3299 #ifdef DIAGNOSTIC 3300 if (!(xfer->rqflags & URQ_REQUEST)) { 3301 panic("ehci_ctrl_done: not a request"); 3302 } 3303 #endif 3304 3305 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3306 ehci_del_intr_list(sc, ex); /* remove from active list */ 3307 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3308 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3309 BUS_DMASYNC_POSTWRITE); 3310 if (len) 3311 usb_syncmem(&xfer->dmabuf, 0, len, 3312 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3313 } 3314 3315 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3316 } 3317 3318 /* Abort a device control request. */ 3319 Static void 3320 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3321 { 3322 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3323 ehci_abort_xfer(xfer, USBD_CANCELLED); 3324 } 3325 3326 /* Close a device control pipe. */ 3327 Static void 3328 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3329 { 3330 ehci_softc_t *sc = pipe->device->bus->hci_private; 3331 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3332 3333 KASSERT(mutex_owned(&sc->sc_lock)); 3334 3335 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3336 3337 ehci_close_pipe(pipe, sc->sc_async_head); 3338 } 3339 3340 Static usbd_status 3341 ehci_device_request(usbd_xfer_handle xfer) 3342 { 3343 #define exfer EXFER(xfer) 3344 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3345 usb_device_request_t *req = &xfer->request; 3346 usbd_device_handle dev = epipe->pipe.device; 3347 ehci_softc_t *sc = dev->bus->hci_private; 3348 int addr = dev->address; 3349 ehci_soft_qtd_t *setup, *stat, *next; 3350 ehci_soft_qh_t *sqh; 3351 int isread; 3352 int len; 3353 usbd_status err; 3354 3355 isread = req->bmRequestType & UT_READ; 3356 len = UGETW(req->wLength); 3357 3358 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3359 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3360 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3361 UGETW(req->wIndex), len, addr, 3362 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3363 3364 setup = ehci_alloc_sqtd(sc); 3365 if (setup == NULL) { 3366 err = USBD_NOMEM; 3367 goto bad1; 3368 } 3369 stat = ehci_alloc_sqtd(sc); 3370 if (stat == NULL) { 3371 err = USBD_NOMEM; 3372 goto bad2; 3373 } 3374 3375 mutex_enter(&sc->sc_lock); 3376 3377 sqh = epipe->sqh; 3378 3379 /* 3380 * Update device address and length since they may have changed 3381 * during the setup of the control pipe in usbd_new_device(). 3382 */ 3383 /* XXX This only needs to be done once, but it's too early in open. */ 3384 /* XXXX Should not touch ED here! */ 3385 sqh->qh.qh_endp = 3386 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) | 3387 htole32( 3388 EHCI_QH_SET_ADDR(addr) | 3389 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)) 3390 ); 3391 3392 /* Set up data transaction */ 3393 if (len != 0) { 3394 ehci_soft_qtd_t *end; 3395 3396 /* Start toggle at 1. */ 3397 epipe->nexttoggle = 1; 3398 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3399 &next, &end); 3400 if (err) 3401 goto bad3; 3402 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3403 end->nextqtd = stat; 3404 end->qtd.qtd_next = end->qtd.qtd_altnext = 3405 htole32(stat->physaddr); 3406 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3407 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3408 } else { 3409 next = stat; 3410 } 3411 3412 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3413 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3414 3415 /* Clear toggle */ 3416 setup->qtd.qtd_status = htole32( 3417 EHCI_QTD_ACTIVE | 3418 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3419 EHCI_QTD_SET_CERR(3) | 3420 EHCI_QTD_SET_TOGGLE(0) | 3421 EHCI_QTD_SET_BYTES(sizeof *req) 3422 ); 3423 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3424 setup->qtd.qtd_buffer_hi[0] = 0; 3425 setup->nextqtd = next; 3426 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3427 setup->xfer = xfer; 3428 setup->len = sizeof *req; 3429 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3430 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3431 3432 stat->qtd.qtd_status = htole32( 3433 EHCI_QTD_ACTIVE | 3434 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3435 EHCI_QTD_SET_CERR(3) | 3436 EHCI_QTD_SET_TOGGLE(1) | 3437 EHCI_QTD_IOC 3438 ); 3439 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3440 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3441 stat->nextqtd = NULL; 3442 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3443 stat->xfer = xfer; 3444 stat->len = 0; 3445 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3446 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3447 3448 #ifdef EHCI_DEBUG 3449 if (ehcidebug > 5) { 3450 DPRINTF(("ehci_device_request:\n")); 3451 ehci_dump_sqh(sqh); 3452 ehci_dump_sqtds(setup); 3453 } 3454 #endif 3455 3456 exfer->sqtdstart = setup; 3457 exfer->sqtdend = stat; 3458 #ifdef DIAGNOSTIC 3459 if (!exfer->isdone) { 3460 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3461 } 3462 exfer->isdone = 0; 3463 #endif 3464 3465 /* Insert qTD in QH list. */ 3466 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3467 if (xfer->timeout && !sc->sc_bus.use_polling) { 3468 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3469 ehci_timeout, xfer); 3470 } 3471 ehci_add_intr_list(sc, exfer); 3472 xfer->status = USBD_IN_PROGRESS; 3473 mutex_exit(&sc->sc_lock); 3474 3475 #ifdef EHCI_DEBUG 3476 if (ehcidebug > 10) { 3477 DPRINTF(("ehci_device_request: status=%x\n", 3478 EOREAD4(sc, EHCI_USBSTS))); 3479 delay(10000); 3480 ehci_dump_regs(sc); 3481 ehci_dump_sqh(sc->sc_async_head); 3482 ehci_dump_sqh(sqh); 3483 ehci_dump_sqtds(setup); 3484 } 3485 #endif 3486 3487 return (USBD_NORMAL_COMPLETION); 3488 3489 bad3: 3490 mutex_exit(&sc->sc_lock); 3491 ehci_free_sqtd(sc, stat); 3492 bad2: 3493 ehci_free_sqtd(sc, setup); 3494 bad1: 3495 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3496 mutex_enter(&sc->sc_lock); 3497 xfer->status = err; 3498 usb_transfer_complete(xfer); 3499 mutex_exit(&sc->sc_lock); 3500 return (err); 3501 #undef exfer 3502 } 3503 3504 /* 3505 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3506 * qTD status, or miss signalling occasionally under heavy load. If the host 3507 * machine is too fast, we we can miss transaction completion - when we scan 3508 * the active list the transaction still seems to be active. This generally 3509 * exhibits itself as a umass stall that never recovers. 3510 * 3511 * We work around this behaviour by setting up this callback after any softintr 3512 * that completes with transactions still pending, giving us another chance to 3513 * check for completion after the writeback has taken place. 3514 */ 3515 Static void 3516 ehci_intrlist_timeout(void *arg) 3517 { 3518 ehci_softc_t *sc = arg; 3519 3520 DPRINTF(("ehci_intrlist_timeout\n")); 3521 usb_schedsoftintr(&sc->sc_bus); 3522 } 3523 3524 /************************/ 3525 3526 Static usbd_status 3527 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3528 { 3529 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3530 usbd_status err; 3531 3532 /* Insert last in queue. */ 3533 mutex_enter(&sc->sc_lock); 3534 err = usb_insert_transfer(xfer); 3535 mutex_exit(&sc->sc_lock); 3536 if (err) 3537 return (err); 3538 3539 /* Pipe isn't running, start first */ 3540 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3541 } 3542 3543 Static usbd_status 3544 ehci_device_bulk_start(usbd_xfer_handle xfer) 3545 { 3546 #define exfer EXFER(xfer) 3547 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3548 usbd_device_handle dev = epipe->pipe.device; 3549 ehci_softc_t *sc = dev->bus->hci_private; 3550 ehci_soft_qtd_t *data, *dataend; 3551 ehci_soft_qh_t *sqh; 3552 usbd_status err; 3553 int len, isread, endpt; 3554 3555 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3556 xfer, xfer->length, xfer->flags)); 3557 3558 if (sc->sc_dying) 3559 return (USBD_IOERROR); 3560 3561 #ifdef DIAGNOSTIC 3562 if (xfer->rqflags & URQ_REQUEST) 3563 panic("ehci_device_bulk_start: a request"); 3564 #endif 3565 3566 mutex_enter(&sc->sc_lock); 3567 3568 len = xfer->length; 3569 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3570 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3571 sqh = epipe->sqh; 3572 3573 epipe->u.bulk.length = len; 3574 3575 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3576 &dataend); 3577 if (err) { 3578 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3579 xfer->status = err; 3580 usb_transfer_complete(xfer); 3581 mutex_exit(&sc->sc_lock); 3582 return (err); 3583 } 3584 3585 #ifdef EHCI_DEBUG 3586 if (ehcidebug > 5) { 3587 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3588 ehci_dump_sqh(sqh); 3589 ehci_dump_sqtds(data); 3590 } 3591 #endif 3592 3593 /* Set up interrupt info. */ 3594 exfer->sqtdstart = data; 3595 exfer->sqtdend = dataend; 3596 #ifdef DIAGNOSTIC 3597 if (!exfer->isdone) { 3598 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3599 } 3600 exfer->isdone = 0; 3601 #endif 3602 3603 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3604 if (xfer->timeout && !sc->sc_bus.use_polling) { 3605 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3606 ehci_timeout, xfer); 3607 } 3608 ehci_add_intr_list(sc, exfer); 3609 xfer->status = USBD_IN_PROGRESS; 3610 mutex_exit(&sc->sc_lock); 3611 3612 #ifdef EHCI_DEBUG 3613 if (ehcidebug > 10) { 3614 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3615 delay(10000); 3616 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3617 ehci_dump_regs(sc); 3618 #if 0 3619 printf("async_head:\n"); 3620 ehci_dump_sqh(sc->sc_async_head); 3621 #endif 3622 printf("sqh:\n"); 3623 ehci_dump_sqh(sqh); 3624 ehci_dump_sqtds(data); 3625 } 3626 #endif 3627 3628 if (sc->sc_bus.use_polling) 3629 ehci_waitintr(sc, xfer); 3630 3631 return (USBD_IN_PROGRESS); 3632 #undef exfer 3633 } 3634 3635 Static void 3636 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3637 { 3638 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3639 ehci_abort_xfer(xfer, USBD_CANCELLED); 3640 } 3641 3642 /* 3643 * Close a device bulk pipe. 3644 */ 3645 Static void 3646 ehci_device_bulk_close(usbd_pipe_handle pipe) 3647 { 3648 ehci_softc_t *sc = pipe->device->bus->hci_private; 3649 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3650 3651 KASSERT(mutex_owned(&sc->sc_lock)); 3652 3653 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3654 pipe->endpoint->datatoggle = epipe->nexttoggle; 3655 ehci_close_pipe(pipe, sc->sc_async_head); 3656 } 3657 3658 Static void 3659 ehci_device_bulk_done(usbd_xfer_handle xfer) 3660 { 3661 struct ehci_xfer *ex = EXFER(xfer); 3662 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3663 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3664 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3665 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3666 3667 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3668 xfer, xfer->actlen)); 3669 3670 KASSERT(mutex_owned(&sc->sc_lock)); 3671 3672 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3673 ehci_del_intr_list(sc, ex); /* remove from active list */ 3674 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3675 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3676 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3677 } 3678 3679 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3680 } 3681 3682 /************************/ 3683 3684 Static usbd_status 3685 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3686 { 3687 struct ehci_soft_islot *isp; 3688 int islot, lev; 3689 3690 /* Find a poll rate that is large enough. */ 3691 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3692 if (EHCI_ILEV_IVAL(lev) <= ival) 3693 break; 3694 3695 /* Pick an interrupt slot at the right level. */ 3696 /* XXX could do better than picking at random */ 3697 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3698 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3699 3700 sqh->islot = islot; 3701 isp = &sc->sc_islots[islot]; 3702 mutex_enter(&sc->sc_lock); 3703 ehci_add_qh(sc, sqh, isp->sqh); 3704 mutex_exit(&sc->sc_lock); 3705 3706 return (USBD_NORMAL_COMPLETION); 3707 } 3708 3709 Static usbd_status 3710 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3711 { 3712 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3713 usbd_status err; 3714 3715 /* Insert last in queue. */ 3716 mutex_enter(&sc->sc_lock); 3717 err = usb_insert_transfer(xfer); 3718 mutex_exit(&sc->sc_lock); 3719 if (err) 3720 return (err); 3721 3722 /* 3723 * Pipe isn't running (otherwise err would be USBD_INPROG), 3724 * so start it first. 3725 */ 3726 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3727 } 3728 3729 Static usbd_status 3730 ehci_device_intr_start(usbd_xfer_handle xfer) 3731 { 3732 #define exfer EXFER(xfer) 3733 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3734 usbd_device_handle dev = xfer->pipe->device; 3735 ehci_softc_t *sc = dev->bus->hci_private; 3736 ehci_soft_qtd_t *data, *dataend; 3737 ehci_soft_qh_t *sqh; 3738 usbd_status err; 3739 int len, isread, endpt; 3740 3741 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3742 xfer, xfer->length, xfer->flags)); 3743 3744 if (sc->sc_dying) 3745 return (USBD_IOERROR); 3746 3747 #ifdef DIAGNOSTIC 3748 if (xfer->rqflags & URQ_REQUEST) 3749 panic("ehci_device_intr_start: a request"); 3750 #endif 3751 3752 mutex_enter(&sc->sc_lock); 3753 3754 len = xfer->length; 3755 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3756 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3757 sqh = epipe->sqh; 3758 3759 epipe->u.intr.length = len; 3760 3761 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3762 &dataend); 3763 if (err) { 3764 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3765 xfer->status = err; 3766 usb_transfer_complete(xfer); 3767 mutex_exit(&sc->sc_lock); 3768 return (err); 3769 } 3770 3771 #ifdef EHCI_DEBUG 3772 if (ehcidebug > 5) { 3773 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3774 ehci_dump_sqh(sqh); 3775 ehci_dump_sqtds(data); 3776 } 3777 #endif 3778 3779 /* Set up interrupt info. */ 3780 exfer->sqtdstart = data; 3781 exfer->sqtdend = dataend; 3782 #ifdef DIAGNOSTIC 3783 if (!exfer->isdone) { 3784 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3785 } 3786 exfer->isdone = 0; 3787 #endif 3788 3789 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3790 if (xfer->timeout && !sc->sc_bus.use_polling) { 3791 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3792 ehci_timeout, xfer); 3793 } 3794 ehci_add_intr_list(sc, exfer); 3795 xfer->status = USBD_IN_PROGRESS; 3796 mutex_exit(&sc->sc_lock); 3797 3798 #ifdef EHCI_DEBUG 3799 if (ehcidebug > 10) { 3800 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3801 delay(10000); 3802 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3803 ehci_dump_regs(sc); 3804 printf("sqh:\n"); 3805 ehci_dump_sqh(sqh); 3806 ehci_dump_sqtds(data); 3807 } 3808 #endif 3809 3810 if (sc->sc_bus.use_polling) 3811 ehci_waitintr(sc, xfer); 3812 3813 return (USBD_IN_PROGRESS); 3814 #undef exfer 3815 } 3816 3817 Static void 3818 ehci_device_intr_abort(usbd_xfer_handle xfer) 3819 { 3820 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3821 if (xfer->pipe->intrxfer == xfer) { 3822 DPRINTFN(1, ("echi_device_intr_abort: remove\n")); 3823 xfer->pipe->intrxfer = NULL; 3824 } 3825 /* 3826 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3827 * async doorbell. That's dependent on the async list, wheras 3828 * intr xfers are periodic, should not use this? 3829 */ 3830 ehci_abort_xfer(xfer, USBD_CANCELLED); 3831 } 3832 3833 Static void 3834 ehci_device_intr_close(usbd_pipe_handle pipe) 3835 { 3836 ehci_softc_t *sc = pipe->device->bus->hci_private; 3837 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3838 struct ehci_soft_islot *isp; 3839 3840 KASSERT(mutex_owned(&sc->sc_lock)); 3841 3842 isp = &sc->sc_islots[epipe->sqh->islot]; 3843 ehci_close_pipe(pipe, isp->sqh); 3844 } 3845 3846 Static void 3847 ehci_device_intr_done(usbd_xfer_handle xfer) 3848 { 3849 #define exfer EXFER(xfer) 3850 struct ehci_xfer *ex = EXFER(xfer); 3851 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3852 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3853 ehci_soft_qtd_t *data, *dataend; 3854 ehci_soft_qh_t *sqh; 3855 usbd_status err; 3856 int len, isread, endpt; 3857 3858 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3859 xfer, xfer->actlen)); 3860 3861 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 3862 3863 if (xfer->pipe->repeat) { 3864 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3865 3866 len = epipe->u.intr.length; 3867 xfer->length = len; 3868 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3869 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3870 usb_syncmem(&xfer->dmabuf, 0, len, 3871 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3872 sqh = epipe->sqh; 3873 3874 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3875 &data, &dataend); 3876 if (err) { 3877 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3878 xfer->status = err; 3879 return; 3880 } 3881 3882 /* Set up interrupt info. */ 3883 exfer->sqtdstart = data; 3884 exfer->sqtdend = dataend; 3885 #ifdef DIAGNOSTIC 3886 if (!exfer->isdone) { 3887 printf("ehci_device_intr_done: not done, ex=%p\n", 3888 exfer); 3889 } 3890 exfer->isdone = 0; 3891 #endif 3892 3893 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3894 if (xfer->timeout && !sc->sc_bus.use_polling) { 3895 callout_reset(&xfer->timeout_handle, 3896 mstohz(xfer->timeout), ehci_timeout, xfer); 3897 } 3898 3899 xfer->status = USBD_IN_PROGRESS; 3900 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3901 ehci_del_intr_list(sc, ex); /* remove from active list */ 3902 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3903 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3904 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3905 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3906 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3907 } 3908 #undef exfer 3909 } 3910 3911 /************************/ 3912 3913 Static usbd_status 3914 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3915 { 3916 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3917 usbd_status err; 3918 3919 mutex_enter(&sc->sc_lock); 3920 err = usb_insert_transfer(xfer); 3921 mutex_exit(&sc->sc_lock); 3922 if (err && err != USBD_IN_PROGRESS) 3923 return err; 3924 3925 return ehci_device_isoc_start(xfer); 3926 } 3927 3928 Static usbd_status 3929 ehci_device_isoc_start(usbd_xfer_handle xfer) 3930 { 3931 struct ehci_pipe *epipe; 3932 ehci_softc_t *sc; 3933 struct ehci_xfer *exfer; 3934 ehci_soft_itd_t *itd, *prev, *start, *stop; 3935 usb_dma_t *dma_buf; 3936 int i, j, k, frames, uframes, ufrperframe; 3937 int trans_count, offs, total_length; 3938 int frindex; 3939 3940 start = NULL; 3941 prev = NULL; 3942 itd = NULL; 3943 trans_count = 0; 3944 total_length = 0; 3945 exfer = (struct ehci_xfer *) xfer; 3946 sc = xfer->pipe->device->bus->hci_private; 3947 epipe = (struct ehci_pipe *)xfer->pipe; 3948 3949 /* 3950 * To allow continuous transfers, above we start all transfers 3951 * immediately. However, we're still going to get usbd_start_next call 3952 * this when another xfer completes. So, check if this is already 3953 * in progress or not 3954 */ 3955 3956 if (exfer->itdstart != NULL) 3957 return USBD_IN_PROGRESS; 3958 3959 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3960 xfer, xfer->length, xfer->flags)); 3961 3962 if (sc->sc_dying) 3963 return USBD_IOERROR; 3964 3965 /* 3966 * To avoid complication, don't allow a request right now that'll span 3967 * the entire frame table. To within 4 frames, to allow some leeway 3968 * on either side of where the hc currently is. 3969 */ 3970 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3971 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3972 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3973 return USBD_INVAL; 3974 } 3975 3976 #ifdef DIAGNOSTIC 3977 if (xfer->rqflags & URQ_REQUEST) 3978 panic("ehci_device_isoc_start: request\n"); 3979 3980 if (!exfer->isdone) 3981 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3982 exfer->isdone = 0; 3983 #endif 3984 3985 /* 3986 * Step 1: Allocate and initialize itds, how many do we need? 3987 * One per transfer if interval >= 8 microframes, fewer if we use 3988 * multiple microframes per frame. 3989 */ 3990 3991 i = epipe->pipe.endpoint->edesc->bInterval; 3992 if (i > 16 || i == 0) { 3993 /* Spec page 271 says intervals > 16 are invalid */ 3994 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 3995 return USBD_INVAL; 3996 } 3997 3998 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 3999 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4000 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4001 4002 if (frames == 0) { 4003 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 4004 return USBD_INVAL; 4005 } 4006 4007 dma_buf = &xfer->dmabuf; 4008 offs = 0; 4009 4010 for (i = 0; i < frames; i++) { 4011 int froffs = offs; 4012 itd = ehci_alloc_itd(sc); 4013 4014 if (prev != NULL) { 4015 prev->itd.itd_next = 4016 htole32(itd->physaddr | EHCI_LINK_ITD); 4017 usb_syncmem(&itd->dma, 4018 itd->offs + offsetof(ehci_itd_t, itd_next), 4019 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4020 4021 prev->xfer_next = itd; 4022 } else { 4023 start = itd; 4024 } 4025 4026 /* 4027 * Step 1.5, initialize uframes 4028 */ 4029 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4030 /* Calculate which page in the list this starts in */ 4031 int addr = DMAADDR(dma_buf, froffs); 4032 addr = EHCI_PAGE_OFFSET(addr); 4033 addr += (offs - froffs); 4034 addr = EHCI_PAGE(addr); 4035 addr /= EHCI_PAGE_SIZE; 4036 4037 /* This gets the initial offset into the first page, 4038 * looks how far further along the current uframe 4039 * offset is. Works out how many pages that is. 4040 */ 4041 4042 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4043 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4044 EHCI_ITD_SET_PG(addr) | 4045 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4046 4047 total_length += xfer->frlengths[trans_count]; 4048 offs += xfer->frlengths[trans_count]; 4049 trans_count++; 4050 4051 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4052 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4053 break; 4054 } 4055 } 4056 4057 /* Step 1.75, set buffer pointers. To simplify matters, all 4058 * pointers are filled out for the next 7 hardware pages in 4059 * the dma block, so no need to worry what pages to cover 4060 * and what to not. 4061 */ 4062 4063 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4064 /* 4065 * Don't try to lookup a page that's past the end 4066 * of buffer 4067 */ 4068 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4069 if (page_offs >= dma_buf->block->size) 4070 break; 4071 4072 unsigned long long page = DMAADDR(dma_buf, page_offs); 4073 page = EHCI_PAGE(page); 4074 itd->itd.itd_bufr[j] = 4075 htole32(EHCI_ITD_SET_BPTR(page)); 4076 itd->itd.itd_bufr_hi[j] = 4077 htole32(page >> 32); 4078 } 4079 4080 /* 4081 * Other special values 4082 */ 4083 4084 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4085 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4086 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4087 4088 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4089 ? 1 : 0; 4090 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4091 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4092 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4093 4094 /* FIXME: handle invalid trans */ 4095 itd->itd.itd_bufr[2] |= 4096 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4097 4098 usb_syncmem(&itd->dma, 4099 itd->offs + offsetof(ehci_itd_t, itd_next), 4100 sizeof(ehci_itd_t), 4101 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4102 4103 prev = itd; 4104 } /* End of frame */ 4105 4106 stop = itd; 4107 stop->xfer_next = NULL; 4108 exfer->isoc_len = total_length; 4109 4110 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4111 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4112 4113 /* 4114 * Part 2: Transfer descriptors have now been set up, now they must 4115 * be scheduled into the period frame list. Erk. Not wanting to 4116 * complicate matters, transfer is denied if the transfer spans 4117 * more than the period frame list. 4118 */ 4119 4120 mutex_enter(&sc->sc_lock); 4121 4122 /* Start inserting frames */ 4123 if (epipe->u.isoc.cur_xfers > 0) { 4124 frindex = epipe->u.isoc.next_frame; 4125 } else { 4126 frindex = EOREAD4(sc, EHCI_FRINDEX); 4127 frindex = frindex >> 3; /* Erase microframe index */ 4128 frindex += 2; 4129 } 4130 4131 if (frindex >= sc->sc_flsize) 4132 frindex &= (sc->sc_flsize - 1); 4133 4134 /* What's the frame interval? */ 4135 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4136 if (i / USB_UFRAMES_PER_FRAME == 0) 4137 i = 1; 4138 else 4139 i /= USB_UFRAMES_PER_FRAME; 4140 4141 itd = start; 4142 for (j = 0; j < frames; j++) { 4143 if (itd == NULL) 4144 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4145 4146 itd->itd.itd_next = sc->sc_flist[frindex]; 4147 if (itd->itd.itd_next == 0) 4148 /* FIXME: frindex table gets initialized to NULL 4149 * or EHCI_NULL? */ 4150 itd->itd.itd_next = EHCI_NULL; 4151 4152 usb_syncmem(&itd->dma, 4153 itd->offs + offsetof(ehci_itd_t, itd_next), 4154 sizeof(itd->itd.itd_next), 4155 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4156 4157 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4158 4159 usb_syncmem(&sc->sc_fldma, 4160 sizeof(ehci_link_t) * frindex, 4161 sizeof(ehci_link_t), 4162 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4163 4164 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4165 sc->sc_softitds[frindex] = itd; 4166 if (itd->u.frame_list.next != NULL) 4167 itd->u.frame_list.next->u.frame_list.prev = itd; 4168 itd->slot = frindex; 4169 itd->u.frame_list.prev = NULL; 4170 4171 frindex += i; 4172 if (frindex >= sc->sc_flsize) 4173 frindex -= sc->sc_flsize; 4174 4175 itd = itd->xfer_next; 4176 } 4177 4178 epipe->u.isoc.cur_xfers++; 4179 epipe->u.isoc.next_frame = frindex; 4180 4181 exfer->itdstart = start; 4182 exfer->itdend = stop; 4183 exfer->sqtdstart = NULL; 4184 exfer->sqtdstart = NULL; 4185 4186 ehci_add_intr_list(sc, exfer); 4187 xfer->status = USBD_IN_PROGRESS; 4188 xfer->done = 0; 4189 mutex_exit(&sc->sc_lock); 4190 4191 if (sc->sc_bus.use_polling) { 4192 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4193 ehci_waitintr(sc, xfer); 4194 } 4195 4196 return USBD_IN_PROGRESS; 4197 } 4198 4199 Static void 4200 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4201 { 4202 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4203 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4204 } 4205 4206 Static void 4207 ehci_device_isoc_close(usbd_pipe_handle pipe) 4208 { 4209 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4210 } 4211 4212 Static void 4213 ehci_device_isoc_done(usbd_xfer_handle xfer) 4214 { 4215 struct ehci_xfer *exfer; 4216 ehci_softc_t *sc; 4217 struct ehci_pipe *epipe; 4218 4219 exfer = EXFER(xfer); 4220 sc = xfer->pipe->device->bus->hci_private; 4221 epipe = (struct ehci_pipe *) xfer->pipe; 4222 4223 KASSERT(mutex_owned(&sc->sc_lock)); 4224 4225 epipe->u.isoc.cur_xfers--; 4226 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4227 ehci_del_intr_list(sc, exfer); 4228 ehci_rem_free_itd_chain(sc, exfer); 4229 } 4230 4231 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4232 BUS_DMASYNC_POSTREAD); 4233 4234 } 4235
Indexes created Wed Sep 24 22:09:59 GMT 2025