ehci.c revision 1.227
1 /* $NetBSD: ehci.c,v 1.227 2014/08/05 06:35:24 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.227 2014/08/05 06:35:24 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #include <sys/param.h> 62 #include <sys/systm.h> 63 #include <sys/kernel.h> 64 #include <sys/kmem.h> 65 #include <sys/device.h> 66 #include <sys/select.h> 67 #include <sys/proc.h> 68 #include <sys/queue.h> 69 #include <sys/mutex.h> 70 #include <sys/bus.h> 71 #include <sys/cpu.h> 72 73 #include <machine/endian.h> 74 75 #include <dev/usb/usb.h> 76 #include <dev/usb/usbdi.h> 77 #include <dev/usb/usbdivar.h> 78 #include <dev/usb/usb_mem.h> 79 #include <dev/usb/usb_quirks.h> 80 81 #include <dev/usb/ehcireg.h> 82 #include <dev/usb/ehcivar.h> 83 #include <dev/usb/usbroothub_subr.h> 84 85 #ifdef EHCI_DEBUG 86 static void __printflike(1, 2) 87 ehciprintf(const char *fmt, ...) 88 { 89 va_list ap; 90 91 va_start(ap, fmt); 92 vprintf(fmt, ap); 93 va_end(ap); 94 } 95 96 #define DPRINTF(x) do { if (ehcidebug) ehciprintf x; } while(0) 97 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) ehciprintf x; } while (0) 98 int ehcidebug = 0; 99 #else 100 #define DPRINTF(x) 101 #define DPRINTFN(n,x) 102 #endif 103 104 struct ehci_pipe { 105 struct usbd_pipe pipe; 106 int nexttoggle; 107 108 ehci_soft_qh_t *sqh; 109 union { 110 ehci_soft_qtd_t *qtd; 111 /* ehci_soft_itd_t *itd; */ 112 } tail; 113 union { 114 /* Control pipe */ 115 struct { 116 usb_dma_t reqdma; 117 } ctl; 118 /* Interrupt pipe */ 119 struct { 120 u_int length; 121 } intr; 122 /* Bulk pipe */ 123 struct { 124 u_int length; 125 } bulk; 126 /* Iso pipe */ 127 struct { 128 u_int next_frame; 129 u_int cur_xfers; 130 } isoc; 131 } u; 132 }; 133 134 Static usbd_status ehci_open(usbd_pipe_handle); 135 Static void ehci_poll(struct usbd_bus *); 136 Static void ehci_softintr(void *); 137 Static int ehci_intr1(ehci_softc_t *); 138 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 139 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 140 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 141 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 142 Static void ehci_idone(struct ehci_xfer *); 143 Static void ehci_timeout(void *); 144 Static void ehci_timeout_task(void *); 145 Static void ehci_intrlist_timeout(void *); 146 Static void ehci_doorbell(void *); 147 Static void ehci_pcd(void *); 148 149 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 150 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 151 152 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 153 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 154 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 155 156 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 157 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 158 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 159 Static void ehci_root_ctrl_close(usbd_pipe_handle); 160 Static void ehci_root_ctrl_done(usbd_xfer_handle); 161 162 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 163 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 164 Static void ehci_root_intr_abort(usbd_xfer_handle); 165 Static void ehci_root_intr_close(usbd_pipe_handle); 166 Static void ehci_root_intr_done(usbd_xfer_handle); 167 168 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 169 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 170 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 171 Static void ehci_device_ctrl_close(usbd_pipe_handle); 172 Static void ehci_device_ctrl_done(usbd_xfer_handle); 173 174 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 175 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 176 Static void ehci_device_bulk_abort(usbd_xfer_handle); 177 Static void ehci_device_bulk_close(usbd_pipe_handle); 178 Static void ehci_device_bulk_done(usbd_xfer_handle); 179 180 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 181 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 182 Static void ehci_device_intr_abort(usbd_xfer_handle); 183 Static void ehci_device_intr_close(usbd_pipe_handle); 184 Static void ehci_device_intr_done(usbd_xfer_handle); 185 186 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 187 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 188 Static void ehci_device_isoc_abort(usbd_xfer_handle); 189 Static void ehci_device_isoc_close(usbd_pipe_handle); 190 Static void ehci_device_isoc_done(usbd_xfer_handle); 191 192 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 193 Static void ehci_noop(usbd_pipe_handle pipe); 194 195 Static void ehci_disown(ehci_softc_t *, int, int); 196 197 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 198 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 199 200 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 201 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 202 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 203 ehci_softc_t *, int, int, usbd_xfer_handle, 204 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 205 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 206 ehci_soft_qtd_t *); 207 208 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 209 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 210 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 211 struct ehci_xfer *exfer); 212 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 213 usbd_status status); 214 215 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 216 217 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 218 int ival); 219 220 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 221 ehci_soft_qh_t *); 222 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 223 ehci_soft_qh_t *); 224 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 225 Static void ehci_sync_hc(ehci_softc_t *); 226 227 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 228 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 229 230 #ifdef EHCI_DEBUG 231 Static void ehci_dump_regs(ehci_softc_t *); 232 void ehci_dump(void); 233 Static ehci_softc_t *theehci; 234 Static void ehci_dump_link(ehci_link_t, int); 235 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 236 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 237 Static void ehci_dump_qtd(ehci_qtd_t *); 238 Static void ehci_dump_sqh(ehci_soft_qh_t *); 239 #if notyet 240 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 241 Static void ehci_dump_itd(struct ehci_soft_itd *); 242 #endif 243 #ifdef DIAGNOSTIC 244 Static void ehci_dump_exfer(struct ehci_xfer *); 245 #endif 246 #endif 247 248 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 249 250 #define EHCI_INTR_ENDPT 1 251 252 #define ehci_add_intr_list(sc, ex) \ 253 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 254 #define ehci_del_intr_list(sc, ex) \ 255 do { \ 256 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 257 (ex)->inext.tqe_prev = NULL; \ 258 } while (0) 259 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 260 261 Static const struct usbd_bus_methods ehci_bus_methods = { 262 .open_pipe = ehci_open, 263 .soft_intr = ehci_softintr, 264 .do_poll = ehci_poll, 265 .allocm = ehci_allocm, 266 .freem = ehci_freem, 267 .allocx = ehci_allocx, 268 .freex = ehci_freex, 269 .get_lock = ehci_get_lock, 270 .new_device = NULL, 271 }; 272 273 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 274 .transfer = ehci_root_ctrl_transfer, 275 .start = ehci_root_ctrl_start, 276 .abort = ehci_root_ctrl_abort, 277 .close = ehci_root_ctrl_close, 278 .cleartoggle = ehci_noop, 279 .done = ehci_root_ctrl_done, 280 }; 281 282 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 283 .transfer = ehci_root_intr_transfer, 284 .start = ehci_root_intr_start, 285 .abort = ehci_root_intr_abort, 286 .close = ehci_root_intr_close, 287 .cleartoggle = ehci_noop, 288 .done = ehci_root_intr_done, 289 }; 290 291 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 292 .transfer = ehci_device_ctrl_transfer, 293 .start = ehci_device_ctrl_start, 294 .abort = ehci_device_ctrl_abort, 295 .close = ehci_device_ctrl_close, 296 .cleartoggle = ehci_noop, 297 .done = ehci_device_ctrl_done, 298 }; 299 300 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 301 .transfer = ehci_device_intr_transfer, 302 .start = ehci_device_intr_start, 303 .abort = ehci_device_intr_abort, 304 .close = ehci_device_intr_close, 305 .cleartoggle = ehci_device_clear_toggle, 306 .done = ehci_device_intr_done, 307 }; 308 309 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 310 .transfer = ehci_device_bulk_transfer, 311 .start = ehci_device_bulk_start, 312 .abort = ehci_device_bulk_abort, 313 .close = ehci_device_bulk_close, 314 .cleartoggle = ehci_device_clear_toggle, 315 .done = ehci_device_bulk_done, 316 }; 317 318 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 319 .transfer = ehci_device_isoc_transfer, 320 .start = ehci_device_isoc_start, 321 .abort = ehci_device_isoc_abort, 322 .close = ehci_device_isoc_close, 323 .cleartoggle = ehci_noop, 324 .done = ehci_device_isoc_done, 325 }; 326 327 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 328 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 329 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 330 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 331 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 332 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 333 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 334 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 335 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 336 }; 337 338 usbd_status 339 ehci_init(ehci_softc_t *sc) 340 { 341 u_int32_t vers, sparams, cparams, hcr; 342 u_int i; 343 usbd_status err; 344 ehci_soft_qh_t *sqh; 345 u_int ncomp; 346 347 DPRINTF(("ehci_init: start\n")); 348 #ifdef EHCI_DEBUG 349 theehci = sc; 350 #endif 351 352 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 353 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 354 cv_init(&sc->sc_softwake_cv, "ehciab"); 355 cv_init(&sc->sc_doorbell, "ehcidi"); 356 357 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 358 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 359 360 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 361 ehci_doorbell, sc); 362 KASSERT(sc->sc_doorbell_si != NULL); 363 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 364 ehci_pcd, sc); 365 KASSERT(sc->sc_pcd_si != NULL); 366 367 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 368 369 vers = EREAD2(sc, EHCI_HCIVERSION); 370 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 371 vers >> 8, vers & 0xff); 372 373 sparams = EREAD4(sc, EHCI_HCSPARAMS); 374 DPRINTF(("ehci_init: sparams=0x%x\n", sparams)); 375 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 376 ncomp = EHCI_HCS_N_CC(sparams); 377 if (ncomp != sc->sc_ncomp) { 378 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 379 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 380 #if NOHCI == 0 || NUHCI == 0 381 aprint_error("%s: ohci or uhci probably not configured\n", 382 device_xname(sc->sc_dev)); 383 #endif 384 if (ncomp < sc->sc_ncomp) 385 sc->sc_ncomp = ncomp; 386 } 387 if (sc->sc_ncomp > 0) { 388 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 389 aprint_normal("%s: companion controller%s, %d port%s each:", 390 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 391 EHCI_HCS_N_PCC(sparams), 392 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 393 for (i = 0; i < sc->sc_ncomp; i++) 394 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 395 aprint_normal("\n"); 396 } 397 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 398 cparams = EREAD4(sc, EHCI_HCCPARAMS); 399 DPRINTF(("ehci_init: cparams=0x%x\n", cparams)); 400 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 401 402 if (EHCI_HCC_64BIT(cparams)) { 403 /* MUST clear segment register if 64 bit capable. */ 404 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 405 } 406 407 sc->sc_bus.usbrev = USBREV_2_0; 408 409 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 410 USB_MEM_RESERVE); 411 412 /* Reset the controller */ 413 DPRINTF(("%s: resetting\n", device_xname(sc->sc_dev))); 414 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 415 usb_delay_ms(&sc->sc_bus, 1); 416 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 417 for (i = 0; i < 100; i++) { 418 usb_delay_ms(&sc->sc_bus, 1); 419 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 420 if (!hcr) 421 break; 422 } 423 if (hcr) { 424 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 425 return (USBD_IOERROR); 426 } 427 if (sc->sc_vendor_init) 428 sc->sc_vendor_init(sc); 429 430 /* 431 * If we are doing embedded transaction translation function, force 432 * the controller to host mode. 433 */ 434 if (sc->sc_flags & EHCIF_ETTF) { 435 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 436 usbmode &= ~EHCI_USBMODE_CM; 437 usbmode |= EHCI_USBMODE_CM_HOST; 438 EWRITE4(sc, EHCI_USBMODE, usbmode); 439 } 440 441 /* XXX need proper intr scheduling */ 442 sc->sc_rand = 96; 443 444 /* frame list size at default, read back what we got and use that */ 445 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 446 case 0: sc->sc_flsize = 1024; break; 447 case 1: sc->sc_flsize = 512; break; 448 case 2: sc->sc_flsize = 256; break; 449 case 3: return (USBD_IOERROR); 450 } 451 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 452 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 453 if (err) 454 return (err); 455 DPRINTF(("%s: flsize=%d\n", device_xname(sc->sc_dev),sc->sc_flsize)); 456 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 457 458 for (i = 0; i < sc->sc_flsize; i++) { 459 sc->sc_flist[i] = EHCI_NULL; 460 } 461 462 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 463 464 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 465 KM_SLEEP); 466 if (sc->sc_softitds == NULL) 467 return ENOMEM; 468 LIST_INIT(&sc->sc_freeitds); 469 TAILQ_INIT(&sc->sc_intrhead); 470 471 /* Set up the bus struct. */ 472 sc->sc_bus.methods = &ehci_bus_methods; 473 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 474 475 sc->sc_eintrs = EHCI_NORMAL_INTRS; 476 477 /* 478 * Allocate the interrupt dummy QHs. These are arranged to give poll 479 * intervals that are powers of 2 times 1ms. 480 */ 481 for (i = 0; i < EHCI_INTRQHS; i++) { 482 sqh = ehci_alloc_sqh(sc); 483 if (sqh == NULL) { 484 err = USBD_NOMEM; 485 goto bad1; 486 } 487 sc->sc_islots[i].sqh = sqh; 488 } 489 for (i = 0; i < EHCI_INTRQHS; i++) { 490 sqh = sc->sc_islots[i].sqh; 491 if (i == 0) { 492 /* The last (1ms) QH terminates. */ 493 sqh->qh.qh_link = EHCI_NULL; 494 sqh->next = NULL; 495 } else { 496 /* Otherwise the next QH has half the poll interval */ 497 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 498 sqh->qh.qh_link = htole32(sqh->next->physaddr | 499 EHCI_LINK_QH); 500 } 501 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 502 sqh->qh.qh_curqtd = EHCI_NULL; 503 sqh->next = NULL; 504 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 505 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 506 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 507 sqh->sqtd = NULL; 508 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 509 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 510 } 511 /* Point the frame list at the last level (128ms). */ 512 for (i = 0; i < sc->sc_flsize; i++) { 513 int j; 514 515 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 516 revbits[i & (EHCI_MAX_POLLRATE-1)]; 517 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 518 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 519 i)].sqh->physaddr); 520 } 521 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 522 BUS_DMASYNC_PREWRITE); 523 524 /* Allocate dummy QH that starts the async list. */ 525 sqh = ehci_alloc_sqh(sc); 526 if (sqh == NULL) { 527 err = USBD_NOMEM; 528 goto bad1; 529 } 530 /* Fill the QH */ 531 sqh->qh.qh_endp = 532 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 533 sqh->qh.qh_link = 534 htole32(sqh->physaddr | EHCI_LINK_QH); 535 sqh->qh.qh_curqtd = EHCI_NULL; 536 sqh->next = NULL; 537 /* Fill the overlay qTD */ 538 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 539 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 540 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 541 sqh->sqtd = NULL; 542 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 543 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 544 #ifdef EHCI_DEBUG 545 if (ehcidebug) { 546 ehci_dump_sqh(sqh); 547 } 548 #endif 549 550 /* Point to async list */ 551 sc->sc_async_head = sqh; 552 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 553 554 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 555 556 /* Turn on controller */ 557 EOWRITE4(sc, EHCI_USBCMD, 558 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 559 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 560 EHCI_CMD_ASE | 561 EHCI_CMD_PSE | 562 EHCI_CMD_RS); 563 564 /* Take over port ownership */ 565 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 566 567 for (i = 0; i < 100; i++) { 568 usb_delay_ms(&sc->sc_bus, 1); 569 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 570 if (!hcr) 571 break; 572 } 573 if (hcr) { 574 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 575 return (USBD_IOERROR); 576 } 577 578 /* Enable interrupts */ 579 DPRINTFN(1,("ehci_init: enabling\n")); 580 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 581 582 return (USBD_NORMAL_COMPLETION); 583 584 #if 0 585 bad2: 586 ehci_free_sqh(sc, sc->sc_async_head); 587 #endif 588 bad1: 589 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 590 return (err); 591 } 592 593 int 594 ehci_intr(void *v) 595 { 596 ehci_softc_t *sc = v; 597 int ret = 0; 598 599 if (sc == NULL) 600 return 0; 601 602 mutex_spin_enter(&sc->sc_intr_lock); 603 604 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 605 goto done; 606 607 /* If we get an interrupt while polling, then just ignore it. */ 608 if (sc->sc_bus.use_polling) { 609 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 610 611 if (intrs) 612 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 613 #ifdef DIAGNOSTIC 614 DPRINTFN(16, ("ehci_intr: ignored interrupt while polling\n")); 615 #endif 616 goto done; 617 } 618 619 ret = ehci_intr1(sc); 620 621 done: 622 mutex_spin_exit(&sc->sc_intr_lock); 623 return ret; 624 } 625 626 Static int 627 ehci_intr1(ehci_softc_t *sc) 628 { 629 u_int32_t intrs, eintrs; 630 631 DPRINTFN(20,("ehci_intr1: enter\n")); 632 633 /* In case the interrupt occurs before initialization has completed. */ 634 if (sc == NULL) { 635 #ifdef DIAGNOSTIC 636 printf("ehci_intr1: sc == NULL\n"); 637 #endif 638 return (0); 639 } 640 641 KASSERT(mutex_owned(&sc->sc_intr_lock)); 642 643 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 644 if (!intrs) 645 return (0); 646 647 eintrs = intrs & sc->sc_eintrs; 648 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n", 649 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), 650 (u_int)eintrs)); 651 if (!eintrs) 652 return (0); 653 654 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 655 sc->sc_bus.no_intrs++; 656 if (eintrs & EHCI_STS_IAA) { 657 DPRINTF(("ehci_intr1: door bell\n")); 658 kpreempt_disable(); 659 KASSERT(sc->sc_doorbell_si != NULL); 660 softint_schedule(sc->sc_doorbell_si); 661 kpreempt_enable(); 662 eintrs &= ~EHCI_STS_IAA; 663 } 664 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 665 DPRINTFN(5,("ehci_intr1: %s %s\n", 666 eintrs & EHCI_STS_INT ? "INT" : "", 667 eintrs & EHCI_STS_ERRINT ? "ERRINT" : "")); 668 usb_schedsoftintr(&sc->sc_bus); 669 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 670 } 671 if (eintrs & EHCI_STS_HSE) { 672 printf("%s: unrecoverable error, controller halted\n", 673 device_xname(sc->sc_dev)); 674 /* XXX what else */ 675 } 676 if (eintrs & EHCI_STS_PCD) { 677 kpreempt_disable(); 678 KASSERT(sc->sc_pcd_si != NULL); 679 softint_schedule(sc->sc_pcd_si); 680 kpreempt_enable(); 681 eintrs &= ~EHCI_STS_PCD; 682 } 683 684 if (eintrs != 0) { 685 /* Block unprocessed interrupts. */ 686 sc->sc_eintrs &= ~eintrs; 687 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 688 printf("%s: blocking intrs 0x%x\n", 689 device_xname(sc->sc_dev), eintrs); 690 } 691 692 return (1); 693 } 694 695 Static void 696 ehci_doorbell(void *addr) 697 { 698 ehci_softc_t *sc = addr; 699 700 mutex_enter(&sc->sc_lock); 701 cv_broadcast(&sc->sc_doorbell); 702 mutex_exit(&sc->sc_lock); 703 } 704 705 Static void 706 ehci_pcd(void *addr) 707 { 708 ehci_softc_t *sc = addr; 709 usbd_xfer_handle xfer; 710 u_char *p; 711 int i, m; 712 713 mutex_enter(&sc->sc_lock); 714 xfer = sc->sc_intrxfer; 715 716 if (xfer == NULL) { 717 /* Just ignore the change. */ 718 goto done; 719 } 720 721 p = KERNADDR(&xfer->dmabuf, 0); 722 m = min(sc->sc_noport, xfer->length * 8 - 1); 723 memset(p, 0, xfer->length); 724 for (i = 1; i <= m; i++) { 725 /* Pick out CHANGE bits from the status reg. */ 726 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 727 p[i/8] |= 1 << (i%8); 728 } 729 DPRINTF(("ehci_pcd: change=0x%02x\n", *p)); 730 xfer->actlen = xfer->length; 731 xfer->status = USBD_NORMAL_COMPLETION; 732 733 usb_transfer_complete(xfer); 734 735 done: 736 mutex_exit(&sc->sc_lock); 737 } 738 739 Static void 740 ehci_softintr(void *v) 741 { 742 struct usbd_bus *bus = v; 743 ehci_softc_t *sc = bus->hci_private; 744 struct ehci_xfer *ex, *nextex; 745 746 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 747 748 DPRINTFN(10,("%s: ehci_softintr\n", device_xname(sc->sc_dev))); 749 750 /* 751 * The only explanation I can think of for why EHCI is as brain dead 752 * as UHCI interrupt-wise is that Intel was involved in both. 753 * An interrupt just tells us that something is done, we have no 754 * clue what, so we need to scan through all active transfers. :-( 755 */ 756 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 757 nextex = TAILQ_NEXT(ex, inext); 758 ehci_check_intr(sc, ex); 759 } 760 761 /* Schedule a callout to catch any dropped transactions. */ 762 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 763 !TAILQ_EMPTY(&sc->sc_intrhead)) 764 callout_reset(&sc->sc_tmo_intrlist, 765 hz, ehci_intrlist_timeout, sc); 766 767 if (sc->sc_softwake) { 768 sc->sc_softwake = 0; 769 cv_broadcast(&sc->sc_softwake_cv); 770 } 771 } 772 773 /* Check for an interrupt. */ 774 Static void 775 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 776 { 777 int attr; 778 779 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex)); 780 781 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 782 783 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 784 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 785 ehci_check_itd_intr(sc, ex); 786 else 787 ehci_check_qh_intr(sc, ex); 788 789 return; 790 } 791 792 Static void 793 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 794 { 795 ehci_soft_qtd_t *sqtd, *lsqtd; 796 __uint32_t status; 797 798 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 799 800 if (ex->sqtdstart == NULL) { 801 printf("ehci_check_qh_intr: not valid sqtd\n"); 802 return; 803 } 804 805 lsqtd = ex->sqtdend; 806 #ifdef DIAGNOSTIC 807 if (lsqtd == NULL) { 808 printf("ehci_check_qh_intr: lsqtd==0\n"); 809 return; 810 } 811 #endif 812 /* 813 * If the last TD is still active we need to check whether there 814 * is an error somewhere in the middle, or whether there was a 815 * short packet (SPD and not ACTIVE). 816 */ 817 usb_syncmem(&lsqtd->dma, 818 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 819 sizeof(lsqtd->qtd.qtd_status), 820 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 821 status = le32toh(lsqtd->qtd.qtd_status); 822 usb_syncmem(&lsqtd->dma, 823 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 824 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 825 if (status & EHCI_QTD_ACTIVE) { 826 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex)); 827 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 828 usb_syncmem(&sqtd->dma, 829 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 830 sizeof(sqtd->qtd.qtd_status), 831 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 832 status = le32toh(sqtd->qtd.qtd_status); 833 usb_syncmem(&sqtd->dma, 834 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 835 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 836 /* If there's an active QTD the xfer isn't done. */ 837 if (status & EHCI_QTD_ACTIVE) 838 break; 839 /* Any kind of error makes the xfer done. */ 840 if (status & EHCI_QTD_HALTED) 841 goto done; 842 /* Handle short packets */ 843 if (EHCI_QTD_GET_BYTES(status) != 0) { 844 usbd_pipe_handle pipe = ex->xfer.pipe; 845 usb_endpoint_descriptor_t *ed = 846 pipe->endpoint->edesc; 847 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 848 849 /* 850 * If we get here for a control transfer then 851 * we need to let the hardware complete the 852 * status phase. That is, we're not done 853 * quite yet. 854 * 855 * Otherwise, we're done. 856 */ 857 if (xt == UE_CONTROL) { 858 break; 859 } 860 goto done; 861 } 862 } 863 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n", 864 ex, ex->sqtdstart)); 865 return; 866 } 867 done: 868 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex)); 869 callout_stop(&ex->xfer.timeout_handle); 870 ehci_idone(ex); 871 } 872 873 Static void 874 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 875 { 876 ehci_soft_itd_t *itd; 877 int i; 878 879 KASSERT(mutex_owned(&sc->sc_lock)); 880 881 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 882 return; 883 884 if (ex->itdstart == NULL) { 885 printf("ehci_check_itd_intr: not valid itd\n"); 886 return; 887 } 888 889 itd = ex->itdend; 890 #ifdef DIAGNOSTIC 891 if (itd == NULL) { 892 printf("ehci_check_itd_intr: itdend == 0\n"); 893 return; 894 } 895 #endif 896 897 /* 898 * check no active transfers in last itd, meaning we're finished 899 */ 900 901 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 902 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 903 BUS_DMASYNC_POSTREAD); 904 905 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 906 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 907 break; 908 } 909 910 if (i == EHCI_ITD_NUFRAMES) { 911 goto done; /* All 8 descriptors inactive, it's done */ 912 } 913 914 DPRINTFN(12, ("ehci_check_itd_intr: ex %p itd %p still active\n", ex, 915 ex->itdstart)); 916 return; 917 done: 918 DPRINTFN(12, ("ehci_check_itd_intr: ex=%p done\n", ex)); 919 callout_stop(&ex->xfer.timeout_handle); 920 ehci_idone(ex); 921 } 922 923 Static void 924 ehci_idone(struct ehci_xfer *ex) 925 { 926 usbd_xfer_handle xfer = &ex->xfer; 927 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 928 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 929 ehci_soft_qtd_t *sqtd, *lsqtd; 930 u_int32_t status = 0, nstatus = 0; 931 int actlen; 932 933 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 934 935 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex)); 936 937 #ifdef DIAGNOSTIC 938 if (ex->isdone) { 939 printf("ehci_idone: ex=%p is done!\n", ex); 940 #ifdef EHCI_DEBUG 941 ehci_dump_exfer(ex); 942 #endif 943 return; 944 } 945 ex->isdone = 1; 946 #endif 947 948 if (xfer->status == USBD_CANCELLED || 949 xfer->status == USBD_TIMEOUT) { 950 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer)); 951 return; 952 } 953 954 #ifdef EHCI_DEBUG 955 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe)); 956 if (ehcidebug > 10) 957 ehci_dump_sqtds(ex->sqtdstart); 958 #endif 959 960 /* The transfer is done, compute actual length and status. */ 961 962 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 963 == UE_ISOCHRONOUS) { 964 /* Isoc transfer */ 965 struct ehci_soft_itd *itd; 966 int i, nframes, len, uframes; 967 968 nframes = 0; 969 actlen = 0; 970 971 i = xfer->pipe->endpoint->edesc->bInterval; 972 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 973 974 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 975 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 976 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 977 BUS_DMASYNC_POSTREAD); 978 979 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 980 /* XXX - driver didn't fill in the frame full 981 * of uframes. This leads to scheduling 982 * inefficiencies, but working around 983 * this doubles complexity of tracking 984 * an xfer. 985 */ 986 if (nframes >= xfer->nframes) 987 break; 988 989 status = le32toh(itd->itd.itd_ctl[i]); 990 len = EHCI_ITD_GET_LEN(status); 991 if (EHCI_ITD_GET_STATUS(status) != 0) 992 len = 0; /*No valid data on error*/ 993 994 xfer->frlengths[nframes++] = len; 995 actlen += len; 996 } 997 998 if (nframes >= xfer->nframes) 999 break; 1000 } 1001 1002 xfer->actlen = actlen; 1003 xfer->status = USBD_NORMAL_COMPLETION; 1004 goto end; 1005 } 1006 1007 /* Continue processing xfers using queue heads */ 1008 1009 lsqtd = ex->sqtdend; 1010 actlen = 0; 1011 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1012 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1013 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1014 nstatus = le32toh(sqtd->qtd.qtd_status); 1015 if (nstatus & EHCI_QTD_ACTIVE) 1016 break; 1017 1018 status = nstatus; 1019 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1020 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1021 } 1022 1023 1024 /* 1025 * If there are left over TDs we need to update the toggle. 1026 * The default pipe doesn't need it since control transfers 1027 * start the toggle at 0 every time. 1028 * For a short transfer we need to update the toggle for the missing 1029 * packets within the qTD. 1030 */ 1031 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1032 xfer->pipe->device->default_pipe != xfer->pipe) { 1033 DPRINTFN(2, ("ehci_idone: need toggle update " 1034 "status=%08x nstatus=%08x\n", status, nstatus)); 1035 #if 0 1036 ehci_dump_sqh(epipe->sqh); 1037 ehci_dump_sqtds(ex->sqtdstart); 1038 #endif 1039 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1040 } 1041 1042 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n", 1043 xfer->length, actlen, status)); 1044 xfer->actlen = actlen; 1045 if (status & EHCI_QTD_HALTED) { 1046 #ifdef EHCI_DEBUG 1047 char sbuf[128]; 1048 1049 snprintb(sbuf, sizeof(sbuf), 1050 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE" 1051 "\4XACTERR\3MISSED\2SPLIT\1PING", 1052 (u_int32_t)status); 1053 1054 DPRINTFN(2, ("%s: error, addr=%d, endpt=0x%02x, " 1055 "cerr=%d pid=%d stat=%s\n", __func__, 1056 xfer->pipe->device->address, 1057 xfer->pipe->endpoint->edesc->bEndpointAddress, 1058 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), sbuf)); 1059 1060 if (ehcidebug > 2) { 1061 ehci_dump_sqh(epipe->sqh); 1062 ehci_dump_sqtds(ex->sqtdstart); 1063 } 1064 #endif 1065 /* low&full speed has an extra error flag */ 1066 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1067 EHCI_QH_SPEED_HIGH) 1068 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1069 else 1070 status &= EHCI_QTD_STATERRS; 1071 if (status == 0) /* no other errors means a stall */ { 1072 xfer->status = USBD_STALLED; 1073 } else { 1074 xfer->status = USBD_IOERROR; /* more info XXX */ 1075 } 1076 /* XXX need to reset TT on missed microframe */ 1077 if (status & EHCI_QTD_MISSEDMICRO) { 1078 printf("%s: missed microframe, TT reset not " 1079 "implemented, hub might be inoperational\n", 1080 device_xname(sc->sc_dev)); 1081 } 1082 } else { 1083 xfer->status = USBD_NORMAL_COMPLETION; 1084 } 1085 1086 end: 1087 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1088 * during this call, before methods->done is called: dma sync required 1089 * beforehand? */ 1090 usb_transfer_complete(xfer); 1091 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex)); 1092 } 1093 1094 /* 1095 * Wait here until controller claims to have an interrupt. 1096 * Then call ehci_intr and return. Use timeout to avoid waiting 1097 * too long. 1098 */ 1099 Static void 1100 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1101 { 1102 int timo; 1103 u_int32_t intrs; 1104 1105 xfer->status = USBD_IN_PROGRESS; 1106 for (timo = xfer->timeout; timo >= 0; timo--) { 1107 usb_delay_ms(&sc->sc_bus, 1); 1108 if (sc->sc_dying) 1109 break; 1110 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1111 sc->sc_eintrs; 1112 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs)); 1113 #ifdef EHCI_DEBUG 1114 if (ehcidebug > 15) 1115 ehci_dump_regs(sc); 1116 #endif 1117 if (intrs) { 1118 mutex_spin_enter(&sc->sc_intr_lock); 1119 ehci_intr1(sc); 1120 mutex_spin_exit(&sc->sc_intr_lock); 1121 if (xfer->status != USBD_IN_PROGRESS) 1122 return; 1123 } 1124 } 1125 1126 /* Timeout */ 1127 DPRINTF(("ehci_waitintr: timeout\n")); 1128 xfer->status = USBD_TIMEOUT; 1129 mutex_enter(&sc->sc_lock); 1130 usb_transfer_complete(xfer); 1131 mutex_exit(&sc->sc_lock); 1132 /* XXX should free TD */ 1133 } 1134 1135 Static void 1136 ehci_poll(struct usbd_bus *bus) 1137 { 1138 ehci_softc_t *sc = bus->hci_private; 1139 #ifdef EHCI_DEBUG 1140 static int last; 1141 int new; 1142 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1143 if (new != last) { 1144 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new)); 1145 last = new; 1146 } 1147 #endif 1148 1149 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1150 mutex_spin_enter(&sc->sc_intr_lock); 1151 ehci_intr1(sc); 1152 mutex_spin_exit(&sc->sc_intr_lock); 1153 } 1154 } 1155 1156 void 1157 ehci_childdet(device_t self, device_t child) 1158 { 1159 struct ehci_softc *sc = device_private(self); 1160 1161 KASSERT(sc->sc_child == child); 1162 sc->sc_child = NULL; 1163 } 1164 1165 int 1166 ehci_detach(struct ehci_softc *sc, int flags) 1167 { 1168 int rv = 0; 1169 1170 if (sc->sc_child != NULL) 1171 rv = config_detach(sc->sc_child, flags); 1172 1173 if (rv != 0) 1174 return (rv); 1175 1176 callout_halt(&sc->sc_tmo_intrlist, NULL); 1177 callout_destroy(&sc->sc_tmo_intrlist); 1178 1179 /* XXX free other data structures XXX */ 1180 if (sc->sc_softitds) 1181 kmem_free(sc->sc_softitds, 1182 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1183 cv_destroy(&sc->sc_doorbell); 1184 cv_destroy(&sc->sc_softwake_cv); 1185 1186 #if 0 1187 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1188 1189 softint_disestablish(sc->sc_doorbell_si); 1190 softint_disestablish(sc->sc_pcd_si); 1191 1192 mutex_destroy(&sc->sc_lock); 1193 mutex_destroy(&sc->sc_intr_lock); 1194 #endif 1195 1196 pool_cache_destroy(sc->sc_xferpool); 1197 1198 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1199 1200 return (rv); 1201 } 1202 1203 1204 int 1205 ehci_activate(device_t self, enum devact act) 1206 { 1207 struct ehci_softc *sc = device_private(self); 1208 1209 switch (act) { 1210 case DVACT_DEACTIVATE: 1211 sc->sc_dying = 1; 1212 return 0; 1213 default: 1214 return EOPNOTSUPP; 1215 } 1216 } 1217 1218 /* 1219 * Handle suspend/resume. 1220 * 1221 * We need to switch to polling mode here, because this routine is 1222 * called from an interrupt context. This is all right since we 1223 * are almost suspended anyway. 1224 * 1225 * Note that this power handler isn't to be registered directly; the 1226 * bus glue needs to call out to it. 1227 */ 1228 bool 1229 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1230 { 1231 ehci_softc_t *sc = device_private(dv); 1232 int i; 1233 uint32_t cmd, hcr; 1234 1235 mutex_spin_enter(&sc->sc_intr_lock); 1236 sc->sc_bus.use_polling++; 1237 mutex_spin_exit(&sc->sc_intr_lock); 1238 1239 for (i = 1; i <= sc->sc_noport; i++) { 1240 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1241 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1242 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1243 } 1244 1245 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1246 1247 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1248 EOWRITE4(sc, EHCI_USBCMD, cmd); 1249 1250 for (i = 0; i < 100; i++) { 1251 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1252 if (hcr == 0) 1253 break; 1254 1255 usb_delay_ms(&sc->sc_bus, 1); 1256 } 1257 if (hcr != 0) 1258 printf("%s: reset timeout\n", device_xname(dv)); 1259 1260 cmd &= ~EHCI_CMD_RS; 1261 EOWRITE4(sc, EHCI_USBCMD, cmd); 1262 1263 for (i = 0; i < 100; i++) { 1264 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1265 if (hcr == EHCI_STS_HCH) 1266 break; 1267 1268 usb_delay_ms(&sc->sc_bus, 1); 1269 } 1270 if (hcr != EHCI_STS_HCH) 1271 printf("%s: config timeout\n", device_xname(dv)); 1272 1273 mutex_spin_enter(&sc->sc_intr_lock); 1274 sc->sc_bus.use_polling--; 1275 mutex_spin_exit(&sc->sc_intr_lock); 1276 1277 return true; 1278 } 1279 1280 bool 1281 ehci_resume(device_t dv, const pmf_qual_t *qual) 1282 { 1283 ehci_softc_t *sc = device_private(dv); 1284 int i; 1285 uint32_t cmd, hcr; 1286 1287 /* restore things in case the bios sucks */ 1288 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1289 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1290 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1291 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1292 1293 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1294 1295 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1296 1297 hcr = 0; 1298 for (i = 1; i <= sc->sc_noport; i++) { 1299 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1300 if ((cmd & EHCI_PS_PO) == 0 && 1301 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1302 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1303 hcr = 1; 1304 } 1305 } 1306 1307 if (hcr) { 1308 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1309 1310 for (i = 1; i <= sc->sc_noport; i++) { 1311 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1312 if ((cmd & EHCI_PS_PO) == 0 && 1313 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1314 EOWRITE4(sc, EHCI_PORTSC(i), 1315 cmd & ~EHCI_PS_FPR); 1316 } 1317 } 1318 1319 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1320 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1321 1322 for (i = 0; i < 100; i++) { 1323 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1324 if (hcr != EHCI_STS_HCH) 1325 break; 1326 1327 usb_delay_ms(&sc->sc_bus, 1); 1328 } 1329 if (hcr == EHCI_STS_HCH) 1330 printf("%s: config timeout\n", device_xname(dv)); 1331 1332 return true; 1333 } 1334 1335 /* 1336 * Shut down the controller when the system is going down. 1337 */ 1338 bool 1339 ehci_shutdown(device_t self, int flags) 1340 { 1341 ehci_softc_t *sc = device_private(self); 1342 1343 DPRINTF(("ehci_shutdown: stopping the HC\n")); 1344 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1345 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1346 return true; 1347 } 1348 1349 Static usbd_status 1350 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1351 { 1352 struct ehci_softc *sc = bus->hci_private; 1353 usbd_status err; 1354 1355 err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, USBMALLOC_MULTISEG); 1356 #ifdef EHCI_DEBUG 1357 if (err) 1358 printf("ehci_allocm: usb_allocmem_flags()= %s (%d)\n", 1359 usbd_errstr(err), err); 1360 #endif 1361 if (err == USBD_NOMEM) 1362 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1363 #ifdef EHCI_DEBUG 1364 if (err) 1365 printf("ehci_allocm: usb_reserve_allocm()= %s (%d)\n", 1366 usbd_errstr(err), err); 1367 #endif 1368 return (err); 1369 } 1370 1371 Static void 1372 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1373 { 1374 struct ehci_softc *sc = bus->hci_private; 1375 1376 if (dma->block->flags & USB_DMA_RESERVE) { 1377 usb_reserve_freem(&sc->sc_dma_reserve, 1378 dma); 1379 return; 1380 } 1381 usb_freemem(&sc->sc_bus, dma); 1382 } 1383 1384 Static usbd_xfer_handle 1385 ehci_allocx(struct usbd_bus *bus) 1386 { 1387 struct ehci_softc *sc = bus->hci_private; 1388 usbd_xfer_handle xfer; 1389 1390 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1391 if (xfer != NULL) { 1392 memset(xfer, 0, sizeof(struct ehci_xfer)); 1393 #ifdef DIAGNOSTIC 1394 EXFER(xfer)->isdone = 1; 1395 xfer->busy_free = XFER_BUSY; 1396 #endif 1397 } 1398 return (xfer); 1399 } 1400 1401 Static void 1402 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1403 { 1404 struct ehci_softc *sc = bus->hci_private; 1405 1406 #ifdef DIAGNOSTIC 1407 if (xfer->busy_free != XFER_BUSY) { 1408 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1409 xfer->busy_free); 1410 } 1411 xfer->busy_free = XFER_FREE; 1412 if (!EXFER(xfer)->isdone) { 1413 printf("ehci_freex: !isdone\n"); 1414 } 1415 #endif 1416 pool_cache_put(sc->sc_xferpool, xfer); 1417 } 1418 1419 Static void 1420 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1421 { 1422 struct ehci_softc *sc = bus->hci_private; 1423 1424 *lock = &sc->sc_lock; 1425 } 1426 1427 Static void 1428 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1429 { 1430 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1431 1432 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n", 1433 epipe, epipe->sqh->qh.qh_qtd.qtd_status)); 1434 #ifdef EHCI_DEBUG 1435 if (ehcidebug) 1436 usbd_dump_pipe(pipe); 1437 #endif 1438 epipe->nexttoggle = 0; 1439 } 1440 1441 Static void 1442 ehci_noop(usbd_pipe_handle pipe) 1443 { 1444 } 1445 1446 #ifdef EHCI_DEBUG 1447 Static void 1448 ehci_dump_regs(ehci_softc_t *sc) 1449 { 1450 int i; 1451 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1452 EOREAD4(sc, EHCI_USBCMD), 1453 EOREAD4(sc, EHCI_USBSTS), 1454 EOREAD4(sc, EHCI_USBINTR)); 1455 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1456 EOREAD4(sc, EHCI_FRINDEX), 1457 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1458 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1459 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1460 for (i = 1; i <= sc->sc_noport; i++) 1461 printf("port %d status=0x%08x\n", i, 1462 EOREAD4(sc, EHCI_PORTSC(i))); 1463 } 1464 1465 /* 1466 * Unused function - this is meant to be called from a kernel 1467 * debugger. 1468 */ 1469 void 1470 ehci_dump(void) 1471 { 1472 ehci_dump_regs(theehci); 1473 } 1474 1475 Static void 1476 ehci_dump_link(ehci_link_t link, int type) 1477 { 1478 link = le32toh(link); 1479 printf("0x%08x", link); 1480 if (link & EHCI_LINK_TERMINATE) 1481 printf("<T>"); 1482 else { 1483 printf("<"); 1484 if (type) { 1485 switch (EHCI_LINK_TYPE(link)) { 1486 case EHCI_LINK_ITD: printf("ITD"); break; 1487 case EHCI_LINK_QH: printf("QH"); break; 1488 case EHCI_LINK_SITD: printf("SITD"); break; 1489 case EHCI_LINK_FSTN: printf("FSTN"); break; 1490 } 1491 } 1492 printf(">"); 1493 } 1494 } 1495 1496 Static void 1497 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1498 { 1499 int i; 1500 u_int32_t stop; 1501 1502 stop = 0; 1503 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1504 ehci_dump_sqtd(sqtd); 1505 usb_syncmem(&sqtd->dma, 1506 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1507 sizeof(sqtd->qtd), 1508 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1509 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1510 usb_syncmem(&sqtd->dma, 1511 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1512 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1513 } 1514 if (sqtd) 1515 printf("dump aborted, too many TDs\n"); 1516 } 1517 1518 Static void 1519 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1520 { 1521 usb_syncmem(&sqtd->dma, sqtd->offs, 1522 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1523 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr); 1524 ehci_dump_qtd(&sqtd->qtd); 1525 usb_syncmem(&sqtd->dma, sqtd->offs, 1526 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1527 } 1528 1529 Static void 1530 ehci_dump_qtd(ehci_qtd_t *qtd) 1531 { 1532 u_int32_t s; 1533 char sbuf[128]; 1534 1535 printf(" next="); ehci_dump_link(qtd->qtd_next, 0); 1536 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0); 1537 printf("\n"); 1538 s = le32toh(qtd->qtd_status); 1539 snprintb(sbuf, sizeof(sbuf), 1540 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR" 1541 "\3MISSED\2SPLIT\1PING", EHCI_QTD_GET_STATUS(s)); 1542 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n", 1543 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s), 1544 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s)); 1545 printf(" cerr=%d pid=%d stat=%s\n", EHCI_QTD_GET_CERR(s), 1546 EHCI_QTD_GET_PID(s), sbuf); 1547 for (s = 0; s < 5; s++) 1548 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s])); 1549 } 1550 1551 Static void 1552 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1553 { 1554 ehci_qh_t *qh = &sqh->qh; 1555 u_int32_t endp, endphub; 1556 1557 usb_syncmem(&sqh->dma, sqh->offs, 1558 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1559 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr); 1560 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n"); 1561 endp = le32toh(qh->qh_endp); 1562 printf(" endp=0x%08x\n", endp); 1563 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n", 1564 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1565 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp), 1566 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp)); 1567 printf(" mpl=0x%x ctl=%d nrl=%d\n", 1568 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp), 1569 EHCI_QH_GET_NRL(endp)); 1570 endphub = le32toh(qh->qh_endphub); 1571 printf(" endphub=0x%08x\n", endphub); 1572 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n", 1573 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1574 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1575 EHCI_QH_GET_MULT(endphub)); 1576 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n"); 1577 printf("Overlay qTD:\n"); 1578 ehci_dump_qtd(&qh->qh_qtd); 1579 usb_syncmem(&sqh->dma, sqh->offs, 1580 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1581 } 1582 1583 #if notyet 1584 Static void 1585 ehci_dump_itd(struct ehci_soft_itd *itd) 1586 { 1587 ehci_isoc_trans_t t; 1588 ehci_isoc_bufr_ptr_t b, b2, b3; 1589 int i; 1590 1591 printf("ITD: next phys=%X\n", itd->itd.itd_next); 1592 1593 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1594 t = le32toh(itd->itd.itd_ctl[i]); 1595 printf("ITDctl %d: stat=%X len=%X ioc=%X pg=%X offs=%X\n", i, 1596 EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 1597 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1598 EHCI_ITD_GET_OFFS(t)); 1599 } 1600 printf("ITDbufr: "); 1601 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1602 printf("%X,", EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i]))); 1603 1604 b = le32toh(itd->itd.itd_bufr[0]); 1605 b2 = le32toh(itd->itd.itd_bufr[1]); 1606 b3 = le32toh(itd->itd.itd_bufr[2]); 1607 printf("\nep=%X daddr=%X dir=%d maxpkt=%X multi=%X\n", 1608 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 1609 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3)); 1610 } 1611 1612 Static void 1613 ehci_dump_sitd(struct ehci_soft_itd *itd) 1614 { 1615 printf("SITD %p next=%p prev=%p xfernext=%p physaddr=%X slot=%d\n", 1616 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 1617 itd->xfer_next, itd->physaddr, itd->slot); 1618 } 1619 #endif 1620 1621 #ifdef DIAGNOSTIC 1622 Static void 1623 ehci_dump_exfer(struct ehci_xfer *ex) 1624 { 1625 printf("ehci_dump_exfer: ex=%p sqtdstart=%p end=%p itdstart=%p end=%p isdone=%d\n", ex, ex->sqtdstart, ex->sqtdend, ex->itdstart, ex->itdend, ex->isdone); 1626 } 1627 #endif 1628 #endif 1629 1630 Static usbd_status 1631 ehci_open(usbd_pipe_handle pipe) 1632 { 1633 usbd_device_handle dev = pipe->device; 1634 ehci_softc_t *sc = dev->bus->hci_private; 1635 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1636 u_int8_t addr = dev->address; 1637 u_int8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1638 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1639 ehci_soft_qh_t *sqh; 1640 usbd_status err; 1641 int ival, speed, naks; 1642 int hshubaddr, hshubport; 1643 1644 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n", 1645 pipe, addr, ed->bEndpointAddress, sc->sc_addr)); 1646 1647 if (dev->myhsport) { 1648 /* 1649 * When directly attached FS/LS device while doing embedded 1650 * transaction translations and we are the hub, set the hub 1651 * address to 0 (us). 1652 */ 1653 if (!(sc->sc_flags & EHCIF_ETTF) 1654 || (dev->myhsport->parent->address != sc->sc_addr)) { 1655 hshubaddr = dev->myhsport->parent->address; 1656 } else { 1657 hshubaddr = 0; 1658 } 1659 hshubport = dev->myhsport->portno; 1660 } else { 1661 hshubaddr = 0; 1662 hshubport = 0; 1663 } 1664 1665 if (sc->sc_dying) 1666 return (USBD_IOERROR); 1667 1668 /* toggle state needed for bulk endpoints */ 1669 epipe->nexttoggle = pipe->endpoint->datatoggle; 1670 1671 if (addr == sc->sc_addr) { 1672 switch (ed->bEndpointAddress) { 1673 case USB_CONTROL_ENDPOINT: 1674 pipe->methods = &ehci_root_ctrl_methods; 1675 break; 1676 case UE_DIR_IN | EHCI_INTR_ENDPT: 1677 pipe->methods = &ehci_root_intr_methods; 1678 break; 1679 default: 1680 DPRINTF(("ehci_open: bad bEndpointAddress 0x%02x\n", 1681 ed->bEndpointAddress)); 1682 return (USBD_INVAL); 1683 } 1684 return (USBD_NORMAL_COMPLETION); 1685 } 1686 1687 /* XXX All this stuff is only valid for async. */ 1688 switch (dev->speed) { 1689 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1690 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1691 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1692 default: panic("ehci_open: bad device speed %d", dev->speed); 1693 } 1694 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1695 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1696 "isoc endpoint.\n"); 1697 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1698 "attached to a USB2 hub, and transaction translations are " 1699 "not yet supported.\n"); 1700 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1701 "root hub instead.\n"); 1702 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n", 1703 hshubaddr, hshubport)); 1704 return USBD_INVAL; 1705 } 1706 1707 /* 1708 * For interrupt transfer, nak throttling must be disabled, but for 1709 * the other transfer type, nak throttling should be enabled from the 1710 * viewpoint that avoids the memory thrashing. 1711 */ 1712 naks = (xfertype == UE_INTERRUPT) ? 0 1713 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1714 1715 /* Allocate sqh for everything, save isoc xfers */ 1716 if (xfertype != UE_ISOCHRONOUS) { 1717 sqh = ehci_alloc_sqh(sc); 1718 if (sqh == NULL) 1719 return (USBD_NOMEM); 1720 /* qh_link filled when the QH is added */ 1721 sqh->qh.qh_endp = htole32( 1722 EHCI_QH_SET_ADDR(addr) | 1723 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1724 EHCI_QH_SET_EPS(speed) | 1725 EHCI_QH_DTC | 1726 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1727 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1728 EHCI_QH_CTL : 0) | 1729 EHCI_QH_SET_NRL(naks) 1730 ); 1731 sqh->qh.qh_endphub = htole32( 1732 EHCI_QH_SET_MULT(1) | 1733 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1734 ); 1735 if (speed != EHCI_QH_SPEED_HIGH) 1736 sqh->qh.qh_endphub |= htole32( 1737 EHCI_QH_SET_PORT(hshubport) | 1738 EHCI_QH_SET_HUBA(hshubaddr) | 1739 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1740 ); 1741 sqh->qh.qh_curqtd = EHCI_NULL; 1742 /* Fill the overlay qTD */ 1743 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1744 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1745 sqh->qh.qh_qtd.qtd_status = htole32(0); 1746 1747 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1748 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1749 epipe->sqh = sqh; 1750 } else { 1751 sqh = NULL; 1752 } /*xfertype == UE_ISOC*/ 1753 1754 switch (xfertype) { 1755 case UE_CONTROL: 1756 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1757 0, &epipe->u.ctl.reqdma); 1758 #ifdef EHCI_DEBUG 1759 if (err) 1760 printf("ehci_open: usb_allocmem()=%d\n", err); 1761 #endif 1762 if (err) 1763 goto bad; 1764 pipe->methods = &ehci_device_ctrl_methods; 1765 mutex_enter(&sc->sc_lock); 1766 ehci_add_qh(sc, sqh, sc->sc_async_head); 1767 mutex_exit(&sc->sc_lock); 1768 break; 1769 case UE_BULK: 1770 pipe->methods = &ehci_device_bulk_methods; 1771 mutex_enter(&sc->sc_lock); 1772 ehci_add_qh(sc, sqh, sc->sc_async_head); 1773 mutex_exit(&sc->sc_lock); 1774 break; 1775 case UE_INTERRUPT: 1776 pipe->methods = &ehci_device_intr_methods; 1777 ival = pipe->interval; 1778 if (ival == USBD_DEFAULT_INTERVAL) { 1779 if (speed == EHCI_QH_SPEED_HIGH) { 1780 if (ed->bInterval > 16) { 1781 /* 1782 * illegal with high-speed, but there 1783 * were documentation bugs in the spec, 1784 * so be generous 1785 */ 1786 ival = 256; 1787 } else 1788 ival = (1 << (ed->bInterval - 1)) / 8; 1789 } else 1790 ival = ed->bInterval; 1791 } 1792 err = ehci_device_setintr(sc, sqh, ival); 1793 if (err) 1794 goto bad; 1795 break; 1796 case UE_ISOCHRONOUS: 1797 pipe->methods = &ehci_device_isoc_methods; 1798 if (ed->bInterval == 0 || ed->bInterval > 16) { 1799 printf("ehci: opening pipe with invalid bInterval\n"); 1800 err = USBD_INVAL; 1801 goto bad; 1802 } 1803 if (UGETW(ed->wMaxPacketSize) == 0) { 1804 printf("ehci: zero length endpoint open request\n"); 1805 err = USBD_INVAL; 1806 goto bad; 1807 } 1808 epipe->u.isoc.next_frame = 0; 1809 epipe->u.isoc.cur_xfers = 0; 1810 break; 1811 default: 1812 DPRINTF(("ehci: bad xfer type %d\n", xfertype)); 1813 err = USBD_INVAL; 1814 goto bad; 1815 } 1816 return (USBD_NORMAL_COMPLETION); 1817 1818 bad: 1819 if (sqh != NULL) 1820 ehci_free_sqh(sc, sqh); 1821 return (err); 1822 } 1823 1824 /* 1825 * Add an ED to the schedule. Called with USB lock held. 1826 */ 1827 Static void 1828 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1829 { 1830 1831 KASSERT(mutex_owned(&sc->sc_lock)); 1832 1833 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1834 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1835 sqh->next = head->next; 1836 sqh->qh.qh_link = head->qh.qh_link; 1837 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1838 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1839 head->next = sqh; 1840 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1841 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1842 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1843 1844 #ifdef EHCI_DEBUG 1845 if (ehcidebug > 5) { 1846 printf("ehci_add_qh:\n"); 1847 ehci_dump_sqh(sqh); 1848 } 1849 #endif 1850 } 1851 1852 /* 1853 * Remove an ED from the schedule. Called with USB lock held. 1854 */ 1855 Static void 1856 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1857 { 1858 ehci_soft_qh_t *p; 1859 1860 KASSERT(mutex_owned(&sc->sc_lock)); 1861 1862 /* XXX */ 1863 for (p = head; p != NULL && p->next != sqh; p = p->next) 1864 ; 1865 if (p == NULL) 1866 panic("ehci_rem_qh: ED not found"); 1867 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1868 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1869 p->next = sqh->next; 1870 p->qh.qh_link = sqh->qh.qh_link; 1871 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 1872 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 1873 1874 ehci_sync_hc(sc); 1875 } 1876 1877 Static void 1878 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 1879 { 1880 int i; 1881 u_int32_t status; 1882 1883 /* Save toggle bit and ping status. */ 1884 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1885 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1886 status = sqh->qh.qh_qtd.qtd_status & 1887 htole32(EHCI_QTD_TOGGLE_MASK | 1888 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 1889 /* Set HALTED to make hw leave it alone. */ 1890 sqh->qh.qh_qtd.qtd_status = 1891 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 1892 usb_syncmem(&sqh->dma, 1893 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1894 sizeof(sqh->qh.qh_qtd.qtd_status), 1895 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1896 sqh->qh.qh_curqtd = 0; 1897 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 1898 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1899 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 1900 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 1901 sqh->sqtd = sqtd; 1902 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1903 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1904 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 1905 sqh->qh.qh_qtd.qtd_status = status; 1906 usb_syncmem(&sqh->dma, 1907 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 1908 sizeof(sqh->qh.qh_qtd.qtd_status), 1909 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1910 } 1911 1912 /* 1913 * Ensure that the HC has released all references to the QH. We do this 1914 * by asking for a Async Advance Doorbell interrupt and then we wait for 1915 * the interrupt. 1916 * To make this easier we first obtain exclusive use of the doorbell. 1917 */ 1918 Static void 1919 ehci_sync_hc(ehci_softc_t *sc) 1920 { 1921 int error __diagused; 1922 1923 KASSERT(mutex_owned(&sc->sc_lock)); 1924 1925 if (sc->sc_dying) { 1926 DPRINTFN(2,("ehci_sync_hc: dying\n")); 1927 return; 1928 } 1929 DPRINTFN(2,("ehci_sync_hc: enter\n")); 1930 /* ask for doorbell */ 1931 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 1932 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1933 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1934 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 1935 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n", 1936 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS))); 1937 #ifdef DIAGNOSTIC 1938 if (error) 1939 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 1940 #endif 1941 DPRINTFN(2,("ehci_sync_hc: exit\n")); 1942 } 1943 1944 Static void 1945 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 1946 { 1947 struct ehci_soft_itd *itd, *prev; 1948 1949 prev = NULL; 1950 1951 if (exfer->itdstart == NULL || exfer->itdend == NULL) 1952 panic("ehci isoc xfer being freed, but with no itd chain\n"); 1953 1954 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1955 prev = itd->u.frame_list.prev; 1956 /* Unlink itd from hardware chain, or frame array */ 1957 if (prev == NULL) { /* We're at the table head */ 1958 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 1959 sc->sc_flist[itd->slot] = itd->itd.itd_next; 1960 usb_syncmem(&sc->sc_fldma, 1961 sizeof(ehci_link_t) * itd->slot, 1962 sizeof(ehci_link_t), 1963 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1964 1965 if (itd->u.frame_list.next != NULL) 1966 itd->u.frame_list.next->u.frame_list.prev = NULL; 1967 } else { 1968 /* XXX this part is untested... */ 1969 prev->itd.itd_next = itd->itd.itd_next; 1970 usb_syncmem(&itd->dma, 1971 itd->offs + offsetof(ehci_itd_t, itd_next), 1972 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 1973 1974 prev->u.frame_list.next = itd->u.frame_list.next; 1975 if (itd->u.frame_list.next != NULL) 1976 itd->u.frame_list.next->u.frame_list.prev = prev; 1977 } 1978 } 1979 1980 prev = NULL; 1981 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 1982 if (prev != NULL) 1983 ehci_free_itd(sc, prev); 1984 prev = itd; 1985 } 1986 if (prev) 1987 ehci_free_itd(sc, prev); 1988 exfer->itdstart = NULL; 1989 exfer->itdend = NULL; 1990 } 1991 1992 /***********/ 1993 1994 /* 1995 * Data structures and routines to emulate the root hub. 1996 */ 1997 Static usb_device_descriptor_t ehci_devd = { 1998 USB_DEVICE_DESCRIPTOR_SIZE, 1999 UDESC_DEVICE, /* type */ 2000 {0x00, 0x02}, /* USB version */ 2001 UDCLASS_HUB, /* class */ 2002 UDSUBCLASS_HUB, /* subclass */ 2003 UDPROTO_HSHUBSTT, /* protocol */ 2004 64, /* max packet */ 2005 {0},{0},{0x00,0x01}, /* device id */ 2006 1,2,0, /* string indicies */ 2007 1 /* # of configurations */ 2008 }; 2009 2010 Static const usb_device_qualifier_t ehci_odevd = { 2011 USB_DEVICE_DESCRIPTOR_SIZE, 2012 UDESC_DEVICE_QUALIFIER, /* type */ 2013 {0x00, 0x02}, /* USB version */ 2014 UDCLASS_HUB, /* class */ 2015 UDSUBCLASS_HUB, /* subclass */ 2016 UDPROTO_FSHUB, /* protocol */ 2017 64, /* max packet */ 2018 1, /* # of configurations */ 2019 0 2020 }; 2021 2022 Static const usb_config_descriptor_t ehci_confd = { 2023 USB_CONFIG_DESCRIPTOR_SIZE, 2024 UDESC_CONFIG, 2025 {USB_CONFIG_DESCRIPTOR_SIZE + 2026 USB_INTERFACE_DESCRIPTOR_SIZE + 2027 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2028 1, 2029 1, 2030 0, 2031 UC_ATTR_MBO | UC_SELF_POWERED, 2032 0 /* max power */ 2033 }; 2034 2035 Static const usb_interface_descriptor_t ehci_ifcd = { 2036 USB_INTERFACE_DESCRIPTOR_SIZE, 2037 UDESC_INTERFACE, 2038 0, 2039 0, 2040 1, 2041 UICLASS_HUB, 2042 UISUBCLASS_HUB, 2043 UIPROTO_HSHUBSTT, 2044 0 2045 }; 2046 2047 Static const usb_endpoint_descriptor_t ehci_endpd = { 2048 USB_ENDPOINT_DESCRIPTOR_SIZE, 2049 UDESC_ENDPOINT, 2050 UE_DIR_IN | EHCI_INTR_ENDPT, 2051 UE_INTERRUPT, 2052 {8, 0}, /* max packet */ 2053 12 2054 }; 2055 2056 Static const usb_hub_descriptor_t ehci_hubd = { 2057 USB_HUB_DESCRIPTOR_SIZE, 2058 UDESC_HUB, 2059 0, 2060 {0,0}, 2061 0, 2062 0, 2063 {""}, 2064 {""}, 2065 }; 2066 2067 /* 2068 * Simulate a hardware hub by handling all the necessary requests. 2069 */ 2070 Static usbd_status 2071 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2072 { 2073 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2074 usbd_status err; 2075 2076 /* Insert last in queue. */ 2077 mutex_enter(&sc->sc_lock); 2078 err = usb_insert_transfer(xfer); 2079 mutex_exit(&sc->sc_lock); 2080 if (err) 2081 return (err); 2082 2083 /* Pipe isn't running, start first */ 2084 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2085 } 2086 2087 Static usbd_status 2088 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2089 { 2090 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2091 usb_device_request_t *req; 2092 void *buf = NULL; 2093 int port, i; 2094 int len, value, index, l, totlen = 0; 2095 usb_port_status_t ps; 2096 usb_hub_descriptor_t hubd; 2097 usbd_status err; 2098 u_int32_t v; 2099 2100 if (sc->sc_dying) 2101 return (USBD_IOERROR); 2102 2103 #ifdef DIAGNOSTIC 2104 if (!(xfer->rqflags & URQ_REQUEST)) 2105 /* XXX panic */ 2106 return (USBD_INVAL); 2107 #endif 2108 req = &xfer->request; 2109 2110 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n", 2111 req->bmRequestType, req->bRequest)); 2112 2113 len = UGETW(req->wLength); 2114 value = UGETW(req->wValue); 2115 index = UGETW(req->wIndex); 2116 2117 if (len != 0) 2118 buf = KERNADDR(&xfer->dmabuf, 0); 2119 2120 #define C(x,y) ((x) | ((y) << 8)) 2121 switch(C(req->bRequest, req->bmRequestType)) { 2122 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2123 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2124 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2125 /* 2126 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2127 * for the integrated root hub. 2128 */ 2129 break; 2130 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2131 if (len > 0) { 2132 *(u_int8_t *)buf = sc->sc_conf; 2133 totlen = 1; 2134 } 2135 break; 2136 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2137 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value)); 2138 if (len == 0) 2139 break; 2140 switch(value >> 8) { 2141 case UDESC_DEVICE: 2142 if ((value & 0xff) != 0) { 2143 err = USBD_IOERROR; 2144 goto ret; 2145 } 2146 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2147 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2148 memcpy(buf, &ehci_devd, l); 2149 break; 2150 /* 2151 * We can't really operate at another speed, but the spec says 2152 * we need this descriptor. 2153 */ 2154 case UDESC_DEVICE_QUALIFIER: 2155 if ((value & 0xff) != 0) { 2156 err = USBD_IOERROR; 2157 goto ret; 2158 } 2159 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2160 memcpy(buf, &ehci_odevd, l); 2161 break; 2162 /* 2163 * We can't really operate at another speed, but the spec says 2164 * we need this descriptor. 2165 */ 2166 case UDESC_OTHER_SPEED_CONFIGURATION: 2167 case UDESC_CONFIG: 2168 if ((value & 0xff) != 0) { 2169 err = USBD_IOERROR; 2170 goto ret; 2171 } 2172 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2173 memcpy(buf, &ehci_confd, l); 2174 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2175 value >> 8; 2176 buf = (char *)buf + l; 2177 len -= l; 2178 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2179 totlen += l; 2180 memcpy(buf, &ehci_ifcd, l); 2181 buf = (char *)buf + l; 2182 len -= l; 2183 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2184 totlen += l; 2185 memcpy(buf, &ehci_endpd, l); 2186 break; 2187 case UDESC_STRING: 2188 #define sd ((usb_string_descriptor_t *)buf) 2189 switch (value & 0xff) { 2190 case 0: /* Language table */ 2191 totlen = usb_makelangtbl(sd, len); 2192 break; 2193 case 1: /* Vendor */ 2194 totlen = usb_makestrdesc(sd, len, 2195 sc->sc_vendor); 2196 break; 2197 case 2: /* Product */ 2198 totlen = usb_makestrdesc(sd, len, 2199 "EHCI root hub"); 2200 break; 2201 } 2202 #undef sd 2203 break; 2204 default: 2205 err = USBD_IOERROR; 2206 goto ret; 2207 } 2208 break; 2209 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2210 if (len > 0) { 2211 *(u_int8_t *)buf = 0; 2212 totlen = 1; 2213 } 2214 break; 2215 case C(UR_GET_STATUS, UT_READ_DEVICE): 2216 if (len > 1) { 2217 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2218 totlen = 2; 2219 } 2220 break; 2221 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2222 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2223 if (len > 1) { 2224 USETW(((usb_status_t *)buf)->wStatus, 0); 2225 totlen = 2; 2226 } 2227 break; 2228 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2229 if (value >= USB_MAX_DEVICES) { 2230 err = USBD_IOERROR; 2231 goto ret; 2232 } 2233 sc->sc_addr = value; 2234 break; 2235 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2236 if (value != 0 && value != 1) { 2237 err = USBD_IOERROR; 2238 goto ret; 2239 } 2240 sc->sc_conf = value; 2241 break; 2242 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2243 break; 2244 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2245 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2246 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2247 err = USBD_IOERROR; 2248 goto ret; 2249 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2250 break; 2251 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2252 break; 2253 /* Hub requests */ 2254 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2255 break; 2256 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2257 DPRINTFN(4, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE " 2258 "port=%d feature=%d\n", 2259 index, value)); 2260 if (index < 1 || index > sc->sc_noport) { 2261 err = USBD_IOERROR; 2262 goto ret; 2263 } 2264 port = EHCI_PORTSC(index); 2265 v = EOREAD4(sc, port); 2266 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2267 v &= ~EHCI_PS_CLEAR; 2268 switch(value) { 2269 case UHF_PORT_ENABLE: 2270 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2271 break; 2272 case UHF_PORT_SUSPEND: 2273 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2274 break; 2275 v &= ~EHCI_PS_SUSP; 2276 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2277 /* see USB2 spec ch. 7.1.7.7 */ 2278 usb_delay_ms(&sc->sc_bus, 20); 2279 EOWRITE4(sc, port, v); 2280 usb_delay_ms(&sc->sc_bus, 2); 2281 #ifdef DEBUG 2282 v = EOREAD4(sc, port); 2283 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2284 printf("ehci: resume failed: %x\n", v); 2285 #endif 2286 break; 2287 case UHF_PORT_POWER: 2288 if (sc->sc_hasppc) 2289 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2290 break; 2291 case UHF_PORT_TEST: 2292 DPRINTFN(2,("ehci_root_ctrl_start: clear port test " 2293 "%d\n", index)); 2294 break; 2295 case UHF_PORT_INDICATOR: 2296 DPRINTFN(2,("ehci_root_ctrl_start: clear port ind " 2297 "%d\n", index)); 2298 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2299 break; 2300 case UHF_C_PORT_CONNECTION: 2301 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2302 break; 2303 case UHF_C_PORT_ENABLE: 2304 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2305 break; 2306 case UHF_C_PORT_SUSPEND: 2307 /* how? */ 2308 break; 2309 case UHF_C_PORT_OVER_CURRENT: 2310 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2311 break; 2312 case UHF_C_PORT_RESET: 2313 sc->sc_isreset[index] = 0; 2314 break; 2315 default: 2316 err = USBD_IOERROR; 2317 goto ret; 2318 } 2319 #if 0 2320 switch(value) { 2321 case UHF_C_PORT_CONNECTION: 2322 case UHF_C_PORT_ENABLE: 2323 case UHF_C_PORT_SUSPEND: 2324 case UHF_C_PORT_OVER_CURRENT: 2325 case UHF_C_PORT_RESET: 2326 default: 2327 break; 2328 } 2329 #endif 2330 break; 2331 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2332 if (len == 0) 2333 break; 2334 if ((value & 0xff) != 0) { 2335 err = USBD_IOERROR; 2336 goto ret; 2337 } 2338 hubd = ehci_hubd; 2339 hubd.bNbrPorts = sc->sc_noport; 2340 v = EOREAD4(sc, EHCI_HCSPARAMS); 2341 USETW(hubd.wHubCharacteristics, 2342 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2343 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2344 ? UHD_PORT_IND : 0); 2345 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2346 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2347 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2348 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2349 l = min(len, hubd.bDescLength); 2350 totlen = l; 2351 memcpy(buf, &hubd, l); 2352 break; 2353 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2354 if (len != 4) { 2355 err = USBD_IOERROR; 2356 goto ret; 2357 } 2358 memset(buf, 0, len); /* ? XXX */ 2359 totlen = len; 2360 break; 2361 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2362 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n", 2363 index)); 2364 if (index < 1 || index > sc->sc_noport) { 2365 err = USBD_IOERROR; 2366 goto ret; 2367 } 2368 if (len != 4) { 2369 err = USBD_IOERROR; 2370 goto ret; 2371 } 2372 v = EOREAD4(sc, EHCI_PORTSC(index)); 2373 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v)); 2374 2375 i = UPS_HIGH_SPEED; 2376 if (sc->sc_flags & EHCIF_ETTF) { 2377 /* 2378 * If we are doing embedded transaction translation, 2379 * then directly attached LS/FS devices are reset by 2380 * the EHCI controller itself. PSPD is encoded 2381 * the same way as in USBSTATUS. 2382 */ 2383 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2384 } 2385 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2386 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2387 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2388 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2389 if (v & EHCI_PS_PR) i |= UPS_RESET; 2390 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2391 if (sc->sc_vendor_port_status) 2392 i = sc->sc_vendor_port_status(sc, v, i); 2393 USETW(ps.wPortStatus, i); 2394 i = 0; 2395 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2396 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2397 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2398 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2399 USETW(ps.wPortChange, i); 2400 l = min(len, sizeof ps); 2401 memcpy(buf, &ps, l); 2402 totlen = l; 2403 break; 2404 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2405 err = USBD_IOERROR; 2406 goto ret; 2407 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2408 break; 2409 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2410 if (index < 1 || index > sc->sc_noport) { 2411 err = USBD_IOERROR; 2412 goto ret; 2413 } 2414 port = EHCI_PORTSC(index); 2415 v = EOREAD4(sc, port); 2416 DPRINTFN(4, ("ehci_root_ctrl_start: portsc=0x%08x\n", v)); 2417 v &= ~EHCI_PS_CLEAR; 2418 switch(value) { 2419 case UHF_PORT_ENABLE: 2420 EOWRITE4(sc, port, v | EHCI_PS_PE); 2421 break; 2422 case UHF_PORT_SUSPEND: 2423 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2424 break; 2425 case UHF_PORT_RESET: 2426 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n", 2427 index)); 2428 if (EHCI_PS_IS_LOWSPEED(v) 2429 && sc->sc_ncomp > 0 2430 && !(sc->sc_flags & EHCIF_ETTF)) { 2431 /* 2432 * Low speed device on non-ETTF controller or 2433 * unaccompanied controller, give up ownership. 2434 */ 2435 ehci_disown(sc, index, 1); 2436 break; 2437 } 2438 /* Start reset sequence. */ 2439 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2440 EOWRITE4(sc, port, v | EHCI_PS_PR); 2441 /* Wait for reset to complete. */ 2442 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2443 if (sc->sc_dying) { 2444 err = USBD_IOERROR; 2445 goto ret; 2446 } 2447 /* 2448 * An embedded transaction translator will automatically 2449 * terminate the reset sequence so there's no need to 2450 * it. 2451 */ 2452 v = EOREAD4(sc, port); 2453 if (v & EHCI_PS_PR) { 2454 /* Terminate reset sequence. */ 2455 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2456 /* Wait for HC to complete reset. */ 2457 usb_delay_ms(&sc->sc_bus, 2458 EHCI_PORT_RESET_COMPLETE); 2459 if (sc->sc_dying) { 2460 err = USBD_IOERROR; 2461 goto ret; 2462 } 2463 } 2464 2465 v = EOREAD4(sc, port); 2466 DPRINTF(("ehci after reset, status=0x%08x\n", v)); 2467 if (v & EHCI_PS_PR) { 2468 printf("%s: port reset timeout\n", 2469 device_xname(sc->sc_dev)); 2470 return (USBD_TIMEOUT); 2471 } 2472 if (!(v & EHCI_PS_PE)) { 2473 /* Not a high speed device, give up ownership.*/ 2474 ehci_disown(sc, index, 0); 2475 break; 2476 } 2477 sc->sc_isreset[index] = 1; 2478 DPRINTF(("ehci port %d reset, status = 0x%08x\n", 2479 index, v)); 2480 break; 2481 case UHF_PORT_POWER: 2482 DPRINTFN(2,("ehci_root_ctrl_start: set port power " 2483 "%d (has PPC = %d)\n", index, 2484 sc->sc_hasppc)); 2485 if (sc->sc_hasppc) 2486 EOWRITE4(sc, port, v | EHCI_PS_PP); 2487 break; 2488 case UHF_PORT_TEST: 2489 DPRINTFN(2,("ehci_root_ctrl_start: set port test " 2490 "%d\n", index)); 2491 break; 2492 case UHF_PORT_INDICATOR: 2493 DPRINTFN(2,("ehci_root_ctrl_start: set port ind " 2494 "%d\n", index)); 2495 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2496 break; 2497 default: 2498 err = USBD_IOERROR; 2499 goto ret; 2500 } 2501 break; 2502 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2503 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2504 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2505 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2506 break; 2507 default: 2508 err = USBD_IOERROR; 2509 goto ret; 2510 } 2511 xfer->actlen = totlen; 2512 err = USBD_NORMAL_COMPLETION; 2513 ret: 2514 mutex_enter(&sc->sc_lock); 2515 xfer->status = err; 2516 usb_transfer_complete(xfer); 2517 mutex_exit(&sc->sc_lock); 2518 return (USBD_IN_PROGRESS); 2519 } 2520 2521 Static void 2522 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2523 { 2524 int port; 2525 u_int32_t v; 2526 2527 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed)); 2528 #ifdef DIAGNOSTIC 2529 if (sc->sc_npcomp != 0) { 2530 int i = (index-1) / sc->sc_npcomp; 2531 if (i >= sc->sc_ncomp) 2532 printf("%s: strange port\n", 2533 device_xname(sc->sc_dev)); 2534 else 2535 printf("%s: handing over %s speed device on " 2536 "port %d to %s\n", 2537 device_xname(sc->sc_dev), 2538 lowspeed ? "low" : "full", 2539 index, device_xname(sc->sc_comps[i])); 2540 } else { 2541 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2542 } 2543 #endif 2544 port = EHCI_PORTSC(index); 2545 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2546 EOWRITE4(sc, port, v | EHCI_PS_PO); 2547 } 2548 2549 /* Abort a root control request. */ 2550 Static void 2551 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2552 { 2553 /* Nothing to do, all transfers are synchronous. */ 2554 } 2555 2556 /* Close the root pipe. */ 2557 Static void 2558 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2559 { 2560 DPRINTF(("ehci_root_ctrl_close\n")); 2561 /* Nothing to do. */ 2562 } 2563 2564 Static void 2565 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2566 { 2567 xfer->hcpriv = NULL; 2568 } 2569 2570 Static usbd_status 2571 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2572 { 2573 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2574 usbd_status err; 2575 2576 /* Insert last in queue. */ 2577 mutex_enter(&sc->sc_lock); 2578 err = usb_insert_transfer(xfer); 2579 mutex_exit(&sc->sc_lock); 2580 if (err) 2581 return (err); 2582 2583 /* Pipe isn't running, start first */ 2584 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2585 } 2586 2587 Static usbd_status 2588 ehci_root_intr_start(usbd_xfer_handle xfer) 2589 { 2590 usbd_pipe_handle pipe = xfer->pipe; 2591 ehci_softc_t *sc = pipe->device->bus->hci_private; 2592 2593 if (sc->sc_dying) 2594 return (USBD_IOERROR); 2595 2596 mutex_enter(&sc->sc_lock); 2597 sc->sc_intrxfer = xfer; 2598 mutex_exit(&sc->sc_lock); 2599 2600 return (USBD_IN_PROGRESS); 2601 } 2602 2603 /* Abort a root interrupt request. */ 2604 Static void 2605 ehci_root_intr_abort(usbd_xfer_handle xfer) 2606 { 2607 #ifdef DIAGNOSTIC 2608 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2609 #endif 2610 2611 KASSERT(mutex_owned(&sc->sc_lock)); 2612 KASSERT(xfer->pipe->intrxfer == xfer); 2613 2614 sc->sc_intrxfer = NULL; 2615 2616 xfer->status = USBD_CANCELLED; 2617 usb_transfer_complete(xfer); 2618 } 2619 2620 /* Close the root pipe. */ 2621 Static void 2622 ehci_root_intr_close(usbd_pipe_handle pipe) 2623 { 2624 ehci_softc_t *sc = pipe->device->bus->hci_private; 2625 2626 KASSERT(mutex_owned(&sc->sc_lock)); 2627 2628 DPRINTF(("ehci_root_intr_close\n")); 2629 2630 sc->sc_intrxfer = NULL; 2631 } 2632 2633 Static void 2634 ehci_root_intr_done(usbd_xfer_handle xfer) 2635 { 2636 xfer->hcpriv = NULL; 2637 } 2638 2639 /************************/ 2640 2641 Static ehci_soft_qh_t * 2642 ehci_alloc_sqh(ehci_softc_t *sc) 2643 { 2644 ehci_soft_qh_t *sqh; 2645 usbd_status err; 2646 int i, offs; 2647 usb_dma_t dma; 2648 2649 if (sc->sc_freeqhs == NULL) { 2650 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n")); 2651 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2652 EHCI_PAGE_SIZE, &dma); 2653 #ifdef EHCI_DEBUG 2654 if (err) 2655 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2656 #endif 2657 if (err) 2658 return (NULL); 2659 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2660 offs = i * EHCI_SQH_SIZE; 2661 sqh = KERNADDR(&dma, offs); 2662 sqh->physaddr = DMAADDR(&dma, offs); 2663 sqh->dma = dma; 2664 sqh->offs = offs; 2665 sqh->next = sc->sc_freeqhs; 2666 sc->sc_freeqhs = sqh; 2667 } 2668 } 2669 sqh = sc->sc_freeqhs; 2670 sc->sc_freeqhs = sqh->next; 2671 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2672 sqh->next = NULL; 2673 return (sqh); 2674 } 2675 2676 Static void 2677 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2678 { 2679 sqh->next = sc->sc_freeqhs; 2680 sc->sc_freeqhs = sqh; 2681 } 2682 2683 Static ehci_soft_qtd_t * 2684 ehci_alloc_sqtd(ehci_softc_t *sc) 2685 { 2686 ehci_soft_qtd_t *sqtd = NULL; 2687 usbd_status err; 2688 int i, offs; 2689 usb_dma_t dma; 2690 2691 if (sc->sc_freeqtds == NULL) { 2692 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n")); 2693 2694 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2695 EHCI_PAGE_SIZE, &dma); 2696 #ifdef EHCI_DEBUG 2697 if (err) 2698 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2699 #endif 2700 if (err) 2701 goto done; 2702 2703 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2704 offs = i * EHCI_SQTD_SIZE; 2705 sqtd = KERNADDR(&dma, offs); 2706 sqtd->physaddr = DMAADDR(&dma, offs); 2707 sqtd->dma = dma; 2708 sqtd->offs = offs; 2709 2710 sqtd->nextqtd = sc->sc_freeqtds; 2711 sc->sc_freeqtds = sqtd; 2712 } 2713 } 2714 2715 sqtd = sc->sc_freeqtds; 2716 sc->sc_freeqtds = sqtd->nextqtd; 2717 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2718 sqtd->nextqtd = NULL; 2719 sqtd->xfer = NULL; 2720 2721 done: 2722 return (sqtd); 2723 } 2724 2725 Static void 2726 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2727 { 2728 2729 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 2730 2731 sqtd->nextqtd = sc->sc_freeqtds; 2732 sc->sc_freeqtds = sqtd; 2733 } 2734 2735 Static usbd_status 2736 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2737 int alen, int rd, usbd_xfer_handle xfer, 2738 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2739 { 2740 ehci_soft_qtd_t *next, *cur; 2741 ehci_physaddr_t nextphys; 2742 u_int32_t qtdstatus; 2743 int len, curlen, mps; 2744 int i, tog; 2745 int pages, pageoffs; 2746 bus_size_t curoffs; 2747 vaddr_t va, va_offs; 2748 usb_dma_t *dma = &xfer->dmabuf; 2749 u_int16_t flags = xfer->flags; 2750 paddr_t a; 2751 2752 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen)); 2753 2754 len = alen; 2755 qtdstatus = EHCI_QTD_ACTIVE | 2756 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2757 EHCI_QTD_SET_CERR(3) 2758 /* IOC set below */ 2759 /* BYTES set below */ 2760 ; 2761 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2762 tog = epipe->nexttoggle; 2763 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2764 2765 cur = ehci_alloc_sqtd(sc); 2766 *sp = cur; 2767 if (cur == NULL) 2768 goto nomem; 2769 2770 usb_syncmem(dma, 0, alen, 2771 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2772 curoffs = 0; 2773 for (;;) { 2774 /* The EHCI hardware can handle at most 5 pages. */ 2775 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2776 va_offs = EHCI_PAGE_OFFSET(va_offs); 2777 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 2778 /* we can handle it in this QTD */ 2779 curlen = len - curoffs; 2780 } else { 2781 /* must use multiple TDs, fill as much as possible. */ 2782 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 2783 2784 /* the length must be a multiple of the max size */ 2785 curlen -= curlen % mps; 2786 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, " 2787 "curlen=%d\n", curlen)); 2788 #ifdef DIAGNOSTIC 2789 if (curlen == 0) 2790 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2791 #endif 2792 } 2793 DPRINTFN(4,("ehci_alloc_sqtd_chain: len=%d curlen=%d " 2794 "curoffs=%zu\n", len, curlen, (size_t)curoffs)); 2795 2796 /* 2797 * Allocate another transfer if there's more data left, 2798 * or if force last short transfer flag is set and we're 2799 * allocating a multiple of the max packet size. 2800 */ 2801 2802 if (curoffs + curlen != len || 2803 ((curlen % mps) == 0 && !rd && curlen != 0 && 2804 (flags & USBD_FORCE_SHORT_XFER))) { 2805 next = ehci_alloc_sqtd(sc); 2806 if (next == NULL) 2807 goto nomem; 2808 nextphys = htole32(next->physaddr); 2809 } else { 2810 next = NULL; 2811 nextphys = EHCI_NULL; 2812 } 2813 2814 /* Find number of pages we'll be using, insert dma addresses */ 2815 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2816 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2817 pageoffs = EHCI_PAGE(curoffs); 2818 for (i = 0; i < pages; i++) { 2819 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2820 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2821 /* Cast up to avoid compiler warnings */ 2822 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2823 } 2824 2825 /* First buffer pointer requires a page offset to start at */ 2826 va = (vaddr_t)KERNADDR(dma, curoffs); 2827 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2828 2829 cur->nextqtd = next; 2830 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2831 cur->qtd.qtd_status = 2832 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2833 cur->xfer = xfer; 2834 cur->len = curlen; 2835 2836 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08zx end=0x%08zx\n", 2837 (size_t)curoffs, (size_t)(curoffs + curlen))); 2838 2839 /* adjust the toggle based on the number of packets in this 2840 qtd */ 2841 if (((curlen + mps - 1) / mps) & 1) { 2842 tog ^= 1; 2843 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2844 } 2845 if (next == NULL) 2846 break; 2847 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2848 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2849 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n")); 2850 if (len) 2851 curoffs += curlen; 2852 cur = next; 2853 } 2854 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2855 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2856 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2857 *ep = cur; 2858 epipe->nexttoggle = tog; 2859 2860 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n", 2861 *sp, *ep)); 2862 2863 return (USBD_NORMAL_COMPLETION); 2864 2865 nomem: 2866 /* XXX free chain */ 2867 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n")); 2868 return (USBD_NOMEM); 2869 } 2870 2871 Static void 2872 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2873 ehci_soft_qtd_t *sqtdend) 2874 { 2875 ehci_soft_qtd_t *p; 2876 int i; 2877 2878 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n", 2879 sqtd, sqtdend)); 2880 2881 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2882 p = sqtd->nextqtd; 2883 ehci_free_sqtd(sc, sqtd); 2884 } 2885 } 2886 2887 Static ehci_soft_itd_t * 2888 ehci_alloc_itd(ehci_softc_t *sc) 2889 { 2890 struct ehci_soft_itd *itd, *freeitd; 2891 usbd_status err; 2892 int i, offs, frindex, previndex; 2893 usb_dma_t dma; 2894 2895 mutex_enter(&sc->sc_lock); 2896 2897 /* Find an itd that wasn't freed this frame or last frame. This can 2898 * discard itds that were freed before frindex wrapped around 2899 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2900 * interrupt and fiddling with list when that happens */ 2901 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2902 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2903 2904 freeitd = NULL; 2905 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2906 if (itd == NULL) 2907 break; 2908 if (itd->slot != frindex && itd->slot != previndex) { 2909 freeitd = itd; 2910 break; 2911 } 2912 } 2913 2914 if (freeitd == NULL) { 2915 DPRINTFN(2, ("ehci_alloc_itd allocating chunk\n")); 2916 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2917 EHCI_PAGE_SIZE, &dma); 2918 2919 if (err) { 2920 DPRINTF(("ehci_alloc_itd, alloc returned %d\n", err)); 2921 mutex_exit(&sc->sc_lock); 2922 return NULL; 2923 } 2924 2925 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2926 offs = i * EHCI_ITD_SIZE; 2927 itd = KERNADDR(&dma, offs); 2928 itd->physaddr = DMAADDR(&dma, offs); 2929 itd->dma = dma; 2930 itd->offs = offs; 2931 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2932 } 2933 freeitd = LIST_FIRST(&sc->sc_freeitds); 2934 } 2935 2936 itd = freeitd; 2937 LIST_REMOVE(itd, u.free_list); 2938 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2939 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2940 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 2941 BUS_DMASYNC_PREREAD); 2942 2943 itd->u.frame_list.next = NULL; 2944 itd->u.frame_list.prev = NULL; 2945 itd->xfer_next = NULL; 2946 itd->slot = 0; 2947 2948 mutex_exit(&sc->sc_lock); 2949 2950 return itd; 2951 } 2952 2953 Static void 2954 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 2955 { 2956 2957 KASSERT(mutex_owned(&sc->sc_lock)); 2958 2959 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2960 } 2961 2962 /****************/ 2963 2964 /* 2965 * Close a reqular pipe. 2966 * Assumes that there are no pending transactions. 2967 */ 2968 Static void 2969 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 2970 { 2971 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 2972 ehci_softc_t *sc = pipe->device->bus->hci_private; 2973 ehci_soft_qh_t *sqh = epipe->sqh; 2974 2975 KASSERT(mutex_owned(&sc->sc_lock)); 2976 2977 ehci_rem_qh(sc, sqh, head); 2978 ehci_free_sqh(sc, epipe->sqh); 2979 } 2980 2981 /* 2982 * Abort a device request. 2983 * If this routine is called at splusb() it guarantees that the request 2984 * will be removed from the hardware scheduling and that the callback 2985 * for it will be called with USBD_CANCELLED status. 2986 * It's impossible to guarantee that the requested transfer will not 2987 * have happened since the hardware runs concurrently. 2988 * If the transaction has already happened we rely on the ordinary 2989 * interrupt processing to process it. 2990 * XXX This is most probably wrong. 2991 * XXXMRG this doesn't make sense anymore. 2992 */ 2993 Static void 2994 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 2995 { 2996 #define exfer EXFER(xfer) 2997 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 2998 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 2999 ehci_soft_qh_t *sqh = epipe->sqh; 3000 ehci_soft_qtd_t *sqtd; 3001 ehci_physaddr_t cur; 3002 u_int32_t qhstatus; 3003 int hit; 3004 int wake; 3005 3006 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe)); 3007 3008 KASSERT(mutex_owned(&sc->sc_lock)); 3009 3010 if (sc->sc_dying) { 3011 /* If we're dying, just do the software part. */ 3012 xfer->status = status; /* make software ignore it */ 3013 callout_stop(&xfer->timeout_handle); 3014 usb_transfer_complete(xfer); 3015 return; 3016 } 3017 3018 if (cpu_intr_p() || cpu_softintr_p()) 3019 panic("ehci_abort_xfer: not in process context"); 3020 3021 /* 3022 * If an abort is already in progress then just wait for it to 3023 * complete and return. 3024 */ 3025 if (xfer->hcflags & UXFER_ABORTING) { 3026 DPRINTFN(2, ("ehci_abort_xfer: already aborting\n")); 3027 #ifdef DIAGNOSTIC 3028 if (status == USBD_TIMEOUT) 3029 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3030 #endif 3031 /* Override the status which might be USBD_TIMEOUT. */ 3032 xfer->status = status; 3033 DPRINTFN(2, ("ehci_abort_xfer: waiting for abort to finish\n")); 3034 xfer->hcflags |= UXFER_ABORTWAIT; 3035 while (xfer->hcflags & UXFER_ABORTING) 3036 cv_wait(&xfer->hccv, &sc->sc_lock); 3037 return; 3038 } 3039 xfer->hcflags |= UXFER_ABORTING; 3040 3041 /* 3042 * Step 1: Make interrupt routine and hardware ignore xfer. 3043 */ 3044 xfer->status = status; /* make software ignore it */ 3045 callout_stop(&xfer->timeout_handle); 3046 3047 usb_syncmem(&sqh->dma, 3048 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3049 sizeof(sqh->qh.qh_qtd.qtd_status), 3050 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3051 qhstatus = sqh->qh.qh_qtd.qtd_status; 3052 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3053 usb_syncmem(&sqh->dma, 3054 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3055 sizeof(sqh->qh.qh_qtd.qtd_status), 3056 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3057 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3058 usb_syncmem(&sqtd->dma, 3059 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3060 sizeof(sqtd->qtd.qtd_status), 3061 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3062 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3063 usb_syncmem(&sqtd->dma, 3064 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3065 sizeof(sqtd->qtd.qtd_status), 3066 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3067 if (sqtd == exfer->sqtdend) 3068 break; 3069 } 3070 3071 /* 3072 * Step 2: Wait until we know hardware has finished any possible 3073 * use of the xfer. Also make sure the soft interrupt routine 3074 * has run. 3075 */ 3076 ehci_sync_hc(sc); 3077 sc->sc_softwake = 1; 3078 usb_schedsoftintr(&sc->sc_bus); 3079 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3080 3081 /* 3082 * Step 3: Remove any vestiges of the xfer from the hardware. 3083 * The complication here is that the hardware may have executed 3084 * beyond the xfer we're trying to abort. So as we're scanning 3085 * the TDs of this xfer we check if the hardware points to 3086 * any of them. 3087 */ 3088 3089 usb_syncmem(&sqh->dma, 3090 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3091 sizeof(sqh->qh.qh_curqtd), 3092 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3093 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3094 hit = 0; 3095 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3096 hit |= cur == sqtd->physaddr; 3097 if (sqtd == exfer->sqtdend) 3098 break; 3099 } 3100 sqtd = sqtd->nextqtd; 3101 /* Zap curqtd register if hardware pointed inside the xfer. */ 3102 if (hit && sqtd != NULL) { 3103 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr)); 3104 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3105 usb_syncmem(&sqh->dma, 3106 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3107 sizeof(sqh->qh.qh_curqtd), 3108 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3109 sqh->qh.qh_qtd.qtd_status = qhstatus; 3110 usb_syncmem(&sqh->dma, 3111 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3112 sizeof(sqh->qh.qh_qtd.qtd_status), 3113 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3114 } else { 3115 DPRINTFN(1,("ehci_abort_xfer: no hit\n")); 3116 } 3117 3118 /* 3119 * Step 4: Execute callback. 3120 */ 3121 #ifdef DIAGNOSTIC 3122 exfer->isdone = 1; 3123 #endif 3124 wake = xfer->hcflags & UXFER_ABORTWAIT; 3125 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3126 usb_transfer_complete(xfer); 3127 if (wake) { 3128 cv_broadcast(&xfer->hccv); 3129 } 3130 3131 KASSERT(mutex_owned(&sc->sc_lock)); 3132 #undef exfer 3133 } 3134 3135 Static void 3136 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3137 { 3138 ehci_isoc_trans_t trans_status; 3139 struct ehci_pipe *epipe; 3140 struct ehci_xfer *exfer; 3141 ehci_softc_t *sc; 3142 struct ehci_soft_itd *itd; 3143 int i, wake; 3144 3145 epipe = (struct ehci_pipe *) xfer->pipe; 3146 exfer = EXFER(xfer); 3147 sc = epipe->pipe.device->bus->hci_private; 3148 3149 DPRINTF(("ehci_abort_isoc_xfer: xfer %p pipe %p\n", xfer, epipe)); 3150 3151 KASSERT(mutex_owned(&sc->sc_lock)); 3152 3153 if (sc->sc_dying) { 3154 xfer->status = status; 3155 callout_stop(&xfer->timeout_handle); 3156 usb_transfer_complete(xfer); 3157 return; 3158 } 3159 3160 if (xfer->hcflags & UXFER_ABORTING) { 3161 DPRINTFN(2, ("ehci_abort_isoc_xfer: already aborting\n")); 3162 3163 #ifdef DIAGNOSTIC 3164 if (status == USBD_TIMEOUT) 3165 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3166 #endif 3167 3168 xfer->status = status; 3169 DPRINTFN(2, ("ehci_abort_isoc_xfer: waiting for abort to finish\n")); 3170 xfer->hcflags |= UXFER_ABORTWAIT; 3171 while (xfer->hcflags & UXFER_ABORTING) 3172 cv_wait(&xfer->hccv, &sc->sc_lock); 3173 goto done; 3174 } 3175 xfer->hcflags |= UXFER_ABORTING; 3176 3177 xfer->status = status; 3178 callout_stop(&xfer->timeout_handle); 3179 3180 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3181 usb_syncmem(&itd->dma, 3182 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3183 sizeof(itd->itd.itd_ctl), 3184 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3185 3186 for (i = 0; i < 8; i++) { 3187 trans_status = le32toh(itd->itd.itd_ctl[i]); 3188 trans_status &= ~EHCI_ITD_ACTIVE; 3189 itd->itd.itd_ctl[i] = htole32(trans_status); 3190 } 3191 3192 usb_syncmem(&itd->dma, 3193 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3194 sizeof(itd->itd.itd_ctl), 3195 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3196 } 3197 3198 sc->sc_softwake = 1; 3199 usb_schedsoftintr(&sc->sc_bus); 3200 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3201 3202 #ifdef DIAGNOSTIC 3203 exfer->isdone = 1; 3204 #endif 3205 wake = xfer->hcflags & UXFER_ABORTWAIT; 3206 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3207 usb_transfer_complete(xfer); 3208 if (wake) { 3209 cv_broadcast(&xfer->hccv); 3210 } 3211 3212 done: 3213 KASSERT(mutex_owned(&sc->sc_lock)); 3214 return; 3215 } 3216 3217 Static void 3218 ehci_timeout(void *addr) 3219 { 3220 struct ehci_xfer *exfer = addr; 3221 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3222 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3223 3224 DPRINTF(("ehci_timeout: exfer=%p\n", exfer)); 3225 #ifdef EHCI_DEBUG 3226 if (ehcidebug > 1) 3227 usbd_dump_pipe(exfer->xfer.pipe); 3228 #endif 3229 3230 if (sc->sc_dying) { 3231 mutex_enter(&sc->sc_lock); 3232 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3233 mutex_exit(&sc->sc_lock); 3234 return; 3235 } 3236 3237 /* Execute the abort in a process context. */ 3238 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr, 3239 USB_TASKQ_MPSAFE); 3240 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3241 USB_TASKQ_HC); 3242 } 3243 3244 Static void 3245 ehci_timeout_task(void *addr) 3246 { 3247 usbd_xfer_handle xfer = addr; 3248 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3249 3250 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer)); 3251 3252 mutex_enter(&sc->sc_lock); 3253 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3254 mutex_exit(&sc->sc_lock); 3255 } 3256 3257 /************************/ 3258 3259 Static usbd_status 3260 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3261 { 3262 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3263 usbd_status err; 3264 3265 /* Insert last in queue. */ 3266 mutex_enter(&sc->sc_lock); 3267 err = usb_insert_transfer(xfer); 3268 mutex_exit(&sc->sc_lock); 3269 if (err) 3270 return (err); 3271 3272 /* Pipe isn't running, start first */ 3273 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3274 } 3275 3276 Static usbd_status 3277 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3278 { 3279 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3280 usbd_status err; 3281 3282 if (sc->sc_dying) 3283 return (USBD_IOERROR); 3284 3285 #ifdef DIAGNOSTIC 3286 if (!(xfer->rqflags & URQ_REQUEST)) { 3287 /* XXX panic */ 3288 printf("ehci_device_ctrl_transfer: not a request\n"); 3289 return (USBD_INVAL); 3290 } 3291 #endif 3292 3293 err = ehci_device_request(xfer); 3294 if (err) { 3295 return (err); 3296 } 3297 3298 if (sc->sc_bus.use_polling) 3299 ehci_waitintr(sc, xfer); 3300 3301 return (USBD_IN_PROGRESS); 3302 } 3303 3304 Static void 3305 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3306 { 3307 struct ehci_xfer *ex = EXFER(xfer); 3308 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3309 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3310 usb_device_request_t *req = &xfer->request; 3311 int len = UGETW(req->wLength); 3312 int rd = req->bmRequestType & UT_READ; 3313 3314 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer)); 3315 3316 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 3317 3318 #ifdef DIAGNOSTIC 3319 if (!(xfer->rqflags & URQ_REQUEST)) { 3320 panic("ehci_ctrl_done: not a request"); 3321 } 3322 #endif 3323 3324 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3325 ehci_del_intr_list(sc, ex); /* remove from active list */ 3326 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3327 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3328 BUS_DMASYNC_POSTWRITE); 3329 if (len) 3330 usb_syncmem(&xfer->dmabuf, 0, len, 3331 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3332 } 3333 3334 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen)); 3335 } 3336 3337 /* Abort a device control request. */ 3338 Static void 3339 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3340 { 3341 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer)); 3342 ehci_abort_xfer(xfer, USBD_CANCELLED); 3343 } 3344 3345 /* Close a device control pipe. */ 3346 Static void 3347 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3348 { 3349 ehci_softc_t *sc = pipe->device->bus->hci_private; 3350 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3351 3352 KASSERT(mutex_owned(&sc->sc_lock)); 3353 3354 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe)); 3355 3356 ehci_close_pipe(pipe, sc->sc_async_head); 3357 } 3358 3359 Static usbd_status 3360 ehci_device_request(usbd_xfer_handle xfer) 3361 { 3362 #define exfer EXFER(xfer) 3363 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3364 usb_device_request_t *req = &xfer->request; 3365 usbd_device_handle dev = epipe->pipe.device; 3366 ehci_softc_t *sc = dev->bus->hci_private; 3367 ehci_soft_qtd_t *setup, *stat, *next; 3368 ehci_soft_qh_t *sqh; 3369 int isread; 3370 int len; 3371 usbd_status err; 3372 3373 isread = req->bmRequestType & UT_READ; 3374 len = UGETW(req->wLength); 3375 3376 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, " 3377 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n", 3378 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3379 UGETW(req->wIndex), len, dev->address, 3380 epipe->pipe.endpoint->edesc->bEndpointAddress)); 3381 3382 setup = ehci_alloc_sqtd(sc); 3383 if (setup == NULL) { 3384 err = USBD_NOMEM; 3385 goto bad1; 3386 } 3387 stat = ehci_alloc_sqtd(sc); 3388 if (stat == NULL) { 3389 err = USBD_NOMEM; 3390 goto bad2; 3391 } 3392 3393 mutex_enter(&sc->sc_lock); 3394 3395 sqh = epipe->sqh; 3396 3397 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->address, 3398 "address QH %d pipe %d\n", 3399 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->address); 3400 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3401 UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize), 3402 "MPS QH %d pipe %d\n", 3403 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3404 UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)); 3405 3406 /* Set up data transaction */ 3407 if (len != 0) { 3408 ehci_soft_qtd_t *end; 3409 3410 /* Start toggle at 1. */ 3411 epipe->nexttoggle = 1; 3412 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3413 &next, &end); 3414 if (err) 3415 goto bad3; 3416 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3417 end->nextqtd = stat; 3418 end->qtd.qtd_next = end->qtd.qtd_altnext = 3419 htole32(stat->physaddr); 3420 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3421 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3422 } else { 3423 next = stat; 3424 } 3425 3426 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3427 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3428 3429 /* Clear toggle */ 3430 setup->qtd.qtd_status = htole32( 3431 EHCI_QTD_ACTIVE | 3432 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3433 EHCI_QTD_SET_CERR(3) | 3434 EHCI_QTD_SET_TOGGLE(0) | 3435 EHCI_QTD_SET_BYTES(sizeof *req) 3436 ); 3437 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3438 setup->qtd.qtd_buffer_hi[0] = 0; 3439 setup->nextqtd = next; 3440 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3441 setup->xfer = xfer; 3442 setup->len = sizeof *req; 3443 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3444 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3445 3446 stat->qtd.qtd_status = htole32( 3447 EHCI_QTD_ACTIVE | 3448 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3449 EHCI_QTD_SET_CERR(3) | 3450 EHCI_QTD_SET_TOGGLE(1) | 3451 EHCI_QTD_IOC 3452 ); 3453 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3454 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3455 stat->nextqtd = NULL; 3456 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3457 stat->xfer = xfer; 3458 stat->len = 0; 3459 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3460 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3461 3462 #ifdef EHCI_DEBUG 3463 if (ehcidebug > 5) { 3464 DPRINTF(("ehci_device_request:\n")); 3465 ehci_dump_sqh(sqh); 3466 ehci_dump_sqtds(setup); 3467 } 3468 #endif 3469 3470 exfer->sqtdstart = setup; 3471 exfer->sqtdend = stat; 3472 #ifdef DIAGNOSTIC 3473 if (!exfer->isdone) { 3474 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3475 } 3476 exfer->isdone = 0; 3477 #endif 3478 3479 /* Insert qTD in QH list. */ 3480 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3481 if (xfer->timeout && !sc->sc_bus.use_polling) { 3482 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3483 ehci_timeout, xfer); 3484 } 3485 ehci_add_intr_list(sc, exfer); 3486 xfer->status = USBD_IN_PROGRESS; 3487 mutex_exit(&sc->sc_lock); 3488 3489 #ifdef EHCI_DEBUG 3490 if (ehcidebug > 10) { 3491 DPRINTF(("ehci_device_request: status=%x\n", 3492 EOREAD4(sc, EHCI_USBSTS))); 3493 delay(10000); 3494 ehci_dump_regs(sc); 3495 ehci_dump_sqh(sc->sc_async_head); 3496 ehci_dump_sqh(sqh); 3497 ehci_dump_sqtds(setup); 3498 } 3499 #endif 3500 3501 return (USBD_NORMAL_COMPLETION); 3502 3503 bad3: 3504 mutex_exit(&sc->sc_lock); 3505 ehci_free_sqtd(sc, stat); 3506 bad2: 3507 ehci_free_sqtd(sc, setup); 3508 bad1: 3509 DPRINTFN(-1,("ehci_device_request: no memory\n")); 3510 mutex_enter(&sc->sc_lock); 3511 xfer->status = err; 3512 usb_transfer_complete(xfer); 3513 mutex_exit(&sc->sc_lock); 3514 return (err); 3515 #undef exfer 3516 } 3517 3518 /* 3519 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3520 * qTD status, or miss signalling occasionally under heavy load. If the host 3521 * machine is too fast, we we can miss transaction completion - when we scan 3522 * the active list the transaction still seems to be active. This generally 3523 * exhibits itself as a umass stall that never recovers. 3524 * 3525 * We work around this behaviour by setting up this callback after any softintr 3526 * that completes with transactions still pending, giving us another chance to 3527 * check for completion after the writeback has taken place. 3528 */ 3529 Static void 3530 ehci_intrlist_timeout(void *arg) 3531 { 3532 ehci_softc_t *sc = arg; 3533 3534 DPRINTF(("ehci_intrlist_timeout\n")); 3535 usb_schedsoftintr(&sc->sc_bus); 3536 } 3537 3538 /************************/ 3539 3540 Static usbd_status 3541 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3542 { 3543 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3544 usbd_status err; 3545 3546 /* Insert last in queue. */ 3547 mutex_enter(&sc->sc_lock); 3548 err = usb_insert_transfer(xfer); 3549 mutex_exit(&sc->sc_lock); 3550 if (err) 3551 return (err); 3552 3553 /* Pipe isn't running, start first */ 3554 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3555 } 3556 3557 Static usbd_status 3558 ehci_device_bulk_start(usbd_xfer_handle xfer) 3559 { 3560 #define exfer EXFER(xfer) 3561 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3562 usbd_device_handle dev = epipe->pipe.device; 3563 ehci_softc_t *sc = dev->bus->hci_private; 3564 ehci_soft_qtd_t *data, *dataend; 3565 ehci_soft_qh_t *sqh; 3566 usbd_status err; 3567 int len, isread, endpt; 3568 3569 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n", 3570 xfer, xfer->length, xfer->flags)); 3571 3572 if (sc->sc_dying) 3573 return (USBD_IOERROR); 3574 3575 #ifdef DIAGNOSTIC 3576 if (xfer->rqflags & URQ_REQUEST) 3577 panic("ehci_device_bulk_start: a request"); 3578 #endif 3579 3580 mutex_enter(&sc->sc_lock); 3581 3582 len = xfer->length; 3583 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3584 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3585 sqh = epipe->sqh; 3586 3587 epipe->u.bulk.length = len; 3588 3589 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3590 &dataend); 3591 if (err) { 3592 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n")); 3593 xfer->status = err; 3594 usb_transfer_complete(xfer); 3595 mutex_exit(&sc->sc_lock); 3596 return (err); 3597 } 3598 3599 #ifdef EHCI_DEBUG 3600 if (ehcidebug > 5) { 3601 DPRINTF(("ehci_device_bulk_start: data(1)\n")); 3602 ehci_dump_sqh(sqh); 3603 ehci_dump_sqtds(data); 3604 } 3605 #endif 3606 3607 /* Set up interrupt info. */ 3608 exfer->sqtdstart = data; 3609 exfer->sqtdend = dataend; 3610 #ifdef DIAGNOSTIC 3611 if (!exfer->isdone) { 3612 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3613 } 3614 exfer->isdone = 0; 3615 #endif 3616 3617 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3618 if (xfer->timeout && !sc->sc_bus.use_polling) { 3619 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3620 ehci_timeout, xfer); 3621 } 3622 ehci_add_intr_list(sc, exfer); 3623 xfer->status = USBD_IN_PROGRESS; 3624 mutex_exit(&sc->sc_lock); 3625 3626 #ifdef EHCI_DEBUG 3627 if (ehcidebug > 10) { 3628 DPRINTF(("ehci_device_bulk_start: data(2)\n")); 3629 delay(10000); 3630 DPRINTF(("ehci_device_bulk_start: data(3)\n")); 3631 ehci_dump_regs(sc); 3632 #if 0 3633 printf("async_head:\n"); 3634 ehci_dump_sqh(sc->sc_async_head); 3635 #endif 3636 printf("sqh:\n"); 3637 ehci_dump_sqh(sqh); 3638 ehci_dump_sqtds(data); 3639 } 3640 #endif 3641 3642 if (sc->sc_bus.use_polling) 3643 ehci_waitintr(sc, xfer); 3644 3645 return (USBD_IN_PROGRESS); 3646 #undef exfer 3647 } 3648 3649 Static void 3650 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3651 { 3652 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer)); 3653 ehci_abort_xfer(xfer, USBD_CANCELLED); 3654 } 3655 3656 /* 3657 * Close a device bulk pipe. 3658 */ 3659 Static void 3660 ehci_device_bulk_close(usbd_pipe_handle pipe) 3661 { 3662 ehci_softc_t *sc = pipe->device->bus->hci_private; 3663 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3664 3665 KASSERT(mutex_owned(&sc->sc_lock)); 3666 3667 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe)); 3668 pipe->endpoint->datatoggle = epipe->nexttoggle; 3669 ehci_close_pipe(pipe, sc->sc_async_head); 3670 } 3671 3672 Static void 3673 ehci_device_bulk_done(usbd_xfer_handle xfer) 3674 { 3675 struct ehci_xfer *ex = EXFER(xfer); 3676 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3677 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3678 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3679 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3680 3681 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n", 3682 xfer, xfer->actlen)); 3683 3684 KASSERT(mutex_owned(&sc->sc_lock)); 3685 3686 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3687 ehci_del_intr_list(sc, ex); /* remove from active list */ 3688 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3689 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3690 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3691 } 3692 3693 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen)); 3694 } 3695 3696 /************************/ 3697 3698 Static usbd_status 3699 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3700 { 3701 struct ehci_soft_islot *isp; 3702 int islot, lev; 3703 3704 /* Find a poll rate that is large enough. */ 3705 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3706 if (EHCI_ILEV_IVAL(lev) <= ival) 3707 break; 3708 3709 /* Pick an interrupt slot at the right level. */ 3710 /* XXX could do better than picking at random */ 3711 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3712 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3713 3714 sqh->islot = islot; 3715 isp = &sc->sc_islots[islot]; 3716 mutex_enter(&sc->sc_lock); 3717 ehci_add_qh(sc, sqh, isp->sqh); 3718 mutex_exit(&sc->sc_lock); 3719 3720 return (USBD_NORMAL_COMPLETION); 3721 } 3722 3723 Static usbd_status 3724 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3725 { 3726 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3727 usbd_status err; 3728 3729 /* Insert last in queue. */ 3730 mutex_enter(&sc->sc_lock); 3731 err = usb_insert_transfer(xfer); 3732 mutex_exit(&sc->sc_lock); 3733 if (err) 3734 return (err); 3735 3736 /* 3737 * Pipe isn't running (otherwise err would be USBD_INPROG), 3738 * so start it first. 3739 */ 3740 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3741 } 3742 3743 Static usbd_status 3744 ehci_device_intr_start(usbd_xfer_handle xfer) 3745 { 3746 #define exfer EXFER(xfer) 3747 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3748 usbd_device_handle dev = xfer->pipe->device; 3749 ehci_softc_t *sc = dev->bus->hci_private; 3750 ehci_soft_qtd_t *data, *dataend; 3751 ehci_soft_qh_t *sqh; 3752 usbd_status err; 3753 int len, isread, endpt; 3754 3755 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n", 3756 xfer, xfer->length, xfer->flags)); 3757 3758 if (sc->sc_dying) 3759 return (USBD_IOERROR); 3760 3761 #ifdef DIAGNOSTIC 3762 if (xfer->rqflags & URQ_REQUEST) 3763 panic("ehci_device_intr_start: a request"); 3764 #endif 3765 3766 mutex_enter(&sc->sc_lock); 3767 3768 len = xfer->length; 3769 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3770 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3771 sqh = epipe->sqh; 3772 3773 epipe->u.intr.length = len; 3774 3775 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3776 &dataend); 3777 if (err) { 3778 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n")); 3779 xfer->status = err; 3780 usb_transfer_complete(xfer); 3781 mutex_exit(&sc->sc_lock); 3782 return (err); 3783 } 3784 3785 #ifdef EHCI_DEBUG 3786 if (ehcidebug > 5) { 3787 DPRINTF(("ehci_device_intr_start: data(1)\n")); 3788 ehci_dump_sqh(sqh); 3789 ehci_dump_sqtds(data); 3790 } 3791 #endif 3792 3793 /* Set up interrupt info. */ 3794 exfer->sqtdstart = data; 3795 exfer->sqtdend = dataend; 3796 #ifdef DIAGNOSTIC 3797 if (!exfer->isdone) { 3798 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3799 } 3800 exfer->isdone = 0; 3801 #endif 3802 3803 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3804 if (xfer->timeout && !sc->sc_bus.use_polling) { 3805 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3806 ehci_timeout, xfer); 3807 } 3808 ehci_add_intr_list(sc, exfer); 3809 xfer->status = USBD_IN_PROGRESS; 3810 mutex_exit(&sc->sc_lock); 3811 3812 #ifdef EHCI_DEBUG 3813 if (ehcidebug > 10) { 3814 DPRINTF(("ehci_device_intr_start: data(2)\n")); 3815 delay(10000); 3816 DPRINTF(("ehci_device_intr_start: data(3)\n")); 3817 ehci_dump_regs(sc); 3818 printf("sqh:\n"); 3819 ehci_dump_sqh(sqh); 3820 ehci_dump_sqtds(data); 3821 } 3822 #endif 3823 3824 if (sc->sc_bus.use_polling) 3825 ehci_waitintr(sc, xfer); 3826 3827 return (USBD_IN_PROGRESS); 3828 #undef exfer 3829 } 3830 3831 Static void 3832 ehci_device_intr_abort(usbd_xfer_handle xfer) 3833 { 3834 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer)); 3835 KASSERT(xfer->pipe->intrxfer == xfer); 3836 3837 /* 3838 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3839 * async doorbell. That's dependent on the async list, wheras 3840 * intr xfers are periodic, should not use this? 3841 */ 3842 ehci_abort_xfer(xfer, USBD_CANCELLED); 3843 } 3844 3845 Static void 3846 ehci_device_intr_close(usbd_pipe_handle pipe) 3847 { 3848 ehci_softc_t *sc = pipe->device->bus->hci_private; 3849 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3850 struct ehci_soft_islot *isp; 3851 3852 KASSERT(mutex_owned(&sc->sc_lock)); 3853 3854 isp = &sc->sc_islots[epipe->sqh->islot]; 3855 ehci_close_pipe(pipe, isp->sqh); 3856 } 3857 3858 Static void 3859 ehci_device_intr_done(usbd_xfer_handle xfer) 3860 { 3861 #define exfer EXFER(xfer) 3862 struct ehci_xfer *ex = EXFER(xfer); 3863 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3864 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3865 ehci_soft_qtd_t *data, *dataend; 3866 ehci_soft_qh_t *sqh; 3867 usbd_status err; 3868 int len, isread, endpt; 3869 3870 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n", 3871 xfer, xfer->actlen)); 3872 3873 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 3874 3875 if (xfer->pipe->repeat) { 3876 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3877 3878 len = epipe->u.intr.length; 3879 xfer->length = len; 3880 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3881 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3882 usb_syncmem(&xfer->dmabuf, 0, len, 3883 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3884 sqh = epipe->sqh; 3885 3886 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3887 &data, &dataend); 3888 if (err) { 3889 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n")); 3890 xfer->status = err; 3891 return; 3892 } 3893 3894 /* Set up interrupt info. */ 3895 exfer->sqtdstart = data; 3896 exfer->sqtdend = dataend; 3897 #ifdef DIAGNOSTIC 3898 if (!exfer->isdone) { 3899 printf("ehci_device_intr_done: not done, ex=%p\n", 3900 exfer); 3901 } 3902 exfer->isdone = 0; 3903 #endif 3904 3905 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3906 if (xfer->timeout && !sc->sc_bus.use_polling) { 3907 callout_reset(&xfer->timeout_handle, 3908 mstohz(xfer->timeout), ehci_timeout, xfer); 3909 } 3910 3911 xfer->status = USBD_IN_PROGRESS; 3912 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3913 ehci_del_intr_list(sc, ex); /* remove from active list */ 3914 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3915 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3916 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3917 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3918 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3919 } 3920 #undef exfer 3921 } 3922 3923 /************************/ 3924 3925 Static usbd_status 3926 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 3927 { 3928 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3929 usbd_status err; 3930 3931 mutex_enter(&sc->sc_lock); 3932 err = usb_insert_transfer(xfer); 3933 mutex_exit(&sc->sc_lock); 3934 if (err && err != USBD_IN_PROGRESS) 3935 return err; 3936 3937 return ehci_device_isoc_start(xfer); 3938 } 3939 3940 Static usbd_status 3941 ehci_device_isoc_start(usbd_xfer_handle xfer) 3942 { 3943 struct ehci_pipe *epipe; 3944 ehci_softc_t *sc; 3945 struct ehci_xfer *exfer; 3946 ehci_soft_itd_t *itd, *prev, *start, *stop; 3947 usb_dma_t *dma_buf; 3948 int i, j, k, frames, uframes, ufrperframe; 3949 int trans_count, offs, total_length; 3950 int frindex; 3951 3952 start = NULL; 3953 prev = NULL; 3954 itd = NULL; 3955 trans_count = 0; 3956 total_length = 0; 3957 exfer = (struct ehci_xfer *) xfer; 3958 sc = xfer->pipe->device->bus->hci_private; 3959 epipe = (struct ehci_pipe *)xfer->pipe; 3960 3961 /* 3962 * To allow continuous transfers, above we start all transfers 3963 * immediately. However, we're still going to get usbd_start_next call 3964 * this when another xfer completes. So, check if this is already 3965 * in progress or not 3966 */ 3967 3968 if (exfer->itdstart != NULL) 3969 return USBD_IN_PROGRESS; 3970 3971 DPRINTFN(2, ("ehci_device_isoc_start: xfer %p len %d flags %d\n", 3972 xfer, xfer->length, xfer->flags)); 3973 3974 if (sc->sc_dying) 3975 return USBD_IOERROR; 3976 3977 /* 3978 * To avoid complication, don't allow a request right now that'll span 3979 * the entire frame table. To within 4 frames, to allow some leeway 3980 * on either side of where the hc currently is. 3981 */ 3982 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 3983 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 3984 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 3985 return USBD_INVAL; 3986 } 3987 3988 #ifdef DIAGNOSTIC 3989 if (xfer->rqflags & URQ_REQUEST) 3990 panic("ehci_device_isoc_start: request\n"); 3991 3992 if (!exfer->isdone) 3993 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 3994 exfer->isdone = 0; 3995 #endif 3996 3997 /* 3998 * Step 1: Allocate and initialize itds, how many do we need? 3999 * One per transfer if interval >= 8 microframes, fewer if we use 4000 * multiple microframes per frame. 4001 */ 4002 4003 i = epipe->pipe.endpoint->edesc->bInterval; 4004 if (i > 16 || i == 0) { 4005 /* Spec page 271 says intervals > 16 are invalid */ 4006 DPRINTF(("ehci_device_isoc_start: bInvertal %d invalid\n", i)); 4007 return USBD_INVAL; 4008 } 4009 4010 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4011 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4012 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4013 4014 if (frames == 0) { 4015 DPRINTF(("ehci_device_isoc_start: frames == 0\n")); 4016 return USBD_INVAL; 4017 } 4018 4019 dma_buf = &xfer->dmabuf; 4020 offs = 0; 4021 4022 for (i = 0; i < frames; i++) { 4023 int froffs = offs; 4024 itd = ehci_alloc_itd(sc); 4025 4026 if (prev != NULL) { 4027 prev->itd.itd_next = 4028 htole32(itd->physaddr | EHCI_LINK_ITD); 4029 usb_syncmem(&itd->dma, 4030 itd->offs + offsetof(ehci_itd_t, itd_next), 4031 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4032 4033 prev->xfer_next = itd; 4034 } else { 4035 start = itd; 4036 } 4037 4038 /* 4039 * Step 1.5, initialize uframes 4040 */ 4041 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4042 /* Calculate which page in the list this starts in */ 4043 int addr = DMAADDR(dma_buf, froffs); 4044 addr = EHCI_PAGE_OFFSET(addr); 4045 addr += (offs - froffs); 4046 addr = EHCI_PAGE(addr); 4047 addr /= EHCI_PAGE_SIZE; 4048 4049 /* This gets the initial offset into the first page, 4050 * looks how far further along the current uframe 4051 * offset is. Works out how many pages that is. 4052 */ 4053 4054 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4055 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4056 EHCI_ITD_SET_PG(addr) | 4057 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4058 4059 total_length += xfer->frlengths[trans_count]; 4060 offs += xfer->frlengths[trans_count]; 4061 trans_count++; 4062 4063 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4064 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4065 break; 4066 } 4067 } 4068 4069 /* Step 1.75, set buffer pointers. To simplify matters, all 4070 * pointers are filled out for the next 7 hardware pages in 4071 * the dma block, so no need to worry what pages to cover 4072 * and what to not. 4073 */ 4074 4075 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4076 /* 4077 * Don't try to lookup a page that's past the end 4078 * of buffer 4079 */ 4080 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4081 if (page_offs >= dma_buf->block->size) 4082 break; 4083 4084 unsigned long long page = DMAADDR(dma_buf, page_offs); 4085 page = EHCI_PAGE(page); 4086 itd->itd.itd_bufr[j] = 4087 htole32(EHCI_ITD_SET_BPTR(page)); 4088 itd->itd.itd_bufr_hi[j] = 4089 htole32(page >> 32); 4090 } 4091 4092 /* 4093 * Other special values 4094 */ 4095 4096 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4097 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4098 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4099 4100 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4101 ? 1 : 0; 4102 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4103 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4104 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4105 4106 /* FIXME: handle invalid trans */ 4107 itd->itd.itd_bufr[2] |= 4108 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4109 4110 usb_syncmem(&itd->dma, 4111 itd->offs + offsetof(ehci_itd_t, itd_next), 4112 sizeof(ehci_itd_t), 4113 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4114 4115 prev = itd; 4116 } /* End of frame */ 4117 4118 stop = itd; 4119 stop->xfer_next = NULL; 4120 exfer->isoc_len = total_length; 4121 4122 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4123 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4124 4125 /* 4126 * Part 2: Transfer descriptors have now been set up, now they must 4127 * be scheduled into the period frame list. Erk. Not wanting to 4128 * complicate matters, transfer is denied if the transfer spans 4129 * more than the period frame list. 4130 */ 4131 4132 mutex_enter(&sc->sc_lock); 4133 4134 /* Start inserting frames */ 4135 if (epipe->u.isoc.cur_xfers > 0) { 4136 frindex = epipe->u.isoc.next_frame; 4137 } else { 4138 frindex = EOREAD4(sc, EHCI_FRINDEX); 4139 frindex = frindex >> 3; /* Erase microframe index */ 4140 frindex += 2; 4141 } 4142 4143 if (frindex >= sc->sc_flsize) 4144 frindex &= (sc->sc_flsize - 1); 4145 4146 /* What's the frame interval? */ 4147 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4148 if (i / USB_UFRAMES_PER_FRAME == 0) 4149 i = 1; 4150 else 4151 i /= USB_UFRAMES_PER_FRAME; 4152 4153 itd = start; 4154 for (j = 0; j < frames; j++) { 4155 if (itd == NULL) 4156 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4157 4158 itd->itd.itd_next = sc->sc_flist[frindex]; 4159 if (itd->itd.itd_next == 0) 4160 /* FIXME: frindex table gets initialized to NULL 4161 * or EHCI_NULL? */ 4162 itd->itd.itd_next = EHCI_NULL; 4163 4164 usb_syncmem(&itd->dma, 4165 itd->offs + offsetof(ehci_itd_t, itd_next), 4166 sizeof(itd->itd.itd_next), 4167 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4168 4169 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4170 4171 usb_syncmem(&sc->sc_fldma, 4172 sizeof(ehci_link_t) * frindex, 4173 sizeof(ehci_link_t), 4174 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4175 4176 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4177 sc->sc_softitds[frindex] = itd; 4178 if (itd->u.frame_list.next != NULL) 4179 itd->u.frame_list.next->u.frame_list.prev = itd; 4180 itd->slot = frindex; 4181 itd->u.frame_list.prev = NULL; 4182 4183 frindex += i; 4184 if (frindex >= sc->sc_flsize) 4185 frindex -= sc->sc_flsize; 4186 4187 itd = itd->xfer_next; 4188 } 4189 4190 epipe->u.isoc.cur_xfers++; 4191 epipe->u.isoc.next_frame = frindex; 4192 4193 exfer->itdstart = start; 4194 exfer->itdend = stop; 4195 exfer->sqtdstart = NULL; 4196 exfer->sqtdend = NULL; 4197 4198 ehci_add_intr_list(sc, exfer); 4199 xfer->status = USBD_IN_PROGRESS; 4200 xfer->done = 0; 4201 mutex_exit(&sc->sc_lock); 4202 4203 if (sc->sc_bus.use_polling) { 4204 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4205 ehci_waitintr(sc, xfer); 4206 } 4207 4208 return USBD_IN_PROGRESS; 4209 } 4210 4211 Static void 4212 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4213 { 4214 DPRINTFN(1, ("ehci_device_isoc_abort: xfer = %p\n", xfer)); 4215 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4216 } 4217 4218 Static void 4219 ehci_device_isoc_close(usbd_pipe_handle pipe) 4220 { 4221 DPRINTFN(1, ("ehci_device_isoc_close: nothing in the pipe to free?\n")); 4222 } 4223 4224 Static void 4225 ehci_device_isoc_done(usbd_xfer_handle xfer) 4226 { 4227 struct ehci_xfer *exfer; 4228 ehci_softc_t *sc; 4229 struct ehci_pipe *epipe; 4230 4231 exfer = EXFER(xfer); 4232 sc = xfer->pipe->device->bus->hci_private; 4233 epipe = (struct ehci_pipe *) xfer->pipe; 4234 4235 KASSERT(mutex_owned(&sc->sc_lock)); 4236 4237 epipe->u.isoc.cur_xfers--; 4238 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4239 ehci_del_intr_list(sc, exfer); 4240 ehci_rem_free_itd_chain(sc, exfer); 4241 } 4242 4243 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4244 BUS_DMASYNC_POSTREAD); 4245 4246 } 4247
Indexes created Mon Sep 22 13:09:51 GMT 2025