ehci.c revision 1.23 1 /* $NetBSD: ehci.c,v 1.23 2001/11/21 16:05:13 augustss Exp $ */
2
3 /*
4 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (lennart (at) augustsson.net).
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /*
40 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
41 *
42 * The EHCI 0.96 spec can be found at
43 * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
44 * and the USB 2.0 spec at
45 * http://www.usb.org/developers/data/usb_20.zip
46 *
47 */
48
49 #include <sys/cdefs.h>
50 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.23 2001/11/21 16:05:13 augustss Exp $");
51
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/kernel.h>
55 #include <sys/malloc.h>
56 #include <sys/device.h>
57 #include <sys/select.h>
58 #include <sys/proc.h>
59 #include <sys/queue.h>
60
61 #include <machine/bus.h>
62 #include <machine/endian.h>
63
64 #include <dev/usb/usb.h>
65 #include <dev/usb/usbdi.h>
66 #include <dev/usb/usbdivar.h>
67 #include <dev/usb/usb_mem.h>
68 #include <dev/usb/usb_quirks.h>
69
70 #include <dev/usb/ehcireg.h>
71 #include <dev/usb/ehcivar.h>
72
73 #ifdef EHCI_DEBUG
74 #define DPRINTF(x) if (ehcidebug) printf x
75 #define DPRINTFN(n,x) if (ehcidebug>(n)) printf x
76 int ehcidebug = 0;
77 #ifndef __NetBSD__
78 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f))
79 #endif
80 #else
81 #define DPRINTF(x)
82 #define DPRINTFN(n,x)
83 #endif
84
85 struct ehci_pipe {
86 struct usbd_pipe pipe;
87 ehci_soft_qh_t *sqh;
88 union {
89 ehci_soft_qtd_t *qtd;
90 /* ehci_soft_itd_t *itd; */
91 } tail;
92 union {
93 /* Control pipe */
94 struct {
95 usb_dma_t reqdma;
96 u_int length;
97 /*ehci_soft_qtd_t *setup, *data, *stat;*/
98 } ctl;
99 /* Interrupt pipe */
100 /* XXX */
101 /* Bulk pipe */
102 struct {
103 u_int length;
104 } bulk;
105 /* Iso pipe */
106 /* XXX */
107 } u;
108 };
109
110 Static void ehci_shutdown(void *);
111 Static void ehci_power(int, void *);
112
113 Static usbd_status ehci_open(usbd_pipe_handle);
114 Static void ehci_poll(struct usbd_bus *);
115 Static void ehci_softintr(void *);
116 Static int ehci_intr1(ehci_softc_t *);
117 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle);
118 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *);
119 Static void ehci_idone(struct ehci_xfer *);
120 Static void ehci_timeout(void *);
121 Static void ehci_timeout_task(void *);
122
123 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t);
124 Static void ehci_freem(struct usbd_bus *, usb_dma_t *);
125
126 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *);
127 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle);
128
129 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle);
130 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle);
131 Static void ehci_root_ctrl_abort(usbd_xfer_handle);
132 Static void ehci_root_ctrl_close(usbd_pipe_handle);
133 Static void ehci_root_ctrl_done(usbd_xfer_handle);
134
135 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle);
136 Static usbd_status ehci_root_intr_start(usbd_xfer_handle);
137 Static void ehci_root_intr_abort(usbd_xfer_handle);
138 Static void ehci_root_intr_close(usbd_pipe_handle);
139 Static void ehci_root_intr_done(usbd_xfer_handle);
140
141 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle);
142 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle);
143 Static void ehci_device_ctrl_abort(usbd_xfer_handle);
144 Static void ehci_device_ctrl_close(usbd_pipe_handle);
145 Static void ehci_device_ctrl_done(usbd_xfer_handle);
146
147 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle);
148 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle);
149 Static void ehci_device_bulk_abort(usbd_xfer_handle);
150 Static void ehci_device_bulk_close(usbd_pipe_handle);
151 Static void ehci_device_bulk_done(usbd_xfer_handle);
152
153 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle);
154 Static usbd_status ehci_device_intr_start(usbd_xfer_handle);
155 Static void ehci_device_intr_abort(usbd_xfer_handle);
156 Static void ehci_device_intr_close(usbd_pipe_handle);
157 Static void ehci_device_intr_done(usbd_xfer_handle);
158
159 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle);
160 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle);
161 Static void ehci_device_isoc_abort(usbd_xfer_handle);
162 Static void ehci_device_isoc_close(usbd_pipe_handle);
163 Static void ehci_device_isoc_done(usbd_xfer_handle);
164
165 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe);
166 Static void ehci_noop(usbd_pipe_handle pipe);
167
168 Static int ehci_str(usb_string_descriptor_t *, int, char *);
169 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle);
170 Static void ehci_pcd_able(ehci_softc_t *, int);
171 Static void ehci_pcd_enable(void *);
172 Static void ehci_disown(ehci_softc_t *, int, int);
173
174 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *);
175 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *);
176
177 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *);
178 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *);
179 Static usbd_status ehci_alloc_std_chain(struct ehci_pipe *,
180 ehci_softc_t *, int, int, usbd_xfer_handle,
181 ehci_soft_qtd_t **, ehci_soft_qtd_t **);
182 Static void ehci_free_std_chain(ehci_softc_t *, ehci_soft_qtd_t *,
183 ehci_soft_qtd_t *);
184
185 Static usbd_status ehci_device_request(usbd_xfer_handle xfer);
186
187 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *);
188 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *,
189 ehci_soft_qh_t *);
190 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *);
191 Static void ehci_sync_hc(ehci_softc_t *);
192
193 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *);
194 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status);
195
196 #ifdef EHCI_DEBUG
197 Static void ehci_dump_regs(ehci_softc_t *);
198 Static void ehci_dump(void);
199 Static ehci_softc_t *theehci;
200 Static void ehci_dump_link(ehci_link_t, int);
201 Static void ehci_dump_sqtds(ehci_soft_qtd_t *);
202 Static void ehci_dump_sqtd(ehci_soft_qtd_t *);
203 Static void ehci_dump_qtd(ehci_qtd_t *);
204 Static void ehci_dump_sqh(ehci_soft_qh_t *);
205 Static void ehci_dump_exfer(struct ehci_xfer *);
206 #endif
207
208 #define MS_TO_TICKS(ms) ((ms) * hz / 1000)
209
210 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE)
211
212 #define EHCI_INTR_ENDPT 1
213
214 #define ehci_add_intr_list(sc, ex) \
215 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext);
216 #define ehci_del_intr_list(ex) \
217 LIST_REMOVE((ex), inext)
218
219 Static struct usbd_bus_methods ehci_bus_methods = {
220 ehci_open,
221 ehci_softintr,
222 ehci_poll,
223 ehci_allocm,
224 ehci_freem,
225 ehci_allocx,
226 ehci_freex,
227 };
228
229 Static struct usbd_pipe_methods ehci_root_ctrl_methods = {
230 ehci_root_ctrl_transfer,
231 ehci_root_ctrl_start,
232 ehci_root_ctrl_abort,
233 ehci_root_ctrl_close,
234 ehci_noop,
235 ehci_root_ctrl_done,
236 };
237
238 Static struct usbd_pipe_methods ehci_root_intr_methods = {
239 ehci_root_intr_transfer,
240 ehci_root_intr_start,
241 ehci_root_intr_abort,
242 ehci_root_intr_close,
243 ehci_noop,
244 ehci_root_intr_done,
245 };
246
247 Static struct usbd_pipe_methods ehci_device_ctrl_methods = {
248 ehci_device_ctrl_transfer,
249 ehci_device_ctrl_start,
250 ehci_device_ctrl_abort,
251 ehci_device_ctrl_close,
252 ehci_noop,
253 ehci_device_ctrl_done,
254 };
255
256 Static struct usbd_pipe_methods ehci_device_intr_methods = {
257 ehci_device_intr_transfer,
258 ehci_device_intr_start,
259 ehci_device_intr_abort,
260 ehci_device_intr_close,
261 ehci_device_clear_toggle,
262 ehci_device_intr_done,
263 };
264
265 Static struct usbd_pipe_methods ehci_device_bulk_methods = {
266 ehci_device_bulk_transfer,
267 ehci_device_bulk_start,
268 ehci_device_bulk_abort,
269 ehci_device_bulk_close,
270 ehci_device_clear_toggle,
271 ehci_device_bulk_done,
272 };
273
274 Static struct usbd_pipe_methods ehci_device_isoc_methods = {
275 ehci_device_isoc_transfer,
276 ehci_device_isoc_start,
277 ehci_device_isoc_abort,
278 ehci_device_isoc_close,
279 ehci_noop,
280 ehci_device_isoc_done,
281 };
282
283 usbd_status
284 ehci_init(ehci_softc_t *sc)
285 {
286 u_int32_t version, sparams, cparams, hcr;
287 u_int i;
288 usbd_status err;
289 ehci_soft_qh_t *sqh;
290
291 DPRINTF(("ehci_init: start\n"));
292 #ifdef EHCI_DEBUG
293 theehci = sc;
294 #endif
295
296 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
297
298 version = EREAD2(sc, EHCI_HCIVERSION);
299 printf("%s: EHCI version %x.%x\n", USBDEVNAME(sc->sc_bus.bdev),
300 version >> 8, version & 0xff);
301
302 sparams = EREAD4(sc, EHCI_HCSPARAMS);
303 DPRINTF(("ehci_init: sparams=0x%x\n", sparams));
304 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams);
305 if (EHCI_HCS_N_CC(sparams) != sc->sc_ncomp) {
306 printf("%s: wrong number of companions (%d != %d)\n",
307 USBDEVNAME(sc->sc_bus.bdev),
308 EHCI_HCS_N_CC(sparams), sc->sc_ncomp);
309 return (USBD_IOERROR);
310 }
311 if (sc->sc_ncomp > 0) {
312 printf("%s: companion controller%s, %d port%s each:",
313 USBDEVNAME(sc->sc_bus.bdev), sc->sc_ncomp!=1 ? "s" : "",
314 EHCI_HCS_N_PCC(sparams),
315 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "");
316 for (i = 0; i < sc->sc_ncomp; i++)
317 printf(" %s", USBDEVNAME(sc->sc_comps[i]->bdev));
318 printf("\n");
319 }
320 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
321 cparams = EREAD4(sc, EHCI_HCCPARAMS);
322 DPRINTF(("ehci_init: cparams=0x%x\n", cparams));
323
324 sc->sc_bus.usbrev = USBREV_2_0;
325
326 /* Reset the controller */
327 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev)));
328 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
329 usb_delay_ms(&sc->sc_bus, 1);
330 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
331 for (i = 0; i < 100; i++) {
332 delay(10);
333 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
334 if (!hcr)
335 break;
336 }
337 if (hcr) {
338 printf("%s: reset timeout\n", USBDEVNAME(sc->sc_bus.bdev));
339 return (USBD_IOERROR);
340 }
341
342 /* frame list size at default, read back what we got and use that */
343 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) {
344 case 0: sc->sc_flsize = 1024*4; break;
345 case 1: sc->sc_flsize = 512*4; break;
346 case 2: sc->sc_flsize = 256*4; break;
347 case 3: return (USBD_IOERROR);
348 }
349 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize,
350 EHCI_FLALIGN_ALIGN, &sc->sc_fldma);
351 if (err)
352 return (err);
353 DPRINTF(("%s: flsize=%d\n", USBDEVNAME(sc->sc_bus.bdev),sc->sc_flsize));
354
355 /* Set up the bus struct. */
356 sc->sc_bus.methods = &ehci_bus_methods;
357 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe);
358
359 sc->sc_powerhook = powerhook_establish(ehci_power, sc);
360 sc->sc_shutdownhook = shutdownhook_establish(ehci_shutdown, sc);
361
362 sc->sc_eintrs = EHCI_NORMAL_INTRS;
363
364 /* Allocate dummy QH that starts the async list. */
365 sqh = ehci_alloc_sqh(sc);
366 if (sqh == NULL) {
367 err = USBD_NOMEM;
368 goto bad1;
369 }
370 /* Fill the QH */
371 sqh->qh.qh_endp =
372 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
373 sqh->qh.qh_link =
374 htole32(sqh->physaddr | EHCI_LINK_QH);
375 sqh->qh.qh_curqtd = EHCI_NULL;
376 sqh->next = NULL;
377 /* Fill the overlay qTD */
378 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
379 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
380 sqh->qh.qh_qtd.qtd_status =
381 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED));
382 sqh->sqtd = NULL;
383 #ifdef EHCI_DEBUG
384 if (ehcidebug) {
385 ehci_dump_sqh(sc->sc_async_head);
386 }
387 #endif
388
389 /* Point to async list */
390 sc->sc_async_head = sqh;
391 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH);
392
393 usb_callout_init(sc->sc_tmo_pcd);
394
395 lockinit(&sc->sc_doorbell_lock, PZERO, "ehcidb", 0, 0);
396
397 /* Enable interrupts */
398 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
399
400 /* Turn on controller */
401 EOWRITE4(sc, EHCI_USBCMD,
402 EHCI_CMD_ITC_8 | /* 8 microframes */
403 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
404 EHCI_CMD_ASE |
405 /* EHCI_CMD_PSE | */
406 EHCI_CMD_RS);
407
408 /* Take over port ownership */
409 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
410
411 for (i = 0; i < 100; i++) {
412 delay(10);
413 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
414 if (!hcr)
415 break;
416 }
417 if (hcr) {
418 printf("%s: run timeout\n", USBDEVNAME(sc->sc_bus.bdev));
419 return (USBD_IOERROR);
420 }
421
422 return (USBD_NORMAL_COMPLETION);
423
424 #if 0
425 bad2:
426 ehci_free_sqh(sc, sc->sc_async_head);
427 #endif
428 bad1:
429 usb_freemem(&sc->sc_bus, &sc->sc_fldma);
430 return (err);
431 }
432
433 int
434 ehci_intr(void *v)
435 {
436 ehci_softc_t *sc = v;
437
438 if (sc == NULL || sc->sc_dying)
439 return (0);
440
441 /* If we get an interrupt while polling, then just ignore it. */
442 if (sc->sc_bus.use_polling) {
443 #ifdef DIAGNOSTIC
444 printf("ehci_intr: ignored interrupt while polling\n");
445 #endif
446 return (0);
447 }
448
449 return (ehci_intr1(sc));
450 }
451
452 Static int
453 ehci_intr1(ehci_softc_t *sc)
454 {
455 u_int32_t intrs, eintrs;
456
457 DPRINTFN(20,("ehci_intr1: enter\n"));
458
459 /* In case the interrupt occurs before initialization has completed. */
460 if (sc == NULL) {
461 #ifdef DIAGNOSTIC
462 printf("ehci_intr: sc == NULL\n");
463 #endif
464 return (0);
465 }
466
467 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
468
469 if (!intrs)
470 return (0);
471
472 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
473 eintrs = intrs & sc->sc_eintrs;
474 DPRINTFN(7, ("ehci_intr: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n",
475 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS),
476 (u_int)eintrs));
477 if (!eintrs)
478 return (0);
479
480 sc->sc_bus.intr_context++;
481 sc->sc_bus.no_intrs++;
482 if (eintrs & EHCI_STS_IAA) {
483 DPRINTF(("ehci_intr1: door bell\n"));
484 wakeup(&sc->sc_async_head);
485 eintrs &= ~EHCI_STS_IAA;
486 }
487 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) {
488 DPRINTF(("ehci_intr1: %s %s\n",
489 eintrs & EHCI_STS_INT ? "INT" : "",
490 eintrs & EHCI_STS_ERRINT ? "ERRINT" : ""));
491 usb_schedsoftintr(&sc->sc_bus);
492 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT);
493 }
494 if (eintrs & EHCI_STS_HSE) {
495 printf("%s: unrecoverable error, controller halted\n",
496 USBDEVNAME(sc->sc_bus.bdev));
497 /* XXX what else */
498 }
499 if (eintrs & EHCI_STS_PCD) {
500 ehci_pcd(sc, sc->sc_intrxfer);
501 /*
502 * Disable PCD interrupt for now, because it will be
503 * on until the port has been reset.
504 */
505 ehci_pcd_able(sc, 0);
506 /* Do not allow RHSC interrupts > 1 per second */
507 usb_callout(sc->sc_tmo_pcd, hz, ehci_pcd_enable, sc);
508 eintrs &= ~EHCI_STS_PCD;
509 }
510
511 sc->sc_bus.intr_context--;
512
513 if (eintrs != 0) {
514 /* Block unprocessed interrupts. */
515 sc->sc_eintrs &= ~eintrs;
516 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
517 printf("%s: blocking intrs 0x%x\n",
518 USBDEVNAME(sc->sc_bus.bdev), eintrs);
519 }
520
521 return (1);
522 }
523
524 void
525 ehci_pcd_able(ehci_softc_t *sc, int on)
526 {
527 DPRINTFN(4, ("ehci_pcd_able: on=%d\n", on));
528 if (on)
529 sc->sc_eintrs |= EHCI_STS_PCD;
530 else
531 sc->sc_eintrs &= ~EHCI_STS_PCD;
532 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
533 }
534
535 void
536 ehci_pcd_enable(void *v_sc)
537 {
538 ehci_softc_t *sc = v_sc;
539
540 ehci_pcd_able(sc, 1);
541 }
542
543 void
544 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer)
545 {
546 usbd_pipe_handle pipe;
547 struct ehci_pipe *epipe;
548 u_char *p;
549 int i, m;
550
551 if (xfer == NULL) {
552 /* Just ignore the change. */
553 return;
554 }
555
556 pipe = xfer->pipe;
557 epipe = (struct ehci_pipe *)pipe;
558
559 p = KERNADDR(&xfer->dmabuf);
560 m = min(sc->sc_noport, xfer->length * 8 - 1);
561 memset(p, 0, xfer->length);
562 for (i = 1; i <= m; i++) {
563 /* Pick out CHANGE bits from the status reg. */
564 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR)
565 p[i/8] |= 1 << (i%8);
566 }
567 DPRINTF(("ehci_pcd: change=0x%02x\n", *p));
568 xfer->actlen = xfer->length;
569 xfer->status = USBD_NORMAL_COMPLETION;
570
571 usb_transfer_complete(xfer);
572 }
573
574 void
575 ehci_softintr(void *v)
576 {
577 ehci_softc_t *sc = v;
578 struct ehci_xfer *ex;
579
580 DPRINTFN(10,("%s: ehci_softintr (%d)\n", USBDEVNAME(sc->sc_bus.bdev),
581 sc->sc_bus.intr_context));
582
583 sc->sc_bus.intr_context++;
584
585 /*
586 * The only explanation I can think of for why EHCI is as brain dead
587 * as UHCI interrupt-wise is that Intel was involved in both.
588 * An interrupt just tells us that something is done, we have no
589 * clue what, so we need to scan through all active transfers. :-(
590 */
591 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = LIST_NEXT(ex, inext))
592 ehci_check_intr(sc, ex);
593
594 sc->sc_bus.intr_context--;
595 }
596
597 /* Check for an interrupt. */
598 void
599 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
600 {
601 ehci_soft_qtd_t *sqtd, *lsqtd;
602 u_int32_t status;
603
604 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex));
605
606 if (ex->sqtdstart == NULL) {
607 printf("ehci_check_intr: sqtdstart=NULL\n");
608 return;
609 }
610 lsqtd = ex->sqtdend;
611 #ifdef DIAGNOSTIC
612 if (lsqtd == NULL) {
613 printf("ehci_check_intr: sqtd==0\n");
614 return;
615 }
616 #endif
617 /*
618 * If the last TD is still active we need to check whether there
619 * is a an error somewhere in the middle, or whether there was a
620 * short packet (SPD and not ACTIVE).
621 */
622 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) {
623 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex));
624 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) {
625 status = le32toh(sqtd->qtd.qtd_status);
626 /* If there's an active QTD the xfer isn't done. */
627 if (status & EHCI_QTD_ACTIVE)
628 break;
629 /* Any kind of error makes the xfer done. */
630 if (status & EHCI_QTD_HALTED)
631 goto done;
632 /* We want short packets, and it is short: it's done */
633 if (EHCI_QTD_SET_BYTES(status) != 0)
634 goto done;
635 }
636 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n",
637 ex, ex->sqtdstart));
638 return;
639 }
640 done:
641 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex));
642 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex);
643 ehci_idone(ex);
644 }
645
646 void
647 ehci_idone(struct ehci_xfer *ex)
648 {
649 usbd_xfer_handle xfer = &ex->xfer;
650 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
651 ehci_soft_qtd_t *sqtd;
652 u_int32_t status = 0, nstatus;
653 int actlen;
654
655 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex));
656 #ifdef DIAGNOSTIC
657 {
658 int s = splhigh();
659 if (ex->isdone) {
660 splx(s);
661 #ifdef EHCI_DEBUG
662 printf("ehci_idone: ex is done!\n ");
663 ehci_dump_exfer(ex);
664 #else
665 printf("ehci_idone: ex=%p is done!\n", ex);
666 #endif
667 return;
668 }
669 ex->isdone = 1;
670 splx(s);
671 }
672 #endif
673
674 if (xfer->status == USBD_CANCELLED ||
675 xfer->status == USBD_TIMEOUT) {
676 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer));
677 return;
678 }
679
680 #ifdef EHCI_DEBUG
681 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe));
682 if (ehcidebug > 10)
683 ehci_dump_sqtds(ex->sqtdstart);
684 #endif
685
686 /* The transfer is done, compute actual length and status. */
687 actlen = 0;
688 for (sqtd = ex->sqtdstart; sqtd != NULL; sqtd = sqtd->nextqtd) {
689 nstatus = le32toh(sqtd->qtd.qtd_status);
690 if (nstatus & EHCI_QTD_ACTIVE)
691 break;
692
693 status = nstatus;
694 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP)
695 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status);
696 }
697
698 /* If there are left over TDs we need to update the toggle. */
699 if (sqtd != NULL) {
700 printf("ehci_idone: need toggle update\n");
701 #if 0
702 epipe->nexttoggle = EHCI_TD_GET_DT(le32toh(std->td.td_token));
703 #endif
704 }
705
706 status &= EHCI_QTD_STATERRS;
707 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, status=0x%x\n",
708 xfer->length, actlen, status));
709 xfer->actlen = actlen;
710 if (status != 0) {
711 #ifdef EHCI_DEBUG
712 char sbuf[128];
713
714 bitmask_snprintf((u_int32_t)status,
715 "\20\3MISSEDMICRO\4XACT\5BABBLE\6BABBLE"
716 "\7HALTED",
717 sbuf, sizeof(sbuf));
718
719 DPRINTFN((status == EHCI_QTD_HALTED)*/*10*/2,
720 ("ehci_idone: error, addr=%d, endpt=0x%02x, "
721 "status 0x%s\n",
722 xfer->pipe->device->address,
723 xfer->pipe->endpoint->edesc->bEndpointAddress,
724 sbuf));
725 if (ehcidebug > 2) {
726 ehci_dump_sqh(epipe->sqh);
727 ehci_dump_sqtds(ex->sqtdstart);
728 }
729 #endif
730 if (status == EHCI_QTD_HALTED)
731 xfer->status = USBD_STALLED;
732 else
733 xfer->status = USBD_IOERROR; /* more info XXX */
734 } else {
735 xfer->status = USBD_NORMAL_COMPLETION;
736 }
737
738 usb_transfer_complete(xfer);
739 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex));
740 }
741
742 /*
743 * Wait here until controller claims to have an interrupt.
744 * Then call ehci_intr and return. Use timeout to avoid waiting
745 * too long.
746 */
747 void
748 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer)
749 {
750 int timo = xfer->timeout;
751 int usecs;
752 u_int32_t intrs;
753
754 xfer->status = USBD_IN_PROGRESS;
755 for (usecs = timo * 1000000 / hz; usecs > 0; usecs -= 1000) {
756 usb_delay_ms(&sc->sc_bus, 1);
757 if (sc->sc_dying)
758 break;
759 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) &
760 sc->sc_eintrs;
761 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs));
762 #ifdef OHCI_DEBUG
763 if (ehcidebug > 15)
764 ehci_dump_regs(sc);
765 #endif
766 if (intrs) {
767 ehci_intr1(sc);
768 if (xfer->status != USBD_IN_PROGRESS)
769 return;
770 }
771 }
772
773 /* Timeout */
774 DPRINTF(("ehci_waitintr: timeout\n"));
775 xfer->status = USBD_TIMEOUT;
776 usb_transfer_complete(xfer);
777 /* XXX should free TD */
778 }
779
780 void
781 ehci_poll(struct usbd_bus *bus)
782 {
783 ehci_softc_t *sc = (ehci_softc_t *)bus;
784 #ifdef EHCI_DEBUG
785 static int last;
786 int new;
787 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
788 if (new != last) {
789 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new));
790 last = new;
791 }
792 #endif
793
794 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs)
795 ehci_intr1(sc);
796 }
797
798 int
799 ehci_detach(struct ehci_softc *sc, int flags)
800 {
801 int rv = 0;
802
803 if (sc->sc_child != NULL)
804 rv = config_detach(sc->sc_child, flags);
805
806 if (rv != 0)
807 return (rv);
808
809 usb_uncallout(sc->sc_tmo_pcd, ehci_pcd_enable, sc);
810
811 if (sc->sc_powerhook != NULL)
812 powerhook_disestablish(sc->sc_powerhook);
813 if (sc->sc_shutdownhook != NULL)
814 shutdownhook_disestablish(sc->sc_shutdownhook);
815
816 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
817
818 /* XXX free other data structures XXX */
819
820 return (rv);
821 }
822
823
824 int
825 ehci_activate(device_ptr_t self, enum devact act)
826 {
827 struct ehci_softc *sc = (struct ehci_softc *)self;
828 int rv = 0;
829
830 switch (act) {
831 case DVACT_ACTIVATE:
832 return (EOPNOTSUPP);
833 break;
834
835 case DVACT_DEACTIVATE:
836 if (sc->sc_child != NULL)
837 rv = config_deactivate(sc->sc_child);
838 sc->sc_dying = 1;
839 break;
840 }
841 return (rv);
842 }
843
844 /*
845 * Handle suspend/resume.
846 *
847 * We need to switch to polling mode here, because this routine is
848 * called from an intterupt context. This is all right since we
849 * are almost suspended anyway.
850 */
851 void
852 ehci_power(int why, void *v)
853 {
854 ehci_softc_t *sc = v;
855 //u_int32_t ctl;
856 int s;
857
858 #ifdef EHCI_DEBUG
859 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why));
860 ehci_dump_regs(sc);
861 #endif
862
863 s = splhardusb();
864 switch (why) {
865 case PWR_SUSPEND:
866 case PWR_STANDBY:
867 sc->sc_bus.use_polling++;
868 #if 0
869 OOO
870 ctl = OREAD4(sc, EHCI_CONTROL) & ~EHCI_HCFS_MASK;
871 if (sc->sc_control == 0) {
872 /*
873 * Preserve register values, in case that APM BIOS
874 * does not recover them.
875 */
876 sc->sc_control = ctl;
877 sc->sc_intre = OREAD4(sc, EHCI_INTERRUPT_ENABLE);
878 }
879 ctl |= EHCI_HCFS_SUSPEND;
880 OWRITE4(sc, EHCI_CONTROL, ctl);
881 #endif
882 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
883 sc->sc_bus.use_polling--;
884 break;
885 case PWR_RESUME:
886 sc->sc_bus.use_polling++;
887 #if 0
888 OOO
889 /* Some broken BIOSes do not recover these values */
890 OWRITE4(sc, EHCI_HCCA, DMAADDR(&sc->sc_hccadma));
891 OWRITE4(sc, EHCI_CONTROL_HEAD_ED, sc->sc_ctrl_head->physaddr);
892 OWRITE4(sc, EHCI_BULK_HEAD_ED, sc->sc_bulk_head->physaddr);
893 if (sc->sc_intre)
894 OWRITE4(sc, EHCI_INTERRUPT_ENABLE,
895 sc->sc_intre & (EHCI_ALL_INTRS | EHCI_MIE));
896 if (sc->sc_control)
897 ctl = sc->sc_control;
898 else
899 ctl = OREAD4(sc, EHCI_CONTROL);
900 ctl |= EHCI_HCFS_RESUME;
901 OWRITE4(sc, EHCI_CONTROL, ctl);
902 usb_delay_ms(&sc->sc_bus, USB_RESUME_DELAY);
903 ctl = (ctl & ~EHCI_HCFS_MASK) | EHCI_HCFS_OPERATIONAL;
904 OWRITE4(sc, EHCI_CONTROL, ctl);
905 usb_delay_ms(&sc->sc_bus, USB_RESUME_RECOVERY);
906 sc->sc_control = sc->sc_intre = 0;
907 #endif
908 sc->sc_bus.use_polling--;
909 break;
910 case PWR_SOFTSUSPEND:
911 case PWR_SOFTSTANDBY:
912 case PWR_SOFTRESUME:
913 break;
914 }
915 splx(s);
916 }
917
918 /*
919 * Shut down the controller when the system is going down.
920 */
921 void
922 ehci_shutdown(void *v)
923 {
924 ehci_softc_t *sc = v;
925
926 DPRINTF(("ehci_shutdown: stopping the HC\n"));
927 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
928 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
929 }
930
931 usbd_status
932 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size)
933 {
934 struct ehci_softc *sc = (struct ehci_softc *)bus;
935
936 return (usb_allocmem(&sc->sc_bus, size, 0, dma));
937 }
938
939 void
940 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma)
941 {
942 struct ehci_softc *sc = (struct ehci_softc *)bus;
943
944 usb_freemem(&sc->sc_bus, dma);
945 }
946
947 usbd_xfer_handle
948 ehci_allocx(struct usbd_bus *bus)
949 {
950 struct ehci_softc *sc = (struct ehci_softc *)bus;
951 usbd_xfer_handle xfer;
952
953 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers);
954 if (xfer != NULL)
955 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, xfer, next);
956 else
957 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT);
958 if (xfer != NULL) {
959 memset(xfer, 0, sizeof (struct ehci_xfer));
960 #ifdef DIAGNOSTIC
961 EXFER(xfer)->isdone = 1;
962 xfer->busy_free = XFER_BUSY;
963 #endif
964 }
965 return (xfer);
966 }
967
968 void
969 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer)
970 {
971 struct ehci_softc *sc = (struct ehci_softc *)bus;
972
973 #ifdef DIAGNOSTIC
974 if (xfer->busy_free != XFER_BUSY) {
975 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer,
976 xfer->busy_free);
977 return;
978 }
979 xfer->busy_free = XFER_FREE;
980 if (!EXFER(xfer)->isdone) {
981 printf("ehci_freex: !isdone\n");
982 return;
983 }
984 #endif
985 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next);
986 }
987
988 Static void
989 ehci_device_clear_toggle(usbd_pipe_handle pipe)
990 {
991 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
992
993 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n",
994 epipe, epipe->sqh->qh.qh_qtd.qtd_status));
995 #ifdef USB_DEBUG
996 if (ehcidebug)
997 usbd_dump_pipe(pipe);
998 #endif
999 epipe->sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE);
1000 }
1001
1002 Static void
1003 ehci_noop(usbd_pipe_handle pipe)
1004 {
1005 }
1006
1007 #ifdef EHCI_DEBUG
1008 void
1009 ehci_dump_regs(ehci_softc_t *sc)
1010 {
1011 int i;
1012 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n",
1013 EOREAD4(sc, EHCI_USBCMD),
1014 EOREAD4(sc, EHCI_USBSTS),
1015 EOREAD4(sc, EHCI_USBINTR));
1016 printf("frindex=0x08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
1017 EOREAD4(sc, EHCI_FRINDEX),
1018 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
1019 EOREAD4(sc, EHCI_PERIODICLISTBASE),
1020 EOREAD4(sc, EHCI_ASYNCLISTADDR));
1021 for (i = 1; i <= sc->sc_noport; i++)
1022 printf("port %d status=0x%08x\n", i,
1023 EOREAD4(sc, EHCI_PORTSC(i)));
1024 }
1025
1026 void
1027 ehci_dump()
1028 {
1029 ehci_dump_regs(theehci);
1030 }
1031
1032 void
1033 ehci_dump_link(ehci_link_t link, int type)
1034 {
1035 link = le32toh(link);
1036 printf("0x%08x", link);
1037 if (link & EHCI_LINK_TERMINATE)
1038 printf("<T>");
1039 else {
1040 printf("<");
1041 if (type) {
1042 switch (EHCI_LINK_TYPE(link)) {
1043 case EHCI_LINK_ITD: printf("ITD"); break;
1044 case EHCI_LINK_QH: printf("QH"); break;
1045 case EHCI_LINK_SITD: printf("SITD"); break;
1046 case EHCI_LINK_FSTN: printf("FSTN"); break;
1047 }
1048 }
1049 printf(">");
1050 }
1051 }
1052
1053 void
1054 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd)
1055 {
1056 for (; sqtd; sqtd = sqtd->nextqtd)
1057 ehci_dump_sqtd(sqtd);
1058 }
1059
1060 void
1061 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd)
1062 {
1063 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr);
1064 ehci_dump_qtd(&sqtd->qtd);
1065 }
1066
1067 void
1068 ehci_dump_qtd(ehci_qtd_t *qtd)
1069 {
1070 u_int32_t s;
1071 char sbuf[128];
1072
1073 printf(" next="); ehci_dump_link(qtd->qtd_next, 0);
1074 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0);
1075 printf("\n");
1076 s = le32toh(qtd->qtd_status);
1077 bitmask_snprintf(EHCI_QTD_GET_STATUS(s),
1078 "\20\10ACTIVE\7HALTED\6BUFERR\5BABBLE\4XACTERR"
1079 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf));
1080 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
1081 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
1082 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
1083 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s),
1084 EHCI_QTD_GET_PID(s), sbuf);
1085 for (s = 0; s < 5; s++)
1086 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s]));
1087 }
1088
1089 void
1090 ehci_dump_sqh(ehci_soft_qh_t *sqh)
1091 {
1092 ehci_qh_t *qh = &sqh->qh;
1093 u_int32_t endp, endphub;
1094
1095 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr);
1096 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n");
1097 endp = le32toh(qh->qh_endp);
1098 printf(" endp=0x%08x\n", endp);
1099 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
1100 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
1101 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
1102 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
1103 printf(" mpl=0x%x ctl=%d nrl=%d\n",
1104 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
1105 EHCI_QH_GET_NRL(endp));
1106 endphub = le32toh(qh->qh_endphub);
1107 printf(" endphub=0x%08x\n", endphub);
1108 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
1109 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
1110 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
1111 EHCI_QH_GET_MULT(endphub));
1112 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n");
1113 printf("Overlay qTD:\n");
1114 ehci_dump_qtd(&qh->qh_qtd);
1115 }
1116
1117 Static void
1118 ehci_dump_exfer(struct ehci_xfer *ex)
1119 {
1120 printf("ehci_dump_exfer: ex=%p\n", ex);
1121 }
1122 #endif
1123
1124 usbd_status
1125 ehci_open(usbd_pipe_handle pipe)
1126 {
1127 usbd_device_handle dev = pipe->device;
1128 ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
1129 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
1130 u_int8_t addr = dev->address;
1131 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
1132 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1133 ehci_soft_qh_t *sqh;
1134 usbd_status err;
1135 #if 0
1136 ehci_soft_itd_t *sitd;
1137 ehci_physaddr_t tdphys;
1138 u_int32_t fmt;
1139 int ival;
1140 #endif
1141 int s;
1142 int speed, naks;
1143
1144 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
1145 pipe, addr, ed->bEndpointAddress, sc->sc_addr));
1146
1147 if (sc->sc_dying)
1148 return (USBD_IOERROR);
1149
1150 if (addr == sc->sc_addr) {
1151 switch (ed->bEndpointAddress) {
1152 case USB_CONTROL_ENDPOINT:
1153 pipe->methods = &ehci_root_ctrl_methods;
1154 break;
1155 case UE_DIR_IN | EHCI_INTR_ENDPT:
1156 pipe->methods = &ehci_root_intr_methods;
1157 break;
1158 default:
1159 return (USBD_INVAL);
1160 }
1161 return (USBD_NORMAL_COMPLETION);
1162 }
1163
1164 switch (dev->speed) {
1165 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break;
1166 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break;
1167 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break;
1168 default: panic("ehci_open: bad device speed %d\n", dev->speed);
1169 }
1170 naks = 8; /* XXX */
1171 sqh = ehci_alloc_sqh(sc);
1172 if (sqh == NULL)
1173 goto bad0;
1174 /* qh_link filled when the QH is added */
1175 sqh->qh.qh_endp = htole32(
1176 EHCI_QH_SET_ADDR(addr) |
1177 EHCI_QH_SET_ENDPT(ed->bEndpointAddress) |
1178 EHCI_QH_SET_EPS(speed) | /* XXX */
1179 /* XXX EHCI_QH_DTC ? */
1180 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) |
1181 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ?
1182 EHCI_QH_CTL : 0) |
1183 EHCI_QH_SET_NRL(naks)
1184 );
1185 sqh->qh.qh_endphub = htole32(
1186 EHCI_QH_SET_MULT(1)
1187 /* XXX TT stuff */
1188 /* XXX interrupt mask */
1189 );
1190 sqh->qh.qh_curqtd = EHCI_NULL;
1191 /* Fill the overlay qTD */
1192 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
1193 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
1194 sqh->qh.qh_qtd.qtd_status = htole32(0);
1195
1196 epipe->sqh = sqh;
1197
1198 switch (xfertype) {
1199 case UE_CONTROL:
1200 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
1201 0, &epipe->u.ctl.reqdma);
1202 if (err)
1203 goto bad1;
1204 pipe->methods = &ehci_device_ctrl_methods;
1205 s = splusb();
1206 ehci_add_qh(sqh, sc->sc_async_head);
1207 splx(s);
1208 break;
1209 case UE_BULK:
1210 pipe->methods = &ehci_device_bulk_methods;
1211 s = splusb();
1212 ehci_add_qh(sqh, sc->sc_async_head);
1213 splx(s);
1214 break;
1215 default:
1216 return (USBD_INVAL);
1217 }
1218 return (USBD_NORMAL_COMPLETION);
1219
1220 bad1:
1221 ehci_free_sqh(sc, sqh);
1222 bad0:
1223 return (USBD_NOMEM);
1224 }
1225
1226 /*
1227 * Add an ED to the schedule. Called at splusb().
1228 */
1229 void
1230 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1231 {
1232 SPLUSBCHECK;
1233
1234 sqh->next = head->next;
1235 sqh->qh.qh_link = head->qh.qh_link;
1236 head->next = sqh;
1237 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH);
1238
1239 #ifdef EHCI_DEBUG
1240 if (ehcidebug > 5) {
1241 printf("ehci_add_qh:\n");
1242 ehci_dump_sqh(sqh);
1243 }
1244 #endif
1245 }
1246
1247 /*
1248 * Remove an ED from the schedule. Called at splusb().
1249 */
1250 void
1251 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1252 {
1253 ehci_soft_qh_t *p;
1254
1255 SPLUSBCHECK;
1256 /* XXX */
1257 for (p = head; p == NULL && p->next != sqh; p = p->next)
1258 ;
1259 if (p == NULL)
1260 panic("ehci_rem_qh: ED not found\n");
1261 p->next = sqh->next;
1262 p->qh.qh_link = sqh->qh.qh_link;
1263
1264 ehci_sync_hc(sc);
1265 }
1266
1267 void
1268 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd)
1269 {
1270 /* Halt while we are messing. */
1271 sqh->qh.qh_qtd.qtd_status |= htole32(EHCI_QTD_HALTED);
1272 sqh->qh.qh_curqtd = 0;
1273 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr);
1274 sqh->sqtd = sqtd;
1275 /* Keep toggle, clear the rest, including length. */
1276 sqh->qh.qh_qtd.qtd_status &= htole32(EHCI_QTD_TOGGLE);
1277 }
1278
1279 /*
1280 * Ensure that the HC has released all references to the QH. We do this
1281 * by asking for a Async Advance Doorbell interrupt and then we wait for
1282 * the interrupt.
1283 * To make this easier we first obtain exclusive use of the doorbell.
1284 */
1285 void
1286 ehci_sync_hc(ehci_softc_t *sc)
1287 {
1288 int s, error;
1289
1290 if (sc->sc_dying) {
1291 DPRINTFN(2,("ehci_sync_hc: dying\n"));
1292 return;
1293 }
1294 DPRINTFN(2,("ehci_sync_hc: enter\n"));
1295 lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE, NULL); /* get doorbell */
1296 s = splhardusb();
1297 /* ask for doorbell */
1298 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD);
1299 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1300 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1301 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */
1302 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1303 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1304 splx(s);
1305 lockmgr(&sc->sc_doorbell_lock, LK_RELEASE, NULL); /* release doorbell */
1306 #ifdef DIAGNOSTIC
1307 if (error)
1308 printf("ehci_sync_hc: tsleep() = %d\n", error);
1309 #endif
1310 DPRINTFN(2,("ehci_sync_hc: exit\n"));
1311 }
1312
1313 /***********/
1314
1315 /*
1316 * Data structures and routines to emulate the root hub.
1317 */
1318 Static usb_device_descriptor_t ehci_devd = {
1319 USB_DEVICE_DESCRIPTOR_SIZE,
1320 UDESC_DEVICE, /* type */
1321 {0x00, 0x02}, /* USB version */
1322 UDCLASS_HUB, /* class */
1323 UDSUBCLASS_HUB, /* subclass */
1324 UDPROTO_HSHUBSTT, /* protocol */
1325 64, /* max packet */
1326 {0},{0},{0x00,0x01}, /* device id */
1327 1,2,0, /* string indicies */
1328 1 /* # of configurations */
1329 };
1330
1331 Static usb_device_qualifier_t ehci_odevd = {
1332 USB_DEVICE_DESCRIPTOR_SIZE,
1333 UDESC_DEVICE_QUALIFIER, /* type */
1334 {0x00, 0x02}, /* USB version */
1335 UDCLASS_HUB, /* class */
1336 UDSUBCLASS_HUB, /* subclass */
1337 UDPROTO_FSHUB, /* protocol */
1338 64, /* max packet */
1339 1, /* # of configurations */
1340 0
1341 };
1342
1343 Static usb_config_descriptor_t ehci_confd = {
1344 USB_CONFIG_DESCRIPTOR_SIZE,
1345 UDESC_CONFIG,
1346 {USB_CONFIG_DESCRIPTOR_SIZE +
1347 USB_INTERFACE_DESCRIPTOR_SIZE +
1348 USB_ENDPOINT_DESCRIPTOR_SIZE},
1349 1,
1350 1,
1351 0,
1352 UC_SELF_POWERED,
1353 0 /* max power */
1354 };
1355
1356 Static usb_interface_descriptor_t ehci_ifcd = {
1357 USB_INTERFACE_DESCRIPTOR_SIZE,
1358 UDESC_INTERFACE,
1359 0,
1360 0,
1361 1,
1362 UICLASS_HUB,
1363 UISUBCLASS_HUB,
1364 UIPROTO_HSHUBSTT,
1365 0
1366 };
1367
1368 Static usb_endpoint_descriptor_t ehci_endpd = {
1369 USB_ENDPOINT_DESCRIPTOR_SIZE,
1370 UDESC_ENDPOINT,
1371 UE_DIR_IN | EHCI_INTR_ENDPT,
1372 UE_INTERRUPT,
1373 {8, 0}, /* max packet */
1374 255
1375 };
1376
1377 Static usb_hub_descriptor_t ehci_hubd = {
1378 USB_HUB_DESCRIPTOR_SIZE,
1379 UDESC_HUB,
1380 0,
1381 {0,0},
1382 0,
1383 0,
1384 {0},
1385 };
1386
1387 Static int
1388 ehci_str(p, l, s)
1389 usb_string_descriptor_t *p;
1390 int l;
1391 char *s;
1392 {
1393 int i;
1394
1395 if (l == 0)
1396 return (0);
1397 p->bLength = 2 * strlen(s) + 2;
1398 if (l == 1)
1399 return (1);
1400 p->bDescriptorType = UDESC_STRING;
1401 l -= 2;
1402 for (i = 0; s[i] && l > 1; i++, l -= 2)
1403 USETW2(p->bString[i], 0, s[i]);
1404 return (2*i+2);
1405 }
1406
1407 /*
1408 * Simulate a hardware hub by handling all the necessary requests.
1409 */
1410 Static usbd_status
1411 ehci_root_ctrl_transfer(usbd_xfer_handle xfer)
1412 {
1413 usbd_status err;
1414
1415 /* Insert last in queue. */
1416 err = usb_insert_transfer(xfer);
1417 if (err)
1418 return (err);
1419
1420 /* Pipe isn't running, start first */
1421 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
1422 }
1423
1424 Static usbd_status
1425 ehci_root_ctrl_start(usbd_xfer_handle xfer)
1426 {
1427 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
1428 usb_device_request_t *req;
1429 void *buf = NULL;
1430 int port, i;
1431 int s, len, value, index, l, totlen = 0;
1432 usb_port_status_t ps;
1433 usb_hub_descriptor_t hubd;
1434 usbd_status err;
1435 u_int32_t v;
1436
1437 if (sc->sc_dying)
1438 return (USBD_IOERROR);
1439
1440 #ifdef DIAGNOSTIC
1441 if (!(xfer->rqflags & URQ_REQUEST))
1442 /* XXX panic */
1443 return (USBD_INVAL);
1444 #endif
1445 req = &xfer->request;
1446
1447 DPRINTFN(4,("ehci_root_ctrl_control type=0x%02x request=%02x\n",
1448 req->bmRequestType, req->bRequest));
1449
1450 len = UGETW(req->wLength);
1451 value = UGETW(req->wValue);
1452 index = UGETW(req->wIndex);
1453
1454 if (len != 0)
1455 buf = KERNADDR(&xfer->dmabuf);
1456
1457 #define C(x,y) ((x) | ((y) << 8))
1458 switch(C(req->bRequest, req->bmRequestType)) {
1459 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
1460 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
1461 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
1462 /*
1463 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
1464 * for the integrated root hub.
1465 */
1466 break;
1467 case C(UR_GET_CONFIG, UT_READ_DEVICE):
1468 if (len > 0) {
1469 *(u_int8_t *)buf = sc->sc_conf;
1470 totlen = 1;
1471 }
1472 break;
1473 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
1474 DPRINTFN(8,("ehci_root_ctrl_control wValue=0x%04x\n", value));
1475 switch(value >> 8) {
1476 case UDESC_DEVICE:
1477 if ((value & 0xff) != 0) {
1478 err = USBD_IOERROR;
1479 goto ret;
1480 }
1481 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
1482 USETW(ehci_devd.idVendor, sc->sc_id_vendor);
1483 memcpy(buf, &ehci_devd, l);
1484 break;
1485 /*
1486 * We can't really operate at another speed, but the spec says
1487 * we need this descriptor.
1488 */
1489 case UDESC_DEVICE_QUALIFIER:
1490 if ((value & 0xff) != 0) {
1491 err = USBD_IOERROR;
1492 goto ret;
1493 }
1494 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
1495 memcpy(buf, &ehci_odevd, l);
1496 break;
1497 /*
1498 * We can't really operate at another speed, but the spec says
1499 * we need this descriptor.
1500 */
1501 case UDESC_OTHER_SPEED_CONFIGURATION:
1502 case UDESC_CONFIG:
1503 if ((value & 0xff) != 0) {
1504 err = USBD_IOERROR;
1505 goto ret;
1506 }
1507 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
1508 memcpy(buf, &ehci_confd, l);
1509 ((usb_config_descriptor_t *)buf)->bDescriptorType =
1510 value >> 8;
1511 buf = (char *)buf + l;
1512 len -= l;
1513 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
1514 totlen += l;
1515 memcpy(buf, &ehci_ifcd, l);
1516 buf = (char *)buf + l;
1517 len -= l;
1518 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
1519 totlen += l;
1520 memcpy(buf, &ehci_endpd, l);
1521 break;
1522 case UDESC_STRING:
1523 if (len == 0)
1524 break;
1525 *(u_int8_t *)buf = 0;
1526 totlen = 1;
1527 switch (value & 0xff) {
1528 case 1: /* Vendor */
1529 totlen = ehci_str(buf, len, sc->sc_vendor);
1530 break;
1531 case 2: /* Product */
1532 totlen = ehci_str(buf, len, "EHCI root hub");
1533 break;
1534 }
1535 break;
1536 default:
1537 err = USBD_IOERROR;
1538 goto ret;
1539 }
1540 break;
1541 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
1542 if (len > 0) {
1543 *(u_int8_t *)buf = 0;
1544 totlen = 1;
1545 }
1546 break;
1547 case C(UR_GET_STATUS, UT_READ_DEVICE):
1548 if (len > 1) {
1549 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
1550 totlen = 2;
1551 }
1552 break;
1553 case C(UR_GET_STATUS, UT_READ_INTERFACE):
1554 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
1555 if (len > 1) {
1556 USETW(((usb_status_t *)buf)->wStatus, 0);
1557 totlen = 2;
1558 }
1559 break;
1560 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
1561 if (value >= USB_MAX_DEVICES) {
1562 err = USBD_IOERROR;
1563 goto ret;
1564 }
1565 sc->sc_addr = value;
1566 break;
1567 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
1568 if (value != 0 && value != 1) {
1569 err = USBD_IOERROR;
1570 goto ret;
1571 }
1572 sc->sc_conf = value;
1573 break;
1574 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
1575 break;
1576 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
1577 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
1578 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
1579 err = USBD_IOERROR;
1580 goto ret;
1581 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
1582 break;
1583 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
1584 break;
1585 /* Hub requests */
1586 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
1587 break;
1588 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
1589 DPRINTFN(8, ("ehci_root_ctrl_control: UR_CLEAR_PORT_FEATURE "
1590 "port=%d feature=%d\n",
1591 index, value));
1592 if (index < 1 || index > sc->sc_noport) {
1593 err = USBD_IOERROR;
1594 goto ret;
1595 }
1596 port = EHCI_PORTSC(index);
1597 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
1598 switch(value) {
1599 case UHF_PORT_ENABLE:
1600 EOWRITE4(sc, port, v &~ EHCI_PS_PE);
1601 break;
1602 case UHF_PORT_SUSPEND:
1603 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP);
1604 break;
1605 case UHF_PORT_POWER:
1606 EOWRITE4(sc, port, v &~ EHCI_PS_PP);
1607 break;
1608 case UHF_PORT_TEST:
1609 DPRINTFN(2,("ehci_root_ctrl_transfer: clear port test "
1610 "%d\n", index));
1611 break;
1612 case UHF_PORT_INDICATOR:
1613 DPRINTFN(2,("ehci_root_ctrl_transfer: clear port ind "
1614 "%d\n", index));
1615 EOWRITE4(sc, port, v &~ EHCI_PS_PIC);
1616 break;
1617 case UHF_C_PORT_CONNECTION:
1618 EOWRITE4(sc, port, v | EHCI_PS_CSC);
1619 break;
1620 case UHF_C_PORT_ENABLE:
1621 EOWRITE4(sc, port, v | EHCI_PS_PEC);
1622 break;
1623 case UHF_C_PORT_SUSPEND:
1624 /* how? */
1625 break;
1626 case UHF_C_PORT_OVER_CURRENT:
1627 EOWRITE4(sc, port, v | EHCI_PS_OCC);
1628 break;
1629 case UHF_C_PORT_RESET:
1630 sc->sc_isreset = 0;
1631 break;
1632 default:
1633 err = USBD_IOERROR;
1634 goto ret;
1635 }
1636 #if 0
1637 switch(value) {
1638 case UHF_C_PORT_CONNECTION:
1639 case UHF_C_PORT_ENABLE:
1640 case UHF_C_PORT_SUSPEND:
1641 case UHF_C_PORT_OVER_CURRENT:
1642 case UHF_C_PORT_RESET:
1643 /* Enable RHSC interrupt if condition is cleared. */
1644 if ((OREAD4(sc, port) >> 16) == 0)
1645 ehci_pcd_able(sc, 1);
1646 break;
1647 default:
1648 break;
1649 }
1650 #endif
1651 break;
1652 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
1653 if (value != 0) {
1654 err = USBD_IOERROR;
1655 goto ret;
1656 }
1657 hubd = ehci_hubd;
1658 hubd.bNbrPorts = sc->sc_noport;
1659 v = EOREAD4(sc, EHCI_HCSPARAMS);
1660 USETW(hubd.wHubCharacteristics,
1661 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH |
1662 EHCI_HCS_P_INCICATOR(EREAD4(sc, EHCI_HCSPARAMS))
1663 ? UHD_PORT_IND : 0);
1664 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */
1665 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
1666 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */
1667 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
1668 l = min(len, hubd.bDescLength);
1669 totlen = l;
1670 memcpy(buf, &hubd, l);
1671 break;
1672 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
1673 if (len != 4) {
1674 err = USBD_IOERROR;
1675 goto ret;
1676 }
1677 memset(buf, 0, len); /* ? XXX */
1678 totlen = len;
1679 break;
1680 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
1681 DPRINTFN(8,("ehci_root_ctrl_transfer: get port status i=%d\n",
1682 index));
1683 if (index < 1 || index > sc->sc_noport) {
1684 err = USBD_IOERROR;
1685 goto ret;
1686 }
1687 if (len != 4) {
1688 err = USBD_IOERROR;
1689 goto ret;
1690 }
1691 v = EOREAD4(sc, EHCI_PORTSC(index));
1692 DPRINTFN(8,("ehci_root_ctrl_transfer: port status=0x%04x\n",
1693 v));
1694 i = UPS_HIGH_SPEED;
1695 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS;
1696 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED;
1697 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND;
1698 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR;
1699 if (v & EHCI_PS_PR) i |= UPS_RESET;
1700 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER;
1701 USETW(ps.wPortStatus, i);
1702 i = 0;
1703 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS;
1704 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED;
1705 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR;
1706 if (sc->sc_isreset) i |= UPS_C_PORT_RESET;
1707 USETW(ps.wPortChange, i);
1708 l = min(len, sizeof ps);
1709 memcpy(buf, &ps, l);
1710 totlen = l;
1711 break;
1712 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
1713 err = USBD_IOERROR;
1714 goto ret;
1715 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
1716 break;
1717 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
1718 if (index < 1 || index > sc->sc_noport) {
1719 err = USBD_IOERROR;
1720 goto ret;
1721 }
1722 port = EHCI_PORTSC(index);
1723 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
1724 switch(value) {
1725 case UHF_PORT_ENABLE:
1726 EOWRITE4(sc, port, v | EHCI_PS_PE);
1727 break;
1728 case UHF_PORT_SUSPEND:
1729 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
1730 break;
1731 case UHF_PORT_RESET:
1732 DPRINTFN(5,("ehci_root_ctrl_transfer: reset port %d\n",
1733 index));
1734 if (EHCI_PS_IS_LOWSPEED(v)) {
1735 /* Low speed device, give up ownership. */
1736 ehci_disown(sc, index, 1);
1737 break;
1738 }
1739 /* Start reset sequence. */
1740 v &= ~ (EHCI_PS_PE | EHCI_PS_PR);
1741 EOWRITE4(sc, port, v | EHCI_PS_PR);
1742 /* Wait for reset to complete. */
1743 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
1744 if (sc->sc_dying) {
1745 err = USBD_IOERROR;
1746 goto ret;
1747 }
1748 /* Terminate reset sequence. */
1749 EOWRITE4(sc, port, v);
1750 /* Wait for HC to complete reset. */
1751 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE);
1752 if (sc->sc_dying) {
1753 err = USBD_IOERROR;
1754 goto ret;
1755 }
1756 v = EOREAD4(sc, port);
1757 DPRINTF(("ehci after reset, status=0x%08x\n", v));
1758 if (v & EHCI_PS_PR) {
1759 printf("%s: port reset timeout\n",
1760 USBDEVNAME(sc->sc_bus.bdev));
1761 return (USBD_TIMEOUT);
1762 }
1763 if (!(v & EHCI_PS_PE)) {
1764 /* Not a high speed device, give up ownership.*/
1765 ehci_disown(sc, index, 0);
1766 break;
1767 }
1768 sc->sc_isreset = 1;
1769 DPRINTF(("ehci port %d reset, status = 0x%08x\n",
1770 index, v));
1771 break;
1772 case UHF_PORT_POWER:
1773 DPRINTFN(2,("ehci_root_ctrl_transfer: set port power "
1774 "%d\n", index));
1775 EOWRITE4(sc, port, v | EHCI_PS_PP);
1776 break;
1777 case UHF_PORT_TEST:
1778 DPRINTFN(2,("ehci_root_ctrl_transfer: set port test "
1779 "%d\n", index));
1780 break;
1781 case UHF_PORT_INDICATOR:
1782 DPRINTFN(2,("ehci_root_ctrl_transfer: set port ind "
1783 "%d\n", index));
1784 EOWRITE4(sc, port, v | EHCI_PS_PIC);
1785 break;
1786 default:
1787 err = USBD_IOERROR;
1788 goto ret;
1789 }
1790 break;
1791 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
1792 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
1793 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
1794 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
1795 break;
1796 default:
1797 err = USBD_IOERROR;
1798 goto ret;
1799 }
1800 xfer->actlen = totlen;
1801 err = USBD_NORMAL_COMPLETION;
1802 ret:
1803 xfer->status = err;
1804 s = splusb();
1805 usb_transfer_complete(xfer);
1806 splx(s);
1807 return (USBD_IN_PROGRESS);
1808 }
1809
1810 void
1811 ehci_disown(ehci_softc_t *sc, int index, int lowspeed)
1812 {
1813 int i, port;
1814 u_int32_t v;
1815
1816 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed));
1817 #ifdef DIAGNOSTIC
1818 if (sc->sc_npcomp != 0) {
1819 i = (index-1) / sc->sc_npcomp;
1820 if (i >= sc->sc_ncomp)
1821 printf("%s: strange port\n",
1822 USBDEVNAME(sc->sc_bus.bdev));
1823 else
1824 printf("%s: handing over %s speed device on "
1825 "port %d to %s\n",
1826 USBDEVNAME(sc->sc_bus.bdev),
1827 lowspeed ? "low" : "full",
1828 index, USBDEVNAME(sc->sc_comps[i]->bdev));
1829 } else {
1830 printf("%s: npcomp == 0\n", USBDEVNAME(sc->sc_bus.bdev));
1831 }
1832 #endif
1833 port = EHCI_PORTSC(index);
1834 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
1835 EOWRITE4(sc, port, v | EHCI_PS_PO);
1836 }
1837
1838 /* Abort a root control request. */
1839 Static void
1840 ehci_root_ctrl_abort(usbd_xfer_handle xfer)
1841 {
1842 /* Nothing to do, all transfers are synchronous. */
1843 }
1844
1845 /* Close the root pipe. */
1846 Static void
1847 ehci_root_ctrl_close(usbd_pipe_handle pipe)
1848 {
1849 DPRINTF(("ehci_root_ctrl_close\n"));
1850 /* Nothing to do. */
1851 }
1852
1853 void
1854 ehci_root_intr_done(usbd_xfer_handle xfer)
1855 {
1856 xfer->hcpriv = NULL;
1857 }
1858
1859 Static usbd_status
1860 ehci_root_intr_transfer(usbd_xfer_handle xfer)
1861 {
1862 usbd_status err;
1863
1864 /* Insert last in queue. */
1865 err = usb_insert_transfer(xfer);
1866 if (err)
1867 return (err);
1868
1869 /* Pipe isn't running, start first */
1870 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
1871 }
1872
1873 Static usbd_status
1874 ehci_root_intr_start(usbd_xfer_handle xfer)
1875 {
1876 usbd_pipe_handle pipe = xfer->pipe;
1877 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
1878
1879 if (sc->sc_dying)
1880 return (USBD_IOERROR);
1881
1882 sc->sc_intrxfer = xfer;
1883
1884 return (USBD_IN_PROGRESS);
1885 }
1886
1887 /* Abort a root interrupt request. */
1888 Static void
1889 ehci_root_intr_abort(usbd_xfer_handle xfer)
1890 {
1891 int s;
1892
1893 if (xfer->pipe->intrxfer == xfer) {
1894 DPRINTF(("ehci_root_intr_abort: remove\n"));
1895 xfer->pipe->intrxfer = NULL;
1896 }
1897 xfer->status = USBD_CANCELLED;
1898 s = splusb();
1899 usb_transfer_complete(xfer);
1900 splx(s);
1901 }
1902
1903 /* Close the root pipe. */
1904 Static void
1905 ehci_root_intr_close(usbd_pipe_handle pipe)
1906 {
1907 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
1908
1909 DPRINTF(("ehci_root_intr_close\n"));
1910
1911 sc->sc_intrxfer = NULL;
1912 }
1913
1914 void
1915 ehci_root_ctrl_done(usbd_xfer_handle xfer)
1916 {
1917 xfer->hcpriv = NULL;
1918 }
1919
1920 /************************/
1921
1922 ehci_soft_qh_t *
1923 ehci_alloc_sqh(ehci_softc_t *sc)
1924 {
1925 ehci_soft_qh_t *sqh;
1926 usbd_status err;
1927 int i, offs;
1928 usb_dma_t dma;
1929
1930 if (sc->sc_freeqhs == NULL) {
1931 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n"));
1932 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK,
1933 EHCI_PAGE_SIZE, &dma);
1934 if (err)
1935 return (NULL);
1936 for(i = 0; i < EHCI_SQH_CHUNK; i++) {
1937 offs = i * EHCI_SQH_SIZE;
1938 sqh = (ehci_soft_qh_t *)((char *)KERNADDR(&dma) + offs);
1939 sqh->physaddr = DMAADDR(&dma) + offs;
1940 sqh->next = sc->sc_freeqhs;
1941 sc->sc_freeqhs = sqh;
1942 }
1943 }
1944 sqh = sc->sc_freeqhs;
1945 sc->sc_freeqhs = sqh->next;
1946 memset(&sqh->qh, 0, sizeof(ehci_qh_t));
1947 sqh->next = NULL;
1948 return (sqh);
1949 }
1950
1951 void
1952 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh)
1953 {
1954 sqh->next = sc->sc_freeqhs;
1955 sc->sc_freeqhs = sqh;
1956 }
1957
1958 ehci_soft_qtd_t *
1959 ehci_alloc_sqtd(ehci_softc_t *sc)
1960 {
1961 ehci_soft_qtd_t *sqtd;
1962 usbd_status err;
1963 int i, offs;
1964 usb_dma_t dma;
1965 int s;
1966
1967 if (sc->sc_freeqtds == NULL) {
1968 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n"));
1969 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK,
1970 EHCI_PAGE_SIZE, &dma);
1971 if (err)
1972 return (NULL);
1973 s = splusb();
1974 for(i = 0; i < EHCI_SQTD_CHUNK; i++) {
1975 offs = i * EHCI_SQTD_SIZE;
1976 sqtd = (ehci_soft_qtd_t *)((char *)KERNADDR(&dma)+offs);
1977 sqtd->physaddr = DMAADDR(&dma) + offs;
1978 sqtd->nextqtd = sc->sc_freeqtds;
1979 sc->sc_freeqtds = sqtd;
1980 }
1981 splx(s);
1982 }
1983
1984 s = splusb();
1985 sqtd = sc->sc_freeqtds;
1986 sc->sc_freeqtds = sqtd->nextqtd;
1987 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t));
1988 sqtd->nextqtd = NULL;
1989 sqtd->xfer = NULL;
1990 splx(s);
1991
1992 return (sqtd);
1993 }
1994
1995 void
1996 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd)
1997 {
1998 int s;
1999
2000 s = splusb();
2001 sqtd->nextqtd = sc->sc_freeqtds;
2002 sc->sc_freeqtds = sqtd;
2003 splx(s);
2004 }
2005
2006 usbd_status
2007 ehci_alloc_std_chain(struct ehci_pipe *epipe, ehci_softc_t *sc,
2008 int alen, int rd, usbd_xfer_handle xfer,
2009 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep)
2010 {
2011 ehci_soft_qtd_t *next, *cur;
2012 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys;
2013 u_int32_t qtdstatus;
2014 int len, curlen;
2015 int i;
2016 usb_dma_t *dma = &xfer->dmabuf;
2017
2018 DPRINTFN(alen < 4096,("ehci_alloc_std_chain: start len=%d\n", alen));
2019
2020 len = alen;
2021 dataphys = DMAADDR(dma);
2022 dataphyslastpage = EHCI_PAGE(dataphys + len - 1);
2023 qtdstatus = htole32(
2024 EHCI_QTD_SET_STATUS(EHCI_QTD_ACTIVE) |
2025 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) |
2026 EHCI_QTD_SET_CERR(3)
2027 /* IOC set below */
2028 /* BYTES set below */
2029 /* XXX Data toggle */
2030 );
2031
2032 cur = ehci_alloc_sqtd(sc);
2033 if (cur == NULL)
2034 goto nomem;
2035 *sp = cur;
2036 for (;;) {
2037 dataphyspage = EHCI_PAGE(dataphys);
2038 /* The EHCI hardware can handle at most 4 page crossings. */
2039 if (dataphyslastpage - dataphyspage < EHCI_QTD_NBUFFERS) {
2040 /* we can handle it in this QTD */
2041 curlen = len;
2042 } else {
2043 DPRINTF(("ehci_alloc_std_chain: multiple QTDs\n"));
2044
2045 /* must use multiple TDs, fill as much as possible. */
2046 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE -
2047 EHCI_PAGE_OFFSET(dataphys);
2048
2049 /* XXX true for EHCI? */
2050 /* the length must be a multiple of the max size */
2051 curlen -= curlen % UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize);
2052 #ifdef DIAGNOSTIC
2053 if (curlen == 0)
2054 panic("ehci_alloc_std: curlen == 0\n");
2055 #endif
2056 }
2057 DPRINTFN(4,("ehci_alloc_std_chain: dataphys=0x%08x "
2058 "dataphyslastpage=0x%08x len=%d curlen=%d\n",
2059 dataphys, dataphyslastpage,
2060 len, curlen));
2061 len -= curlen;
2062
2063 if (len != 0) {
2064 next = ehci_alloc_sqtd(sc);
2065 if (next == NULL)
2066 goto nomem;
2067 nextphys = next->physaddr;
2068 } else {
2069 next = NULL;
2070 nextphys = EHCI_NULL;
2071 }
2072
2073 for (i = 0; i * EHCI_PAGE_SIZE < curlen; i++) {
2074 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE;
2075 if (i != 0) /* use offset only in first buffer */
2076 a = EHCI_PAGE(a);
2077 cur->qtd.qtd_buffer[i] = htole32(a);
2078 }
2079 cur->nextqtd = next;
2080 cur->qtd.qtd_next = cur->qtd.qtd_altnext = htole32(nextphys);
2081 cur->qtd.qtd_status =
2082 qtdstatus | htole32(EHCI_QTD_SET_BYTES(curlen));
2083 cur->xfer = xfer;
2084 cur->len = curlen;
2085 DPRINTFN(10,("ehci_alloc_std_chain: cbp=0x%08x be=0x%08x\n",
2086 dataphys, dataphys + curlen - 1));
2087 if (len == 0)
2088 break;
2089 DPRINTFN(10,("ehci_alloc_std_chain: extend chain\n"));
2090 dataphys += curlen;
2091 cur = next;
2092 }
2093 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC);
2094 *ep = cur;
2095
2096 return (USBD_NORMAL_COMPLETION);
2097
2098 nomem:
2099 /* XXX free chain */
2100 return (USBD_NOMEM);
2101 }
2102
2103 Static void
2104 ehci_free_std_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd,
2105 ehci_soft_qtd_t *sqtdend)
2106 {
2107 ehci_soft_qtd_t *p;
2108
2109 for (; sqtd != sqtdend; sqtd = p) {
2110 p = sqtd->nextqtd;
2111 ehci_free_sqtd(sc, sqtd);
2112 }
2113 }
2114
2115 /****************/
2116
2117 /*
2118 * Close a reqular pipe.
2119 * Assumes that there are no pending transactions.
2120 */
2121 void
2122 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head)
2123 {
2124 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
2125 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2126 ehci_soft_qh_t *sqh = epipe->sqh;
2127 int s;
2128
2129 s = splusb();
2130 ehci_rem_qh(sc, sqh, head);
2131 splx(s);
2132 ehci_free_sqh(sc, epipe->sqh);
2133 }
2134
2135 /*
2136 * Abort a device request.
2137 * If this routine is called at splusb() it guarantees that the request
2138 * will be removed from the hardware scheduling and that the callback
2139 * for it will be called with USBD_CANCELLED status.
2140 * It's impossible to guarantee that the requested transfer will not
2141 * have happened since the hardware runs concurrently.
2142 * If the transaction has already happened we rely on the ordinary
2143 * interrupt processing to process it.
2144 */
2145 void
2146 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
2147 {
2148 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2149 ehci_soft_qh_t *sqh = epipe->sqh;
2150 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus;
2151 #if 0
2152 ehci_soft_td_t *p, *n;
2153 ehci_physaddr_t headp;
2154 int hit;
2155 #endif
2156 int s;
2157
2158 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p sqh=%p\n", xfer, epipe,sqh));
2159
2160 if (sc->sc_dying) {
2161 /* If we're dying, just do the software part. */
2162 s = splusb();
2163 xfer->status = status; /* make software ignore it */
2164 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer);
2165 usb_transfer_complete(xfer);
2166 splx(s);
2167 return;
2168 }
2169
2170 if (xfer->device->bus->intr_context || !curproc)
2171 panic("ehci_abort_xfer: not in process context\n");
2172
2173 /*
2174 * Step 1: Make interrupt routine and hardware ignore xfer.
2175 */
2176 s = splusb();
2177 xfer->status = status; /* make software ignore it */
2178 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer);
2179 splx(s);
2180 /* XXX */
2181
2182 /*
2183 * Step 2: Wait until we know hardware has finished any possible
2184 * use of the xfer. Also make sure the soft interrupt routine
2185 * has run.
2186 */
2187 usb_delay_ms(epipe->pipe.device->bus, 1); /* Hardware finishes in 1ms */
2188 /* XXX should have some communication with softintr() to know
2189 when it's done */
2190 usb_delay_ms(epipe->pipe.device->bus, 250);
2191
2192 /*
2193 * Step 3: Remove any vestiges of the xfer from the hardware.
2194 * The complication here is that the hardware may have executed
2195 * beyond the xfer we're trying to abort. So as we're scanning
2196 * the TDs of this xfer we check if the hardware points to
2197 * any of them.
2198 */
2199 s = splusb(); /* XXX why? */
2200 /* XXX */
2201
2202 /*
2203 * Step 4: Turn on hardware again.
2204 */
2205 /* XXX */
2206
2207 /*
2208 * Step 5: Execute callback.
2209 */
2210 #ifdef DIAGNOSTIC
2211 EXFER(xfer)->isdone = 1;
2212 #endif
2213 usb_transfer_complete(xfer);
2214
2215 splx(s);
2216 }
2217
2218 void
2219 ehci_timeout(void *addr)
2220 {
2221 struct ehci_xfer *exfer = addr;
2222 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe;
2223 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus;
2224
2225 DPRINTF(("ehci_timeout: exfer=%p\n", exfer));
2226 #ifdef USB_DEBUG
2227 if (ehcidebug)
2228 usbd_dump_pipe(exfer->xfer.pipe);
2229 #endif
2230
2231 if (sc->sc_dying) {
2232 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT);
2233 return;
2234 }
2235
2236 /* Execute the abort in a process context. */
2237 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr);
2238 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task);
2239 }
2240
2241 void
2242 ehci_timeout_task(void *addr)
2243 {
2244 usbd_xfer_handle xfer = addr;
2245 int s;
2246
2247 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer));
2248
2249 s = splusb();
2250 ehci_abort_xfer(xfer, USBD_TIMEOUT);
2251 splx(s);
2252 }
2253
2254 /************************/
2255
2256 Static usbd_status
2257 ehci_device_ctrl_transfer(usbd_xfer_handle xfer)
2258 {
2259 usbd_status err;
2260
2261 /* Insert last in queue. */
2262 err = usb_insert_transfer(xfer);
2263 if (err)
2264 return (err);
2265
2266 /* Pipe isn't running, start first */
2267 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2268 }
2269
2270 Static usbd_status
2271 ehci_device_ctrl_start(usbd_xfer_handle xfer)
2272 {
2273 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2274 usbd_status err;
2275
2276 if (sc->sc_dying)
2277 return (USBD_IOERROR);
2278
2279 #ifdef DIAGNOSTIC
2280 if (!(xfer->rqflags & URQ_REQUEST)) {
2281 /* XXX panic */
2282 printf("ehci_device_ctrl_transfer: not a request\n");
2283 return (USBD_INVAL);
2284 }
2285 #endif
2286
2287 err = ehci_device_request(xfer);
2288 if (err)
2289 return (err);
2290
2291 if (sc->sc_bus.use_polling)
2292 ehci_waitintr(sc, xfer);
2293 return (USBD_IN_PROGRESS);
2294 }
2295
2296 void
2297 ehci_device_ctrl_done(usbd_xfer_handle xfer)
2298 {
2299 struct ehci_xfer *ex = EXFER(xfer);
2300 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2301 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2302
2303 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer));
2304
2305 #ifdef DIAGNOSTIC
2306 if (!(xfer->rqflags & URQ_REQUEST)) {
2307 panic("ehci_ctrl_done: not a request\n");
2308 }
2309 #endif
2310
2311 ehci_del_intr_list(ex); /* remove from active list */
2312
2313 if (epipe->u.ctl.length != 0)
2314 ehci_free_std_chain(sc, ex->sqtdstart, NULL);
2315
2316 DPRINTFN(5, ("uhci_ctrl_done: length=%d\n", xfer->actlen));
2317 }
2318
2319 /* Abort a device control request. */
2320 Static void
2321 ehci_device_ctrl_abort(usbd_xfer_handle xfer)
2322 {
2323 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer));
2324 ehci_abort_xfer(xfer, USBD_CANCELLED);
2325 }
2326
2327 /* Close a device control pipe. */
2328 Static void
2329 ehci_device_ctrl_close(usbd_pipe_handle pipe)
2330 {
2331 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2332 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/
2333
2334 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe));
2335 ehci_close_pipe(pipe, sc->sc_async_head);
2336 }
2337
2338 usbd_status
2339 ehci_device_request(usbd_xfer_handle xfer)
2340 {
2341 #define exfer EXFER(xfer)
2342 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2343 usb_device_request_t *req = &xfer->request;
2344 usbd_device_handle dev = epipe->pipe.device;
2345 ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
2346 int addr = dev->address;
2347 ehci_soft_qtd_t *setup, *stat, *next;
2348 ehci_soft_qh_t *sqh;
2349 int isread;
2350 int len;
2351 usbd_status err;
2352 int s;
2353
2354 isread = req->bmRequestType & UT_READ;
2355 len = UGETW(req->wLength);
2356
2357 DPRINTFN(3,("ehci_device_control type=0x%02x, request=0x%02x, "
2358 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
2359 req->bmRequestType, req->bRequest, UGETW(req->wValue),
2360 UGETW(req->wIndex), len, addr,
2361 epipe->pipe.endpoint->edesc->bEndpointAddress));
2362
2363 setup = ehci_alloc_sqtd(sc);
2364 if (setup == NULL) {
2365 err = USBD_NOMEM;
2366 goto bad1;
2367 }
2368 stat = ehci_alloc_sqtd(sc);
2369 if (stat == NULL) {
2370 err = USBD_NOMEM;
2371 goto bad2;
2372 }
2373
2374 sqh = epipe->sqh;
2375 epipe->u.ctl.length = len;
2376
2377 /* XXX
2378 * Since we're messing with the QH we must know the HC is in sync.
2379 * This needs to go away since it slows down control transfers.
2380 * Removing it entails:
2381 * - fill the QH only once with addr & wMaxPacketSize
2382 * - put the correct data toggles in the qtds and set DTC
2383 */
2384 /* ehci_sync_hc(sc); */
2385 /* Update device address and length since they may have changed. */
2386 /* XXX This only needs to be done once, but it's too early in open. */
2387 /* XXXX Should not touch ED here! */
2388 sqh->qh.qh_endp =
2389 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QG_MPLMASK))) |
2390 htole32(
2391 EHCI_QH_SET_ADDR(addr) |
2392 /* EHCI_QH_DTC | */
2393 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize))
2394 );
2395 /* Clear toggle */
2396 sqh->qh.qh_qtd.qtd_status &= htole32(~EHCI_QTD_TOGGLE);
2397
2398 /* Set up data transaction */
2399 if (len != 0) {
2400 ehci_soft_qtd_t *end;
2401
2402 err = ehci_alloc_std_chain(epipe, sc, len, isread, xfer,
2403 &next, &end);
2404 if (err)
2405 goto bad3;
2406 end->nextqtd = stat;
2407 end->qtd.qtd_next =
2408 end->qtd.qtd_altnext = htole32(stat->physaddr);
2409 /* Start toggle at 1. */
2410 /*next->qtd.td_flags |= htole32(EHCI_QTD_TOGGLE);*/
2411 } else {
2412 next = stat;
2413 }
2414
2415 memcpy(KERNADDR(&epipe->u.ctl.reqdma), req, sizeof *req);
2416
2417 setup->qtd.qtd_status = htole32(
2418 EHCI_QTD_SET_STATUS(EHCI_QTD_ACTIVE) |
2419 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
2420 EHCI_QTD_SET_CERR(3) |
2421 EHCI_QTD_SET_BYTES(sizeof *req)
2422 );
2423 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma));
2424 setup->nextqtd = next;
2425 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr);
2426 setup->xfer = xfer;
2427 setup->len = sizeof *req;
2428
2429 stat->qtd.qtd_status = htole32(
2430 EHCI_QTD_SET_STATUS(EHCI_QTD_ACTIVE) |
2431 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) |
2432 EHCI_QTD_SET_CERR(3) |
2433 EHCI_QTD_IOC
2434 );
2435 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */
2436 stat->nextqtd = NULL;
2437 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL;
2438 stat->xfer = xfer;
2439 stat->len = 0;
2440
2441 #ifdef EHCI_DEBUG
2442 if (ehcidebug > 5) {
2443 DPRINTF(("ehci_device_request:\n"));
2444 ehci_dump_sqh(sqh);
2445 ehci_dump_sqtds(setup);
2446 }
2447 #endif
2448
2449 exfer->sqtdstart = setup;
2450 exfer->sqtdend = stat;
2451 #ifdef DIAGNOSTIC
2452 if (!exfer->isdone) {
2453 printf("ehci_device_request: not done, exfer=%p\n", exfer);
2454 }
2455 exfer->isdone = 0;
2456 #endif
2457
2458 /* Insert qTD in QH list. */
2459 s = splusb();
2460 ehci_set_qh_qtd(sqh, setup);
2461 if (xfer->timeout && !sc->sc_bus.use_polling) {
2462 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout),
2463 ehci_timeout, xfer);
2464 }
2465 ehci_add_intr_list(sc, exfer);
2466 xfer->status = USBD_IN_PROGRESS;
2467 splx(s);
2468
2469 #ifdef EHCI_DEBUG
2470 if (ehcidebug > 10) {
2471 DPRINTF(("ehci_device_request: status=%x\n",
2472 EOREAD4(sc, EHCI_USBSTS)));
2473 delay(10000);
2474 ehci_dump_regs(sc);
2475 ehci_dump_sqh(sc->sc_async_head);
2476 ehci_dump_sqh(sqh);
2477 ehci_dump_sqtds(setup);
2478 }
2479 #endif
2480
2481 return (USBD_NORMAL_COMPLETION);
2482
2483 bad3:
2484 ehci_free_sqtd(sc, stat);
2485 bad2:
2486 ehci_free_sqtd(sc, setup);
2487 bad1:
2488 return (err);
2489 #undef exfer
2490 }
2491
2492 /************************/
2493
2494 Static usbd_status
2495 ehci_device_bulk_transfer(usbd_xfer_handle xfer)
2496 {
2497 usbd_status err;
2498
2499 /* Insert last in queue. */
2500 err = usb_insert_transfer(xfer);
2501 if (err)
2502 return (err);
2503
2504 /* Pipe isn't running, start first */
2505 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2506 }
2507
2508 usbd_status
2509 ehci_device_bulk_start(usbd_xfer_handle xfer)
2510 {
2511 #define exfer EXFER(xfer)
2512 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2513 usbd_device_handle dev = epipe->pipe.device;
2514 ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
2515 ehci_soft_qtd_t *data, *dataend;
2516 ehci_soft_qh_t *sqh;
2517 usbd_status err;
2518 int len, isread, endpt;
2519 int s;
2520
2521 DPRINTFN(2, ("ehci_device_bulk_transfer: xfer=%p len=%d flags=%d\n",
2522 xfer, xfer->length, xfer->flags));
2523
2524 if (sc->sc_dying)
2525 return (USBD_IOERROR);
2526
2527 #ifdef DIAGNOSTIC
2528 if (xfer->rqflags & URQ_REQUEST)
2529 panic("ehci_device_bulk_transfer: a request\n");
2530 #endif
2531
2532 len = xfer->length;
2533 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
2534 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2535 sqh = epipe->sqh;
2536
2537 epipe->u.bulk.length = len;
2538
2539 err = ehci_alloc_std_chain(epipe, sc, len, isread, xfer, &data,
2540 &dataend);
2541 if (err)
2542 return (err);
2543
2544 #ifdef EHCI_DEBUG
2545 if (ehcidebug > 5) {
2546 DPRINTF(("ehci_device_bulk_transfer: data(1)\n"));
2547 ehci_dump_sqh(sqh);
2548 ehci_dump_sqtds(data);
2549 }
2550 #endif
2551
2552 /* Set up interrupt info. */
2553 exfer->sqtdstart = data;
2554 exfer->sqtdend = dataend;
2555 #ifdef DIAGNOSTIC
2556 if (!exfer->isdone) {
2557 printf("ehci_device_bulk_transfer: not done, ex=%p\n", exfer);
2558 }
2559 exfer->isdone = 0;
2560 #endif
2561
2562 s = splusb();
2563 ehci_set_qh_qtd(sqh, data);
2564 if (xfer->timeout && !sc->sc_bus.use_polling) {
2565 usb_callout(xfer->timeout_handle, MS_TO_TICKS(xfer->timeout),
2566 ehci_timeout, xfer);
2567 }
2568 ehci_add_intr_list(sc, exfer);
2569 xfer->status = USBD_IN_PROGRESS;
2570 splx(s);
2571
2572 #ifdef EHCI_DEBUG
2573 if (ehcidebug > 10) {
2574 DPRINTF(("ehci_device_bulk_transfer: data(2)\n"));
2575 delay(10000);
2576 ehci_dump_regs(sc);
2577 ehci_dump_sqh(sc->sc_async_head);
2578 ehci_dump_sqh(sqh);
2579 ehci_dump_sqtds(data);
2580 }
2581 #endif
2582
2583 if (sc->sc_bus.use_polling)
2584 ehci_waitintr(sc, xfer);
2585
2586 return (USBD_IN_PROGRESS);
2587 #undef exfer
2588 }
2589
2590 Static void
2591 ehci_device_bulk_abort(usbd_xfer_handle xfer)
2592 {
2593 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer));
2594 ehci_abort_xfer(xfer, USBD_CANCELLED);
2595 }
2596
2597 /*
2598 * Close a device bulk pipe.
2599 */
2600 Static void
2601 ehci_device_bulk_close(usbd_pipe_handle pipe)
2602 {
2603 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2604
2605 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe));
2606 ehci_close_pipe(pipe, sc->sc_async_head);
2607 }
2608
2609 void
2610 ehci_device_bulk_done(usbd_xfer_handle xfer)
2611 {
2612 struct ehci_xfer *ex = EXFER(xfer);
2613 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2614 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/
2615
2616 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n",
2617 xfer, xfer->actlen));
2618
2619 ehci_del_intr_list(ex); /* remove from active list */
2620
2621 ehci_free_std_chain(sc, ex->sqtdstart, 0);
2622
2623 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen));
2624 }
2625
2626 /************************/
2627
2628 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle xfer) { return USBD_IOERROR; }
2629 Static usbd_status ehci_device_intr_start(usbd_xfer_handle xfer) { return USBD_IOERROR; }
2630 Static void ehci_device_intr_abort(usbd_xfer_handle xfer) { }
2631 Static void ehci_device_intr_close(usbd_pipe_handle pipe) { }
2632 Static void ehci_device_intr_done(usbd_xfer_handle xfer) { }
2633
2634 /************************/
2635
2636 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle xfer) { return USBD_IOERROR; }
2637 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle xfer) { return USBD_IOERROR; }
2638 Static void ehci_device_isoc_abort(usbd_xfer_handle xfer) { }
2639 Static void ehci_device_isoc_close(usbd_pipe_handle pipe) { }
2640 Static void ehci_device_isoc_done(usbd_xfer_handle xfer) { }
2641