ehci.c revision 1.233
1 /* $NetBSD: ehci.c,v 1.233 2014/09/16 10:27:53 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.233 2014/09/16 10:27:53 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 #include <dev/usb/usbroothub_subr.h> 85 86 #include <dev/usb/ehcireg.h> 87 #include <dev/usb/ehcivar.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 } tail; 135 union { 136 /* Control pipe */ 137 struct { 138 usb_dma_t reqdma; 139 } ctl; 140 /* Interrupt pipe */ 141 struct { 142 u_int length; 143 } intr; 144 /* Bulk pipe */ 145 struct { 146 u_int length; 147 } bulk; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 } u; 154 }; 155 156 Static usbd_status ehci_open(usbd_pipe_handle); 157 Static void ehci_poll(struct usbd_bus *); 158 Static void ehci_softintr(void *); 159 Static int ehci_intr1(ehci_softc_t *); 160 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 161 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 162 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_idone(struct ehci_xfer *); 165 Static void ehci_timeout(void *); 166 Static void ehci_timeout_task(void *); 167 Static void ehci_intrlist_timeout(void *); 168 Static void ehci_doorbell(void *); 169 Static void ehci_pcd(void *); 170 171 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t); 172 Static void ehci_freem(struct usbd_bus *, usb_dma_t *); 173 174 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 175 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 176 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 177 178 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 179 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 180 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 181 Static void ehci_root_ctrl_close(usbd_pipe_handle); 182 Static void ehci_root_ctrl_done(usbd_xfer_handle); 183 184 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 185 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 186 Static void ehci_root_intr_abort(usbd_xfer_handle); 187 Static void ehci_root_intr_close(usbd_pipe_handle); 188 Static void ehci_root_intr_done(usbd_xfer_handle); 189 190 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 191 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 192 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 193 Static void ehci_device_ctrl_close(usbd_pipe_handle); 194 Static void ehci_device_ctrl_done(usbd_xfer_handle); 195 196 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 197 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 198 Static void ehci_device_bulk_abort(usbd_xfer_handle); 199 Static void ehci_device_bulk_close(usbd_pipe_handle); 200 Static void ehci_device_bulk_done(usbd_xfer_handle); 201 202 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 203 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 204 Static void ehci_device_intr_abort(usbd_xfer_handle); 205 Static void ehci_device_intr_close(usbd_pipe_handle); 206 Static void ehci_device_intr_done(usbd_xfer_handle); 207 208 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 209 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 210 Static void ehci_device_isoc_abort(usbd_xfer_handle); 211 Static void ehci_device_isoc_close(usbd_pipe_handle); 212 Static void ehci_device_isoc_done(usbd_xfer_handle); 213 214 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 215 Static void ehci_noop(usbd_pipe_handle pipe); 216 217 Static void ehci_disown(ehci_softc_t *, int, int); 218 219 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 220 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 221 222 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 223 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 224 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 225 ehci_softc_t *, int, int, usbd_xfer_handle, 226 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 227 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 228 ehci_soft_qtd_t *); 229 230 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 231 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 232 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 233 struct ehci_xfer *exfer); 234 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 235 usbd_status status); 236 237 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 238 239 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 240 int ival); 241 242 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 243 ehci_soft_qh_t *); 244 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 245 ehci_soft_qh_t *); 246 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 247 Static void ehci_sync_hc(ehci_softc_t *); 248 249 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 250 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 251 252 #ifdef EHCI_DEBUG 253 Static ehci_softc_t *theehci; 254 void ehci_dump(void); 255 #endif 256 257 #ifdef EHCI_DEBUG 258 Static void ehci_dump_regs(ehci_softc_t *); 259 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 260 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 261 Static void ehci_dump_qtd(ehci_qtd_t *); 262 Static void ehci_dump_sqh(ehci_soft_qh_t *); 263 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 264 Static void ehci_dump_itd(struct ehci_soft_itd *); 265 Static void ehci_dump_exfer(struct ehci_xfer *); 266 #endif 267 268 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 269 270 #define EHCI_INTR_ENDPT 1 271 272 #define ehci_add_intr_list(sc, ex) \ 273 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 274 #define ehci_del_intr_list(sc, ex) \ 275 do { \ 276 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 277 (ex)->inext.tqe_prev = NULL; \ 278 } while (0) 279 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 280 281 Static const struct usbd_bus_methods ehci_bus_methods = { 282 .open_pipe = ehci_open, 283 .soft_intr = ehci_softintr, 284 .do_poll = ehci_poll, 285 .allocm = ehci_allocm, 286 .freem = ehci_freem, 287 .allocx = ehci_allocx, 288 .freex = ehci_freex, 289 .get_lock = ehci_get_lock, 290 .new_device = NULL, 291 }; 292 293 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 294 .transfer = ehci_root_ctrl_transfer, 295 .start = ehci_root_ctrl_start, 296 .abort = ehci_root_ctrl_abort, 297 .close = ehci_root_ctrl_close, 298 .cleartoggle = ehci_noop, 299 .done = ehci_root_ctrl_done, 300 }; 301 302 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 303 .transfer = ehci_root_intr_transfer, 304 .start = ehci_root_intr_start, 305 .abort = ehci_root_intr_abort, 306 .close = ehci_root_intr_close, 307 .cleartoggle = ehci_noop, 308 .done = ehci_root_intr_done, 309 }; 310 311 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 312 .transfer = ehci_device_ctrl_transfer, 313 .start = ehci_device_ctrl_start, 314 .abort = ehci_device_ctrl_abort, 315 .close = ehci_device_ctrl_close, 316 .cleartoggle = ehci_noop, 317 .done = ehci_device_ctrl_done, 318 }; 319 320 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 321 .transfer = ehci_device_intr_transfer, 322 .start = ehci_device_intr_start, 323 .abort = ehci_device_intr_abort, 324 .close = ehci_device_intr_close, 325 .cleartoggle = ehci_device_clear_toggle, 326 .done = ehci_device_intr_done, 327 }; 328 329 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 330 .transfer = ehci_device_bulk_transfer, 331 .start = ehci_device_bulk_start, 332 .abort = ehci_device_bulk_abort, 333 .close = ehci_device_bulk_close, 334 .cleartoggle = ehci_device_clear_toggle, 335 .done = ehci_device_bulk_done, 336 }; 337 338 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 339 .transfer = ehci_device_isoc_transfer, 340 .start = ehci_device_isoc_start, 341 .abort = ehci_device_isoc_abort, 342 .close = ehci_device_isoc_close, 343 .cleartoggle = ehci_noop, 344 .done = ehci_device_isoc_done, 345 }; 346 347 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 348 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 349 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 350 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 351 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 352 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 353 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 354 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 355 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 356 }; 357 358 usbd_status 359 ehci_init(ehci_softc_t *sc) 360 { 361 u_int32_t vers, sparams, cparams, hcr; 362 u_int i; 363 usbd_status err; 364 ehci_soft_qh_t *sqh; 365 u_int ncomp; 366 367 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 368 #ifdef EHCI_DEBUG 369 theehci = sc; 370 #endif 371 372 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 373 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 374 cv_init(&sc->sc_softwake_cv, "ehciab"); 375 cv_init(&sc->sc_doorbell, "ehcidi"); 376 377 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 378 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 379 380 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 381 ehci_doorbell, sc); 382 KASSERT(sc->sc_doorbell_si != NULL); 383 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 384 ehci_pcd, sc); 385 KASSERT(sc->sc_pcd_si != NULL); 386 387 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 388 389 vers = EREAD2(sc, EHCI_HCIVERSION); 390 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 391 vers >> 8, vers & 0xff); 392 393 sparams = EREAD4(sc, EHCI_HCSPARAMS); 394 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 395 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 396 ncomp = EHCI_HCS_N_CC(sparams); 397 if (ncomp != sc->sc_ncomp) { 398 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 399 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 400 #if NOHCI == 0 || NUHCI == 0 401 aprint_error("%s: ohci or uhci probably not configured\n", 402 device_xname(sc->sc_dev)); 403 #endif 404 if (ncomp < sc->sc_ncomp) 405 sc->sc_ncomp = ncomp; 406 } 407 if (sc->sc_ncomp > 0) { 408 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 409 aprint_normal("%s: companion controller%s, %d port%s each:", 410 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 411 EHCI_HCS_N_PCC(sparams), 412 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 413 for (i = 0; i < sc->sc_ncomp; i++) 414 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 415 aprint_normal("\n"); 416 } 417 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 418 cparams = EREAD4(sc, EHCI_HCCPARAMS); 419 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 420 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 421 422 if (EHCI_HCC_64BIT(cparams)) { 423 /* MUST clear segment register if 64 bit capable. */ 424 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 425 } 426 427 sc->sc_bus.usbrev = USBREV_2_0; 428 429 usb_setup_reserve(sc->sc_dev, &sc->sc_dma_reserve, sc->sc_bus.dmatag, 430 USB_MEM_RESERVE); 431 432 /* Reset the controller */ 433 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 434 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 435 usb_delay_ms(&sc->sc_bus, 1); 436 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 437 for (i = 0; i < 100; i++) { 438 usb_delay_ms(&sc->sc_bus, 1); 439 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 440 if (!hcr) 441 break; 442 } 443 if (hcr) { 444 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 445 return (USBD_IOERROR); 446 } 447 if (sc->sc_vendor_init) 448 sc->sc_vendor_init(sc); 449 450 /* 451 * If we are doing embedded transaction translation function, force 452 * the controller to host mode. 453 */ 454 if (sc->sc_flags & EHCIF_ETTF) { 455 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 456 usbmode &= ~EHCI_USBMODE_CM; 457 usbmode |= EHCI_USBMODE_CM_HOST; 458 EWRITE4(sc, EHCI_USBMODE, usbmode); 459 } 460 461 /* XXX need proper intr scheduling */ 462 sc->sc_rand = 96; 463 464 /* frame list size at default, read back what we got and use that */ 465 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 466 case 0: sc->sc_flsize = 1024; break; 467 case 1: sc->sc_flsize = 512; break; 468 case 2: sc->sc_flsize = 256; break; 469 case 3: return (USBD_IOERROR); 470 } 471 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 472 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 473 if (err) 474 return (err); 475 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 476 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 477 478 for (i = 0; i < sc->sc_flsize; i++) { 479 sc->sc_flist[i] = EHCI_NULL; 480 } 481 482 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 483 484 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 485 KM_SLEEP); 486 if (sc->sc_softitds == NULL) 487 return ENOMEM; 488 LIST_INIT(&sc->sc_freeitds); 489 TAILQ_INIT(&sc->sc_intrhead); 490 491 /* Set up the bus struct. */ 492 sc->sc_bus.methods = &ehci_bus_methods; 493 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe); 494 495 sc->sc_eintrs = EHCI_NORMAL_INTRS; 496 497 /* 498 * Allocate the interrupt dummy QHs. These are arranged to give poll 499 * intervals that are powers of 2 times 1ms. 500 */ 501 for (i = 0; i < EHCI_INTRQHS; i++) { 502 sqh = ehci_alloc_sqh(sc); 503 if (sqh == NULL) { 504 err = USBD_NOMEM; 505 goto bad1; 506 } 507 sc->sc_islots[i].sqh = sqh; 508 } 509 for (i = 0; i < EHCI_INTRQHS; i++) { 510 sqh = sc->sc_islots[i].sqh; 511 if (i == 0) { 512 /* The last (1ms) QH terminates. */ 513 sqh->qh.qh_link = EHCI_NULL; 514 sqh->next = NULL; 515 } else { 516 /* Otherwise the next QH has half the poll interval */ 517 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 518 sqh->qh.qh_link = htole32(sqh->next->physaddr | 519 EHCI_LINK_QH); 520 } 521 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 522 sqh->qh.qh_curqtd = EHCI_NULL; 523 sqh->next = NULL; 524 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 525 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 526 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 527 sqh->sqtd = NULL; 528 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 529 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 530 } 531 /* Point the frame list at the last level (128ms). */ 532 for (i = 0; i < sc->sc_flsize; i++) { 533 int j; 534 535 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 536 revbits[i & (EHCI_MAX_POLLRATE-1)]; 537 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 538 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 539 i)].sqh->physaddr); 540 } 541 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 542 BUS_DMASYNC_PREWRITE); 543 544 /* Allocate dummy QH that starts the async list. */ 545 sqh = ehci_alloc_sqh(sc); 546 if (sqh == NULL) { 547 err = USBD_NOMEM; 548 goto bad1; 549 } 550 /* Fill the QH */ 551 sqh->qh.qh_endp = 552 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 553 sqh->qh.qh_link = 554 htole32(sqh->physaddr | EHCI_LINK_QH); 555 sqh->qh.qh_curqtd = EHCI_NULL; 556 sqh->next = NULL; 557 /* Fill the overlay qTD */ 558 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 559 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 560 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 561 sqh->sqtd = NULL; 562 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 563 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 564 #ifdef EHCI_DEBUG 565 ehci_dump_sqh(sqh); 566 #endif 567 568 /* Point to async list */ 569 sc->sc_async_head = sqh; 570 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 571 572 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 573 574 /* Turn on controller */ 575 EOWRITE4(sc, EHCI_USBCMD, 576 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 577 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 578 EHCI_CMD_ASE | 579 EHCI_CMD_PSE | 580 EHCI_CMD_RS); 581 582 /* Take over port ownership */ 583 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 584 585 for (i = 0; i < 100; i++) { 586 usb_delay_ms(&sc->sc_bus, 1); 587 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 588 if (!hcr) 589 break; 590 } 591 if (hcr) { 592 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 593 return (USBD_IOERROR); 594 } 595 596 /* Enable interrupts */ 597 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 598 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 599 600 return (USBD_NORMAL_COMPLETION); 601 602 #if 0 603 bad2: 604 ehci_free_sqh(sc, sc->sc_async_head); 605 #endif 606 bad1: 607 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 608 return (err); 609 } 610 611 int 612 ehci_intr(void *v) 613 { 614 ehci_softc_t *sc = v; 615 int ret = 0; 616 617 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 618 619 if (sc == NULL) 620 return 0; 621 622 mutex_spin_enter(&sc->sc_intr_lock); 623 624 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 625 goto done; 626 627 /* If we get an interrupt while polling, then just ignore it. */ 628 if (sc->sc_bus.use_polling) { 629 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 630 631 if (intrs) 632 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 633 #ifdef DIAGNOSTIC 634 USBHIST_LOGN(ehcidebug, 16, 635 "ignored interrupt while polling", 0, 0, 0, 0); 636 #endif 637 goto done; 638 } 639 640 ret = ehci_intr1(sc); 641 642 done: 643 mutex_spin_exit(&sc->sc_intr_lock); 644 return ret; 645 } 646 647 Static int 648 ehci_intr1(ehci_softc_t *sc) 649 { 650 u_int32_t intrs, eintrs; 651 652 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 653 654 /* In case the interrupt occurs before initialization has completed. */ 655 if (sc == NULL) { 656 #ifdef DIAGNOSTIC 657 printf("ehci_intr1: sc == NULL\n"); 658 #endif 659 return (0); 660 } 661 662 KASSERT(mutex_owned(&sc->sc_intr_lock)); 663 664 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 665 if (!intrs) 666 return (0); 667 668 eintrs = intrs & sc->sc_eintrs; 669 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 670 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 671 if (!eintrs) 672 return (0); 673 674 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 675 sc->sc_bus.no_intrs++; 676 if (eintrs & EHCI_STS_IAA) { 677 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 678 kpreempt_disable(); 679 KASSERT(sc->sc_doorbell_si != NULL); 680 softint_schedule(sc->sc_doorbell_si); 681 kpreempt_enable(); 682 eintrs &= ~EHCI_STS_IAA; 683 } 684 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 685 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 686 eintrs & EHCI_STS_INT ? 1 : 0, 687 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 688 usb_schedsoftintr(&sc->sc_bus); 689 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 690 } 691 if (eintrs & EHCI_STS_HSE) { 692 printf("%s: unrecoverable error, controller halted\n", 693 device_xname(sc->sc_dev)); 694 /* XXX what else */ 695 } 696 if (eintrs & EHCI_STS_PCD) { 697 kpreempt_disable(); 698 KASSERT(sc->sc_pcd_si != NULL); 699 softint_schedule(sc->sc_pcd_si); 700 kpreempt_enable(); 701 eintrs &= ~EHCI_STS_PCD; 702 } 703 704 if (eintrs != 0) { 705 /* Block unprocessed interrupts. */ 706 sc->sc_eintrs &= ~eintrs; 707 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 708 printf("%s: blocking intrs 0x%x\n", 709 device_xname(sc->sc_dev), eintrs); 710 } 711 712 return (1); 713 } 714 715 Static void 716 ehci_doorbell(void *addr) 717 { 718 ehci_softc_t *sc = addr; 719 720 mutex_enter(&sc->sc_lock); 721 cv_broadcast(&sc->sc_doorbell); 722 mutex_exit(&sc->sc_lock); 723 } 724 725 Static void 726 ehci_pcd(void *addr) 727 { 728 ehci_softc_t *sc = addr; 729 usbd_xfer_handle xfer; 730 u_char *p; 731 int i, m; 732 733 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 734 735 mutex_enter(&sc->sc_lock); 736 xfer = sc->sc_intrxfer; 737 738 if (xfer == NULL) { 739 /* Just ignore the change. */ 740 goto done; 741 } 742 743 p = KERNADDR(&xfer->dmabuf, 0); 744 m = min(sc->sc_noport, xfer->length * 8 - 1); 745 memset(p, 0, xfer->length); 746 for (i = 1; i <= m; i++) { 747 /* Pick out CHANGE bits from the status reg. */ 748 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 749 p[i/8] |= 1 << (i%8); 750 if (i % 8 == 7) 751 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 752 p[i/8], 0, 0); 753 } 754 xfer->actlen = xfer->length; 755 xfer->status = USBD_NORMAL_COMPLETION; 756 757 usb_transfer_complete(xfer); 758 759 done: 760 mutex_exit(&sc->sc_lock); 761 } 762 763 Static void 764 ehci_softintr(void *v) 765 { 766 struct usbd_bus *bus = v; 767 ehci_softc_t *sc = bus->hci_private; 768 struct ehci_xfer *ex, *nextex; 769 770 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 771 772 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 773 774 /* 775 * The only explanation I can think of for why EHCI is as brain dead 776 * as UHCI interrupt-wise is that Intel was involved in both. 777 * An interrupt just tells us that something is done, we have no 778 * clue what, so we need to scan through all active transfers. :-( 779 */ 780 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 781 nextex = TAILQ_NEXT(ex, inext); 782 ehci_check_intr(sc, ex); 783 } 784 785 /* Schedule a callout to catch any dropped transactions. */ 786 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 787 !TAILQ_EMPTY(&sc->sc_intrhead)) 788 callout_reset(&sc->sc_tmo_intrlist, 789 hz, ehci_intrlist_timeout, sc); 790 791 if (sc->sc_softwake) { 792 sc->sc_softwake = 0; 793 cv_broadcast(&sc->sc_softwake_cv); 794 } 795 } 796 797 /* Check for an interrupt. */ 798 Static void 799 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 800 { 801 int attr; 802 803 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 804 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 805 806 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 807 808 attr = ex->xfer.pipe->endpoint->edesc->bmAttributes; 809 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) 810 ehci_check_itd_intr(sc, ex); 811 else 812 ehci_check_qh_intr(sc, ex); 813 814 return; 815 } 816 817 Static void 818 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 819 { 820 ehci_soft_qtd_t *sqtd, *lsqtd; 821 __uint32_t status; 822 823 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 824 825 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 826 827 if (ex->sqtdstart == NULL) { 828 printf("ehci_check_qh_intr: not valid sqtd\n"); 829 return; 830 } 831 832 lsqtd = ex->sqtdend; 833 #ifdef DIAGNOSTIC 834 if (lsqtd == NULL) { 835 printf("ehci_check_qh_intr: lsqtd==0\n"); 836 return; 837 } 838 #endif 839 /* 840 * If the last TD is still active we need to check whether there 841 * is an error somewhere in the middle, or whether there was a 842 * short packet (SPD and not ACTIVE). 843 */ 844 usb_syncmem(&lsqtd->dma, 845 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 846 sizeof(lsqtd->qtd.qtd_status), 847 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 848 status = le32toh(lsqtd->qtd.qtd_status); 849 usb_syncmem(&lsqtd->dma, 850 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 851 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 852 if (status & EHCI_QTD_ACTIVE) { 853 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 854 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 855 usb_syncmem(&sqtd->dma, 856 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 857 sizeof(sqtd->qtd.qtd_status), 858 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 859 status = le32toh(sqtd->qtd.qtd_status); 860 usb_syncmem(&sqtd->dma, 861 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 862 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 863 /* If there's an active QTD the xfer isn't done. */ 864 if (status & EHCI_QTD_ACTIVE) 865 break; 866 /* Any kind of error makes the xfer done. */ 867 if (status & EHCI_QTD_HALTED) 868 goto done; 869 /* Handle short packets */ 870 if (EHCI_QTD_GET_BYTES(status) != 0) { 871 usbd_pipe_handle pipe = ex->xfer.pipe; 872 usb_endpoint_descriptor_t *ed = 873 pipe->endpoint->edesc; 874 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 875 876 /* 877 * If we get here for a control transfer then 878 * we need to let the hardware complete the 879 * status phase. That is, we're not done 880 * quite yet. 881 * 882 * Otherwise, we're done. 883 */ 884 if (xt == UE_CONTROL) { 885 break; 886 } 887 goto done; 888 } 889 } 890 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 891 ex, ex->sqtdstart, 0, 0); 892 return; 893 } 894 done: 895 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 896 callout_stop(&ex->xfer.timeout_handle); 897 ehci_idone(ex); 898 } 899 900 Static void 901 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 902 { 903 ehci_soft_itd_t *itd; 904 int i; 905 906 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 907 908 KASSERT(mutex_owned(&sc->sc_lock)); 909 910 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.pipe->queue)) 911 return; 912 913 if (ex->itdstart == NULL) { 914 printf("ehci_check_itd_intr: not valid itd\n"); 915 return; 916 } 917 918 itd = ex->itdend; 919 #ifdef DIAGNOSTIC 920 if (itd == NULL) { 921 printf("ehci_check_itd_intr: itdend == 0\n"); 922 return; 923 } 924 #endif 925 926 /* 927 * check no active transfers in last itd, meaning we're finished 928 */ 929 930 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 931 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 932 BUS_DMASYNC_POSTREAD); 933 934 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 935 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 936 break; 937 } 938 939 if (i == EHCI_ITD_NUFRAMES) { 940 goto done; /* All 8 descriptors inactive, it's done */ 941 } 942 943 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 944 ex->itdstart, 0, 0); 945 return; 946 done: 947 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 948 callout_stop(&ex->xfer.timeout_handle); 949 ehci_idone(ex); 950 } 951 952 Static void 953 ehci_idone(struct ehci_xfer *ex) 954 { 955 usbd_xfer_handle xfer = &ex->xfer; 956 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 957 struct ehci_softc *sc = xfer->pipe->device->bus->hci_private; 958 ehci_soft_qtd_t *sqtd, *lsqtd; 959 u_int32_t status = 0, nstatus = 0; 960 int actlen; 961 962 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 963 964 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 965 966 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 967 968 #ifdef DIAGNOSTIC 969 if (ex->isdone) { 970 printf("ehci_idone: ex=%p is done!\n", ex); 971 #ifdef EHCI_DEBUG 972 ehci_dump_exfer(ex); 973 #endif 974 return; 975 } 976 ex->isdone = 1; 977 #endif 978 979 if (xfer->status == USBD_CANCELLED || 980 xfer->status == USBD_TIMEOUT) { 981 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 982 return; 983 } 984 985 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 986 #ifdef EHCI_DEBUG 987 ehci_dump_sqtds(ex->sqtdstart); 988 #endif 989 990 /* The transfer is done, compute actual length and status. */ 991 992 if (UE_GET_XFERTYPE(xfer->pipe->endpoint->edesc->bmAttributes) 993 == UE_ISOCHRONOUS) { 994 /* Isoc transfer */ 995 struct ehci_soft_itd *itd; 996 int i, nframes, len, uframes; 997 998 nframes = 0; 999 actlen = 0; 1000 1001 i = xfer->pipe->endpoint->edesc->bInterval; 1002 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1003 1004 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1005 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1006 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1007 BUS_DMASYNC_POSTREAD); 1008 1009 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1010 /* XXX - driver didn't fill in the frame full 1011 * of uframes. This leads to scheduling 1012 * inefficiencies, but working around 1013 * this doubles complexity of tracking 1014 * an xfer. 1015 */ 1016 if (nframes >= xfer->nframes) 1017 break; 1018 1019 status = le32toh(itd->itd.itd_ctl[i]); 1020 len = EHCI_ITD_GET_LEN(status); 1021 if (EHCI_ITD_GET_STATUS(status) != 0) 1022 len = 0; /*No valid data on error*/ 1023 1024 xfer->frlengths[nframes++] = len; 1025 actlen += len; 1026 } 1027 1028 if (nframes >= xfer->nframes) 1029 break; 1030 } 1031 1032 xfer->actlen = actlen; 1033 xfer->status = USBD_NORMAL_COMPLETION; 1034 goto end; 1035 } 1036 1037 /* Continue processing xfers using queue heads */ 1038 1039 lsqtd = ex->sqtdend; 1040 actlen = 0; 1041 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1042 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1043 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1044 nstatus = le32toh(sqtd->qtd.qtd_status); 1045 if (nstatus & EHCI_QTD_ACTIVE) 1046 break; 1047 1048 status = nstatus; 1049 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1050 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1051 } 1052 1053 1054 /* 1055 * If there are left over TDs we need to update the toggle. 1056 * The default pipe doesn't need it since control transfers 1057 * start the toggle at 0 every time. 1058 * For a short transfer we need to update the toggle for the missing 1059 * packets within the qTD. 1060 */ 1061 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1062 xfer->pipe->device->default_pipe != xfer->pipe) { 1063 USBHIST_LOG(ehcidebug, 1064 "toggle update status=0x%08x nstatus=0x%08x", 1065 status, nstatus, 0, 0); 1066 #if 0 1067 ehci_dump_sqh(epipe->sqh); 1068 ehci_dump_sqtds(ex->sqtdstart); 1069 #endif 1070 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1071 } 1072 1073 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->length, 1074 actlen, status, 0); 1075 xfer->actlen = actlen; 1076 if (status & EHCI_QTD_HALTED) { 1077 #ifdef EHCI_DEBUG 1078 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1079 xfer->pipe->device->address, 1080 xfer->pipe->endpoint->edesc->bEndpointAddress, 0, 0); 1081 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d stat=%#x", 1082 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1083 status, 0); 1084 USBHIST_LOG(ehcidebug, 1085 "active =%d halted=%d buferr=%d babble=%d", 1086 status & EHCI_QTD_ACTIVE ? 1 : 0, 1087 status & EHCI_QTD_HALTED ? 1 : 0, 1088 status & EHCI_QTD_BUFERR ? 1 : 0, 1089 status & EHCI_QTD_BABBLE ? 1 : 0); 1090 1091 USBHIST_LOG(ehcidebug, 1092 "xacterr=%d missed=%d split =%d ping =%d", 1093 status & EHCI_QTD_XACTERR ? 1 : 0, 1094 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1095 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1096 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1097 1098 ehci_dump_sqh(epipe->sqh); 1099 ehci_dump_sqtds(ex->sqtdstart); 1100 #endif 1101 /* low&full speed has an extra error flag */ 1102 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1103 EHCI_QH_SPEED_HIGH) 1104 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1105 else 1106 status &= EHCI_QTD_STATERRS; 1107 if (status == 0) /* no other errors means a stall */ { 1108 xfer->status = USBD_STALLED; 1109 } else { 1110 xfer->status = USBD_IOERROR; /* more info XXX */ 1111 } 1112 /* XXX need to reset TT on missed microframe */ 1113 if (status & EHCI_QTD_MISSEDMICRO) { 1114 printf("%s: missed microframe, TT reset not " 1115 "implemented, hub might be inoperational\n", 1116 device_xname(sc->sc_dev)); 1117 } 1118 } else { 1119 xfer->status = USBD_NORMAL_COMPLETION; 1120 } 1121 1122 end: 1123 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1124 * during this call, before methods->done is called: dma sync required 1125 * beforehand? */ 1126 usb_transfer_complete(xfer); 1127 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1128 } 1129 1130 /* 1131 * Wait here until controller claims to have an interrupt. 1132 * Then call ehci_intr and return. Use timeout to avoid waiting 1133 * too long. 1134 */ 1135 Static void 1136 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1137 { 1138 int timo; 1139 u_int32_t intrs; 1140 1141 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1142 1143 xfer->status = USBD_IN_PROGRESS; 1144 for (timo = xfer->timeout; timo >= 0; timo--) { 1145 usb_delay_ms(&sc->sc_bus, 1); 1146 if (sc->sc_dying) 1147 break; 1148 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1149 sc->sc_eintrs; 1150 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1151 #ifdef EHCI_DEBUG 1152 if (ehcidebug > 15) 1153 ehci_dump_regs(sc); 1154 #endif 1155 if (intrs) { 1156 mutex_spin_enter(&sc->sc_intr_lock); 1157 ehci_intr1(sc); 1158 mutex_spin_exit(&sc->sc_intr_lock); 1159 if (xfer->status != USBD_IN_PROGRESS) 1160 return; 1161 } 1162 } 1163 1164 /* Timeout */ 1165 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1166 xfer->status = USBD_TIMEOUT; 1167 mutex_enter(&sc->sc_lock); 1168 usb_transfer_complete(xfer); 1169 mutex_exit(&sc->sc_lock); 1170 /* XXX should free TD */ 1171 } 1172 1173 Static void 1174 ehci_poll(struct usbd_bus *bus) 1175 { 1176 ehci_softc_t *sc = bus->hci_private; 1177 1178 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1179 1180 #ifdef EHCI_DEBUG 1181 static int last; 1182 int new; 1183 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1184 if (new != last) { 1185 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1186 last = new; 1187 } 1188 #endif 1189 1190 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1191 mutex_spin_enter(&sc->sc_intr_lock); 1192 ehci_intr1(sc); 1193 mutex_spin_exit(&sc->sc_intr_lock); 1194 } 1195 } 1196 1197 void 1198 ehci_childdet(device_t self, device_t child) 1199 { 1200 struct ehci_softc *sc = device_private(self); 1201 1202 KASSERT(sc->sc_child == child); 1203 sc->sc_child = NULL; 1204 } 1205 1206 int 1207 ehci_detach(struct ehci_softc *sc, int flags) 1208 { 1209 int rv = 0; 1210 1211 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1212 1213 if (sc->sc_child != NULL) 1214 rv = config_detach(sc->sc_child, flags); 1215 1216 if (rv != 0) 1217 return (rv); 1218 1219 callout_halt(&sc->sc_tmo_intrlist, NULL); 1220 callout_destroy(&sc->sc_tmo_intrlist); 1221 1222 /* XXX free other data structures XXX */ 1223 if (sc->sc_softitds) 1224 kmem_free(sc->sc_softitds, 1225 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1226 cv_destroy(&sc->sc_doorbell); 1227 cv_destroy(&sc->sc_softwake_cv); 1228 1229 #if 0 1230 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1231 1232 softint_disestablish(sc->sc_doorbell_si); 1233 softint_disestablish(sc->sc_pcd_si); 1234 1235 mutex_destroy(&sc->sc_lock); 1236 mutex_destroy(&sc->sc_intr_lock); 1237 #endif 1238 1239 pool_cache_destroy(sc->sc_xferpool); 1240 1241 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1242 1243 return (rv); 1244 } 1245 1246 1247 int 1248 ehci_activate(device_t self, enum devact act) 1249 { 1250 struct ehci_softc *sc = device_private(self); 1251 1252 switch (act) { 1253 case DVACT_DEACTIVATE: 1254 sc->sc_dying = 1; 1255 return 0; 1256 default: 1257 return EOPNOTSUPP; 1258 } 1259 } 1260 1261 /* 1262 * Handle suspend/resume. 1263 * 1264 * We need to switch to polling mode here, because this routine is 1265 * called from an interrupt context. This is all right since we 1266 * are almost suspended anyway. 1267 * 1268 * Note that this power handler isn't to be registered directly; the 1269 * bus glue needs to call out to it. 1270 */ 1271 bool 1272 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1273 { 1274 ehci_softc_t *sc = device_private(dv); 1275 int i; 1276 uint32_t cmd, hcr; 1277 1278 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1279 1280 mutex_spin_enter(&sc->sc_intr_lock); 1281 sc->sc_bus.use_polling++; 1282 mutex_spin_exit(&sc->sc_intr_lock); 1283 1284 for (i = 1; i <= sc->sc_noport; i++) { 1285 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1286 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1287 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1288 } 1289 1290 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1291 1292 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1293 EOWRITE4(sc, EHCI_USBCMD, cmd); 1294 1295 for (i = 0; i < 100; i++) { 1296 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1297 if (hcr == 0) 1298 break; 1299 1300 usb_delay_ms(&sc->sc_bus, 1); 1301 } 1302 if (hcr != 0) 1303 printf("%s: reset timeout\n", device_xname(dv)); 1304 1305 cmd &= ~EHCI_CMD_RS; 1306 EOWRITE4(sc, EHCI_USBCMD, cmd); 1307 1308 for (i = 0; i < 100; i++) { 1309 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1310 if (hcr == EHCI_STS_HCH) 1311 break; 1312 1313 usb_delay_ms(&sc->sc_bus, 1); 1314 } 1315 if (hcr != EHCI_STS_HCH) 1316 printf("%s: config timeout\n", device_xname(dv)); 1317 1318 mutex_spin_enter(&sc->sc_intr_lock); 1319 sc->sc_bus.use_polling--; 1320 mutex_spin_exit(&sc->sc_intr_lock); 1321 1322 return true; 1323 } 1324 1325 bool 1326 ehci_resume(device_t dv, const pmf_qual_t *qual) 1327 { 1328 ehci_softc_t *sc = device_private(dv); 1329 int i; 1330 uint32_t cmd, hcr; 1331 1332 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1333 1334 /* restore things in case the bios sucks */ 1335 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1336 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1337 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1338 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1339 1340 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1341 1342 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1343 1344 hcr = 0; 1345 for (i = 1; i <= sc->sc_noport; i++) { 1346 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1347 if ((cmd & EHCI_PS_PO) == 0 && 1348 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1349 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1350 hcr = 1; 1351 } 1352 } 1353 1354 if (hcr) { 1355 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1356 1357 for (i = 1; i <= sc->sc_noport; i++) { 1358 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1359 if ((cmd & EHCI_PS_PO) == 0 && 1360 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1361 EOWRITE4(sc, EHCI_PORTSC(i), 1362 cmd & ~EHCI_PS_FPR); 1363 } 1364 } 1365 1366 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1367 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1368 1369 for (i = 0; i < 100; i++) { 1370 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1371 if (hcr != EHCI_STS_HCH) 1372 break; 1373 1374 usb_delay_ms(&sc->sc_bus, 1); 1375 } 1376 if (hcr == EHCI_STS_HCH) 1377 printf("%s: config timeout\n", device_xname(dv)); 1378 1379 return true; 1380 } 1381 1382 /* 1383 * Shut down the controller when the system is going down. 1384 */ 1385 bool 1386 ehci_shutdown(device_t self, int flags) 1387 { 1388 ehci_softc_t *sc = device_private(self); 1389 1390 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1391 1392 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1393 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1394 return true; 1395 } 1396 1397 Static usbd_status 1398 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size) 1399 { 1400 struct ehci_softc *sc = bus->hci_private; 1401 usbd_status err; 1402 1403 err = usb_allocmem_flags(&sc->sc_bus, size, 0, dma, USBMALLOC_MULTISEG); 1404 #ifdef EHCI_DEBUG 1405 if (err) 1406 printf("ehci_allocm: usb_allocmem_flags()= %s (%d)\n", 1407 usbd_errstr(err), err); 1408 #endif 1409 if (err == USBD_NOMEM) 1410 err = usb_reserve_allocm(&sc->sc_dma_reserve, dma, size); 1411 #ifdef EHCI_DEBUG 1412 if (err) 1413 printf("ehci_allocm: usb_reserve_allocm()= %s (%d)\n", 1414 usbd_errstr(err), err); 1415 #endif 1416 return (err); 1417 } 1418 1419 Static void 1420 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma) 1421 { 1422 struct ehci_softc *sc = bus->hci_private; 1423 1424 if (dma->block->flags & USB_DMA_RESERVE) { 1425 usb_reserve_freem(&sc->sc_dma_reserve, 1426 dma); 1427 return; 1428 } 1429 usb_freemem(&sc->sc_bus, dma); 1430 } 1431 1432 Static usbd_xfer_handle 1433 ehci_allocx(struct usbd_bus *bus) 1434 { 1435 struct ehci_softc *sc = bus->hci_private; 1436 usbd_xfer_handle xfer; 1437 1438 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1439 if (xfer != NULL) { 1440 memset(xfer, 0, sizeof(struct ehci_xfer)); 1441 #ifdef DIAGNOSTIC 1442 EXFER(xfer)->isdone = 1; 1443 xfer->busy_free = XFER_BUSY; 1444 #endif 1445 } 1446 return (xfer); 1447 } 1448 1449 Static void 1450 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1451 { 1452 struct ehci_softc *sc = bus->hci_private; 1453 1454 #ifdef DIAGNOSTIC 1455 if (xfer->busy_free != XFER_BUSY) { 1456 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1457 xfer->busy_free); 1458 } 1459 xfer->busy_free = XFER_FREE; 1460 if (!EXFER(xfer)->isdone) { 1461 printf("ehci_freex: !isdone\n"); 1462 } 1463 #endif 1464 pool_cache_put(sc->sc_xferpool, xfer); 1465 } 1466 1467 Static void 1468 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1469 { 1470 struct ehci_softc *sc = bus->hci_private; 1471 1472 *lock = &sc->sc_lock; 1473 } 1474 1475 Static void 1476 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1477 { 1478 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1479 1480 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1481 1482 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1483 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1484 #ifdef EHCI_DEBUG 1485 if (ehcidebug) 1486 usbd_dump_pipe(pipe); 1487 #endif 1488 epipe->nexttoggle = 0; 1489 } 1490 1491 Static void 1492 ehci_noop(usbd_pipe_handle pipe) 1493 { 1494 } 1495 1496 #ifdef EHCI_DEBUG 1497 /* 1498 * Unused function - this is meant to be called from a kernel 1499 * debugger. 1500 */ 1501 void 1502 ehci_dump(void) 1503 { 1504 ehci_softc_t *sc = theehci; 1505 int i; 1506 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1507 EOREAD4(sc, EHCI_USBCMD), 1508 EOREAD4(sc, EHCI_USBSTS), 1509 EOREAD4(sc, EHCI_USBINTR)); 1510 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1511 EOREAD4(sc, EHCI_FRINDEX), 1512 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1513 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1514 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1515 for (i = 1; i <= sc->sc_noport; i++) 1516 printf("port %d status=0x%08x\n", i, 1517 EOREAD4(sc, EHCI_PORTSC(i))); 1518 } 1519 1520 Static void 1521 ehci_dump_regs(ehci_softc_t *sc) 1522 { 1523 int i; 1524 1525 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1526 1527 USBHIST_LOG(ehcidebug, 1528 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1529 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1530 EOREAD4(sc, EHCI_USBINTR), 0); 1531 USBHIST_LOG(ehcidebug, 1532 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1533 "async = 0x%08x", 1534 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1535 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1536 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1537 for (i = 1; i <= sc->sc_noport; i += 2) { 1538 if (i == sc->sc_noport) { 1539 USBHIST_LOG(ehcidebug, 1540 "port %d status = 0x%08x", i, 1541 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1542 } else { 1543 USBHIST_LOG(ehcidebug, 1544 "port %d status = 0x%08x port %d status = 0x%08x", 1545 i, EOREAD4(sc, EHCI_PORTSC(i)), 1546 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1547 } 1548 } 1549 } 1550 1551 #ifdef EHCI_DEBUG 1552 #define ehci_dump_link(link, type) do { \ 1553 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1554 link, \ 1555 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1556 if (type) { \ 1557 USBHIST_LOG(ehcidebug, \ 1558 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1559 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1560 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1561 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1562 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1563 } \ 1564 } while(0) 1565 #else 1566 #define ehci_dump_link(link, type) 1567 #endif 1568 1569 Static void 1570 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1571 { 1572 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1573 int i; 1574 uint32_t stop = 0; 1575 1576 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1577 ehci_dump_sqtd(sqtd); 1578 usb_syncmem(&sqtd->dma, 1579 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1580 sizeof(sqtd->qtd), 1581 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1582 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1583 usb_syncmem(&sqtd->dma, 1584 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1585 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1586 } 1587 if (sqtd) 1588 USBHIST_LOG(ehcidebug, 1589 "dump aborted, too many TDs", 0, 0, 0, 0); 1590 } 1591 1592 Static void 1593 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1594 { 1595 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1596 1597 usb_syncmem(&sqtd->dma, sqtd->offs, 1598 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1599 1600 USBHIST_LOGN(ehcidebug, 10, 1601 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1602 ehci_dump_qtd(&sqtd->qtd); 1603 1604 usb_syncmem(&sqtd->dma, sqtd->offs, 1605 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1606 } 1607 1608 Static void 1609 ehci_dump_qtd(ehci_qtd_t *qtd) 1610 { 1611 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1612 1613 #ifdef USBHIST 1614 uint32_t s = le32toh(qtd->qtd_status); 1615 #endif 1616 1617 USBHIST_LOGN(ehcidebug, 10, 1618 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1619 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1620 USBHIST_LOGN(ehcidebug, 10, 1621 " toggle = %d ioc = %d bytes = %#x " 1622 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1623 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1624 USBHIST_LOGN(ehcidebug, 10, 1625 " cerr = %d pid = %d stat = %x", 1626 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1627 0); 1628 USBHIST_LOGN(ehcidebug, 10, 1629 "active =%d halted=%d buferr=%d babble=%d", 1630 s & EHCI_QTD_ACTIVE ? 1 : 0, 1631 s & EHCI_QTD_HALTED ? 1 : 0, 1632 s & EHCI_QTD_BUFERR ? 1 : 0, 1633 s & EHCI_QTD_BABBLE ? 1 : 0); 1634 USBHIST_LOGN(ehcidebug, 10, 1635 "xacterr=%d missed=%d split =%d ping =%d", 1636 s & EHCI_QTD_XACTERR ? 1 : 0, 1637 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1638 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1639 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1640 USBHIST_LOGN(ehcidebug, 10, 1641 "buffer[0] = %#x buffer[1] = %#x " 1642 "buffer[2] = %#x buffer[3] = %#x", 1643 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1644 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1645 USBHIST_LOGN(ehcidebug, 10, 1646 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1647 } 1648 1649 Static void 1650 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1651 { 1652 #ifdef USBHIST 1653 ehci_qh_t *qh = &sqh->qh; 1654 ehci_link_t link; 1655 #endif 1656 u_int32_t endp, endphub; 1657 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1658 1659 usb_syncmem(&sqh->dma, sqh->offs, 1660 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1661 1662 USBHIST_LOGN(ehcidebug, 10, 1663 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1664 link = le32toh(qh->qh_link); 1665 ehci_dump_link(link, true); 1666 1667 endp = le32toh(qh->qh_endp); 1668 USBHIST_LOGN(ehcidebug, 10, 1669 " endp = %#x", endp, 0, 0, 0); 1670 USBHIST_LOGN(ehcidebug, 10, 1671 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1672 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1673 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1674 USBHIST_LOGN(ehcidebug, 10, 1675 " dtc = %d hrecl = %d", 1676 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1677 USBHIST_LOGN(ehcidebug, 10, 1678 " ctl = %d nrl = %d mpl = %#x(%d)", 1679 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1680 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1681 1682 endphub = le32toh(qh->qh_endphub); 1683 USBHIST_LOGN(ehcidebug, 10, 1684 " endphub = %#x", endphub, 0, 0, 0); 1685 USBHIST_LOGN(ehcidebug, 10, 1686 " smask = 0x%02x cmask = 0x%02x", 1687 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1688 USBHIST_LOGN(ehcidebug, 10, 1689 " huba = 0x%02x port = %d mult = %d", 1690 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1691 EHCI_QH_GET_MULT(endphub), 0); 1692 1693 link = le32toh(qh->qh_curqtd); 1694 ehci_dump_link(link, false); 1695 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1696 ehci_dump_qtd(&qh->qh_qtd); 1697 1698 usb_syncmem(&sqh->dma, sqh->offs, 1699 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1700 } 1701 1702 Static void 1703 ehci_dump_itd(struct ehci_soft_itd *itd) 1704 { 1705 ehci_isoc_trans_t t; 1706 ehci_isoc_bufr_ptr_t b, b2, b3; 1707 int i; 1708 1709 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1710 1711 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1712 0, 0); 1713 1714 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1715 t = le32toh(itd->itd.itd_ctl[i]); 1716 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1717 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1718 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1719 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1720 EHCI_ITD_GET_OFFS(t), 0); 1721 } 1722 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1723 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1724 USBHIST_LOG(ehcidebug, " %x", 1725 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1726 1727 b = le32toh(itd->itd.itd_bufr[0]); 1728 b2 = le32toh(itd->itd.itd_bufr[1]); 1729 b3 = le32toh(itd->itd.itd_bufr[2]); 1730 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1731 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1732 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1733 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1734 } 1735 1736 Static void 1737 ehci_dump_sitd(struct ehci_soft_itd *itd) 1738 { 1739 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1740 1741 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1742 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1743 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1744 itd->xfer_next, itd->physaddr, itd->slot, 0); 1745 } 1746 1747 Static void 1748 ehci_dump_exfer(struct ehci_xfer *ex) 1749 { 1750 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1751 1752 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1753 ex, ex->sqtdstart, ex->sqtdend, 0); 1754 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1755 ex->itdstart, ex->itdend, ex->isdone, 0); 1756 } 1757 #endif 1758 1759 Static usbd_status 1760 ehci_open(usbd_pipe_handle pipe) 1761 { 1762 usbd_device_handle dev = pipe->device; 1763 ehci_softc_t *sc = dev->bus->hci_private; 1764 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc; 1765 u_int8_t addr = dev->address; 1766 u_int8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1767 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1768 ehci_soft_qh_t *sqh; 1769 usbd_status err; 1770 int ival, speed, naks; 1771 int hshubaddr, hshubport; 1772 1773 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1774 1775 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1776 pipe, addr, ed->bEndpointAddress, sc->sc_addr); 1777 1778 if (dev->myhsport) { 1779 /* 1780 * When directly attached FS/LS device while doing embedded 1781 * transaction translations and we are the hub, set the hub 1782 * address to 0 (us). 1783 */ 1784 if (!(sc->sc_flags & EHCIF_ETTF) 1785 || (dev->myhsport->parent->address != sc->sc_addr)) { 1786 hshubaddr = dev->myhsport->parent->address; 1787 } else { 1788 hshubaddr = 0; 1789 } 1790 hshubport = dev->myhsport->portno; 1791 } else { 1792 hshubaddr = 0; 1793 hshubport = 0; 1794 } 1795 1796 if (sc->sc_dying) 1797 return (USBD_IOERROR); 1798 1799 /* toggle state needed for bulk endpoints */ 1800 epipe->nexttoggle = pipe->endpoint->datatoggle; 1801 1802 if (addr == sc->sc_addr) { 1803 switch (ed->bEndpointAddress) { 1804 case USB_CONTROL_ENDPOINT: 1805 pipe->methods = &ehci_root_ctrl_methods; 1806 break; 1807 case UE_DIR_IN | EHCI_INTR_ENDPT: 1808 pipe->methods = &ehci_root_intr_methods; 1809 break; 1810 default: 1811 USBHIST_LOG(ehcidebug, 1812 "bad bEndpointAddress 0x%02x", 1813 ed->bEndpointAddress, 0, 0, 0); 1814 return (USBD_INVAL); 1815 } 1816 return (USBD_NORMAL_COMPLETION); 1817 } 1818 1819 /* XXX All this stuff is only valid for async. */ 1820 switch (dev->speed) { 1821 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1822 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1823 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1824 default: panic("ehci_open: bad device speed %d", dev->speed); 1825 } 1826 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) { 1827 aprint_error_dev(sc->sc_dev, "error opening low/full speed " 1828 "isoc endpoint.\n"); 1829 aprint_normal_dev(sc->sc_dev, "a low/full speed device is " 1830 "attached to a USB2 hub, and transaction translations are " 1831 "not yet supported.\n"); 1832 aprint_normal_dev(sc->sc_dev, "reattach the device to the " 1833 "root hub instead.\n"); 1834 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1835 hshubaddr, hshubport, 0, 0); 1836 return USBD_INVAL; 1837 } 1838 1839 /* 1840 * For interrupt transfer, nak throttling must be disabled, but for 1841 * the other transfer type, nak throttling should be enabled from the 1842 * viewpoint that avoids the memory thrashing. 1843 */ 1844 naks = (xfertype == UE_INTERRUPT) ? 0 1845 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1846 1847 /* Allocate sqh for everything, save isoc xfers */ 1848 if (xfertype != UE_ISOCHRONOUS) { 1849 sqh = ehci_alloc_sqh(sc); 1850 if (sqh == NULL) 1851 return (USBD_NOMEM); 1852 /* qh_link filled when the QH is added */ 1853 sqh->qh.qh_endp = htole32( 1854 EHCI_QH_SET_ADDR(addr) | 1855 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1856 EHCI_QH_SET_EPS(speed) | 1857 EHCI_QH_DTC | 1858 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1859 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1860 EHCI_QH_CTL : 0) | 1861 EHCI_QH_SET_NRL(naks) 1862 ); 1863 sqh->qh.qh_endphub = htole32( 1864 EHCI_QH_SET_MULT(1) | 1865 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1866 ); 1867 if (speed != EHCI_QH_SPEED_HIGH) 1868 sqh->qh.qh_endphub |= htole32( 1869 EHCI_QH_SET_PORT(hshubport) | 1870 EHCI_QH_SET_HUBA(hshubaddr) | 1871 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1872 ); 1873 sqh->qh.qh_curqtd = EHCI_NULL; 1874 /* Fill the overlay qTD */ 1875 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1876 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1877 sqh->qh.qh_qtd.qtd_status = htole32(0); 1878 1879 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1880 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1881 epipe->sqh = sqh; 1882 } else { 1883 sqh = NULL; 1884 } /*xfertype == UE_ISOC*/ 1885 1886 switch (xfertype) { 1887 case UE_CONTROL: 1888 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1889 0, &epipe->u.ctl.reqdma); 1890 #ifdef EHCI_DEBUG 1891 if (err) 1892 printf("ehci_open: usb_allocmem()=%d\n", err); 1893 #endif 1894 if (err) 1895 goto bad; 1896 pipe->methods = &ehci_device_ctrl_methods; 1897 mutex_enter(&sc->sc_lock); 1898 ehci_add_qh(sc, sqh, sc->sc_async_head); 1899 mutex_exit(&sc->sc_lock); 1900 break; 1901 case UE_BULK: 1902 pipe->methods = &ehci_device_bulk_methods; 1903 mutex_enter(&sc->sc_lock); 1904 ehci_add_qh(sc, sqh, sc->sc_async_head); 1905 mutex_exit(&sc->sc_lock); 1906 break; 1907 case UE_INTERRUPT: 1908 pipe->methods = &ehci_device_intr_methods; 1909 ival = pipe->interval; 1910 if (ival == USBD_DEFAULT_INTERVAL) { 1911 if (speed == EHCI_QH_SPEED_HIGH) { 1912 if (ed->bInterval > 16) { 1913 /* 1914 * illegal with high-speed, but there 1915 * were documentation bugs in the spec, 1916 * so be generous 1917 */ 1918 ival = 256; 1919 } else 1920 ival = (1 << (ed->bInterval - 1)) / 8; 1921 } else 1922 ival = ed->bInterval; 1923 } 1924 err = ehci_device_setintr(sc, sqh, ival); 1925 if (err) 1926 goto bad; 1927 break; 1928 case UE_ISOCHRONOUS: 1929 pipe->methods = &ehci_device_isoc_methods; 1930 if (ed->bInterval == 0 || ed->bInterval > 16) { 1931 printf("ehci: opening pipe with invalid bInterval\n"); 1932 err = USBD_INVAL; 1933 goto bad; 1934 } 1935 if (UGETW(ed->wMaxPacketSize) == 0) { 1936 printf("ehci: zero length endpoint open request\n"); 1937 err = USBD_INVAL; 1938 goto bad; 1939 } 1940 epipe->u.isoc.next_frame = 0; 1941 epipe->u.isoc.cur_xfers = 0; 1942 break; 1943 default: 1944 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 1945 err = USBD_INVAL; 1946 goto bad; 1947 } 1948 return (USBD_NORMAL_COMPLETION); 1949 1950 bad: 1951 if (sqh != NULL) 1952 ehci_free_sqh(sc, sqh); 1953 return (err); 1954 } 1955 1956 /* 1957 * Add an ED to the schedule. Called with USB lock held. 1958 */ 1959 Static void 1960 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1961 { 1962 1963 KASSERT(mutex_owned(&sc->sc_lock)); 1964 1965 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1966 1967 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1968 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 1969 1970 sqh->next = head->next; 1971 sqh->qh.qh_link = head->qh.qh_link; 1972 1973 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 1974 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 1975 1976 head->next = sqh; 1977 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 1978 1979 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 1980 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 1981 1982 #ifdef EHCI_DEBUG 1983 ehci_dump_sqh(sqh); 1984 #endif 1985 } 1986 1987 /* 1988 * Remove an ED from the schedule. Called with USB lock held. 1989 */ 1990 Static void 1991 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 1992 { 1993 ehci_soft_qh_t *p; 1994 1995 KASSERT(mutex_owned(&sc->sc_lock)); 1996 1997 /* XXX */ 1998 for (p = head; p != NULL && p->next != sqh; p = p->next) 1999 ; 2000 if (p == NULL) 2001 panic("ehci_rem_qh: ED not found"); 2002 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2003 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2004 p->next = sqh->next; 2005 p->qh.qh_link = sqh->qh.qh_link; 2006 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2007 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2008 2009 ehci_sync_hc(sc); 2010 } 2011 2012 Static void 2013 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2014 { 2015 int i; 2016 u_int32_t status; 2017 2018 /* Save toggle bit and ping status. */ 2019 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2020 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2021 status = sqh->qh.qh_qtd.qtd_status & 2022 htole32(EHCI_QTD_TOGGLE_MASK | 2023 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2024 /* Set HALTED to make hw leave it alone. */ 2025 sqh->qh.qh_qtd.qtd_status = 2026 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2027 usb_syncmem(&sqh->dma, 2028 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2029 sizeof(sqh->qh.qh_qtd.qtd_status), 2030 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2031 sqh->qh.qh_curqtd = 0; 2032 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2033 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2034 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2035 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2036 sqh->sqtd = sqtd; 2037 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2038 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2039 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2040 sqh->qh.qh_qtd.qtd_status = status; 2041 usb_syncmem(&sqh->dma, 2042 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2043 sizeof(sqh->qh.qh_qtd.qtd_status), 2044 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2045 } 2046 2047 /* 2048 * Ensure that the HC has released all references to the QH. We do this 2049 * by asking for a Async Advance Doorbell interrupt and then we wait for 2050 * the interrupt. 2051 * To make this easier we first obtain exclusive use of the doorbell. 2052 */ 2053 Static void 2054 ehci_sync_hc(ehci_softc_t *sc) 2055 { 2056 int error __diagused; 2057 2058 KASSERT(mutex_owned(&sc->sc_lock)); 2059 2060 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2061 2062 if (sc->sc_dying) { 2063 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2064 return; 2065 } 2066 /* ask for doorbell */ 2067 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2068 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2069 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2070 2071 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2072 2073 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2074 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2075 #ifdef DIAGNOSTIC 2076 if (error) 2077 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2078 #endif 2079 } 2080 2081 Static void 2082 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2083 { 2084 struct ehci_soft_itd *itd, *prev; 2085 2086 prev = NULL; 2087 2088 if (exfer->itdstart == NULL || exfer->itdend == NULL) 2089 panic("ehci isoc xfer being freed, but with no itd chain\n"); 2090 2091 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2092 prev = itd->u.frame_list.prev; 2093 /* Unlink itd from hardware chain, or frame array */ 2094 if (prev == NULL) { /* We're at the table head */ 2095 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2096 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2097 usb_syncmem(&sc->sc_fldma, 2098 sizeof(ehci_link_t) * itd->slot, 2099 sizeof(ehci_link_t), 2100 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2101 2102 if (itd->u.frame_list.next != NULL) 2103 itd->u.frame_list.next->u.frame_list.prev = NULL; 2104 } else { 2105 /* XXX this part is untested... */ 2106 prev->itd.itd_next = itd->itd.itd_next; 2107 usb_syncmem(&itd->dma, 2108 itd->offs + offsetof(ehci_itd_t, itd_next), 2109 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2110 2111 prev->u.frame_list.next = itd->u.frame_list.next; 2112 if (itd->u.frame_list.next != NULL) 2113 itd->u.frame_list.next->u.frame_list.prev = prev; 2114 } 2115 } 2116 2117 prev = NULL; 2118 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2119 if (prev != NULL) 2120 ehci_free_itd(sc, prev); 2121 prev = itd; 2122 } 2123 if (prev) 2124 ehci_free_itd(sc, prev); 2125 exfer->itdstart = NULL; 2126 exfer->itdend = NULL; 2127 } 2128 2129 /***********/ 2130 2131 /* 2132 * Data structures and routines to emulate the root hub. 2133 */ 2134 Static usb_device_descriptor_t ehci_devd = { 2135 USB_DEVICE_DESCRIPTOR_SIZE, 2136 UDESC_DEVICE, /* type */ 2137 {0x00, 0x02}, /* USB version */ 2138 UDCLASS_HUB, /* class */ 2139 UDSUBCLASS_HUB, /* subclass */ 2140 UDPROTO_HSHUBSTT, /* protocol */ 2141 64, /* max packet */ 2142 {0},{0},{0x00,0x01}, /* device id */ 2143 1,2,0, /* string indicies */ 2144 1 /* # of configurations */ 2145 }; 2146 2147 Static const usb_device_qualifier_t ehci_odevd = { 2148 USB_DEVICE_DESCRIPTOR_SIZE, 2149 UDESC_DEVICE_QUALIFIER, /* type */ 2150 {0x00, 0x02}, /* USB version */ 2151 UDCLASS_HUB, /* class */ 2152 UDSUBCLASS_HUB, /* subclass */ 2153 UDPROTO_FSHUB, /* protocol */ 2154 64, /* max packet */ 2155 1, /* # of configurations */ 2156 0 2157 }; 2158 2159 Static const usb_config_descriptor_t ehci_confd = { 2160 USB_CONFIG_DESCRIPTOR_SIZE, 2161 UDESC_CONFIG, 2162 {USB_CONFIG_DESCRIPTOR_SIZE + 2163 USB_INTERFACE_DESCRIPTOR_SIZE + 2164 USB_ENDPOINT_DESCRIPTOR_SIZE}, 2165 1, 2166 1, 2167 0, 2168 UC_ATTR_MBO | UC_SELF_POWERED, 2169 0 /* max power */ 2170 }; 2171 2172 Static const usb_interface_descriptor_t ehci_ifcd = { 2173 USB_INTERFACE_DESCRIPTOR_SIZE, 2174 UDESC_INTERFACE, 2175 0, 2176 0, 2177 1, 2178 UICLASS_HUB, 2179 UISUBCLASS_HUB, 2180 UIPROTO_HSHUBSTT, 2181 0 2182 }; 2183 2184 Static const usb_endpoint_descriptor_t ehci_endpd = { 2185 USB_ENDPOINT_DESCRIPTOR_SIZE, 2186 UDESC_ENDPOINT, 2187 UE_DIR_IN | EHCI_INTR_ENDPT, 2188 UE_INTERRUPT, 2189 {8, 0}, /* max packet */ 2190 12 2191 }; 2192 2193 Static const usb_hub_descriptor_t ehci_hubd = { 2194 USB_HUB_DESCRIPTOR_SIZE, 2195 UDESC_HUB, 2196 0, 2197 {0,0}, 2198 0, 2199 0, 2200 {""}, 2201 {""}, 2202 }; 2203 2204 /* 2205 * Simulate a hardware hub by handling all the necessary requests. 2206 */ 2207 Static usbd_status 2208 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2209 { 2210 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2211 usbd_status err; 2212 2213 /* Insert last in queue. */ 2214 mutex_enter(&sc->sc_lock); 2215 err = usb_insert_transfer(xfer); 2216 mutex_exit(&sc->sc_lock); 2217 if (err) 2218 return (err); 2219 2220 /* Pipe isn't running, start first */ 2221 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2222 } 2223 2224 Static usbd_status 2225 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2226 { 2227 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2228 usb_device_request_t *req; 2229 void *buf = NULL; 2230 int port, i; 2231 int len, value, index, l, totlen = 0; 2232 usb_port_status_t ps; 2233 usb_hub_descriptor_t hubd; 2234 usbd_status err; 2235 u_int32_t v; 2236 2237 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2238 2239 if (sc->sc_dying) 2240 return (USBD_IOERROR); 2241 2242 #ifdef DIAGNOSTIC 2243 if (!(xfer->rqflags & URQ_REQUEST)) 2244 /* XXX panic */ 2245 return (USBD_INVAL); 2246 #endif 2247 req = &xfer->request; 2248 2249 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2250 req->bmRequestType, req->bRequest, 0, 0); 2251 2252 len = UGETW(req->wLength); 2253 value = UGETW(req->wValue); 2254 index = UGETW(req->wIndex); 2255 2256 if (len != 0) 2257 buf = KERNADDR(&xfer->dmabuf, 0); 2258 2259 #define C(x,y) ((x) | ((y) << 8)) 2260 switch(C(req->bRequest, req->bmRequestType)) { 2261 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2262 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2263 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2264 /* 2265 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2266 * for the integrated root hub. 2267 */ 2268 break; 2269 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2270 if (len > 0) { 2271 *(u_int8_t *)buf = sc->sc_conf; 2272 totlen = 1; 2273 } 2274 break; 2275 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2276 USBHIST_LOG(ehcidebug, "wValue=0x%04x", value, 0, 0, 0); 2277 if (len == 0) 2278 break; 2279 switch(value >> 8) { 2280 case UDESC_DEVICE: 2281 if ((value & 0xff) != 0) { 2282 err = USBD_IOERROR; 2283 goto ret; 2284 } 2285 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2286 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2287 memcpy(buf, &ehci_devd, l); 2288 break; 2289 /* 2290 * We can't really operate at another speed, but the spec says 2291 * we need this descriptor. 2292 */ 2293 case UDESC_DEVICE_QUALIFIER: 2294 if ((value & 0xff) != 0) { 2295 err = USBD_IOERROR; 2296 goto ret; 2297 } 2298 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2299 memcpy(buf, &ehci_odevd, l); 2300 break; 2301 /* 2302 * We can't really operate at another speed, but the spec says 2303 * we need this descriptor. 2304 */ 2305 case UDESC_OTHER_SPEED_CONFIGURATION: 2306 case UDESC_CONFIG: 2307 if ((value & 0xff) != 0) { 2308 err = USBD_IOERROR; 2309 goto ret; 2310 } 2311 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2312 memcpy(buf, &ehci_confd, l); 2313 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2314 value >> 8; 2315 buf = (char *)buf + l; 2316 len -= l; 2317 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2318 totlen += l; 2319 memcpy(buf, &ehci_ifcd, l); 2320 buf = (char *)buf + l; 2321 len -= l; 2322 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2323 totlen += l; 2324 memcpy(buf, &ehci_endpd, l); 2325 break; 2326 case UDESC_STRING: 2327 #define sd ((usb_string_descriptor_t *)buf) 2328 switch (value & 0xff) { 2329 case 0: /* Language table */ 2330 totlen = usb_makelangtbl(sd, len); 2331 break; 2332 case 1: /* Vendor */ 2333 totlen = usb_makestrdesc(sd, len, 2334 sc->sc_vendor); 2335 break; 2336 case 2: /* Product */ 2337 totlen = usb_makestrdesc(sd, len, 2338 "EHCI root hub"); 2339 break; 2340 } 2341 #undef sd 2342 break; 2343 default: 2344 err = USBD_IOERROR; 2345 goto ret; 2346 } 2347 break; 2348 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2349 if (len > 0) { 2350 *(u_int8_t *)buf = 0; 2351 totlen = 1; 2352 } 2353 break; 2354 case C(UR_GET_STATUS, UT_READ_DEVICE): 2355 if (len > 1) { 2356 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2357 totlen = 2; 2358 } 2359 break; 2360 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2361 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2362 if (len > 1) { 2363 USETW(((usb_status_t *)buf)->wStatus, 0); 2364 totlen = 2; 2365 } 2366 break; 2367 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2368 if (value >= USB_MAX_DEVICES) { 2369 err = USBD_IOERROR; 2370 goto ret; 2371 } 2372 sc->sc_addr = value; 2373 break; 2374 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2375 if (value != 0 && value != 1) { 2376 err = USBD_IOERROR; 2377 goto ret; 2378 } 2379 sc->sc_conf = value; 2380 break; 2381 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2382 break; 2383 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2384 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2385 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2386 err = USBD_IOERROR; 2387 goto ret; 2388 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2389 break; 2390 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2391 break; 2392 /* Hub requests */ 2393 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2394 break; 2395 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2396 USBHIST_LOG(ehcidebug, 2397 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2398 0, 0); 2399 if (index < 1 || index > sc->sc_noport) { 2400 err = USBD_IOERROR; 2401 goto ret; 2402 } 2403 port = EHCI_PORTSC(index); 2404 v = EOREAD4(sc, port); 2405 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2406 v &= ~EHCI_PS_CLEAR; 2407 switch(value) { 2408 case UHF_PORT_ENABLE: 2409 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2410 break; 2411 case UHF_PORT_SUSPEND: 2412 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2413 break; 2414 v &= ~EHCI_PS_SUSP; 2415 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2416 /* see USB2 spec ch. 7.1.7.7 */ 2417 usb_delay_ms(&sc->sc_bus, 20); 2418 EOWRITE4(sc, port, v); 2419 usb_delay_ms(&sc->sc_bus, 2); 2420 #ifdef DEBUG 2421 v = EOREAD4(sc, port); 2422 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2423 printf("ehci: resume failed: %x\n", v); 2424 #endif 2425 break; 2426 case UHF_PORT_POWER: 2427 if (sc->sc_hasppc) 2428 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2429 break; 2430 case UHF_PORT_TEST: 2431 USBHIST_LOG(ehcidebug, "clear port test " 2432 "%d", index, 0, 0, 0); 2433 break; 2434 case UHF_PORT_INDICATOR: 2435 USBHIST_LOG(ehcidebug, "clear port ind " 2436 "%d", index, 0, 0, 0); 2437 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2438 break; 2439 case UHF_C_PORT_CONNECTION: 2440 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2441 break; 2442 case UHF_C_PORT_ENABLE: 2443 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2444 break; 2445 case UHF_C_PORT_SUSPEND: 2446 /* how? */ 2447 break; 2448 case UHF_C_PORT_OVER_CURRENT: 2449 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2450 break; 2451 case UHF_C_PORT_RESET: 2452 sc->sc_isreset[index] = 0; 2453 break; 2454 default: 2455 err = USBD_IOERROR; 2456 goto ret; 2457 } 2458 #if 0 2459 switch(value) { 2460 case UHF_C_PORT_CONNECTION: 2461 case UHF_C_PORT_ENABLE: 2462 case UHF_C_PORT_SUSPEND: 2463 case UHF_C_PORT_OVER_CURRENT: 2464 case UHF_C_PORT_RESET: 2465 default: 2466 break; 2467 } 2468 #endif 2469 break; 2470 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2471 if (len == 0) 2472 break; 2473 if ((value & 0xff) != 0) { 2474 err = USBD_IOERROR; 2475 goto ret; 2476 } 2477 hubd = ehci_hubd; 2478 hubd.bNbrPorts = sc->sc_noport; 2479 v = EOREAD4(sc, EHCI_HCSPARAMS); 2480 USETW(hubd.wHubCharacteristics, 2481 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2482 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2483 ? UHD_PORT_IND : 0); 2484 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2485 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2486 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2487 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2488 l = min(len, hubd.bDescLength); 2489 totlen = l; 2490 memcpy(buf, &hubd, l); 2491 break; 2492 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2493 if (len != 4) { 2494 err = USBD_IOERROR; 2495 goto ret; 2496 } 2497 memset(buf, 0, len); /* ? XXX */ 2498 totlen = len; 2499 break; 2500 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2501 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2502 if (index < 1 || index > sc->sc_noport) { 2503 err = USBD_IOERROR; 2504 goto ret; 2505 } 2506 if (len != 4) { 2507 err = USBD_IOERROR; 2508 goto ret; 2509 } 2510 v = EOREAD4(sc, EHCI_PORTSC(index)); 2511 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2512 2513 i = UPS_HIGH_SPEED; 2514 if (sc->sc_flags & EHCIF_ETTF) { 2515 /* 2516 * If we are doing embedded transaction translation, 2517 * then directly attached LS/FS devices are reset by 2518 * the EHCI controller itself. PSPD is encoded 2519 * the same way as in USBSTATUS. 2520 */ 2521 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2522 } 2523 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2524 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2525 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2526 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2527 if (v & EHCI_PS_PR) i |= UPS_RESET; 2528 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2529 if (sc->sc_vendor_port_status) 2530 i = sc->sc_vendor_port_status(sc, v, i); 2531 USETW(ps.wPortStatus, i); 2532 i = 0; 2533 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2534 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2535 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2536 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2537 USETW(ps.wPortChange, i); 2538 l = min(len, sizeof ps); 2539 memcpy(buf, &ps, l); 2540 totlen = l; 2541 break; 2542 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2543 err = USBD_IOERROR; 2544 goto ret; 2545 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2546 break; 2547 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2548 if (index < 1 || index > sc->sc_noport) { 2549 err = USBD_IOERROR; 2550 goto ret; 2551 } 2552 port = EHCI_PORTSC(index); 2553 v = EOREAD4(sc, port); 2554 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2555 v &= ~EHCI_PS_CLEAR; 2556 switch(value) { 2557 case UHF_PORT_ENABLE: 2558 EOWRITE4(sc, port, v | EHCI_PS_PE); 2559 break; 2560 case UHF_PORT_SUSPEND: 2561 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2562 break; 2563 case UHF_PORT_RESET: 2564 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2565 if (EHCI_PS_IS_LOWSPEED(v) 2566 && sc->sc_ncomp > 0 2567 && !(sc->sc_flags & EHCIF_ETTF)) { 2568 /* 2569 * Low speed device on non-ETTF controller or 2570 * unaccompanied controller, give up ownership. 2571 */ 2572 ehci_disown(sc, index, 1); 2573 break; 2574 } 2575 /* Start reset sequence. */ 2576 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2577 EOWRITE4(sc, port, v | EHCI_PS_PR); 2578 /* Wait for reset to complete. */ 2579 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2580 if (sc->sc_dying) { 2581 err = USBD_IOERROR; 2582 goto ret; 2583 } 2584 /* 2585 * An embedded transaction translator will automatically 2586 * terminate the reset sequence so there's no need to 2587 * it. 2588 */ 2589 v = EOREAD4(sc, port); 2590 if (v & EHCI_PS_PR) { 2591 /* Terminate reset sequence. */ 2592 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2593 /* Wait for HC to complete reset. */ 2594 usb_delay_ms(&sc->sc_bus, 2595 EHCI_PORT_RESET_COMPLETE); 2596 if (sc->sc_dying) { 2597 err = USBD_IOERROR; 2598 goto ret; 2599 } 2600 } 2601 2602 v = EOREAD4(sc, port); 2603 USBHIST_LOG(ehcidebug, 2604 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2605 if (v & EHCI_PS_PR) { 2606 printf("%s: port reset timeout\n", 2607 device_xname(sc->sc_dev)); 2608 return (USBD_TIMEOUT); 2609 } 2610 if (!(v & EHCI_PS_PE)) { 2611 /* Not a high speed device, give up ownership.*/ 2612 ehci_disown(sc, index, 0); 2613 break; 2614 } 2615 sc->sc_isreset[index] = 1; 2616 USBHIST_LOG(ehcidebug, 2617 "ehci port %d reset, status = 0x%08x", index, v, 0, 2618 0); 2619 break; 2620 case UHF_PORT_POWER: 2621 USBHIST_LOG(ehcidebug, 2622 "set port power %d (has PPC = %d)", index, 2623 sc->sc_hasppc, 0, 0); 2624 if (sc->sc_hasppc) 2625 EOWRITE4(sc, port, v | EHCI_PS_PP); 2626 break; 2627 case UHF_PORT_TEST: 2628 USBHIST_LOG(ehcidebug, "set port test %d", 2629 index, 0, 0, 0); 2630 break; 2631 case UHF_PORT_INDICATOR: 2632 USBHIST_LOG(ehcidebug, "set port ind %d", 2633 index, 0, 0, 0); 2634 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2635 break; 2636 default: 2637 err = USBD_IOERROR; 2638 goto ret; 2639 } 2640 break; 2641 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2642 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2643 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2644 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2645 break; 2646 default: 2647 err = USBD_IOERROR; 2648 goto ret; 2649 } 2650 xfer->actlen = totlen; 2651 err = USBD_NORMAL_COMPLETION; 2652 ret: 2653 mutex_enter(&sc->sc_lock); 2654 xfer->status = err; 2655 usb_transfer_complete(xfer); 2656 mutex_exit(&sc->sc_lock); 2657 return (USBD_IN_PROGRESS); 2658 } 2659 2660 Static void 2661 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2662 { 2663 int port; 2664 u_int32_t v; 2665 2666 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2667 2668 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2669 #ifdef DIAGNOSTIC 2670 if (sc->sc_npcomp != 0) { 2671 int i = (index-1) / sc->sc_npcomp; 2672 if (i >= sc->sc_ncomp) 2673 printf("%s: strange port\n", 2674 device_xname(sc->sc_dev)); 2675 else 2676 printf("%s: handing over %s speed device on " 2677 "port %d to %s\n", 2678 device_xname(sc->sc_dev), 2679 lowspeed ? "low" : "full", 2680 index, device_xname(sc->sc_comps[i])); 2681 } else { 2682 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2683 } 2684 #endif 2685 port = EHCI_PORTSC(index); 2686 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2687 EOWRITE4(sc, port, v | EHCI_PS_PO); 2688 } 2689 2690 /* Abort a root control request. */ 2691 Static void 2692 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2693 { 2694 /* Nothing to do, all transfers are synchronous. */ 2695 } 2696 2697 /* Close the root pipe. */ 2698 Static void 2699 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2700 { 2701 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2702 /* Nothing to do. */ 2703 } 2704 2705 Static void 2706 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2707 { 2708 xfer->hcpriv = NULL; 2709 } 2710 2711 Static usbd_status 2712 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2713 { 2714 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2715 usbd_status err; 2716 2717 /* Insert last in queue. */ 2718 mutex_enter(&sc->sc_lock); 2719 err = usb_insert_transfer(xfer); 2720 mutex_exit(&sc->sc_lock); 2721 if (err) 2722 return (err); 2723 2724 /* Pipe isn't running, start first */ 2725 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 2726 } 2727 2728 Static usbd_status 2729 ehci_root_intr_start(usbd_xfer_handle xfer) 2730 { 2731 usbd_pipe_handle pipe = xfer->pipe; 2732 ehci_softc_t *sc = pipe->device->bus->hci_private; 2733 2734 if (sc->sc_dying) 2735 return (USBD_IOERROR); 2736 2737 mutex_enter(&sc->sc_lock); 2738 sc->sc_intrxfer = xfer; 2739 mutex_exit(&sc->sc_lock); 2740 2741 return (USBD_IN_PROGRESS); 2742 } 2743 2744 /* Abort a root interrupt request. */ 2745 Static void 2746 ehci_root_intr_abort(usbd_xfer_handle xfer) 2747 { 2748 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 2749 2750 KASSERT(mutex_owned(&sc->sc_lock)); 2751 KASSERT(xfer->pipe->intrxfer == xfer); 2752 2753 sc->sc_intrxfer = NULL; 2754 2755 xfer->status = USBD_CANCELLED; 2756 usb_transfer_complete(xfer); 2757 } 2758 2759 /* Close the root pipe. */ 2760 Static void 2761 ehci_root_intr_close(usbd_pipe_handle pipe) 2762 { 2763 ehci_softc_t *sc = pipe->device->bus->hci_private; 2764 2765 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2766 2767 KASSERT(mutex_owned(&sc->sc_lock)); 2768 2769 sc->sc_intrxfer = NULL; 2770 } 2771 2772 Static void 2773 ehci_root_intr_done(usbd_xfer_handle xfer) 2774 { 2775 xfer->hcpriv = NULL; 2776 } 2777 2778 /************************/ 2779 2780 Static ehci_soft_qh_t * 2781 ehci_alloc_sqh(ehci_softc_t *sc) 2782 { 2783 ehci_soft_qh_t *sqh; 2784 usbd_status err; 2785 int i, offs; 2786 usb_dma_t dma; 2787 2788 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2789 2790 if (sc->sc_freeqhs == NULL) { 2791 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2792 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2793 EHCI_PAGE_SIZE, &dma); 2794 #ifdef EHCI_DEBUG 2795 if (err) 2796 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2797 #endif 2798 if (err) 2799 return (NULL); 2800 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2801 offs = i * EHCI_SQH_SIZE; 2802 sqh = KERNADDR(&dma, offs); 2803 sqh->physaddr = DMAADDR(&dma, offs); 2804 sqh->dma = dma; 2805 sqh->offs = offs; 2806 sqh->next = sc->sc_freeqhs; 2807 sc->sc_freeqhs = sqh; 2808 } 2809 } 2810 sqh = sc->sc_freeqhs; 2811 sc->sc_freeqhs = sqh->next; 2812 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2813 sqh->next = NULL; 2814 return (sqh); 2815 } 2816 2817 Static void 2818 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2819 { 2820 sqh->next = sc->sc_freeqhs; 2821 sc->sc_freeqhs = sqh; 2822 } 2823 2824 Static ehci_soft_qtd_t * 2825 ehci_alloc_sqtd(ehci_softc_t *sc) 2826 { 2827 ehci_soft_qtd_t *sqtd = NULL; 2828 usbd_status err; 2829 int i, offs; 2830 usb_dma_t dma; 2831 2832 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2833 2834 if (sc->sc_freeqtds == NULL) { 2835 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2836 2837 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2838 EHCI_PAGE_SIZE, &dma); 2839 #ifdef EHCI_DEBUG 2840 if (err) 2841 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2842 #endif 2843 if (err) 2844 goto done; 2845 2846 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2847 offs = i * EHCI_SQTD_SIZE; 2848 sqtd = KERNADDR(&dma, offs); 2849 sqtd->physaddr = DMAADDR(&dma, offs); 2850 sqtd->dma = dma; 2851 sqtd->offs = offs; 2852 2853 sqtd->nextqtd = sc->sc_freeqtds; 2854 sc->sc_freeqtds = sqtd; 2855 } 2856 } 2857 2858 sqtd = sc->sc_freeqtds; 2859 sc->sc_freeqtds = sqtd->nextqtd; 2860 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2861 sqtd->nextqtd = NULL; 2862 sqtd->xfer = NULL; 2863 2864 done: 2865 return (sqtd); 2866 } 2867 2868 Static void 2869 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2870 { 2871 2872 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 2873 2874 sqtd->nextqtd = sc->sc_freeqtds; 2875 sc->sc_freeqtds = sqtd; 2876 } 2877 2878 Static usbd_status 2879 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2880 int alen, int rd, usbd_xfer_handle xfer, 2881 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2882 { 2883 ehci_soft_qtd_t *next, *cur; 2884 ehci_physaddr_t nextphys; 2885 u_int32_t qtdstatus; 2886 int len, curlen, mps; 2887 int i, tog; 2888 int pages, pageoffs; 2889 bus_size_t curoffs; 2890 vaddr_t va, va_offs; 2891 usb_dma_t *dma = &xfer->dmabuf; 2892 u_int16_t flags = xfer->flags; 2893 paddr_t a; 2894 2895 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2896 2897 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2898 2899 len = alen; 2900 qtdstatus = EHCI_QTD_ACTIVE | 2901 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2902 EHCI_QTD_SET_CERR(3) 2903 /* IOC set below */ 2904 /* BYTES set below */ 2905 ; 2906 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 2907 tog = epipe->nexttoggle; 2908 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2909 2910 cur = ehci_alloc_sqtd(sc); 2911 *sp = cur; 2912 if (cur == NULL) 2913 goto nomem; 2914 2915 usb_syncmem(dma, 0, alen, 2916 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2917 curoffs = 0; 2918 for (;;) { 2919 /* The EHCI hardware can handle at most 5 pages. */ 2920 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2921 va_offs = EHCI_PAGE_OFFSET(va_offs); 2922 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 2923 /* we can handle it in this QTD */ 2924 curlen = len - curoffs; 2925 } else { 2926 /* must use multiple TDs, fill as much as possible. */ 2927 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 2928 2929 /* the length must be a multiple of the max size */ 2930 curlen -= curlen % mps; 2931 USBHIST_LOG(ehcidebug, "multiple QTDs, " 2932 "curlen=%d", curlen, 0, 0, 0); 2933 #ifdef DIAGNOSTIC 2934 if (curlen == 0) 2935 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2936 #endif 2937 } 2938 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 2939 len, curlen, (size_t)curoffs, 0); 2940 2941 /* 2942 * Allocate another transfer if there's more data left, 2943 * or if force last short transfer flag is set and we're 2944 * allocating a multiple of the max packet size. 2945 */ 2946 2947 if (curoffs + curlen != len || 2948 ((curlen % mps) == 0 && !rd && curlen != 0 && 2949 (flags & USBD_FORCE_SHORT_XFER))) { 2950 next = ehci_alloc_sqtd(sc); 2951 if (next == NULL) 2952 goto nomem; 2953 nextphys = htole32(next->physaddr); 2954 } else { 2955 next = NULL; 2956 nextphys = EHCI_NULL; 2957 } 2958 2959 /* Find number of pages we'll be using, insert dma addresses */ 2960 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2961 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2962 pageoffs = EHCI_PAGE(curoffs); 2963 for (i = 0; i < pages; i++) { 2964 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2965 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2966 /* Cast up to avoid compiler warnings */ 2967 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2968 } 2969 2970 /* First buffer pointer requires a page offset to start at */ 2971 va = (vaddr_t)KERNADDR(dma, curoffs); 2972 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2973 2974 cur->nextqtd = next; 2975 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2976 cur->qtd.qtd_status = 2977 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2978 cur->xfer = xfer; 2979 cur->len = curlen; 2980 2981 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2982 (size_t)curoffs, (size_t)(curoffs + curlen), 0, 0); 2983 2984 /* adjust the toggle based on the number of packets in this 2985 qtd */ 2986 if (((curlen + mps - 1) / mps) & 1) { 2987 tog ^= 1; 2988 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2989 } 2990 if (next == NULL) 2991 break; 2992 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2993 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2994 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2995 if (len) 2996 curoffs += curlen; 2997 cur = next; 2998 } 2999 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3000 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 3001 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3002 *ep = cur; 3003 epipe->nexttoggle = tog; 3004 3005 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 3006 *sp, *ep, 0, 0); 3007 3008 return (USBD_NORMAL_COMPLETION); 3009 3010 nomem: 3011 /* XXX free chain */ 3012 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3013 return (USBD_NOMEM); 3014 } 3015 3016 Static void 3017 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 3018 ehci_soft_qtd_t *sqtdend) 3019 { 3020 ehci_soft_qtd_t *p; 3021 int i; 3022 3023 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3024 3025 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 3026 sqtd, sqtdend, 0, 0); 3027 3028 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 3029 p = sqtd->nextqtd; 3030 ehci_free_sqtd(sc, sqtd); 3031 } 3032 } 3033 3034 Static ehci_soft_itd_t * 3035 ehci_alloc_itd(ehci_softc_t *sc) 3036 { 3037 struct ehci_soft_itd *itd, *freeitd; 3038 usbd_status err; 3039 int i, offs, frindex, previndex; 3040 usb_dma_t dma; 3041 3042 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3043 3044 mutex_enter(&sc->sc_lock); 3045 3046 /* Find an itd that wasn't freed this frame or last frame. This can 3047 * discard itds that were freed before frindex wrapped around 3048 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3049 * interrupt and fiddling with list when that happens */ 3050 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3051 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3052 3053 freeitd = NULL; 3054 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 3055 if (itd == NULL) 3056 break; 3057 if (itd->slot != frindex && itd->slot != previndex) { 3058 freeitd = itd; 3059 break; 3060 } 3061 } 3062 3063 if (freeitd == NULL) { 3064 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3065 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3066 EHCI_PAGE_SIZE, &dma); 3067 3068 if (err) { 3069 USBHIST_LOG(ehcidebug, 3070 "alloc returned %d", err, 0, 0, 0); 3071 mutex_exit(&sc->sc_lock); 3072 return NULL; 3073 } 3074 3075 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 3076 offs = i * EHCI_ITD_SIZE; 3077 itd = KERNADDR(&dma, offs); 3078 itd->physaddr = DMAADDR(&dma, offs); 3079 itd->dma = dma; 3080 itd->offs = offs; 3081 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3082 } 3083 freeitd = LIST_FIRST(&sc->sc_freeitds); 3084 } 3085 3086 itd = freeitd; 3087 LIST_REMOVE(itd, u.free_list); 3088 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3089 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 3090 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE | 3091 BUS_DMASYNC_PREREAD); 3092 3093 itd->u.frame_list.next = NULL; 3094 itd->u.frame_list.prev = NULL; 3095 itd->xfer_next = NULL; 3096 itd->slot = 0; 3097 3098 mutex_exit(&sc->sc_lock); 3099 3100 return itd; 3101 } 3102 3103 Static void 3104 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3105 { 3106 3107 KASSERT(mutex_owned(&sc->sc_lock)); 3108 3109 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3110 } 3111 3112 /****************/ 3113 3114 /* 3115 * Close a reqular pipe. 3116 * Assumes that there are no pending transactions. 3117 */ 3118 Static void 3119 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3120 { 3121 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3122 ehci_softc_t *sc = pipe->device->bus->hci_private; 3123 ehci_soft_qh_t *sqh = epipe->sqh; 3124 3125 KASSERT(mutex_owned(&sc->sc_lock)); 3126 3127 ehci_rem_qh(sc, sqh, head); 3128 ehci_free_sqh(sc, epipe->sqh); 3129 } 3130 3131 /* 3132 * Abort a device request. 3133 * If this routine is called at splusb() it guarantees that the request 3134 * will be removed from the hardware scheduling and that the callback 3135 * for it will be called with USBD_CANCELLED status. 3136 * It's impossible to guarantee that the requested transfer will not 3137 * have happened since the hardware runs concurrently. 3138 * If the transaction has already happened we rely on the ordinary 3139 * interrupt processing to process it. 3140 * XXX This is most probably wrong. 3141 * XXXMRG this doesn't make sense anymore. 3142 */ 3143 Static void 3144 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3145 { 3146 #define exfer EXFER(xfer) 3147 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3148 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3149 ehci_soft_qh_t *sqh = epipe->sqh; 3150 ehci_soft_qtd_t *sqtd; 3151 ehci_physaddr_t cur; 3152 u_int32_t qhstatus; 3153 int hit; 3154 int wake; 3155 3156 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3157 3158 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3159 3160 KASSERT(mutex_owned(&sc->sc_lock)); 3161 3162 if (sc->sc_dying) { 3163 /* If we're dying, just do the software part. */ 3164 xfer->status = status; /* make software ignore it */ 3165 callout_stop(&xfer->timeout_handle); 3166 usb_transfer_complete(xfer); 3167 return; 3168 } 3169 3170 if (cpu_intr_p() || cpu_softintr_p()) 3171 panic("ehci_abort_xfer: not in process context"); 3172 3173 /* 3174 * If an abort is already in progress then just wait for it to 3175 * complete and return. 3176 */ 3177 if (xfer->hcflags & UXFER_ABORTING) { 3178 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3179 #ifdef DIAGNOSTIC 3180 if (status == USBD_TIMEOUT) 3181 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3182 #endif 3183 /* Override the status which might be USBD_TIMEOUT. */ 3184 xfer->status = status; 3185 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3186 0, 0, 0, 0); 3187 xfer->hcflags |= UXFER_ABORTWAIT; 3188 while (xfer->hcflags & UXFER_ABORTING) 3189 cv_wait(&xfer->hccv, &sc->sc_lock); 3190 return; 3191 } 3192 xfer->hcflags |= UXFER_ABORTING; 3193 3194 /* 3195 * Step 1: Make interrupt routine and hardware ignore xfer. 3196 */ 3197 xfer->status = status; /* make software ignore it */ 3198 callout_stop(&xfer->timeout_handle); 3199 3200 usb_syncmem(&sqh->dma, 3201 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3202 sizeof(sqh->qh.qh_qtd.qtd_status), 3203 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3204 qhstatus = sqh->qh.qh_qtd.qtd_status; 3205 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3206 usb_syncmem(&sqh->dma, 3207 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3208 sizeof(sqh->qh.qh_qtd.qtd_status), 3209 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3210 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3211 usb_syncmem(&sqtd->dma, 3212 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3213 sizeof(sqtd->qtd.qtd_status), 3214 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3215 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3216 usb_syncmem(&sqtd->dma, 3217 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3218 sizeof(sqtd->qtd.qtd_status), 3219 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3220 if (sqtd == exfer->sqtdend) 3221 break; 3222 } 3223 3224 /* 3225 * Step 2: Wait until we know hardware has finished any possible 3226 * use of the xfer. Also make sure the soft interrupt routine 3227 * has run. 3228 */ 3229 ehci_sync_hc(sc); 3230 sc->sc_softwake = 1; 3231 usb_schedsoftintr(&sc->sc_bus); 3232 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3233 3234 /* 3235 * Step 3: Remove any vestiges of the xfer from the hardware. 3236 * The complication here is that the hardware may have executed 3237 * beyond the xfer we're trying to abort. So as we're scanning 3238 * the TDs of this xfer we check if the hardware points to 3239 * any of them. 3240 */ 3241 3242 usb_syncmem(&sqh->dma, 3243 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3244 sizeof(sqh->qh.qh_curqtd), 3245 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3246 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3247 hit = 0; 3248 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3249 hit |= cur == sqtd->physaddr; 3250 if (sqtd == exfer->sqtdend) 3251 break; 3252 } 3253 sqtd = sqtd->nextqtd; 3254 /* Zap curqtd register if hardware pointed inside the xfer. */ 3255 if (hit && sqtd != NULL) { 3256 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3257 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3258 usb_syncmem(&sqh->dma, 3259 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3260 sizeof(sqh->qh.qh_curqtd), 3261 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3262 sqh->qh.qh_qtd.qtd_status = qhstatus; 3263 usb_syncmem(&sqh->dma, 3264 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3265 sizeof(sqh->qh.qh_qtd.qtd_status), 3266 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3267 } else { 3268 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3269 } 3270 3271 /* 3272 * Step 4: Execute callback. 3273 */ 3274 #ifdef DIAGNOSTIC 3275 exfer->isdone = 1; 3276 #endif 3277 wake = xfer->hcflags & UXFER_ABORTWAIT; 3278 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3279 usb_transfer_complete(xfer); 3280 if (wake) { 3281 cv_broadcast(&xfer->hccv); 3282 } 3283 3284 KASSERT(mutex_owned(&sc->sc_lock)); 3285 #undef exfer 3286 } 3287 3288 Static void 3289 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3290 { 3291 ehci_isoc_trans_t trans_status; 3292 struct ehci_pipe *epipe; 3293 struct ehci_xfer *exfer; 3294 ehci_softc_t *sc; 3295 struct ehci_soft_itd *itd; 3296 int i, wake; 3297 3298 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3299 3300 epipe = (struct ehci_pipe *) xfer->pipe; 3301 exfer = EXFER(xfer); 3302 sc = epipe->pipe.device->bus->hci_private; 3303 3304 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3305 3306 KASSERT(mutex_owned(&sc->sc_lock)); 3307 3308 if (sc->sc_dying) { 3309 xfer->status = status; 3310 callout_stop(&xfer->timeout_handle); 3311 usb_transfer_complete(xfer); 3312 return; 3313 } 3314 3315 if (xfer->hcflags & UXFER_ABORTING) { 3316 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3317 3318 #ifdef DIAGNOSTIC 3319 if (status == USBD_TIMEOUT) 3320 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3321 #endif 3322 3323 xfer->status = status; 3324 USBHIST_LOG(ehcidebug, 3325 "waiting for abort to finish", 0, 0, 0, 0); 3326 xfer->hcflags |= UXFER_ABORTWAIT; 3327 while (xfer->hcflags & UXFER_ABORTING) 3328 cv_wait(&xfer->hccv, &sc->sc_lock); 3329 goto done; 3330 } 3331 xfer->hcflags |= UXFER_ABORTING; 3332 3333 xfer->status = status; 3334 callout_stop(&xfer->timeout_handle); 3335 3336 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3337 usb_syncmem(&itd->dma, 3338 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3339 sizeof(itd->itd.itd_ctl), 3340 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3341 3342 for (i = 0; i < 8; i++) { 3343 trans_status = le32toh(itd->itd.itd_ctl[i]); 3344 trans_status &= ~EHCI_ITD_ACTIVE; 3345 itd->itd.itd_ctl[i] = htole32(trans_status); 3346 } 3347 3348 usb_syncmem(&itd->dma, 3349 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3350 sizeof(itd->itd.itd_ctl), 3351 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3352 } 3353 3354 sc->sc_softwake = 1; 3355 usb_schedsoftintr(&sc->sc_bus); 3356 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3357 3358 #ifdef DIAGNOSTIC 3359 exfer->isdone = 1; 3360 #endif 3361 wake = xfer->hcflags & UXFER_ABORTWAIT; 3362 xfer->hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3363 usb_transfer_complete(xfer); 3364 if (wake) { 3365 cv_broadcast(&xfer->hccv); 3366 } 3367 3368 done: 3369 KASSERT(mutex_owned(&sc->sc_lock)); 3370 return; 3371 } 3372 3373 Static void 3374 ehci_timeout(void *addr) 3375 { 3376 struct ehci_xfer *exfer = addr; 3377 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe; 3378 ehci_softc_t *sc = epipe->pipe.device->bus->hci_private; 3379 3380 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3381 3382 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3383 #ifdef EHCI_DEBUG 3384 if (ehcidebug > 1) 3385 usbd_dump_pipe(exfer->xfer.pipe); 3386 #endif 3387 3388 if (sc->sc_dying) { 3389 mutex_enter(&sc->sc_lock); 3390 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3391 mutex_exit(&sc->sc_lock); 3392 return; 3393 } 3394 3395 /* Execute the abort in a process context. */ 3396 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr, 3397 USB_TASKQ_MPSAFE); 3398 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task, 3399 USB_TASKQ_HC); 3400 } 3401 3402 Static void 3403 ehci_timeout_task(void *addr) 3404 { 3405 usbd_xfer_handle xfer = addr; 3406 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3407 3408 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3409 3410 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3411 3412 mutex_enter(&sc->sc_lock); 3413 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3414 mutex_exit(&sc->sc_lock); 3415 } 3416 3417 /************************/ 3418 3419 Static usbd_status 3420 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3421 { 3422 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3423 usbd_status err; 3424 3425 /* Insert last in queue. */ 3426 mutex_enter(&sc->sc_lock); 3427 err = usb_insert_transfer(xfer); 3428 mutex_exit(&sc->sc_lock); 3429 if (err) 3430 return (err); 3431 3432 /* Pipe isn't running, start first */ 3433 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3434 } 3435 3436 Static usbd_status 3437 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3438 { 3439 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3440 usbd_status err; 3441 3442 if (sc->sc_dying) 3443 return (USBD_IOERROR); 3444 3445 #ifdef DIAGNOSTIC 3446 if (!(xfer->rqflags & URQ_REQUEST)) { 3447 /* XXX panic */ 3448 printf("ehci_device_ctrl_transfer: not a request\n"); 3449 return (USBD_INVAL); 3450 } 3451 #endif 3452 3453 err = ehci_device_request(xfer); 3454 if (err) { 3455 return (err); 3456 } 3457 3458 if (sc->sc_bus.use_polling) 3459 ehci_waitintr(sc, xfer); 3460 3461 return (USBD_IN_PROGRESS); 3462 } 3463 3464 Static void 3465 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3466 { 3467 struct ehci_xfer *ex = EXFER(xfer); 3468 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3469 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3470 usb_device_request_t *req = &xfer->request; 3471 int len = UGETW(req->wLength); 3472 int rd = req->bmRequestType & UT_READ; 3473 3474 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3475 3476 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3477 3478 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 3479 3480 #ifdef DIAGNOSTIC 3481 if (!(xfer->rqflags & URQ_REQUEST)) { 3482 panic("ehci_ctrl_done: not a request"); 3483 } 3484 #endif 3485 3486 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3487 ehci_del_intr_list(sc, ex); /* remove from active list */ 3488 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3489 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3490 BUS_DMASYNC_POSTWRITE); 3491 if (len) 3492 usb_syncmem(&xfer->dmabuf, 0, len, 3493 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3494 } 3495 3496 USBHIST_LOG(ehcidebug, "length=%d", xfer->actlen, 0, 0, 0); 3497 } 3498 3499 /* Abort a device control request. */ 3500 Static void 3501 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3502 { 3503 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3504 3505 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3506 ehci_abort_xfer(xfer, USBD_CANCELLED); 3507 } 3508 3509 /* Close a device control pipe. */ 3510 Static void 3511 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3512 { 3513 ehci_softc_t *sc = pipe->device->bus->hci_private; 3514 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3515 3516 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3517 3518 KASSERT(mutex_owned(&sc->sc_lock)); 3519 3520 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3521 3522 ehci_close_pipe(pipe, sc->sc_async_head); 3523 } 3524 3525 Static usbd_status 3526 ehci_device_request(usbd_xfer_handle xfer) 3527 { 3528 #define exfer EXFER(xfer) 3529 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3530 usb_device_request_t *req = &xfer->request; 3531 usbd_device_handle dev = epipe->pipe.device; 3532 ehci_softc_t *sc = dev->bus->hci_private; 3533 ehci_soft_qtd_t *setup, *stat, *next; 3534 ehci_soft_qh_t *sqh; 3535 int isread; 3536 int len; 3537 usbd_status err; 3538 3539 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3540 3541 isread = req->bmRequestType & UT_READ; 3542 len = UGETW(req->wLength); 3543 3544 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3545 "wValue=0x%04x, wIndex=0x%04x", 3546 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3547 UGETW(req->wIndex)); 3548 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3549 len, dev->address, 3550 epipe->pipe.endpoint->edesc->bEndpointAddress, 0); 3551 3552 setup = ehci_alloc_sqtd(sc); 3553 if (setup == NULL) { 3554 err = USBD_NOMEM; 3555 goto bad1; 3556 } 3557 stat = ehci_alloc_sqtd(sc); 3558 if (stat == NULL) { 3559 err = USBD_NOMEM; 3560 goto bad2; 3561 } 3562 3563 mutex_enter(&sc->sc_lock); 3564 3565 sqh = epipe->sqh; 3566 3567 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->address, 3568 "address QH %d pipe %d\n", 3569 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->address); 3570 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3571 UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize), 3572 "MPS QH %d pipe %d\n", 3573 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3574 UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize)); 3575 3576 /* Set up data transaction */ 3577 if (len != 0) { 3578 ehci_soft_qtd_t *end; 3579 3580 /* Start toggle at 1. */ 3581 epipe->nexttoggle = 1; 3582 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3583 &next, &end); 3584 if (err) 3585 goto bad3; 3586 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3587 end->nextqtd = stat; 3588 end->qtd.qtd_next = end->qtd.qtd_altnext = 3589 htole32(stat->physaddr); 3590 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3591 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3592 } else { 3593 next = stat; 3594 } 3595 3596 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3597 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3598 3599 /* Clear toggle */ 3600 setup->qtd.qtd_status = htole32( 3601 EHCI_QTD_ACTIVE | 3602 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3603 EHCI_QTD_SET_CERR(3) | 3604 EHCI_QTD_SET_TOGGLE(0) | 3605 EHCI_QTD_SET_BYTES(sizeof *req) 3606 ); 3607 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3608 setup->qtd.qtd_buffer_hi[0] = 0; 3609 setup->nextqtd = next; 3610 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3611 setup->xfer = xfer; 3612 setup->len = sizeof *req; 3613 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3614 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3615 3616 stat->qtd.qtd_status = htole32( 3617 EHCI_QTD_ACTIVE | 3618 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3619 EHCI_QTD_SET_CERR(3) | 3620 EHCI_QTD_SET_TOGGLE(1) | 3621 EHCI_QTD_IOC 3622 ); 3623 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3624 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3625 stat->nextqtd = NULL; 3626 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3627 stat->xfer = xfer; 3628 stat->len = 0; 3629 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3630 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3631 3632 #ifdef EHCI_DEBUG 3633 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3634 ehci_dump_sqh(sqh); 3635 ehci_dump_sqtds(setup); 3636 #endif 3637 3638 exfer->sqtdstart = setup; 3639 exfer->sqtdend = stat; 3640 #ifdef DIAGNOSTIC 3641 if (!exfer->isdone) { 3642 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3643 } 3644 exfer->isdone = 0; 3645 #endif 3646 3647 /* Insert qTD in QH list. */ 3648 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3649 if (xfer->timeout && !sc->sc_bus.use_polling) { 3650 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3651 ehci_timeout, xfer); 3652 } 3653 ehci_add_intr_list(sc, exfer); 3654 xfer->status = USBD_IN_PROGRESS; 3655 mutex_exit(&sc->sc_lock); 3656 3657 #ifdef EHCI_DEBUG 3658 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3659 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3660 // delay(10000); 3661 ehci_dump_regs(sc); 3662 ehci_dump_sqh(sc->sc_async_head); 3663 ehci_dump_sqh(sqh); 3664 ehci_dump_sqtds(setup); 3665 #endif 3666 3667 return (USBD_NORMAL_COMPLETION); 3668 3669 bad3: 3670 mutex_exit(&sc->sc_lock); 3671 ehci_free_sqtd(sc, stat); 3672 bad2: 3673 ehci_free_sqtd(sc, setup); 3674 bad1: 3675 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3676 mutex_enter(&sc->sc_lock); 3677 xfer->status = err; 3678 usb_transfer_complete(xfer); 3679 mutex_exit(&sc->sc_lock); 3680 return (err); 3681 #undef exfer 3682 } 3683 3684 /* 3685 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3686 * qTD status, or miss signalling occasionally under heavy load. If the host 3687 * machine is too fast, we we can miss transaction completion - when we scan 3688 * the active list the transaction still seems to be active. This generally 3689 * exhibits itself as a umass stall that never recovers. 3690 * 3691 * We work around this behaviour by setting up this callback after any softintr 3692 * that completes with transactions still pending, giving us another chance to 3693 * check for completion after the writeback has taken place. 3694 */ 3695 Static void 3696 ehci_intrlist_timeout(void *arg) 3697 { 3698 ehci_softc_t *sc = arg; 3699 3700 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3701 3702 usb_schedsoftintr(&sc->sc_bus); 3703 } 3704 3705 /************************/ 3706 3707 Static usbd_status 3708 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3709 { 3710 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3711 usbd_status err; 3712 3713 /* Insert last in queue. */ 3714 mutex_enter(&sc->sc_lock); 3715 err = usb_insert_transfer(xfer); 3716 mutex_exit(&sc->sc_lock); 3717 if (err) 3718 return (err); 3719 3720 /* Pipe isn't running, start first */ 3721 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3722 } 3723 3724 Static usbd_status 3725 ehci_device_bulk_start(usbd_xfer_handle xfer) 3726 { 3727 #define exfer EXFER(xfer) 3728 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3729 usbd_device_handle dev = epipe->pipe.device; 3730 ehci_softc_t *sc = dev->bus->hci_private; 3731 ehci_soft_qtd_t *data, *dataend; 3732 ehci_soft_qh_t *sqh; 3733 usbd_status err; 3734 int len, isread, endpt; 3735 3736 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3737 3738 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3739 xfer, xfer->length, xfer->flags, 0); 3740 3741 if (sc->sc_dying) 3742 return (USBD_IOERROR); 3743 3744 #ifdef DIAGNOSTIC 3745 if (xfer->rqflags & URQ_REQUEST) 3746 panic("ehci_device_bulk_start: a request"); 3747 #endif 3748 3749 mutex_enter(&sc->sc_lock); 3750 3751 len = xfer->length; 3752 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3753 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3754 sqh = epipe->sqh; 3755 3756 epipe->u.bulk.length = len; 3757 3758 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3759 &dataend); 3760 if (err) { 3761 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3762 xfer->status = err; 3763 usb_transfer_complete(xfer); 3764 mutex_exit(&sc->sc_lock); 3765 return (err); 3766 } 3767 3768 #ifdef EHCI_DEBUG 3769 USBHIST_LOGN(ehcidebug, 5, "data(1):", 0, 0, 0, 0); 3770 ehci_dump_sqh(sqh); 3771 ehci_dump_sqtds(data); 3772 #endif 3773 3774 /* Set up interrupt info. */ 3775 exfer->sqtdstart = data; 3776 exfer->sqtdend = dataend; 3777 #ifdef DIAGNOSTIC 3778 if (!exfer->isdone) { 3779 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3780 } 3781 exfer->isdone = 0; 3782 #endif 3783 3784 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3785 if (xfer->timeout && !sc->sc_bus.use_polling) { 3786 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3787 ehci_timeout, xfer); 3788 } 3789 ehci_add_intr_list(sc, exfer); 3790 xfer->status = USBD_IN_PROGRESS; 3791 mutex_exit(&sc->sc_lock); 3792 3793 #ifdef EHCI_DEBUG 3794 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3795 // delay(10000); 3796 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3797 ehci_dump_regs(sc); 3798 #if 0 3799 printf("async_head:\n"); 3800 ehci_dump_sqh(sc->sc_async_head); 3801 #endif 3802 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3803 ehci_dump_sqh(sqh); 3804 ehci_dump_sqtds(data); 3805 #endif 3806 3807 if (sc->sc_bus.use_polling) 3808 ehci_waitintr(sc, xfer); 3809 3810 return (USBD_IN_PROGRESS); 3811 #undef exfer 3812 } 3813 3814 Static void 3815 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3816 { 3817 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3818 3819 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3820 ehci_abort_xfer(xfer, USBD_CANCELLED); 3821 } 3822 3823 /* 3824 * Close a device bulk pipe. 3825 */ 3826 Static void 3827 ehci_device_bulk_close(usbd_pipe_handle pipe) 3828 { 3829 ehci_softc_t *sc = pipe->device->bus->hci_private; 3830 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3831 3832 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3833 3834 KASSERT(mutex_owned(&sc->sc_lock)); 3835 3836 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3837 pipe->endpoint->datatoggle = epipe->nexttoggle; 3838 ehci_close_pipe(pipe, sc->sc_async_head); 3839 } 3840 3841 Static void 3842 ehci_device_bulk_done(usbd_xfer_handle xfer) 3843 { 3844 struct ehci_xfer *ex = EXFER(xfer); 3845 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3846 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3847 int endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3848 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3849 3850 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3851 3852 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3853 xfer, xfer->actlen, 0, 0); 3854 3855 KASSERT(mutex_owned(&sc->sc_lock)); 3856 3857 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3858 ehci_del_intr_list(sc, ex); /* remove from active list */ 3859 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3860 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 3861 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3862 } 3863 3864 USBHIST_LOG(ehcidebug, "length=%d", xfer->actlen, 0, 0, 0); 3865 } 3866 3867 /************************/ 3868 3869 Static usbd_status 3870 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3871 { 3872 struct ehci_soft_islot *isp; 3873 int islot, lev; 3874 3875 /* Find a poll rate that is large enough. */ 3876 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3877 if (EHCI_ILEV_IVAL(lev) <= ival) 3878 break; 3879 3880 /* Pick an interrupt slot at the right level. */ 3881 /* XXX could do better than picking at random */ 3882 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3883 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3884 3885 sqh->islot = islot; 3886 isp = &sc->sc_islots[islot]; 3887 mutex_enter(&sc->sc_lock); 3888 ehci_add_qh(sc, sqh, isp->sqh); 3889 mutex_exit(&sc->sc_lock); 3890 3891 return (USBD_NORMAL_COMPLETION); 3892 } 3893 3894 Static usbd_status 3895 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3896 { 3897 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 3898 usbd_status err; 3899 3900 /* Insert last in queue. */ 3901 mutex_enter(&sc->sc_lock); 3902 err = usb_insert_transfer(xfer); 3903 mutex_exit(&sc->sc_lock); 3904 if (err) 3905 return (err); 3906 3907 /* 3908 * Pipe isn't running (otherwise err would be USBD_INPROG), 3909 * so start it first. 3910 */ 3911 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue))); 3912 } 3913 3914 Static usbd_status 3915 ehci_device_intr_start(usbd_xfer_handle xfer) 3916 { 3917 #define exfer EXFER(xfer) 3918 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 3919 usbd_device_handle dev = xfer->pipe->device; 3920 ehci_softc_t *sc = dev->bus->hci_private; 3921 ehci_soft_qtd_t *data, *dataend; 3922 ehci_soft_qh_t *sqh; 3923 usbd_status err; 3924 int len, isread, endpt; 3925 3926 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3927 3928 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3929 xfer, xfer->length, xfer->flags, 0); 3930 3931 if (sc->sc_dying) 3932 return (USBD_IOERROR); 3933 3934 #ifdef DIAGNOSTIC 3935 if (xfer->rqflags & URQ_REQUEST) 3936 panic("ehci_device_intr_start: a request"); 3937 #endif 3938 3939 mutex_enter(&sc->sc_lock); 3940 3941 len = xfer->length; 3942 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 3943 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3944 sqh = epipe->sqh; 3945 3946 epipe->u.intr.length = len; 3947 3948 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3949 &dataend); 3950 if (err) { 3951 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3952 xfer->status = err; 3953 usb_transfer_complete(xfer); 3954 mutex_exit(&sc->sc_lock); 3955 return (err); 3956 } 3957 3958 #ifdef EHCI_DEBUG 3959 USBHIST_LOGN(ehcidebug, 5, "data(1)", 0, 0, 0, 0); 3960 ehci_dump_sqh(sqh); 3961 ehci_dump_sqtds(data); 3962 #endif 3963 3964 /* Set up interrupt info. */ 3965 exfer->sqtdstart = data; 3966 exfer->sqtdend = dataend; 3967 #ifdef DIAGNOSTIC 3968 if (!exfer->isdone) { 3969 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3970 } 3971 exfer->isdone = 0; 3972 #endif 3973 3974 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3975 if (xfer->timeout && !sc->sc_bus.use_polling) { 3976 callout_reset(&xfer->timeout_handle, mstohz(xfer->timeout), 3977 ehci_timeout, xfer); 3978 } 3979 ehci_add_intr_list(sc, exfer); 3980 xfer->status = USBD_IN_PROGRESS; 3981 mutex_exit(&sc->sc_lock); 3982 3983 #ifdef EHCI_DEBUG 3984 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3985 // delay(10000); 3986 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3987 ehci_dump_regs(sc); 3988 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3989 ehci_dump_sqh(sqh); 3990 ehci_dump_sqtds(data); 3991 #endif 3992 3993 if (sc->sc_bus.use_polling) 3994 ehci_waitintr(sc, xfer); 3995 3996 return (USBD_IN_PROGRESS); 3997 #undef exfer 3998 } 3999 4000 Static void 4001 ehci_device_intr_abort(usbd_xfer_handle xfer) 4002 { 4003 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4004 4005 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 4006 KASSERT(xfer->pipe->intrxfer == xfer); 4007 4008 /* 4009 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4010 * async doorbell. That's dependent on the async list, wheras 4011 * intr xfers are periodic, should not use this? 4012 */ 4013 ehci_abort_xfer(xfer, USBD_CANCELLED); 4014 } 4015 4016 Static void 4017 ehci_device_intr_close(usbd_pipe_handle pipe) 4018 { 4019 ehci_softc_t *sc = pipe->device->bus->hci_private; 4020 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 4021 struct ehci_soft_islot *isp; 4022 4023 KASSERT(mutex_owned(&sc->sc_lock)); 4024 4025 isp = &sc->sc_islots[epipe->sqh->islot]; 4026 ehci_close_pipe(pipe, isp->sqh); 4027 } 4028 4029 Static void 4030 ehci_device_intr_done(usbd_xfer_handle xfer) 4031 { 4032 #define exfer EXFER(xfer) 4033 struct ehci_xfer *ex = EXFER(xfer); 4034 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 4035 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe; 4036 ehci_soft_qtd_t *data, *dataend; 4037 ehci_soft_qh_t *sqh; 4038 usbd_status err; 4039 int len, isread, endpt; 4040 4041 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4042 4043 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4044 xfer, xfer->actlen, 0, 0); 4045 4046 KASSERT(sc->sc_bus.use_polling || mutex_owned(&sc->sc_lock)); 4047 4048 if (xfer->pipe->repeat) { 4049 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4050 4051 len = epipe->u.intr.length; 4052 xfer->length = len; 4053 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 4054 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4055 usb_syncmem(&xfer->dmabuf, 0, len, 4056 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4057 sqh = epipe->sqh; 4058 4059 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4060 &data, &dataend); 4061 if (err) { 4062 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4063 xfer->status = err; 4064 return; 4065 } 4066 4067 /* Set up interrupt info. */ 4068 exfer->sqtdstart = data; 4069 exfer->sqtdend = dataend; 4070 #ifdef DIAGNOSTIC 4071 if (!exfer->isdone) { 4072 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", 4073 exfer, 0, 0, 0); 4074 printf("ehci_device_intr_done: not done, ex=%p\n", 4075 exfer); 4076 } 4077 exfer->isdone = 0; 4078 #endif 4079 4080 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4081 if (xfer->timeout && !sc->sc_bus.use_polling) { 4082 callout_reset(&xfer->timeout_handle, 4083 mstohz(xfer->timeout), ehci_timeout, xfer); 4084 } 4085 4086 xfer->status = USBD_IN_PROGRESS; 4087 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4088 ehci_del_intr_list(sc, ex); /* remove from active list */ 4089 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4090 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress; 4091 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4092 usb_syncmem(&xfer->dmabuf, 0, xfer->length, 4093 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4094 } 4095 #undef exfer 4096 } 4097 4098 /************************/ 4099 4100 Static usbd_status 4101 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 4102 { 4103 ehci_softc_t *sc = xfer->pipe->device->bus->hci_private; 4104 usbd_status err; 4105 4106 mutex_enter(&sc->sc_lock); 4107 err = usb_insert_transfer(xfer); 4108 mutex_exit(&sc->sc_lock); 4109 if (err && err != USBD_IN_PROGRESS) 4110 return err; 4111 4112 return ehci_device_isoc_start(xfer); 4113 } 4114 4115 Static usbd_status 4116 ehci_device_isoc_start(usbd_xfer_handle xfer) 4117 { 4118 struct ehci_pipe *epipe; 4119 ehci_softc_t *sc; 4120 struct ehci_xfer *exfer; 4121 ehci_soft_itd_t *itd, *prev, *start, *stop; 4122 usb_dma_t *dma_buf; 4123 int i, j, k, frames, uframes, ufrperframe; 4124 int trans_count, offs, total_length; 4125 int frindex; 4126 4127 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4128 4129 start = NULL; 4130 prev = NULL; 4131 itd = NULL; 4132 trans_count = 0; 4133 total_length = 0; 4134 exfer = (struct ehci_xfer *) xfer; 4135 sc = xfer->pipe->device->bus->hci_private; 4136 epipe = (struct ehci_pipe *)xfer->pipe; 4137 4138 /* 4139 * To allow continuous transfers, above we start all transfers 4140 * immediately. However, we're still going to get usbd_start_next call 4141 * this when another xfer completes. So, check if this is already 4142 * in progress or not 4143 */ 4144 4145 if (exfer->itdstart != NULL) 4146 return USBD_IN_PROGRESS; 4147 4148 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4149 xfer, xfer->length, xfer->flags, 0); 4150 4151 if (sc->sc_dying) 4152 return USBD_IOERROR; 4153 4154 /* 4155 * To avoid complication, don't allow a request right now that'll span 4156 * the entire frame table. To within 4 frames, to allow some leeway 4157 * on either side of where the hc currently is. 4158 */ 4159 if ((1 << (epipe->pipe.endpoint->edesc->bInterval)) * 4160 xfer->nframes >= (sc->sc_flsize - 4) * 8) { 4161 USBHIST_LOG(ehcidebug, 4162 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4163 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4164 return USBD_INVAL; 4165 } 4166 4167 #ifdef DIAGNOSTIC 4168 if (xfer->rqflags & URQ_REQUEST) 4169 panic("ehci_device_isoc_start: request\n"); 4170 4171 if (!exfer->isdone) { 4172 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", exfer, 4173 0, 0, 0); 4174 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 4175 } 4176 exfer->isdone = 0; 4177 #endif 4178 4179 /* 4180 * Step 1: Allocate and initialize itds, how many do we need? 4181 * One per transfer if interval >= 8 microframes, fewer if we use 4182 * multiple microframes per frame. 4183 */ 4184 4185 i = epipe->pipe.endpoint->edesc->bInterval; 4186 if (i > 16 || i == 0) { 4187 /* Spec page 271 says intervals > 16 are invalid */ 4188 USBHIST_LOG(ehcidebug, "bInvertal %d invalid", i, 0, 0, 0); 4189 return USBD_INVAL; 4190 } 4191 4192 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4193 frames = (xfer->nframes + (ufrperframe - 1)) / ufrperframe; 4194 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4195 4196 if (frames == 0) { 4197 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4198 return USBD_INVAL; 4199 } 4200 4201 dma_buf = &xfer->dmabuf; 4202 offs = 0; 4203 4204 for (i = 0; i < frames; i++) { 4205 int froffs = offs; 4206 itd = ehci_alloc_itd(sc); 4207 4208 if (prev != NULL) { 4209 prev->itd.itd_next = 4210 htole32(itd->physaddr | EHCI_LINK_ITD); 4211 usb_syncmem(&itd->dma, 4212 itd->offs + offsetof(ehci_itd_t, itd_next), 4213 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4214 4215 prev->xfer_next = itd; 4216 } else { 4217 start = itd; 4218 } 4219 4220 /* 4221 * Step 1.5, initialize uframes 4222 */ 4223 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4224 /* Calculate which page in the list this starts in */ 4225 int addr = DMAADDR(dma_buf, froffs); 4226 addr = EHCI_PAGE_OFFSET(addr); 4227 addr += (offs - froffs); 4228 addr = EHCI_PAGE(addr); 4229 addr /= EHCI_PAGE_SIZE; 4230 4231 /* This gets the initial offset into the first page, 4232 * looks how far further along the current uframe 4233 * offset is. Works out how many pages that is. 4234 */ 4235 4236 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4237 EHCI_ITD_SET_LEN(xfer->frlengths[trans_count]) | 4238 EHCI_ITD_SET_PG(addr) | 4239 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4240 4241 total_length += xfer->frlengths[trans_count]; 4242 offs += xfer->frlengths[trans_count]; 4243 trans_count++; 4244 4245 if (trans_count >= xfer->nframes) { /*Set IOC*/ 4246 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4247 break; 4248 } 4249 } 4250 4251 /* Step 1.75, set buffer pointers. To simplify matters, all 4252 * pointers are filled out for the next 7 hardware pages in 4253 * the dma block, so no need to worry what pages to cover 4254 * and what to not. 4255 */ 4256 4257 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4258 /* 4259 * Don't try to lookup a page that's past the end 4260 * of buffer 4261 */ 4262 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4263 if (page_offs >= dma_buf->block->size) 4264 break; 4265 4266 unsigned long long page = DMAADDR(dma_buf, page_offs); 4267 page = EHCI_PAGE(page); 4268 itd->itd.itd_bufr[j] = 4269 htole32(EHCI_ITD_SET_BPTR(page)); 4270 itd->itd.itd_bufr_hi[j] = 4271 htole32(page >> 32); 4272 } 4273 4274 /* 4275 * Other special values 4276 */ 4277 4278 k = epipe->pipe.endpoint->edesc->bEndpointAddress; 4279 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4280 EHCI_ITD_SET_DADDR(epipe->pipe.device->address)); 4281 4282 k = (UE_GET_DIR(epipe->pipe.endpoint->edesc->bEndpointAddress)) 4283 ? 1 : 0; 4284 j = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize); 4285 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4286 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4287 4288 /* FIXME: handle invalid trans */ 4289 itd->itd.itd_bufr[2] |= 4290 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4291 4292 usb_syncmem(&itd->dma, 4293 itd->offs + offsetof(ehci_itd_t, itd_next), 4294 sizeof(ehci_itd_t), 4295 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4296 4297 prev = itd; 4298 } /* End of frame */ 4299 4300 stop = itd; 4301 stop->xfer_next = NULL; 4302 exfer->isoc_len = total_length; 4303 4304 usb_syncmem(&exfer->xfer.dmabuf, 0, total_length, 4305 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4306 4307 /* 4308 * Part 2: Transfer descriptors have now been set up, now they must 4309 * be scheduled into the period frame list. Erk. Not wanting to 4310 * complicate matters, transfer is denied if the transfer spans 4311 * more than the period frame list. 4312 */ 4313 4314 mutex_enter(&sc->sc_lock); 4315 4316 /* Start inserting frames */ 4317 if (epipe->u.isoc.cur_xfers > 0) { 4318 frindex = epipe->u.isoc.next_frame; 4319 } else { 4320 frindex = EOREAD4(sc, EHCI_FRINDEX); 4321 frindex = frindex >> 3; /* Erase microframe index */ 4322 frindex += 2; 4323 } 4324 4325 if (frindex >= sc->sc_flsize) 4326 frindex &= (sc->sc_flsize - 1); 4327 4328 /* What's the frame interval? */ 4329 i = (1 << (epipe->pipe.endpoint->edesc->bInterval - 1)); 4330 if (i / USB_UFRAMES_PER_FRAME == 0) 4331 i = 1; 4332 else 4333 i /= USB_UFRAMES_PER_FRAME; 4334 4335 itd = start; 4336 for (j = 0; j < frames; j++) { 4337 if (itd == NULL) 4338 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4339 4340 itd->itd.itd_next = sc->sc_flist[frindex]; 4341 if (itd->itd.itd_next == 0) 4342 /* FIXME: frindex table gets initialized to NULL 4343 * or EHCI_NULL? */ 4344 itd->itd.itd_next = EHCI_NULL; 4345 4346 usb_syncmem(&itd->dma, 4347 itd->offs + offsetof(ehci_itd_t, itd_next), 4348 sizeof(itd->itd.itd_next), 4349 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4350 4351 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4352 4353 usb_syncmem(&sc->sc_fldma, 4354 sizeof(ehci_link_t) * frindex, 4355 sizeof(ehci_link_t), 4356 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4357 4358 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4359 sc->sc_softitds[frindex] = itd; 4360 if (itd->u.frame_list.next != NULL) 4361 itd->u.frame_list.next->u.frame_list.prev = itd; 4362 itd->slot = frindex; 4363 itd->u.frame_list.prev = NULL; 4364 4365 frindex += i; 4366 if (frindex >= sc->sc_flsize) 4367 frindex -= sc->sc_flsize; 4368 4369 itd = itd->xfer_next; 4370 } 4371 4372 epipe->u.isoc.cur_xfers++; 4373 epipe->u.isoc.next_frame = frindex; 4374 4375 exfer->itdstart = start; 4376 exfer->itdend = stop; 4377 exfer->sqtdstart = NULL; 4378 exfer->sqtdend = NULL; 4379 4380 ehci_add_intr_list(sc, exfer); 4381 xfer->status = USBD_IN_PROGRESS; 4382 xfer->done = 0; 4383 mutex_exit(&sc->sc_lock); 4384 4385 if (sc->sc_bus.use_polling) { 4386 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4387 ehci_waitintr(sc, xfer); 4388 } 4389 4390 return USBD_IN_PROGRESS; 4391 } 4392 4393 Static void 4394 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4395 { 4396 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4397 4398 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4399 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4400 } 4401 4402 Static void 4403 ehci_device_isoc_close(usbd_pipe_handle pipe) 4404 { 4405 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4406 4407 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4408 } 4409 4410 Static void 4411 ehci_device_isoc_done(usbd_xfer_handle xfer) 4412 { 4413 struct ehci_xfer *exfer; 4414 ehci_softc_t *sc; 4415 struct ehci_pipe *epipe; 4416 4417 exfer = EXFER(xfer); 4418 sc = xfer->pipe->device->bus->hci_private; 4419 epipe = (struct ehci_pipe *) xfer->pipe; 4420 4421 KASSERT(mutex_owned(&sc->sc_lock)); 4422 4423 epipe->u.isoc.cur_xfers--; 4424 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4425 ehci_del_intr_list(sc, exfer); 4426 ehci_rem_free_itd_chain(sc, exfer); 4427 } 4428 4429 usb_syncmem(&xfer->dmabuf, 0, xfer->length, BUS_DMASYNC_POSTWRITE | 4430 BUS_DMASYNC_POSTREAD); 4431 4432 } 4433
Indexes created Wed Sep 24 05:09:52 GMT 2025