ehci.c revision 1.234.2.10
1 /* $NetBSD: ehci.c,v 1.234.2.10 2014/12/03 13:19:38 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.10 2014/12/03 13:19:38 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 #include <dev/usb/usbroothub_subr.h> 85 86 #include <dev/usb/ehcireg.h> 87 #include <dev/usb/ehcivar.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 /* ehci_soft_sitd_t *sitd; */ 135 } tail; 136 union { 137 /* Control pipe */ 138 struct { 139 usb_dma_t reqdma; 140 } ctl; 141 /* Interrupt pipe */ 142 struct { 143 u_int length; 144 } intr; 145 /* Bulk pipe */ 146 struct { 147 u_int length; 148 } bulk; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 } u; 155 }; 156 157 Static usbd_status ehci_open(usbd_pipe_handle); 158 Static void ehci_poll(struct usbd_bus *); 159 Static void ehci_softintr(void *); 160 Static int ehci_intr1(ehci_softc_t *); 161 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 162 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 166 Static void ehci_idone(struct ehci_xfer *); 167 Static void ehci_timeout(void *); 168 Static void ehci_timeout_task(void *); 169 Static void ehci_intrlist_timeout(void *); 170 Static void ehci_doorbell(void *); 171 Static void ehci_pcd(void *); 172 173 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 174 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 177 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle); 178 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle); 179 Static void ehci_root_ctrl_abort(usbd_xfer_handle); 180 Static void ehci_root_ctrl_close(usbd_pipe_handle); 181 Static void ehci_root_ctrl_done(usbd_xfer_handle); 182 183 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 184 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 185 Static void ehci_root_intr_abort(usbd_xfer_handle); 186 Static void ehci_root_intr_close(usbd_pipe_handle); 187 Static void ehci_root_intr_done(usbd_xfer_handle); 188 189 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 190 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 191 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 192 Static void ehci_device_ctrl_close(usbd_pipe_handle); 193 Static void ehci_device_ctrl_done(usbd_xfer_handle); 194 195 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 196 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 197 Static void ehci_device_bulk_abort(usbd_xfer_handle); 198 Static void ehci_device_bulk_close(usbd_pipe_handle); 199 Static void ehci_device_bulk_done(usbd_xfer_handle); 200 201 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 202 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 203 Static void ehci_device_intr_abort(usbd_xfer_handle); 204 Static void ehci_device_intr_close(usbd_pipe_handle); 205 Static void ehci_device_intr_done(usbd_xfer_handle); 206 207 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 208 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 209 Static void ehci_device_isoc_abort(usbd_xfer_handle); 210 Static void ehci_device_isoc_close(usbd_pipe_handle); 211 Static void ehci_device_isoc_done(usbd_xfer_handle); 212 213 Static usbd_status ehci_device_fs_isoc_transfer(usbd_xfer_handle); 214 Static usbd_status ehci_device_fs_isoc_start(usbd_xfer_handle); 215 Static void ehci_device_fs_isoc_abort(usbd_xfer_handle); 216 Static void ehci_device_fs_isoc_close(usbd_pipe_handle); 217 Static void ehci_device_fs_isoc_done(usbd_xfer_handle); 218 219 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 220 Static void ehci_noop(usbd_pipe_handle pipe); 221 222 Static void ehci_disown(ehci_softc_t *, int, int); 223 224 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 225 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 226 227 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 228 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 229 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 230 ehci_softc_t *, int, int, usbd_xfer_handle, 231 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 232 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 233 ehci_soft_qtd_t *); 234 235 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 236 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *sc); 237 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 238 Static void ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *); 239 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 240 struct ehci_xfer *exfer); 241 Static void ehci_rem_free_sitd_chain(ehci_softc_t *sc, 242 struct ehci_xfer *exfer); 243 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 244 usbd_status status); 245 246 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 247 248 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 249 int ival); 250 251 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 252 ehci_soft_qh_t *); 253 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 254 ehci_soft_qh_t *); 255 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 256 Static void ehci_sync_hc(ehci_softc_t *); 257 258 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 259 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 260 261 #ifdef EHCI_DEBUG 262 Static ehci_softc_t *theehci; 263 void ehci_dump(void); 264 #endif 265 266 #ifdef EHCI_DEBUG 267 Static void ehci_dump_regs(ehci_softc_t *); 268 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 269 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 270 Static void ehci_dump_qtd(ehci_qtd_t *); 271 Static void ehci_dump_sqh(ehci_soft_qh_t *); 272 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 273 Static void ehci_dump_itd(struct ehci_soft_itd *); 274 Static void ehci_dump_exfer(struct ehci_xfer *); 275 #endif 276 277 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 278 279 #define EHCI_INTR_ENDPT 1 280 281 #define ehci_add_intr_list(sc, ex) \ 282 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 283 #define ehci_del_intr_list(sc, ex) \ 284 do { \ 285 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 286 (ex)->inext.tqe_prev = NULL; \ 287 } while (0) 288 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 289 290 Static const struct usbd_bus_methods ehci_bus_methods = { 291 .ubm_open = ehci_open, 292 .ubm_softint = ehci_softintr, 293 .ubm_dopoll = ehci_poll, 294 .ubm_allocx = ehci_allocx, 295 .ubm_freex = ehci_freex, 296 .ubm_getlock = ehci_get_lock, 297 .ubm_newdev = NULL, 298 }; 299 300 Static const struct usbd_pipe_methods ehci_root_ctrl_methods = { 301 .upm_transfer = ehci_root_ctrl_transfer, 302 .upm_start = ehci_root_ctrl_start, 303 .upm_abort = ehci_root_ctrl_abort, 304 .upm_close = ehci_root_ctrl_close, 305 .upm_cleartoggle = ehci_noop, 306 .upm_done = ehci_root_ctrl_done, 307 }; 308 309 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 310 .upm_transfer = ehci_root_intr_transfer, 311 .upm_start = ehci_root_intr_start, 312 .upm_abort = ehci_root_intr_abort, 313 .upm_close = ehci_root_intr_close, 314 .upm_cleartoggle = ehci_noop, 315 .upm_done = ehci_root_intr_done, 316 }; 317 318 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 319 .upm_transfer = ehci_device_ctrl_transfer, 320 .upm_start = ehci_device_ctrl_start, 321 .upm_abort = ehci_device_ctrl_abort, 322 .upm_close = ehci_device_ctrl_close, 323 .upm_cleartoggle = ehci_noop, 324 .upm_done = ehci_device_ctrl_done, 325 }; 326 327 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 328 .upm_transfer = ehci_device_intr_transfer, 329 .upm_start = ehci_device_intr_start, 330 .upm_abort = ehci_device_intr_abort, 331 .upm_close = ehci_device_intr_close, 332 .upm_cleartoggle = ehci_device_clear_toggle, 333 .upm_done = ehci_device_intr_done, 334 }; 335 336 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 337 .upm_transfer = ehci_device_bulk_transfer, 338 .upm_start = ehci_device_bulk_start, 339 .upm_abort = ehci_device_bulk_abort, 340 .upm_close = ehci_device_bulk_close, 341 .upm_cleartoggle = ehci_device_clear_toggle, 342 .upm_done = ehci_device_bulk_done, 343 }; 344 345 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 346 .upm_transfer = ehci_device_isoc_transfer, 347 .upm_start = ehci_device_isoc_start, 348 .upm_abort = ehci_device_isoc_abort, 349 .upm_close = ehci_device_isoc_close, 350 .upm_cleartoggle = ehci_noop, 351 .upm_done = ehci_device_isoc_done, 352 }; 353 354 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 355 .upm_transfer = ehci_device_fs_isoc_transfer, 356 .upm_start = ehci_device_fs_isoc_start, 357 .upm_abort = ehci_device_fs_isoc_abort, 358 .upm_close = ehci_device_fs_isoc_close, 359 .upm_cleartoggle = ehci_noop, 360 .upm_done = ehci_device_fs_isoc_done, 361 }; 362 363 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 364 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 365 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 366 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 367 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 368 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 369 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 370 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 371 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 372 }; 373 374 usbd_status 375 ehci_init(ehci_softc_t *sc) 376 { 377 uint32_t vers, sparams, cparams, hcr; 378 u_int i; 379 usbd_status err; 380 ehci_soft_qh_t *sqh; 381 u_int ncomp; 382 383 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 384 #ifdef EHCI_DEBUG 385 theehci = sc; 386 #endif 387 388 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 389 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 390 cv_init(&sc->sc_softwake_cv, "ehciab"); 391 cv_init(&sc->sc_doorbell, "ehcidi"); 392 393 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 394 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 395 396 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 397 ehci_doorbell, sc); 398 KASSERT(sc->sc_doorbell_si != NULL); 399 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 400 ehci_pcd, sc); 401 KASSERT(sc->sc_pcd_si != NULL); 402 403 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 404 405 vers = EREAD2(sc, EHCI_HCIVERSION); 406 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 407 vers >> 8, vers & 0xff); 408 409 sparams = EREAD4(sc, EHCI_HCSPARAMS); 410 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 411 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 412 ncomp = EHCI_HCS_N_CC(sparams); 413 if (ncomp != sc->sc_ncomp) { 414 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 415 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 416 #if NOHCI == 0 || NUHCI == 0 417 aprint_error("%s: ohci or uhci probably not configured\n", 418 device_xname(sc->sc_dev)); 419 #endif 420 if (ncomp < sc->sc_ncomp) 421 sc->sc_ncomp = ncomp; 422 } 423 if (sc->sc_ncomp > 0) { 424 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 425 aprint_normal("%s: companion controller%s, %d port%s each:", 426 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 427 EHCI_HCS_N_PCC(sparams), 428 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 429 for (i = 0; i < sc->sc_ncomp; i++) 430 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 431 aprint_normal("\n"); 432 } 433 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 434 cparams = EREAD4(sc, EHCI_HCCPARAMS); 435 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 436 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 437 438 if (EHCI_HCC_64BIT(cparams)) { 439 /* MUST clear segment register if 64 bit capable. */ 440 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 441 } 442 443 sc->sc_bus.ub_revision = USBREV_2_0; 444 sc->sc_bus.ub_usedma = true; 445 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 446 447 /* Reset the controller */ 448 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 449 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 450 usb_delay_ms(&sc->sc_bus, 1); 451 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 452 for (i = 0; i < 100; i++) { 453 usb_delay_ms(&sc->sc_bus, 1); 454 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 455 if (!hcr) 456 break; 457 } 458 if (hcr) { 459 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 460 return (USBD_IOERROR); 461 } 462 if (sc->sc_vendor_init) 463 sc->sc_vendor_init(sc); 464 465 /* 466 * If we are doing embedded transaction translation function, force 467 * the controller to host mode. 468 */ 469 if (sc->sc_flags & EHCIF_ETTF) { 470 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 471 usbmode &= ~EHCI_USBMODE_CM; 472 usbmode |= EHCI_USBMODE_CM_HOST; 473 EWRITE4(sc, EHCI_USBMODE, usbmode); 474 } 475 476 /* XXX need proper intr scheduling */ 477 sc->sc_rand = 96; 478 479 /* frame list size at default, read back what we got and use that */ 480 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 481 case 0: sc->sc_flsize = 1024; break; 482 case 1: sc->sc_flsize = 512; break; 483 case 2: sc->sc_flsize = 256; break; 484 case 3: return (USBD_IOERROR); 485 } 486 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 487 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 488 if (err) 489 return (err); 490 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 491 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 492 493 for (i = 0; i < sc->sc_flsize; i++) { 494 sc->sc_flist[i] = EHCI_NULL; 495 } 496 497 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 498 499 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 500 KM_SLEEP); 501 if (sc->sc_softitds == NULL) 502 return ENOMEM; 503 LIST_INIT(&sc->sc_freeitds); 504 LIST_INIT(&sc->sc_freesitds); 505 TAILQ_INIT(&sc->sc_intrhead); 506 507 /* Set up the bus struct. */ 508 sc->sc_bus.ub_methods = &ehci_bus_methods; 509 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 510 511 sc->sc_eintrs = EHCI_NORMAL_INTRS; 512 513 /* 514 * Allocate the interrupt dummy QHs. These are arranged to give poll 515 * intervals that are powers of 2 times 1ms. 516 */ 517 for (i = 0; i < EHCI_INTRQHS; i++) { 518 sqh = ehci_alloc_sqh(sc); 519 if (sqh == NULL) { 520 err = USBD_NOMEM; 521 goto bad1; 522 } 523 sc->sc_islots[i].sqh = sqh; 524 } 525 for (i = 0; i < EHCI_INTRQHS; i++) { 526 sqh = sc->sc_islots[i].sqh; 527 if (i == 0) { 528 /* The last (1ms) QH terminates. */ 529 sqh->qh.qh_link = EHCI_NULL; 530 sqh->next = NULL; 531 } else { 532 /* Otherwise the next QH has half the poll interval */ 533 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 534 sqh->qh.qh_link = htole32(sqh->next->physaddr | 535 EHCI_LINK_QH); 536 } 537 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 538 sqh->qh.qh_curqtd = EHCI_NULL; 539 sqh->next = NULL; 540 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 541 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 542 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 543 sqh->sqtd = NULL; 544 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 545 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 546 } 547 /* Point the frame list at the last level (128ms). */ 548 for (i = 0; i < sc->sc_flsize; i++) { 549 int j; 550 551 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 552 revbits[i & (EHCI_MAX_POLLRATE-1)]; 553 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 554 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 555 i)].sqh->physaddr); 556 } 557 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 558 BUS_DMASYNC_PREWRITE); 559 560 /* Allocate dummy QH that starts the async list. */ 561 sqh = ehci_alloc_sqh(sc); 562 if (sqh == NULL) { 563 err = USBD_NOMEM; 564 goto bad1; 565 } 566 /* Fill the QH */ 567 sqh->qh.qh_endp = 568 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 569 sqh->qh.qh_link = 570 htole32(sqh->physaddr | EHCI_LINK_QH); 571 sqh->qh.qh_curqtd = EHCI_NULL; 572 sqh->next = NULL; 573 /* Fill the overlay qTD */ 574 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 575 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 576 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 577 sqh->sqtd = NULL; 578 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 579 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 580 #ifdef EHCI_DEBUG 581 ehci_dump_sqh(sqh); 582 #endif 583 584 /* Point to async list */ 585 sc->sc_async_head = sqh; 586 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 587 588 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 589 590 /* Turn on controller */ 591 EOWRITE4(sc, EHCI_USBCMD, 592 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 593 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 594 EHCI_CMD_ASE | 595 EHCI_CMD_PSE | 596 EHCI_CMD_RS); 597 598 /* Take over port ownership */ 599 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 600 601 for (i = 0; i < 100; i++) { 602 usb_delay_ms(&sc->sc_bus, 1); 603 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 604 if (!hcr) 605 break; 606 } 607 if (hcr) { 608 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 609 return (USBD_IOERROR); 610 } 611 612 /* Enable interrupts */ 613 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 614 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 615 616 return (USBD_NORMAL_COMPLETION); 617 618 #if 0 619 bad2: 620 ehci_free_sqh(sc, sc->sc_async_head); 621 #endif 622 bad1: 623 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 624 return (err); 625 } 626 627 int 628 ehci_intr(void *v) 629 { 630 ehci_softc_t *sc = v; 631 int ret = 0; 632 633 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 634 635 if (sc == NULL) 636 return 0; 637 638 mutex_spin_enter(&sc->sc_intr_lock); 639 640 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 641 goto done; 642 643 /* If we get an interrupt while polling, then just ignore it. */ 644 if (sc->sc_bus.ub_usepolling) { 645 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 646 647 if (intrs) 648 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 649 #ifdef DIAGNOSTIC 650 USBHIST_LOGN(ehcidebug, 16, 651 "ignored interrupt while polling", 0, 0, 0, 0); 652 #endif 653 goto done; 654 } 655 656 ret = ehci_intr1(sc); 657 658 done: 659 mutex_spin_exit(&sc->sc_intr_lock); 660 return ret; 661 } 662 663 Static int 664 ehci_intr1(ehci_softc_t *sc) 665 { 666 uint32_t intrs, eintrs; 667 668 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 669 670 /* In case the interrupt occurs before initialization has completed. */ 671 if (sc == NULL) { 672 #ifdef DIAGNOSTIC 673 printf("ehci_intr1: sc == NULL\n"); 674 #endif 675 return (0); 676 } 677 678 KASSERT(mutex_owned(&sc->sc_intr_lock)); 679 680 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 681 if (!intrs) 682 return (0); 683 684 eintrs = intrs & sc->sc_eintrs; 685 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 686 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 687 if (!eintrs) 688 return (0); 689 690 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 691 if (eintrs & EHCI_STS_IAA) { 692 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 693 kpreempt_disable(); 694 KASSERT(sc->sc_doorbell_si != NULL); 695 softint_schedule(sc->sc_doorbell_si); 696 kpreempt_enable(); 697 eintrs &= ~EHCI_STS_IAA; 698 } 699 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 700 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 701 eintrs & EHCI_STS_INT ? 1 : 0, 702 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 703 usb_schedsoftintr(&sc->sc_bus); 704 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 705 } 706 if (eintrs & EHCI_STS_HSE) { 707 printf("%s: unrecoverable error, controller halted\n", 708 device_xname(sc->sc_dev)); 709 /* XXX what else */ 710 } 711 if (eintrs & EHCI_STS_PCD) { 712 kpreempt_disable(); 713 KASSERT(sc->sc_pcd_si != NULL); 714 softint_schedule(sc->sc_pcd_si); 715 kpreempt_enable(); 716 eintrs &= ~EHCI_STS_PCD; 717 } 718 719 if (eintrs != 0) { 720 /* Block unprocessed interrupts. */ 721 sc->sc_eintrs &= ~eintrs; 722 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 723 printf("%s: blocking intrs 0x%x\n", 724 device_xname(sc->sc_dev), eintrs); 725 } 726 727 return (1); 728 } 729 730 Static void 731 ehci_doorbell(void *addr) 732 { 733 ehci_softc_t *sc = addr; 734 735 mutex_enter(&sc->sc_lock); 736 cv_broadcast(&sc->sc_doorbell); 737 mutex_exit(&sc->sc_lock); 738 } 739 740 Static void 741 ehci_pcd(void *addr) 742 { 743 ehci_softc_t *sc = addr; 744 usbd_xfer_handle xfer; 745 u_char *p; 746 int i, m; 747 748 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 749 750 mutex_enter(&sc->sc_lock); 751 xfer = sc->sc_intrxfer; 752 753 if (xfer == NULL) { 754 /* Just ignore the change. */ 755 goto done; 756 } 757 758 p = xfer->ux_buf; 759 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 760 memset(p, 0, xfer->ux_length); 761 for (i = 1; i <= m; i++) { 762 /* Pick out CHANGE bits from the status reg. */ 763 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 764 p[i/8] |= 1 << (i%8); 765 if (i % 8 == 7) 766 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 767 p[i/8], 0, 0); 768 } 769 xfer->ux_actlen = xfer->ux_length; 770 xfer->ux_status = USBD_NORMAL_COMPLETION; 771 772 usb_transfer_complete(xfer); 773 774 done: 775 mutex_exit(&sc->sc_lock); 776 } 777 778 Static void 779 ehci_softintr(void *v) 780 { 781 struct usbd_bus *bus = v; 782 ehci_softc_t *sc = bus->ub_hcpriv; 783 struct ehci_xfer *ex, *nextex; 784 785 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 786 787 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 788 789 /* 790 * The only explanation I can think of for why EHCI is as brain dead 791 * as UHCI interrupt-wise is that Intel was involved in both. 792 * An interrupt just tells us that something is done, we have no 793 * clue what, so we need to scan through all active transfers. :-( 794 */ 795 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 796 nextex = TAILQ_NEXT(ex, inext); 797 ehci_check_intr(sc, ex); 798 } 799 800 /* Schedule a callout to catch any dropped transactions. */ 801 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 802 !TAILQ_EMPTY(&sc->sc_intrhead)) 803 callout_reset(&sc->sc_tmo_intrlist, 804 hz, ehci_intrlist_timeout, sc); 805 806 if (sc->sc_softwake) { 807 sc->sc_softwake = 0; 808 cv_broadcast(&sc->sc_softwake_cv); 809 } 810 } 811 812 /* Check for an interrupt. */ 813 Static void 814 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 815 { 816 usbd_device_handle dev = ex->xfer.ux_pipe->up_dev; 817 int attr; 818 819 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 820 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 821 822 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 823 824 attr = ex->xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 825 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 826 if (dev->ud_speed == USB_SPEED_HIGH) 827 ehci_check_itd_intr(sc, ex); 828 else 829 ehci_check_sitd_intr(sc, ex); 830 } else 831 ehci_check_qh_intr(sc, ex); 832 833 return; 834 } 835 836 Static void 837 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 838 { 839 ehci_soft_qtd_t *sqtd, *lsqtd; 840 uint32_t status; 841 842 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 843 844 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 845 846 if (ex->sqtdstart == NULL) { 847 printf("ehci_check_qh_intr: not valid sqtd\n"); 848 return; 849 } 850 851 lsqtd = ex->sqtdend; 852 #ifdef DIAGNOSTIC 853 if (lsqtd == NULL) { 854 printf("ehci_check_qh_intr: lsqtd==0\n"); 855 return; 856 } 857 #endif 858 /* 859 * If the last TD is still active we need to check whether there 860 * is an error somewhere in the middle, or whether there was a 861 * short packet (SPD and not ACTIVE). 862 */ 863 usb_syncmem(&lsqtd->dma, 864 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 865 sizeof(lsqtd->qtd.qtd_status), 866 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 867 status = le32toh(lsqtd->qtd.qtd_status); 868 usb_syncmem(&lsqtd->dma, 869 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 870 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 871 if (status & EHCI_QTD_ACTIVE) { 872 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 873 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 874 usb_syncmem(&sqtd->dma, 875 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 876 sizeof(sqtd->qtd.qtd_status), 877 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 878 status = le32toh(sqtd->qtd.qtd_status); 879 usb_syncmem(&sqtd->dma, 880 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 881 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 882 /* If there's an active QTD the xfer isn't done. */ 883 if (status & EHCI_QTD_ACTIVE) 884 break; 885 /* Any kind of error makes the xfer done. */ 886 if (status & EHCI_QTD_HALTED) 887 goto done; 888 /* Handle short packets */ 889 if (EHCI_QTD_GET_BYTES(status) != 0) { 890 usbd_pipe_handle pipe = ex->xfer.ux_pipe; 891 usb_endpoint_descriptor_t *ed = 892 pipe->up_endpoint->ue_edesc; 893 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 894 895 /* 896 * If we get here for a control transfer then 897 * we need to let the hardware complete the 898 * status phase. That is, we're not done 899 * quite yet. 900 * 901 * Otherwise, we're done. 902 */ 903 if (xt == UE_CONTROL) { 904 break; 905 } 906 goto done; 907 } 908 } 909 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 910 ex, ex->sqtdstart, 0, 0); 911 return; 912 } 913 done: 914 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 915 callout_stop(&ex->xfer.ux_callout); 916 ehci_idone(ex); 917 } 918 919 Static void 920 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 921 { 922 ehci_soft_itd_t *itd; 923 int i; 924 925 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 926 927 KASSERT(mutex_owned(&sc->sc_lock)); 928 929 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.ux_pipe->up_queue)) 930 return; 931 932 if (ex->itdstart == NULL) { 933 printf("ehci_check_itd_intr: not valid itd\n"); 934 return; 935 } 936 937 itd = ex->itdend; 938 #ifdef DIAGNOSTIC 939 if (itd == NULL) { 940 printf("ehci_check_itd_intr: itdend == 0\n"); 941 return; 942 } 943 #endif 944 945 /* 946 * check no active transfers in last itd, meaning we're finished 947 */ 948 949 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 950 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 951 BUS_DMASYNC_POSTREAD); 952 953 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 954 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 955 break; 956 } 957 958 if (i == EHCI_ITD_NUFRAMES) { 959 goto done; /* All 8 descriptors inactive, it's done */ 960 } 961 962 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 963 ex->itdstart, 0, 0); 964 return; 965 done: 966 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 967 callout_stop(&ex->xfer.ux_callout); 968 ehci_idone(ex); 969 } 970 971 void 972 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 973 { 974 ehci_soft_sitd_t *sitd; 975 976 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 977 978 KASSERT(mutex_owned(&sc->sc_lock)); 979 980 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.ux_pipe->up_queue)) 981 return; 982 983 if (ex->sitdstart == NULL) { 984 printf("ehci_check_sitd_intr: not valid sitd\n"); 985 return; 986 } 987 988 sitd = ex->sitdend; 989 #ifdef DIAGNOSTIC 990 if (sitd == NULL) { 991 printf("ehci_check_sitd_intr: sitdend == 0\n"); 992 return; 993 } 994 #endif 995 996 /* 997 * check no active transfers in last sitd, meaning we're finished 998 */ 999 1000 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 1001 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 1002 BUS_DMASYNC_POSTREAD); 1003 1004 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 1005 return; 1006 1007 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 1008 callout_stop(&(ex->xfer.ux_callout)); 1009 ehci_idone(ex); 1010 } 1011 1012 1013 Static void 1014 ehci_idone(struct ehci_xfer *ex) 1015 { 1016 usbd_xfer_handle xfer = &ex->xfer; 1017 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1018 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1019 ehci_soft_qtd_t *sqtd, *lsqtd; 1020 uint32_t status = 0, nstatus = 0; 1021 int actlen; 1022 1023 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1024 1025 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1026 1027 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1028 1029 #ifdef DIAGNOSTIC 1030 if (ex->isdone) { 1031 printf("ehci_idone: ex=%p is done!\n", ex); 1032 #ifdef EHCI_DEBUG 1033 ehci_dump_exfer(ex); 1034 #endif 1035 return; 1036 } 1037 ex->isdone = 1; 1038 #endif 1039 1040 if (xfer->ux_status == USBD_CANCELLED || 1041 xfer->ux_status == USBD_TIMEOUT) { 1042 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1043 return; 1044 } 1045 1046 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1047 #ifdef EHCI_DEBUG 1048 ehci_dump_sqtds(ex->sqtdstart); 1049 #endif 1050 1051 /* The transfer is done, compute actual length and status. */ 1052 1053 u_int xfertype, speed; 1054 1055 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1056 speed = xfer->ux_pipe->up_dev->ud_speed; 1057 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1058 /* HS isoc transfer */ 1059 1060 struct ehci_soft_itd *itd; 1061 int i, nframes, len, uframes; 1062 1063 nframes = 0; 1064 actlen = 0; 1065 1066 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1067 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1068 1069 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1070 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1071 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1072 BUS_DMASYNC_POSTREAD); 1073 1074 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1075 /* XXX - driver didn't fill in the frame full 1076 * of uframes. This leads to scheduling 1077 * inefficiencies, but working around 1078 * this doubles complexity of tracking 1079 * an xfer. 1080 */ 1081 if (nframes >= xfer->ux_nframes) 1082 break; 1083 1084 status = le32toh(itd->itd.itd_ctl[i]); 1085 len = EHCI_ITD_GET_LEN(status); 1086 if (EHCI_ITD_GET_STATUS(status) != 0) 1087 len = 0; /*No valid data on error*/ 1088 1089 xfer->ux_frlengths[nframes++] = len; 1090 actlen += len; 1091 } 1092 1093 if (nframes >= xfer->ux_nframes) 1094 break; 1095 } 1096 1097 xfer->ux_actlen = actlen; 1098 xfer->ux_status = USBD_NORMAL_COMPLETION; 1099 goto end; 1100 } 1101 1102 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1103 /* FS isoc transfer */ 1104 struct ehci_soft_sitd *sitd; 1105 int nframes, len; 1106 1107 nframes = 0; 1108 actlen = 0; 1109 1110 for (sitd = ex->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1111 usb_syncmem(&sitd->dma,sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 1112 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 1113 BUS_DMASYNC_POSTREAD); 1114 1115 /* XXX - driver didn't fill in the frame full 1116 * of uframes. This leads to scheduling 1117 * inefficiencies, but working around 1118 * this doubles complexity of tracking 1119 * an xfer. 1120 */ 1121 if (nframes >= xfer->ux_nframes) 1122 break; 1123 1124 status = le32toh(sitd->sitd.sitd_trans); 1125 len = EHCI_SITD_GET_LEN(status); 1126 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1127 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1128 /* No valid data on error */ 1129 len = xfer->ux_frlengths[nframes]; 1130 } 1131 1132 /* 1133 * frlengths[i]: # of bytes to send 1134 * len: # of bytes host didn't send 1135 */ 1136 xfer->ux_frlengths[nframes] -= len; 1137 /* frlengths[i]: # of bytes host sent */ 1138 actlen += xfer->ux_frlengths[nframes++]; 1139 1140 if (nframes >= xfer->ux_nframes) 1141 break; 1142 } 1143 1144 xfer->ux_actlen = actlen; 1145 xfer->ux_status = USBD_NORMAL_COMPLETION; 1146 goto end; 1147 } 1148 1149 /* Continue processing xfers using queue heads */ 1150 1151 lsqtd = ex->sqtdend; 1152 actlen = 0; 1153 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; 1154 sqtd = sqtd->nextqtd) { 1155 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1156 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1157 nstatus = le32toh(sqtd->qtd.qtd_status); 1158 if (nstatus & EHCI_QTD_ACTIVE) 1159 break; 1160 1161 status = nstatus; 1162 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1163 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1164 } 1165 1166 1167 /* 1168 * If there are left over TDs we need to update the toggle. 1169 * The default pipe doesn't need it since control transfers 1170 * start the toggle at 0 every time. 1171 * For a short transfer we need to update the toggle for the missing 1172 * packets within the qTD. 1173 */ 1174 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1175 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1176 USBHIST_LOG(ehcidebug, 1177 "toggle update status=0x%08x nstatus=0x%08x", 1178 status, nstatus, 0, 0); 1179 #if 0 1180 ehci_dump_sqh(epipe->sqh); 1181 ehci_dump_sqtds(ex->sqtdstart); 1182 #endif 1183 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1184 } 1185 1186 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1187 actlen, status, 0); 1188 xfer->ux_actlen = actlen; 1189 if (status & EHCI_QTD_HALTED) { 1190 #ifdef EHCI_DEBUG 1191 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1192 xfer->ux_pipe->up_dev->ud_addr, 1193 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1194 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d stat=%#x", 1195 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1196 status, 0); 1197 USBHIST_LOG(ehcidebug, 1198 "active =%d halted=%d buferr=%d babble=%d", 1199 status & EHCI_QTD_ACTIVE ? 1 : 0, 1200 status & EHCI_QTD_HALTED ? 1 : 0, 1201 status & EHCI_QTD_BUFERR ? 1 : 0, 1202 status & EHCI_QTD_BABBLE ? 1 : 0); 1203 1204 USBHIST_LOG(ehcidebug, 1205 "xacterr=%d missed=%d split =%d ping =%d", 1206 status & EHCI_QTD_XACTERR ? 1 : 0, 1207 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1208 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1209 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1210 1211 ehci_dump_sqh(epipe->sqh); 1212 ehci_dump_sqtds(ex->sqtdstart); 1213 #endif 1214 /* low&full speed has an extra error flag */ 1215 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1216 EHCI_QH_SPEED_HIGH) 1217 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1218 else 1219 status &= EHCI_QTD_STATERRS; 1220 if (status == 0) /* no other errors means a stall */ { 1221 xfer->ux_status = USBD_STALLED; 1222 } else { 1223 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1224 } 1225 /* XXX need to reset TT on missed microframe */ 1226 if (status & EHCI_QTD_MISSEDMICRO) { 1227 printf("%s: missed microframe, TT reset not " 1228 "implemented, hub might be inoperational\n", 1229 device_xname(sc->sc_dev)); 1230 } 1231 } else { 1232 xfer->ux_status = USBD_NORMAL_COMPLETION; 1233 } 1234 1235 end: 1236 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1237 * during this call, before methods->done is called: dma sync required 1238 * beforehand? */ 1239 usb_transfer_complete(xfer); 1240 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1241 } 1242 1243 /* 1244 * Wait here until controller claims to have an interrupt. 1245 * Then call ehci_intr and return. Use timeout to avoid waiting 1246 * too long. 1247 */ 1248 Static void 1249 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1250 { 1251 int timo; 1252 uint32_t intrs; 1253 1254 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1255 1256 xfer->ux_status = USBD_IN_PROGRESS; 1257 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1258 usb_delay_ms(&sc->sc_bus, 1); 1259 if (sc->sc_dying) 1260 break; 1261 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1262 sc->sc_eintrs; 1263 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1264 #ifdef EHCI_DEBUG 1265 if (ehcidebug > 15) 1266 ehci_dump_regs(sc); 1267 #endif 1268 if (intrs) { 1269 mutex_spin_enter(&sc->sc_intr_lock); 1270 ehci_intr1(sc); 1271 mutex_spin_exit(&sc->sc_intr_lock); 1272 if (xfer->ux_status != USBD_IN_PROGRESS) 1273 return; 1274 } 1275 } 1276 1277 /* Timeout */ 1278 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1279 xfer->ux_status = USBD_TIMEOUT; 1280 mutex_enter(&sc->sc_lock); 1281 usb_transfer_complete(xfer); 1282 mutex_exit(&sc->sc_lock); 1283 /* XXX should free TD */ 1284 } 1285 1286 Static void 1287 ehci_poll(struct usbd_bus *bus) 1288 { 1289 ehci_softc_t *sc = bus->ub_hcpriv; 1290 1291 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1292 1293 #ifdef EHCI_DEBUG 1294 static int last; 1295 int new; 1296 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1297 if (new != last) { 1298 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1299 last = new; 1300 } 1301 #endif 1302 1303 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1304 mutex_spin_enter(&sc->sc_intr_lock); 1305 ehci_intr1(sc); 1306 mutex_spin_exit(&sc->sc_intr_lock); 1307 } 1308 } 1309 1310 void 1311 ehci_childdet(device_t self, device_t child) 1312 { 1313 struct ehci_softc *sc = device_private(self); 1314 1315 KASSERT(sc->sc_child == child); 1316 sc->sc_child = NULL; 1317 } 1318 1319 int 1320 ehci_detach(struct ehci_softc *sc, int flags) 1321 { 1322 int rv = 0; 1323 1324 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1325 1326 if (sc->sc_child != NULL) 1327 rv = config_detach(sc->sc_child, flags); 1328 1329 if (rv != 0) 1330 return (rv); 1331 1332 callout_halt(&sc->sc_tmo_intrlist, NULL); 1333 callout_destroy(&sc->sc_tmo_intrlist); 1334 1335 /* XXX free other data structures XXX */ 1336 if (sc->sc_softitds) 1337 kmem_free(sc->sc_softitds, 1338 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1339 cv_destroy(&sc->sc_doorbell); 1340 cv_destroy(&sc->sc_softwake_cv); 1341 1342 #if 0 1343 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1344 1345 softint_disestablish(sc->sc_doorbell_si); 1346 softint_disestablish(sc->sc_pcd_si); 1347 1348 mutex_destroy(&sc->sc_lock); 1349 mutex_destroy(&sc->sc_intr_lock); 1350 #endif 1351 1352 pool_cache_destroy(sc->sc_xferpool); 1353 1354 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1355 1356 return (rv); 1357 } 1358 1359 1360 int 1361 ehci_activate(device_t self, enum devact act) 1362 { 1363 struct ehci_softc *sc = device_private(self); 1364 1365 switch (act) { 1366 case DVACT_DEACTIVATE: 1367 sc->sc_dying = 1; 1368 return 0; 1369 default: 1370 return EOPNOTSUPP; 1371 } 1372 } 1373 1374 /* 1375 * Handle suspend/resume. 1376 * 1377 * We need to switch to polling mode here, because this routine is 1378 * called from an interrupt context. This is all right since we 1379 * are almost suspended anyway. 1380 * 1381 * Note that this power handler isn't to be registered directly; the 1382 * bus glue needs to call out to it. 1383 */ 1384 bool 1385 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1386 { 1387 ehci_softc_t *sc = device_private(dv); 1388 int i; 1389 uint32_t cmd, hcr; 1390 1391 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1392 1393 mutex_spin_enter(&sc->sc_intr_lock); 1394 sc->sc_bus.ub_usepolling++; 1395 mutex_spin_exit(&sc->sc_intr_lock); 1396 1397 for (i = 1; i <= sc->sc_noport; i++) { 1398 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1399 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1400 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1401 } 1402 1403 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1404 1405 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1406 EOWRITE4(sc, EHCI_USBCMD, cmd); 1407 1408 for (i = 0; i < 100; i++) { 1409 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1410 if (hcr == 0) 1411 break; 1412 1413 usb_delay_ms(&sc->sc_bus, 1); 1414 } 1415 if (hcr != 0) 1416 printf("%s: reset timeout\n", device_xname(dv)); 1417 1418 cmd &= ~EHCI_CMD_RS; 1419 EOWRITE4(sc, EHCI_USBCMD, cmd); 1420 1421 for (i = 0; i < 100; i++) { 1422 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1423 if (hcr == EHCI_STS_HCH) 1424 break; 1425 1426 usb_delay_ms(&sc->sc_bus, 1); 1427 } 1428 if (hcr != EHCI_STS_HCH) 1429 printf("%s: config timeout\n", device_xname(dv)); 1430 1431 mutex_spin_enter(&sc->sc_intr_lock); 1432 sc->sc_bus.ub_usepolling--; 1433 mutex_spin_exit(&sc->sc_intr_lock); 1434 1435 return true; 1436 } 1437 1438 bool 1439 ehci_resume(device_t dv, const pmf_qual_t *qual) 1440 { 1441 ehci_softc_t *sc = device_private(dv); 1442 int i; 1443 uint32_t cmd, hcr; 1444 1445 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1446 1447 /* restore things in case the bios sucks */ 1448 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1449 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1450 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1451 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1452 1453 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1454 1455 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1456 1457 hcr = 0; 1458 for (i = 1; i <= sc->sc_noport; i++) { 1459 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1460 if ((cmd & EHCI_PS_PO) == 0 && 1461 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1462 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1463 hcr = 1; 1464 } 1465 } 1466 1467 if (hcr) { 1468 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1469 1470 for (i = 1; i <= sc->sc_noport; i++) { 1471 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1472 if ((cmd & EHCI_PS_PO) == 0 && 1473 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1474 EOWRITE4(sc, EHCI_PORTSC(i), 1475 cmd & ~EHCI_PS_FPR); 1476 } 1477 } 1478 1479 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1480 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1481 1482 for (i = 0; i < 100; i++) { 1483 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1484 if (hcr != EHCI_STS_HCH) 1485 break; 1486 1487 usb_delay_ms(&sc->sc_bus, 1); 1488 } 1489 if (hcr == EHCI_STS_HCH) 1490 printf("%s: config timeout\n", device_xname(dv)); 1491 1492 return true; 1493 } 1494 1495 /* 1496 * Shut down the controller when the system is going down. 1497 */ 1498 bool 1499 ehci_shutdown(device_t self, int flags) 1500 { 1501 ehci_softc_t *sc = device_private(self); 1502 1503 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1504 1505 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1506 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1507 return true; 1508 } 1509 1510 Static usbd_xfer_handle 1511 ehci_allocx(struct usbd_bus *bus) 1512 { 1513 struct ehci_softc *sc = bus->ub_hcpriv; 1514 usbd_xfer_handle xfer; 1515 1516 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1517 if (xfer != NULL) { 1518 memset(xfer, 0, sizeof(struct ehci_xfer)); 1519 #ifdef DIAGNOSTIC 1520 EXFER(xfer)->isdone = 1; 1521 xfer->ux_state = XFER_BUSY; 1522 #endif 1523 } 1524 return (xfer); 1525 } 1526 1527 Static void 1528 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1529 { 1530 struct ehci_softc *sc = bus->ub_hcpriv; 1531 1532 #ifdef DIAGNOSTIC 1533 if (xfer->ux_state != XFER_BUSY) { 1534 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1535 xfer->ux_state); 1536 } 1537 xfer->ux_state = XFER_FREE; 1538 if (!EXFER(xfer)->isdone) { 1539 printf("ehci_freex: !isdone\n"); 1540 } 1541 #endif 1542 pool_cache_put(sc->sc_xferpool, xfer); 1543 } 1544 1545 Static void 1546 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1547 { 1548 struct ehci_softc *sc = bus->ub_hcpriv; 1549 1550 *lock = &sc->sc_lock; 1551 } 1552 1553 Static void 1554 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1555 { 1556 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1557 1558 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1559 1560 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1561 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1562 #ifdef EHCI_DEBUG 1563 if (ehcidebug) 1564 usbd_dump_pipe(pipe); 1565 #endif 1566 epipe->nexttoggle = 0; 1567 } 1568 1569 Static void 1570 ehci_noop(usbd_pipe_handle pipe) 1571 { 1572 } 1573 1574 #ifdef EHCI_DEBUG 1575 /* 1576 * Unused function - this is meant to be called from a kernel 1577 * debugger. 1578 */ 1579 void 1580 ehci_dump(void) 1581 { 1582 ehci_softc_t *sc = theehci; 1583 int i; 1584 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1585 EOREAD4(sc, EHCI_USBCMD), 1586 EOREAD4(sc, EHCI_USBSTS), 1587 EOREAD4(sc, EHCI_USBINTR)); 1588 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1589 EOREAD4(sc, EHCI_FRINDEX), 1590 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1591 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1592 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1593 for (i = 1; i <= sc->sc_noport; i++) 1594 printf("port %d status=0x%08x\n", i, 1595 EOREAD4(sc, EHCI_PORTSC(i))); 1596 } 1597 1598 Static void 1599 ehci_dump_regs(ehci_softc_t *sc) 1600 { 1601 int i; 1602 1603 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1604 1605 USBHIST_LOG(ehcidebug, 1606 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1607 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1608 EOREAD4(sc, EHCI_USBINTR), 0); 1609 USBHIST_LOG(ehcidebug, 1610 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1611 "async = 0x%08x", 1612 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1613 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1614 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1615 for (i = 1; i <= sc->sc_noport; i += 2) { 1616 if (i == sc->sc_noport) { 1617 USBHIST_LOG(ehcidebug, 1618 "port %d status = 0x%08x", i, 1619 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1620 } else { 1621 USBHIST_LOG(ehcidebug, 1622 "port %d status = 0x%08x port %d status = 0x%08x", 1623 i, EOREAD4(sc, EHCI_PORTSC(i)), 1624 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1625 } 1626 } 1627 } 1628 1629 #ifdef EHCI_DEBUG 1630 #define ehci_dump_link(link, type) do { \ 1631 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1632 link, \ 1633 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1634 if (type) { \ 1635 USBHIST_LOG(ehcidebug, \ 1636 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1637 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1638 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1639 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1640 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1641 } \ 1642 } while(0) 1643 #else 1644 #define ehci_dump_link(link, type) 1645 #endif 1646 1647 Static void 1648 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1649 { 1650 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1651 int i; 1652 uint32_t stop = 0; 1653 1654 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1655 ehci_dump_sqtd(sqtd); 1656 usb_syncmem(&sqtd->dma, 1657 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1658 sizeof(sqtd->qtd), 1659 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1660 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1661 usb_syncmem(&sqtd->dma, 1662 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1663 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1664 } 1665 if (sqtd) 1666 USBHIST_LOG(ehcidebug, 1667 "dump aborted, too many TDs", 0, 0, 0, 0); 1668 } 1669 1670 Static void 1671 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1672 { 1673 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1674 1675 usb_syncmem(&sqtd->dma, sqtd->offs, 1676 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1677 1678 USBHIST_LOGN(ehcidebug, 10, 1679 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1680 ehci_dump_qtd(&sqtd->qtd); 1681 1682 usb_syncmem(&sqtd->dma, sqtd->offs, 1683 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1684 } 1685 1686 Static void 1687 ehci_dump_qtd(ehci_qtd_t *qtd) 1688 { 1689 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1690 1691 #ifdef USBHIST 1692 uint32_t s = le32toh(qtd->qtd_status); 1693 #endif 1694 1695 USBHIST_LOGN(ehcidebug, 10, 1696 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1697 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1698 USBHIST_LOGN(ehcidebug, 10, 1699 " toggle = %d ioc = %d bytes = %#x " 1700 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1701 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1702 USBHIST_LOGN(ehcidebug, 10, 1703 " cerr = %d pid = %d stat = %x", 1704 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1705 0); 1706 USBHIST_LOGN(ehcidebug, 10, 1707 "active =%d halted=%d buferr=%d babble=%d", 1708 s & EHCI_QTD_ACTIVE ? 1 : 0, 1709 s & EHCI_QTD_HALTED ? 1 : 0, 1710 s & EHCI_QTD_BUFERR ? 1 : 0, 1711 s & EHCI_QTD_BABBLE ? 1 : 0); 1712 USBHIST_LOGN(ehcidebug, 10, 1713 "xacterr=%d missed=%d split =%d ping =%d", 1714 s & EHCI_QTD_XACTERR ? 1 : 0, 1715 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1716 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1717 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1718 USBHIST_LOGN(ehcidebug, 10, 1719 "buffer[0] = %#x buffer[1] = %#x " 1720 "buffer[2] = %#x buffer[3] = %#x", 1721 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1722 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1723 USBHIST_LOGN(ehcidebug, 10, 1724 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1725 } 1726 1727 Static void 1728 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1729 { 1730 #ifdef USBHIST 1731 ehci_qh_t *qh = &sqh->qh; 1732 ehci_link_t link; 1733 #endif 1734 uint32_t endp, endphub; 1735 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1736 1737 usb_syncmem(&sqh->dma, sqh->offs, 1738 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1739 1740 USBHIST_LOGN(ehcidebug, 10, 1741 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1742 link = le32toh(qh->qh_link); 1743 ehci_dump_link(link, true); 1744 1745 endp = le32toh(qh->qh_endp); 1746 USBHIST_LOGN(ehcidebug, 10, 1747 " endp = %#x", endp, 0, 0, 0); 1748 USBHIST_LOGN(ehcidebug, 10, 1749 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1750 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1751 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1752 USBHIST_LOGN(ehcidebug, 10, 1753 " dtc = %d hrecl = %d", 1754 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1755 USBHIST_LOGN(ehcidebug, 10, 1756 " ctl = %d nrl = %d mpl = %#x(%d)", 1757 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1758 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1759 1760 endphub = le32toh(qh->qh_endphub); 1761 USBHIST_LOGN(ehcidebug, 10, 1762 " endphub = %#x", endphub, 0, 0, 0); 1763 USBHIST_LOGN(ehcidebug, 10, 1764 " smask = 0x%02x cmask = 0x%02x", 1765 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1766 USBHIST_LOGN(ehcidebug, 10, 1767 " huba = 0x%02x port = %d mult = %d", 1768 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1769 EHCI_QH_GET_MULT(endphub), 0); 1770 1771 link = le32toh(qh->qh_curqtd); 1772 ehci_dump_link(link, false); 1773 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1774 ehci_dump_qtd(&qh->qh_qtd); 1775 1776 usb_syncmem(&sqh->dma, sqh->offs, 1777 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1778 } 1779 1780 Static void 1781 ehci_dump_itd(struct ehci_soft_itd *itd) 1782 { 1783 ehci_isoc_trans_t t; 1784 ehci_isoc_bufr_ptr_t b, b2, b3; 1785 int i; 1786 1787 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1788 1789 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1790 0, 0); 1791 1792 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1793 t = le32toh(itd->itd.itd_ctl[i]); 1794 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1795 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1796 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1797 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1798 EHCI_ITD_GET_OFFS(t), 0); 1799 } 1800 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1801 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1802 USBHIST_LOG(ehcidebug, " %x", 1803 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1804 1805 b = le32toh(itd->itd.itd_bufr[0]); 1806 b2 = le32toh(itd->itd.itd_bufr[1]); 1807 b3 = le32toh(itd->itd.itd_bufr[2]); 1808 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1809 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1810 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1811 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1812 } 1813 1814 Static void 1815 ehci_dump_sitd(struct ehci_soft_itd *itd) 1816 { 1817 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1818 1819 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1820 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1821 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1822 itd->xfer_next, itd->physaddr, itd->slot, 0); 1823 } 1824 1825 Static void 1826 ehci_dump_exfer(struct ehci_xfer *ex) 1827 { 1828 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1829 1830 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1831 ex, ex->sqtdstart, ex->sqtdend, 0); 1832 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1833 ex->itdstart, ex->itdend, ex->isdone, 0); 1834 } 1835 #endif 1836 1837 Static usbd_status 1838 ehci_open(usbd_pipe_handle pipe) 1839 { 1840 usbd_device_handle dev = pipe->up_dev; 1841 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1842 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1843 uint8_t addr = dev->ud_addr; 1844 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1845 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1846 ehci_soft_qh_t *sqh; 1847 usbd_status err; 1848 int ival, speed, naks; 1849 int hshubaddr, hshubport; 1850 1851 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1852 1853 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1854 pipe, addr, ed->bEndpointAddress, sc->sc_addr); 1855 1856 if (dev->ud_myhsport) { 1857 /* 1858 * When directly attached FS/LS device while doing embedded 1859 * transaction translations and we are the hub, set the hub 1860 * address to 0 (us). 1861 */ 1862 if (!(sc->sc_flags & EHCIF_ETTF) 1863 || (dev->ud_myhsport->up_parent->ud_addr != sc->sc_addr)) { 1864 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1865 } else { 1866 hshubaddr = 0; 1867 } 1868 hshubport = dev->ud_myhsport->up_portno; 1869 } else { 1870 hshubaddr = 0; 1871 hshubport = 0; 1872 } 1873 1874 if (sc->sc_dying) 1875 return (USBD_IOERROR); 1876 1877 /* toggle state needed for bulk endpoints */ 1878 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1879 1880 if (addr == sc->sc_addr) { 1881 switch (ed->bEndpointAddress) { 1882 case USB_CONTROL_ENDPOINT: 1883 pipe->up_methods = &ehci_root_ctrl_methods; 1884 break; 1885 case UE_DIR_IN | EHCI_INTR_ENDPT: 1886 pipe->up_methods = &ehci_root_intr_methods; 1887 break; 1888 default: 1889 USBHIST_LOG(ehcidebug, 1890 "bad bEndpointAddress 0x%02x", 1891 ed->bEndpointAddress, 0, 0, 0); 1892 return (USBD_INVAL); 1893 } 1894 return (USBD_NORMAL_COMPLETION); 1895 } 1896 1897 /* XXX All this stuff is only valid for async. */ 1898 switch (dev->ud_speed) { 1899 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1900 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1901 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1902 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1903 } 1904 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1905 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1906 hshubaddr, hshubport, 0, 0); 1907 return USBD_INVAL; 1908 } 1909 1910 /* 1911 * For interrupt transfer, nak throttling must be disabled, but for 1912 * the other transfer type, nak throttling should be enabled from the 1913 * viewpoint that avoids the memory thrashing. 1914 */ 1915 naks = (xfertype == UE_INTERRUPT) ? 0 1916 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1917 1918 /* Allocate sqh for everything, save isoc xfers */ 1919 if (xfertype != UE_ISOCHRONOUS) { 1920 sqh = ehci_alloc_sqh(sc); 1921 if (sqh == NULL) 1922 return (USBD_NOMEM); 1923 /* qh_link filled when the QH is added */ 1924 sqh->qh.qh_endp = htole32( 1925 EHCI_QH_SET_ADDR(addr) | 1926 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1927 EHCI_QH_SET_EPS(speed) | 1928 EHCI_QH_DTC | 1929 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1930 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1931 EHCI_QH_CTL : 0) | 1932 EHCI_QH_SET_NRL(naks) 1933 ); 1934 sqh->qh.qh_endphub = htole32( 1935 EHCI_QH_SET_MULT(1) | 1936 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1937 ); 1938 if (speed != EHCI_QH_SPEED_HIGH) 1939 sqh->qh.qh_endphub |= htole32( 1940 EHCI_QH_SET_PORT(hshubport) | 1941 EHCI_QH_SET_HUBA(hshubaddr) | 1942 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1943 ); 1944 sqh->qh.qh_curqtd = EHCI_NULL; 1945 /* Fill the overlay qTD */ 1946 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1947 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1948 sqh->qh.qh_qtd.qtd_status = htole32(0); 1949 1950 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1951 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1952 epipe->sqh = sqh; 1953 } else { 1954 sqh = NULL; 1955 } /*xfertype == UE_ISOC*/ 1956 1957 switch (xfertype) { 1958 case UE_CONTROL: 1959 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1960 0, &epipe->u.ctl.reqdma); 1961 #ifdef EHCI_DEBUG 1962 if (err) 1963 printf("ehci_open: usb_allocmem()=%d\n", err); 1964 #endif 1965 if (err) 1966 goto bad; 1967 pipe->up_methods = &ehci_device_ctrl_methods; 1968 mutex_enter(&sc->sc_lock); 1969 ehci_add_qh(sc, sqh, sc->sc_async_head); 1970 mutex_exit(&sc->sc_lock); 1971 break; 1972 case UE_BULK: 1973 pipe->up_methods = &ehci_device_bulk_methods; 1974 mutex_enter(&sc->sc_lock); 1975 ehci_add_qh(sc, sqh, sc->sc_async_head); 1976 mutex_exit(&sc->sc_lock); 1977 break; 1978 case UE_INTERRUPT: 1979 pipe->up_methods = &ehci_device_intr_methods; 1980 ival = pipe->up_interval; 1981 if (ival == USBD_DEFAULT_INTERVAL) { 1982 if (speed == EHCI_QH_SPEED_HIGH) { 1983 if (ed->bInterval > 16) { 1984 /* 1985 * illegal with high-speed, but there 1986 * were documentation bugs in the spec, 1987 * so be generous 1988 */ 1989 ival = 256; 1990 } else 1991 ival = (1 << (ed->bInterval - 1)) / 8; 1992 } else 1993 ival = ed->bInterval; 1994 } 1995 err = ehci_device_setintr(sc, sqh, ival); 1996 if (err) 1997 goto bad; 1998 break; 1999 case UE_ISOCHRONOUS: 2000 if (speed == EHCI_QH_SPEED_HIGH) 2001 pipe->up_methods = &ehci_device_isoc_methods; 2002 else 2003 pipe->up_methods = &ehci_device_fs_isoc_methods; 2004 if (ed->bInterval == 0 || ed->bInterval > 16) { 2005 printf("ehci: opening pipe with invalid bInterval\n"); 2006 err = USBD_INVAL; 2007 goto bad; 2008 } 2009 if (UGETW(ed->wMaxPacketSize) == 0) { 2010 printf("ehci: zero length endpoint open request\n"); 2011 err = USBD_INVAL; 2012 goto bad; 2013 } 2014 epipe->u.isoc.next_frame = 0; 2015 epipe->u.isoc.cur_xfers = 0; 2016 break; 2017 default: 2018 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2019 err = USBD_INVAL; 2020 goto bad; 2021 } 2022 return (USBD_NORMAL_COMPLETION); 2023 2024 bad: 2025 if (sqh != NULL) 2026 ehci_free_sqh(sc, sqh); 2027 return (err); 2028 } 2029 2030 /* 2031 * Add an ED to the schedule. Called with USB lock held. 2032 */ 2033 Static void 2034 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2035 { 2036 2037 KASSERT(mutex_owned(&sc->sc_lock)); 2038 2039 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2040 2041 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2042 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2043 2044 sqh->next = head->next; 2045 sqh->qh.qh_link = head->qh.qh_link; 2046 2047 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2048 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2049 2050 head->next = sqh; 2051 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2052 2053 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2054 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2055 2056 #ifdef EHCI_DEBUG 2057 ehci_dump_sqh(sqh); 2058 #endif 2059 } 2060 2061 /* 2062 * Remove an ED from the schedule. Called with USB lock held. 2063 */ 2064 Static void 2065 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2066 { 2067 ehci_soft_qh_t *p; 2068 2069 KASSERT(mutex_owned(&sc->sc_lock)); 2070 2071 /* XXX */ 2072 for (p = head; p != NULL && p->next != sqh; p = p->next) 2073 ; 2074 if (p == NULL) 2075 panic("ehci_rem_qh: ED not found"); 2076 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2077 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2078 p->next = sqh->next; 2079 p->qh.qh_link = sqh->qh.qh_link; 2080 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2081 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2082 2083 ehci_sync_hc(sc); 2084 } 2085 2086 Static void 2087 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2088 { 2089 int i; 2090 uint32_t status; 2091 2092 /* Save toggle bit and ping status. */ 2093 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2094 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2095 status = sqh->qh.qh_qtd.qtd_status & 2096 htole32(EHCI_QTD_TOGGLE_MASK | 2097 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2098 /* Set HALTED to make hw leave it alone. */ 2099 sqh->qh.qh_qtd.qtd_status = 2100 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2101 usb_syncmem(&sqh->dma, 2102 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2103 sizeof(sqh->qh.qh_qtd.qtd_status), 2104 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2105 sqh->qh.qh_curqtd = 0; 2106 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2107 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2108 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2109 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2110 sqh->sqtd = sqtd; 2111 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2112 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2113 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2114 sqh->qh.qh_qtd.qtd_status = status; 2115 usb_syncmem(&sqh->dma, 2116 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2117 sizeof(sqh->qh.qh_qtd.qtd_status), 2118 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2119 } 2120 2121 /* 2122 * Ensure that the HC has released all references to the QH. We do this 2123 * by asking for a Async Advance Doorbell interrupt and then we wait for 2124 * the interrupt. 2125 * To make this easier we first obtain exclusive use of the doorbell. 2126 */ 2127 Static void 2128 ehci_sync_hc(ehci_softc_t *sc) 2129 { 2130 int error __diagused; 2131 2132 KASSERT(mutex_owned(&sc->sc_lock)); 2133 2134 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2135 2136 if (sc->sc_dying) { 2137 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2138 return; 2139 } 2140 /* ask for doorbell */ 2141 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2142 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2143 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2144 2145 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2146 2147 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2148 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2149 #ifdef DIAGNOSTIC 2150 if (error) 2151 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2152 #endif 2153 } 2154 2155 Static void 2156 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2157 { 2158 struct ehci_soft_itd *itd, *prev; 2159 2160 prev = NULL; 2161 2162 if (exfer->itdstart == NULL || exfer->itdend == NULL) 2163 panic("ehci isoc xfer being freed, but with no itd chain\n"); 2164 2165 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2166 prev = itd->u.frame_list.prev; 2167 /* Unlink itd from hardware chain, or frame array */ 2168 if (prev == NULL) { /* We're at the table head */ 2169 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2170 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2171 usb_syncmem(&sc->sc_fldma, 2172 sizeof(ehci_link_t) * itd->slot, 2173 sizeof(ehci_link_t), 2174 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2175 2176 if (itd->u.frame_list.next != NULL) 2177 itd->u.frame_list.next->u.frame_list.prev = NULL; 2178 } else { 2179 /* XXX this part is untested... */ 2180 prev->itd.itd_next = itd->itd.itd_next; 2181 usb_syncmem(&itd->dma, 2182 itd->offs + offsetof(ehci_itd_t, itd_next), 2183 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2184 2185 prev->u.frame_list.next = itd->u.frame_list.next; 2186 if (itd->u.frame_list.next != NULL) 2187 itd->u.frame_list.next->u.frame_list.prev = prev; 2188 } 2189 } 2190 2191 prev = NULL; 2192 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2193 if (prev != NULL) 2194 ehci_free_itd(sc, prev); 2195 prev = itd; 2196 } 2197 if (prev) 2198 ehci_free_itd(sc, prev); 2199 exfer->itdstart = NULL; 2200 exfer->itdend = NULL; 2201 } 2202 2203 Static void 2204 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2205 { 2206 struct ehci_soft_sitd *sitd, *prev; 2207 2208 prev = NULL; 2209 2210 if (exfer->sitdstart == NULL || exfer->sitdend == NULL) 2211 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2212 2213 for (sitd = exfer->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2214 prev = sitd->u.frame_list.prev; 2215 /* Unlink sitd from hardware chain, or frame array */ 2216 if (prev == NULL) { /* We're at the table head */ 2217 sc->sc_softsitds[sitd->slot] = sitd->u.frame_list.next; 2218 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2219 usb_syncmem(&sc->sc_fldma, 2220 sizeof(ehci_link_t) * sitd->slot, 2221 sizeof(ehci_link_t), 2222 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2223 2224 if (sitd->u.frame_list.next != NULL) 2225 sitd->u.frame_list.next->u.frame_list.prev = NULL; 2226 } else { 2227 /* XXX this part is untested... */ 2228 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2229 usb_syncmem(&sitd->dma, 2230 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2231 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2232 2233 prev->u.frame_list.next = sitd->u.frame_list.next; 2234 if (sitd->u.frame_list.next != NULL) 2235 sitd->u.frame_list.next->u.frame_list.prev = prev; 2236 } 2237 } 2238 2239 prev = NULL; 2240 for (sitd = exfer->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2241 if (prev != NULL) 2242 ehci_free_sitd(sc, prev); 2243 prev = sitd; 2244 } 2245 if (prev) 2246 ehci_free_sitd(sc, prev); 2247 exfer->sitdstart = NULL; 2248 exfer->sitdend = NULL; 2249 } 2250 2251 2252 /***********/ 2253 2254 /* 2255 * Data structures and routines to emulate the root hub. 2256 */ 2257 Static usb_device_descriptor_t ehci_devd = { 2258 .bLength = USB_DEVICE_DESCRIPTOR_SIZE, 2259 .bDescriptorType = UDESC_DEVICE, 2260 .bcdUSB = {0x00, 0x02}, 2261 .bDeviceClass = UDCLASS_HUB, 2262 .bDeviceSubClass = UDSUBCLASS_HUB, 2263 .bDeviceProtocol = UDPROTO_HSHUBSTT, 2264 .bMaxPacketSize = 64, 2265 .idVendor = {0}, 2266 .idProduct = {0}, 2267 .bcdDevice = {0x00,0x01}, 2268 .iManufacturer = 1, 2269 .iProduct = 2, 2270 .iSerialNumber = 0, 2271 .bNumConfigurations = 1 2272 }; 2273 2274 Static const usb_device_qualifier_t ehci_odevd = { 2275 .bLength = USB_DEVICE_DESCRIPTOR_SIZE, 2276 .bDescriptorType = UDESC_DEVICE_QUALIFIER, 2277 .bcdUSB = {0x00, 0x02}, 2278 .bDeviceClass = UDCLASS_HUB, 2279 .bDeviceSubClass = UDSUBCLASS_HUB, 2280 .bDeviceProtocol = UDPROTO_FSHUB, 2281 .bMaxPacketSize0 = 64, 2282 .bNumConfigurations = 1, 2283 0 2284 }; 2285 2286 Static const usb_config_descriptor_t ehci_confd = { 2287 .bLength = USB_CONFIG_DESCRIPTOR_SIZE, 2288 .bDescriptorType = UDESC_CONFIG, 2289 .wTotalLength = { 2290 USB_CONFIG_DESCRIPTOR_SIZE + 2291 USB_INTERFACE_DESCRIPTOR_SIZE + 2292 USB_ENDPOINT_DESCRIPTOR_SIZE 2293 }, 2294 .bNumInterface = 1, 2295 .bConfigurationValue = 1, 2296 .iConfiguration = 0, 2297 .bmAttributes = UC_ATTR_MBO | UC_SELF_POWERED, 2298 .bMaxPower = 0 2299 }; 2300 2301 Static const usb_interface_descriptor_t ehci_ifcd = { 2302 .bLength = USB_INTERFACE_DESCRIPTOR_SIZE, 2303 .bDescriptorType = UDESC_INTERFACE, 2304 .bInterfaceNumber = 0, 2305 .bAlternateSetting = 0, 2306 .bNumEndpoints = 1, 2307 .bInterfaceClass = UICLASS_HUB, 2308 .bInterfaceSubClass = UISUBCLASS_HUB, 2309 .bInterfaceProtocol = UIPROTO_HSHUBSTT, 2310 .iInterface = 0 2311 }; 2312 2313 Static const usb_endpoint_descriptor_t ehci_endpd = { 2314 .bLength = USB_ENDPOINT_DESCRIPTOR_SIZE, 2315 .bDescriptorType = UDESC_ENDPOINT, 2316 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT, 2317 .bmAttributes = UE_INTERRUPT, 2318 .wMaxPacketSize = {8, 0}, 2319 .bInterval = 12 2320 }; 2321 2322 Static const usb_hub_descriptor_t ehci_hubd = { 2323 .bDescLength = USB_HUB_DESCRIPTOR_SIZE, 2324 .bDescriptorType = UDESC_HUB, 2325 .bNbrPorts = 0, 2326 .wHubCharacteristics = {0,0}, 2327 .bPwrOn2PwrGood = 0, 2328 .bHubContrCurrent = 0, 2329 .DeviceRemovable = {""}, 2330 .PortPowerCtrlMask = {""}, 2331 }; 2332 2333 /* 2334 * Simulate a hardware hub by handling all the necessary requests. 2335 */ 2336 Static usbd_status 2337 ehci_root_ctrl_transfer(usbd_xfer_handle xfer) 2338 { 2339 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2340 usbd_status err; 2341 2342 /* Insert last in queue. */ 2343 mutex_enter(&sc->sc_lock); 2344 err = usb_insert_transfer(xfer); 2345 mutex_exit(&sc->sc_lock); 2346 if (err) 2347 return (err); 2348 2349 /* Pipe isn't running, start first */ 2350 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2351 } 2352 2353 Static usbd_status 2354 ehci_root_ctrl_start(usbd_xfer_handle xfer) 2355 { 2356 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2357 usb_device_request_t *req; 2358 void *buf = NULL; 2359 int port, i; 2360 int len, value, index, l, totlen = 0; 2361 usb_port_status_t ps; 2362 usb_hub_descriptor_t hubd; 2363 usbd_status err; 2364 uint32_t v; 2365 2366 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2367 2368 if (sc->sc_dying) 2369 return (USBD_IOERROR); 2370 2371 #ifdef DIAGNOSTIC 2372 if (!(xfer->ux_rqflags & URQ_REQUEST)) 2373 /* XXX panic */ 2374 return (USBD_INVAL); 2375 #endif 2376 req = &xfer->ux_request; 2377 2378 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2379 req->bmRequestType, req->bRequest, 0, 0); 2380 2381 len = UGETW(req->wLength); 2382 value = UGETW(req->wValue); 2383 index = UGETW(req->wIndex); 2384 2385 if (len != 0) 2386 buf = xfer->ux_buf; 2387 2388 #define C(x,y) ((x) | ((y) << 8)) 2389 switch(C(req->bRequest, req->bmRequestType)) { 2390 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2391 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2392 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2393 /* 2394 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2395 * for the integrated root hub. 2396 */ 2397 break; 2398 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2399 if (len > 0) { 2400 *(uint8_t *)buf = sc->sc_conf; 2401 totlen = 1; 2402 } 2403 break; 2404 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2405 USBHIST_LOG(ehcidebug, "wValue=0x%04x", value, 0, 0, 0); 2406 if (len == 0) 2407 break; 2408 switch(value >> 8) { 2409 case UDESC_DEVICE: 2410 if ((value & 0xff) != 0) { 2411 err = USBD_IOERROR; 2412 goto ret; 2413 } 2414 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2415 USETW(ehci_devd.idVendor, sc->sc_id_vendor); 2416 memcpy(buf, &ehci_devd, l); 2417 break; 2418 /* 2419 * We can't really operate at another speed, but the spec says 2420 * we need this descriptor. 2421 */ 2422 case UDESC_DEVICE_QUALIFIER: 2423 if ((value & 0xff) != 0) { 2424 err = USBD_IOERROR; 2425 goto ret; 2426 } 2427 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE); 2428 memcpy(buf, &ehci_odevd, l); 2429 break; 2430 /* 2431 * We can't really operate at another speed, but the spec says 2432 * we need this descriptor. 2433 */ 2434 case UDESC_OTHER_SPEED_CONFIGURATION: 2435 case UDESC_CONFIG: 2436 if ((value & 0xff) != 0) { 2437 err = USBD_IOERROR; 2438 goto ret; 2439 } 2440 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE); 2441 memcpy(buf, &ehci_confd, l); 2442 ((usb_config_descriptor_t *)buf)->bDescriptorType = 2443 value >> 8; 2444 buf = (char *)buf + l; 2445 len -= l; 2446 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE); 2447 totlen += l; 2448 memcpy(buf, &ehci_ifcd, l); 2449 buf = (char *)buf + l; 2450 len -= l; 2451 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE); 2452 totlen += l; 2453 memcpy(buf, &ehci_endpd, l); 2454 break; 2455 case UDESC_STRING: 2456 #define sd ((usb_string_descriptor_t *)buf) 2457 switch (value & 0xff) { 2458 case 0: /* Language table */ 2459 totlen = usb_makelangtbl(sd, len); 2460 break; 2461 case 1: /* Vendor */ 2462 totlen = usb_makestrdesc(sd, len, 2463 sc->sc_vendor); 2464 break; 2465 case 2: /* Product */ 2466 totlen = usb_makestrdesc(sd, len, 2467 "EHCI root hub"); 2468 break; 2469 } 2470 #undef sd 2471 break; 2472 default: 2473 err = USBD_IOERROR; 2474 goto ret; 2475 } 2476 break; 2477 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 2478 if (len > 0) { 2479 *(uint8_t *)buf = 0; 2480 totlen = 1; 2481 } 2482 break; 2483 case C(UR_GET_STATUS, UT_READ_DEVICE): 2484 if (len > 1) { 2485 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED); 2486 totlen = 2; 2487 } 2488 break; 2489 case C(UR_GET_STATUS, UT_READ_INTERFACE): 2490 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 2491 if (len > 1) { 2492 USETW(((usb_status_t *)buf)->wStatus, 0); 2493 totlen = 2; 2494 } 2495 break; 2496 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 2497 if (value >= USB_MAX_DEVICES) { 2498 err = USBD_IOERROR; 2499 goto ret; 2500 } 2501 sc->sc_addr = value; 2502 break; 2503 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 2504 if (value != 0 && value != 1) { 2505 err = USBD_IOERROR; 2506 goto ret; 2507 } 2508 sc->sc_conf = value; 2509 break; 2510 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 2511 break; 2512 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 2513 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 2514 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 2515 err = USBD_IOERROR; 2516 goto ret; 2517 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 2518 break; 2519 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 2520 break; 2521 /* Hub requests */ 2522 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2523 break; 2524 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2525 USBHIST_LOG(ehcidebug, 2526 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2527 0, 0); 2528 if (index < 1 || index > sc->sc_noport) { 2529 err = USBD_IOERROR; 2530 goto ret; 2531 } 2532 port = EHCI_PORTSC(index); 2533 v = EOREAD4(sc, port); 2534 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2535 v &= ~EHCI_PS_CLEAR; 2536 switch(value) { 2537 case UHF_PORT_ENABLE: 2538 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2539 break; 2540 case UHF_PORT_SUSPEND: 2541 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2542 break; 2543 v &= ~EHCI_PS_SUSP; 2544 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2545 /* see USB2 spec ch. 7.1.7.7 */ 2546 usb_delay_ms(&sc->sc_bus, 20); 2547 EOWRITE4(sc, port, v); 2548 usb_delay_ms(&sc->sc_bus, 2); 2549 #ifdef DEBUG 2550 v = EOREAD4(sc, port); 2551 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2552 printf("ehci: resume failed: %x\n", v); 2553 #endif 2554 break; 2555 case UHF_PORT_POWER: 2556 if (sc->sc_hasppc) 2557 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2558 break; 2559 case UHF_PORT_TEST: 2560 USBHIST_LOG(ehcidebug, "clear port test " 2561 "%d", index, 0, 0, 0); 2562 break; 2563 case UHF_PORT_INDICATOR: 2564 USBHIST_LOG(ehcidebug, "clear port ind " 2565 "%d", index, 0, 0, 0); 2566 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2567 break; 2568 case UHF_C_PORT_CONNECTION: 2569 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2570 break; 2571 case UHF_C_PORT_ENABLE: 2572 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2573 break; 2574 case UHF_C_PORT_SUSPEND: 2575 /* how? */ 2576 break; 2577 case UHF_C_PORT_OVER_CURRENT: 2578 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2579 break; 2580 case UHF_C_PORT_RESET: 2581 sc->sc_isreset[index] = 0; 2582 break; 2583 default: 2584 err = USBD_IOERROR; 2585 goto ret; 2586 } 2587 #if 0 2588 switch(value) { 2589 case UHF_C_PORT_CONNECTION: 2590 case UHF_C_PORT_ENABLE: 2591 case UHF_C_PORT_SUSPEND: 2592 case UHF_C_PORT_OVER_CURRENT: 2593 case UHF_C_PORT_RESET: 2594 default: 2595 break; 2596 } 2597 #endif 2598 break; 2599 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2600 if (len == 0) 2601 break; 2602 if ((value & 0xff) != 0) { 2603 err = USBD_IOERROR; 2604 goto ret; 2605 } 2606 hubd = ehci_hubd; 2607 hubd.bNbrPorts = sc->sc_noport; 2608 v = EOREAD4(sc, EHCI_HCSPARAMS); 2609 USETW(hubd.wHubCharacteristics, 2610 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2611 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2612 ? UHD_PORT_IND : 0); 2613 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2614 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2615 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2616 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2617 l = min(len, hubd.bDescLength); 2618 totlen = l; 2619 memcpy(buf, &hubd, l); 2620 break; 2621 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2622 if (len != 4) { 2623 err = USBD_IOERROR; 2624 goto ret; 2625 } 2626 memset(buf, 0, len); /* ? XXX */ 2627 totlen = len; 2628 break; 2629 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2630 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2631 if (index < 1 || index > sc->sc_noport) { 2632 err = USBD_IOERROR; 2633 goto ret; 2634 } 2635 if (len != 4) { 2636 err = USBD_IOERROR; 2637 goto ret; 2638 } 2639 v = EOREAD4(sc, EHCI_PORTSC(index)); 2640 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2641 2642 i = UPS_HIGH_SPEED; 2643 if (sc->sc_flags & EHCIF_ETTF) { 2644 /* 2645 * If we are doing embedded transaction translation, 2646 * then directly attached LS/FS devices are reset by 2647 * the EHCI controller itself. PSPD is encoded 2648 * the same way as in USBSTATUS. 2649 */ 2650 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2651 } 2652 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2653 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2654 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2655 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2656 if (v & EHCI_PS_PR) i |= UPS_RESET; 2657 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2658 if (sc->sc_vendor_port_status) 2659 i = sc->sc_vendor_port_status(sc, v, i); 2660 USETW(ps.wPortStatus, i); 2661 i = 0; 2662 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2663 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2664 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2665 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2666 USETW(ps.wPortChange, i); 2667 l = min(len, sizeof ps); 2668 memcpy(buf, &ps, l); 2669 totlen = l; 2670 break; 2671 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2672 err = USBD_IOERROR; 2673 goto ret; 2674 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2675 break; 2676 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2677 if (index < 1 || index > sc->sc_noport) { 2678 err = USBD_IOERROR; 2679 goto ret; 2680 } 2681 port = EHCI_PORTSC(index); 2682 v = EOREAD4(sc, port); 2683 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2684 v &= ~EHCI_PS_CLEAR; 2685 switch(value) { 2686 case UHF_PORT_ENABLE: 2687 EOWRITE4(sc, port, v | EHCI_PS_PE); 2688 break; 2689 case UHF_PORT_SUSPEND: 2690 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2691 break; 2692 case UHF_PORT_RESET: 2693 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2694 if (EHCI_PS_IS_LOWSPEED(v) 2695 && sc->sc_ncomp > 0 2696 && !(sc->sc_flags & EHCIF_ETTF)) { 2697 /* 2698 * Low speed device on non-ETTF controller or 2699 * unaccompanied controller, give up ownership. 2700 */ 2701 ehci_disown(sc, index, 1); 2702 break; 2703 } 2704 /* Start reset sequence. */ 2705 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2706 EOWRITE4(sc, port, v | EHCI_PS_PR); 2707 /* Wait for reset to complete. */ 2708 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2709 if (sc->sc_dying) { 2710 err = USBD_IOERROR; 2711 goto ret; 2712 } 2713 /* 2714 * An embedded transaction translator will automatically 2715 * terminate the reset sequence so there's no need to 2716 * it. 2717 */ 2718 v = EOREAD4(sc, port); 2719 if (v & EHCI_PS_PR) { 2720 /* Terminate reset sequence. */ 2721 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2722 /* Wait for HC to complete reset. */ 2723 usb_delay_ms(&sc->sc_bus, 2724 EHCI_PORT_RESET_COMPLETE); 2725 if (sc->sc_dying) { 2726 err = USBD_IOERROR; 2727 goto ret; 2728 } 2729 } 2730 2731 v = EOREAD4(sc, port); 2732 USBHIST_LOG(ehcidebug, 2733 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2734 if (v & EHCI_PS_PR) { 2735 printf("%s: port reset timeout\n", 2736 device_xname(sc->sc_dev)); 2737 return (USBD_TIMEOUT); 2738 } 2739 if (!(v & EHCI_PS_PE)) { 2740 /* Not a high speed device, give up ownership.*/ 2741 ehci_disown(sc, index, 0); 2742 break; 2743 } 2744 sc->sc_isreset[index] = 1; 2745 USBHIST_LOG(ehcidebug, 2746 "ehci port %d reset, status = 0x%08x", index, v, 0, 2747 0); 2748 break; 2749 case UHF_PORT_POWER: 2750 USBHIST_LOG(ehcidebug, 2751 "set port power %d (has PPC = %d)", index, 2752 sc->sc_hasppc, 0, 0); 2753 if (sc->sc_hasppc) 2754 EOWRITE4(sc, port, v | EHCI_PS_PP); 2755 break; 2756 case UHF_PORT_TEST: 2757 USBHIST_LOG(ehcidebug, "set port test %d", 2758 index, 0, 0, 0); 2759 break; 2760 case UHF_PORT_INDICATOR: 2761 USBHIST_LOG(ehcidebug, "set port ind %d", 2762 index, 0, 0, 0); 2763 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2764 break; 2765 default: 2766 err = USBD_IOERROR; 2767 goto ret; 2768 } 2769 break; 2770 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2771 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2772 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2773 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2774 break; 2775 default: 2776 err = USBD_IOERROR; 2777 goto ret; 2778 } 2779 xfer->ux_actlen = totlen; 2780 err = USBD_NORMAL_COMPLETION; 2781 ret: 2782 mutex_enter(&sc->sc_lock); 2783 xfer->ux_status = err; 2784 usb_transfer_complete(xfer); 2785 mutex_exit(&sc->sc_lock); 2786 return (USBD_IN_PROGRESS); 2787 } 2788 2789 Static void 2790 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2791 { 2792 int port; 2793 uint32_t v; 2794 2795 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2796 2797 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2798 #ifdef DIAGNOSTIC 2799 if (sc->sc_npcomp != 0) { 2800 int i = (index-1) / sc->sc_npcomp; 2801 if (i >= sc->sc_ncomp) 2802 printf("%s: strange port\n", 2803 device_xname(sc->sc_dev)); 2804 else 2805 printf("%s: handing over %s speed device on " 2806 "port %d to %s\n", 2807 device_xname(sc->sc_dev), 2808 lowspeed ? "low" : "full", 2809 index, device_xname(sc->sc_comps[i])); 2810 } else { 2811 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2812 } 2813 #endif 2814 port = EHCI_PORTSC(index); 2815 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2816 EOWRITE4(sc, port, v | EHCI_PS_PO); 2817 } 2818 2819 /* Abort a root control request. */ 2820 Static void 2821 ehci_root_ctrl_abort(usbd_xfer_handle xfer) 2822 { 2823 /* Nothing to do, all transfers are synchronous. */ 2824 } 2825 2826 /* Close the root pipe. */ 2827 Static void 2828 ehci_root_ctrl_close(usbd_pipe_handle pipe) 2829 { 2830 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2831 /* Nothing to do. */ 2832 } 2833 2834 Static void 2835 ehci_root_ctrl_done(usbd_xfer_handle xfer) 2836 { 2837 xfer->ux_hcpriv = NULL; 2838 } 2839 2840 Static usbd_status 2841 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2842 { 2843 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2844 usbd_status err; 2845 2846 /* Insert last in queue. */ 2847 mutex_enter(&sc->sc_lock); 2848 err = usb_insert_transfer(xfer); 2849 mutex_exit(&sc->sc_lock); 2850 if (err) 2851 return (err); 2852 2853 /* Pipe isn't running, start first */ 2854 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 2855 } 2856 2857 Static usbd_status 2858 ehci_root_intr_start(usbd_xfer_handle xfer) 2859 { 2860 usbd_pipe_handle pipe = xfer->ux_pipe; 2861 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2862 2863 if (sc->sc_dying) 2864 return (USBD_IOERROR); 2865 2866 mutex_enter(&sc->sc_lock); 2867 sc->sc_intrxfer = xfer; 2868 mutex_exit(&sc->sc_lock); 2869 2870 return (USBD_IN_PROGRESS); 2871 } 2872 2873 /* Abort a root interrupt request. */ 2874 Static void 2875 ehci_root_intr_abort(usbd_xfer_handle xfer) 2876 { 2877 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2878 2879 KASSERT(mutex_owned(&sc->sc_lock)); 2880 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2881 2882 sc->sc_intrxfer = NULL; 2883 2884 xfer->ux_status = USBD_CANCELLED; 2885 usb_transfer_complete(xfer); 2886 } 2887 2888 /* Close the root pipe. */ 2889 Static void 2890 ehci_root_intr_close(usbd_pipe_handle pipe) 2891 { 2892 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2893 2894 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2895 2896 KASSERT(mutex_owned(&sc->sc_lock)); 2897 2898 sc->sc_intrxfer = NULL; 2899 } 2900 2901 Static void 2902 ehci_root_intr_done(usbd_xfer_handle xfer) 2903 { 2904 xfer->ux_hcpriv = NULL; 2905 } 2906 2907 /************************/ 2908 2909 Static ehci_soft_qh_t * 2910 ehci_alloc_sqh(ehci_softc_t *sc) 2911 { 2912 ehci_soft_qh_t *sqh; 2913 usbd_status err; 2914 int i, offs; 2915 usb_dma_t dma; 2916 2917 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2918 2919 if (sc->sc_freeqhs == NULL) { 2920 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2921 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2922 EHCI_PAGE_SIZE, &dma); 2923 #ifdef EHCI_DEBUG 2924 if (err) 2925 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2926 #endif 2927 if (err) 2928 return (NULL); 2929 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2930 offs = i * EHCI_SQH_SIZE; 2931 sqh = KERNADDR(&dma, offs); 2932 sqh->physaddr = DMAADDR(&dma, offs); 2933 sqh->dma = dma; 2934 sqh->offs = offs; 2935 sqh->next = sc->sc_freeqhs; 2936 sc->sc_freeqhs = sqh; 2937 } 2938 } 2939 sqh = sc->sc_freeqhs; 2940 sc->sc_freeqhs = sqh->next; 2941 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2942 sqh->next = NULL; 2943 return (sqh); 2944 } 2945 2946 Static void 2947 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2948 { 2949 sqh->next = sc->sc_freeqhs; 2950 sc->sc_freeqhs = sqh; 2951 } 2952 2953 Static ehci_soft_qtd_t * 2954 ehci_alloc_sqtd(ehci_softc_t *sc) 2955 { 2956 ehci_soft_qtd_t *sqtd = NULL; 2957 usbd_status err; 2958 int i, offs; 2959 usb_dma_t dma; 2960 2961 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2962 2963 if (sc->sc_freeqtds == NULL) { 2964 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2965 2966 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2967 EHCI_PAGE_SIZE, &dma); 2968 #ifdef EHCI_DEBUG 2969 if (err) 2970 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2971 #endif 2972 if (err) 2973 goto done; 2974 2975 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2976 offs = i * EHCI_SQTD_SIZE; 2977 sqtd = KERNADDR(&dma, offs); 2978 sqtd->physaddr = DMAADDR(&dma, offs); 2979 sqtd->dma = dma; 2980 sqtd->offs = offs; 2981 2982 sqtd->nextqtd = sc->sc_freeqtds; 2983 sc->sc_freeqtds = sqtd; 2984 } 2985 } 2986 2987 sqtd = sc->sc_freeqtds; 2988 sc->sc_freeqtds = sqtd->nextqtd; 2989 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2990 sqtd->nextqtd = NULL; 2991 sqtd->xfer = NULL; 2992 2993 done: 2994 return (sqtd); 2995 } 2996 2997 Static void 2998 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2999 { 3000 3001 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3002 3003 sqtd->nextqtd = sc->sc_freeqtds; 3004 sc->sc_freeqtds = sqtd; 3005 } 3006 3007 Static usbd_status 3008 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 3009 int alen, int rd, usbd_xfer_handle xfer, 3010 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 3011 { 3012 ehci_soft_qtd_t *next, *cur; 3013 ehci_physaddr_t nextphys; 3014 uint32_t qtdstatus; 3015 int len, curlen, mps; 3016 int i, tog; 3017 int pages, pageoffs; 3018 bus_size_t curoffs; 3019 vaddr_t va, va_offs; 3020 usb_dma_t *dma = &xfer->ux_dmabuf; 3021 uint16_t flags = xfer->ux_flags; 3022 paddr_t a; 3023 3024 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3025 3026 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 3027 3028 len = alen; 3029 qtdstatus = EHCI_QTD_ACTIVE | 3030 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 3031 EHCI_QTD_SET_CERR(3) 3032 /* IOC set below */ 3033 /* BYTES set below */ 3034 ; 3035 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 3036 tog = epipe->nexttoggle; 3037 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 3038 3039 cur = ehci_alloc_sqtd(sc); 3040 *sp = cur; 3041 if (cur == NULL) 3042 goto nomem; 3043 3044 usb_syncmem(dma, 0, alen, 3045 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3046 curoffs = 0; 3047 for (;;) { 3048 /* The EHCI hardware can handle at most 5 pages. */ 3049 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 3050 va_offs = EHCI_PAGE_OFFSET(va_offs); 3051 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 3052 /* we can handle it in this QTD */ 3053 curlen = len - curoffs; 3054 } else { 3055 /* must use multiple TDs, fill as much as possible. */ 3056 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 3057 3058 /* the length must be a multiple of the max size */ 3059 curlen -= curlen % mps; 3060 USBHIST_LOG(ehcidebug, "multiple QTDs, " 3061 "curlen=%d", curlen, 0, 0, 0); 3062 #ifdef DIAGNOSTIC 3063 if (curlen == 0) 3064 panic("ehci_alloc_sqtd_chain: curlen == 0"); 3065 #endif 3066 } 3067 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 3068 len, curlen, (size_t)curoffs, 0); 3069 3070 /* 3071 * Allocate another transfer if there's more data left, 3072 * or if force last short transfer flag is set and we're 3073 * allocating a multiple of the max packet size. 3074 */ 3075 3076 if (curoffs + curlen != len || 3077 ((curlen % mps) == 0 && !rd && curlen != 0 && 3078 (flags & USBD_FORCE_SHORT_XFER))) { 3079 next = ehci_alloc_sqtd(sc); 3080 if (next == NULL) 3081 goto nomem; 3082 nextphys = htole32(next->physaddr); 3083 } else { 3084 next = NULL; 3085 nextphys = EHCI_NULL; 3086 } 3087 3088 /* Find number of pages we'll be using, insert dma addresses */ 3089 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 3090 KASSERT(pages <= EHCI_QTD_NBUFFERS); 3091 pageoffs = EHCI_PAGE(curoffs); 3092 for (i = 0; i < pages; i++) { 3093 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 3094 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 3095 /* Cast up to avoid compiler warnings */ 3096 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 3097 } 3098 3099 /* First buffer pointer requires a page offset to start at */ 3100 va = (vaddr_t)KERNADDR(dma, curoffs); 3101 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 3102 3103 cur->nextqtd = next; 3104 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 3105 cur->qtd.qtd_status = 3106 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 3107 cur->xfer = xfer; 3108 cur->len = curlen; 3109 3110 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 3111 (size_t)curoffs, (size_t)(curoffs + curlen), 0, 0); 3112 3113 /* adjust the toggle based on the number of packets in this 3114 qtd */ 3115 if (((curlen + mps - 1) / mps) & 1) { 3116 tog ^= 1; 3117 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 3118 } 3119 if (next == NULL) 3120 break; 3121 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 3122 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3123 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 3124 if (len) 3125 curoffs += curlen; 3126 cur = next; 3127 } 3128 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3129 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 3130 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3131 *ep = cur; 3132 epipe->nexttoggle = tog; 3133 3134 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 3135 *sp, *ep, 0, 0); 3136 3137 return (USBD_NORMAL_COMPLETION); 3138 3139 nomem: 3140 /* XXX free chain */ 3141 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3142 return (USBD_NOMEM); 3143 } 3144 3145 Static void 3146 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 3147 ehci_soft_qtd_t *sqtdend) 3148 { 3149 ehci_soft_qtd_t *p; 3150 int i; 3151 3152 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3153 3154 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 3155 sqtd, sqtdend, 0, 0); 3156 3157 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 3158 p = sqtd->nextqtd; 3159 ehci_free_sqtd(sc, sqtd); 3160 } 3161 } 3162 3163 Static ehci_soft_itd_t * 3164 ehci_alloc_itd(ehci_softc_t *sc) 3165 { 3166 struct ehci_soft_itd *itd, *freeitd; 3167 usbd_status err; 3168 int i, offs, frindex, previndex; 3169 usb_dma_t dma; 3170 3171 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3172 3173 mutex_enter(&sc->sc_lock); 3174 3175 /* Find an itd that wasn't freed this frame or last frame. This can 3176 * discard itds that were freed before frindex wrapped around 3177 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3178 * interrupt and fiddling with list when that happens */ 3179 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3180 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3181 3182 freeitd = NULL; 3183 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 3184 if (itd == NULL) 3185 break; 3186 if (itd->slot != frindex && itd->slot != previndex) { 3187 freeitd = itd; 3188 break; 3189 } 3190 } 3191 3192 if (freeitd == NULL) { 3193 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3194 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3195 EHCI_PAGE_SIZE, &dma); 3196 3197 if (err) { 3198 USBHIST_LOG(ehcidebug, 3199 "alloc returned %d", err, 0, 0, 0); 3200 mutex_exit(&sc->sc_lock); 3201 return NULL; 3202 } 3203 3204 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 3205 offs = i * EHCI_ITD_SIZE; 3206 itd = KERNADDR(&dma, offs); 3207 itd->physaddr = DMAADDR(&dma, offs); 3208 itd->dma = dma; 3209 itd->offs = offs; 3210 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3211 } 3212 freeitd = LIST_FIRST(&sc->sc_freeitds); 3213 } 3214 3215 itd = freeitd; 3216 LIST_REMOVE(itd, u.free_list); 3217 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3218 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 3219 sizeof(itd->itd.itd_next), 3220 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3221 3222 itd->u.frame_list.next = NULL; 3223 itd->u.frame_list.prev = NULL; 3224 itd->xfer_next = NULL; 3225 itd->slot = 0; 3226 3227 mutex_exit(&sc->sc_lock); 3228 3229 return itd; 3230 } 3231 3232 Static ehci_soft_sitd_t * 3233 ehci_alloc_sitd(ehci_softc_t *sc) 3234 { 3235 struct ehci_soft_sitd *sitd, *freesitd; 3236 usbd_status err; 3237 int i, offs, frindex, previndex; 3238 usb_dma_t dma; 3239 3240 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3241 3242 mutex_enter(&sc->sc_lock); 3243 3244 /* Find an sitd that wasn't freed this frame or last frame. This can 3245 * discard sitds that were freed before frindex wrapped around 3246 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3247 * interrupt and fiddling with list when that happens */ 3248 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3249 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3250 3251 freesitd = NULL; 3252 LIST_FOREACH(sitd, &sc->sc_freesitds, u.free_list) { 3253 if (sitd == NULL) 3254 break; 3255 if (sitd->slot != frindex && sitd->slot != previndex) { 3256 freesitd = sitd; 3257 break; 3258 } 3259 } 3260 3261 if (freesitd == NULL) { 3262 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3263 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3264 EHCI_PAGE_SIZE, &dma); 3265 3266 if (err) { 3267 USBHIST_LOG(ehcidebug, 3268 "alloc returned %d", err, 0, 0, 0); 3269 mutex_exit(&sc->sc_lock); 3270 return NULL; 3271 } 3272 3273 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3274 offs = i * EHCI_SITD_SIZE; 3275 sitd = KERNADDR(&dma, offs); 3276 sitd->physaddr = DMAADDR(&dma, offs); 3277 sitd->dma = dma; 3278 sitd->offs = offs; 3279 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3280 } 3281 freesitd = LIST_FIRST(&sc->sc_freesitds); 3282 } 3283 3284 sitd = freesitd; 3285 LIST_REMOVE(sitd, u.free_list); 3286 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3287 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3288 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3289 BUS_DMASYNC_PREREAD); 3290 3291 sitd->u.frame_list.next = NULL; 3292 sitd->u.frame_list.prev = NULL; 3293 sitd->xfer_next = NULL; 3294 sitd->slot = 0; 3295 3296 mutex_exit(&sc->sc_lock); 3297 3298 return sitd; 3299 } 3300 3301 Static void 3302 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3303 { 3304 3305 KASSERT(mutex_owned(&sc->sc_lock)); 3306 3307 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3308 } 3309 3310 Static void 3311 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3312 { 3313 3314 KASSERT(mutex_owned(&sc->sc_lock)); 3315 3316 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3317 } 3318 3319 /****************/ 3320 3321 /* 3322 * Close a reqular pipe. 3323 * Assumes that there are no pending transactions. 3324 */ 3325 Static void 3326 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3327 { 3328 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3329 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3330 ehci_soft_qh_t *sqh = epipe->sqh; 3331 3332 KASSERT(mutex_owned(&sc->sc_lock)); 3333 3334 ehci_rem_qh(sc, sqh, head); 3335 ehci_free_sqh(sc, epipe->sqh); 3336 } 3337 3338 /* 3339 * Abort a device request. 3340 * If this routine is called at splusb() it guarantees that the request 3341 * will be removed from the hardware scheduling and that the callback 3342 * for it will be called with USBD_CANCELLED status. 3343 * It's impossible to guarantee that the requested transfer will not 3344 * have happened since the hardware runs concurrently. 3345 * If the transaction has already happened we rely on the ordinary 3346 * interrupt processing to process it. 3347 * XXX This is most probably wrong. 3348 * XXXMRG this doesn't make sense anymore. 3349 */ 3350 Static void 3351 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3352 { 3353 #define exfer EXFER(xfer) 3354 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3355 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3356 ehci_soft_qh_t *sqh = epipe->sqh; 3357 ehci_soft_qtd_t *sqtd; 3358 ehci_physaddr_t cur; 3359 uint32_t qhstatus; 3360 int hit; 3361 int wake; 3362 3363 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3364 3365 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3366 3367 KASSERT(mutex_owned(&sc->sc_lock)); 3368 ASSERT_SLEEPABLE(); 3369 3370 if (sc->sc_dying) { 3371 /* If we're dying, just do the software part. */ 3372 xfer->ux_status = status; /* make software ignore it */ 3373 callout_stop(&xfer->ux_callout); 3374 usb_transfer_complete(xfer); 3375 return; 3376 } 3377 3378 /* 3379 * If an abort is already in progress then just wait for it to 3380 * complete and return. 3381 */ 3382 if (xfer->ux_hcflags & UXFER_ABORTING) { 3383 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3384 #ifdef DIAGNOSTIC 3385 if (status == USBD_TIMEOUT) 3386 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3387 #endif 3388 /* Override the status which might be USBD_TIMEOUT. */ 3389 xfer->ux_status = status; 3390 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3391 0, 0, 0, 0); 3392 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3393 while (xfer->ux_hcflags & UXFER_ABORTING) 3394 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3395 return; 3396 } 3397 xfer->ux_hcflags |= UXFER_ABORTING; 3398 3399 /* 3400 * Step 1: Make interrupt routine and hardware ignore xfer. 3401 */ 3402 xfer->ux_status = status; /* make software ignore it */ 3403 callout_stop(&xfer->ux_callout); 3404 3405 usb_syncmem(&sqh->dma, 3406 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3407 sizeof(sqh->qh.qh_qtd.qtd_status), 3408 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3409 qhstatus = sqh->qh.qh_qtd.qtd_status; 3410 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3411 usb_syncmem(&sqh->dma, 3412 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3413 sizeof(sqh->qh.qh_qtd.qtd_status), 3414 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3415 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3416 usb_syncmem(&sqtd->dma, 3417 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3418 sizeof(sqtd->qtd.qtd_status), 3419 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3420 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3421 usb_syncmem(&sqtd->dma, 3422 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3423 sizeof(sqtd->qtd.qtd_status), 3424 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3425 if (sqtd == exfer->sqtdend) 3426 break; 3427 } 3428 3429 /* 3430 * Step 2: Wait until we know hardware has finished any possible 3431 * use of the xfer. Also make sure the soft interrupt routine 3432 * has run. 3433 */ 3434 ehci_sync_hc(sc); 3435 sc->sc_softwake = 1; 3436 usb_schedsoftintr(&sc->sc_bus); 3437 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3438 3439 /* 3440 * Step 3: Remove any vestiges of the xfer from the hardware. 3441 * The complication here is that the hardware may have executed 3442 * beyond the xfer we're trying to abort. So as we're scanning 3443 * the TDs of this xfer we check if the hardware points to 3444 * any of them. 3445 */ 3446 3447 usb_syncmem(&sqh->dma, 3448 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3449 sizeof(sqh->qh.qh_curqtd), 3450 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3451 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3452 hit = 0; 3453 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3454 hit |= cur == sqtd->physaddr; 3455 if (sqtd == exfer->sqtdend) 3456 break; 3457 } 3458 sqtd = sqtd->nextqtd; 3459 /* Zap curqtd register if hardware pointed inside the xfer. */ 3460 if (hit && sqtd != NULL) { 3461 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3462 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3463 usb_syncmem(&sqh->dma, 3464 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3465 sizeof(sqh->qh.qh_curqtd), 3466 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3467 sqh->qh.qh_qtd.qtd_status = qhstatus; 3468 usb_syncmem(&sqh->dma, 3469 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3470 sizeof(sqh->qh.qh_qtd.qtd_status), 3471 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3472 } else { 3473 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3474 } 3475 3476 /* 3477 * Step 4: Execute callback. 3478 */ 3479 #ifdef DIAGNOSTIC 3480 exfer->isdone = 1; 3481 #endif 3482 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3483 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3484 usb_transfer_complete(xfer); 3485 if (wake) { 3486 cv_broadcast(&xfer->ux_hccv); 3487 } 3488 3489 KASSERT(mutex_owned(&sc->sc_lock)); 3490 #undef exfer 3491 } 3492 3493 Static void 3494 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3495 { 3496 ehci_isoc_trans_t trans_status; 3497 struct ehci_pipe *epipe; 3498 struct ehci_xfer *exfer; 3499 ehci_softc_t *sc; 3500 struct ehci_soft_itd *itd; 3501 struct ehci_soft_sitd *sitd; 3502 int i, wake; 3503 3504 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3505 3506 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3507 exfer = EXFER(xfer); 3508 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3509 3510 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3511 3512 KASSERT(mutex_owned(&sc->sc_lock)); 3513 3514 if (sc->sc_dying) { 3515 xfer->ux_status = status; 3516 callout_stop(&xfer->ux_callout); 3517 usb_transfer_complete(xfer); 3518 return; 3519 } 3520 3521 if (xfer->ux_hcflags & UXFER_ABORTING) { 3522 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3523 3524 #ifdef DIAGNOSTIC 3525 if (status == USBD_TIMEOUT) 3526 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3527 #endif 3528 3529 xfer->ux_status = status; 3530 USBHIST_LOG(ehcidebug, 3531 "waiting for abort to finish", 0, 0, 0, 0); 3532 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3533 while (xfer->ux_hcflags & UXFER_ABORTING) 3534 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3535 goto done; 3536 } 3537 xfer->ux_hcflags |= UXFER_ABORTING; 3538 3539 xfer->ux_status = status; 3540 callout_stop(&xfer->ux_callout); 3541 3542 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3543 usb_syncmem(&itd->dma, 3544 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3545 sizeof(itd->itd.itd_ctl), 3546 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3547 3548 for (i = 0; i < 8; i++) { 3549 trans_status = le32toh(itd->itd.itd_ctl[i]); 3550 trans_status &= ~EHCI_ITD_ACTIVE; 3551 itd->itd.itd_ctl[i] = htole32(trans_status); 3552 } 3553 3554 usb_syncmem(&itd->dma, 3555 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3556 sizeof(itd->itd.itd_ctl), 3557 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3558 } 3559 for (sitd = exfer->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 3560 usb_syncmem(&sitd->dma, 3561 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3562 sizeof(sitd->sitd.sitd_buffer), 3563 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3564 3565 trans_status = le32toh(sitd->sitd.sitd_trans); 3566 trans_status &= ~EHCI_SITD_ACTIVE; 3567 sitd->sitd.sitd_trans = htole32(trans_status); 3568 3569 usb_syncmem(&sitd->dma, 3570 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3571 sizeof(sitd->sitd.sitd_buffer), 3572 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3573 } 3574 3575 sc->sc_softwake = 1; 3576 usb_schedsoftintr(&sc->sc_bus); 3577 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3578 3579 #ifdef DIAGNOSTIC 3580 exfer->isdone = 1; 3581 #endif 3582 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3583 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3584 usb_transfer_complete(xfer); 3585 if (wake) { 3586 cv_broadcast(&xfer->ux_hccv); 3587 } 3588 3589 done: 3590 KASSERT(mutex_owned(&sc->sc_lock)); 3591 return; 3592 } 3593 3594 Static void 3595 ehci_timeout(void *addr) 3596 { 3597 struct ehci_xfer *exfer = addr; 3598 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.ux_pipe; 3599 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3600 3601 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3602 3603 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3604 #ifdef EHCI_DEBUG 3605 if (ehcidebug > 1) 3606 usbd_dump_pipe(exfer->xfer.ux_pipe); 3607 #endif 3608 3609 if (sc->sc_dying) { 3610 mutex_enter(&sc->sc_lock); 3611 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3612 mutex_exit(&sc->sc_lock); 3613 return; 3614 } 3615 3616 /* Execute the abort in a process context. */ 3617 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr, 3618 USB_TASKQ_MPSAFE); 3619 usb_add_task(exfer->xfer.ux_pipe->up_dev, &exfer->abort_task, 3620 USB_TASKQ_HC); 3621 } 3622 3623 Static void 3624 ehci_timeout_task(void *addr) 3625 { 3626 usbd_xfer_handle xfer = addr; 3627 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3628 3629 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3630 3631 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3632 3633 mutex_enter(&sc->sc_lock); 3634 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3635 mutex_exit(&sc->sc_lock); 3636 } 3637 3638 /************************/ 3639 3640 Static usbd_status 3641 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3642 { 3643 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3644 usbd_status err; 3645 3646 /* Insert last in queue. */ 3647 mutex_enter(&sc->sc_lock); 3648 err = usb_insert_transfer(xfer); 3649 mutex_exit(&sc->sc_lock); 3650 if (err) 3651 return (err); 3652 3653 /* Pipe isn't running, start first */ 3654 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 3655 } 3656 3657 Static usbd_status 3658 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3659 { 3660 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3661 usbd_status err; 3662 3663 if (sc->sc_dying) 3664 return (USBD_IOERROR); 3665 3666 #ifdef DIAGNOSTIC 3667 if (!(xfer->ux_rqflags & URQ_REQUEST)) { 3668 /* XXX panic */ 3669 printf("ehci_device_ctrl_transfer: not a request\n"); 3670 return (USBD_INVAL); 3671 } 3672 #endif 3673 3674 err = ehci_device_request(xfer); 3675 if (err) { 3676 return (err); 3677 } 3678 3679 if (sc->sc_bus.ub_usepolling) 3680 ehci_waitintr(sc, xfer); 3681 3682 return (USBD_IN_PROGRESS); 3683 } 3684 3685 Static void 3686 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3687 { 3688 struct ehci_xfer *ex = EXFER(xfer); 3689 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3690 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3691 usb_device_request_t *req = &xfer->ux_request; 3692 int len = UGETW(req->wLength); 3693 int rd = req->bmRequestType & UT_READ; 3694 3695 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3696 3697 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3698 3699 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3700 3701 #ifdef DIAGNOSTIC 3702 if (!(xfer->ux_rqflags & URQ_REQUEST)) { 3703 panic("ehci_ctrl_done: not a request"); 3704 } 3705 #endif 3706 3707 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3708 ehci_del_intr_list(sc, ex); /* remove from active list */ 3709 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3710 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3711 BUS_DMASYNC_POSTWRITE); 3712 if (len) 3713 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3714 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3715 } 3716 3717 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3718 } 3719 3720 /* Abort a device control request. */ 3721 Static void 3722 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3723 { 3724 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3725 3726 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3727 ehci_abort_xfer(xfer, USBD_CANCELLED); 3728 } 3729 3730 /* Close a device control pipe. */ 3731 Static void 3732 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3733 { 3734 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3735 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3736 3737 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3738 3739 KASSERT(mutex_owned(&sc->sc_lock)); 3740 3741 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3742 3743 ehci_close_pipe(pipe, sc->sc_async_head); 3744 } 3745 3746 Static usbd_status 3747 ehci_device_request(usbd_xfer_handle xfer) 3748 { 3749 #define exfer EXFER(xfer) 3750 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3751 usb_device_request_t *req = &xfer->ux_request; 3752 usbd_device_handle dev = epipe->pipe.up_dev; 3753 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3754 ehci_soft_qtd_t *setup, *stat, *next; 3755 ehci_soft_qh_t *sqh; 3756 int isread; 3757 int len; 3758 usbd_status err; 3759 3760 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3761 3762 isread = req->bmRequestType & UT_READ; 3763 len = UGETW(req->wLength); 3764 3765 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3766 "wValue=0x%04x, wIndex=0x%04x", 3767 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3768 UGETW(req->wIndex)); 3769 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3770 len, dev->ud_addr, 3771 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3772 3773 setup = ehci_alloc_sqtd(sc); 3774 if (setup == NULL) { 3775 err = USBD_NOMEM; 3776 goto bad1; 3777 } 3778 stat = ehci_alloc_sqtd(sc); 3779 if (stat == NULL) { 3780 err = USBD_NOMEM; 3781 goto bad2; 3782 } 3783 3784 mutex_enter(&sc->sc_lock); 3785 3786 sqh = epipe->sqh; 3787 3788 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3789 "address QH %d pipe %d\n", 3790 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3791 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3792 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3793 "MPS QH %d pipe %d\n", 3794 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3795 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3796 3797 /* Set up data transaction */ 3798 if (len != 0) { 3799 ehci_soft_qtd_t *end; 3800 3801 /* Start toggle at 1. */ 3802 epipe->nexttoggle = 1; 3803 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3804 &next, &end); 3805 if (err) 3806 goto bad3; 3807 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3808 end->nextqtd = stat; 3809 end->qtd.qtd_next = end->qtd.qtd_altnext = 3810 htole32(stat->physaddr); 3811 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3812 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3813 } else { 3814 next = stat; 3815 } 3816 3817 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3818 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3819 3820 /* Clear toggle */ 3821 setup->qtd.qtd_status = htole32( 3822 EHCI_QTD_ACTIVE | 3823 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3824 EHCI_QTD_SET_CERR(3) | 3825 EHCI_QTD_SET_TOGGLE(0) | 3826 EHCI_QTD_SET_BYTES(sizeof *req) 3827 ); 3828 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3829 setup->qtd.qtd_buffer_hi[0] = 0; 3830 setup->nextqtd = next; 3831 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3832 setup->xfer = xfer; 3833 setup->len = sizeof *req; 3834 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3835 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3836 3837 stat->qtd.qtd_status = htole32( 3838 EHCI_QTD_ACTIVE | 3839 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3840 EHCI_QTD_SET_CERR(3) | 3841 EHCI_QTD_SET_TOGGLE(1) | 3842 EHCI_QTD_IOC 3843 ); 3844 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3845 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3846 stat->nextqtd = NULL; 3847 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3848 stat->xfer = xfer; 3849 stat->len = 0; 3850 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3851 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3852 3853 #ifdef EHCI_DEBUG 3854 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3855 ehci_dump_sqh(sqh); 3856 ehci_dump_sqtds(setup); 3857 #endif 3858 3859 exfer->sqtdstart = setup; 3860 exfer->sqtdend = stat; 3861 #ifdef DIAGNOSTIC 3862 if (!exfer->isdone) { 3863 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3864 } 3865 exfer->isdone = 0; 3866 #endif 3867 3868 /* Insert qTD in QH list. */ 3869 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3870 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3871 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3872 ehci_timeout, xfer); 3873 } 3874 ehci_add_intr_list(sc, exfer); 3875 xfer->ux_status = USBD_IN_PROGRESS; 3876 mutex_exit(&sc->sc_lock); 3877 3878 #ifdef EHCI_DEBUG 3879 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3880 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3881 // delay(10000); 3882 ehci_dump_regs(sc); 3883 ehci_dump_sqh(sc->sc_async_head); 3884 ehci_dump_sqh(sqh); 3885 ehci_dump_sqtds(setup); 3886 #endif 3887 3888 return (USBD_NORMAL_COMPLETION); 3889 3890 bad3: 3891 mutex_exit(&sc->sc_lock); 3892 ehci_free_sqtd(sc, stat); 3893 bad2: 3894 ehci_free_sqtd(sc, setup); 3895 bad1: 3896 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3897 mutex_enter(&sc->sc_lock); 3898 xfer->ux_status = err; 3899 usb_transfer_complete(xfer); 3900 mutex_exit(&sc->sc_lock); 3901 return (err); 3902 #undef exfer 3903 } 3904 3905 /* 3906 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3907 * qTD status, or miss signalling occasionally under heavy load. If the host 3908 * machine is too fast, we we can miss transaction completion - when we scan 3909 * the active list the transaction still seems to be active. This generally 3910 * exhibits itself as a umass stall that never recovers. 3911 * 3912 * We work around this behaviour by setting up this callback after any softintr 3913 * that completes with transactions still pending, giving us another chance to 3914 * check for completion after the writeback has taken place. 3915 */ 3916 Static void 3917 ehci_intrlist_timeout(void *arg) 3918 { 3919 ehci_softc_t *sc = arg; 3920 3921 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3922 3923 usb_schedsoftintr(&sc->sc_bus); 3924 } 3925 3926 /************************/ 3927 3928 Static usbd_status 3929 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3930 { 3931 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3932 usbd_status err; 3933 3934 /* Insert last in queue. */ 3935 mutex_enter(&sc->sc_lock); 3936 err = usb_insert_transfer(xfer); 3937 mutex_exit(&sc->sc_lock); 3938 if (err) 3939 return (err); 3940 3941 /* Pipe isn't running, start first */ 3942 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 3943 } 3944 3945 Static usbd_status 3946 ehci_device_bulk_start(usbd_xfer_handle xfer) 3947 { 3948 #define exfer EXFER(xfer) 3949 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3950 usbd_device_handle dev = epipe->pipe.up_dev; 3951 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3952 ehci_soft_qtd_t *data, *dataend; 3953 ehci_soft_qh_t *sqh; 3954 usbd_status err; 3955 int len, isread, endpt; 3956 3957 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3958 3959 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3960 xfer, xfer->ux_length, xfer->ux_flags, 0); 3961 3962 if (sc->sc_dying) 3963 return (USBD_IOERROR); 3964 3965 #ifdef DIAGNOSTIC 3966 if (xfer->ux_rqflags & URQ_REQUEST) 3967 panic("ehci_device_bulk_start: a request"); 3968 #endif 3969 3970 mutex_enter(&sc->sc_lock); 3971 3972 len = xfer->ux_length; 3973 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3974 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3975 sqh = epipe->sqh; 3976 3977 epipe->u.bulk.length = len; 3978 3979 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3980 &dataend); 3981 if (err) { 3982 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3983 xfer->ux_status = err; 3984 usb_transfer_complete(xfer); 3985 mutex_exit(&sc->sc_lock); 3986 return (err); 3987 } 3988 3989 #ifdef EHCI_DEBUG 3990 USBHIST_LOGN(ehcidebug, 5, "data(1):", 0, 0, 0, 0); 3991 ehci_dump_sqh(sqh); 3992 ehci_dump_sqtds(data); 3993 #endif 3994 3995 /* Set up interrupt info. */ 3996 exfer->sqtdstart = data; 3997 exfer->sqtdend = dataend; 3998 #ifdef DIAGNOSTIC 3999 if (!exfer->isdone) { 4000 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 4001 } 4002 exfer->isdone = 0; 4003 #endif 4004 4005 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4006 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4007 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4008 ehci_timeout, xfer); 4009 } 4010 ehci_add_intr_list(sc, exfer); 4011 xfer->ux_status = USBD_IN_PROGRESS; 4012 mutex_exit(&sc->sc_lock); 4013 4014 #ifdef EHCI_DEBUG 4015 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 4016 // delay(10000); 4017 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 4018 ehci_dump_regs(sc); 4019 #if 0 4020 printf("async_head:\n"); 4021 ehci_dump_sqh(sc->sc_async_head); 4022 #endif 4023 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 4024 ehci_dump_sqh(sqh); 4025 ehci_dump_sqtds(data); 4026 #endif 4027 4028 if (sc->sc_bus.ub_usepolling) 4029 ehci_waitintr(sc, xfer); 4030 4031 return (USBD_IN_PROGRESS); 4032 #undef exfer 4033 } 4034 4035 Static void 4036 ehci_device_bulk_abort(usbd_xfer_handle xfer) 4037 { 4038 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4039 4040 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 4041 ehci_abort_xfer(xfer, USBD_CANCELLED); 4042 } 4043 4044 /* 4045 * Close a device bulk pipe. 4046 */ 4047 Static void 4048 ehci_device_bulk_close(usbd_pipe_handle pipe) 4049 { 4050 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 4051 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 4052 4053 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4054 4055 KASSERT(mutex_owned(&sc->sc_lock)); 4056 4057 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 4058 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 4059 ehci_close_pipe(pipe, sc->sc_async_head); 4060 } 4061 4062 Static void 4063 ehci_device_bulk_done(usbd_xfer_handle xfer) 4064 { 4065 struct ehci_xfer *ex = EXFER(xfer); 4066 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4067 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 4068 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4069 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 4070 4071 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4072 4073 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4074 xfer, xfer->ux_actlen, 0, 0); 4075 4076 KASSERT(mutex_owned(&sc->sc_lock)); 4077 4078 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4079 ehci_del_intr_list(sc, ex); /* remove from active list */ 4080 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4081 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4082 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4083 } 4084 4085 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 4086 } 4087 4088 /************************/ 4089 4090 Static usbd_status 4091 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 4092 { 4093 struct ehci_soft_islot *isp; 4094 int islot, lev; 4095 4096 /* Find a poll rate that is large enough. */ 4097 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 4098 if (EHCI_ILEV_IVAL(lev) <= ival) 4099 break; 4100 4101 /* Pick an interrupt slot at the right level. */ 4102 /* XXX could do better than picking at random */ 4103 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 4104 islot = EHCI_IQHIDX(lev, sc->sc_rand); 4105 4106 sqh->islot = islot; 4107 isp = &sc->sc_islots[islot]; 4108 mutex_enter(&sc->sc_lock); 4109 ehci_add_qh(sc, sqh, isp->sqh); 4110 mutex_exit(&sc->sc_lock); 4111 4112 return (USBD_NORMAL_COMPLETION); 4113 } 4114 4115 Static usbd_status 4116 ehci_device_intr_transfer(usbd_xfer_handle xfer) 4117 { 4118 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4119 usbd_status err; 4120 4121 /* Insert last in queue. */ 4122 mutex_enter(&sc->sc_lock); 4123 err = usb_insert_transfer(xfer); 4124 mutex_exit(&sc->sc_lock); 4125 if (err) 4126 return (err); 4127 4128 /* 4129 * Pipe isn't running (otherwise err would be USBD_INPROG), 4130 * so start it first. 4131 */ 4132 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue))); 4133 } 4134 4135 Static usbd_status 4136 ehci_device_intr_start(usbd_xfer_handle xfer) 4137 { 4138 #define exfer EXFER(xfer) 4139 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 4140 usbd_device_handle dev = xfer->ux_pipe->up_dev; 4141 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 4142 ehci_soft_qtd_t *data, *dataend; 4143 ehci_soft_qh_t *sqh; 4144 usbd_status err; 4145 int len, isread, endpt; 4146 4147 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4148 4149 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 4150 xfer, xfer->ux_length, xfer->ux_flags, 0); 4151 4152 if (sc->sc_dying) 4153 return (USBD_IOERROR); 4154 4155 #ifdef DIAGNOSTIC 4156 if (xfer->ux_rqflags & URQ_REQUEST) 4157 panic("ehci_device_intr_start: a request"); 4158 #endif 4159 4160 mutex_enter(&sc->sc_lock); 4161 4162 len = xfer->ux_length; 4163 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4164 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4165 sqh = epipe->sqh; 4166 4167 epipe->u.intr.length = len; 4168 4169 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 4170 &dataend); 4171 if (err) { 4172 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4173 xfer->ux_status = err; 4174 usb_transfer_complete(xfer); 4175 mutex_exit(&sc->sc_lock); 4176 return (err); 4177 } 4178 4179 #ifdef EHCI_DEBUG 4180 USBHIST_LOGN(ehcidebug, 5, "data(1)", 0, 0, 0, 0); 4181 ehci_dump_sqh(sqh); 4182 ehci_dump_sqtds(data); 4183 #endif 4184 4185 /* Set up interrupt info. */ 4186 exfer->sqtdstart = data; 4187 exfer->sqtdend = dataend; 4188 #ifdef DIAGNOSTIC 4189 if (!exfer->isdone) { 4190 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 4191 } 4192 exfer->isdone = 0; 4193 #endif 4194 4195 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4196 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4197 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4198 ehci_timeout, xfer); 4199 } 4200 ehci_add_intr_list(sc, exfer); 4201 xfer->ux_status = USBD_IN_PROGRESS; 4202 mutex_exit(&sc->sc_lock); 4203 4204 #ifdef EHCI_DEBUG 4205 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 4206 // delay(10000); 4207 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 4208 ehci_dump_regs(sc); 4209 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 4210 ehci_dump_sqh(sqh); 4211 ehci_dump_sqtds(data); 4212 #endif 4213 4214 if (sc->sc_bus.ub_usepolling) 4215 ehci_waitintr(sc, xfer); 4216 4217 return (USBD_IN_PROGRESS); 4218 #undef exfer 4219 } 4220 4221 Static void 4222 ehci_device_intr_abort(usbd_xfer_handle xfer) 4223 { 4224 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4225 4226 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 4227 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4228 4229 /* 4230 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4231 * async doorbell. That's dependent on the async list, wheras 4232 * intr xfers are periodic, should not use this? 4233 */ 4234 ehci_abort_xfer(xfer, USBD_CANCELLED); 4235 } 4236 4237 Static void 4238 ehci_device_intr_close(usbd_pipe_handle pipe) 4239 { 4240 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 4241 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 4242 struct ehci_soft_islot *isp; 4243 4244 KASSERT(mutex_owned(&sc->sc_lock)); 4245 4246 isp = &sc->sc_islots[epipe->sqh->islot]; 4247 ehci_close_pipe(pipe, isp->sqh); 4248 } 4249 4250 Static void 4251 ehci_device_intr_done(usbd_xfer_handle xfer) 4252 { 4253 #define exfer EXFER(xfer) 4254 struct ehci_xfer *ex = EXFER(xfer); 4255 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4256 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 4257 ehci_soft_qtd_t *data, *dataend; 4258 ehci_soft_qh_t *sqh; 4259 usbd_status err; 4260 int len, isread, endpt; 4261 4262 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4263 4264 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4265 xfer, xfer->ux_actlen, 0, 0); 4266 4267 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4268 4269 if (xfer->ux_pipe->up_repeat) { 4270 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4271 4272 len = epipe->u.intr.length; 4273 xfer->ux_length = len; 4274 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4275 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4276 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4277 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4278 sqh = epipe->sqh; 4279 4280 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4281 &data, &dataend); 4282 if (err) { 4283 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4284 xfer->ux_status = err; 4285 return; 4286 } 4287 4288 /* Set up interrupt info. */ 4289 exfer->sqtdstart = data; 4290 exfer->sqtdend = dataend; 4291 #ifdef DIAGNOSTIC 4292 if (!exfer->isdone) { 4293 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", 4294 exfer, 0, 0, 0); 4295 printf("ehci_device_intr_done: not done, ex=%p\n", 4296 exfer); 4297 } 4298 exfer->isdone = 0; 4299 #endif 4300 4301 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4302 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4303 callout_reset(&xfer->ux_callout, 4304 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4305 } 4306 4307 xfer->ux_status = USBD_IN_PROGRESS; 4308 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4309 ehci_del_intr_list(sc, ex); /* remove from active list */ 4310 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4311 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4312 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4313 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4314 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4315 } 4316 #undef exfer 4317 } 4318 4319 /************************/ 4320 4321 Static usbd_status 4322 ehci_device_fs_isoc_transfer(usbd_xfer_handle xfer) 4323 { 4324 usbd_status err; 4325 4326 err = usb_insert_transfer(xfer); 4327 if (err && err != USBD_IN_PROGRESS) 4328 return err; 4329 4330 return ehci_device_fs_isoc_start(xfer); 4331 } 4332 4333 Static usbd_status 4334 ehci_device_fs_isoc_start(usbd_xfer_handle xfer) 4335 { 4336 struct ehci_pipe *epipe; 4337 usbd_device_handle dev; 4338 ehci_softc_t *sc; 4339 struct ehci_xfer *exfer; 4340 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4341 usb_dma_t *dma_buf; 4342 int i, j, k, frames; 4343 int offs, total_length; 4344 int frindex; 4345 u_int huba, dir; 4346 4347 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4348 4349 start = NULL; 4350 prev = NULL; 4351 sitd = NULL; 4352 total_length = 0; 4353 exfer = (struct ehci_xfer *) xfer; 4354 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4355 dev = xfer->ux_pipe->up_dev; 4356 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4357 4358 /* 4359 * To allow continuous transfers, above we start all transfers 4360 * immediately. However, we're still going to get usbd_start_next call 4361 * this when another xfer completes. So, check if this is already 4362 * in progress or not 4363 */ 4364 4365 if (exfer->sitdstart != NULL) 4366 return USBD_IN_PROGRESS; 4367 4368 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4369 xfer, xfer->ux_length, xfer->ux_flags, 0); 4370 4371 if (sc->sc_dying) 4372 return USBD_IOERROR; 4373 4374 /* 4375 * To avoid complication, don't allow a request right now that'll span 4376 * the entire frame table. To within 4 frames, to allow some leeway 4377 * on either side of where the hc currently is. 4378 */ 4379 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4380 xfer->ux_nframes >= sc->sc_flsize - 4) { 4381 printf("ehci: isoc descriptor requested that spans the entire" 4382 "frametable, too many frames\n"); 4383 return USBD_INVAL; 4384 } 4385 4386 #ifdef DIAGNOSTIC 4387 if (xfer->ux_rqflags & URQ_REQUEST) 4388 panic("ehci_device_fs_isoc_start: request\n"); 4389 4390 if (!exfer->isdone) 4391 printf("ehci_device_fs_isoc_start: not done, ex = %p\n", exfer); 4392 exfer->isdone = 0; 4393 #endif 4394 4395 /* 4396 * Step 1: Allocate and initialize sitds. 4397 */ 4398 4399 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4400 if (i > 16 || i == 0) { 4401 /* Spec page 271 says intervals > 16 are invalid */ 4402 USBHIST_LOG(ehcidebug, "bInverval %d invalid\n", 0, 0, 0, 0); 4403 4404 return USBD_INVAL; 4405 } 4406 4407 frames = xfer->ux_nframes; 4408 4409 if (frames == 0) { 4410 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4411 4412 return USBD_INVAL; 4413 } 4414 4415 dma_buf = &xfer->ux_dmabuf; 4416 offs = 0; 4417 4418 for (i = 0; i < frames; i++) { 4419 sitd = ehci_alloc_sitd(sc); 4420 4421 if (prev) 4422 prev->xfer_next = sitd; 4423 else 4424 start = sitd; 4425 4426 #ifdef DIAGNOSTIC 4427 if (xfer->ux_frlengths[i] > 0x3ff) { 4428 printf("ehci: invalid frame length\n"); 4429 xfer->ux_frlengths[i] = 0x3ff; 4430 } 4431 #endif 4432 4433 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4434 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4435 4436 /* Set page0 index and offset. */ 4437 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4438 4439 total_length += xfer->ux_frlengths[i]; 4440 offs += xfer->ux_frlengths[i]; 4441 4442 sitd->sitd.sitd_buffer[1] = 4443 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4444 4445 huba = dev->ud_myhsport->up_parent->ud_addr; 4446 4447 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4448 // Set hub address to 0 if embedded TT is used. 4449 if (huba == sc->sc_addr) 4450 huba = 0; 4451 } 4452 */ 4453 4454 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4455 dir = UE_GET_DIR(k) ? 1 : 0; 4456 sitd->sitd.sitd_endp = 4457 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4458 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4459 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4460 EHCI_SITD_SET_HUBA(huba) | 4461 EHCI_SITD_SET_DIR(dir)); 4462 4463 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4464 4465 /* XXX */ 4466 u_char sa, sb; 4467 u_int temp, tlen; 4468 sa = 0; 4469 4470 if (dir == 0) { /* OUT */ 4471 temp = 0; 4472 tlen = xfer->ux_frlengths[i]; 4473 if (tlen <= 188) { 4474 temp |= 1; /* T-count = 1, TP = ALL */ 4475 tlen = 1; 4476 } else { 4477 tlen += 187; 4478 tlen /= 188; 4479 temp |= tlen; /* T-count = [1..6] */ 4480 temp |= 8; /* TP = Begin */ 4481 } 4482 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4483 4484 tlen += sa; 4485 4486 if (tlen >= 8) { 4487 sb = 0; 4488 } else { 4489 sb = (1 << tlen); 4490 } 4491 4492 sa = (1 << sa); 4493 sa = (sb - sa) & 0x3F; 4494 sb = 0; 4495 } else { 4496 sb = (-(4 << sa)) & 0xFE; 4497 sa = (1 << sa) & 0x3F; 4498 sa = 0x01; 4499 sb = 0xfc; 4500 } 4501 4502 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4503 EHCI_SITD_SET_CMASK(sb)); 4504 4505 prev = sitd; 4506 } /* End of frame */ 4507 4508 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4509 4510 stop = sitd; 4511 stop->xfer_next = NULL; 4512 exfer->isoc_len = total_length; 4513 4514 usb_syncmem(&exfer->xfer.ux_dmabuf, 0, total_length, 4515 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4516 4517 /* 4518 * Part 2: Transfer descriptors have now been set up, now they must 4519 * be scheduled into the periodic frame list. Erk. Not wanting to 4520 * complicate matters, transfer is denied if the transfer spans 4521 * more than the period frame list. 4522 */ 4523 4524 mutex_enter(&sc->sc_lock); 4525 4526 /* Start inserting frames */ 4527 if (epipe->u.isoc.cur_xfers > 0) { 4528 frindex = epipe->u.isoc.next_frame; 4529 } else { 4530 frindex = EOREAD4(sc, EHCI_FRINDEX); 4531 frindex = frindex >> 3; /* Erase microframe index */ 4532 frindex += 2; 4533 } 4534 4535 if (frindex >= sc->sc_flsize) 4536 frindex &= (sc->sc_flsize - 1); 4537 4538 /* Whats the frame interval? */ 4539 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4540 4541 sitd = start; 4542 for (j = 0; j < frames; j++) { 4543 if (sitd == NULL) 4544 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4545 4546 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4547 if (sitd->sitd.sitd_next == 0) 4548 /* FIXME: frindex table gets initialized to NULL 4549 * or EHCI_NULL? */ 4550 sitd->sitd.sitd_next = EHCI_NULL; 4551 4552 usb_syncmem(&sitd->dma, 4553 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4554 sizeof(ehci_sitd_t), 4555 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4556 4557 sc->sc_flist[frindex] = 4558 htole32(EHCI_LINK_SITD | sitd->physaddr); 4559 4560 usb_syncmem(&sc->sc_fldma, 4561 sizeof(ehci_link_t) * frindex, 4562 sizeof(ehci_link_t), 4563 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4564 4565 sitd->u.frame_list.next = sc->sc_softsitds[frindex]; 4566 sc->sc_softsitds[frindex] = sitd; 4567 if (sitd->u.frame_list.next != NULL) 4568 sitd->u.frame_list.next->u.frame_list.prev = sitd; 4569 sitd->slot = frindex; 4570 sitd->u.frame_list.prev = NULL; 4571 4572 frindex += i; 4573 if (frindex >= sc->sc_flsize) 4574 frindex -= sc->sc_flsize; 4575 4576 sitd = sitd->xfer_next; 4577 } 4578 4579 epipe->u.isoc.cur_xfers++; 4580 epipe->u.isoc.next_frame = frindex; 4581 4582 exfer->sitdstart = start; 4583 exfer->sitdend = stop; 4584 exfer->sqtdstart = NULL; 4585 exfer->sqtdstart = NULL; 4586 4587 ehci_add_intr_list(sc, exfer); 4588 xfer->ux_status = USBD_IN_PROGRESS; 4589 xfer->ux_done = 0; 4590 4591 mutex_exit(&sc->sc_lock); 4592 4593 if (sc->sc_bus.ub_usepolling) { 4594 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4595 ehci_waitintr(sc, xfer); 4596 } 4597 4598 return USBD_IN_PROGRESS; 4599 } 4600 4601 Static void 4602 ehci_device_fs_isoc_abort(usbd_xfer_handle xfer) 4603 { 4604 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4605 4606 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4607 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4608 } 4609 4610 Static void 4611 ehci_device_fs_isoc_close(usbd_pipe_handle pipe) 4612 { 4613 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4614 4615 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4616 } 4617 4618 Static void 4619 ehci_device_fs_isoc_done(usbd_xfer_handle xfer) 4620 { 4621 struct ehci_xfer *exfer; 4622 ehci_softc_t *sc; 4623 struct ehci_pipe *epipe; 4624 4625 exfer = EXFER(xfer); 4626 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4627 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4628 4629 KASSERT(mutex_owned(&sc->sc_lock)); 4630 4631 epipe->u.isoc.cur_xfers--; 4632 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4633 ehci_del_intr_list(sc, exfer); 4634 ehci_rem_free_sitd_chain(sc, exfer); 4635 } 4636 4637 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4638 BUS_DMASYNC_POSTREAD); 4639 } 4640 Static usbd_status 4641 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 4642 { 4643 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4644 usbd_status err; 4645 4646 mutex_enter(&sc->sc_lock); 4647 err = usb_insert_transfer(xfer); 4648 mutex_exit(&sc->sc_lock); 4649 if (err && err != USBD_IN_PROGRESS) 4650 return err; 4651 4652 return ehci_device_isoc_start(xfer); 4653 } 4654 4655 Static usbd_status 4656 ehci_device_isoc_start(usbd_xfer_handle xfer) 4657 { 4658 struct ehci_pipe *epipe; 4659 ehci_softc_t *sc; 4660 struct ehci_xfer *exfer; 4661 ehci_soft_itd_t *itd, *prev, *start, *stop; 4662 usb_dma_t *dma_buf; 4663 int i, j, k, frames, uframes, ufrperframe; 4664 int trans_count, offs, total_length; 4665 int frindex; 4666 4667 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4668 4669 start = NULL; 4670 prev = NULL; 4671 itd = NULL; 4672 trans_count = 0; 4673 total_length = 0; 4674 exfer = (struct ehci_xfer *) xfer; 4675 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4676 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4677 4678 /* 4679 * To allow continuous transfers, above we start all transfers 4680 * immediately. However, we're still going to get usbd_start_next call 4681 * this when another xfer completes. So, check if this is already 4682 * in progress or not 4683 */ 4684 4685 if (exfer->itdstart != NULL) 4686 return USBD_IN_PROGRESS; 4687 4688 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4689 xfer, xfer->ux_length, xfer->ux_flags, 0); 4690 4691 if (sc->sc_dying) 4692 return USBD_IOERROR; 4693 4694 /* 4695 * To avoid complication, don't allow a request right now that'll span 4696 * the entire frame table. To within 4 frames, to allow some leeway 4697 * on either side of where the hc currently is. 4698 */ 4699 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4700 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4701 USBHIST_LOG(ehcidebug, 4702 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4703 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4704 return USBD_INVAL; 4705 } 4706 4707 #ifdef DIAGNOSTIC 4708 if (xfer->ux_rqflags & URQ_REQUEST) 4709 panic("ehci_device_isoc_start: request\n"); 4710 4711 if (!exfer->isdone) { 4712 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", exfer, 4713 0, 0, 0); 4714 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 4715 } 4716 exfer->isdone = 0; 4717 #endif 4718 4719 /* 4720 * Step 1: Allocate and initialize itds, how many do we need? 4721 * One per transfer if interval >= 8 microframes, fewer if we use 4722 * multiple microframes per frame. 4723 */ 4724 4725 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4726 if (i > 16 || i == 0) { 4727 /* Spec page 271 says intervals > 16 are invalid */ 4728 USBHIST_LOG(ehcidebug, "bInvertal %d invalid", i, 0, 0, 0); 4729 return USBD_INVAL; 4730 } 4731 4732 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4733 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4734 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4735 4736 if (frames == 0) { 4737 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4738 return USBD_INVAL; 4739 } 4740 4741 dma_buf = &xfer->ux_dmabuf; 4742 offs = 0; 4743 4744 for (i = 0; i < frames; i++) { 4745 int froffs = offs; 4746 itd = ehci_alloc_itd(sc); 4747 4748 if (prev != NULL) { 4749 prev->itd.itd_next = 4750 htole32(itd->physaddr | EHCI_LINK_ITD); 4751 usb_syncmem(&itd->dma, 4752 itd->offs + offsetof(ehci_itd_t, itd_next), 4753 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4754 4755 prev->xfer_next = itd; 4756 } else { 4757 start = itd; 4758 } 4759 4760 /* 4761 * Step 1.5, initialize uframes 4762 */ 4763 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4764 /* Calculate which page in the list this starts in */ 4765 int addr = DMAADDR(dma_buf, froffs); 4766 addr = EHCI_PAGE_OFFSET(addr); 4767 addr += (offs - froffs); 4768 addr = EHCI_PAGE(addr); 4769 addr /= EHCI_PAGE_SIZE; 4770 4771 /* This gets the initial offset into the first page, 4772 * looks how far further along the current uframe 4773 * offset is. Works out how many pages that is. 4774 */ 4775 4776 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4777 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4778 EHCI_ITD_SET_PG(addr) | 4779 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4780 4781 total_length += xfer->ux_frlengths[trans_count]; 4782 offs += xfer->ux_frlengths[trans_count]; 4783 trans_count++; 4784 4785 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4786 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4787 break; 4788 } 4789 } 4790 4791 /* Step 1.75, set buffer pointers. To simplify matters, all 4792 * pointers are filled out for the next 7 hardware pages in 4793 * the dma block, so no need to worry what pages to cover 4794 * and what to not. 4795 */ 4796 4797 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4798 /* 4799 * Don't try to lookup a page that's past the end 4800 * of buffer 4801 */ 4802 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4803 if (page_offs >= dma_buf->udma_block->size) 4804 break; 4805 4806 unsigned long long page = DMAADDR(dma_buf, page_offs); 4807 page = EHCI_PAGE(page); 4808 itd->itd.itd_bufr[j] = 4809 htole32(EHCI_ITD_SET_BPTR(page)); 4810 itd->itd.itd_bufr_hi[j] = 4811 htole32(page >> 32); 4812 } 4813 4814 /* 4815 * Other special values 4816 */ 4817 4818 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4819 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4820 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4821 4822 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4823 ? 1 : 0; 4824 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4825 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4826 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4827 4828 /* FIXME: handle invalid trans */ 4829 itd->itd.itd_bufr[2] |= 4830 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4831 4832 usb_syncmem(&itd->dma, 4833 itd->offs + offsetof(ehci_itd_t, itd_next), 4834 sizeof(ehci_itd_t), 4835 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4836 4837 prev = itd; 4838 } /* End of frame */ 4839 4840 stop = itd; 4841 stop->xfer_next = NULL; 4842 exfer->isoc_len = total_length; 4843 4844 usb_syncmem(&exfer->xfer.ux_dmabuf, 0, total_length, 4845 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4846 4847 /* 4848 * Part 2: Transfer descriptors have now been set up, now they must 4849 * be scheduled into the period frame list. Erk. Not wanting to 4850 * complicate matters, transfer is denied if the transfer spans 4851 * more than the period frame list. 4852 */ 4853 4854 mutex_enter(&sc->sc_lock); 4855 4856 /* Start inserting frames */ 4857 if (epipe->u.isoc.cur_xfers > 0) { 4858 frindex = epipe->u.isoc.next_frame; 4859 } else { 4860 frindex = EOREAD4(sc, EHCI_FRINDEX); 4861 frindex = frindex >> 3; /* Erase microframe index */ 4862 frindex += 2; 4863 } 4864 4865 if (frindex >= sc->sc_flsize) 4866 frindex &= (sc->sc_flsize - 1); 4867 4868 /* What's the frame interval? */ 4869 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4870 if (i / USB_UFRAMES_PER_FRAME == 0) 4871 i = 1; 4872 else 4873 i /= USB_UFRAMES_PER_FRAME; 4874 4875 itd = start; 4876 for (j = 0; j < frames; j++) { 4877 if (itd == NULL) 4878 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4879 4880 itd->itd.itd_next = sc->sc_flist[frindex]; 4881 if (itd->itd.itd_next == 0) 4882 /* FIXME: frindex table gets initialized to NULL 4883 * or EHCI_NULL? */ 4884 itd->itd.itd_next = EHCI_NULL; 4885 4886 usb_syncmem(&itd->dma, 4887 itd->offs + offsetof(ehci_itd_t, itd_next), 4888 sizeof(itd->itd.itd_next), 4889 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4890 4891 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4892 4893 usb_syncmem(&sc->sc_fldma, 4894 sizeof(ehci_link_t) * frindex, 4895 sizeof(ehci_link_t), 4896 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4897 4898 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4899 sc->sc_softitds[frindex] = itd; 4900 if (itd->u.frame_list.next != NULL) 4901 itd->u.frame_list.next->u.frame_list.prev = itd; 4902 itd->slot = frindex; 4903 itd->u.frame_list.prev = NULL; 4904 4905 frindex += i; 4906 if (frindex >= sc->sc_flsize) 4907 frindex -= sc->sc_flsize; 4908 4909 itd = itd->xfer_next; 4910 } 4911 4912 epipe->u.isoc.cur_xfers++; 4913 epipe->u.isoc.next_frame = frindex; 4914 4915 exfer->itdstart = start; 4916 exfer->itdend = stop; 4917 exfer->sqtdstart = NULL; 4918 exfer->sqtdend = NULL; 4919 4920 ehci_add_intr_list(sc, exfer); 4921 xfer->ux_status = USBD_IN_PROGRESS; 4922 xfer->ux_done = 0; 4923 mutex_exit(&sc->sc_lock); 4924 4925 if (sc->sc_bus.ub_usepolling) { 4926 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4927 ehci_waitintr(sc, xfer); 4928 } 4929 4930 return USBD_IN_PROGRESS; 4931 } 4932 4933 Static void 4934 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4935 { 4936 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4937 4938 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4939 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4940 } 4941 4942 Static void 4943 ehci_device_isoc_close(usbd_pipe_handle pipe) 4944 { 4945 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4946 4947 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4948 } 4949 4950 Static void 4951 ehci_device_isoc_done(usbd_xfer_handle xfer) 4952 { 4953 struct ehci_xfer *exfer; 4954 ehci_softc_t *sc; 4955 struct ehci_pipe *epipe; 4956 4957 exfer = EXFER(xfer); 4958 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4959 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4960 4961 KASSERT(mutex_owned(&sc->sc_lock)); 4962 4963 epipe->u.isoc.cur_xfers--; 4964 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4965 ehci_del_intr_list(sc, exfer); 4966 ehci_rem_free_itd_chain(sc, exfer); 4967 } 4968 4969 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4970 BUS_DMASYNC_POSTREAD); 4971 4972 } 4973
Indexes created Wed Oct 01 19:09:53 GMT 2025