ehci.c revision 1.234.2.107
1 /* $NetBSD: ehci.c,v 1.234.2.107 2016/12/27 10:37:52 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.107 2016/12/27 10:37:52 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 130 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 131 #define EHCIHIST_FUNC() USBHIST_FUNC() 132 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 133 134 struct ehci_pipe { 135 struct usbd_pipe pipe; 136 int nexttoggle; 137 138 ehci_soft_qh_t *sqh; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 157 158 Static usbd_status ehci_open(struct usbd_pipe *); 159 Static void ehci_poll(struct usbd_bus *); 160 Static void ehci_softintr(void *); 161 Static int ehci_intr1(ehci_softc_t *); 162 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 163 ex_completeq_t *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 165 ex_completeq_t *); 166 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 167 ex_completeq_t *); 168 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 169 Static void ehci_timeout(void *); 170 Static void ehci_timeout_task(void *); 171 Static void ehci_intrlist_timeout(void *); 172 Static void ehci_doorbell(void *); 173 Static void ehci_pcd(void *); 174 175 Static struct usbd_xfer * 176 ehci_allocx(struct usbd_bus *, unsigned int); 177 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 178 179 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 180 Static int ehci_roothub_ctrl(struct usbd_bus *, 181 usb_device_request_t *, void *, int); 182 183 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 185 Static void ehci_root_intr_abort(struct usbd_xfer *); 186 Static void ehci_root_intr_close(struct usbd_pipe *); 187 Static void ehci_root_intr_done(struct usbd_xfer *); 188 189 Static int ehci_device_ctrl_init(struct usbd_xfer *); 190 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 193 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 194 Static void ehci_device_ctrl_close(struct usbd_pipe *); 195 Static void ehci_device_ctrl_done(struct usbd_xfer *); 196 197 Static int ehci_device_bulk_init(struct usbd_xfer *); 198 Static void ehci_device_bulk_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 201 Static void ehci_device_bulk_abort(struct usbd_xfer *); 202 Static void ehci_device_bulk_close(struct usbd_pipe *); 203 Static void ehci_device_bulk_done(struct usbd_xfer *); 204 205 Static int ehci_device_intr_init(struct usbd_xfer *); 206 Static void ehci_device_intr_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 209 Static void ehci_device_intr_abort(struct usbd_xfer *); 210 Static void ehci_device_intr_close(struct usbd_pipe *); 211 Static void ehci_device_intr_done(struct usbd_xfer *); 212 213 Static int ehci_device_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 216 Static void ehci_device_isoc_abort(struct usbd_xfer *); 217 Static void ehci_device_isoc_close(struct usbd_pipe *); 218 Static void ehci_device_isoc_done(struct usbd_xfer *); 219 220 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 222 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 225 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 226 227 Static void ehci_device_clear_toggle(struct usbd_pipe *); 228 Static void ehci_noop(struct usbd_pipe *); 229 230 Static void ehci_disown(ehci_softc_t *, int, int); 231 232 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 233 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 234 235 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 236 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 237 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 238 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 239 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 240 241 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 242 int, int, int *, ehci_soft_qtd_t **); 243 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qtd(ehci_qtd_t *); 293 Static void ehci_dump_sqh(ehci_soft_qh_t *); 294 Static void ehci_dump_sitd(struct ehci_soft_itd *); 295 Static void ehci_dump_itds(ehci_soft_itd_t *); 296 Static void ehci_dump_itd(struct ehci_soft_itd *); 297 Static void ehci_dump_exfer(struct ehci_xfer *); 298 #endif 299 300 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 301 302 static inline void 303 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 304 { 305 306 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 307 } 308 309 static inline void 310 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 311 { 312 313 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 314 } 315 316 Static const struct usbd_bus_methods ehci_bus_methods = { 317 .ubm_open = ehci_open, 318 .ubm_softint = ehci_softintr, 319 .ubm_dopoll = ehci_poll, 320 .ubm_allocx = ehci_allocx, 321 .ubm_freex = ehci_freex, 322 .ubm_getlock = ehci_get_lock, 323 .ubm_rhctrl = ehci_roothub_ctrl, 324 }; 325 326 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 327 .upm_transfer = ehci_root_intr_transfer, 328 .upm_start = ehci_root_intr_start, 329 .upm_abort = ehci_root_intr_abort, 330 .upm_close = ehci_root_intr_close, 331 .upm_cleartoggle = ehci_noop, 332 .upm_done = ehci_root_intr_done, 333 }; 334 335 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 336 .upm_init = ehci_device_ctrl_init, 337 .upm_fini = ehci_device_ctrl_fini, 338 .upm_transfer = ehci_device_ctrl_transfer, 339 .upm_start = ehci_device_ctrl_start, 340 .upm_abort = ehci_device_ctrl_abort, 341 .upm_close = ehci_device_ctrl_close, 342 .upm_cleartoggle = ehci_noop, 343 .upm_done = ehci_device_ctrl_done, 344 }; 345 346 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 347 .upm_init = ehci_device_intr_init, 348 .upm_fini = ehci_device_intr_fini, 349 .upm_transfer = ehci_device_intr_transfer, 350 .upm_start = ehci_device_intr_start, 351 .upm_abort = ehci_device_intr_abort, 352 .upm_close = ehci_device_intr_close, 353 .upm_cleartoggle = ehci_device_clear_toggle, 354 .upm_done = ehci_device_intr_done, 355 }; 356 357 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 358 .upm_init = ehci_device_bulk_init, 359 .upm_fini = ehci_device_bulk_fini, 360 .upm_transfer = ehci_device_bulk_transfer, 361 .upm_start = ehci_device_bulk_start, 362 .upm_abort = ehci_device_bulk_abort, 363 .upm_close = ehci_device_bulk_close, 364 .upm_cleartoggle = ehci_device_clear_toggle, 365 .upm_done = ehci_device_bulk_done, 366 }; 367 368 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 369 .upm_init = ehci_device_isoc_init, 370 .upm_fini = ehci_device_isoc_fini, 371 .upm_transfer = ehci_device_isoc_transfer, 372 .upm_abort = ehci_device_isoc_abort, 373 .upm_close = ehci_device_isoc_close, 374 .upm_cleartoggle = ehci_noop, 375 .upm_done = ehci_device_isoc_done, 376 }; 377 378 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 379 .upm_init = ehci_device_fs_isoc_init, 380 .upm_fini = ehci_device_fs_isoc_fini, 381 .upm_transfer = ehci_device_fs_isoc_transfer, 382 .upm_abort = ehci_device_fs_isoc_abort, 383 .upm_close = ehci_device_fs_isoc_close, 384 .upm_cleartoggle = ehci_noop, 385 .upm_done = ehci_device_fs_isoc_done, 386 }; 387 388 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 389 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 390 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 391 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 392 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 393 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 394 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 395 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 396 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 397 }; 398 399 int 400 ehci_init(ehci_softc_t *sc) 401 { 402 uint32_t vers, sparams, cparams, hcr; 403 u_int i; 404 usbd_status err; 405 ehci_soft_qh_t *sqh; 406 u_int ncomp; 407 408 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 409 #ifdef EHCI_DEBUG 410 theehci = sc; 411 #endif 412 413 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 414 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 415 cv_init(&sc->sc_doorbell, "ehcidb"); 416 417 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 418 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 419 420 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 421 ehci_doorbell, sc); 422 KASSERT(sc->sc_doorbell_si != NULL); 423 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 424 ehci_pcd, sc); 425 KASSERT(sc->sc_pcd_si != NULL); 426 427 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 428 429 vers = EREAD2(sc, EHCI_HCIVERSION); 430 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 431 vers >> 8, vers & 0xff); 432 433 sparams = EREAD4(sc, EHCI_HCSPARAMS); 434 DPRINTF("sparams=%#x", sparams, 0, 0, 0); 435 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 436 ncomp = EHCI_HCS_N_CC(sparams); 437 if (ncomp != sc->sc_ncomp) { 438 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 439 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 440 #if NOHCI == 0 || NUHCI == 0 441 aprint_error("%s: ohci or uhci probably not configured\n", 442 device_xname(sc->sc_dev)); 443 #endif 444 if (ncomp < sc->sc_ncomp) 445 sc->sc_ncomp = ncomp; 446 } 447 if (sc->sc_ncomp > 0) { 448 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 449 aprint_normal("%s: companion controller%s, %d port%s each:", 450 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 451 EHCI_HCS_N_PCC(sparams), 452 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 453 for (i = 0; i < sc->sc_ncomp; i++) 454 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 455 aprint_normal("\n"); 456 } 457 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 458 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 459 460 cparams = EREAD4(sc, EHCI_HCCPARAMS); 461 DPRINTF("cparams=%#x", cparams, 0, 0, 0); 462 463 if (EHCI_HCC_64BIT(cparams)) { 464 /* MUST clear segment register if 64 bit capable. */ 465 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 466 } 467 468 if (cparams & EHCI_HCC_IST_FULLFRAME) { 469 sc->sc_istthreshold = 0; 470 } else { 471 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 472 } 473 474 sc->sc_bus.ub_revision = USBREV_2_0; 475 sc->sc_bus.ub_usedma = true; 476 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 477 478 /* Reset the controller */ 479 DPRINTF("resetting", 0, 0, 0, 0); 480 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 481 usb_delay_ms(&sc->sc_bus, 1); 482 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 483 for (i = 0; i < 100; i++) { 484 usb_delay_ms(&sc->sc_bus, 1); 485 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 486 if (!hcr) 487 break; 488 } 489 if (hcr) { 490 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 491 return EIO; 492 } 493 if (sc->sc_vendor_init) 494 sc->sc_vendor_init(sc); 495 496 /* XXX need proper intr scheduling */ 497 sc->sc_rand = 96; 498 499 /* frame list size at default, read back what we got and use that */ 500 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 501 case 0: sc->sc_flsize = 1024; break; 502 case 1: sc->sc_flsize = 512; break; 503 case 2: sc->sc_flsize = 256; break; 504 case 3: return EIO; 505 } 506 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 507 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 508 if (err) 509 return err; 510 DPRINTF("flsize=%d", sc->sc_flsize, 0, 0, 0); 511 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 512 513 for (i = 0; i < sc->sc_flsize; i++) { 514 sc->sc_flist[i] = EHCI_NULL; 515 } 516 517 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 518 519 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 520 KM_SLEEP); 521 if (sc->sc_softitds == NULL) 522 return ENOMEM; 523 LIST_INIT(&sc->sc_freeitds); 524 LIST_INIT(&sc->sc_freesitds); 525 TAILQ_INIT(&sc->sc_intrhead); 526 527 /* Set up the bus struct. */ 528 sc->sc_bus.ub_methods = &ehci_bus_methods; 529 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 530 531 sc->sc_eintrs = EHCI_NORMAL_INTRS; 532 533 /* 534 * Allocate the interrupt dummy QHs. These are arranged to give poll 535 * intervals that are powers of 2 times 1ms. 536 */ 537 for (i = 0; i < EHCI_INTRQHS; i++) { 538 sqh = ehci_alloc_sqh(sc); 539 if (sqh == NULL) { 540 err = ENOMEM; 541 goto bad1; 542 } 543 sc->sc_islots[i].sqh = sqh; 544 } 545 for (i = 0; i < EHCI_INTRQHS; i++) { 546 sqh = sc->sc_islots[i].sqh; 547 if (i == 0) { 548 /* The last (1ms) QH terminates. */ 549 sqh->qh.qh_link = EHCI_NULL; 550 sqh->next = NULL; 551 } else { 552 /* Otherwise the next QH has half the poll interval */ 553 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 554 sqh->qh.qh_link = htole32(sqh->next->physaddr | 555 EHCI_LINK_QH); 556 } 557 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 558 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 559 sqh->qh.qh_curqtd = EHCI_NULL; 560 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 561 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 562 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 563 sqh->sqtd = NULL; 564 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 565 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 566 } 567 /* Point the frame list at the last level (128ms). */ 568 for (i = 0; i < sc->sc_flsize; i++) { 569 int j; 570 571 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 572 revbits[i & (EHCI_MAX_POLLRATE-1)]; 573 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 574 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 575 i)].sqh->physaddr); 576 } 577 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 578 BUS_DMASYNC_PREWRITE); 579 580 /* Allocate dummy QH that starts the async list. */ 581 sqh = ehci_alloc_sqh(sc); 582 if (sqh == NULL) { 583 err = ENOMEM; 584 goto bad1; 585 } 586 /* Fill the QH */ 587 sqh->qh.qh_endp = 588 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 589 sqh->qh.qh_link = 590 htole32(sqh->physaddr | EHCI_LINK_QH); 591 sqh->qh.qh_curqtd = EHCI_NULL; 592 sqh->next = NULL; 593 /* Fill the overlay qTD */ 594 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 595 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 596 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 597 sqh->sqtd = NULL; 598 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 599 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 600 #ifdef EHCI_DEBUG 601 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 602 ehci_dump_sqh(sqh); 603 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 604 #endif 605 606 /* Point to async list */ 607 sc->sc_async_head = sqh; 608 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 609 610 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 611 612 /* Turn on controller */ 613 EOWRITE4(sc, EHCI_USBCMD, 614 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 615 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 616 EHCI_CMD_ASE | 617 EHCI_CMD_PSE | 618 EHCI_CMD_RS); 619 620 /* Take over port ownership */ 621 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 622 623 for (i = 0; i < 100; i++) { 624 usb_delay_ms(&sc->sc_bus, 1); 625 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 626 if (!hcr) 627 break; 628 } 629 if (hcr) { 630 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 631 return EIO; 632 } 633 634 /* Enable interrupts */ 635 DPRINTF("enabling interupts", 0, 0, 0, 0); 636 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 637 638 return 0; 639 640 #if 0 641 bad2: 642 ehci_free_sqh(sc, sc->sc_async_head); 643 #endif 644 bad1: 645 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 646 return err; 647 } 648 649 int 650 ehci_intr(void *v) 651 { 652 ehci_softc_t *sc = v; 653 int ret = 0; 654 655 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 656 657 if (sc == NULL) 658 return 0; 659 660 mutex_spin_enter(&sc->sc_intr_lock); 661 662 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 663 goto done; 664 665 /* If we get an interrupt while polling, then just ignore it. */ 666 if (sc->sc_bus.ub_usepolling) { 667 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 668 669 if (intrs) 670 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 671 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 672 goto done; 673 } 674 675 ret = ehci_intr1(sc); 676 677 done: 678 mutex_spin_exit(&sc->sc_intr_lock); 679 return ret; 680 } 681 682 Static int 683 ehci_intr1(ehci_softc_t *sc) 684 { 685 uint32_t intrs, eintrs; 686 687 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 688 689 /* In case the interrupt occurs before initialization has completed. */ 690 if (sc == NULL) { 691 #ifdef DIAGNOSTIC 692 printf("ehci_intr1: sc == NULL\n"); 693 #endif 694 return 0; 695 } 696 697 KASSERT(mutex_owned(&sc->sc_intr_lock)); 698 699 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 700 if (!intrs) 701 return 0; 702 703 eintrs = intrs & sc->sc_eintrs; 704 DPRINTF("sc=%p intrs=%#x(%#x) eintrs=%#x", sc, intrs, 705 EOREAD4(sc, EHCI_USBSTS), eintrs); 706 if (!eintrs) 707 return 0; 708 709 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 710 if (eintrs & EHCI_STS_IAA) { 711 DPRINTF("door bell", 0, 0, 0, 0); 712 kpreempt_disable(); 713 KASSERT(sc->sc_doorbell_si != NULL); 714 softint_schedule(sc->sc_doorbell_si); 715 kpreempt_enable(); 716 eintrs &= ~EHCI_STS_IAA; 717 } 718 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 719 DPRINTF("INT=%d ERRINT=%d", 720 eintrs & EHCI_STS_INT ? 1 : 0, 721 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 722 usb_schedsoftintr(&sc->sc_bus); 723 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 724 } 725 if (eintrs & EHCI_STS_HSE) { 726 printf("%s: unrecoverable error, controller halted\n", 727 device_xname(sc->sc_dev)); 728 /* XXX what else */ 729 } 730 if (eintrs & EHCI_STS_PCD) { 731 kpreempt_disable(); 732 KASSERT(sc->sc_pcd_si != NULL); 733 softint_schedule(sc->sc_pcd_si); 734 kpreempt_enable(); 735 eintrs &= ~EHCI_STS_PCD; 736 } 737 738 if (eintrs != 0) { 739 /* Block unprocessed interrupts. */ 740 sc->sc_eintrs &= ~eintrs; 741 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 742 printf("%s: blocking intrs 0x%x\n", 743 device_xname(sc->sc_dev), eintrs); 744 } 745 746 return 1; 747 } 748 749 Static void 750 ehci_doorbell(void *addr) 751 { 752 ehci_softc_t *sc = addr; 753 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 754 755 mutex_enter(&sc->sc_lock); 756 sc->sc_dbanswered = true; 757 cv_broadcast(&sc->sc_doorbell); 758 mutex_exit(&sc->sc_lock); 759 } 760 761 Static void 762 ehci_pcd(void *addr) 763 { 764 ehci_softc_t *sc = addr; 765 struct usbd_xfer *xfer; 766 u_char *p; 767 int i, m; 768 769 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 770 771 mutex_enter(&sc->sc_lock); 772 xfer = sc->sc_intrxfer; 773 774 if (xfer == NULL) { 775 /* Just ignore the change. */ 776 goto done; 777 } 778 779 p = xfer->ux_buf; 780 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 781 memset(p, 0, xfer->ux_length); 782 for (i = 1; i <= m; i++) { 783 /* Pick out CHANGE bits from the status reg. */ 784 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 785 p[i/8] |= 1 << (i%8); 786 if (i % 8 == 7) 787 DPRINTF("change(%d)=0x%02x", i / 8, p[i/8], 0, 0); 788 } 789 xfer->ux_actlen = xfer->ux_length; 790 xfer->ux_status = USBD_NORMAL_COMPLETION; 791 792 usb_transfer_complete(xfer); 793 794 done: 795 mutex_exit(&sc->sc_lock); 796 } 797 798 Static void 799 ehci_softintr(void *v) 800 { 801 struct usbd_bus *bus = v; 802 ehci_softc_t *sc = EHCI_BUS2SC(bus); 803 struct ehci_xfer *ex, *nextex; 804 805 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 806 807 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 808 809 ex_completeq_t cq; 810 TAILQ_INIT(&cq); 811 812 /* 813 * The only explanation I can think of for why EHCI is as brain dead 814 * as UHCI interrupt-wise is that Intel was involved in both. 815 * An interrupt just tells us that something is done, we have no 816 * clue what, so we need to scan through all active transfers. :-( 817 */ 818 819 /* 820 * ehci_idone will remove transfer from sc->sc_intrhead if it's 821 * complete and add to our cq list 822 * 823 */ 824 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 825 switch (ex->ex_type) { 826 case EX_CTRL: 827 case EX_BULK: 828 case EX_INTR: 829 ehci_check_qh_intr(sc, ex, &cq); 830 break; 831 case EX_ISOC: 832 ehci_check_itd_intr(sc, ex, &cq); 833 break; 834 case EX_FS_ISOC: 835 ehci_check_sitd_intr(sc, ex, &cq); 836 break; 837 default: 838 KASSERT(false); 839 } 840 841 } 842 843 /* 844 * We abuse ex_next for the interrupt and complete lists and 845 * interrupt transfers will get re-added here so use 846 * the _SAFE version of TAILQ_FOREACH. 847 */ 848 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 849 usb_transfer_complete(&ex->ex_xfer); 850 } 851 852 /* Schedule a callout to catch any dropped transactions. */ 853 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 854 !TAILQ_EMPTY(&sc->sc_intrhead)) 855 callout_reset(&sc->sc_tmo_intrlist, 856 hz, ehci_intrlist_timeout, sc); 857 } 858 859 Static void 860 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 861 { 862 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 863 uint32_t status; 864 865 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 866 867 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 868 869 if (ex->ex_type == EX_CTRL) { 870 fsqtd = ex->ex_setup; 871 lsqtd = ex->ex_status; 872 } else { 873 fsqtd = ex->ex_sqtdstart; 874 lsqtd = ex->ex_sqtdend; 875 } 876 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 877 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 878 879 /* 880 * If the last TD is still active we need to check whether there 881 * is an error somewhere in the middle, or whether there was a 882 * short packet (SPD and not ACTIVE). 883 */ 884 usb_syncmem(&lsqtd->dma, 885 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 886 sizeof(lsqtd->qtd.qtd_status), 887 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 888 status = le32toh(lsqtd->qtd.qtd_status); 889 usb_syncmem(&lsqtd->dma, 890 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 891 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 892 if (status & EHCI_QTD_ACTIVE) { 893 DPRINTFN(10, "active ex=%p", ex, 0, 0, 0); 894 895 /* last qTD has already been checked */ 896 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 897 usb_syncmem(&sqtd->dma, 898 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 899 sizeof(sqtd->qtd.qtd_status), 900 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 901 status = le32toh(sqtd->qtd.qtd_status); 902 usb_syncmem(&sqtd->dma, 903 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 904 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 905 /* If there's an active QTD the xfer isn't done. */ 906 if (status & EHCI_QTD_ACTIVE) 907 break; 908 /* Any kind of error makes the xfer done. */ 909 if (status & EHCI_QTD_HALTED) 910 goto done; 911 /* Handle short packets */ 912 if (EHCI_QTD_GET_BYTES(status) != 0) { 913 /* 914 * If we get here for a control transfer then 915 * we need to let the hardware complete the 916 * status phase. That is, we're not done 917 * quite yet. 918 * 919 * Otherwise, we're done. 920 */ 921 if (ex->ex_type == EX_CTRL) { 922 break; 923 } 924 goto done; 925 } 926 } 927 DPRINTFN(10, "ex=%p std=%p still active", ex, ex->ex_sqtdstart, 928 0, 0); 929 #ifdef EHCI_DEBUG 930 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 931 ehci_dump_sqtds(ex->ex_sqtdstart); 932 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 933 #endif 934 return; 935 } 936 done: 937 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 938 ehci_idone(ex, cq); 939 } 940 941 Static void 942 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 943 { 944 ehci_soft_itd_t *itd; 945 int i; 946 947 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 948 949 KASSERT(mutex_owned(&sc->sc_lock)); 950 951 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 952 return; 953 954 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 955 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 956 957 itd = ex->ex_itdend; 958 959 /* 960 * check no active transfers in last itd, meaning we're finished 961 */ 962 963 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 964 sizeof(itd->itd.itd_ctl), 965 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 966 967 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 968 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 969 break; 970 } 971 972 if (i == EHCI_ITD_NUFRAMES) { 973 goto done; /* All 8 descriptors inactive, it's done */ 974 } 975 976 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 977 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 978 979 DPRINTFN(10, "ex %p itd %p still active", ex, ex->ex_itdstart, 0, 0); 980 return; 981 done: 982 DPRINTF("ex %p done", ex, 0, 0, 0); 983 ehci_idone(ex, cq); 984 } 985 986 void 987 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 988 { 989 ehci_soft_sitd_t *sitd; 990 991 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 992 993 KASSERT(mutex_owned(&sc->sc_lock)); 994 995 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 996 return; 997 998 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 999 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1000 1001 sitd = ex->ex_sitdend; 1002 1003 /* 1004 * check no active transfers in last sitd, meaning we're finished 1005 */ 1006 1007 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1008 sizeof(sitd->sitd.sitd_trans), 1009 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1010 1011 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1012 1013 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1014 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1015 1016 if (active) 1017 return; 1018 1019 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 1020 ehci_idone(ex, cq); 1021 } 1022 1023 1024 Static void 1025 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1026 { 1027 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1028 struct usbd_xfer *xfer = &ex->ex_xfer; 1029 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1030 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1031 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1032 uint32_t status = 0, nstatus = 0; 1033 int actlen = 0; 1034 bool polling = sc->sc_bus.ub_usepolling; 1035 1036 KASSERT(polling || mutex_owned(&sc->sc_lock)); 1037 1038 DPRINTF("ex=%p", ex, 0, 0, 0); 1039 1040 /* 1041 * Make sure the timeout handler didn't run or ran to the end 1042 * and set the transfer status. 1043 */ 1044 callout_halt(&ex->ex_xfer.ux_callout, polling ? NULL : &sc->sc_lock); 1045 if (xfer->ux_status == USBD_CANCELLED || 1046 xfer->ux_status == USBD_TIMEOUT) { 1047 DPRINTF("aborted xfer=%p", xfer, 0, 0, 0); 1048 return; 1049 } 1050 1051 #ifdef DIAGNOSTIC 1052 #ifdef EHCI_DEBUG 1053 if (ex->ex_isdone) { 1054 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1055 ehci_dump_exfer(ex); 1056 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1057 } 1058 #endif 1059 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1060 ex->ex_type, xfer->ux_status); 1061 ex->ex_isdone = true; 1062 #endif 1063 1064 DPRINTF("xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1065 1066 /* The transfer is done, compute actual length and status. */ 1067 if (ex->ex_type == EX_ISOC) { 1068 /* HS isoc transfer */ 1069 1070 struct ehci_soft_itd *itd; 1071 int i, nframes, len, uframes; 1072 1073 nframes = 0; 1074 1075 #ifdef EHCI_DEBUG 1076 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1077 ehci_dump_itds(ex->ex_itdstart); 1078 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1079 #endif 1080 1081 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1082 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1083 1084 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1085 usb_syncmem(&itd->dma, 1086 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1087 sizeof(itd->itd.itd_ctl), 1088 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1089 1090 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1091 /* 1092 * XXX - driver didn't fill in the frame full 1093 * of uframes. This leads to scheduling 1094 * inefficiencies, but working around 1095 * this doubles complexity of tracking 1096 * an xfer. 1097 */ 1098 if (nframes >= xfer->ux_nframes) 1099 break; 1100 1101 status = le32toh(itd->itd.itd_ctl[i]); 1102 len = EHCI_ITD_GET_LEN(status); 1103 if (EHCI_ITD_GET_STATUS(status) != 0) 1104 len = 0; /*No valid data on error*/ 1105 1106 xfer->ux_frlengths[nframes++] = len; 1107 actlen += len; 1108 } 1109 usb_syncmem(&itd->dma, 1110 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1111 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1112 1113 if (nframes >= xfer->ux_nframes) 1114 break; 1115 } 1116 1117 xfer->ux_actlen = actlen; 1118 xfer->ux_status = USBD_NORMAL_COMPLETION; 1119 goto end; 1120 } else if (ex->ex_type == EX_FS_ISOC) { 1121 /* FS isoc transfer */ 1122 struct ehci_soft_sitd *sitd; 1123 int nframes, len; 1124 1125 nframes = 0; 1126 1127 for (sitd = ex->ex_sitdstart; sitd != NULL; 1128 sitd = sitd->xfer_next) { 1129 usb_syncmem(&sitd->dma, 1130 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1131 sizeof(sitd->sitd.sitd_trans), 1132 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1133 1134 /* 1135 * XXX - driver didn't fill in the frame full 1136 * of uframes. This leads to scheduling 1137 * inefficiencies, but working around 1138 * this doubles complexity of tracking 1139 * an xfer. 1140 */ 1141 if (nframes >= xfer->ux_nframes) 1142 break; 1143 1144 status = le32toh(sitd->sitd.sitd_trans); 1145 usb_syncmem(&sitd->dma, 1146 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1147 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1148 1149 len = EHCI_SITD_GET_LEN(status); 1150 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1151 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1152 /* No valid data on error */ 1153 len = xfer->ux_frlengths[nframes]; 1154 } 1155 1156 /* 1157 * frlengths[i]: # of bytes to send 1158 * len: # of bytes host didn't send 1159 */ 1160 xfer->ux_frlengths[nframes] -= len; 1161 /* frlengths[i]: # of bytes host sent */ 1162 actlen += xfer->ux_frlengths[nframes++]; 1163 1164 if (nframes >= xfer->ux_nframes) 1165 break; 1166 } 1167 1168 xfer->ux_actlen = actlen; 1169 xfer->ux_status = USBD_NORMAL_COMPLETION; 1170 goto end; 1171 } 1172 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1173 ex->ex_type == EX_BULK); 1174 1175 /* Continue processing xfers using queue heads */ 1176 if (ex->ex_type == EX_CTRL) { 1177 fsqtd = ex->ex_setup; 1178 lsqtd = ex->ex_status; 1179 } else { 1180 fsqtd = ex->ex_sqtdstart; 1181 lsqtd = ex->ex_sqtdend; 1182 } 1183 #ifdef EHCI_DEBUG 1184 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1185 ehci_dump_sqtds(fsqtd); 1186 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1187 #endif 1188 1189 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1190 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1191 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1192 nstatus = le32toh(sqtd->qtd.qtd_status); 1193 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1194 BUS_DMASYNC_PREREAD); 1195 if (nstatus & EHCI_QTD_ACTIVE) 1196 break; 1197 1198 status = nstatus; 1199 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1200 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1201 } 1202 1203 /* 1204 * If there are left over TDs we need to update the toggle. 1205 * The default pipe doesn't need it since control transfers 1206 * start the toggle at 0 every time. 1207 * For a short transfer we need to update the toggle for the missing 1208 * packets within the qTD. 1209 */ 1210 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1211 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1212 DPRINTF("toggle update status=0x%08x nstatus=0x%08x", 1213 status, nstatus, 0, 0); 1214 #if 0 1215 ehci_dump_sqh(epipe->sqh); 1216 ehci_dump_sqtds(ex->ex_sqtdstart); 1217 #endif 1218 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1219 } 1220 1221 DPRINTF("len=%d actlen=%d status=0x%08x", xfer->ux_length, actlen, 1222 status, 0); 1223 xfer->ux_actlen = actlen; 1224 if (status & EHCI_QTD_HALTED) { 1225 #ifdef EHCI_DEBUG 1226 DPRINTF("halted addr=%d endpt=0x%02x", 1227 xfer->ux_pipe->up_dev->ud_addr, 1228 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1229 0, 0); 1230 DPRINTF("cerr=%d pid=%d", 1231 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1232 0, 0); 1233 DPRINTF("active =%d halted=%d buferr=%d babble=%d", 1234 status & EHCI_QTD_ACTIVE ? 1 : 0, 1235 status & EHCI_QTD_HALTED ? 1 : 0, 1236 status & EHCI_QTD_BUFERR ? 1 : 0, 1237 status & EHCI_QTD_BABBLE ? 1 : 0); 1238 1239 DPRINTF("xacterr=%d missed=%d split =%d ping =%d", 1240 status & EHCI_QTD_XACTERR ? 1 : 0, 1241 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1242 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1243 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1244 1245 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1246 ehci_dump_sqh(epipe->sqh); 1247 ehci_dump_sqtds(ex->ex_sqtdstart); 1248 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1249 #endif 1250 /* low&full speed has an extra error flag */ 1251 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1252 EHCI_QH_SPEED_HIGH) 1253 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1254 else 1255 status &= EHCI_QTD_STATERRS; 1256 if (status == 0) /* no other errors means a stall */ { 1257 xfer->ux_status = USBD_STALLED; 1258 } else { 1259 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1260 } 1261 /* XXX need to reset TT on missed microframe */ 1262 if (status & EHCI_QTD_MISSEDMICRO) { 1263 printf("%s: missed microframe, TT reset not " 1264 "implemented, hub might be inoperational\n", 1265 device_xname(sc->sc_dev)); 1266 } 1267 } else { 1268 xfer->ux_status = USBD_NORMAL_COMPLETION; 1269 } 1270 1271 end: 1272 1273 ehci_del_intr_list(sc, ex); 1274 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1275 1276 DPRINTF("ex=%p done", ex, 0, 0, 0); 1277 } 1278 1279 Static void 1280 ehci_poll(struct usbd_bus *bus) 1281 { 1282 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1283 1284 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1285 1286 #ifdef EHCI_DEBUG 1287 static int last; 1288 int new; 1289 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1290 if (new != last) { 1291 DPRINTF("intrs=0x%04x", new, 0, 0, 0); 1292 last = new; 1293 } 1294 #endif 1295 1296 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1297 mutex_spin_enter(&sc->sc_intr_lock); 1298 ehci_intr1(sc); 1299 mutex_spin_exit(&sc->sc_intr_lock); 1300 } 1301 } 1302 1303 void 1304 ehci_childdet(device_t self, device_t child) 1305 { 1306 struct ehci_softc *sc = device_private(self); 1307 1308 KASSERT(sc->sc_child == child); 1309 sc->sc_child = NULL; 1310 } 1311 1312 int 1313 ehci_detach(struct ehci_softc *sc, int flags) 1314 { 1315 int rv = 0; 1316 1317 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1318 1319 if (sc->sc_child != NULL) 1320 rv = config_detach(sc->sc_child, flags); 1321 1322 if (rv != 0) 1323 return rv; 1324 1325 callout_halt(&sc->sc_tmo_intrlist, NULL); 1326 callout_destroy(&sc->sc_tmo_intrlist); 1327 1328 /* XXX free other data structures XXX */ 1329 if (sc->sc_softitds) 1330 kmem_free(sc->sc_softitds, 1331 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1332 cv_destroy(&sc->sc_doorbell); 1333 1334 #if 0 1335 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1336 1337 softint_disestablish(sc->sc_doorbell_si); 1338 softint_disestablish(sc->sc_pcd_si); 1339 1340 mutex_destroy(&sc->sc_lock); 1341 mutex_destroy(&sc->sc_intr_lock); 1342 #endif 1343 1344 pool_cache_destroy(sc->sc_xferpool); 1345 1346 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1347 1348 return rv; 1349 } 1350 1351 1352 int 1353 ehci_activate(device_t self, enum devact act) 1354 { 1355 struct ehci_softc *sc = device_private(self); 1356 1357 switch (act) { 1358 case DVACT_DEACTIVATE: 1359 sc->sc_dying = 1; 1360 return 0; 1361 default: 1362 return EOPNOTSUPP; 1363 } 1364 } 1365 1366 /* 1367 * Handle suspend/resume. 1368 * 1369 * We need to switch to polling mode here, because this routine is 1370 * called from an interrupt context. This is all right since we 1371 * are almost suspended anyway. 1372 * 1373 * Note that this power handler isn't to be registered directly; the 1374 * bus glue needs to call out to it. 1375 */ 1376 bool 1377 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1378 { 1379 ehci_softc_t *sc = device_private(dv); 1380 int i; 1381 uint32_t cmd, hcr; 1382 1383 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1384 1385 mutex_spin_enter(&sc->sc_intr_lock); 1386 sc->sc_bus.ub_usepolling++; 1387 mutex_spin_exit(&sc->sc_intr_lock); 1388 1389 for (i = 1; i <= sc->sc_noport; i++) { 1390 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1391 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1392 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1393 } 1394 1395 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1396 1397 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1398 EOWRITE4(sc, EHCI_USBCMD, cmd); 1399 1400 for (i = 0; i < 100; i++) { 1401 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1402 if (hcr == 0) 1403 break; 1404 1405 usb_delay_ms(&sc->sc_bus, 1); 1406 } 1407 if (hcr != 0) 1408 printf("%s: reset timeout\n", device_xname(dv)); 1409 1410 cmd &= ~EHCI_CMD_RS; 1411 EOWRITE4(sc, EHCI_USBCMD, cmd); 1412 1413 for (i = 0; i < 100; i++) { 1414 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1415 if (hcr == EHCI_STS_HCH) 1416 break; 1417 1418 usb_delay_ms(&sc->sc_bus, 1); 1419 } 1420 if (hcr != EHCI_STS_HCH) 1421 printf("%s: config timeout\n", device_xname(dv)); 1422 1423 mutex_spin_enter(&sc->sc_intr_lock); 1424 sc->sc_bus.ub_usepolling--; 1425 mutex_spin_exit(&sc->sc_intr_lock); 1426 1427 return true; 1428 } 1429 1430 bool 1431 ehci_resume(device_t dv, const pmf_qual_t *qual) 1432 { 1433 ehci_softc_t *sc = device_private(dv); 1434 int i; 1435 uint32_t cmd, hcr; 1436 1437 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1438 1439 /* restore things in case the bios sucks */ 1440 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1441 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1442 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1443 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1444 1445 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1446 1447 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1448 1449 hcr = 0; 1450 for (i = 1; i <= sc->sc_noport; i++) { 1451 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1452 if ((cmd & EHCI_PS_PO) == 0 && 1453 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1454 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1455 hcr = 1; 1456 } 1457 } 1458 1459 if (hcr) { 1460 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1461 1462 for (i = 1; i <= sc->sc_noport; i++) { 1463 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1464 if ((cmd & EHCI_PS_PO) == 0 && 1465 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1466 EOWRITE4(sc, EHCI_PORTSC(i), 1467 cmd & ~EHCI_PS_FPR); 1468 } 1469 } 1470 1471 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1472 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1473 1474 for (i = 0; i < 100; i++) { 1475 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1476 if (hcr != EHCI_STS_HCH) 1477 break; 1478 1479 usb_delay_ms(&sc->sc_bus, 1); 1480 } 1481 if (hcr == EHCI_STS_HCH) 1482 printf("%s: config timeout\n", device_xname(dv)); 1483 1484 return true; 1485 } 1486 1487 /* 1488 * Shut down the controller when the system is going down. 1489 */ 1490 bool 1491 ehci_shutdown(device_t self, int flags) 1492 { 1493 ehci_softc_t *sc = device_private(self); 1494 1495 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1496 1497 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1498 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1499 return true; 1500 } 1501 1502 Static struct usbd_xfer * 1503 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1504 { 1505 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1506 struct usbd_xfer *xfer; 1507 1508 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1509 if (xfer != NULL) { 1510 memset(xfer, 0, sizeof(struct ehci_xfer)); 1511 #ifdef DIAGNOSTIC 1512 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1513 ex->ex_isdone = true; 1514 xfer->ux_state = XFER_BUSY; 1515 #endif 1516 } 1517 return xfer; 1518 } 1519 1520 Static void 1521 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1522 { 1523 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1524 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1525 1526 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1527 xfer->ux_state); 1528 KASSERT(ex->ex_isdone); 1529 1530 #ifdef DIAGNOSTIC 1531 xfer->ux_state = XFER_FREE; 1532 #endif 1533 1534 pool_cache_put(sc->sc_xferpool, xfer); 1535 } 1536 1537 Static void 1538 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1539 { 1540 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1541 1542 *lock = &sc->sc_lock; 1543 } 1544 1545 Static void 1546 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1547 { 1548 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1549 1550 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1551 1552 DPRINTF("epipe=%p status=0x%08x", epipe, 1553 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1554 #ifdef EHCI_DEBUG 1555 if (ehcidebug) 1556 usbd_dump_pipe(pipe); 1557 #endif 1558 epipe->nexttoggle = 0; 1559 } 1560 1561 Static void 1562 ehci_noop(struct usbd_pipe *pipe) 1563 { 1564 } 1565 1566 #ifdef EHCI_DEBUG 1567 /* 1568 * Unused function - this is meant to be called from a kernel 1569 * debugger. 1570 */ 1571 void 1572 ehci_dump(void) 1573 { 1574 ehci_softc_t *sc = theehci; 1575 int i; 1576 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1577 EOREAD4(sc, EHCI_USBCMD), 1578 EOREAD4(sc, EHCI_USBSTS), 1579 EOREAD4(sc, EHCI_USBINTR)); 1580 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1581 EOREAD4(sc, EHCI_FRINDEX), 1582 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1583 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1584 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1585 for (i = 1; i <= sc->sc_noport; i++) 1586 printf("port %d status=0x%08x\n", i, 1587 EOREAD4(sc, EHCI_PORTSC(i))); 1588 } 1589 1590 Static void 1591 ehci_dump_regs(ehci_softc_t *sc) 1592 { 1593 int i; 1594 1595 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1596 1597 DPRINTF("cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1598 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1599 EOREAD4(sc, EHCI_USBINTR), 0); 1600 DPRINTF("frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1601 "async = 0x%08x", 1602 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1603 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1604 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1605 for (i = 1; i <= sc->sc_noport; i += 2) { 1606 if (i == sc->sc_noport) { 1607 DPRINTF("port %d status = 0x%08x", i, 1608 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1609 } else { 1610 DPRINTF( 1611 "port %d status = 0x%08x port %d status = 0x%08x", 1612 i, EOREAD4(sc, EHCI_PORTSC(i)), 1613 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1614 } 1615 } 1616 } 1617 1618 #define ehci_dump_link(link, type) do { \ 1619 DPRINTF(" link 0x%08x (T = %d):", \ 1620 link, \ 1621 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1622 if (type) { \ 1623 DPRINTF( \ 1624 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1625 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1626 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1627 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1628 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1629 } \ 1630 } while(0) 1631 1632 Static void 1633 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1634 { 1635 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1636 int i; 1637 uint32_t stop = 0; 1638 1639 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1640 ehci_dump_sqtd(sqtd); 1641 usb_syncmem(&sqtd->dma, 1642 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1643 sizeof(sqtd->qtd), 1644 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1645 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1646 usb_syncmem(&sqtd->dma, 1647 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1648 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1649 } 1650 if (!stop) 1651 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1652 } 1653 1654 Static void 1655 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1656 { 1657 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1658 1659 usb_syncmem(&sqtd->dma, sqtd->offs, 1660 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1661 1662 DPRINTFN(10, "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1663 ehci_dump_qtd(&sqtd->qtd); 1664 1665 usb_syncmem(&sqtd->dma, sqtd->offs, 1666 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1667 } 1668 1669 Static void 1670 ehci_dump_qtd(ehci_qtd_t *qtd) 1671 { 1672 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1673 uint32_t s = le32toh(qtd->qtd_status); 1674 1675 DPRINTFN(10, 1676 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1677 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1678 DPRINTFN(10, 1679 " toggle = %d ioc = %d bytes = %#x " 1680 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1681 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1682 DPRINTFN(10, 1683 " cerr = %d pid = %d stat = %x", 1684 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1685 0); 1686 DPRINTFN(10, 1687 "active =%d halted=%d buferr=%d babble=%d", 1688 s & EHCI_QTD_ACTIVE ? 1 : 0, 1689 s & EHCI_QTD_HALTED ? 1 : 0, 1690 s & EHCI_QTD_BUFERR ? 1 : 0, 1691 s & EHCI_QTD_BABBLE ? 1 : 0); 1692 DPRINTFN(10, 1693 "xacterr=%d missed=%d split =%d ping =%d", 1694 s & EHCI_QTD_XACTERR ? 1 : 0, 1695 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1696 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1697 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1698 DPRINTFN(10, 1699 "buffer[0] = %#x buffer[1] = %#x " 1700 "buffer[2] = %#x buffer[3] = %#x", 1701 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1702 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1703 DPRINTFN(10, 1704 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1705 } 1706 1707 Static void 1708 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1709 { 1710 ehci_qh_t *qh = &sqh->qh; 1711 ehci_link_t link; 1712 uint32_t endp, endphub; 1713 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1714 1715 usb_syncmem(&sqh->dma, sqh->offs, 1716 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1717 1718 DPRINTFN(10, "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1719 link = le32toh(qh->qh_link); 1720 ehci_dump_link(link, true); 1721 1722 endp = le32toh(qh->qh_endp); 1723 DPRINTFN(10, " endp = %#x", endp, 0, 0, 0); 1724 DPRINTFN(10, " addr = 0x%02x inact = %d endpt = %d eps = %d", 1725 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1726 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1727 DPRINTFN(10, " dtc = %d hrecl = %d", 1728 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1729 DPRINTFN(10, " ctl = %d nrl = %d mpl = %#x(%d)", 1730 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1731 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1732 1733 endphub = le32toh(qh->qh_endphub); 1734 DPRINTFN(10, " endphub = %#x", endphub, 0, 0, 0); 1735 DPRINTFN(10, " smask = 0x%02x cmask = 0x%02x", 1736 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1737 DPRINTFN(10, " huba = 0x%02x port = %d mult = %d", 1738 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1739 EHCI_QH_GET_MULT(endphub), 0); 1740 1741 link = le32toh(qh->qh_curqtd); 1742 ehci_dump_link(link, false); 1743 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1744 ehci_dump_qtd(&qh->qh_qtd); 1745 1746 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1747 BUS_DMASYNC_PREREAD); 1748 } 1749 1750 Static void 1751 ehci_dump_itds(ehci_soft_itd_t *itd) 1752 { 1753 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1754 int i; 1755 uint32_t stop = 0; 1756 1757 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1758 ehci_dump_itd(itd); 1759 usb_syncmem(&itd->dma, 1760 itd->offs + offsetof(ehci_itd_t, itd_next), 1761 sizeof(itd->itd), 1762 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1763 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1764 usb_syncmem(&itd->dma, 1765 itd->offs + offsetof(ehci_itd_t, itd_next), 1766 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1767 } 1768 if (!stop) 1769 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1770 } 1771 1772 Static void 1773 ehci_dump_itd(struct ehci_soft_itd *itd) 1774 { 1775 ehci_isoc_trans_t t; 1776 ehci_isoc_bufr_ptr_t b, b2, b3; 1777 int i; 1778 1779 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1780 1781 DPRINTF("ITD: next phys = %#x", itd->itd.itd_next, 0, 0, 0); 1782 1783 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1784 t = le32toh(itd->itd.itd_ctl[i]); 1785 DPRINTF("ITDctl %d: stat = %x len = %x", 1786 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1787 DPRINTF(" ioc = %x pg = %x offs = %x", 1788 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1789 EHCI_ITD_GET_OFFS(t), 0); 1790 } 1791 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1792 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1793 DPRINTF(" %x", 1794 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1795 1796 b = le32toh(itd->itd.itd_bufr[0]); 1797 b2 = le32toh(itd->itd.itd_bufr[1]); 1798 b3 = le32toh(itd->itd.itd_bufr[2]); 1799 DPRINTF(" ep = %x daddr = %x dir = %d", 1800 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1801 DPRINTF(" maxpkt = %x multi = %x", 1802 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1803 } 1804 1805 Static void 1806 ehci_dump_sitd(struct ehci_soft_itd *itd) 1807 { 1808 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1809 1810 DPRINTF("SITD %p next = %p prev = %p", 1811 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1812 DPRINTF(" xfernext=%p physaddr=%X slot=%d", 1813 itd->xfer_next, itd->physaddr, itd->slot, 0); 1814 } 1815 1816 Static void 1817 ehci_dump_exfer(struct ehci_xfer *ex) 1818 { 1819 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1820 1821 DPRINTF("ex = %p type %d isdone", ex, ex->ex_type, 1822 ex->ex_isdone, 0); 1823 1824 switch (ex->ex_type) { 1825 case EX_CTRL: 1826 DPRINTF(" setup = %p data = %p status = %p", 1827 ex->ex_setup, ex->ex_data, ex->ex_status, 0); 1828 break; 1829 case EX_BULK: 1830 case EX_INTR: 1831 DPRINTF(" qtdstart = %p qtdend = %p", 1832 ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); 1833 break; 1834 case EX_ISOC: 1835 DPRINTF(" itdstart = %p itdend = %p", 1836 ex->ex_itdstart, ex->ex_itdend, 0, 0); 1837 break; 1838 case EX_FS_ISOC: 1839 DPRINTF(" sitdstart = %p sitdend = %p", 1840 ex->ex_sitdstart, ex->ex_sitdend, 0, 0); 1841 break; 1842 default: 1843 DPRINTF(" unknown type", 0, 0, 0, 0); 1844 } 1845 } 1846 #endif 1847 1848 Static usbd_status 1849 ehci_open(struct usbd_pipe *pipe) 1850 { 1851 struct usbd_device *dev = pipe->up_dev; 1852 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1853 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1854 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1855 uint8_t addr = dev->ud_addr; 1856 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1857 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1858 ehci_soft_qh_t *sqh; 1859 usbd_status err; 1860 int ival, speed, naks; 1861 int hshubaddr, hshubport; 1862 1863 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1864 1865 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 1866 ed->bEndpointAddress, rhaddr); 1867 1868 if (dev->ud_myhsport) { 1869 /* 1870 * When directly attached FS/LS device while doing embedded 1871 * transaction translations and we are the hub, set the hub 1872 * address to 0 (us). 1873 */ 1874 if (!(sc->sc_flags & EHCIF_ETTF) 1875 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1876 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1877 } else { 1878 hshubaddr = 0; 1879 } 1880 hshubport = dev->ud_myhsport->up_portno; 1881 } else { 1882 hshubaddr = 0; 1883 hshubport = 0; 1884 } 1885 1886 if (sc->sc_dying) 1887 return USBD_IOERROR; 1888 1889 /* toggle state needed for bulk endpoints */ 1890 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1891 1892 if (addr == rhaddr) { 1893 switch (ed->bEndpointAddress) { 1894 case USB_CONTROL_ENDPOINT: 1895 pipe->up_methods = &roothub_ctrl_methods; 1896 break; 1897 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1898 pipe->up_methods = &ehci_root_intr_methods; 1899 break; 1900 default: 1901 DPRINTF("bad bEndpointAddress 0x%02x", 1902 ed->bEndpointAddress, 0, 0, 0); 1903 return USBD_INVAL; 1904 } 1905 return USBD_NORMAL_COMPLETION; 1906 } 1907 1908 /* XXX All this stuff is only valid for async. */ 1909 switch (dev->ud_speed) { 1910 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1911 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1912 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1913 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1914 } 1915 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1916 DPRINTF("hshubaddr=%d hshubport=%d", hshubaddr, hshubport, 0, 1917 0); 1918 return USBD_INVAL; 1919 } 1920 1921 /* 1922 * For interrupt transfer, nak throttling must be disabled, but for 1923 * the other transfer type, nak throttling should be enabled from the 1924 * viewpoint that avoids the memory thrashing. 1925 */ 1926 naks = (xfertype == UE_INTERRUPT) ? 0 1927 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1928 1929 /* Allocate sqh for everything, save isoc xfers */ 1930 if (xfertype != UE_ISOCHRONOUS) { 1931 sqh = ehci_alloc_sqh(sc); 1932 if (sqh == NULL) 1933 return USBD_NOMEM; 1934 /* qh_link filled when the QH is added */ 1935 sqh->qh.qh_endp = htole32( 1936 EHCI_QH_SET_ADDR(addr) | 1937 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1938 EHCI_QH_SET_EPS(speed) | 1939 EHCI_QH_DTC | 1940 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1941 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1942 EHCI_QH_CTL : 0) | 1943 EHCI_QH_SET_NRL(naks) 1944 ); 1945 sqh->qh.qh_endphub = htole32( 1946 EHCI_QH_SET_MULT(1) | 1947 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1948 ); 1949 if (speed != EHCI_QH_SPEED_HIGH) 1950 sqh->qh.qh_endphub |= htole32( 1951 EHCI_QH_SET_PORT(hshubport) | 1952 EHCI_QH_SET_HUBA(hshubaddr) | 1953 (xfertype == UE_INTERRUPT ? 1954 EHCI_QH_SET_CMASK(0x08) : 0) 1955 ); 1956 sqh->qh.qh_curqtd = EHCI_NULL; 1957 /* Fill the overlay qTD */ 1958 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1959 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1960 sqh->qh.qh_qtd.qtd_status = htole32(0); 1961 1962 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1963 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1964 epipe->sqh = sqh; 1965 } else { 1966 sqh = NULL; 1967 } /*xfertype == UE_ISOC*/ 1968 1969 switch (xfertype) { 1970 case UE_CONTROL: 1971 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1972 0, &epipe->ctrl.reqdma); 1973 #ifdef EHCI_DEBUG 1974 if (err) 1975 printf("ehci_open: usb_allocmem()=%d\n", err); 1976 #endif 1977 if (err) 1978 goto bad; 1979 pipe->up_methods = &ehci_device_ctrl_methods; 1980 mutex_enter(&sc->sc_lock); 1981 ehci_add_qh(sc, sqh, sc->sc_async_head); 1982 mutex_exit(&sc->sc_lock); 1983 break; 1984 case UE_BULK: 1985 pipe->up_methods = &ehci_device_bulk_methods; 1986 mutex_enter(&sc->sc_lock); 1987 ehci_add_qh(sc, sqh, sc->sc_async_head); 1988 mutex_exit(&sc->sc_lock); 1989 break; 1990 case UE_INTERRUPT: 1991 pipe->up_methods = &ehci_device_intr_methods; 1992 ival = pipe->up_interval; 1993 if (ival == USBD_DEFAULT_INTERVAL) { 1994 if (speed == EHCI_QH_SPEED_HIGH) { 1995 if (ed->bInterval > 16) { 1996 /* 1997 * illegal with high-speed, but there 1998 * were documentation bugs in the spec, 1999 * so be generous 2000 */ 2001 ival = 256; 2002 } else 2003 ival = (1 << (ed->bInterval - 1)) / 8; 2004 } else 2005 ival = ed->bInterval; 2006 } 2007 err = ehci_device_setintr(sc, sqh, ival); 2008 if (err) 2009 goto bad; 2010 break; 2011 case UE_ISOCHRONOUS: 2012 pipe->up_serialise = false; 2013 if (speed == EHCI_QH_SPEED_HIGH) 2014 pipe->up_methods = &ehci_device_isoc_methods; 2015 else 2016 pipe->up_methods = &ehci_device_fs_isoc_methods; 2017 if (ed->bInterval == 0 || ed->bInterval > 16) { 2018 printf("ehci: opening pipe with invalid bInterval\n"); 2019 err = USBD_INVAL; 2020 goto bad; 2021 } 2022 if (UGETW(ed->wMaxPacketSize) == 0) { 2023 printf("ehci: zero length endpoint open request\n"); 2024 err = USBD_INVAL; 2025 goto bad; 2026 } 2027 epipe->isoc.next_frame = 0; 2028 epipe->isoc.cur_xfers = 0; 2029 break; 2030 default: 2031 DPRINTF("bad xfer type %d", xfertype, 0, 0, 0); 2032 err = USBD_INVAL; 2033 goto bad; 2034 } 2035 return USBD_NORMAL_COMPLETION; 2036 2037 bad: 2038 if (sqh != NULL) { 2039 mutex_enter(&sc->sc_lock); 2040 ehci_free_sqh(sc, sqh); 2041 mutex_exit(&sc->sc_lock); 2042 } 2043 return err; 2044 } 2045 2046 /* 2047 * Add an ED to the schedule. Called with USB lock held. 2048 */ 2049 Static void 2050 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2051 { 2052 2053 KASSERT(mutex_owned(&sc->sc_lock)); 2054 2055 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2056 2057 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2058 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2059 2060 sqh->next = head->next; 2061 sqh->qh.qh_link = head->qh.qh_link; 2062 2063 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2064 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2065 2066 head->next = sqh; 2067 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2068 2069 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2070 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2071 2072 #ifdef EHCI_DEBUG 2073 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2074 ehci_dump_sqh(sqh); 2075 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2076 #endif 2077 } 2078 2079 /* 2080 * Remove an ED from the schedule. Called with USB lock held. 2081 */ 2082 Static void 2083 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2084 { 2085 ehci_soft_qh_t *p; 2086 2087 KASSERT(mutex_owned(&sc->sc_lock)); 2088 2089 /* XXX */ 2090 for (p = head; p != NULL && p->next != sqh; p = p->next) 2091 ; 2092 if (p == NULL) 2093 panic("ehci_rem_qh: ED not found"); 2094 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2095 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2096 p->next = sqh->next; 2097 p->qh.qh_link = sqh->qh.qh_link; 2098 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2099 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2100 2101 ehci_sync_hc(sc); 2102 } 2103 2104 Static void 2105 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2106 { 2107 int i; 2108 uint32_t status; 2109 2110 /* Save toggle bit and ping status. */ 2111 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2112 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2113 status = sqh->qh.qh_qtd.qtd_status & 2114 htole32(EHCI_QTD_TOGGLE_MASK | 2115 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2116 /* Set HALTED to make hw leave it alone. */ 2117 sqh->qh.qh_qtd.qtd_status = 2118 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2119 usb_syncmem(&sqh->dma, 2120 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2121 sizeof(sqh->qh.qh_qtd.qtd_status), 2122 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2123 sqh->qh.qh_curqtd = 0; 2124 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2125 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2126 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2127 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2128 sqh->sqtd = sqtd; 2129 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2130 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2131 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2132 sqh->qh.qh_qtd.qtd_status = status; 2133 usb_syncmem(&sqh->dma, 2134 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2135 sizeof(sqh->qh.qh_qtd.qtd_status), 2136 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2137 } 2138 2139 /* 2140 * Ensure that the HC has released all references to the QH. We do this 2141 * by asking for a Async Advance Doorbell interrupt and then we wait for 2142 * the interrupt. 2143 * To make this easier we first obtain exclusive use of the doorbell. 2144 */ 2145 Static void 2146 ehci_sync_hc(ehci_softc_t *sc) 2147 { 2148 int error __diagused; 2149 2150 KASSERT(mutex_owned(&sc->sc_lock)); 2151 2152 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2153 2154 if (sc->sc_dying) { 2155 DPRINTF("dying", 0, 0, 0, 0); 2156 return; 2157 } 2158 2159 /* ask for doorbell */ 2160 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2161 DPRINTF("cmd = 0x%08x sts = 0x%08x", 2162 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2163 2164 sc->sc_dbanswered = false; 2165 /* bell wait */ 2166 while (!sc->sc_dbanswered) { 2167 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); 2168 2169 DPRINTF("cmd = 0x%08x sts = 0x%08x ... done", 2170 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2171 #ifdef DIAGNOSTIC 2172 if (error == EWOULDBLOCK) { 2173 printf("%s: timed out\n", __func__); 2174 } else if (error) { 2175 printf("%s: cv_timedwait: error %d\n", __func__, error); 2176 } 2177 #endif 2178 } 2179 } 2180 2181 Static void 2182 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2183 { 2184 2185 KASSERT(mutex_owned(&sc->sc_lock)); 2186 2187 for (; itd != NULL; itd = itd->xfer_next) { 2188 struct ehci_soft_itd *prev = itd->frame_list.prev; 2189 2190 /* Unlink itd from hardware chain, or frame array */ 2191 if (prev == NULL) { /* We're at the table head */ 2192 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2193 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2194 usb_syncmem(&sc->sc_fldma, 2195 sizeof(ehci_link_t) * itd->slot, 2196 sizeof(ehci_link_t), 2197 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2198 2199 if (itd->frame_list.next != NULL) 2200 itd->frame_list.next->frame_list.prev = NULL; 2201 } else { 2202 /* XXX this part is untested... */ 2203 prev->itd.itd_next = itd->itd.itd_next; 2204 usb_syncmem(&itd->dma, 2205 itd->offs + offsetof(ehci_itd_t, itd_next), 2206 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2207 2208 prev->frame_list.next = itd->frame_list.next; 2209 if (itd->frame_list.next != NULL) 2210 itd->frame_list.next->frame_list.prev = prev; 2211 } 2212 } 2213 } 2214 2215 Static void 2216 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2217 { 2218 struct ehci_soft_itd *next; 2219 2220 mutex_enter(&sc->sc_lock); 2221 next = NULL; 2222 for (; itd != NULL; itd = next) { 2223 next = itd->xfer_next; 2224 ehci_free_itd_locked(sc, itd); 2225 } 2226 mutex_exit(&sc->sc_lock); 2227 } 2228 2229 Static void 2230 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2231 { 2232 2233 KASSERT(mutex_owned(&sc->sc_lock)); 2234 2235 for (; sitd != NULL; sitd = sitd->xfer_next) { 2236 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2237 2238 /* Unlink sitd from hardware chain, or frame array */ 2239 if (prev == NULL) { /* We're at the table head */ 2240 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2241 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2242 usb_syncmem(&sc->sc_fldma, 2243 sizeof(ehci_link_t) * sitd->slot, 2244 sizeof(ehci_link_t), 2245 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2246 2247 if (sitd->frame_list.next != NULL) 2248 sitd->frame_list.next->frame_list.prev = NULL; 2249 } else { 2250 /* XXX this part is untested... */ 2251 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2252 usb_syncmem(&sitd->dma, 2253 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2254 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2255 2256 prev->frame_list.next = sitd->frame_list.next; 2257 if (sitd->frame_list.next != NULL) 2258 sitd->frame_list.next->frame_list.prev = prev; 2259 } 2260 } 2261 } 2262 2263 Static void 2264 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2265 { 2266 2267 mutex_enter(&sc->sc_lock); 2268 struct ehci_soft_sitd *next = NULL; 2269 for (; sitd != NULL; sitd = next) { 2270 next = sitd->xfer_next; 2271 ehci_free_sitd_locked(sc, sitd); 2272 } 2273 mutex_exit(&sc->sc_lock); 2274 } 2275 2276 /***********/ 2277 2278 Static int 2279 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2280 void *buf, int buflen) 2281 { 2282 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2283 usb_hub_descriptor_t hubd; 2284 usb_port_status_t ps; 2285 uint16_t len, value, index; 2286 int l, totlen = 0; 2287 int port, i; 2288 uint32_t v; 2289 2290 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2291 2292 if (sc->sc_dying) 2293 return -1; 2294 2295 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, req->bRequest, 2296 0, 0); 2297 2298 len = UGETW(req->wLength); 2299 value = UGETW(req->wValue); 2300 index = UGETW(req->wIndex); 2301 2302 #define C(x,y) ((x) | ((y) << 8)) 2303 switch (C(req->bRequest, req->bmRequestType)) { 2304 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2305 if (len == 0) 2306 break; 2307 switch (value) { 2308 case C(0, UDESC_DEVICE): { 2309 usb_device_descriptor_t devd; 2310 totlen = min(buflen, sizeof(devd)); 2311 memcpy(&devd, buf, totlen); 2312 USETW(devd.idVendor, sc->sc_id_vendor); 2313 memcpy(buf, &devd, totlen); 2314 break; 2315 2316 } 2317 #define sd ((usb_string_descriptor_t *)buf) 2318 case C(1, UDESC_STRING): 2319 /* Vendor */ 2320 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2321 break; 2322 case C(2, UDESC_STRING): 2323 /* Product */ 2324 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2325 break; 2326 #undef sd 2327 default: 2328 /* default from usbroothub */ 2329 return buflen; 2330 } 2331 break; 2332 2333 /* Hub requests */ 2334 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2335 break; 2336 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2337 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 2338 value, 0, 0); 2339 if (index < 1 || index > sc->sc_noport) { 2340 return -1; 2341 } 2342 port = EHCI_PORTSC(index); 2343 v = EOREAD4(sc, port); 2344 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2345 v &= ~EHCI_PS_CLEAR; 2346 switch (value) { 2347 case UHF_PORT_ENABLE: 2348 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2349 break; 2350 case UHF_PORT_SUSPEND: 2351 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2352 break; 2353 v &= ~EHCI_PS_SUSP; 2354 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2355 /* see USB2 spec ch. 7.1.7.7 */ 2356 usb_delay_ms(&sc->sc_bus, 20); 2357 EOWRITE4(sc, port, v); 2358 usb_delay_ms(&sc->sc_bus, 2); 2359 #ifdef DEBUG 2360 v = EOREAD4(sc, port); 2361 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2362 printf("ehci: resume failed: %x\n", v); 2363 #endif 2364 break; 2365 case UHF_PORT_POWER: 2366 if (sc->sc_hasppc) 2367 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2368 break; 2369 case UHF_PORT_TEST: 2370 DPRINTF("clear port test %d", index, 0, 0, 0); 2371 break; 2372 case UHF_PORT_INDICATOR: 2373 DPRINTF("clear port ind %d", index, 0, 0, 0); 2374 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2375 break; 2376 case UHF_C_PORT_CONNECTION: 2377 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2378 break; 2379 case UHF_C_PORT_ENABLE: 2380 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2381 break; 2382 case UHF_C_PORT_SUSPEND: 2383 /* how? */ 2384 break; 2385 case UHF_C_PORT_OVER_CURRENT: 2386 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2387 break; 2388 case UHF_C_PORT_RESET: 2389 sc->sc_isreset[index] = 0; 2390 break; 2391 default: 2392 return -1; 2393 } 2394 #if 0 2395 switch(value) { 2396 case UHF_C_PORT_CONNECTION: 2397 case UHF_C_PORT_ENABLE: 2398 case UHF_C_PORT_SUSPEND: 2399 case UHF_C_PORT_OVER_CURRENT: 2400 case UHF_C_PORT_RESET: 2401 default: 2402 break; 2403 } 2404 #endif 2405 break; 2406 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2407 if (len == 0) 2408 break; 2409 if ((value & 0xff) != 0) { 2410 return -1; 2411 } 2412 totlen = min(buflen, sizeof(hubd)); 2413 memcpy(&hubd, buf, totlen); 2414 hubd.bNbrPorts = sc->sc_noport; 2415 v = EOREAD4(sc, EHCI_HCSPARAMS); 2416 USETW(hubd.wHubCharacteristics, 2417 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2418 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2419 ? UHD_PORT_IND : 0); 2420 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2421 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2422 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2423 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2424 totlen = min(totlen, hubd.bDescLength); 2425 memcpy(buf, &hubd, totlen); 2426 break; 2427 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2428 if (len != 4) { 2429 return -1; 2430 } 2431 memset(buf, 0, len); /* ? XXX */ 2432 totlen = len; 2433 break; 2434 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2435 DPRINTF("get port status i=%d", index, 0, 0, 0); 2436 if (index < 1 || index > sc->sc_noport) { 2437 return -1; 2438 } 2439 if (len != 4) { 2440 return -1; 2441 } 2442 v = EOREAD4(sc, EHCI_PORTSC(index)); 2443 DPRINTF("port status=0x%04x", v, 0, 0, 0); 2444 2445 i = UPS_HIGH_SPEED; 2446 if (sc->sc_flags & EHCIF_ETTF) { 2447 /* 2448 * If we are doing embedded transaction translation, 2449 * then directly attached LS/FS devices are reset by 2450 * the EHCI controller itself. PSPD is encoded 2451 * the same way as in USBSTATUS. 2452 */ 2453 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2454 } 2455 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2456 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2457 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2458 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2459 if (v & EHCI_PS_PR) i |= UPS_RESET; 2460 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2461 if (sc->sc_vendor_port_status) 2462 i = sc->sc_vendor_port_status(sc, v, i); 2463 USETW(ps.wPortStatus, i); 2464 i = 0; 2465 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2466 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2467 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2468 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2469 USETW(ps.wPortChange, i); 2470 totlen = min(len, sizeof(ps)); 2471 memcpy(buf, &ps, totlen); 2472 break; 2473 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2474 return -1; 2475 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2476 break; 2477 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2478 if (index < 1 || index > sc->sc_noport) { 2479 return -1; 2480 } 2481 port = EHCI_PORTSC(index); 2482 v = EOREAD4(sc, port); 2483 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2484 v &= ~EHCI_PS_CLEAR; 2485 switch(value) { 2486 case UHF_PORT_ENABLE: 2487 EOWRITE4(sc, port, v | EHCI_PS_PE); 2488 break; 2489 case UHF_PORT_SUSPEND: 2490 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2491 break; 2492 case UHF_PORT_RESET: 2493 DPRINTF("reset port %d", index, 0, 0, 0); 2494 if (EHCI_PS_IS_LOWSPEED(v) 2495 && sc->sc_ncomp > 0 2496 && !(sc->sc_flags & EHCIF_ETTF)) { 2497 /* 2498 * Low speed device on non-ETTF controller or 2499 * unaccompanied controller, give up ownership. 2500 */ 2501 ehci_disown(sc, index, 1); 2502 break; 2503 } 2504 /* Start reset sequence. */ 2505 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2506 EOWRITE4(sc, port, v | EHCI_PS_PR); 2507 /* Wait for reset to complete. */ 2508 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2509 if (sc->sc_dying) { 2510 return -1; 2511 } 2512 /* 2513 * An embedded transaction translator will automatically 2514 * terminate the reset sequence so there's no need to 2515 * it. 2516 */ 2517 v = EOREAD4(sc, port); 2518 if (v & EHCI_PS_PR) { 2519 /* Terminate reset sequence. */ 2520 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2521 /* Wait for HC to complete reset. */ 2522 usb_delay_ms(&sc->sc_bus, 2523 EHCI_PORT_RESET_COMPLETE); 2524 if (sc->sc_dying) { 2525 return -1; 2526 } 2527 } 2528 2529 v = EOREAD4(sc, port); 2530 DPRINTF("ehci after reset, status=0x%08x", v, 0, 0, 0); 2531 if (v & EHCI_PS_PR) { 2532 printf("%s: port reset timeout\n", 2533 device_xname(sc->sc_dev)); 2534 return USBD_TIMEOUT; 2535 } 2536 if (!(v & EHCI_PS_PE)) { 2537 /* Not a high speed device, give up ownership.*/ 2538 ehci_disown(sc, index, 0); 2539 break; 2540 } 2541 sc->sc_isreset[index] = 1; 2542 DPRINTF("ehci port %d reset, status = 0x%08x", index, 2543 v, 0, 0); 2544 break; 2545 case UHF_PORT_POWER: 2546 DPRINTF("set port power %d (has PPC = %d)", index, 2547 sc->sc_hasppc, 0, 0); 2548 if (sc->sc_hasppc) 2549 EOWRITE4(sc, port, v | EHCI_PS_PP); 2550 break; 2551 case UHF_PORT_TEST: 2552 DPRINTF("set port test %d", index, 0, 0, 0); 2553 break; 2554 case UHF_PORT_INDICATOR: 2555 DPRINTF("set port ind %d", index, 0, 0, 0); 2556 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2557 break; 2558 default: 2559 return -1; 2560 } 2561 break; 2562 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2563 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2564 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2565 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2566 break; 2567 default: 2568 /* default from usbroothub */ 2569 DPRINTF("returning %d (usbroothub default)", buflen, 0, 0, 0); 2570 2571 return buflen; 2572 } 2573 2574 DPRINTF("returning %d", totlen, 0, 0, 0); 2575 2576 return totlen; 2577 } 2578 2579 Static void 2580 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2581 { 2582 int port; 2583 uint32_t v; 2584 2585 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2586 2587 DPRINTF("index=%d lowspeed=%d", index, lowspeed, 0, 0); 2588 #ifdef DIAGNOSTIC 2589 if (sc->sc_npcomp != 0) { 2590 int i = (index-1) / sc->sc_npcomp; 2591 if (i >= sc->sc_ncomp) 2592 printf("%s: strange port\n", 2593 device_xname(sc->sc_dev)); 2594 else 2595 printf("%s: handing over %s speed device on " 2596 "port %d to %s\n", 2597 device_xname(sc->sc_dev), 2598 lowspeed ? "low" : "full", 2599 index, device_xname(sc->sc_comps[i])); 2600 } else { 2601 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2602 } 2603 #endif 2604 port = EHCI_PORTSC(index); 2605 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2606 EOWRITE4(sc, port, v | EHCI_PS_PO); 2607 } 2608 2609 Static usbd_status 2610 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2611 { 2612 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2613 usbd_status err; 2614 2615 /* Insert last in queue. */ 2616 mutex_enter(&sc->sc_lock); 2617 err = usb_insert_transfer(xfer); 2618 mutex_exit(&sc->sc_lock); 2619 if (err) 2620 return err; 2621 2622 /* Pipe isn't running, start first */ 2623 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2624 } 2625 2626 Static usbd_status 2627 ehci_root_intr_start(struct usbd_xfer *xfer) 2628 { 2629 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2630 2631 if (sc->sc_dying) 2632 return USBD_IOERROR; 2633 2634 mutex_enter(&sc->sc_lock); 2635 sc->sc_intrxfer = xfer; 2636 mutex_exit(&sc->sc_lock); 2637 2638 return USBD_IN_PROGRESS; 2639 } 2640 2641 /* Abort a root interrupt request. */ 2642 Static void 2643 ehci_root_intr_abort(struct usbd_xfer *xfer) 2644 { 2645 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2646 2647 KASSERT(mutex_owned(&sc->sc_lock)); 2648 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2649 2650 sc->sc_intrxfer = NULL; 2651 2652 xfer->ux_status = USBD_CANCELLED; 2653 usb_transfer_complete(xfer); 2654 } 2655 2656 /* Close the root pipe. */ 2657 Static void 2658 ehci_root_intr_close(struct usbd_pipe *pipe) 2659 { 2660 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2661 2662 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2663 2664 KASSERT(mutex_owned(&sc->sc_lock)); 2665 2666 sc->sc_intrxfer = NULL; 2667 } 2668 2669 Static void 2670 ehci_root_intr_done(struct usbd_xfer *xfer) 2671 { 2672 } 2673 2674 /************************/ 2675 2676 Static ehci_soft_qh_t * 2677 ehci_alloc_sqh(ehci_softc_t *sc) 2678 { 2679 ehci_soft_qh_t *sqh; 2680 usbd_status err; 2681 int i, offs; 2682 usb_dma_t dma; 2683 2684 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2685 2686 mutex_enter(&sc->sc_lock); 2687 if (sc->sc_freeqhs == NULL) { 2688 DPRINTF("allocating chunk", 0, 0, 0, 0); 2689 mutex_exit(&sc->sc_lock); 2690 2691 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2692 EHCI_PAGE_SIZE, &dma); 2693 #ifdef EHCI_DEBUG 2694 if (err) 2695 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2696 #endif 2697 if (err) 2698 return NULL; 2699 2700 mutex_enter(&sc->sc_lock); 2701 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2702 offs = i * EHCI_SQH_SIZE; 2703 sqh = KERNADDR(&dma, offs); 2704 sqh->physaddr = DMAADDR(&dma, offs); 2705 sqh->dma = dma; 2706 sqh->offs = offs; 2707 sqh->next = sc->sc_freeqhs; 2708 sc->sc_freeqhs = sqh; 2709 } 2710 } 2711 sqh = sc->sc_freeqhs; 2712 sc->sc_freeqhs = sqh->next; 2713 mutex_exit(&sc->sc_lock); 2714 2715 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2716 sqh->next = NULL; 2717 return sqh; 2718 } 2719 2720 Static void 2721 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2722 { 2723 KASSERT(mutex_owned(&sc->sc_lock)); 2724 2725 sqh->next = sc->sc_freeqhs; 2726 sc->sc_freeqhs = sqh; 2727 } 2728 2729 Static ehci_soft_qtd_t * 2730 ehci_alloc_sqtd(ehci_softc_t *sc) 2731 { 2732 ehci_soft_qtd_t *sqtd = NULL; 2733 usbd_status err; 2734 int i, offs; 2735 usb_dma_t dma; 2736 2737 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2738 2739 mutex_enter(&sc->sc_lock); 2740 if (sc->sc_freeqtds == NULL) { 2741 DPRINTF("allocating chunk", 0, 0, 0, 0); 2742 mutex_exit(&sc->sc_lock); 2743 2744 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2745 EHCI_PAGE_SIZE, &dma); 2746 #ifdef EHCI_DEBUG 2747 if (err) 2748 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2749 #endif 2750 if (err) 2751 goto done; 2752 2753 mutex_enter(&sc->sc_lock); 2754 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2755 offs = i * EHCI_SQTD_SIZE; 2756 sqtd = KERNADDR(&dma, offs); 2757 sqtd->physaddr = DMAADDR(&dma, offs); 2758 sqtd->dma = dma; 2759 sqtd->offs = offs; 2760 2761 sqtd->nextqtd = sc->sc_freeqtds; 2762 sc->sc_freeqtds = sqtd; 2763 } 2764 } 2765 2766 sqtd = sc->sc_freeqtds; 2767 sc->sc_freeqtds = sqtd->nextqtd; 2768 mutex_exit(&sc->sc_lock); 2769 2770 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2771 sqtd->nextqtd = NULL; 2772 sqtd->xfer = NULL; 2773 2774 done: 2775 return sqtd; 2776 } 2777 2778 Static void 2779 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2780 { 2781 2782 mutex_enter(&sc->sc_lock); 2783 sqtd->nextqtd = sc->sc_freeqtds; 2784 sc->sc_freeqtds = sqtd; 2785 mutex_exit(&sc->sc_lock); 2786 } 2787 2788 Static int 2789 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2790 int alen, int rd, ehci_soft_qtd_t **sp) 2791 { 2792 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2793 uint16_t flags = xfer->ux_flags; 2794 2795 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2796 2797 ASSERT_SLEEPABLE(); 2798 KASSERT(sp); 2799 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2800 2801 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2802 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2803 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2804 KM_SLEEP); 2805 exfer->ex_nsqtd = nsqtd; 2806 2807 DPRINTF("xfer %p len %d nsqtd %d flags %x", xfer, alen, nsqtd, flags); 2808 2809 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2810 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2811 if (cur == NULL) 2812 goto nomem; 2813 exfer->ex_sqtds[j++] = cur; 2814 2815 cur->xfer = xfer; 2816 cur->len = 0; 2817 2818 } 2819 2820 *sp = exfer->ex_sqtds[0]; 2821 DPRINTF("return sqtd=%p", *sp, 0, 0, 0); 2822 2823 return 0; 2824 2825 nomem: 2826 ehci_free_sqtds(sc, exfer); 2827 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2828 DPRINTF("no memory", 0, 0, 0, 0); 2829 return ENOMEM; 2830 } 2831 2832 Static void 2833 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2834 { 2835 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2836 DPRINTF("exfer=%p", exfer, 0, 0, 0); 2837 2838 mutex_enter(&sc->sc_lock); 2839 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2840 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2841 2842 if (sqtd == NULL) 2843 break; 2844 2845 sqtd->nextqtd = sc->sc_freeqtds; 2846 sc->sc_freeqtds = sqtd; 2847 } 2848 mutex_exit(&sc->sc_lock); 2849 } 2850 2851 Static void 2852 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2853 { 2854 if (prev) { 2855 prev->nextqtd = sqtd; 2856 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2857 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2858 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2859 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2860 } 2861 } 2862 2863 Static void 2864 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2865 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2866 { 2867 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2868 usb_dma_t *dma = &xfer->ux_dmabuf; 2869 uint16_t flags = xfer->ux_flags; 2870 ehci_soft_qtd_t *sqtd, *prev; 2871 int tog = *toggle; 2872 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2873 int len = length; 2874 2875 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2876 DPRINTF("xfer=%p len %d isread %d toggle %d", xfer, len, isread, tog); 2877 DPRINTF(" VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 0, 0, 0); 2878 2879 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2880 2881 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2882 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2883 EHCI_QTD_SET_CERR(3) 2884 ; 2885 2886 sqtd = prev = NULL; 2887 size_t curoffs = 0; 2888 size_t j = 0; 2889 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 2890 sqtd = exfer->ex_sqtds[j++]; 2891 DPRINTF("sqtd[%d]=%p prev %p", j, sqtd, prev, 0); 2892 2893 /* 2894 * The EHCI hardware can handle at most 5 pages and they do 2895 * not have to be contiguous 2896 */ 2897 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 2898 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 2899 size_t curlen = len; 2900 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 2901 /* must use multiple TDs, fill as much as possible. */ 2902 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2903 2904 /* the length must be a multiple of the max size */ 2905 curlen -= curlen % mps; 2906 } 2907 KASSERT(curlen != 0); 2908 DPRINTF(" len=%d curlen=%d curoffs=%zu", len, curlen, 2909 curoffs, 0); 2910 2911 /* Fill the qTD */ 2912 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2913 sqtd->qtd.qtd_status = htole32( 2914 qtdstatus | 2915 EHCI_QTD_SET_BYTES(curlen) | 2916 EHCI_QTD_SET_TOGGLE(tog)); 2917 2918 /* Find number of pages we'll be using, insert dma addresses */ 2919 size_t pages = EHCI_NPAGES(curlen); 2920 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2921 size_t pageoffs = EHCI_PAGE(curoffs); 2922 for (size_t i = 0; i < pages; i++) { 2923 paddr_t a = DMAADDR(dma, 2924 pageoffs + i * EHCI_PAGE_SIZE); 2925 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2926 /* Cast up to avoid compiler warnings */ 2927 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2928 DPRINTF(" buffer[%d/%d] 0x%08x 0x%08x", i, pages, 2929 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 2930 le32toh(sqtd->qtd.qtd_buffer[i])); 2931 } 2932 /* First buffer pointer requires a page offset to start at */ 2933 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 2934 2935 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2936 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2937 2938 sqtd->len = curlen; 2939 2940 DPRINTF(" va %p pa %p len %d", va, 2941 DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 2942 2943 ehci_append_sqtd(sqtd, prev); 2944 2945 if (((curlen + mps - 1) / mps) & 1) { 2946 tog ^= 1; 2947 } 2948 2949 curoffs += curlen; 2950 len -= curlen; 2951 } 2952 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 2953 xfer, length, len, mps, exfer->ex_nsqtd, j); 2954 2955 if (!isread && 2956 (flags & USBD_FORCE_SHORT_XFER) && 2957 length % mps == 0) { 2958 /* Force a 0 length transfer at the end. */ 2959 2960 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 2961 exfer->ex_nsqtd); 2962 prev = sqtd; 2963 sqtd = exfer->ex_sqtds[j++]; 2964 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 2965 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2966 sqtd->qtd.qtd_status = htole32( 2967 qtdstatus | 2968 EHCI_QTD_SET_BYTES(0) | 2969 EHCI_QTD_SET_TOGGLE(tog)); 2970 2971 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2972 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2973 2974 ehci_append_sqtd(sqtd, prev); 2975 tog ^= 1; 2976 } 2977 2978 *lsqtd = sqtd; 2979 *toggle = tog; 2980 } 2981 2982 Static ehci_soft_itd_t * 2983 ehci_alloc_itd(ehci_softc_t *sc) 2984 { 2985 struct ehci_soft_itd *itd, *freeitd; 2986 usbd_status err; 2987 usb_dma_t dma; 2988 2989 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2990 2991 mutex_enter(&sc->sc_lock); 2992 2993 freeitd = LIST_FIRST(&sc->sc_freeitds); 2994 if (freeitd == NULL) { 2995 DPRINTF("allocating chunk", 0, 0, 0, 0); 2996 mutex_exit(&sc->sc_lock); 2997 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2998 EHCI_PAGE_SIZE, &dma); 2999 3000 if (err) { 3001 DPRINTF("alloc returned %d", err, 0, 0, 0); 3002 return NULL; 3003 } 3004 mutex_enter(&sc->sc_lock); 3005 3006 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3007 int offs = i * EHCI_ITD_SIZE; 3008 itd = KERNADDR(&dma, offs); 3009 itd->physaddr = DMAADDR(&dma, offs); 3010 itd->dma = dma; 3011 itd->offs = offs; 3012 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3013 } 3014 freeitd = LIST_FIRST(&sc->sc_freeitds); 3015 } 3016 3017 itd = freeitd; 3018 LIST_REMOVE(itd, free_list); 3019 mutex_exit(&sc->sc_lock); 3020 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3021 3022 itd->frame_list.next = NULL; 3023 itd->frame_list.prev = NULL; 3024 itd->xfer_next = NULL; 3025 itd->slot = 0; 3026 3027 return itd; 3028 } 3029 3030 Static ehci_soft_sitd_t * 3031 ehci_alloc_sitd(ehci_softc_t *sc) 3032 { 3033 struct ehci_soft_sitd *sitd, *freesitd; 3034 usbd_status err; 3035 int i, offs; 3036 usb_dma_t dma; 3037 3038 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3039 3040 mutex_enter(&sc->sc_lock); 3041 freesitd = LIST_FIRST(&sc->sc_freesitds); 3042 if (freesitd == NULL) { 3043 DPRINTF("allocating chunk", 0, 0, 0, 0); 3044 mutex_exit(&sc->sc_lock); 3045 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3046 EHCI_PAGE_SIZE, &dma); 3047 3048 if (err) { 3049 DPRINTF("alloc returned %d", err, 0, 0, 3050 0); 3051 return NULL; 3052 } 3053 3054 mutex_enter(&sc->sc_lock); 3055 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3056 offs = i * EHCI_SITD_SIZE; 3057 sitd = KERNADDR(&dma, offs); 3058 sitd->physaddr = DMAADDR(&dma, offs); 3059 sitd->dma = dma; 3060 sitd->offs = offs; 3061 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3062 } 3063 freesitd = LIST_FIRST(&sc->sc_freesitds); 3064 } 3065 3066 sitd = freesitd; 3067 LIST_REMOVE(sitd, free_list); 3068 mutex_exit(&sc->sc_lock); 3069 3070 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3071 3072 sitd->frame_list.next = NULL; 3073 sitd->frame_list.prev = NULL; 3074 sitd->xfer_next = NULL; 3075 sitd->slot = 0; 3076 3077 return sitd; 3078 } 3079 3080 /****************/ 3081 3082 /* 3083 * Close a reqular pipe. 3084 * Assumes that there are no pending transactions. 3085 */ 3086 Static void 3087 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3088 { 3089 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3090 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3091 ehci_soft_qh_t *sqh = epipe->sqh; 3092 3093 KASSERT(mutex_owned(&sc->sc_lock)); 3094 3095 ehci_rem_qh(sc, sqh, head); 3096 ehci_free_sqh(sc, epipe->sqh); 3097 } 3098 3099 /* 3100 * Cancel or timeout a device request. We have two cases to deal with 3101 * 3102 * 1) A driver wants to stop scheduled or inflight transfers 3103 * 2) A transfer has timed out 3104 * 3105 * have (partially) happened since the hardware runs concurrently. 3106 * 3107 * Transfer state is protected by the bus lock and we set the transfer status 3108 * as soon as either of the above happens (with bus lock held). 3109 * 3110 * Then we arrange for the hardware to tells us that it is not still 3111 * processing the TDs by setting the QH halted bit and wait for the ehci 3112 * door bell 3113 */ 3114 Static void 3115 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3116 { 3117 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3118 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3119 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3120 ehci_soft_qh_t *sqh = epipe->sqh; 3121 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3122 ehci_physaddr_t cur; 3123 uint32_t qhstatus; 3124 int hit; 3125 int wake; 3126 3127 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3128 3129 DPRINTF("xfer=%p pipe=%p", xfer, epipe, 0, 0); 3130 3131 KASSERT(mutex_owned(&sc->sc_lock)); 3132 ASSERT_SLEEPABLE(); 3133 3134 if (sc->sc_dying) { 3135 /* If we're dying, just do the software part. */ 3136 xfer->ux_status = status; 3137 callout_halt(&xfer->ux_callout, &sc->sc_lock); 3138 KASSERT(xfer->ux_status == status); 3139 usb_transfer_complete(xfer); 3140 return; 3141 } 3142 3143 /* 3144 * If an abort is already in progress then just wait for it to 3145 * complete and return. 3146 */ 3147 if (xfer->ux_hcflags & UXFER_ABORTING) { 3148 DPRINTF("already aborting", 0, 0, 0, 0); 3149 #ifdef DIAGNOSTIC 3150 if (status == USBD_TIMEOUT) 3151 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3152 #endif 3153 /* Override the status which might be USBD_TIMEOUT. */ 3154 xfer->ux_status = status; 3155 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3156 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3157 while (xfer->ux_hcflags & UXFER_ABORTING) 3158 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3159 return; 3160 } 3161 xfer->ux_hcflags |= UXFER_ABORTING; 3162 3163 /* 3164 * Step 1: When cancelling a transfer make sure the timeout handler 3165 * didn't run or ran to the end and saw the USBD_CANCELLED status. 3166 * Otherwise we must have got here via a timeout. 3167 */ 3168 if (status == USBD_CANCELLED) { 3169 xfer->ux_status = status; 3170 callout_halt(&xfer->ux_callout, &sc->sc_lock); 3171 } else { 3172 KASSERT(xfer->ux_status == USBD_TIMEOUT); 3173 } 3174 3175 /* 3176 * Step 2: Make interrupt routine and hardware ignore xfer. 3177 */ 3178 ehci_del_intr_list(sc, exfer); 3179 3180 usb_syncmem(&sqh->dma, 3181 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3182 sizeof(sqh->qh.qh_qtd.qtd_status), 3183 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3184 qhstatus = sqh->qh.qh_qtd.qtd_status; 3185 if (exfer->ex_type == EX_CTRL) { 3186 fsqtd = exfer->ex_setup; 3187 lsqtd = exfer->ex_status; 3188 } else { 3189 fsqtd = exfer->ex_sqtdstart; 3190 lsqtd = exfer->ex_sqtdend; 3191 } 3192 if (!(qhstatus & htole32(EHCI_QTD_HALTED))) { 3193 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3194 usb_syncmem(&sqh->dma, 3195 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3196 sizeof(sqh->qh.qh_qtd.qtd_status), 3197 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3198 3199 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3200 usb_syncmem(&sqtd->dma, 3201 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3202 sizeof(sqtd->qtd.qtd_status), 3203 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3204 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3205 usb_syncmem(&sqtd->dma, 3206 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3207 sizeof(sqtd->qtd.qtd_status), 3208 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3209 if (sqtd == lsqtd) 3210 break; 3211 } 3212 } 3213 3214 /* 3215 * Step 3: Wait until we know hardware has finished any possible 3216 * use of the xfer. 3217 */ 3218 ehci_sync_hc(sc); 3219 3220 /* 3221 * Step 4: Remove any vestiges of the xfer from the hardware. 3222 * The complication here is that the hardware may have executed 3223 * beyond the xfer we're trying to abort. So as we're scanning 3224 * the TDs of this xfer we check if the hardware points to 3225 * any of them. 3226 */ 3227 3228 usb_syncmem(&sqh->dma, 3229 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3230 sizeof(sqh->qh.qh_curqtd), 3231 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3232 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3233 hit = 0; 3234 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3235 hit |= cur == sqtd->physaddr; 3236 if (sqtd == lsqtd) 3237 break; 3238 } 3239 sqtd = sqtd->nextqtd; 3240 /* Zap curqtd register if hardware pointed inside the xfer. */ 3241 if (hit && sqtd != NULL) { 3242 DPRINTF("cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3243 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3244 usb_syncmem(&sqh->dma, 3245 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3246 sizeof(sqh->qh.qh_curqtd), 3247 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3248 sqh->qh.qh_qtd.qtd_status = qhstatus; 3249 usb_syncmem(&sqh->dma, 3250 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3251 sizeof(sqh->qh.qh_qtd.qtd_status), 3252 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3253 } else { 3254 DPRINTF("no hit", 0, 0, 0, 0); 3255 usb_syncmem(&sqh->dma, 3256 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3257 sizeof(sqh->qh.qh_curqtd), 3258 BUS_DMASYNC_PREREAD); 3259 } 3260 3261 /* 3262 * Step 5: Execute callback. 3263 */ 3264 #ifdef DIAGNOSTIC 3265 exfer->ex_isdone = true; 3266 #endif 3267 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3268 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3269 usb_transfer_complete(xfer); 3270 if (wake) { 3271 cv_broadcast(&xfer->ux_hccv); 3272 } 3273 3274 KASSERT(mutex_owned(&sc->sc_lock)); 3275 } 3276 3277 Static void 3278 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3279 { 3280 ehci_isoc_trans_t trans_status; 3281 struct ehci_xfer *exfer; 3282 ehci_softc_t *sc; 3283 struct ehci_soft_itd *itd; 3284 struct ehci_soft_sitd *sitd; 3285 int i, wake; 3286 3287 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3288 3289 exfer = EHCI_XFER2EXFER(xfer); 3290 sc = EHCI_XFER2SC(xfer); 3291 3292 DPRINTF("xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3293 3294 KASSERT(mutex_owned(&sc->sc_lock)); 3295 3296 if (sc->sc_dying) { 3297 /* If we're dying, just do the software part. */ 3298 xfer->ux_status = status; 3299 callout_halt(&xfer->ux_callout, &sc->sc_lock); 3300 KASSERT(xfer->ux_status == status); 3301 usb_transfer_complete(xfer); 3302 return; 3303 } 3304 3305 if (xfer->ux_hcflags & UXFER_ABORTING) { 3306 DPRINTF("already aborting", 0, 0, 0, 0); 3307 3308 #ifdef DIAGNOSTIC 3309 if (status == USBD_TIMEOUT) 3310 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3311 #endif 3312 3313 xfer->ux_status = status; 3314 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3315 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3316 while (xfer->ux_hcflags & UXFER_ABORTING) 3317 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3318 goto done; 3319 } 3320 xfer->ux_hcflags |= UXFER_ABORTING; 3321 3322 /* 3323 * Step 1: When cancelling a transfer make sure the timeout handler 3324 * didn't run or ran to the end and saw the USBD_CANCELLED status. 3325 * Otherwise we must have got here via a timeout. 3326 */ 3327 if (status == USBD_CANCELLED) { 3328 xfer->ux_status = status; 3329 callout_halt(&xfer->ux_callout, &sc->sc_lock); 3330 } else { 3331 KASSERT(xfer->ux_status == USBD_TIMEOUT); 3332 } 3333 3334 /* 3335 * Step 2: Make interrupt routine and hardware ignore xfer. 3336 */ 3337 ehci_del_intr_list(sc, exfer); 3338 3339 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3340 for (itd = exfer->ex_itdstart; itd != NULL; 3341 itd = itd->xfer_next) { 3342 usb_syncmem(&itd->dma, 3343 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3344 sizeof(itd->itd.itd_ctl), 3345 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3346 3347 for (i = 0; i < 8; i++) { 3348 trans_status = le32toh(itd->itd.itd_ctl[i]); 3349 trans_status &= ~EHCI_ITD_ACTIVE; 3350 itd->itd.itd_ctl[i] = htole32(trans_status); 3351 } 3352 3353 usb_syncmem(&itd->dma, 3354 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3355 sizeof(itd->itd.itd_ctl), 3356 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3357 } 3358 } else { 3359 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3360 sitd = sitd->xfer_next) { 3361 usb_syncmem(&sitd->dma, 3362 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3363 sizeof(sitd->sitd.sitd_buffer), 3364 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3365 3366 trans_status = le32toh(sitd->sitd.sitd_trans); 3367 trans_status &= ~EHCI_SITD_ACTIVE; 3368 sitd->sitd.sitd_trans = htole32(trans_status); 3369 3370 usb_syncmem(&sitd->dma, 3371 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3372 sizeof(sitd->sitd.sitd_buffer), 3373 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3374 } 3375 } 3376 3377 #ifdef DIAGNOSTIC 3378 exfer->ex_isdone = true; 3379 #endif 3380 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3381 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3382 usb_transfer_complete(xfer); 3383 if (wake) { 3384 cv_broadcast(&xfer->ux_hccv); 3385 } 3386 3387 done: 3388 KASSERT(mutex_owned(&sc->sc_lock)); 3389 return; 3390 } 3391 3392 Static void 3393 ehci_timeout(void *addr) 3394 { 3395 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3396 struct usbd_xfer *xfer = addr; 3397 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3398 bool timeout = false; 3399 3400 DPRINTF("xfer %p", xfer, 0, 0, 0); 3401 #ifdef EHCI_DEBUG 3402 if (ehcidebug >= 2) { 3403 struct usbd_pipe *pipe = xfer->ux_pipe; 3404 usbd_dump_pipe(pipe); 3405 } 3406 #endif 3407 3408 mutex_enter(&sc->sc_lock); 3409 if (sc->sc_dying) { 3410 mutex_exit(&sc->sc_lock); 3411 return; 3412 } 3413 if (xfer->ux_status != USBD_CANCELLED) { 3414 xfer->ux_status = USBD_TIMEOUT; 3415 timeout = true; 3416 } 3417 mutex_exit(&sc->sc_lock); 3418 3419 if (timeout) { 3420 struct usbd_device *dev = xfer->ux_pipe->up_dev; 3421 3422 /* Execute the abort in a process context. */ 3423 usb_init_task(&xfer->ux_aborttask, ehci_timeout_task, xfer, 3424 USB_TASKQ_MPSAFE); 3425 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 3426 } 3427 } 3428 3429 Static void 3430 ehci_timeout_task(void *addr) 3431 { 3432 struct usbd_xfer *xfer = addr; 3433 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3434 3435 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3436 3437 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3438 3439 mutex_enter(&sc->sc_lock); 3440 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3441 mutex_exit(&sc->sc_lock); 3442 } 3443 3444 /************************/ 3445 3446 Static int 3447 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3448 { 3449 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3450 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3451 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3452 usb_device_request_t *req = &xfer->ux_request; 3453 ehci_soft_qtd_t *setup, *status, *next; 3454 int isread = req->bmRequestType & UT_READ; 3455 int len = xfer->ux_bufsize; 3456 int err; 3457 3458 exfer->ex_type = EX_CTRL; 3459 exfer->ex_status = NULL; 3460 exfer->ex_data = NULL; 3461 exfer->ex_setup = ehci_alloc_sqtd(sc); 3462 if (exfer->ex_setup == NULL) { 3463 err = ENOMEM; 3464 goto bad1; 3465 } 3466 exfer->ex_status = ehci_alloc_sqtd(sc); 3467 if (exfer->ex_status == NULL) { 3468 err = ENOMEM; 3469 goto bad2; 3470 } 3471 setup = exfer->ex_setup; 3472 status = exfer->ex_status; 3473 exfer->ex_nsqtd = 0; 3474 next = status; 3475 /* Set up data transaction */ 3476 if (len != 0) { 3477 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3478 &exfer->ex_data); 3479 if (err) 3480 goto bad3; 3481 next = exfer->ex_data; 3482 } 3483 3484 /* Clear toggle */ 3485 setup->qtd.qtd_status = htole32( 3486 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3487 EHCI_QTD_SET_TOGGLE(0) | 3488 EHCI_QTD_SET_BYTES(sizeof(*req)) 3489 ); 3490 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3491 setup->qtd.qtd_buffer_hi[0] = 0; 3492 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3493 setup->nextqtd = next; 3494 setup->xfer = xfer; 3495 setup->len = sizeof(*req); 3496 3497 status->qtd.qtd_status = htole32( 3498 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3499 EHCI_QTD_SET_TOGGLE(1) | 3500 EHCI_QTD_IOC 3501 ); 3502 status->qtd.qtd_buffer[0] = 0; 3503 status->qtd.qtd_buffer_hi[0] = 0; 3504 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3505 status->nextqtd = NULL; 3506 status->xfer = xfer; 3507 status->len = 0; 3508 3509 return 0; 3510 bad3: 3511 ehci_free_sqtd(sc, exfer->ex_status); 3512 bad2: 3513 ehci_free_sqtd(sc, exfer->ex_setup); 3514 bad1: 3515 return err; 3516 } 3517 3518 Static void 3519 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3520 { 3521 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3522 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3523 3524 KASSERT(ex->ex_type == EX_CTRL); 3525 3526 ehci_free_sqtd(sc, ex->ex_setup); 3527 ehci_free_sqtd(sc, ex->ex_status); 3528 ehci_free_sqtds(sc, ex); 3529 if (ex->ex_nsqtd) 3530 kmem_free(ex->ex_sqtds, 3531 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3532 } 3533 3534 Static usbd_status 3535 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3536 { 3537 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3538 usbd_status err; 3539 3540 /* Insert last in queue. */ 3541 mutex_enter(&sc->sc_lock); 3542 err = usb_insert_transfer(xfer); 3543 mutex_exit(&sc->sc_lock); 3544 if (err) 3545 return err; 3546 3547 /* Pipe isn't running, start first */ 3548 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3549 } 3550 3551 Static usbd_status 3552 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3553 { 3554 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3555 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3556 usb_device_request_t *req = &xfer->ux_request; 3557 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3558 ehci_soft_qtd_t *setup, *status, *next; 3559 ehci_soft_qh_t *sqh; 3560 3561 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3562 3563 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3564 3565 if (sc->sc_dying) 3566 return USBD_IOERROR; 3567 3568 const int isread = req->bmRequestType & UT_READ; 3569 const int len = UGETW(req->wLength); 3570 3571 DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x", 3572 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3573 UGETW(req->wIndex)); 3574 DPRINTF("len=%d, addr=%d, endpt=%d", len, epipe->pipe.up_dev->ud_addr, 3575 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3576 3577 sqh = epipe->sqh; 3578 3579 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3580 "address QH %" __PRIuBIT " pipe %d\n", 3581 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3582 epipe->pipe.up_dev->ud_addr); 3583 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3584 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3585 "MPS QH %" __PRIuBIT " pipe %d\n", 3586 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3587 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3588 3589 setup = exfer->ex_setup; 3590 status = exfer->ex_status; 3591 3592 DPRINTF("setup %p status %p data %p", setup, status, exfer->ex_data, 0); 3593 KASSERTMSG(setup != NULL && status != NULL, 3594 "Failed memory allocation, setup %p status %p", 3595 setup, status); 3596 3597 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3598 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3599 3600 /* Clear toggle */ 3601 setup->qtd.qtd_status &= ~htole32( 3602 EHCI_QTD_STATUS_MASK | 3603 EHCI_QTD_BYTES_MASK | 3604 EHCI_QTD_TOGGLE_MASK | 3605 EHCI_QTD_CERR_MASK 3606 ); 3607 setup->qtd.qtd_status |= htole32( 3608 EHCI_QTD_ACTIVE | 3609 EHCI_QTD_SET_CERR(3) | 3610 EHCI_QTD_SET_TOGGLE(0) | 3611 EHCI_QTD_SET_BYTES(sizeof(*req)) 3612 ); 3613 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3614 setup->qtd.qtd_buffer_hi[0] = 0; 3615 3616 next = status; 3617 status->qtd.qtd_status &= ~htole32( 3618 EHCI_QTD_STATUS_MASK | 3619 EHCI_QTD_PID_MASK | 3620 EHCI_QTD_BYTES_MASK | 3621 EHCI_QTD_TOGGLE_MASK | 3622 EHCI_QTD_CERR_MASK 3623 ); 3624 status->qtd.qtd_status |= htole32( 3625 EHCI_QTD_ACTIVE | 3626 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3627 EHCI_QTD_SET_CERR(3) | 3628 EHCI_QTD_SET_TOGGLE(1) | 3629 EHCI_QTD_SET_BYTES(0) | 3630 EHCI_QTD_IOC 3631 ); 3632 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3633 3634 KASSERT(exfer->ex_isdone); 3635 #ifdef DIAGNOSTIC 3636 exfer->ex_isdone = false; 3637 #endif 3638 3639 /* Set up data transaction */ 3640 if (len != 0) { 3641 ehci_soft_qtd_t *end; 3642 3643 /* Start toggle at 1. */ 3644 int toggle = 1; 3645 next = exfer->ex_data; 3646 KASSERTMSG(next != NULL, "Failed memory allocation"); 3647 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3648 end->nextqtd = status; 3649 end->qtd.qtd_next = end->qtd.qtd_altnext = 3650 htole32(status->physaddr); 3651 3652 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3653 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3654 3655 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3656 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3657 } 3658 3659 setup->nextqtd = next; 3660 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3661 3662 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3663 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3664 3665 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3666 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3667 3668 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3669 3670 #ifdef EHCI_DEBUG 3671 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3672 ehci_dump_sqh(sqh); 3673 ehci_dump_sqtds(setup); 3674 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3675 #endif 3676 3677 mutex_enter(&sc->sc_lock); 3678 3679 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3680 ehci_set_qh_qtd(sqh, setup); 3681 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3682 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3683 ehci_timeout, xfer); 3684 } 3685 ehci_add_intr_list(sc, exfer); 3686 xfer->ux_status = USBD_IN_PROGRESS; 3687 mutex_exit(&sc->sc_lock); 3688 3689 #if 0 3690 #ifdef EHCI_DEBUG 3691 DPRINTFN(10, "status=%x, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3692 // delay(10000); 3693 ehci_dump_regs(sc); 3694 ehci_dump_sqh(sc->sc_async_head); 3695 ehci_dump_sqh(sqh); 3696 ehci_dump_sqtds(setup); 3697 #endif 3698 #endif 3699 3700 return USBD_IN_PROGRESS; 3701 } 3702 3703 Static void 3704 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3705 { 3706 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3707 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3708 usb_device_request_t *req = &xfer->ux_request; 3709 int len = UGETW(req->wLength); 3710 int rd = req->bmRequestType & UT_READ; 3711 3712 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3713 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3714 3715 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3716 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3717 3718 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3719 BUS_DMASYNC_POSTWRITE); 3720 if (len) 3721 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3722 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3723 3724 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3725 } 3726 3727 /* Abort a device control request. */ 3728 Static void 3729 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3730 { 3731 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3732 3733 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3734 ehci_abort_xfer(xfer, USBD_CANCELLED); 3735 } 3736 3737 /* Close a device control pipe. */ 3738 Static void 3739 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3740 { 3741 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3742 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3743 3744 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3745 3746 KASSERT(mutex_owned(&sc->sc_lock)); 3747 3748 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3749 3750 ehci_close_pipe(pipe, sc->sc_async_head); 3751 } 3752 3753 /* 3754 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3755 * qTD status, or miss signalling occasionally under heavy load. If the host 3756 * machine is too fast, we we can miss transaction completion - when we scan 3757 * the active list the transaction still seems to be active. This generally 3758 * exhibits itself as a umass stall that never recovers. 3759 * 3760 * We work around this behaviour by setting up this callback after any softintr 3761 * that completes with transactions still pending, giving us another chance to 3762 * check for completion after the writeback has taken place. 3763 */ 3764 Static void 3765 ehci_intrlist_timeout(void *arg) 3766 { 3767 ehci_softc_t *sc = arg; 3768 3769 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3770 3771 usb_schedsoftintr(&sc->sc_bus); 3772 } 3773 3774 /************************/ 3775 3776 Static int 3777 ehci_device_bulk_init(struct usbd_xfer *xfer) 3778 { 3779 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3780 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3781 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3782 int endpt = ed->bEndpointAddress; 3783 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3784 int len = xfer->ux_bufsize; 3785 int err = 0; 3786 3787 exfer->ex_type = EX_BULK; 3788 exfer->ex_nsqtd = 0; 3789 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3790 &exfer->ex_sqtdstart); 3791 3792 return err; 3793 } 3794 3795 Static void 3796 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3797 { 3798 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3799 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3800 3801 KASSERT(ex->ex_type == EX_BULK); 3802 3803 ehci_free_sqtds(sc, ex); 3804 if (ex->ex_nsqtd) 3805 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3806 } 3807 3808 Static usbd_status 3809 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3810 { 3811 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3812 usbd_status err; 3813 3814 /* Insert last in queue. */ 3815 mutex_enter(&sc->sc_lock); 3816 err = usb_insert_transfer(xfer); 3817 mutex_exit(&sc->sc_lock); 3818 if (err) 3819 return err; 3820 3821 /* Pipe isn't running, start first */ 3822 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3823 } 3824 3825 Static usbd_status 3826 ehci_device_bulk_start(struct usbd_xfer *xfer) 3827 { 3828 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3829 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3830 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3831 ehci_soft_qh_t *sqh; 3832 ehci_soft_qtd_t *end; 3833 int len, isread, endpt; 3834 3835 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3836 3837 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3838 xfer->ux_flags, 0); 3839 3840 if (sc->sc_dying) 3841 return USBD_IOERROR; 3842 3843 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3844 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3845 3846 len = xfer->ux_length; 3847 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3848 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3849 sqh = epipe->sqh; 3850 3851 KASSERT(exfer->ex_isdone); 3852 #ifdef DIAGNOSTIC 3853 exfer->ex_isdone = false; 3854 #endif 3855 3856 /* Take lock here to protect nexttoggle */ 3857 mutex_enter(&sc->sc_lock); 3858 3859 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3860 3861 exfer->ex_sqtdend = end; 3862 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3863 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3864 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3865 3866 #ifdef EHCI_DEBUG 3867 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3868 ehci_dump_sqh(sqh); 3869 ehci_dump_sqtds(exfer->ex_sqtdstart); 3870 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3871 #endif 3872 3873 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3874 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3875 3876 /* also does usb_syncmem(sqh) */ 3877 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3878 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3879 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3880 ehci_timeout, xfer); 3881 } 3882 ehci_add_intr_list(sc, exfer); 3883 xfer->ux_status = USBD_IN_PROGRESS; 3884 mutex_exit(&sc->sc_lock); 3885 3886 #if 0 3887 #ifdef EHCI_DEBUG 3888 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3889 // delay(10000); 3890 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3891 ehci_dump_regs(sc); 3892 #if 0 3893 printf("async_head:\n"); 3894 ehci_dump_sqh(sc->sc_async_head); 3895 #endif 3896 DPRINTF("sqh:", 0, 0, 0, 0); 3897 ehci_dump_sqh(sqh); 3898 ehci_dump_sqtds(exfer->ex_sqtdstart); 3899 #endif 3900 #endif 3901 3902 return USBD_IN_PROGRESS; 3903 } 3904 3905 Static void 3906 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3907 { 3908 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3909 3910 DPRINTF("xfer %p", xfer, 0, 0, 0); 3911 ehci_abort_xfer(xfer, USBD_CANCELLED); 3912 } 3913 3914 /* 3915 * Close a device bulk pipe. 3916 */ 3917 Static void 3918 ehci_device_bulk_close(struct usbd_pipe *pipe) 3919 { 3920 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3921 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3922 3923 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3924 3925 KASSERT(mutex_owned(&sc->sc_lock)); 3926 3927 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3928 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3929 ehci_close_pipe(pipe, sc->sc_async_head); 3930 } 3931 3932 Static void 3933 ehci_device_bulk_done(struct usbd_xfer *xfer) 3934 { 3935 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3936 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3937 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3938 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3939 3940 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3941 3942 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 3943 3944 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3945 3946 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3947 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3948 3949 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3950 } 3951 3952 /************************/ 3953 3954 Static usbd_status 3955 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3956 { 3957 struct ehci_soft_islot *isp; 3958 int islot, lev; 3959 3960 /* Find a poll rate that is large enough. */ 3961 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3962 if (EHCI_ILEV_IVAL(lev) <= ival) 3963 break; 3964 3965 /* Pick an interrupt slot at the right level. */ 3966 /* XXX could do better than picking at random */ 3967 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3968 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3969 3970 sqh->islot = islot; 3971 isp = &sc->sc_islots[islot]; 3972 mutex_enter(&sc->sc_lock); 3973 ehci_add_qh(sc, sqh, isp->sqh); 3974 mutex_exit(&sc->sc_lock); 3975 3976 return USBD_NORMAL_COMPLETION; 3977 } 3978 3979 3980 Static int 3981 ehci_device_intr_init(struct usbd_xfer *xfer) 3982 { 3983 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3984 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3985 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3986 int endpt = ed->bEndpointAddress; 3987 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3988 int len = xfer->ux_bufsize; 3989 int err; 3990 3991 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3992 3993 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3994 xfer->ux_flags, 0); 3995 3996 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3997 KASSERT(len != 0); 3998 3999 exfer->ex_type = EX_INTR; 4000 exfer->ex_nsqtd = 0; 4001 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4002 &exfer->ex_sqtdstart); 4003 4004 return err; 4005 } 4006 4007 Static void 4008 ehci_device_intr_fini(struct usbd_xfer *xfer) 4009 { 4010 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4011 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4012 4013 KASSERT(ex->ex_type == EX_INTR); 4014 4015 ehci_free_sqtds(sc, ex); 4016 if (ex->ex_nsqtd) 4017 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4018 } 4019 4020 Static usbd_status 4021 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4022 { 4023 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4024 usbd_status err; 4025 4026 /* Insert last in queue. */ 4027 mutex_enter(&sc->sc_lock); 4028 err = usb_insert_transfer(xfer); 4029 mutex_exit(&sc->sc_lock); 4030 if (err) 4031 return err; 4032 4033 /* 4034 * Pipe isn't running (otherwise err would be USBD_INPROG), 4035 * so start it first. 4036 */ 4037 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4038 } 4039 4040 Static usbd_status 4041 ehci_device_intr_start(struct usbd_xfer *xfer) 4042 { 4043 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4044 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4045 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4046 ehci_soft_qtd_t *end; 4047 ehci_soft_qh_t *sqh; 4048 int len, isread, endpt; 4049 4050 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4051 4052 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4053 xfer->ux_flags, 0); 4054 4055 if (sc->sc_dying) 4056 return USBD_IOERROR; 4057 4058 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4059 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4060 4061 len = xfer->ux_length; 4062 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4063 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4064 sqh = epipe->sqh; 4065 4066 KASSERT(exfer->ex_isdone); 4067 #ifdef DIAGNOSTIC 4068 exfer->ex_isdone = false; 4069 #endif 4070 4071 /* Take lock to protect nexttoggle */ 4072 mutex_enter(&sc->sc_lock); 4073 4074 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4075 4076 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4077 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4078 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4079 exfer->ex_sqtdend = end; 4080 4081 #ifdef EHCI_DEBUG 4082 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4083 ehci_dump_sqh(sqh); 4084 ehci_dump_sqtds(exfer->ex_sqtdstart); 4085 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4086 #endif 4087 4088 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4089 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4090 4091 /* also does usb_syncmem(sqh) */ 4092 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4093 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4094 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4095 ehci_timeout, xfer); 4096 } 4097 ehci_add_intr_list(sc, exfer); 4098 xfer->ux_status = USBD_IN_PROGRESS; 4099 mutex_exit(&sc->sc_lock); 4100 4101 #if 0 4102 #ifdef EHCI_DEBUG 4103 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4104 // delay(10000); 4105 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4106 ehci_dump_regs(sc); 4107 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4108 ehci_dump_sqh(sqh); 4109 ehci_dump_sqtds(exfer->ex_sqtdstart); 4110 #endif 4111 #endif 4112 4113 return USBD_IN_PROGRESS; 4114 } 4115 4116 Static void 4117 ehci_device_intr_abort(struct usbd_xfer *xfer) 4118 { 4119 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4120 4121 DPRINTF("xfer=%p", xfer, 0, 0, 0); 4122 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4123 4124 /* 4125 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4126 * async doorbell. That's dependent on the async list, wheras 4127 * intr xfers are periodic, should not use this? 4128 */ 4129 ehci_abort_xfer(xfer, USBD_CANCELLED); 4130 } 4131 4132 Static void 4133 ehci_device_intr_close(struct usbd_pipe *pipe) 4134 { 4135 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4136 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4137 struct ehci_soft_islot *isp; 4138 4139 KASSERT(mutex_owned(&sc->sc_lock)); 4140 4141 isp = &sc->sc_islots[epipe->sqh->islot]; 4142 ehci_close_pipe(pipe, isp->sqh); 4143 } 4144 4145 Static void 4146 ehci_device_intr_done(struct usbd_xfer *xfer) 4147 { 4148 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4149 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4150 int isread, endpt; 4151 4152 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4153 4154 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4155 0, 0); 4156 4157 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4158 4159 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4160 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4161 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4162 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4163 } 4164 4165 /************************/ 4166 Static int 4167 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4168 { 4169 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4170 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4171 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4172 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4173 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4174 int i, k, frames; 4175 u_int huba, dir; 4176 int err; 4177 4178 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4179 4180 start = NULL; 4181 sitd = NULL; 4182 4183 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4184 xfer->ux_flags, 0); 4185 4186 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4187 KASSERT(xfer->ux_nframes != 0); 4188 KASSERT(exfer->ex_isdone); 4189 4190 exfer->ex_type = EX_FS_ISOC; 4191 /* 4192 * Step 1: Allocate and initialize sitds. 4193 */ 4194 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4195 if (i > 16 || i == 0) { 4196 /* Spec page 271 says intervals > 16 are invalid */ 4197 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4198 4199 return EINVAL; 4200 } 4201 4202 frames = xfer->ux_nframes; 4203 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4204 sitd = ehci_alloc_sitd(sc); 4205 if (sitd == NULL) { 4206 err = ENOMEM; 4207 goto fail; 4208 } 4209 4210 if (prev) 4211 prev->xfer_next = sitd; 4212 else 4213 start = sitd; 4214 4215 huba = dev->ud_myhsport->up_parent->ud_addr; 4216 4217 #if 0 4218 if (sc->sc_flags & EHCIF_FREESCALE) { 4219 // Set hub address to 0 if embedded TT is used. 4220 if (huba == sc->sc_addr) 4221 huba = 0; 4222 } 4223 #endif 4224 4225 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4226 dir = UE_GET_DIR(k) ? 1 : 0; 4227 sitd->sitd.sitd_endp = 4228 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4229 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4230 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4231 EHCI_SITD_SET_HUBA(huba) | 4232 EHCI_SITD_SET_DIR(dir)); 4233 4234 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4235 } /* End of frame */ 4236 4237 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4238 4239 stop = sitd; 4240 stop->xfer_next = NULL; 4241 exfer->ex_sitdstart = start; 4242 exfer->ex_sitdend = stop; 4243 4244 return 0; 4245 4246 fail: 4247 mutex_enter(&sc->sc_lock); 4248 ehci_soft_sitd_t *next; 4249 for (sitd = start; sitd; sitd = next) { 4250 next = sitd->xfer_next; 4251 ehci_free_sitd_locked(sc, sitd); 4252 } 4253 mutex_exit(&sc->sc_lock); 4254 4255 return err; 4256 } 4257 4258 Static void 4259 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4260 { 4261 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4262 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4263 4264 KASSERT(ex->ex_type == EX_FS_ISOC); 4265 4266 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4267 } 4268 4269 Static usbd_status 4270 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4271 { 4272 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4273 usbd_status __diagused err; 4274 4275 mutex_enter(&sc->sc_lock); 4276 err = usb_insert_transfer(xfer); 4277 mutex_exit(&sc->sc_lock); 4278 4279 KASSERT(err == USBD_NORMAL_COMPLETION); 4280 4281 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4282 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4283 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4284 ehci_soft_sitd_t *sitd; 4285 usb_dma_t *dma_buf; 4286 int i, j, k, frames; 4287 int offs, total_length; 4288 int frindex; 4289 u_int dir; 4290 4291 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4292 4293 sitd = NULL; 4294 total_length = 0; 4295 4296 4297 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4298 xfer->ux_flags, 0); 4299 4300 if (sc->sc_dying) 4301 return USBD_IOERROR; 4302 4303 /* 4304 * To avoid complication, don't allow a request right now that'll span 4305 * the entire frame table. To within 4 frames, to allow some leeway 4306 * on either side of where the hc currently is. 4307 */ 4308 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4309 xfer->ux_nframes >= sc->sc_flsize - 4) { 4310 printf("ehci: isoc descriptor requested that spans the entire" 4311 "frametable, too many frames\n"); 4312 return USBD_INVAL; 4313 } 4314 4315 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4316 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4317 KASSERT(exfer->ex_isdone); 4318 #ifdef DIAGNOSTIC 4319 exfer->ex_isdone = false; 4320 #endif 4321 4322 /* 4323 * Step 1: Initialize sitds. 4324 */ 4325 4326 frames = xfer->ux_nframes; 4327 dma_buf = &xfer->ux_dmabuf; 4328 offs = 0; 4329 4330 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4331 i++, sitd = sitd->xfer_next) { 4332 KASSERT(sitd != NULL); 4333 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4334 4335 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4336 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4337 4338 /* Set page0 index and offset - TP and T-offset are set below */ 4339 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4340 4341 total_length += xfer->ux_frlengths[i]; 4342 offs += xfer->ux_frlengths[i]; 4343 4344 sitd->sitd.sitd_buffer[1] = 4345 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4346 4347 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4348 4349 #if 0 4350 if (sc->sc_flags & EHCIF_FREESCALE) { 4351 // Set hub address to 0 if embedded TT is used. 4352 if (huba == sc->sc_addr) 4353 huba = 0; 4354 } 4355 #endif 4356 4357 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4358 dir = UE_GET_DIR(k) ? 1 : 0; 4359 KASSERT(sitd->sitd.sitd_endp == htole32( 4360 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4361 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4362 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4363 EHCI_SITD_SET_HUBA(huba) | 4364 EHCI_SITD_SET_DIR(dir))); 4365 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4366 4367 uint8_t sa = 0; 4368 uint8_t sb = 0; 4369 u_int temp, tlen; 4370 4371 if (dir == 0) { /* OUT */ 4372 temp = 0; 4373 tlen = xfer->ux_frlengths[i]; 4374 if (tlen <= 188) { 4375 temp |= 1; /* T-count = 1, TP = ALL */ 4376 tlen = 1; 4377 } else { 4378 tlen += 187; 4379 tlen /= 188; 4380 temp |= tlen; /* T-count = [1..6] */ 4381 temp |= 8; /* TP = Begin */ 4382 } 4383 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4384 4385 tlen += sa; 4386 4387 if (tlen >= 8) { 4388 sb = 0; 4389 } else { 4390 sb = (1 << tlen); 4391 } 4392 4393 sa = (1 << sa); 4394 sa = (sb - sa) & 0x3F; 4395 sb = 0; 4396 } else { 4397 sb = (-(4 << sa)) & 0xFE; 4398 sa = (1 << sa) & 0x3F; 4399 sa = 0x01; 4400 sb = 0xfc; 4401 } 4402 4403 sitd->sitd.sitd_sched = htole32( 4404 EHCI_SITD_SET_SMASK(sa) | 4405 EHCI_SITD_SET_CMASK(sb) 4406 ); 4407 4408 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4409 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4410 } /* End of frame */ 4411 4412 sitd = exfer->ex_sitdend; 4413 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4414 4415 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4416 sizeof(sitd->sitd.sitd_trans), 4417 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4418 4419 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4420 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4421 4422 /* 4423 * Part 2: Transfer descriptors have now been set up, now they must 4424 * be scheduled into the periodic frame list. Erk. Not wanting to 4425 * complicate matters, transfer is denied if the transfer spans 4426 * more than the period frame list. 4427 */ 4428 4429 mutex_enter(&sc->sc_lock); 4430 4431 /* Start inserting frames */ 4432 if (epipe->isoc.cur_xfers > 0) { 4433 frindex = epipe->isoc.next_frame; 4434 } else { 4435 frindex = EOREAD4(sc, EHCI_FRINDEX); 4436 frindex = frindex >> 3; /* Erase microframe index */ 4437 frindex += 2; 4438 } 4439 4440 if (frindex >= sc->sc_flsize) 4441 frindex &= (sc->sc_flsize - 1); 4442 4443 /* Whats the frame interval? */ 4444 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4445 4446 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4447 j++, sitd = sitd->xfer_next) { 4448 KASSERT(sitd); 4449 4450 usb_syncmem(&sc->sc_fldma, 4451 sizeof(ehci_link_t) * frindex, 4452 sizeof(ehci_link_t), 4453 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4454 4455 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4456 if (sitd->sitd.sitd_next == 0) 4457 /* 4458 * FIXME: frindex table gets initialized to NULL 4459 * or EHCI_NULL? 4460 */ 4461 sitd->sitd.sitd_next = EHCI_NULL; 4462 4463 usb_syncmem(&sitd->dma, 4464 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4465 sizeof(ehci_sitd_t), 4466 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4467 4468 sc->sc_flist[frindex] = 4469 htole32(EHCI_LINK_SITD | sitd->physaddr); 4470 4471 usb_syncmem(&sc->sc_fldma, 4472 sizeof(ehci_link_t) * frindex, 4473 sizeof(ehci_link_t), 4474 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4475 4476 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4477 sc->sc_softsitds[frindex] = sitd; 4478 if (sitd->frame_list.next != NULL) 4479 sitd->frame_list.next->frame_list.prev = sitd; 4480 sitd->slot = frindex; 4481 sitd->frame_list.prev = NULL; 4482 4483 frindex += i; 4484 if (frindex >= sc->sc_flsize) 4485 frindex -= sc->sc_flsize; 4486 } 4487 4488 epipe->isoc.cur_xfers++; 4489 epipe->isoc.next_frame = frindex; 4490 4491 ehci_add_intr_list(sc, exfer); 4492 xfer->ux_status = USBD_IN_PROGRESS; 4493 4494 mutex_exit(&sc->sc_lock); 4495 4496 return USBD_IN_PROGRESS; 4497 } 4498 4499 Static void 4500 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4501 { 4502 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4503 4504 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4505 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4506 } 4507 4508 Static void 4509 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4510 { 4511 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4512 4513 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4514 } 4515 4516 Static void 4517 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4518 { 4519 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4520 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4521 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4522 4523 KASSERT(mutex_owned(&sc->sc_lock)); 4524 4525 epipe->isoc.cur_xfers--; 4526 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4527 4528 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4529 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4530 } 4531 4532 4533 /************************/ 4534 4535 4536 Static int 4537 ehci_device_isoc_init(struct usbd_xfer *xfer) 4538 { 4539 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4540 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4541 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4542 ehci_soft_itd_t *itd, *prev, *start, *stop; 4543 int i, j, k; 4544 int frames, ufrperframe; 4545 int err; 4546 4547 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4548 4549 start = NULL; 4550 prev = NULL; 4551 itd = NULL; 4552 4553 KASSERT(xfer->ux_nframes != 0); 4554 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4555 KASSERT(exfer->ex_isdone); 4556 4557 exfer->ex_type = EX_ISOC; 4558 4559 /* 4560 * Step 1: Allocate and initialize itds, how many do we need? 4561 * One per transfer if interval >= 8 microframes, less if we use 4562 * multiple microframes per frame. 4563 */ 4564 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4565 if (i > 16 || i == 0) { 4566 /* Spec page 271 says intervals > 16 are invalid */ 4567 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4568 return USBD_INVAL; 4569 } 4570 4571 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4572 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4573 4574 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4575 itd = ehci_alloc_itd(sc); 4576 if (itd == NULL) { 4577 err = ENOMEM; 4578 goto fail; 4579 } 4580 4581 if (prev != NULL) { 4582 /* Maybe not as it's updated by the scheduling? */ 4583 prev->itd.itd_next = 4584 htole32(itd->physaddr | EHCI_LINK_ITD); 4585 4586 prev->xfer_next = itd; 4587 } else { 4588 start = itd; 4589 } 4590 4591 /* 4592 * Other special values 4593 */ 4594 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4595 itd->itd.itd_bufr[0] = htole32( 4596 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4597 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4598 4599 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4600 ? 1 : 0; 4601 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4602 itd->itd.itd_bufr[1] |= htole32( 4603 EHCI_ITD_SET_DIR(k) | 4604 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4605 4606 /* FIXME: handle invalid trans - should be done in openpipe */ 4607 itd->itd.itd_bufr[2] |= 4608 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4609 } /* End of frame */ 4610 4611 stop = itd; 4612 stop->xfer_next = NULL; 4613 4614 exfer->ex_itdstart = start; 4615 exfer->ex_itdend = stop; 4616 4617 return 0; 4618 fail: 4619 mutex_enter(&sc->sc_lock); 4620 ehci_soft_itd_t *next; 4621 for (itd = start; itd; itd = next) { 4622 next = itd->xfer_next; 4623 ehci_free_itd_locked(sc, itd); 4624 } 4625 mutex_exit(&sc->sc_lock); 4626 4627 return err; 4628 4629 } 4630 4631 Static void 4632 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4633 { 4634 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4635 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4636 4637 KASSERT(ex->ex_type == EX_ISOC); 4638 4639 ehci_free_itd_chain(sc, ex->ex_itdstart); 4640 } 4641 4642 Static usbd_status 4643 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4644 { 4645 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4646 usbd_status __diagused err; 4647 4648 mutex_enter(&sc->sc_lock); 4649 err = usb_insert_transfer(xfer); 4650 mutex_exit(&sc->sc_lock); 4651 4652 KASSERT(err == USBD_NORMAL_COMPLETION); 4653 4654 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4655 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4656 ehci_soft_itd_t *itd, *prev; 4657 usb_dma_t *dma_buf; 4658 int i, j; 4659 int frames, uframes, ufrperframe; 4660 int trans_count, offs, total_length; 4661 int frindex; 4662 4663 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4664 4665 prev = NULL; 4666 itd = NULL; 4667 trans_count = 0; 4668 total_length = 0; 4669 4670 DPRINTF("xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4671 4672 if (sc->sc_dying) 4673 return USBD_IOERROR; 4674 4675 /* 4676 * To avoid complication, don't allow a request right now that'll span 4677 * the entire frame table. To within 4 frames, to allow some leeway 4678 * on either side of where the hc currently is. 4679 */ 4680 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4681 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4682 DPRINTF( 4683 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4684 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4685 return USBD_INVAL; 4686 } 4687 4688 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4689 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4690 KASSERT(exfer->ex_isdone); 4691 #ifdef DIAGNOSTIC 4692 exfer->ex_isdone = false; 4693 #endif 4694 4695 /* 4696 * Step 1: Re-Initialize itds 4697 */ 4698 4699 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4700 if (i > 16 || i == 0) { 4701 /* Spec page 271 says intervals > 16 are invalid */ 4702 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4703 return USBD_INVAL; 4704 } 4705 4706 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4707 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4708 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4709 4710 if (frames == 0) { 4711 DPRINTF("frames == 0", 0, 0, 0, 0); 4712 return USBD_INVAL; 4713 } 4714 4715 dma_buf = &xfer->ux_dmabuf; 4716 offs = 0; 4717 4718 itd = exfer->ex_itdstart; 4719 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4720 int froffs = offs; 4721 4722 if (prev != NULL) { 4723 prev->itd.itd_next = 4724 htole32(itd->physaddr | EHCI_LINK_ITD); 4725 usb_syncmem(&prev->dma, 4726 prev->offs + offsetof(ehci_itd_t, itd_next), 4727 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4728 prev->xfer_next = itd; 4729 } 4730 4731 /* 4732 * Step 1.5, initialize uframes 4733 */ 4734 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4735 /* Calculate which page in the list this starts in */ 4736 int addr = DMAADDR(dma_buf, froffs); 4737 addr = EHCI_PAGE_OFFSET(addr); 4738 addr += (offs - froffs); 4739 addr = EHCI_PAGE(addr); 4740 addr /= EHCI_PAGE_SIZE; 4741 4742 /* 4743 * This gets the initial offset into the first page, 4744 * looks how far further along the current uframe 4745 * offset is. Works out how many pages that is. 4746 */ 4747 4748 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4749 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4750 EHCI_ITD_SET_PG(addr) | 4751 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4752 4753 total_length += xfer->ux_frlengths[trans_count]; 4754 offs += xfer->ux_frlengths[trans_count]; 4755 trans_count++; 4756 4757 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4758 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4759 break; 4760 } 4761 } 4762 4763 /* 4764 * Step 1.75, set buffer pointers. To simplify matters, all 4765 * pointers are filled out for the next 7 hardware pages in 4766 * the dma block, so no need to worry what pages to cover 4767 * and what to not. 4768 */ 4769 4770 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4771 /* 4772 * Don't try to lookup a page that's past the end 4773 * of buffer 4774 */ 4775 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4776 if (page_offs >= dma_buf->udma_block->size) 4777 break; 4778 4779 uint64_t page = DMAADDR(dma_buf, page_offs); 4780 page = EHCI_PAGE(page); 4781 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4782 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4783 } 4784 /* 4785 * Other special values 4786 */ 4787 4788 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4789 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4790 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4791 4792 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4793 ? 1 : 0; 4794 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4795 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4796 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4797 4798 /* FIXME: handle invalid trans */ 4799 itd->itd.itd_bufr[2] |= 4800 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4801 4802 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4803 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4804 4805 prev = itd; 4806 } /* End of frame */ 4807 4808 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4809 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4810 4811 /* 4812 * Part 2: Transfer descriptors have now been set up, now they must 4813 * be scheduled into the period frame list. Erk. Not wanting to 4814 * complicate matters, transfer is denied if the transfer spans 4815 * more than the period frame list. 4816 */ 4817 4818 mutex_enter(&sc->sc_lock); 4819 4820 /* Start inserting frames */ 4821 if (epipe->isoc.cur_xfers > 0) { 4822 frindex = epipe->isoc.next_frame; 4823 } else { 4824 frindex = EOREAD4(sc, EHCI_FRINDEX); 4825 frindex = frindex >> 3; /* Erase microframe index */ 4826 frindex += 2; 4827 } 4828 4829 if (frindex >= sc->sc_flsize) 4830 frindex &= (sc->sc_flsize - 1); 4831 4832 /* What's the frame interval? */ 4833 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4834 if (i / USB_UFRAMES_PER_FRAME == 0) 4835 i = 1; 4836 else 4837 i /= USB_UFRAMES_PER_FRAME; 4838 4839 itd = exfer->ex_itdstart; 4840 for (j = 0; j < frames; j++) { 4841 KASSERTMSG(itd != NULL, "frame %d\n", j); 4842 4843 usb_syncmem(&sc->sc_fldma, 4844 sizeof(ehci_link_t) * frindex, 4845 sizeof(ehci_link_t), 4846 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4847 4848 itd->itd.itd_next = sc->sc_flist[frindex]; 4849 if (itd->itd.itd_next == 0) 4850 /* 4851 * FIXME: frindex table gets initialized to NULL 4852 * or EHCI_NULL? 4853 */ 4854 itd->itd.itd_next = EHCI_NULL; 4855 4856 usb_syncmem(&itd->dma, 4857 itd->offs + offsetof(ehci_itd_t, itd_next), 4858 sizeof(itd->itd.itd_next), 4859 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4860 4861 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4862 4863 usb_syncmem(&sc->sc_fldma, 4864 sizeof(ehci_link_t) * frindex, 4865 sizeof(ehci_link_t), 4866 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4867 4868 itd->frame_list.next = sc->sc_softitds[frindex]; 4869 sc->sc_softitds[frindex] = itd; 4870 if (itd->frame_list.next != NULL) 4871 itd->frame_list.next->frame_list.prev = itd; 4872 itd->slot = frindex; 4873 itd->frame_list.prev = NULL; 4874 4875 frindex += i; 4876 if (frindex >= sc->sc_flsize) 4877 frindex -= sc->sc_flsize; 4878 4879 itd = itd->xfer_next; 4880 } 4881 4882 epipe->isoc.cur_xfers++; 4883 epipe->isoc.next_frame = frindex; 4884 4885 ehci_add_intr_list(sc, exfer); 4886 xfer->ux_status = USBD_IN_PROGRESS; 4887 4888 mutex_exit(&sc->sc_lock); 4889 4890 return USBD_IN_PROGRESS; 4891 } 4892 4893 Static void 4894 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4895 { 4896 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4897 4898 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4899 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4900 } 4901 4902 Static void 4903 ehci_device_isoc_close(struct usbd_pipe *pipe) 4904 { 4905 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4906 4907 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4908 } 4909 4910 Static void 4911 ehci_device_isoc_done(struct usbd_xfer *xfer) 4912 { 4913 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4914 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4915 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4916 4917 KASSERT(mutex_owned(&sc->sc_lock)); 4918 4919 epipe->isoc.cur_xfers--; 4920 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4921 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4922 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4923 } 4924
Indexes created Wed Oct 01 19:09:53 GMT 2025