ehci.c revision 1.234.2.109
1 /* $NetBSD: ehci.c,v 1.234.2.109 2017/08/28 17:52:27 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.109 2017/08/28 17:52:27 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 61 #ifdef _KERNEL_OPT 62 #include "opt_usb.h" 63 #endif 64 65 #include <sys/param.h> 66 67 #include <sys/bus.h> 68 #include <sys/cpu.h> 69 #include <sys/device.h> 70 #include <sys/kernel.h> 71 #include <sys/kmem.h> 72 #include <sys/mutex.h> 73 #include <sys/proc.h> 74 #include <sys/queue.h> 75 #include <sys/select.h> 76 #include <sys/sysctl.h> 77 #include <sys/systm.h> 78 79 #include <machine/endian.h> 80 81 #include <dev/usb/usb.h> 82 #include <dev/usb/usbdi.h> 83 #include <dev/usb/usbdivar.h> 84 #include <dev/usb/usbhist.h> 85 #include <dev/usb/usb_mem.h> 86 #include <dev/usb/usb_quirks.h> 87 88 #include <dev/usb/ehcireg.h> 89 #include <dev/usb/ehcivar.h> 90 #include <dev/usb/usbroothub.h> 91 92 93 #ifdef USB_DEBUG 94 #ifndef EHCI_DEBUG 95 #define ehcidebug 0 96 #else 97 static int ehcidebug = 0; 98 99 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 100 { 101 int err; 102 const struct sysctlnode *rnode; 103 const struct sysctlnode *cnode; 104 105 err = sysctl_createv(clog, 0, NULL, &rnode, 106 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 107 SYSCTL_DESCR("ehci global controls"), 108 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 109 110 if (err) 111 goto fail; 112 113 /* control debugging printfs */ 114 err = sysctl_createv(clog, 0, &rnode, &cnode, 115 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 116 "debug", SYSCTL_DESCR("Enable debugging output"), 117 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 118 if (err) 119 goto fail; 120 121 return; 122 fail: 123 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 124 } 125 126 #endif /* EHCI_DEBUG */ 127 #endif /* USB_DEBUG */ 128 129 #define DPRINTF(FMT,A,B,C,D) USBHIST_LOG(ehcidebug,FMT,A,B,C,D) 130 #define DPRINTFN(N,FMT,A,B,C,D) USBHIST_LOGN(ehcidebug,N,FMT,A,B,C,D) 131 #define EHCIHIST_FUNC() USBHIST_FUNC() 132 #define EHCIHIST_CALLED() USBHIST_CALLED(ehcidebug) 133 134 struct ehci_pipe { 135 struct usbd_pipe pipe; 136 int nexttoggle; 137 138 ehci_soft_qh_t *sqh; 139 union { 140 /* Control pipe */ 141 struct { 142 usb_dma_t reqdma; 143 } ctrl; 144 /* Interrupt pipe */ 145 struct { 146 u_int length; 147 } intr; 148 /* Iso pipe */ 149 struct { 150 u_int next_frame; 151 u_int cur_xfers; 152 } isoc; 153 }; 154 }; 155 156 typedef TAILQ_HEAD(ex_completeq, ehci_xfer) ex_completeq_t; 157 158 Static usbd_status ehci_open(struct usbd_pipe *); 159 Static void ehci_poll(struct usbd_bus *); 160 Static void ehci_softintr(void *); 161 Static int ehci_intr1(ehci_softc_t *); 162 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *, 163 ex_completeq_t *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *, 165 ex_completeq_t *); 166 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *, 167 ex_completeq_t *); 168 Static void ehci_idone(struct ehci_xfer *, ex_completeq_t *); 169 Static void ehci_timeout(void *); 170 Static void ehci_timeout_task(void *); 171 Static void ehci_intrlist_timeout(void *); 172 Static void ehci_doorbell(void *); 173 Static void ehci_pcd(void *); 174 175 Static struct usbd_xfer * 176 ehci_allocx(struct usbd_bus *, unsigned int); 177 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 178 179 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 180 Static int ehci_roothub_ctrl(struct usbd_bus *, 181 usb_device_request_t *, void *, int); 182 183 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 184 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 185 Static void ehci_root_intr_abort(struct usbd_xfer *); 186 Static void ehci_root_intr_close(struct usbd_pipe *); 187 Static void ehci_root_intr_done(struct usbd_xfer *); 188 189 Static int ehci_device_ctrl_init(struct usbd_xfer *); 190 Static void ehci_device_ctrl_fini(struct usbd_xfer *); 191 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 192 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 193 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 194 Static void ehci_device_ctrl_close(struct usbd_pipe *); 195 Static void ehci_device_ctrl_done(struct usbd_xfer *); 196 197 Static int ehci_device_bulk_init(struct usbd_xfer *); 198 Static void ehci_device_bulk_fini(struct usbd_xfer *); 199 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 200 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 201 Static void ehci_device_bulk_abort(struct usbd_xfer *); 202 Static void ehci_device_bulk_close(struct usbd_pipe *); 203 Static void ehci_device_bulk_done(struct usbd_xfer *); 204 205 Static int ehci_device_intr_init(struct usbd_xfer *); 206 Static void ehci_device_intr_fini(struct usbd_xfer *); 207 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 208 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 209 Static void ehci_device_intr_abort(struct usbd_xfer *); 210 Static void ehci_device_intr_close(struct usbd_pipe *); 211 Static void ehci_device_intr_done(struct usbd_xfer *); 212 213 Static int ehci_device_isoc_init(struct usbd_xfer *); 214 Static void ehci_device_isoc_fini(struct usbd_xfer *); 215 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 216 Static void ehci_device_isoc_abort(struct usbd_xfer *); 217 Static void ehci_device_isoc_close(struct usbd_pipe *); 218 Static void ehci_device_isoc_done(struct usbd_xfer *); 219 220 Static int ehci_device_fs_isoc_init(struct usbd_xfer *); 221 Static void ehci_device_fs_isoc_fini(struct usbd_xfer *); 222 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 223 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 224 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 225 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 226 227 Static void ehci_device_clear_toggle(struct usbd_pipe *); 228 Static void ehci_noop(struct usbd_pipe *); 229 230 Static void ehci_disown(ehci_softc_t *, int, int); 231 232 Static ehci_soft_qh_t * ehci_alloc_sqh(ehci_softc_t *); 233 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 234 235 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 236 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 237 Static int ehci_alloc_sqtd_chain(ehci_softc_t *, 238 struct usbd_xfer *, int, int, ehci_soft_qtd_t **); 239 Static void ehci_free_sqtds(ehci_softc_t *, struct ehci_xfer *); 240 241 Static void ehci_reset_sqtd_chain(ehci_softc_t *, struct usbd_xfer *, 242 int, int, int *, ehci_soft_qtd_t **); 243 Static void ehci_append_sqtd(ehci_soft_qtd_t *, ehci_soft_qtd_t *); 244 245 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 246 Static ehci_soft_sitd_t * 247 ehci_alloc_sitd(ehci_softc_t *); 248 249 Static void ehci_remove_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 250 Static void ehci_remove_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 251 Static void ehci_free_itd_chain(ehci_softc_t *, ehci_soft_itd_t *); 252 Static void ehci_free_sitd_chain(ehci_softc_t *, ehci_soft_sitd_t *); 253 254 static inline void 255 ehci_free_itd_locked(ehci_softc_t *sc, ehci_soft_itd_t *itd) 256 { 257 258 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 259 } 260 261 static inline void 262 ehci_free_sitd_locked(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 263 { 264 265 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 266 } 267 268 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, usbd_status); 269 270 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 271 int); 272 273 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 274 ehci_soft_qh_t *); 275 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 276 ehci_soft_qh_t *); 277 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 278 Static void ehci_sync_hc(ehci_softc_t *); 279 280 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 281 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 282 283 #ifdef EHCI_DEBUG 284 Static ehci_softc_t *theehci; 285 void ehci_dump(void); 286 #endif 287 288 #ifdef EHCI_DEBUG 289 Static void ehci_dump_regs(ehci_softc_t *); 290 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 291 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 292 Static void ehci_dump_qtd(ehci_qtd_t *); 293 Static void ehci_dump_sqh(ehci_soft_qh_t *); 294 Static void ehci_dump_sitd(struct ehci_soft_itd *); 295 Static void ehci_dump_itds(ehci_soft_itd_t *); 296 Static void ehci_dump_itd(struct ehci_soft_itd *); 297 Static void ehci_dump_exfer(struct ehci_xfer *); 298 #endif 299 300 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 301 302 static inline void 303 ehci_add_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 304 { 305 306 TAILQ_INSERT_TAIL(&sc->sc_intrhead, ex, ex_next); 307 } 308 309 static inline void 310 ehci_del_intr_list(ehci_softc_t *sc, struct ehci_xfer *ex) 311 { 312 313 TAILQ_REMOVE(&sc->sc_intrhead, ex, ex_next); 314 } 315 316 Static const struct usbd_bus_methods ehci_bus_methods = { 317 .ubm_open = ehci_open, 318 .ubm_softint = ehci_softintr, 319 .ubm_dopoll = ehci_poll, 320 .ubm_allocx = ehci_allocx, 321 .ubm_freex = ehci_freex, 322 .ubm_getlock = ehci_get_lock, 323 .ubm_rhctrl = ehci_roothub_ctrl, 324 }; 325 326 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 327 .upm_transfer = ehci_root_intr_transfer, 328 .upm_start = ehci_root_intr_start, 329 .upm_abort = ehci_root_intr_abort, 330 .upm_close = ehci_root_intr_close, 331 .upm_cleartoggle = ehci_noop, 332 .upm_done = ehci_root_intr_done, 333 }; 334 335 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 336 .upm_init = ehci_device_ctrl_init, 337 .upm_fini = ehci_device_ctrl_fini, 338 .upm_transfer = ehci_device_ctrl_transfer, 339 .upm_start = ehci_device_ctrl_start, 340 .upm_abort = ehci_device_ctrl_abort, 341 .upm_close = ehci_device_ctrl_close, 342 .upm_cleartoggle = ehci_noop, 343 .upm_done = ehci_device_ctrl_done, 344 }; 345 346 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 347 .upm_init = ehci_device_intr_init, 348 .upm_fini = ehci_device_intr_fini, 349 .upm_transfer = ehci_device_intr_transfer, 350 .upm_start = ehci_device_intr_start, 351 .upm_abort = ehci_device_intr_abort, 352 .upm_close = ehci_device_intr_close, 353 .upm_cleartoggle = ehci_device_clear_toggle, 354 .upm_done = ehci_device_intr_done, 355 }; 356 357 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 358 .upm_init = ehci_device_bulk_init, 359 .upm_fini = ehci_device_bulk_fini, 360 .upm_transfer = ehci_device_bulk_transfer, 361 .upm_start = ehci_device_bulk_start, 362 .upm_abort = ehci_device_bulk_abort, 363 .upm_close = ehci_device_bulk_close, 364 .upm_cleartoggle = ehci_device_clear_toggle, 365 .upm_done = ehci_device_bulk_done, 366 }; 367 368 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 369 .upm_init = ehci_device_isoc_init, 370 .upm_fini = ehci_device_isoc_fini, 371 .upm_transfer = ehci_device_isoc_transfer, 372 .upm_abort = ehci_device_isoc_abort, 373 .upm_close = ehci_device_isoc_close, 374 .upm_cleartoggle = ehci_noop, 375 .upm_done = ehci_device_isoc_done, 376 }; 377 378 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 379 .upm_init = ehci_device_fs_isoc_init, 380 .upm_fini = ehci_device_fs_isoc_fini, 381 .upm_transfer = ehci_device_fs_isoc_transfer, 382 .upm_abort = ehci_device_fs_isoc_abort, 383 .upm_close = ehci_device_fs_isoc_close, 384 .upm_cleartoggle = ehci_noop, 385 .upm_done = ehci_device_fs_isoc_done, 386 }; 387 388 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 389 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 390 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 391 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 392 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 393 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 394 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 395 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 396 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 397 }; 398 399 int 400 ehci_init(ehci_softc_t *sc) 401 { 402 uint32_t vers, sparams, cparams, hcr; 403 u_int i; 404 usbd_status err; 405 ehci_soft_qh_t *sqh; 406 u_int ncomp; 407 408 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 409 #ifdef EHCI_DEBUG 410 theehci = sc; 411 #endif 412 413 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 414 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_USB); 415 cv_init(&sc->sc_doorbell, "ehcidb"); 416 417 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 418 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 419 420 sc->sc_doorbell_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 421 ehci_doorbell, sc); 422 KASSERT(sc->sc_doorbell_si != NULL); 423 sc->sc_pcd_si = softint_establish(SOFTINT_USB | SOFTINT_MPSAFE, 424 ehci_pcd, sc); 425 KASSERT(sc->sc_pcd_si != NULL); 426 427 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 428 429 vers = EREAD2(sc, EHCI_HCIVERSION); 430 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 431 vers >> 8, vers & 0xff); 432 433 sparams = EREAD4(sc, EHCI_HCSPARAMS); 434 DPRINTF("sparams=%#x", sparams, 0, 0, 0); 435 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 436 ncomp = EHCI_HCS_N_CC(sparams); 437 if (ncomp != sc->sc_ncomp) { 438 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 439 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 440 #if NOHCI == 0 || NUHCI == 0 441 aprint_error("%s: ohci or uhci probably not configured\n", 442 device_xname(sc->sc_dev)); 443 #endif 444 if (ncomp < sc->sc_ncomp) 445 sc->sc_ncomp = ncomp; 446 } 447 if (sc->sc_ncomp > 0) { 448 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 449 aprint_normal("%s: %d companion controller%s, %d port%s%s", 450 device_xname(sc->sc_dev), sc->sc_ncomp, 451 sc->sc_ncomp!=1 ? "s" : "", 452 EHCI_HCS_N_PCC(sparams), 453 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : "", 454 sc->sc_ncomp!=1 ? " each" : ""); 455 if (sc->sc_comps[0]) { 456 aprint_normal(":"); 457 for (i = 0; i < sc->sc_ncomp; i++) 458 aprint_normal(" %s", 459 device_xname(sc->sc_comps[i])); 460 } 461 aprint_normal("\n"); 462 } 463 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 464 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 465 466 cparams = EREAD4(sc, EHCI_HCCPARAMS); 467 DPRINTF("cparams=%#x", cparams, 0, 0, 0); 468 469 if (EHCI_HCC_64BIT(cparams)) { 470 /* MUST clear segment register if 64 bit capable. */ 471 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 472 } 473 474 if (cparams & EHCI_HCC_IST_FULLFRAME) { 475 sc->sc_istthreshold = 0; 476 } else { 477 sc->sc_istthreshold = EHCI_HCC_GET_IST_THRESHOLD(cparams); 478 } 479 480 sc->sc_bus.ub_revision = USBREV_2_0; 481 sc->sc_bus.ub_usedma = true; 482 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 483 484 /* Reset the controller */ 485 DPRINTF("resetting", 0, 0, 0, 0); 486 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 487 usb_delay_ms(&sc->sc_bus, 1); 488 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 489 for (i = 0; i < 100; i++) { 490 usb_delay_ms(&sc->sc_bus, 1); 491 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 492 if (!hcr) 493 break; 494 } 495 if (hcr) { 496 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 497 return EIO; 498 } 499 if (sc->sc_vendor_init) 500 sc->sc_vendor_init(sc); 501 502 /* XXX need proper intr scheduling */ 503 sc->sc_rand = 96; 504 505 /* frame list size at default, read back what we got and use that */ 506 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 507 case 0: sc->sc_flsize = 1024; break; 508 case 1: sc->sc_flsize = 512; break; 509 case 2: sc->sc_flsize = 256; break; 510 case 3: return EIO; 511 } 512 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 513 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 514 if (err) 515 return err; 516 DPRINTF("flsize=%d", sc->sc_flsize, 0, 0, 0); 517 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 518 519 for (i = 0; i < sc->sc_flsize; i++) { 520 sc->sc_flist[i] = EHCI_NULL; 521 } 522 523 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 524 525 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 526 KM_SLEEP); 527 if (sc->sc_softitds == NULL) 528 return ENOMEM; 529 LIST_INIT(&sc->sc_freeitds); 530 LIST_INIT(&sc->sc_freesitds); 531 TAILQ_INIT(&sc->sc_intrhead); 532 533 /* Set up the bus struct. */ 534 sc->sc_bus.ub_methods = &ehci_bus_methods; 535 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 536 537 sc->sc_eintrs = EHCI_NORMAL_INTRS; 538 539 /* 540 * Allocate the interrupt dummy QHs. These are arranged to give poll 541 * intervals that are powers of 2 times 1ms. 542 */ 543 for (i = 0; i < EHCI_INTRQHS; i++) { 544 sqh = ehci_alloc_sqh(sc); 545 if (sqh == NULL) { 546 err = ENOMEM; 547 goto bad1; 548 } 549 sc->sc_islots[i].sqh = sqh; 550 } 551 for (i = 0; i < EHCI_INTRQHS; i++) { 552 sqh = sc->sc_islots[i].sqh; 553 if (i == 0) { 554 /* The last (1ms) QH terminates. */ 555 sqh->qh.qh_link = EHCI_NULL; 556 sqh->next = NULL; 557 } else { 558 /* Otherwise the next QH has half the poll interval */ 559 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 560 sqh->qh.qh_link = htole32(sqh->next->physaddr | 561 EHCI_LINK_QH); 562 } 563 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 564 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1)); 565 sqh->qh.qh_curqtd = EHCI_NULL; 566 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 567 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 568 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 569 sqh->sqtd = NULL; 570 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 571 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 572 } 573 /* Point the frame list at the last level (128ms). */ 574 for (i = 0; i < sc->sc_flsize; i++) { 575 int j; 576 577 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 578 revbits[i & (EHCI_MAX_POLLRATE-1)]; 579 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 580 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 581 i)].sqh->physaddr); 582 } 583 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 584 BUS_DMASYNC_PREWRITE); 585 586 /* Allocate dummy QH that starts the async list. */ 587 sqh = ehci_alloc_sqh(sc); 588 if (sqh == NULL) { 589 err = ENOMEM; 590 goto bad1; 591 } 592 /* Fill the QH */ 593 sqh->qh.qh_endp = 594 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 595 sqh->qh.qh_link = 596 htole32(sqh->physaddr | EHCI_LINK_QH); 597 sqh->qh.qh_curqtd = EHCI_NULL; 598 sqh->next = NULL; 599 /* Fill the overlay qTD */ 600 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 601 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 602 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 603 sqh->sqtd = NULL; 604 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 605 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 606 #ifdef EHCI_DEBUG 607 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 608 ehci_dump_sqh(sqh); 609 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 610 #endif 611 612 /* Point to async list */ 613 sc->sc_async_head = sqh; 614 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 615 616 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 617 618 /* Turn on controller */ 619 EOWRITE4(sc, EHCI_USBCMD, 620 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 621 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 622 EHCI_CMD_ASE | 623 EHCI_CMD_PSE | 624 EHCI_CMD_RS); 625 626 /* Take over port ownership */ 627 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 628 629 for (i = 0; i < 100; i++) { 630 usb_delay_ms(&sc->sc_bus, 1); 631 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 632 if (!hcr) 633 break; 634 } 635 if (hcr) { 636 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 637 return EIO; 638 } 639 640 /* Enable interrupts */ 641 DPRINTF("enabling interupts", 0, 0, 0, 0); 642 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 643 644 return 0; 645 646 #if 0 647 bad2: 648 ehci_free_sqh(sc, sc->sc_async_head); 649 #endif 650 bad1: 651 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 652 return err; 653 } 654 655 int 656 ehci_intr(void *v) 657 { 658 ehci_softc_t *sc = v; 659 int ret = 0; 660 661 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 662 663 if (sc == NULL) 664 return 0; 665 666 mutex_spin_enter(&sc->sc_intr_lock); 667 668 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 669 goto done; 670 671 /* If we get an interrupt while polling, then just ignore it. */ 672 if (sc->sc_bus.ub_usepolling) { 673 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 674 675 if (intrs) 676 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 677 DPRINTFN(16, "ignored interrupt while polling", 0, 0, 0, 0); 678 goto done; 679 } 680 681 ret = ehci_intr1(sc); 682 683 done: 684 mutex_spin_exit(&sc->sc_intr_lock); 685 return ret; 686 } 687 688 Static int 689 ehci_intr1(ehci_softc_t *sc) 690 { 691 uint32_t intrs, eintrs; 692 693 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 694 695 /* In case the interrupt occurs before initialization has completed. */ 696 if (sc == NULL) { 697 #ifdef DIAGNOSTIC 698 printf("ehci_intr1: sc == NULL\n"); 699 #endif 700 return 0; 701 } 702 703 KASSERT(mutex_owned(&sc->sc_intr_lock)); 704 705 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 706 if (!intrs) 707 return 0; 708 709 eintrs = intrs & sc->sc_eintrs; 710 DPRINTF("sc=%p intrs=%#x(%#x) eintrs=%#x", sc, intrs, 711 EOREAD4(sc, EHCI_USBSTS), eintrs); 712 if (!eintrs) 713 return 0; 714 715 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 716 if (eintrs & EHCI_STS_IAA) { 717 DPRINTF("door bell", 0, 0, 0, 0); 718 kpreempt_disable(); 719 KASSERT(sc->sc_doorbell_si != NULL); 720 softint_schedule(sc->sc_doorbell_si); 721 kpreempt_enable(); 722 eintrs &= ~EHCI_STS_IAA; 723 } 724 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 725 DPRINTF("INT=%d ERRINT=%d", 726 eintrs & EHCI_STS_INT ? 1 : 0, 727 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 728 usb_schedsoftintr(&sc->sc_bus); 729 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 730 } 731 if (eintrs & EHCI_STS_HSE) { 732 printf("%s: unrecoverable error, controller halted\n", 733 device_xname(sc->sc_dev)); 734 /* XXX what else */ 735 } 736 if (eintrs & EHCI_STS_PCD) { 737 kpreempt_disable(); 738 KASSERT(sc->sc_pcd_si != NULL); 739 softint_schedule(sc->sc_pcd_si); 740 kpreempt_enable(); 741 eintrs &= ~EHCI_STS_PCD; 742 } 743 744 if (eintrs != 0) { 745 /* Block unprocessed interrupts. */ 746 sc->sc_eintrs &= ~eintrs; 747 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 748 printf("%s: blocking intrs 0x%x\n", 749 device_xname(sc->sc_dev), eintrs); 750 } 751 752 return 1; 753 } 754 755 Static void 756 ehci_doorbell(void *addr) 757 { 758 ehci_softc_t *sc = addr; 759 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 760 761 mutex_enter(&sc->sc_lock); 762 sc->sc_dbanswered = true; 763 cv_broadcast(&sc->sc_doorbell); 764 mutex_exit(&sc->sc_lock); 765 } 766 767 Static void 768 ehci_pcd(void *addr) 769 { 770 ehci_softc_t *sc = addr; 771 struct usbd_xfer *xfer; 772 u_char *p; 773 int i, m; 774 775 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 776 777 mutex_enter(&sc->sc_lock); 778 xfer = sc->sc_intrxfer; 779 780 if (xfer == NULL) { 781 /* Just ignore the change. */ 782 goto done; 783 } 784 785 p = xfer->ux_buf; 786 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 787 memset(p, 0, xfer->ux_length); 788 for (i = 1; i <= m; i++) { 789 /* Pick out CHANGE bits from the status reg. */ 790 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 791 p[i/8] |= 1 << (i%8); 792 if (i % 8 == 7) 793 DPRINTF("change(%d)=0x%02x", i / 8, p[i/8], 0, 0); 794 } 795 xfer->ux_actlen = xfer->ux_length; 796 xfer->ux_status = USBD_NORMAL_COMPLETION; 797 798 usb_transfer_complete(xfer); 799 800 done: 801 mutex_exit(&sc->sc_lock); 802 } 803 804 Static void 805 ehci_softintr(void *v) 806 { 807 struct usbd_bus *bus = v; 808 ehci_softc_t *sc = EHCI_BUS2SC(bus); 809 struct ehci_xfer *ex, *nextex; 810 811 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 812 813 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 814 815 ex_completeq_t cq; 816 TAILQ_INIT(&cq); 817 818 /* 819 * The only explanation I can think of for why EHCI is as brain dead 820 * as UHCI interrupt-wise is that Intel was involved in both. 821 * An interrupt just tells us that something is done, we have no 822 * clue what, so we need to scan through all active transfers. :-( 823 */ 824 825 /* 826 * ehci_idone will remove transfer from sc->sc_intrhead if it's 827 * complete and add to our cq list 828 * 829 */ 830 TAILQ_FOREACH_SAFE(ex, &sc->sc_intrhead, ex_next, nextex) { 831 switch (ex->ex_type) { 832 case EX_CTRL: 833 case EX_BULK: 834 case EX_INTR: 835 ehci_check_qh_intr(sc, ex, &cq); 836 break; 837 case EX_ISOC: 838 ehci_check_itd_intr(sc, ex, &cq); 839 break; 840 case EX_FS_ISOC: 841 ehci_check_sitd_intr(sc, ex, &cq); 842 break; 843 default: 844 KASSERT(false); 845 } 846 847 } 848 849 /* 850 * We abuse ex_next for the interrupt and complete lists and 851 * interrupt transfers will get re-added here so use 852 * the _SAFE version of TAILQ_FOREACH. 853 */ 854 TAILQ_FOREACH_SAFE(ex, &cq, ex_next, nextex) { 855 usb_transfer_complete(&ex->ex_xfer); 856 } 857 858 /* Schedule a callout to catch any dropped transactions. */ 859 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 860 !TAILQ_EMPTY(&sc->sc_intrhead)) 861 callout_reset(&sc->sc_tmo_intrlist, 862 hz, ehci_intrlist_timeout, sc); 863 } 864 865 Static void 866 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 867 { 868 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 869 uint32_t status; 870 871 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 872 873 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 874 875 if (ex->ex_type == EX_CTRL) { 876 fsqtd = ex->ex_setup; 877 lsqtd = ex->ex_status; 878 } else { 879 fsqtd = ex->ex_sqtdstart; 880 lsqtd = ex->ex_sqtdend; 881 } 882 KASSERTMSG(fsqtd != NULL && lsqtd != NULL, 883 "xfer %p xt %d fsqtd %p lsqtd %p", ex, ex->ex_type, fsqtd, lsqtd); 884 885 /* 886 * If the last TD is still active we need to check whether there 887 * is an error somewhere in the middle, or whether there was a 888 * short packet (SPD and not ACTIVE). 889 */ 890 usb_syncmem(&lsqtd->dma, 891 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 892 sizeof(lsqtd->qtd.qtd_status), 893 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 894 status = le32toh(lsqtd->qtd.qtd_status); 895 usb_syncmem(&lsqtd->dma, 896 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 897 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 898 if (status & EHCI_QTD_ACTIVE) { 899 DPRINTFN(10, "active ex=%p", ex, 0, 0, 0); 900 901 /* last qTD has already been checked */ 902 for (sqtd = fsqtd; sqtd != lsqtd; sqtd = sqtd->nextqtd) { 903 usb_syncmem(&sqtd->dma, 904 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 905 sizeof(sqtd->qtd.qtd_status), 906 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 907 status = le32toh(sqtd->qtd.qtd_status); 908 usb_syncmem(&sqtd->dma, 909 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 910 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 911 /* If there's an active QTD the xfer isn't done. */ 912 if (status & EHCI_QTD_ACTIVE) 913 break; 914 /* Any kind of error makes the xfer done. */ 915 if (status & EHCI_QTD_HALTED) 916 goto done; 917 /* Handle short packets */ 918 if (EHCI_QTD_GET_BYTES(status) != 0) { 919 /* 920 * If we get here for a control transfer then 921 * we need to let the hardware complete the 922 * status phase. That is, we're not done 923 * quite yet. 924 * 925 * Otherwise, we're done. 926 */ 927 if (ex->ex_type == EX_CTRL) { 928 break; 929 } 930 goto done; 931 } 932 } 933 DPRINTFN(10, "ex=%p std=%p still active", ex, ex->ex_sqtdstart, 934 0, 0); 935 #ifdef EHCI_DEBUG 936 DPRINTFN(5, "--- still active start ---", 0, 0, 0, 0); 937 ehci_dump_sqtds(ex->ex_sqtdstart); 938 DPRINTFN(5, "--- still active end ---", 0, 0, 0, 0); 939 #endif 940 return; 941 } 942 done: 943 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 944 ehci_idone(ex, cq); 945 } 946 947 Static void 948 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 949 { 950 ehci_soft_itd_t *itd; 951 int i; 952 953 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 954 955 KASSERT(mutex_owned(&sc->sc_lock)); 956 957 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 958 return; 959 960 KASSERTMSG(ex->ex_itdstart != NULL && ex->ex_itdend != NULL, 961 "xfer %p fitd %p litd %p", ex, ex->ex_itdstart, ex->ex_itdend); 962 963 itd = ex->ex_itdend; 964 965 /* 966 * check no active transfers in last itd, meaning we're finished 967 */ 968 969 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 970 sizeof(itd->itd.itd_ctl), 971 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 972 973 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 974 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 975 break; 976 } 977 978 if (i == EHCI_ITD_NUFRAMES) { 979 goto done; /* All 8 descriptors inactive, it's done */ 980 } 981 982 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 983 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 984 985 DPRINTFN(10, "ex %p itd %p still active", ex, ex->ex_itdstart, 0, 0); 986 return; 987 done: 988 DPRINTF("ex %p done", ex, 0, 0, 0); 989 ehci_idone(ex, cq); 990 } 991 992 void 993 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex, ex_completeq_t *cq) 994 { 995 ehci_soft_sitd_t *sitd; 996 997 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 998 999 KASSERT(mutex_owned(&sc->sc_lock)); 1000 1001 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 1002 return; 1003 1004 KASSERTMSG(ex->ex_sitdstart != NULL && ex->ex_sitdend != NULL, 1005 "xfer %p fsitd %p lsitd %p", ex, ex->ex_sitdstart, ex->ex_sitdend); 1006 1007 sitd = ex->ex_sitdend; 1008 1009 /* 1010 * check no active transfers in last sitd, meaning we're finished 1011 */ 1012 1013 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1014 sizeof(sitd->sitd.sitd_trans), 1015 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1016 1017 bool active = ((le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) != 0); 1018 1019 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1020 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1021 1022 if (active) 1023 return; 1024 1025 DPRINTFN(10, "ex=%p done", ex, 0, 0, 0); 1026 ehci_idone(ex, cq); 1027 } 1028 1029 1030 Static void 1031 ehci_idone(struct ehci_xfer *ex, ex_completeq_t *cq) 1032 { 1033 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1034 struct usbd_xfer *xfer = &ex->ex_xfer; 1035 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 1036 struct ehci_softc *sc = EHCI_XFER2SC(xfer); 1037 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 1038 uint32_t status = 0, nstatus = 0; 1039 int actlen = 0; 1040 bool polling = sc->sc_bus.ub_usepolling; 1041 1042 KASSERT(polling || mutex_owned(&sc->sc_lock)); 1043 1044 DPRINTF("ex=%p", ex, 0, 0, 0); 1045 1046 /* 1047 * Make sure the timeout handler didn't run or ran to the end 1048 * and set the transfer status. 1049 */ 1050 callout_halt(&ex->ex_xfer.ux_callout, polling ? NULL : &sc->sc_lock); 1051 if (xfer->ux_status == USBD_CANCELLED || 1052 xfer->ux_status == USBD_TIMEOUT) { 1053 DPRINTF("aborted xfer=%p", xfer, 0, 0, 0); 1054 return; 1055 } 1056 1057 #ifdef DIAGNOSTIC 1058 #ifdef EHCI_DEBUG 1059 if (ex->ex_isdone) { 1060 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1061 ehci_dump_exfer(ex); 1062 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1063 } 1064 #endif 1065 KASSERTMSG(!ex->ex_isdone, "xfer %p type %d status %d", xfer, 1066 ex->ex_type, xfer->ux_status); 1067 ex->ex_isdone = true; 1068 #endif 1069 1070 DPRINTF("xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1071 1072 /* The transfer is done, compute actual length and status. */ 1073 if (ex->ex_type == EX_ISOC) { 1074 /* HS isoc transfer */ 1075 1076 struct ehci_soft_itd *itd; 1077 int i, nframes, len, uframes; 1078 1079 nframes = 0; 1080 1081 #ifdef EHCI_DEBUG 1082 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1083 ehci_dump_itds(ex->ex_itdstart); 1084 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1085 #endif 1086 1087 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1088 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1089 1090 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1091 usb_syncmem(&itd->dma, 1092 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1093 sizeof(itd->itd.itd_ctl), 1094 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1095 1096 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1097 /* 1098 * XXX - driver didn't fill in the frame full 1099 * of uframes. This leads to scheduling 1100 * inefficiencies, but working around 1101 * this doubles complexity of tracking 1102 * an xfer. 1103 */ 1104 if (nframes >= xfer->ux_nframes) 1105 break; 1106 1107 status = le32toh(itd->itd.itd_ctl[i]); 1108 len = EHCI_ITD_GET_LEN(status); 1109 if (EHCI_ITD_GET_STATUS(status) != 0) 1110 len = 0; /*No valid data on error*/ 1111 1112 xfer->ux_frlengths[nframes++] = len; 1113 actlen += len; 1114 } 1115 usb_syncmem(&itd->dma, 1116 itd->offs + offsetof(ehci_itd_t,itd_ctl), 1117 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1118 1119 if (nframes >= xfer->ux_nframes) 1120 break; 1121 } 1122 1123 xfer->ux_actlen = actlen; 1124 xfer->ux_status = USBD_NORMAL_COMPLETION; 1125 goto end; 1126 } else if (ex->ex_type == EX_FS_ISOC) { 1127 /* FS isoc transfer */ 1128 struct ehci_soft_sitd *sitd; 1129 int nframes, len; 1130 1131 nframes = 0; 1132 1133 for (sitd = ex->ex_sitdstart; sitd != NULL; 1134 sitd = sitd->xfer_next) { 1135 usb_syncmem(&sitd->dma, 1136 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1137 sizeof(sitd->sitd.sitd_trans), 1138 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1139 1140 /* 1141 * XXX - driver didn't fill in the frame full 1142 * of uframes. This leads to scheduling 1143 * inefficiencies, but working around 1144 * this doubles complexity of tracking 1145 * an xfer. 1146 */ 1147 if (nframes >= xfer->ux_nframes) 1148 break; 1149 1150 status = le32toh(sitd->sitd.sitd_trans); 1151 usb_syncmem(&sitd->dma, 1152 sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1153 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1154 1155 len = EHCI_SITD_GET_LEN(status); 1156 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1157 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1158 /* No valid data on error */ 1159 len = xfer->ux_frlengths[nframes]; 1160 } 1161 1162 /* 1163 * frlengths[i]: # of bytes to send 1164 * len: # of bytes host didn't send 1165 */ 1166 xfer->ux_frlengths[nframes] -= len; 1167 /* frlengths[i]: # of bytes host sent */ 1168 actlen += xfer->ux_frlengths[nframes++]; 1169 1170 if (nframes >= xfer->ux_nframes) 1171 break; 1172 } 1173 1174 xfer->ux_actlen = actlen; 1175 xfer->ux_status = USBD_NORMAL_COMPLETION; 1176 goto end; 1177 } 1178 KASSERT(ex->ex_type == EX_CTRL || ex->ex_type == EX_INTR || 1179 ex->ex_type == EX_BULK); 1180 1181 /* Continue processing xfers using queue heads */ 1182 if (ex->ex_type == EX_CTRL) { 1183 fsqtd = ex->ex_setup; 1184 lsqtd = ex->ex_status; 1185 } else { 1186 fsqtd = ex->ex_sqtdstart; 1187 lsqtd = ex->ex_sqtdend; 1188 } 1189 #ifdef EHCI_DEBUG 1190 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1191 ehci_dump_sqtds(fsqtd); 1192 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1193 #endif 1194 1195 for (sqtd = fsqtd; sqtd != lsqtd->nextqtd; sqtd = sqtd->nextqtd) { 1196 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1197 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1198 nstatus = le32toh(sqtd->qtd.qtd_status); 1199 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1200 BUS_DMASYNC_PREREAD); 1201 if (nstatus & EHCI_QTD_ACTIVE) 1202 break; 1203 1204 status = nstatus; 1205 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1206 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1207 } 1208 1209 /* 1210 * If there are left over TDs we need to update the toggle. 1211 * The default pipe doesn't need it since control transfers 1212 * start the toggle at 0 every time. 1213 * For a short transfer we need to update the toggle for the missing 1214 * packets within the qTD. 1215 */ 1216 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1217 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1218 DPRINTF("toggle update status=0x%08x nstatus=0x%08x", 1219 status, nstatus, 0, 0); 1220 #if 0 1221 ehci_dump_sqh(epipe->sqh); 1222 ehci_dump_sqtds(ex->ex_sqtdstart); 1223 #endif 1224 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1225 } 1226 1227 DPRINTF("len=%d actlen=%d status=0x%08x", xfer->ux_length, actlen, 1228 status, 0); 1229 xfer->ux_actlen = actlen; 1230 if (status & EHCI_QTD_HALTED) { 1231 #ifdef EHCI_DEBUG 1232 DPRINTF("halted addr=%d endpt=0x%02x", 1233 xfer->ux_pipe->up_dev->ud_addr, 1234 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 1235 0, 0); 1236 DPRINTF("cerr=%d pid=%d", 1237 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1238 0, 0); 1239 DPRINTF("active =%d halted=%d buferr=%d babble=%d", 1240 status & EHCI_QTD_ACTIVE ? 1 : 0, 1241 status & EHCI_QTD_HALTED ? 1 : 0, 1242 status & EHCI_QTD_BUFERR ? 1 : 0, 1243 status & EHCI_QTD_BABBLE ? 1 : 0); 1244 1245 DPRINTF("xacterr=%d missed=%d split =%d ping =%d", 1246 status & EHCI_QTD_XACTERR ? 1 : 0, 1247 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1248 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1249 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1250 1251 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 1252 ehci_dump_sqh(epipe->sqh); 1253 ehci_dump_sqtds(ex->ex_sqtdstart); 1254 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 1255 #endif 1256 /* low&full speed has an extra error flag */ 1257 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1258 EHCI_QH_SPEED_HIGH) 1259 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1260 else 1261 status &= EHCI_QTD_STATERRS; 1262 if (status == 0) /* no other errors means a stall */ { 1263 xfer->ux_status = USBD_STALLED; 1264 } else { 1265 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1266 } 1267 /* XXX need to reset TT on missed microframe */ 1268 if (status & EHCI_QTD_MISSEDMICRO) { 1269 printf("%s: missed microframe, TT reset not " 1270 "implemented, hub might be inoperational\n", 1271 device_xname(sc->sc_dev)); 1272 } 1273 } else { 1274 xfer->ux_status = USBD_NORMAL_COMPLETION; 1275 } 1276 1277 end: 1278 1279 ehci_del_intr_list(sc, ex); 1280 TAILQ_INSERT_TAIL(cq, ex, ex_next); 1281 1282 DPRINTF("ex=%p done", ex, 0, 0, 0); 1283 } 1284 1285 Static void 1286 ehci_poll(struct usbd_bus *bus) 1287 { 1288 ehci_softc_t *sc = EHCI_BUS2SC(bus); 1289 1290 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1291 1292 #ifdef EHCI_DEBUG 1293 static int last; 1294 int new; 1295 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1296 if (new != last) { 1297 DPRINTF("intrs=0x%04x", new, 0, 0, 0); 1298 last = new; 1299 } 1300 #endif 1301 1302 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1303 mutex_spin_enter(&sc->sc_intr_lock); 1304 ehci_intr1(sc); 1305 mutex_spin_exit(&sc->sc_intr_lock); 1306 } 1307 } 1308 1309 void 1310 ehci_childdet(device_t self, device_t child) 1311 { 1312 struct ehci_softc *sc = device_private(self); 1313 1314 KASSERT(sc->sc_child == child); 1315 sc->sc_child = NULL; 1316 } 1317 1318 int 1319 ehci_detach(struct ehci_softc *sc, int flags) 1320 { 1321 int rv = 0; 1322 1323 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1324 1325 if (sc->sc_child != NULL) 1326 rv = config_detach(sc->sc_child, flags); 1327 1328 if (rv != 0) 1329 return rv; 1330 1331 callout_halt(&sc->sc_tmo_intrlist, NULL); 1332 callout_destroy(&sc->sc_tmo_intrlist); 1333 1334 /* XXX free other data structures XXX */ 1335 if (sc->sc_softitds) 1336 kmem_free(sc->sc_softitds, 1337 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1338 cv_destroy(&sc->sc_doorbell); 1339 1340 #if 0 1341 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1342 1343 softint_disestablish(sc->sc_doorbell_si); 1344 softint_disestablish(sc->sc_pcd_si); 1345 1346 mutex_destroy(&sc->sc_lock); 1347 mutex_destroy(&sc->sc_intr_lock); 1348 #endif 1349 1350 pool_cache_destroy(sc->sc_xferpool); 1351 1352 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1353 1354 return rv; 1355 } 1356 1357 1358 int 1359 ehci_activate(device_t self, enum devact act) 1360 { 1361 struct ehci_softc *sc = device_private(self); 1362 1363 switch (act) { 1364 case DVACT_DEACTIVATE: 1365 sc->sc_dying = 1; 1366 return 0; 1367 default: 1368 return EOPNOTSUPP; 1369 } 1370 } 1371 1372 /* 1373 * Handle suspend/resume. 1374 * 1375 * We need to switch to polling mode here, because this routine is 1376 * called from an interrupt context. This is all right since we 1377 * are almost suspended anyway. 1378 * 1379 * Note that this power handler isn't to be registered directly; the 1380 * bus glue needs to call out to it. 1381 */ 1382 bool 1383 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1384 { 1385 ehci_softc_t *sc = device_private(dv); 1386 int i; 1387 uint32_t cmd, hcr; 1388 1389 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1390 1391 mutex_spin_enter(&sc->sc_intr_lock); 1392 sc->sc_bus.ub_usepolling++; 1393 mutex_spin_exit(&sc->sc_intr_lock); 1394 1395 for (i = 1; i <= sc->sc_noport; i++) { 1396 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1397 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1398 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1399 } 1400 1401 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1402 1403 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1404 EOWRITE4(sc, EHCI_USBCMD, cmd); 1405 1406 for (i = 0; i < 100; i++) { 1407 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1408 if (hcr == 0) 1409 break; 1410 1411 usb_delay_ms(&sc->sc_bus, 1); 1412 } 1413 if (hcr != 0) 1414 printf("%s: reset timeout\n", device_xname(dv)); 1415 1416 cmd &= ~EHCI_CMD_RS; 1417 EOWRITE4(sc, EHCI_USBCMD, cmd); 1418 1419 for (i = 0; i < 100; i++) { 1420 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1421 if (hcr == EHCI_STS_HCH) 1422 break; 1423 1424 usb_delay_ms(&sc->sc_bus, 1); 1425 } 1426 if (hcr != EHCI_STS_HCH) 1427 printf("%s: config timeout\n", device_xname(dv)); 1428 1429 mutex_spin_enter(&sc->sc_intr_lock); 1430 sc->sc_bus.ub_usepolling--; 1431 mutex_spin_exit(&sc->sc_intr_lock); 1432 1433 return true; 1434 } 1435 1436 bool 1437 ehci_resume(device_t dv, const pmf_qual_t *qual) 1438 { 1439 ehci_softc_t *sc = device_private(dv); 1440 int i; 1441 uint32_t cmd, hcr; 1442 1443 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1444 1445 /* restore things in case the bios sucks */ 1446 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1447 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1448 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1449 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1450 1451 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1452 1453 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1454 1455 hcr = 0; 1456 for (i = 1; i <= sc->sc_noport; i++) { 1457 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1458 if ((cmd & EHCI_PS_PO) == 0 && 1459 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1460 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1461 hcr = 1; 1462 } 1463 } 1464 1465 if (hcr) { 1466 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1467 1468 for (i = 1; i <= sc->sc_noport; i++) { 1469 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1470 if ((cmd & EHCI_PS_PO) == 0 && 1471 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1472 EOWRITE4(sc, EHCI_PORTSC(i), 1473 cmd & ~EHCI_PS_FPR); 1474 } 1475 } 1476 1477 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1478 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1479 1480 for (i = 0; i < 100; i++) { 1481 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1482 if (hcr != EHCI_STS_HCH) 1483 break; 1484 1485 usb_delay_ms(&sc->sc_bus, 1); 1486 } 1487 if (hcr == EHCI_STS_HCH) 1488 printf("%s: config timeout\n", device_xname(dv)); 1489 1490 return true; 1491 } 1492 1493 /* 1494 * Shut down the controller when the system is going down. 1495 */ 1496 bool 1497 ehci_shutdown(device_t self, int flags) 1498 { 1499 ehci_softc_t *sc = device_private(self); 1500 1501 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1502 1503 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1504 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1505 return true; 1506 } 1507 1508 Static struct usbd_xfer * 1509 ehci_allocx(struct usbd_bus *bus, unsigned int nframes) 1510 { 1511 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1512 struct usbd_xfer *xfer; 1513 1514 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1515 if (xfer != NULL) { 1516 memset(xfer, 0, sizeof(struct ehci_xfer)); 1517 #ifdef DIAGNOSTIC 1518 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 1519 ex->ex_isdone = true; 1520 xfer->ux_state = XFER_BUSY; 1521 #endif 1522 } 1523 return xfer; 1524 } 1525 1526 Static void 1527 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1528 { 1529 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1530 struct ehci_xfer *ex __diagused = EHCI_XFER2EXFER(xfer); 1531 1532 KASSERTMSG(xfer->ux_state == XFER_BUSY, "xfer %p state %d\n", xfer, 1533 xfer->ux_state); 1534 KASSERT(ex->ex_isdone); 1535 1536 #ifdef DIAGNOSTIC 1537 xfer->ux_state = XFER_FREE; 1538 #endif 1539 1540 pool_cache_put(sc->sc_xferpool, xfer); 1541 } 1542 1543 Static void 1544 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1545 { 1546 struct ehci_softc *sc = EHCI_BUS2SC(bus); 1547 1548 *lock = &sc->sc_lock; 1549 } 1550 1551 Static void 1552 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1553 { 1554 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1555 1556 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1557 1558 DPRINTF("epipe=%p status=0x%08x", epipe, 1559 epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1560 #ifdef EHCI_DEBUG 1561 if (ehcidebug) 1562 usbd_dump_pipe(pipe); 1563 #endif 1564 epipe->nexttoggle = 0; 1565 } 1566 1567 Static void 1568 ehci_noop(struct usbd_pipe *pipe) 1569 { 1570 } 1571 1572 #ifdef EHCI_DEBUG 1573 /* 1574 * Unused function - this is meant to be called from a kernel 1575 * debugger. 1576 */ 1577 void 1578 ehci_dump(void) 1579 { 1580 ehci_softc_t *sc = theehci; 1581 int i; 1582 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1583 EOREAD4(sc, EHCI_USBCMD), 1584 EOREAD4(sc, EHCI_USBSTS), 1585 EOREAD4(sc, EHCI_USBINTR)); 1586 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1587 EOREAD4(sc, EHCI_FRINDEX), 1588 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1589 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1590 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1591 for (i = 1; i <= sc->sc_noport; i++) 1592 printf("port %d status=0x%08x\n", i, 1593 EOREAD4(sc, EHCI_PORTSC(i))); 1594 } 1595 1596 Static void 1597 ehci_dump_regs(ehci_softc_t *sc) 1598 { 1599 int i; 1600 1601 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1602 1603 DPRINTF("cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1604 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1605 EOREAD4(sc, EHCI_USBINTR), 0); 1606 DPRINTF("frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1607 "async = 0x%08x", 1608 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1609 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1610 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1611 for (i = 1; i <= sc->sc_noport; i += 2) { 1612 if (i == sc->sc_noport) { 1613 DPRINTF("port %d status = 0x%08x", i, 1614 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1615 } else { 1616 DPRINTF( 1617 "port %d status = 0x%08x port %d status = 0x%08x", 1618 i, EOREAD4(sc, EHCI_PORTSC(i)), 1619 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1620 } 1621 } 1622 } 1623 1624 #define ehci_dump_link(link, type) do { \ 1625 DPRINTF(" link 0x%08x (T = %d):", \ 1626 link, \ 1627 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1628 if (type) { \ 1629 DPRINTF( \ 1630 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1631 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1632 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1633 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1634 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1635 } \ 1636 } while(0) 1637 1638 Static void 1639 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1640 { 1641 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1642 int i; 1643 uint32_t stop = 0; 1644 1645 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1646 ehci_dump_sqtd(sqtd); 1647 usb_syncmem(&sqtd->dma, 1648 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1649 sizeof(sqtd->qtd), 1650 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1651 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1652 usb_syncmem(&sqtd->dma, 1653 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1654 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1655 } 1656 if (!stop) 1657 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1658 } 1659 1660 Static void 1661 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1662 { 1663 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1664 1665 usb_syncmem(&sqtd->dma, sqtd->offs, 1666 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1667 1668 DPRINTFN(10, "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1669 ehci_dump_qtd(&sqtd->qtd); 1670 1671 usb_syncmem(&sqtd->dma, sqtd->offs, 1672 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1673 } 1674 1675 Static void 1676 ehci_dump_qtd(ehci_qtd_t *qtd) 1677 { 1678 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1679 uint32_t s = le32toh(qtd->qtd_status); 1680 1681 DPRINTFN(10, 1682 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1683 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1684 DPRINTFN(10, 1685 " toggle = %d ioc = %d bytes = %#x " 1686 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1687 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1688 DPRINTFN(10, 1689 " cerr = %d pid = %d stat = %x", 1690 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1691 0); 1692 DPRINTFN(10, 1693 "active =%d halted=%d buferr=%d babble=%d", 1694 s & EHCI_QTD_ACTIVE ? 1 : 0, 1695 s & EHCI_QTD_HALTED ? 1 : 0, 1696 s & EHCI_QTD_BUFERR ? 1 : 0, 1697 s & EHCI_QTD_BABBLE ? 1 : 0); 1698 DPRINTFN(10, 1699 "xacterr=%d missed=%d split =%d ping =%d", 1700 s & EHCI_QTD_XACTERR ? 1 : 0, 1701 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1702 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1703 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1704 DPRINTFN(10, 1705 "buffer[0] = %#x buffer[1] = %#x " 1706 "buffer[2] = %#x buffer[3] = %#x", 1707 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1708 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1709 DPRINTFN(10, 1710 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1711 } 1712 1713 Static void 1714 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1715 { 1716 ehci_qh_t *qh = &sqh->qh; 1717 ehci_link_t link; 1718 uint32_t endp, endphub; 1719 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1720 1721 usb_syncmem(&sqh->dma, sqh->offs, 1722 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1723 1724 DPRINTFN(10, "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1725 link = le32toh(qh->qh_link); 1726 ehci_dump_link(link, true); 1727 1728 endp = le32toh(qh->qh_endp); 1729 DPRINTFN(10, " endp = %#x", endp, 0, 0, 0); 1730 DPRINTFN(10, " addr = 0x%02x inact = %d endpt = %d eps = %d", 1731 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1732 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1733 DPRINTFN(10, " dtc = %d hrecl = %d", 1734 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1735 DPRINTFN(10, " ctl = %d nrl = %d mpl = %#x(%d)", 1736 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1737 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1738 1739 endphub = le32toh(qh->qh_endphub); 1740 DPRINTFN(10, " endphub = %#x", endphub, 0, 0, 0); 1741 DPRINTFN(10, " smask = 0x%02x cmask = 0x%02x", 1742 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1743 DPRINTFN(10, " huba = 0x%02x port = %d mult = %d", 1744 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1745 EHCI_QH_GET_MULT(endphub), 0); 1746 1747 link = le32toh(qh->qh_curqtd); 1748 ehci_dump_link(link, false); 1749 DPRINTFN(10, "Overlay qTD:", 0, 0, 0, 0); 1750 ehci_dump_qtd(&qh->qh_qtd); 1751 1752 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1753 BUS_DMASYNC_PREREAD); 1754 } 1755 1756 Static void 1757 ehci_dump_itds(ehci_soft_itd_t *itd) 1758 { 1759 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1760 int i; 1761 uint32_t stop = 0; 1762 1763 for (i = 0; itd && i < 20 && !stop; itd = itd->xfer_next, i++) { 1764 ehci_dump_itd(itd); 1765 usb_syncmem(&itd->dma, 1766 itd->offs + offsetof(ehci_itd_t, itd_next), 1767 sizeof(itd->itd), 1768 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1769 stop = itd->itd.itd_next & htole32(EHCI_LINK_TERMINATE); 1770 usb_syncmem(&itd->dma, 1771 itd->offs + offsetof(ehci_itd_t, itd_next), 1772 sizeof(itd->itd), BUS_DMASYNC_PREREAD); 1773 } 1774 if (!stop) 1775 DPRINTF("dump aborted, too many TDs", 0, 0, 0, 0); 1776 } 1777 1778 Static void 1779 ehci_dump_itd(struct ehci_soft_itd *itd) 1780 { 1781 ehci_isoc_trans_t t; 1782 ehci_isoc_bufr_ptr_t b, b2, b3; 1783 int i; 1784 1785 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1786 1787 DPRINTF("ITD: next phys = %#x", itd->itd.itd_next, 0, 0, 0); 1788 1789 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1790 t = le32toh(itd->itd.itd_ctl[i]); 1791 DPRINTF("ITDctl %d: stat = %x len = %x", 1792 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1793 DPRINTF(" ioc = %x pg = %x offs = %x", 1794 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1795 EHCI_ITD_GET_OFFS(t), 0); 1796 } 1797 DPRINTF("ITDbufr: ", 0, 0, 0, 0); 1798 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1799 DPRINTF(" %x", 1800 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1801 1802 b = le32toh(itd->itd.itd_bufr[0]); 1803 b2 = le32toh(itd->itd.itd_bufr[1]); 1804 b3 = le32toh(itd->itd.itd_bufr[2]); 1805 DPRINTF(" ep = %x daddr = %x dir = %d", 1806 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1807 DPRINTF(" maxpkt = %x multi = %x", 1808 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1809 } 1810 1811 Static void 1812 ehci_dump_sitd(struct ehci_soft_itd *itd) 1813 { 1814 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1815 1816 DPRINTF("SITD %p next = %p prev = %p", 1817 itd, itd->frame_list.next, itd->frame_list.prev, 0); 1818 DPRINTF(" xfernext=%p physaddr=%X slot=%d", 1819 itd->xfer_next, itd->physaddr, itd->slot, 0); 1820 } 1821 1822 Static void 1823 ehci_dump_exfer(struct ehci_xfer *ex) 1824 { 1825 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1826 1827 DPRINTF("ex = %p type %d isdone", ex, ex->ex_type, 1828 ex->ex_isdone, 0); 1829 1830 switch (ex->ex_type) { 1831 case EX_CTRL: 1832 DPRINTF(" setup = %p data = %p status = %p", 1833 ex->ex_setup, ex->ex_data, ex->ex_status, 0); 1834 break; 1835 case EX_BULK: 1836 case EX_INTR: 1837 DPRINTF(" qtdstart = %p qtdend = %p", 1838 ex->ex_sqtdstart, ex->ex_sqtdend, 0, 0); 1839 break; 1840 case EX_ISOC: 1841 DPRINTF(" itdstart = %p itdend = %p", 1842 ex->ex_itdstart, ex->ex_itdend, 0, 0); 1843 break; 1844 case EX_FS_ISOC: 1845 DPRINTF(" sitdstart = %p sitdend = %p", 1846 ex->ex_sitdstart, ex->ex_sitdend, 0, 0); 1847 break; 1848 default: 1849 DPRINTF(" unknown type", 0, 0, 0, 0); 1850 } 1851 } 1852 #endif 1853 1854 Static usbd_status 1855 ehci_open(struct usbd_pipe *pipe) 1856 { 1857 struct usbd_device *dev = pipe->up_dev; 1858 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 1859 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1860 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1861 uint8_t addr = dev->ud_addr; 1862 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1863 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 1864 ehci_soft_qh_t *sqh; 1865 usbd_status err; 1866 int ival, speed, naks; 1867 int hshubaddr, hshubport; 1868 1869 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 1870 1871 DPRINTF("pipe=%p, addr=%d, endpt=%d (%d)", pipe, addr, 1872 ed->bEndpointAddress, rhaddr); 1873 1874 if (dev->ud_myhsport) { 1875 /* 1876 * When directly attached FS/LS device while doing embedded 1877 * transaction translations and we are the hub, set the hub 1878 * address to 0 (us). 1879 */ 1880 if (!(sc->sc_flags & EHCIF_ETTF) 1881 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1882 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1883 } else { 1884 hshubaddr = 0; 1885 } 1886 hshubport = dev->ud_myhsport->up_portno; 1887 } else { 1888 hshubaddr = 0; 1889 hshubport = 0; 1890 } 1891 1892 if (sc->sc_dying) 1893 return USBD_IOERROR; 1894 1895 /* toggle state needed for bulk endpoints */ 1896 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1897 1898 if (addr == rhaddr) { 1899 switch (ed->bEndpointAddress) { 1900 case USB_CONTROL_ENDPOINT: 1901 pipe->up_methods = &roothub_ctrl_methods; 1902 break; 1903 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1904 pipe->up_methods = &ehci_root_intr_methods; 1905 break; 1906 default: 1907 DPRINTF("bad bEndpointAddress 0x%02x", 1908 ed->bEndpointAddress, 0, 0, 0); 1909 return USBD_INVAL; 1910 } 1911 return USBD_NORMAL_COMPLETION; 1912 } 1913 1914 /* XXX All this stuff is only valid for async. */ 1915 switch (dev->ud_speed) { 1916 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1917 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1918 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1919 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1920 } 1921 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1922 DPRINTF("hshubaddr=%d hshubport=%d", hshubaddr, hshubport, 0, 1923 0); 1924 return USBD_INVAL; 1925 } 1926 1927 /* 1928 * For interrupt transfer, nak throttling must be disabled, but for 1929 * the other transfer type, nak throttling should be enabled from the 1930 * viewpoint that avoids the memory thrashing. 1931 */ 1932 naks = (xfertype == UE_INTERRUPT) ? 0 1933 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1934 1935 /* Allocate sqh for everything, save isoc xfers */ 1936 if (xfertype != UE_ISOCHRONOUS) { 1937 sqh = ehci_alloc_sqh(sc); 1938 if (sqh == NULL) 1939 return USBD_NOMEM; 1940 /* qh_link filled when the QH is added */ 1941 sqh->qh.qh_endp = htole32( 1942 EHCI_QH_SET_ADDR(addr) | 1943 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1944 EHCI_QH_SET_EPS(speed) | 1945 EHCI_QH_DTC | 1946 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1947 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1948 EHCI_QH_CTL : 0) | 1949 EHCI_QH_SET_NRL(naks) 1950 ); 1951 sqh->qh.qh_endphub = htole32( 1952 EHCI_QH_SET_MULT(1) | 1953 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1954 ); 1955 if (speed != EHCI_QH_SPEED_HIGH) 1956 sqh->qh.qh_endphub |= htole32( 1957 EHCI_QH_SET_PORT(hshubport) | 1958 EHCI_QH_SET_HUBA(hshubaddr) | 1959 (xfertype == UE_INTERRUPT ? 1960 EHCI_QH_SET_CMASK(0x08) : 0) 1961 ); 1962 sqh->qh.qh_curqtd = EHCI_NULL; 1963 /* Fill the overlay qTD */ 1964 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1965 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1966 sqh->qh.qh_qtd.qtd_status = htole32(0); 1967 1968 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1969 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1970 epipe->sqh = sqh; 1971 } else { 1972 sqh = NULL; 1973 } /*xfertype == UE_ISOC*/ 1974 1975 switch (xfertype) { 1976 case UE_CONTROL: 1977 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1978 0, &epipe->ctrl.reqdma); 1979 #ifdef EHCI_DEBUG 1980 if (err) 1981 printf("ehci_open: usb_allocmem()=%d\n", err); 1982 #endif 1983 if (err) 1984 goto bad; 1985 pipe->up_methods = &ehci_device_ctrl_methods; 1986 mutex_enter(&sc->sc_lock); 1987 ehci_add_qh(sc, sqh, sc->sc_async_head); 1988 mutex_exit(&sc->sc_lock); 1989 break; 1990 case UE_BULK: 1991 pipe->up_methods = &ehci_device_bulk_methods; 1992 mutex_enter(&sc->sc_lock); 1993 ehci_add_qh(sc, sqh, sc->sc_async_head); 1994 mutex_exit(&sc->sc_lock); 1995 break; 1996 case UE_INTERRUPT: 1997 pipe->up_methods = &ehci_device_intr_methods; 1998 ival = pipe->up_interval; 1999 if (ival == USBD_DEFAULT_INTERVAL) { 2000 if (speed == EHCI_QH_SPEED_HIGH) { 2001 if (ed->bInterval > 16) { 2002 /* 2003 * illegal with high-speed, but there 2004 * were documentation bugs in the spec, 2005 * so be generous 2006 */ 2007 ival = 256; 2008 } else 2009 ival = (1 << (ed->bInterval - 1)) / 8; 2010 } else 2011 ival = ed->bInterval; 2012 } 2013 err = ehci_device_setintr(sc, sqh, ival); 2014 if (err) 2015 goto bad; 2016 break; 2017 case UE_ISOCHRONOUS: 2018 pipe->up_serialise = false; 2019 if (speed == EHCI_QH_SPEED_HIGH) 2020 pipe->up_methods = &ehci_device_isoc_methods; 2021 else 2022 pipe->up_methods = &ehci_device_fs_isoc_methods; 2023 if (ed->bInterval == 0 || ed->bInterval > 16) { 2024 printf("ehci: opening pipe with invalid bInterval\n"); 2025 err = USBD_INVAL; 2026 goto bad; 2027 } 2028 if (UGETW(ed->wMaxPacketSize) == 0) { 2029 printf("ehci: zero length endpoint open request\n"); 2030 err = USBD_INVAL; 2031 goto bad; 2032 } 2033 epipe->isoc.next_frame = 0; 2034 epipe->isoc.cur_xfers = 0; 2035 break; 2036 default: 2037 DPRINTF("bad xfer type %d", xfertype, 0, 0, 0); 2038 err = USBD_INVAL; 2039 goto bad; 2040 } 2041 return USBD_NORMAL_COMPLETION; 2042 2043 bad: 2044 if (sqh != NULL) { 2045 mutex_enter(&sc->sc_lock); 2046 ehci_free_sqh(sc, sqh); 2047 mutex_exit(&sc->sc_lock); 2048 } 2049 return err; 2050 } 2051 2052 /* 2053 * Add an ED to the schedule. Called with USB lock held. 2054 */ 2055 Static void 2056 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2057 { 2058 2059 KASSERT(mutex_owned(&sc->sc_lock)); 2060 2061 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2062 2063 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2064 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2065 2066 sqh->next = head->next; 2067 sqh->qh.qh_link = head->qh.qh_link; 2068 2069 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2070 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2071 2072 head->next = sqh; 2073 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2074 2075 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2076 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2077 2078 #ifdef EHCI_DEBUG 2079 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 2080 ehci_dump_sqh(sqh); 2081 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 2082 #endif 2083 } 2084 2085 /* 2086 * Remove an ED from the schedule. Called with USB lock held. 2087 */ 2088 Static void 2089 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2090 { 2091 ehci_soft_qh_t *p; 2092 2093 KASSERT(mutex_owned(&sc->sc_lock)); 2094 2095 /* XXX */ 2096 for (p = head; p != NULL && p->next != sqh; p = p->next) 2097 ; 2098 if (p == NULL) 2099 panic("ehci_rem_qh: ED not found"); 2100 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2101 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2102 p->next = sqh->next; 2103 p->qh.qh_link = sqh->qh.qh_link; 2104 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2105 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2106 2107 ehci_sync_hc(sc); 2108 } 2109 2110 Static void 2111 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2112 { 2113 int i; 2114 uint32_t status; 2115 2116 /* Save toggle bit and ping status. */ 2117 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2118 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2119 status = sqh->qh.qh_qtd.qtd_status & 2120 htole32(EHCI_QTD_TOGGLE_MASK | 2121 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2122 /* Set HALTED to make hw leave it alone. */ 2123 sqh->qh.qh_qtd.qtd_status = 2124 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2125 usb_syncmem(&sqh->dma, 2126 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2127 sizeof(sqh->qh.qh_qtd.qtd_status), 2128 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2129 sqh->qh.qh_curqtd = 0; 2130 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2131 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2132 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2133 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2134 sqh->sqtd = sqtd; 2135 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2136 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2137 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2138 sqh->qh.qh_qtd.qtd_status = status; 2139 usb_syncmem(&sqh->dma, 2140 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2141 sizeof(sqh->qh.qh_qtd.qtd_status), 2142 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2143 } 2144 2145 /* 2146 * Ensure that the HC has released all references to the QH. We do this 2147 * by asking for a Async Advance Doorbell interrupt and then we wait for 2148 * the interrupt. 2149 * To make this easier we first obtain exclusive use of the doorbell. 2150 */ 2151 Static void 2152 ehci_sync_hc(ehci_softc_t *sc) 2153 { 2154 int error __diagused; 2155 2156 KASSERT(mutex_owned(&sc->sc_lock)); 2157 2158 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2159 2160 if (sc->sc_dying) { 2161 DPRINTF("dying", 0, 0, 0, 0); 2162 return; 2163 } 2164 2165 /* ask for doorbell */ 2166 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2167 DPRINTF("cmd = 0x%08x sts = 0x%08x", 2168 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2169 2170 sc->sc_dbanswered = false; 2171 /* bell wait */ 2172 while (!sc->sc_dbanswered) { 2173 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); 2174 2175 DPRINTF("cmd = 0x%08x sts = 0x%08x ... done", 2176 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2177 #ifdef DIAGNOSTIC 2178 if (error == EWOULDBLOCK) { 2179 printf("%s: timed out\n", __func__); 2180 } else if (error) { 2181 printf("%s: cv_timedwait: error %d\n", __func__, error); 2182 } 2183 #endif 2184 } 2185 } 2186 2187 Static void 2188 ehci_remove_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2189 { 2190 2191 KASSERT(mutex_owned(&sc->sc_lock)); 2192 2193 for (; itd != NULL; itd = itd->xfer_next) { 2194 struct ehci_soft_itd *prev = itd->frame_list.prev; 2195 2196 /* Unlink itd from hardware chain, or frame array */ 2197 if (prev == NULL) { /* We're at the table head */ 2198 sc->sc_softitds[itd->slot] = itd->frame_list.next; 2199 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2200 usb_syncmem(&sc->sc_fldma, 2201 sizeof(ehci_link_t) * itd->slot, 2202 sizeof(ehci_link_t), 2203 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2204 2205 if (itd->frame_list.next != NULL) 2206 itd->frame_list.next->frame_list.prev = NULL; 2207 } else { 2208 /* XXX this part is untested... */ 2209 prev->itd.itd_next = itd->itd.itd_next; 2210 usb_syncmem(&itd->dma, 2211 itd->offs + offsetof(ehci_itd_t, itd_next), 2212 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2213 2214 prev->frame_list.next = itd->frame_list.next; 2215 if (itd->frame_list.next != NULL) 2216 itd->frame_list.next->frame_list.prev = prev; 2217 } 2218 } 2219 } 2220 2221 Static void 2222 ehci_free_itd_chain(ehci_softc_t *sc, struct ehci_soft_itd *itd) 2223 { 2224 struct ehci_soft_itd *next; 2225 2226 mutex_enter(&sc->sc_lock); 2227 next = NULL; 2228 for (; itd != NULL; itd = next) { 2229 next = itd->xfer_next; 2230 ehci_free_itd_locked(sc, itd); 2231 } 2232 mutex_exit(&sc->sc_lock); 2233 } 2234 2235 Static void 2236 ehci_remove_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2237 { 2238 2239 KASSERT(mutex_owned(&sc->sc_lock)); 2240 2241 for (; sitd != NULL; sitd = sitd->xfer_next) { 2242 struct ehci_soft_sitd *prev = sitd->frame_list.prev; 2243 2244 /* Unlink sitd from hardware chain, or frame array */ 2245 if (prev == NULL) { /* We're at the table head */ 2246 sc->sc_softsitds[sitd->slot] = sitd->frame_list.next; 2247 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2248 usb_syncmem(&sc->sc_fldma, 2249 sizeof(ehci_link_t) * sitd->slot, 2250 sizeof(ehci_link_t), 2251 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2252 2253 if (sitd->frame_list.next != NULL) 2254 sitd->frame_list.next->frame_list.prev = NULL; 2255 } else { 2256 /* XXX this part is untested... */ 2257 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2258 usb_syncmem(&sitd->dma, 2259 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2260 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2261 2262 prev->frame_list.next = sitd->frame_list.next; 2263 if (sitd->frame_list.next != NULL) 2264 sitd->frame_list.next->frame_list.prev = prev; 2265 } 2266 } 2267 } 2268 2269 Static void 2270 ehci_free_sitd_chain(ehci_softc_t *sc, struct ehci_soft_sitd *sitd) 2271 { 2272 2273 mutex_enter(&sc->sc_lock); 2274 struct ehci_soft_sitd *next = NULL; 2275 for (; sitd != NULL; sitd = next) { 2276 next = sitd->xfer_next; 2277 ehci_free_sitd_locked(sc, sitd); 2278 } 2279 mutex_exit(&sc->sc_lock); 2280 } 2281 2282 /***********/ 2283 2284 Static int 2285 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2286 void *buf, int buflen) 2287 { 2288 ehci_softc_t *sc = EHCI_BUS2SC(bus); 2289 usb_hub_descriptor_t hubd; 2290 usb_port_status_t ps; 2291 uint16_t len, value, index; 2292 int l, totlen = 0; 2293 int port, i; 2294 uint32_t v; 2295 2296 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2297 2298 if (sc->sc_dying) 2299 return -1; 2300 2301 DPRINTF("type=0x%02x request=%02x", req->bmRequestType, req->bRequest, 2302 0, 0); 2303 2304 len = UGETW(req->wLength); 2305 value = UGETW(req->wValue); 2306 index = UGETW(req->wIndex); 2307 2308 #define C(x,y) ((x) | ((y) << 8)) 2309 switch (C(req->bRequest, req->bmRequestType)) { 2310 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2311 if (len == 0) 2312 break; 2313 switch (value) { 2314 case C(0, UDESC_DEVICE): { 2315 usb_device_descriptor_t devd; 2316 totlen = min(buflen, sizeof(devd)); 2317 memcpy(&devd, buf, totlen); 2318 USETW(devd.idVendor, sc->sc_id_vendor); 2319 memcpy(buf, &devd, totlen); 2320 break; 2321 2322 } 2323 #define sd ((usb_string_descriptor_t *)buf) 2324 case C(1, UDESC_STRING): 2325 /* Vendor */ 2326 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2327 break; 2328 case C(2, UDESC_STRING): 2329 /* Product */ 2330 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2331 break; 2332 #undef sd 2333 default: 2334 /* default from usbroothub */ 2335 return buflen; 2336 } 2337 break; 2338 2339 /* Hub requests */ 2340 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2341 break; 2342 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2343 DPRINTF("UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, 2344 value, 0, 0); 2345 if (index < 1 || index > sc->sc_noport) { 2346 return -1; 2347 } 2348 port = EHCI_PORTSC(index); 2349 v = EOREAD4(sc, port); 2350 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2351 v &= ~EHCI_PS_CLEAR; 2352 switch (value) { 2353 case UHF_PORT_ENABLE: 2354 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2355 break; 2356 case UHF_PORT_SUSPEND: 2357 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2358 break; 2359 v &= ~EHCI_PS_SUSP; 2360 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2361 /* see USB2 spec ch. 7.1.7.7 */ 2362 usb_delay_ms(&sc->sc_bus, 20); 2363 EOWRITE4(sc, port, v); 2364 usb_delay_ms(&sc->sc_bus, 2); 2365 #ifdef DEBUG 2366 v = EOREAD4(sc, port); 2367 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2368 printf("ehci: resume failed: %x\n", v); 2369 #endif 2370 break; 2371 case UHF_PORT_POWER: 2372 if (sc->sc_hasppc) 2373 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2374 break; 2375 case UHF_PORT_TEST: 2376 DPRINTF("clear port test %d", index, 0, 0, 0); 2377 break; 2378 case UHF_PORT_INDICATOR: 2379 DPRINTF("clear port ind %d", index, 0, 0, 0); 2380 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2381 break; 2382 case UHF_C_PORT_CONNECTION: 2383 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2384 break; 2385 case UHF_C_PORT_ENABLE: 2386 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2387 break; 2388 case UHF_C_PORT_SUSPEND: 2389 /* how? */ 2390 break; 2391 case UHF_C_PORT_OVER_CURRENT: 2392 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2393 break; 2394 case UHF_C_PORT_RESET: 2395 sc->sc_isreset[index] = 0; 2396 break; 2397 default: 2398 return -1; 2399 } 2400 #if 0 2401 switch(value) { 2402 case UHF_C_PORT_CONNECTION: 2403 case UHF_C_PORT_ENABLE: 2404 case UHF_C_PORT_SUSPEND: 2405 case UHF_C_PORT_OVER_CURRENT: 2406 case UHF_C_PORT_RESET: 2407 default: 2408 break; 2409 } 2410 #endif 2411 break; 2412 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2413 if (len == 0) 2414 break; 2415 if ((value & 0xff) != 0) { 2416 return -1; 2417 } 2418 totlen = min(buflen, sizeof(hubd)); 2419 memcpy(&hubd, buf, totlen); 2420 hubd.bNbrPorts = sc->sc_noport; 2421 v = EOREAD4(sc, EHCI_HCSPARAMS); 2422 USETW(hubd.wHubCharacteristics, 2423 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2424 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2425 ? UHD_PORT_IND : 0); 2426 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2427 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2428 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2429 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2430 totlen = min(totlen, hubd.bDescLength); 2431 memcpy(buf, &hubd, totlen); 2432 break; 2433 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2434 if (len != 4) { 2435 return -1; 2436 } 2437 memset(buf, 0, len); /* ? XXX */ 2438 totlen = len; 2439 break; 2440 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2441 DPRINTF("get port status i=%d", index, 0, 0, 0); 2442 if (index < 1 || index > sc->sc_noport) { 2443 return -1; 2444 } 2445 if (len != 4) { 2446 return -1; 2447 } 2448 v = EOREAD4(sc, EHCI_PORTSC(index)); 2449 DPRINTF("port status=0x%04x", v, 0, 0, 0); 2450 2451 i = UPS_HIGH_SPEED; 2452 if (sc->sc_flags & EHCIF_ETTF) { 2453 /* 2454 * If we are doing embedded transaction translation, 2455 * then directly attached LS/FS devices are reset by 2456 * the EHCI controller itself. PSPD is encoded 2457 * the same way as in USBSTATUS. 2458 */ 2459 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2460 } 2461 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2462 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2463 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2464 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2465 if (v & EHCI_PS_PR) i |= UPS_RESET; 2466 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2467 if (sc->sc_vendor_port_status) 2468 i = sc->sc_vendor_port_status(sc, v, i); 2469 USETW(ps.wPortStatus, i); 2470 i = 0; 2471 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2472 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2473 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2474 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2475 USETW(ps.wPortChange, i); 2476 totlen = min(len, sizeof(ps)); 2477 memcpy(buf, &ps, totlen); 2478 break; 2479 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2480 return -1; 2481 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2482 break; 2483 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2484 if (index < 1 || index > sc->sc_noport) { 2485 return -1; 2486 } 2487 port = EHCI_PORTSC(index); 2488 v = EOREAD4(sc, port); 2489 DPRINTF("portsc=0x%08x", v, 0, 0, 0); 2490 v &= ~EHCI_PS_CLEAR; 2491 switch(value) { 2492 case UHF_PORT_ENABLE: 2493 EOWRITE4(sc, port, v | EHCI_PS_PE); 2494 break; 2495 case UHF_PORT_SUSPEND: 2496 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2497 break; 2498 case UHF_PORT_RESET: 2499 DPRINTF("reset port %d", index, 0, 0, 0); 2500 if (EHCI_PS_IS_LOWSPEED(v) 2501 && sc->sc_ncomp > 0 2502 && !(sc->sc_flags & EHCIF_ETTF)) { 2503 /* 2504 * Low speed device on non-ETTF controller or 2505 * unaccompanied controller, give up ownership. 2506 */ 2507 ehci_disown(sc, index, 1); 2508 break; 2509 } 2510 /* Start reset sequence. */ 2511 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2512 EOWRITE4(sc, port, v | EHCI_PS_PR); 2513 /* Wait for reset to complete. */ 2514 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2515 if (sc->sc_dying) { 2516 return -1; 2517 } 2518 /* 2519 * An embedded transaction translator will automatically 2520 * terminate the reset sequence so there's no need to 2521 * it. 2522 */ 2523 v = EOREAD4(sc, port); 2524 if (v & EHCI_PS_PR) { 2525 /* Terminate reset sequence. */ 2526 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2527 /* Wait for HC to complete reset. */ 2528 usb_delay_ms(&sc->sc_bus, 2529 EHCI_PORT_RESET_COMPLETE); 2530 if (sc->sc_dying) { 2531 return -1; 2532 } 2533 } 2534 2535 v = EOREAD4(sc, port); 2536 DPRINTF("ehci after reset, status=0x%08x", v, 0, 0, 0); 2537 if (v & EHCI_PS_PR) { 2538 printf("%s: port reset timeout\n", 2539 device_xname(sc->sc_dev)); 2540 return USBD_TIMEOUT; 2541 } 2542 if (!(v & EHCI_PS_PE)) { 2543 /* Not a high speed device, give up ownership.*/ 2544 ehci_disown(sc, index, 0); 2545 break; 2546 } 2547 sc->sc_isreset[index] = 1; 2548 DPRINTF("ehci port %d reset, status = 0x%08x", index, 2549 v, 0, 0); 2550 break; 2551 case UHF_PORT_POWER: 2552 DPRINTF("set port power %d (has PPC = %d)", index, 2553 sc->sc_hasppc, 0, 0); 2554 if (sc->sc_hasppc) 2555 EOWRITE4(sc, port, v | EHCI_PS_PP); 2556 break; 2557 case UHF_PORT_TEST: 2558 DPRINTF("set port test %d", index, 0, 0, 0); 2559 break; 2560 case UHF_PORT_INDICATOR: 2561 DPRINTF("set port ind %d", index, 0, 0, 0); 2562 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2563 break; 2564 default: 2565 return -1; 2566 } 2567 break; 2568 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2569 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2570 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2571 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2572 break; 2573 default: 2574 /* default from usbroothub */ 2575 DPRINTF("returning %d (usbroothub default)", buflen, 0, 0, 0); 2576 2577 return buflen; 2578 } 2579 2580 DPRINTF("returning %d", totlen, 0, 0, 0); 2581 2582 return totlen; 2583 } 2584 2585 Static void 2586 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2587 { 2588 int port; 2589 uint32_t v; 2590 2591 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2592 2593 DPRINTF("index=%d lowspeed=%d", index, lowspeed, 0, 0); 2594 #ifdef DIAGNOSTIC 2595 if (sc->sc_npcomp != 0) { 2596 int i = (index-1) / sc->sc_npcomp; 2597 if (i >= sc->sc_ncomp) 2598 printf("%s: strange port\n", 2599 device_xname(sc->sc_dev)); 2600 else 2601 printf("%s: handing over %s speed device on " 2602 "port %d to %s\n", 2603 device_xname(sc->sc_dev), 2604 lowspeed ? "low" : "full", 2605 index, sc->sc_comps[i] ? 2606 device_xname(sc->sc_comps[i]) : 2607 "companion controller"); 2608 } else { 2609 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2610 } 2611 #endif 2612 port = EHCI_PORTSC(index); 2613 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2614 EOWRITE4(sc, port, v | EHCI_PS_PO); 2615 } 2616 2617 Static usbd_status 2618 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2619 { 2620 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2621 usbd_status err; 2622 2623 /* Insert last in queue. */ 2624 mutex_enter(&sc->sc_lock); 2625 err = usb_insert_transfer(xfer); 2626 mutex_exit(&sc->sc_lock); 2627 if (err) 2628 return err; 2629 2630 /* Pipe isn't running, start first */ 2631 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2632 } 2633 2634 Static usbd_status 2635 ehci_root_intr_start(struct usbd_xfer *xfer) 2636 { 2637 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2638 2639 if (sc->sc_dying) 2640 return USBD_IOERROR; 2641 2642 mutex_enter(&sc->sc_lock); 2643 sc->sc_intrxfer = xfer; 2644 mutex_exit(&sc->sc_lock); 2645 2646 return USBD_IN_PROGRESS; 2647 } 2648 2649 /* Abort a root interrupt request. */ 2650 Static void 2651 ehci_root_intr_abort(struct usbd_xfer *xfer) 2652 { 2653 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 2654 2655 KASSERT(mutex_owned(&sc->sc_lock)); 2656 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2657 2658 sc->sc_intrxfer = NULL; 2659 2660 xfer->ux_status = USBD_CANCELLED; 2661 usb_transfer_complete(xfer); 2662 } 2663 2664 /* Close the root pipe. */ 2665 Static void 2666 ehci_root_intr_close(struct usbd_pipe *pipe) 2667 { 2668 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 2669 2670 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2671 2672 KASSERT(mutex_owned(&sc->sc_lock)); 2673 2674 sc->sc_intrxfer = NULL; 2675 } 2676 2677 Static void 2678 ehci_root_intr_done(struct usbd_xfer *xfer) 2679 { 2680 } 2681 2682 /************************/ 2683 2684 Static ehci_soft_qh_t * 2685 ehci_alloc_sqh(ehci_softc_t *sc) 2686 { 2687 ehci_soft_qh_t *sqh; 2688 usbd_status err; 2689 int i, offs; 2690 usb_dma_t dma; 2691 2692 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2693 2694 mutex_enter(&sc->sc_lock); 2695 if (sc->sc_freeqhs == NULL) { 2696 DPRINTF("allocating chunk", 0, 0, 0, 0); 2697 mutex_exit(&sc->sc_lock); 2698 2699 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2700 EHCI_PAGE_SIZE, &dma); 2701 #ifdef EHCI_DEBUG 2702 if (err) 2703 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2704 #endif 2705 if (err) 2706 return NULL; 2707 2708 mutex_enter(&sc->sc_lock); 2709 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2710 offs = i * EHCI_SQH_SIZE; 2711 sqh = KERNADDR(&dma, offs); 2712 sqh->physaddr = DMAADDR(&dma, offs); 2713 sqh->dma = dma; 2714 sqh->offs = offs; 2715 sqh->next = sc->sc_freeqhs; 2716 sc->sc_freeqhs = sqh; 2717 } 2718 } 2719 sqh = sc->sc_freeqhs; 2720 sc->sc_freeqhs = sqh->next; 2721 mutex_exit(&sc->sc_lock); 2722 2723 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2724 sqh->next = NULL; 2725 return sqh; 2726 } 2727 2728 Static void 2729 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2730 { 2731 KASSERT(mutex_owned(&sc->sc_lock)); 2732 2733 sqh->next = sc->sc_freeqhs; 2734 sc->sc_freeqhs = sqh; 2735 } 2736 2737 Static ehci_soft_qtd_t * 2738 ehci_alloc_sqtd(ehci_softc_t *sc) 2739 { 2740 ehci_soft_qtd_t *sqtd = NULL; 2741 usbd_status err; 2742 int i, offs; 2743 usb_dma_t dma; 2744 2745 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2746 2747 mutex_enter(&sc->sc_lock); 2748 if (sc->sc_freeqtds == NULL) { 2749 DPRINTF("allocating chunk", 0, 0, 0, 0); 2750 mutex_exit(&sc->sc_lock); 2751 2752 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2753 EHCI_PAGE_SIZE, &dma); 2754 #ifdef EHCI_DEBUG 2755 if (err) 2756 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2757 #endif 2758 if (err) 2759 goto done; 2760 2761 mutex_enter(&sc->sc_lock); 2762 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2763 offs = i * EHCI_SQTD_SIZE; 2764 sqtd = KERNADDR(&dma, offs); 2765 sqtd->physaddr = DMAADDR(&dma, offs); 2766 sqtd->dma = dma; 2767 sqtd->offs = offs; 2768 2769 sqtd->nextqtd = sc->sc_freeqtds; 2770 sc->sc_freeqtds = sqtd; 2771 } 2772 } 2773 2774 sqtd = sc->sc_freeqtds; 2775 sc->sc_freeqtds = sqtd->nextqtd; 2776 mutex_exit(&sc->sc_lock); 2777 2778 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2779 sqtd->nextqtd = NULL; 2780 sqtd->xfer = NULL; 2781 2782 done: 2783 return sqtd; 2784 } 2785 2786 Static void 2787 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2788 { 2789 2790 mutex_enter(&sc->sc_lock); 2791 sqtd->nextqtd = sc->sc_freeqtds; 2792 sc->sc_freeqtds = sqtd; 2793 mutex_exit(&sc->sc_lock); 2794 } 2795 2796 Static int 2797 ehci_alloc_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2798 int alen, int rd, ehci_soft_qtd_t **sp) 2799 { 2800 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2801 uint16_t flags = xfer->ux_flags; 2802 2803 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2804 2805 ASSERT_SLEEPABLE(); 2806 KASSERT(sp); 2807 KASSERT(alen != 0 || (!rd && (flags & USBD_FORCE_SHORT_XFER))); 2808 2809 size_t nsqtd = (!rd && (flags & USBD_FORCE_SHORT_XFER)) ? 1 : 0; 2810 nsqtd += ((alen + EHCI_PAGE_SIZE - 1) / EHCI_PAGE_SIZE); 2811 exfer->ex_sqtds = kmem_zalloc(sizeof(ehci_soft_qtd_t *) * nsqtd, 2812 KM_SLEEP); 2813 exfer->ex_nsqtd = nsqtd; 2814 2815 DPRINTF("xfer %p len %d nsqtd %d flags %x", xfer, alen, nsqtd, flags); 2816 2817 for (size_t j = 0; j < exfer->ex_nsqtd;) { 2818 ehci_soft_qtd_t *cur = ehci_alloc_sqtd(sc); 2819 if (cur == NULL) 2820 goto nomem; 2821 exfer->ex_sqtds[j++] = cur; 2822 2823 cur->xfer = xfer; 2824 cur->len = 0; 2825 2826 } 2827 2828 *sp = exfer->ex_sqtds[0]; 2829 DPRINTF("return sqtd=%p", *sp, 0, 0, 0); 2830 2831 return 0; 2832 2833 nomem: 2834 ehci_free_sqtds(sc, exfer); 2835 kmem_free(exfer->ex_sqtds, sizeof(ehci_soft_qtd_t *) * nsqtd); 2836 DPRINTF("no memory", 0, 0, 0, 0); 2837 return ENOMEM; 2838 } 2839 2840 Static void 2841 ehci_free_sqtds(ehci_softc_t *sc, struct ehci_xfer *exfer) 2842 { 2843 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2844 DPRINTF("exfer=%p", exfer, 0, 0, 0); 2845 2846 mutex_enter(&sc->sc_lock); 2847 for (size_t i = 0; i < exfer->ex_nsqtd; i++) { 2848 ehci_soft_qtd_t *sqtd = exfer->ex_sqtds[i]; 2849 2850 if (sqtd == NULL) 2851 break; 2852 2853 sqtd->nextqtd = sc->sc_freeqtds; 2854 sc->sc_freeqtds = sqtd; 2855 } 2856 mutex_exit(&sc->sc_lock); 2857 } 2858 2859 Static void 2860 ehci_append_sqtd(ehci_soft_qtd_t *sqtd, ehci_soft_qtd_t *prev) 2861 { 2862 if (prev) { 2863 prev->nextqtd = sqtd; 2864 prev->qtd.qtd_next = htole32(sqtd->physaddr); 2865 prev->qtd.qtd_altnext = prev->qtd.qtd_next; 2866 usb_syncmem(&prev->dma, prev->offs, sizeof(prev->qtd), 2867 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2868 } 2869 } 2870 2871 Static void 2872 ehci_reset_sqtd_chain(ehci_softc_t *sc, struct usbd_xfer *xfer, 2873 int length, int isread, int *toggle, ehci_soft_qtd_t **lsqtd) 2874 { 2875 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 2876 usb_dma_t *dma = &xfer->ux_dmabuf; 2877 uint16_t flags = xfer->ux_flags; 2878 ehci_soft_qtd_t *sqtd, *prev; 2879 int tog = *toggle; 2880 int mps = UGETW(xfer->ux_pipe->up_endpoint->ue_edesc->wMaxPacketSize); 2881 int len = length; 2882 2883 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2884 DPRINTF("xfer=%p len %d isread %d toggle %d", xfer, len, isread, tog); 2885 DPRINTF(" VA %p", KERNADDR(&xfer->ux_dmabuf, 0), 0, 0, 0); 2886 2887 KASSERT(length != 0 || (!isread && (flags & USBD_FORCE_SHORT_XFER))); 2888 2889 const uint32_t qtdstatus = EHCI_QTD_ACTIVE | 2890 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2891 EHCI_QTD_SET_CERR(3) 2892 ; 2893 2894 sqtd = prev = NULL; 2895 size_t curoffs = 0; 2896 size_t j = 0; 2897 for (; len != 0 && j < exfer->ex_nsqtd; prev = sqtd) { 2898 sqtd = exfer->ex_sqtds[j++]; 2899 DPRINTF("sqtd[%d]=%p prev %p", j, sqtd, prev, 0); 2900 2901 /* 2902 * The EHCI hardware can handle at most 5 pages and they do 2903 * not have to be contiguous 2904 */ 2905 vaddr_t va = (vaddr_t)KERNADDR(dma, curoffs); 2906 vaddr_t va_offs = EHCI_PAGE_OFFSET(va); 2907 size_t curlen = len; 2908 if (curlen >= EHCI_QTD_MAXTRANSFER - va_offs) { 2909 /* must use multiple TDs, fill as much as possible. */ 2910 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2911 2912 /* the length must be a multiple of the max size */ 2913 curlen -= curlen % mps; 2914 } 2915 KASSERT(curlen != 0); 2916 DPRINTF(" len=%d curlen=%d curoffs=%zu", len, curlen, 2917 curoffs, 0); 2918 2919 /* Fill the qTD */ 2920 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2921 sqtd->qtd.qtd_status = htole32( 2922 qtdstatus | 2923 EHCI_QTD_SET_BYTES(curlen) | 2924 EHCI_QTD_SET_TOGGLE(tog)); 2925 2926 /* Find number of pages we'll be using, insert dma addresses */ 2927 size_t pages = EHCI_NPAGES(curlen); 2928 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2929 size_t pageoffs = EHCI_PAGE(curoffs); 2930 for (size_t i = 0; i < pages; i++) { 2931 paddr_t a = DMAADDR(dma, 2932 pageoffs + i * EHCI_PAGE_SIZE); 2933 sqtd->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2934 /* Cast up to avoid compiler warnings */ 2935 sqtd->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2936 DPRINTF(" buffer[%d/%d] 0x%08x 0x%08x", i, pages, 2937 le32toh(sqtd->qtd.qtd_buffer_hi[i]), 2938 le32toh(sqtd->qtd.qtd_buffer[i])); 2939 } 2940 /* First buffer pointer requires a page offset to start at */ 2941 sqtd->qtd.qtd_buffer[0] |= htole32(va_offs); 2942 2943 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2944 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2945 2946 sqtd->len = curlen; 2947 2948 DPRINTF(" va %p pa %p len %d", va, 2949 DMAADDR(&xfer->ux_dmabuf, curoffs), curlen, 0); 2950 2951 ehci_append_sqtd(sqtd, prev); 2952 2953 if (((curlen + mps - 1) / mps) & 1) { 2954 tog ^= 1; 2955 } 2956 2957 curoffs += curlen; 2958 len -= curlen; 2959 } 2960 KASSERTMSG(len == 0, "xfer %p olen %d len %d mps %d ex_nsqtd %zu j %zu", 2961 xfer, length, len, mps, exfer->ex_nsqtd, j); 2962 2963 if (!isread && 2964 (flags & USBD_FORCE_SHORT_XFER) && 2965 length % mps == 0) { 2966 /* Force a 0 length transfer at the end. */ 2967 2968 KASSERTMSG(j < exfer->ex_nsqtd, "j=%zu nsqtd=%zu", j, 2969 exfer->ex_nsqtd); 2970 prev = sqtd; 2971 sqtd = exfer->ex_sqtds[j++]; 2972 memset(&sqtd->qtd, 0, sizeof(sqtd->qtd)); 2973 sqtd->qtd.qtd_next = sqtd->qtd.qtd_altnext = EHCI_NULL; 2974 sqtd->qtd.qtd_status = htole32( 2975 qtdstatus | 2976 EHCI_QTD_SET_BYTES(0) | 2977 EHCI_QTD_SET_TOGGLE(tog)); 2978 2979 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 2980 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2981 2982 ehci_append_sqtd(sqtd, prev); 2983 tog ^= 1; 2984 } 2985 2986 *lsqtd = sqtd; 2987 *toggle = tog; 2988 } 2989 2990 Static ehci_soft_itd_t * 2991 ehci_alloc_itd(ehci_softc_t *sc) 2992 { 2993 struct ehci_soft_itd *itd, *freeitd; 2994 usbd_status err; 2995 usb_dma_t dma; 2996 2997 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 2998 2999 mutex_enter(&sc->sc_lock); 3000 3001 freeitd = LIST_FIRST(&sc->sc_freeitds); 3002 if (freeitd == NULL) { 3003 DPRINTF("allocating chunk", 0, 0, 0, 0); 3004 mutex_exit(&sc->sc_lock); 3005 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 3006 EHCI_PAGE_SIZE, &dma); 3007 3008 if (err) { 3009 DPRINTF("alloc returned %d", err, 0, 0, 0); 3010 return NULL; 3011 } 3012 mutex_enter(&sc->sc_lock); 3013 3014 for (int i = 0; i < EHCI_ITD_CHUNK; i++) { 3015 int offs = i * EHCI_ITD_SIZE; 3016 itd = KERNADDR(&dma, offs); 3017 itd->physaddr = DMAADDR(&dma, offs); 3018 itd->dma = dma; 3019 itd->offs = offs; 3020 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, free_list); 3021 } 3022 freeitd = LIST_FIRST(&sc->sc_freeitds); 3023 } 3024 3025 itd = freeitd; 3026 LIST_REMOVE(itd, free_list); 3027 mutex_exit(&sc->sc_lock); 3028 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 3029 3030 itd->frame_list.next = NULL; 3031 itd->frame_list.prev = NULL; 3032 itd->xfer_next = NULL; 3033 itd->slot = 0; 3034 3035 return itd; 3036 } 3037 3038 Static ehci_soft_sitd_t * 3039 ehci_alloc_sitd(ehci_softc_t *sc) 3040 { 3041 struct ehci_soft_sitd *sitd, *freesitd; 3042 usbd_status err; 3043 int i, offs; 3044 usb_dma_t dma; 3045 3046 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3047 3048 mutex_enter(&sc->sc_lock); 3049 freesitd = LIST_FIRST(&sc->sc_freesitds); 3050 if (freesitd == NULL) { 3051 DPRINTF("allocating chunk", 0, 0, 0, 0); 3052 mutex_exit(&sc->sc_lock); 3053 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3054 EHCI_PAGE_SIZE, &dma); 3055 3056 if (err) { 3057 DPRINTF("alloc returned %d", err, 0, 0, 3058 0); 3059 return NULL; 3060 } 3061 3062 mutex_enter(&sc->sc_lock); 3063 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3064 offs = i * EHCI_SITD_SIZE; 3065 sitd = KERNADDR(&dma, offs); 3066 sitd->physaddr = DMAADDR(&dma, offs); 3067 sitd->dma = dma; 3068 sitd->offs = offs; 3069 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, free_list); 3070 } 3071 freesitd = LIST_FIRST(&sc->sc_freesitds); 3072 } 3073 3074 sitd = freesitd; 3075 LIST_REMOVE(sitd, free_list); 3076 mutex_exit(&sc->sc_lock); 3077 3078 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3079 3080 sitd->frame_list.next = NULL; 3081 sitd->frame_list.prev = NULL; 3082 sitd->xfer_next = NULL; 3083 sitd->slot = 0; 3084 3085 return sitd; 3086 } 3087 3088 /****************/ 3089 3090 /* 3091 * Close a reqular pipe. 3092 * Assumes that there are no pending transactions. 3093 */ 3094 Static void 3095 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3096 { 3097 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3098 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3099 ehci_soft_qh_t *sqh = epipe->sqh; 3100 3101 KASSERT(mutex_owned(&sc->sc_lock)); 3102 3103 ehci_rem_qh(sc, sqh, head); 3104 ehci_free_sqh(sc, epipe->sqh); 3105 } 3106 3107 /* 3108 * Cancel or timeout a device request. We have two cases to deal with 3109 * 3110 * 1) A driver wants to stop scheduled or inflight transfers 3111 * 2) A transfer has timed out 3112 * 3113 * have (partially) happened since the hardware runs concurrently. 3114 * 3115 * Transfer state is protected by the bus lock and we set the transfer status 3116 * as soon as either of the above happens (with bus lock held). 3117 * 3118 * Then we arrange for the hardware to tells us that it is not still 3119 * processing the TDs by setting the QH halted bit and wait for the ehci 3120 * door bell 3121 */ 3122 Static void 3123 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3124 { 3125 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3126 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3127 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3128 ehci_soft_qh_t *sqh = epipe->sqh; 3129 ehci_soft_qtd_t *sqtd, *fsqtd, *lsqtd; 3130 ehci_physaddr_t cur; 3131 uint32_t qhstatus; 3132 int hit; 3133 int wake; 3134 3135 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3136 3137 DPRINTF("xfer=%p pipe=%p", xfer, epipe, 0, 0); 3138 3139 KASSERT(mutex_owned(&sc->sc_lock)); 3140 ASSERT_SLEEPABLE(); 3141 3142 if (sc->sc_dying) { 3143 /* If we're dying, just do the software part. */ 3144 xfer->ux_status = status; 3145 callout_halt(&xfer->ux_callout, &sc->sc_lock); 3146 KASSERT(xfer->ux_status == status); 3147 usb_transfer_complete(xfer); 3148 return; 3149 } 3150 3151 /* 3152 * If an abort is already in progress then just wait for it to 3153 * complete and return. 3154 */ 3155 if (xfer->ux_hcflags & UXFER_ABORTING) { 3156 DPRINTF("already aborting", 0, 0, 0, 0); 3157 #ifdef DIAGNOSTIC 3158 if (status == USBD_TIMEOUT) 3159 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3160 #endif 3161 /* Override the status which might be USBD_TIMEOUT. */ 3162 xfer->ux_status = status; 3163 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3164 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3165 while (xfer->ux_hcflags & UXFER_ABORTING) 3166 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3167 return; 3168 } 3169 xfer->ux_hcflags |= UXFER_ABORTING; 3170 3171 /* 3172 * Step 1: When cancelling a transfer make sure the timeout handler 3173 * didn't run or ran to the end and saw the USBD_CANCELLED status. 3174 * Otherwise we must have got here via a timeout. 3175 */ 3176 if (status == USBD_CANCELLED) { 3177 xfer->ux_status = status; 3178 callout_halt(&xfer->ux_callout, &sc->sc_lock); 3179 } else { 3180 KASSERT(xfer->ux_status == USBD_TIMEOUT); 3181 } 3182 3183 /* 3184 * Step 2: Make interrupt routine and hardware ignore xfer. 3185 */ 3186 ehci_del_intr_list(sc, exfer); 3187 3188 usb_syncmem(&sqh->dma, 3189 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3190 sizeof(sqh->qh.qh_qtd.qtd_status), 3191 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3192 qhstatus = sqh->qh.qh_qtd.qtd_status; 3193 if (exfer->ex_type == EX_CTRL) { 3194 fsqtd = exfer->ex_setup; 3195 lsqtd = exfer->ex_status; 3196 } else { 3197 fsqtd = exfer->ex_sqtdstart; 3198 lsqtd = exfer->ex_sqtdend; 3199 } 3200 if (!(qhstatus & htole32(EHCI_QTD_HALTED))) { 3201 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3202 usb_syncmem(&sqh->dma, 3203 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3204 sizeof(sqh->qh.qh_qtd.qtd_status), 3205 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3206 3207 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3208 usb_syncmem(&sqtd->dma, 3209 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3210 sizeof(sqtd->qtd.qtd_status), 3211 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3212 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3213 usb_syncmem(&sqtd->dma, 3214 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3215 sizeof(sqtd->qtd.qtd_status), 3216 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3217 if (sqtd == lsqtd) 3218 break; 3219 } 3220 } 3221 3222 /* 3223 * Step 3: Wait until we know hardware has finished any possible 3224 * use of the xfer. 3225 */ 3226 ehci_sync_hc(sc); 3227 3228 /* 3229 * Step 4: Remove any vestiges of the xfer from the hardware. 3230 * The complication here is that the hardware may have executed 3231 * beyond the xfer we're trying to abort. So as we're scanning 3232 * the TDs of this xfer we check if the hardware points to 3233 * any of them. 3234 */ 3235 3236 usb_syncmem(&sqh->dma, 3237 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3238 sizeof(sqh->qh.qh_curqtd), 3239 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3240 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3241 hit = 0; 3242 for (sqtd = fsqtd; ; sqtd = sqtd->nextqtd) { 3243 hit |= cur == sqtd->physaddr; 3244 if (sqtd == lsqtd) 3245 break; 3246 } 3247 sqtd = sqtd->nextqtd; 3248 /* Zap curqtd register if hardware pointed inside the xfer. */ 3249 if (hit && sqtd != NULL) { 3250 DPRINTF("cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3251 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3252 usb_syncmem(&sqh->dma, 3253 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3254 sizeof(sqh->qh.qh_curqtd), 3255 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3256 sqh->qh.qh_qtd.qtd_status = qhstatus; 3257 usb_syncmem(&sqh->dma, 3258 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3259 sizeof(sqh->qh.qh_qtd.qtd_status), 3260 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3261 } else { 3262 DPRINTF("no hit", 0, 0, 0, 0); 3263 usb_syncmem(&sqh->dma, 3264 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3265 sizeof(sqh->qh.qh_curqtd), 3266 BUS_DMASYNC_PREREAD); 3267 } 3268 3269 /* 3270 * Step 5: Execute callback. 3271 */ 3272 #ifdef DIAGNOSTIC 3273 exfer->ex_isdone = true; 3274 #endif 3275 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3276 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3277 usb_transfer_complete(xfer); 3278 if (wake) { 3279 cv_broadcast(&xfer->ux_hccv); 3280 } 3281 3282 KASSERT(mutex_owned(&sc->sc_lock)); 3283 } 3284 3285 Static void 3286 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3287 { 3288 ehci_isoc_trans_t trans_status; 3289 struct ehci_xfer *exfer; 3290 ehci_softc_t *sc; 3291 struct ehci_soft_itd *itd; 3292 struct ehci_soft_sitd *sitd; 3293 int i, wake; 3294 3295 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3296 3297 exfer = EHCI_XFER2EXFER(xfer); 3298 sc = EHCI_XFER2SC(xfer); 3299 3300 DPRINTF("xfer %p pipe %p", xfer, xfer->ux_pipe, 0, 0); 3301 3302 KASSERT(mutex_owned(&sc->sc_lock)); 3303 3304 if (sc->sc_dying) { 3305 /* If we're dying, just do the software part. */ 3306 xfer->ux_status = status; 3307 callout_halt(&xfer->ux_callout, &sc->sc_lock); 3308 KASSERT(xfer->ux_status == status); 3309 usb_transfer_complete(xfer); 3310 return; 3311 } 3312 3313 if (xfer->ux_hcflags & UXFER_ABORTING) { 3314 DPRINTF("already aborting", 0, 0, 0, 0); 3315 3316 #ifdef DIAGNOSTIC 3317 if (status == USBD_TIMEOUT) 3318 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3319 #endif 3320 3321 xfer->ux_status = status; 3322 DPRINTF("waiting for abort to finish", 0, 0, 0, 0); 3323 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3324 while (xfer->ux_hcflags & UXFER_ABORTING) 3325 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3326 goto done; 3327 } 3328 xfer->ux_hcflags |= UXFER_ABORTING; 3329 3330 /* 3331 * Step 1: When cancelling a transfer make sure the timeout handler 3332 * didn't run or ran to the end and saw the USBD_CANCELLED status. 3333 * Otherwise we must have got here via a timeout. 3334 */ 3335 if (status == USBD_CANCELLED) { 3336 xfer->ux_status = status; 3337 callout_halt(&xfer->ux_callout, &sc->sc_lock); 3338 } else { 3339 KASSERT(xfer->ux_status == USBD_TIMEOUT); 3340 } 3341 3342 /* 3343 * Step 2: Make interrupt routine and hardware ignore xfer. 3344 */ 3345 ehci_del_intr_list(sc, exfer); 3346 3347 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3348 for (itd = exfer->ex_itdstart; itd != NULL; 3349 itd = itd->xfer_next) { 3350 usb_syncmem(&itd->dma, 3351 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3352 sizeof(itd->itd.itd_ctl), 3353 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3354 3355 for (i = 0; i < 8; i++) { 3356 trans_status = le32toh(itd->itd.itd_ctl[i]); 3357 trans_status &= ~EHCI_ITD_ACTIVE; 3358 itd->itd.itd_ctl[i] = htole32(trans_status); 3359 } 3360 3361 usb_syncmem(&itd->dma, 3362 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3363 sizeof(itd->itd.itd_ctl), 3364 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3365 } 3366 } else { 3367 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3368 sitd = sitd->xfer_next) { 3369 usb_syncmem(&sitd->dma, 3370 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3371 sizeof(sitd->sitd.sitd_buffer), 3372 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3373 3374 trans_status = le32toh(sitd->sitd.sitd_trans); 3375 trans_status &= ~EHCI_SITD_ACTIVE; 3376 sitd->sitd.sitd_trans = htole32(trans_status); 3377 3378 usb_syncmem(&sitd->dma, 3379 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3380 sizeof(sitd->sitd.sitd_buffer), 3381 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3382 } 3383 } 3384 3385 #ifdef DIAGNOSTIC 3386 exfer->ex_isdone = true; 3387 #endif 3388 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3389 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3390 usb_transfer_complete(xfer); 3391 if (wake) { 3392 cv_broadcast(&xfer->ux_hccv); 3393 } 3394 3395 done: 3396 KASSERT(mutex_owned(&sc->sc_lock)); 3397 return; 3398 } 3399 3400 Static void 3401 ehci_timeout(void *addr) 3402 { 3403 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3404 struct usbd_xfer *xfer = addr; 3405 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3406 bool timeout = false; 3407 3408 DPRINTF("xfer %p", xfer, 0, 0, 0); 3409 #ifdef EHCI_DEBUG 3410 if (ehcidebug >= 2) { 3411 struct usbd_pipe *pipe = xfer->ux_pipe; 3412 usbd_dump_pipe(pipe); 3413 } 3414 #endif 3415 3416 mutex_enter(&sc->sc_lock); 3417 if (sc->sc_dying) { 3418 mutex_exit(&sc->sc_lock); 3419 return; 3420 } 3421 if (xfer->ux_status != USBD_CANCELLED) { 3422 xfer->ux_status = USBD_TIMEOUT; 3423 timeout = true; 3424 } 3425 mutex_exit(&sc->sc_lock); 3426 3427 if (timeout) { 3428 struct usbd_device *dev = xfer->ux_pipe->up_dev; 3429 3430 /* Execute the abort in a process context. */ 3431 usb_init_task(&xfer->ux_aborttask, ehci_timeout_task, xfer, 3432 USB_TASKQ_MPSAFE); 3433 usb_add_task(dev, &xfer->ux_aborttask, USB_TASKQ_HC); 3434 } 3435 } 3436 3437 Static void 3438 ehci_timeout_task(void *addr) 3439 { 3440 struct usbd_xfer *xfer = addr; 3441 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3442 3443 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3444 3445 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3446 3447 mutex_enter(&sc->sc_lock); 3448 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3449 mutex_exit(&sc->sc_lock); 3450 } 3451 3452 /************************/ 3453 3454 Static int 3455 ehci_device_ctrl_init(struct usbd_xfer *xfer) 3456 { 3457 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3458 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3459 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3460 usb_device_request_t *req = &xfer->ux_request; 3461 ehci_soft_qtd_t *setup, *status, *next; 3462 int isread = req->bmRequestType & UT_READ; 3463 int len = xfer->ux_bufsize; 3464 int err; 3465 3466 exfer->ex_type = EX_CTRL; 3467 exfer->ex_status = NULL; 3468 exfer->ex_data = NULL; 3469 exfer->ex_setup = ehci_alloc_sqtd(sc); 3470 if (exfer->ex_setup == NULL) { 3471 err = ENOMEM; 3472 goto bad1; 3473 } 3474 exfer->ex_status = ehci_alloc_sqtd(sc); 3475 if (exfer->ex_status == NULL) { 3476 err = ENOMEM; 3477 goto bad2; 3478 } 3479 setup = exfer->ex_setup; 3480 status = exfer->ex_status; 3481 exfer->ex_nsqtd = 0; 3482 next = status; 3483 /* Set up data transaction */ 3484 if (len != 0) { 3485 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3486 &exfer->ex_data); 3487 if (err) 3488 goto bad3; 3489 next = exfer->ex_data; 3490 } 3491 3492 /* Clear toggle */ 3493 setup->qtd.qtd_status = htole32( 3494 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3495 EHCI_QTD_SET_TOGGLE(0) | 3496 EHCI_QTD_SET_BYTES(sizeof(*req)) 3497 ); 3498 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3499 setup->qtd.qtd_buffer_hi[0] = 0; 3500 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3501 setup->nextqtd = next; 3502 setup->xfer = xfer; 3503 setup->len = sizeof(*req); 3504 3505 status->qtd.qtd_status = htole32( 3506 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3507 EHCI_QTD_SET_TOGGLE(1) | 3508 EHCI_QTD_IOC 3509 ); 3510 status->qtd.qtd_buffer[0] = 0; 3511 status->qtd.qtd_buffer_hi[0] = 0; 3512 status->qtd.qtd_next = status->qtd.qtd_altnext = EHCI_NULL; 3513 status->nextqtd = NULL; 3514 status->xfer = xfer; 3515 status->len = 0; 3516 3517 return 0; 3518 bad3: 3519 ehci_free_sqtd(sc, exfer->ex_status); 3520 bad2: 3521 ehci_free_sqtd(sc, exfer->ex_setup); 3522 bad1: 3523 return err; 3524 } 3525 3526 Static void 3527 ehci_device_ctrl_fini(struct usbd_xfer *xfer) 3528 { 3529 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3530 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3531 3532 KASSERT(ex->ex_type == EX_CTRL); 3533 3534 ehci_free_sqtd(sc, ex->ex_setup); 3535 ehci_free_sqtd(sc, ex->ex_status); 3536 ehci_free_sqtds(sc, ex); 3537 if (ex->ex_nsqtd) 3538 kmem_free(ex->ex_sqtds, 3539 sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3540 } 3541 3542 Static usbd_status 3543 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3544 { 3545 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3546 usbd_status err; 3547 3548 /* Insert last in queue. */ 3549 mutex_enter(&sc->sc_lock); 3550 err = usb_insert_transfer(xfer); 3551 mutex_exit(&sc->sc_lock); 3552 if (err) 3553 return err; 3554 3555 /* Pipe isn't running, start first */ 3556 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3557 } 3558 3559 Static usbd_status 3560 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3561 { 3562 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3563 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3564 usb_device_request_t *req = &xfer->ux_request; 3565 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3566 ehci_soft_qtd_t *setup, *status, *next; 3567 ehci_soft_qh_t *sqh; 3568 3569 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3570 3571 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3572 3573 if (sc->sc_dying) 3574 return USBD_IOERROR; 3575 3576 const int isread = req->bmRequestType & UT_READ; 3577 const int len = UGETW(req->wLength); 3578 3579 DPRINTF("type=0x%02x, request=0x%02x, wValue=0x%04x, wIndex=0x%04x", 3580 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3581 UGETW(req->wIndex)); 3582 DPRINTF("len=%d, addr=%d, endpt=%d", len, epipe->pipe.up_dev->ud_addr, 3583 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3584 3585 sqh = epipe->sqh; 3586 3587 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == epipe->pipe.up_dev->ud_addr, 3588 "address QH %" __PRIuBIT " pipe %d\n", 3589 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), 3590 epipe->pipe.up_dev->ud_addr); 3591 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3592 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3593 "MPS QH %" __PRIuBIT " pipe %d\n", 3594 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3595 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3596 3597 setup = exfer->ex_setup; 3598 status = exfer->ex_status; 3599 3600 DPRINTF("setup %p status %p data %p", setup, status, exfer->ex_data, 0); 3601 KASSERTMSG(setup != NULL && status != NULL, 3602 "Failed memory allocation, setup %p status %p", 3603 setup, status); 3604 3605 memcpy(KERNADDR(&epipe->ctrl.reqdma, 0), req, sizeof(*req)); 3606 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3607 3608 /* Clear toggle */ 3609 setup->qtd.qtd_status &= ~htole32( 3610 EHCI_QTD_STATUS_MASK | 3611 EHCI_QTD_BYTES_MASK | 3612 EHCI_QTD_TOGGLE_MASK | 3613 EHCI_QTD_CERR_MASK 3614 ); 3615 setup->qtd.qtd_status |= htole32( 3616 EHCI_QTD_ACTIVE | 3617 EHCI_QTD_SET_CERR(3) | 3618 EHCI_QTD_SET_TOGGLE(0) | 3619 EHCI_QTD_SET_BYTES(sizeof(*req)) 3620 ); 3621 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->ctrl.reqdma, 0)); 3622 setup->qtd.qtd_buffer_hi[0] = 0; 3623 3624 next = status; 3625 status->qtd.qtd_status &= ~htole32( 3626 EHCI_QTD_STATUS_MASK | 3627 EHCI_QTD_PID_MASK | 3628 EHCI_QTD_BYTES_MASK | 3629 EHCI_QTD_TOGGLE_MASK | 3630 EHCI_QTD_CERR_MASK 3631 ); 3632 status->qtd.qtd_status |= htole32( 3633 EHCI_QTD_ACTIVE | 3634 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3635 EHCI_QTD_SET_CERR(3) | 3636 EHCI_QTD_SET_TOGGLE(1) | 3637 EHCI_QTD_SET_BYTES(0) | 3638 EHCI_QTD_IOC 3639 ); 3640 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3641 3642 KASSERT(exfer->ex_isdone); 3643 #ifdef DIAGNOSTIC 3644 exfer->ex_isdone = false; 3645 #endif 3646 3647 /* Set up data transaction */ 3648 if (len != 0) { 3649 ehci_soft_qtd_t *end; 3650 3651 /* Start toggle at 1. */ 3652 int toggle = 1; 3653 next = exfer->ex_data; 3654 KASSERTMSG(next != NULL, "Failed memory allocation"); 3655 ehci_reset_sqtd_chain(sc, xfer, len, isread, &toggle, &end); 3656 end->nextqtd = status; 3657 end->qtd.qtd_next = end->qtd.qtd_altnext = 3658 htole32(status->physaddr); 3659 3660 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3661 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3662 3663 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3664 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3665 } 3666 3667 setup->nextqtd = next; 3668 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3669 3670 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3671 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3672 3673 usb_syncmem(&status->dma, status->offs, sizeof(status->qtd), 3674 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3675 3676 KASSERT(status->qtd.qtd_status & htole32(EHCI_QTD_TOGGLE_MASK)); 3677 3678 #ifdef EHCI_DEBUG 3679 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3680 ehci_dump_sqh(sqh); 3681 ehci_dump_sqtds(setup); 3682 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3683 #endif 3684 3685 mutex_enter(&sc->sc_lock); 3686 3687 /* Insert qTD in QH list - also does usb_syncmem(sqh) */ 3688 ehci_set_qh_qtd(sqh, setup); 3689 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3690 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3691 ehci_timeout, xfer); 3692 } 3693 ehci_add_intr_list(sc, exfer); 3694 xfer->ux_status = USBD_IN_PROGRESS; 3695 mutex_exit(&sc->sc_lock); 3696 3697 #if 0 3698 #ifdef EHCI_DEBUG 3699 DPRINTFN(10, "status=%x, dump:", EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3700 // delay(10000); 3701 ehci_dump_regs(sc); 3702 ehci_dump_sqh(sc->sc_async_head); 3703 ehci_dump_sqh(sqh); 3704 ehci_dump_sqtds(setup); 3705 #endif 3706 #endif 3707 3708 return USBD_IN_PROGRESS; 3709 } 3710 3711 Static void 3712 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3713 { 3714 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3715 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3716 usb_device_request_t *req = &xfer->ux_request; 3717 int len = UGETW(req->wLength); 3718 int rd = req->bmRequestType & UT_READ; 3719 3720 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3721 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3722 3723 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3724 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3725 3726 usb_syncmem(&epipe->ctrl.reqdma, 0, sizeof(*req), 3727 BUS_DMASYNC_POSTWRITE); 3728 if (len) 3729 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3730 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3731 3732 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3733 } 3734 3735 /* Abort a device control request. */ 3736 Static void 3737 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3738 { 3739 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3740 3741 DPRINTF("xfer=%p", xfer, 0, 0, 0); 3742 ehci_abort_xfer(xfer, USBD_CANCELLED); 3743 } 3744 3745 /* Close a device control pipe. */ 3746 Static void 3747 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3748 { 3749 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3750 /*struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe);*/ 3751 3752 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3753 3754 KASSERT(mutex_owned(&sc->sc_lock)); 3755 3756 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3757 3758 ehci_close_pipe(pipe, sc->sc_async_head); 3759 } 3760 3761 /* 3762 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3763 * qTD status, or miss signalling occasionally under heavy load. If the host 3764 * machine is too fast, we we can miss transaction completion - when we scan 3765 * the active list the transaction still seems to be active. This generally 3766 * exhibits itself as a umass stall that never recovers. 3767 * 3768 * We work around this behaviour by setting up this callback after any softintr 3769 * that completes with transactions still pending, giving us another chance to 3770 * check for completion after the writeback has taken place. 3771 */ 3772 Static void 3773 ehci_intrlist_timeout(void *arg) 3774 { 3775 ehci_softc_t *sc = arg; 3776 3777 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3778 3779 usb_schedsoftintr(&sc->sc_bus); 3780 } 3781 3782 /************************/ 3783 3784 Static int 3785 ehci_device_bulk_init(struct usbd_xfer *xfer) 3786 { 3787 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3788 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3789 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3790 int endpt = ed->bEndpointAddress; 3791 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3792 int len = xfer->ux_bufsize; 3793 int err = 0; 3794 3795 exfer->ex_type = EX_BULK; 3796 exfer->ex_nsqtd = 0; 3797 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 3798 &exfer->ex_sqtdstart); 3799 3800 return err; 3801 } 3802 3803 Static void 3804 ehci_device_bulk_fini(struct usbd_xfer *xfer) 3805 { 3806 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3807 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 3808 3809 KASSERT(ex->ex_type == EX_BULK); 3810 3811 ehci_free_sqtds(sc, ex); 3812 if (ex->ex_nsqtd) 3813 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 3814 } 3815 3816 Static usbd_status 3817 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3818 { 3819 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3820 usbd_status err; 3821 3822 /* Insert last in queue. */ 3823 mutex_enter(&sc->sc_lock); 3824 err = usb_insert_transfer(xfer); 3825 mutex_exit(&sc->sc_lock); 3826 if (err) 3827 return err; 3828 3829 /* Pipe isn't running, start first */ 3830 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3831 } 3832 3833 Static usbd_status 3834 ehci_device_bulk_start(struct usbd_xfer *xfer) 3835 { 3836 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3837 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3838 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3839 ehci_soft_qh_t *sqh; 3840 ehci_soft_qtd_t *end; 3841 int len, isread, endpt; 3842 3843 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3844 3845 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 3846 xfer->ux_flags, 0); 3847 3848 if (sc->sc_dying) 3849 return USBD_IOERROR; 3850 3851 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3852 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 3853 3854 len = xfer->ux_length; 3855 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3856 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3857 sqh = epipe->sqh; 3858 3859 KASSERT(exfer->ex_isdone); 3860 #ifdef DIAGNOSTIC 3861 exfer->ex_isdone = false; 3862 #endif 3863 3864 /* Take lock here to protect nexttoggle */ 3865 mutex_enter(&sc->sc_lock); 3866 3867 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 3868 3869 exfer->ex_sqtdend = end; 3870 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 3871 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3872 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3873 3874 #ifdef EHCI_DEBUG 3875 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 3876 ehci_dump_sqh(sqh); 3877 ehci_dump_sqtds(exfer->ex_sqtdstart); 3878 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 3879 #endif 3880 3881 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3882 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 3883 3884 /* also does usb_syncmem(sqh) */ 3885 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 3886 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3887 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3888 ehci_timeout, xfer); 3889 } 3890 ehci_add_intr_list(sc, exfer); 3891 xfer->ux_status = USBD_IN_PROGRESS; 3892 mutex_exit(&sc->sc_lock); 3893 3894 #if 0 3895 #ifdef EHCI_DEBUG 3896 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 3897 // delay(10000); 3898 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 3899 ehci_dump_regs(sc); 3900 #if 0 3901 printf("async_head:\n"); 3902 ehci_dump_sqh(sc->sc_async_head); 3903 #endif 3904 DPRINTF("sqh:", 0, 0, 0, 0); 3905 ehci_dump_sqh(sqh); 3906 ehci_dump_sqtds(exfer->ex_sqtdstart); 3907 #endif 3908 #endif 3909 3910 return USBD_IN_PROGRESS; 3911 } 3912 3913 Static void 3914 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3915 { 3916 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3917 3918 DPRINTF("xfer %p", xfer, 0, 0, 0); 3919 ehci_abort_xfer(xfer, USBD_CANCELLED); 3920 } 3921 3922 /* 3923 * Close a device bulk pipe. 3924 */ 3925 Static void 3926 ehci_device_bulk_close(struct usbd_pipe *pipe) 3927 { 3928 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 3929 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 3930 3931 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3932 3933 KASSERT(mutex_owned(&sc->sc_lock)); 3934 3935 DPRINTF("pipe=%p", pipe, 0, 0, 0); 3936 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3937 ehci_close_pipe(pipe, sc->sc_async_head); 3938 } 3939 3940 Static void 3941 ehci_device_bulk_done(struct usbd_xfer *xfer) 3942 { 3943 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 3944 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 3945 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3946 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3947 3948 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 3949 3950 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 0, 0); 3951 3952 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3953 3954 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3955 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3956 3957 DPRINTF("length=%d", xfer->ux_actlen, 0, 0, 0); 3958 } 3959 3960 /************************/ 3961 3962 Static usbd_status 3963 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3964 { 3965 struct ehci_soft_islot *isp; 3966 int islot, lev; 3967 3968 /* Find a poll rate that is large enough. */ 3969 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3970 if (EHCI_ILEV_IVAL(lev) <= ival) 3971 break; 3972 3973 /* Pick an interrupt slot at the right level. */ 3974 /* XXX could do better than picking at random */ 3975 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3976 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3977 3978 sqh->islot = islot; 3979 isp = &sc->sc_islots[islot]; 3980 mutex_enter(&sc->sc_lock); 3981 ehci_add_qh(sc, sqh, isp->sqh); 3982 mutex_exit(&sc->sc_lock); 3983 3984 return USBD_NORMAL_COMPLETION; 3985 } 3986 3987 3988 Static int 3989 ehci_device_intr_init(struct usbd_xfer *xfer) 3990 { 3991 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 3992 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 3993 usb_endpoint_descriptor_t *ed = xfer->ux_pipe->up_endpoint->ue_edesc; 3994 int endpt = ed->bEndpointAddress; 3995 int isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3996 int len = xfer->ux_bufsize; 3997 int err; 3998 3999 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4000 4001 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4002 xfer->ux_flags, 0); 4003 4004 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4005 KASSERT(len != 0); 4006 4007 exfer->ex_type = EX_INTR; 4008 exfer->ex_nsqtd = 0; 4009 err = ehci_alloc_sqtd_chain(sc, xfer, len, isread, 4010 &exfer->ex_sqtdstart); 4011 4012 return err; 4013 } 4014 4015 Static void 4016 ehci_device_intr_fini(struct usbd_xfer *xfer) 4017 { 4018 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4019 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4020 4021 KASSERT(ex->ex_type == EX_INTR); 4022 4023 ehci_free_sqtds(sc, ex); 4024 if (ex->ex_nsqtd) 4025 kmem_free(ex->ex_sqtds, sizeof(ehci_soft_qtd_t *) * ex->ex_nsqtd); 4026 } 4027 4028 Static usbd_status 4029 ehci_device_intr_transfer(struct usbd_xfer *xfer) 4030 { 4031 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4032 usbd_status err; 4033 4034 /* Insert last in queue. */ 4035 mutex_enter(&sc->sc_lock); 4036 err = usb_insert_transfer(xfer); 4037 mutex_exit(&sc->sc_lock); 4038 if (err) 4039 return err; 4040 4041 /* 4042 * Pipe isn't running (otherwise err would be USBD_INPROG), 4043 * so start it first. 4044 */ 4045 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 4046 } 4047 4048 Static usbd_status 4049 ehci_device_intr_start(struct usbd_xfer *xfer) 4050 { 4051 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4052 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4053 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4054 ehci_soft_qtd_t *end; 4055 ehci_soft_qh_t *sqh; 4056 int len, isread, endpt; 4057 4058 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4059 4060 DPRINTF("xfer=%p len=%d flags=%d", xfer, xfer->ux_length, 4061 xfer->ux_flags, 0); 4062 4063 if (sc->sc_dying) 4064 return USBD_IOERROR; 4065 4066 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4067 KASSERT(xfer->ux_length <= xfer->ux_bufsize); 4068 4069 len = xfer->ux_length; 4070 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4071 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4072 sqh = epipe->sqh; 4073 4074 KASSERT(exfer->ex_isdone); 4075 #ifdef DIAGNOSTIC 4076 exfer->ex_isdone = false; 4077 #endif 4078 4079 /* Take lock to protect nexttoggle */ 4080 mutex_enter(&sc->sc_lock); 4081 4082 ehci_reset_sqtd_chain(sc, xfer, len, isread, &epipe->nexttoggle, &end); 4083 4084 end->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 4085 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 4086 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4087 exfer->ex_sqtdend = end; 4088 4089 #ifdef EHCI_DEBUG 4090 DPRINTFN(5, "--- dump start ---", 0, 0, 0, 0); 4091 ehci_dump_sqh(sqh); 4092 ehci_dump_sqtds(exfer->ex_sqtdstart); 4093 DPRINTFN(5, "--- dump end ---", 0, 0, 0, 0); 4094 #endif 4095 4096 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4097 isread ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 4098 4099 /* also does usb_syncmem(sqh) */ 4100 ehci_set_qh_qtd(sqh, exfer->ex_sqtdstart); 4101 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4102 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 4103 ehci_timeout, xfer); 4104 } 4105 ehci_add_intr_list(sc, exfer); 4106 xfer->ux_status = USBD_IN_PROGRESS; 4107 mutex_exit(&sc->sc_lock); 4108 4109 #if 0 4110 #ifdef EHCI_DEBUG 4111 DPRINTFN(5, "data(2)", 0, 0, 0, 0); 4112 // delay(10000); 4113 DPRINTFN(5, "data(3)", 0, 0, 0, 0); 4114 ehci_dump_regs(sc); 4115 DPRINTFN(5, "sqh:", 0, 0, 0, 0); 4116 ehci_dump_sqh(sqh); 4117 ehci_dump_sqtds(exfer->ex_sqtdstart); 4118 #endif 4119 #endif 4120 4121 return USBD_IN_PROGRESS; 4122 } 4123 4124 Static void 4125 ehci_device_intr_abort(struct usbd_xfer *xfer) 4126 { 4127 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4128 4129 DPRINTF("xfer=%p", xfer, 0, 0, 0); 4130 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 4131 4132 /* 4133 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 4134 * async doorbell. That's dependent on the async list, wheras 4135 * intr xfers are periodic, should not use this? 4136 */ 4137 ehci_abort_xfer(xfer, USBD_CANCELLED); 4138 } 4139 4140 Static void 4141 ehci_device_intr_close(struct usbd_pipe *pipe) 4142 { 4143 ehci_softc_t *sc = EHCI_PIPE2SC(pipe); 4144 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(pipe); 4145 struct ehci_soft_islot *isp; 4146 4147 KASSERT(mutex_owned(&sc->sc_lock)); 4148 4149 isp = &sc->sc_islots[epipe->sqh->islot]; 4150 ehci_close_pipe(pipe, isp->sqh); 4151 } 4152 4153 Static void 4154 ehci_device_intr_done(struct usbd_xfer *xfer) 4155 { 4156 ehci_softc_t *sc __diagused = EHCI_XFER2SC(xfer); 4157 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4158 int isread, endpt; 4159 4160 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4161 4162 DPRINTF("xfer=%p, actlen=%d", xfer, xfer->ux_actlen, 4163 0, 0); 4164 4165 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4166 4167 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4168 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4169 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4170 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4171 } 4172 4173 /************************/ 4174 Static int 4175 ehci_device_fs_isoc_init(struct usbd_xfer *xfer) 4176 { 4177 struct ehci_pipe *epipe = EHCI_PIPE2EPIPE(xfer->ux_pipe); 4178 struct usbd_device *dev = xfer->ux_pipe->up_dev; 4179 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4180 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4181 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4182 int i, k, frames; 4183 u_int huba, dir; 4184 int err; 4185 4186 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4187 4188 start = NULL; 4189 sitd = NULL; 4190 4191 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4192 xfer->ux_flags, 0); 4193 4194 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4195 KASSERT(xfer->ux_nframes != 0); 4196 KASSERT(exfer->ex_isdone); 4197 4198 exfer->ex_type = EX_FS_ISOC; 4199 /* 4200 * Step 1: Allocate and initialize sitds. 4201 */ 4202 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4203 if (i > 16 || i == 0) { 4204 /* Spec page 271 says intervals > 16 are invalid */ 4205 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4206 4207 return EINVAL; 4208 } 4209 4210 frames = xfer->ux_nframes; 4211 for (i = 0, prev = NULL; i < frames; i++, prev = sitd) { 4212 sitd = ehci_alloc_sitd(sc); 4213 if (sitd == NULL) { 4214 err = ENOMEM; 4215 goto fail; 4216 } 4217 4218 if (prev) 4219 prev->xfer_next = sitd; 4220 else 4221 start = sitd; 4222 4223 huba = dev->ud_myhsport->up_parent->ud_addr; 4224 4225 #if 0 4226 if (sc->sc_flags & EHCIF_FREESCALE) { 4227 // Set hub address to 0 if embedded TT is used. 4228 if (huba == sc->sc_addr) 4229 huba = 0; 4230 } 4231 #endif 4232 4233 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4234 dir = UE_GET_DIR(k) ? 1 : 0; 4235 sitd->sitd.sitd_endp = 4236 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4237 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4238 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4239 EHCI_SITD_SET_HUBA(huba) | 4240 EHCI_SITD_SET_DIR(dir)); 4241 4242 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4243 } /* End of frame */ 4244 4245 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4246 4247 stop = sitd; 4248 stop->xfer_next = NULL; 4249 exfer->ex_sitdstart = start; 4250 exfer->ex_sitdend = stop; 4251 4252 return 0; 4253 4254 fail: 4255 mutex_enter(&sc->sc_lock); 4256 ehci_soft_sitd_t *next; 4257 for (sitd = start; sitd; sitd = next) { 4258 next = sitd->xfer_next; 4259 ehci_free_sitd_locked(sc, sitd); 4260 } 4261 mutex_exit(&sc->sc_lock); 4262 4263 return err; 4264 } 4265 4266 Static void 4267 ehci_device_fs_isoc_fini(struct usbd_xfer *xfer) 4268 { 4269 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4270 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4271 4272 KASSERT(ex->ex_type == EX_FS_ISOC); 4273 4274 ehci_free_sitd_chain(sc, ex->ex_sitdstart); 4275 } 4276 4277 Static usbd_status 4278 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4279 { 4280 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4281 usbd_status __diagused err; 4282 4283 mutex_enter(&sc->sc_lock); 4284 err = usb_insert_transfer(xfer); 4285 mutex_exit(&sc->sc_lock); 4286 4287 KASSERT(err == USBD_NORMAL_COMPLETION); 4288 4289 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer);; 4290 struct usbd_device *dev = xfer->ux_pipe->up_dev;; 4291 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4292 ehci_soft_sitd_t *sitd; 4293 usb_dma_t *dma_buf; 4294 int i, j, k, frames; 4295 int offs, total_length; 4296 int frindex; 4297 u_int dir; 4298 4299 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4300 4301 sitd = NULL; 4302 total_length = 0; 4303 4304 4305 DPRINTF("xfer %p len %d flags %d", xfer, xfer->ux_length, 4306 xfer->ux_flags, 0); 4307 4308 if (sc->sc_dying) 4309 return USBD_IOERROR; 4310 4311 /* 4312 * To avoid complication, don't allow a request right now that'll span 4313 * the entire frame table. To within 4 frames, to allow some leeway 4314 * on either side of where the hc currently is. 4315 */ 4316 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4317 xfer->ux_nframes >= sc->sc_flsize - 4) { 4318 printf("ehci: isoc descriptor requested that spans the entire" 4319 "frametable, too many frames\n"); 4320 return USBD_INVAL; 4321 } 4322 4323 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4324 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4325 KASSERT(exfer->ex_isdone); 4326 #ifdef DIAGNOSTIC 4327 exfer->ex_isdone = false; 4328 #endif 4329 4330 /* 4331 * Step 1: Initialize sitds. 4332 */ 4333 4334 frames = xfer->ux_nframes; 4335 dma_buf = &xfer->ux_dmabuf; 4336 offs = 0; 4337 4338 for (sitd = exfer->ex_sitdstart, i = 0; i < frames; 4339 i++, sitd = sitd->xfer_next) { 4340 KASSERT(sitd != NULL); 4341 KASSERT(xfer->ux_frlengths[i] <= 0x3ff); 4342 4343 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4344 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4345 4346 /* Set page0 index and offset - TP and T-offset are set below */ 4347 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4348 4349 total_length += xfer->ux_frlengths[i]; 4350 offs += xfer->ux_frlengths[i]; 4351 4352 sitd->sitd.sitd_buffer[1] = 4353 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4354 4355 u_int huba __diagused = dev->ud_myhsport->up_parent->ud_addr; 4356 4357 #if 0 4358 if (sc->sc_flags & EHCIF_FREESCALE) { 4359 // Set hub address to 0 if embedded TT is used. 4360 if (huba == sc->sc_addr) 4361 huba = 0; 4362 } 4363 #endif 4364 4365 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4366 dir = UE_GET_DIR(k) ? 1 : 0; 4367 KASSERT(sitd->sitd.sitd_endp == htole32( 4368 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4369 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4370 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4371 EHCI_SITD_SET_HUBA(huba) | 4372 EHCI_SITD_SET_DIR(dir))); 4373 KASSERT(sitd->sitd.sitd_back == htole32(EHCI_LINK_TERMINATE)); 4374 4375 uint8_t sa = 0; 4376 uint8_t sb = 0; 4377 u_int temp, tlen; 4378 4379 if (dir == 0) { /* OUT */ 4380 temp = 0; 4381 tlen = xfer->ux_frlengths[i]; 4382 if (tlen <= 188) { 4383 temp |= 1; /* T-count = 1, TP = ALL */ 4384 tlen = 1; 4385 } else { 4386 tlen += 187; 4387 tlen /= 188; 4388 temp |= tlen; /* T-count = [1..6] */ 4389 temp |= 8; /* TP = Begin */ 4390 } 4391 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4392 4393 tlen += sa; 4394 4395 if (tlen >= 8) { 4396 sb = 0; 4397 } else { 4398 sb = (1 << tlen); 4399 } 4400 4401 sa = (1 << sa); 4402 sa = (sb - sa) & 0x3F; 4403 sb = 0; 4404 } else { 4405 sb = (-(4 << sa)) & 0xFE; 4406 sa = (1 << sa) & 0x3F; 4407 sa = 0x01; 4408 sb = 0xfc; 4409 } 4410 4411 sitd->sitd.sitd_sched = htole32( 4412 EHCI_SITD_SET_SMASK(sa) | 4413 EHCI_SITD_SET_CMASK(sb) 4414 ); 4415 4416 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4417 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4418 } /* End of frame */ 4419 4420 sitd = exfer->ex_sitdend; 4421 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4422 4423 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4424 sizeof(sitd->sitd.sitd_trans), 4425 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4426 4427 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4428 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4429 4430 /* 4431 * Part 2: Transfer descriptors have now been set up, now they must 4432 * be scheduled into the periodic frame list. Erk. Not wanting to 4433 * complicate matters, transfer is denied if the transfer spans 4434 * more than the period frame list. 4435 */ 4436 4437 mutex_enter(&sc->sc_lock); 4438 4439 /* Start inserting frames */ 4440 if (epipe->isoc.cur_xfers > 0) { 4441 frindex = epipe->isoc.next_frame; 4442 } else { 4443 frindex = EOREAD4(sc, EHCI_FRINDEX); 4444 frindex = frindex >> 3; /* Erase microframe index */ 4445 frindex += 2; 4446 } 4447 4448 if (frindex >= sc->sc_flsize) 4449 frindex &= (sc->sc_flsize - 1); 4450 4451 /* Whats the frame interval? */ 4452 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4453 4454 for (sitd = exfer->ex_sitdstart, j = 0; j < frames; 4455 j++, sitd = sitd->xfer_next) { 4456 KASSERT(sitd); 4457 4458 usb_syncmem(&sc->sc_fldma, 4459 sizeof(ehci_link_t) * frindex, 4460 sizeof(ehci_link_t), 4461 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4462 4463 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4464 if (sitd->sitd.sitd_next == 0) 4465 /* 4466 * FIXME: frindex table gets initialized to NULL 4467 * or EHCI_NULL? 4468 */ 4469 sitd->sitd.sitd_next = EHCI_NULL; 4470 4471 usb_syncmem(&sitd->dma, 4472 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4473 sizeof(ehci_sitd_t), 4474 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4475 4476 sc->sc_flist[frindex] = 4477 htole32(EHCI_LINK_SITD | sitd->physaddr); 4478 4479 usb_syncmem(&sc->sc_fldma, 4480 sizeof(ehci_link_t) * frindex, 4481 sizeof(ehci_link_t), 4482 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4483 4484 sitd->frame_list.next = sc->sc_softsitds[frindex]; 4485 sc->sc_softsitds[frindex] = sitd; 4486 if (sitd->frame_list.next != NULL) 4487 sitd->frame_list.next->frame_list.prev = sitd; 4488 sitd->slot = frindex; 4489 sitd->frame_list.prev = NULL; 4490 4491 frindex += i; 4492 if (frindex >= sc->sc_flsize) 4493 frindex -= sc->sc_flsize; 4494 } 4495 4496 epipe->isoc.cur_xfers++; 4497 epipe->isoc.next_frame = frindex; 4498 4499 ehci_add_intr_list(sc, exfer); 4500 xfer->ux_status = USBD_IN_PROGRESS; 4501 mutex_exit(&sc->sc_lock); 4502 4503 return USBD_IN_PROGRESS; 4504 } 4505 4506 Static void 4507 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4508 { 4509 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4510 4511 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4512 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4513 } 4514 4515 Static void 4516 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4517 { 4518 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4519 4520 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4521 } 4522 4523 Static void 4524 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4525 { 4526 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4527 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4528 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4529 4530 KASSERT(mutex_owned(&sc->sc_lock)); 4531 4532 epipe->isoc.cur_xfers--; 4533 ehci_remove_sitd_chain(sc, exfer->ex_itdstart); 4534 4535 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4536 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4537 } 4538 4539 4540 /************************/ 4541 4542 4543 Static int 4544 ehci_device_isoc_init(struct usbd_xfer *xfer) 4545 { 4546 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4547 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4548 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4549 ehci_soft_itd_t *itd, *prev, *start, *stop; 4550 int i, j, k; 4551 int frames, ufrperframe; 4552 int err; 4553 4554 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4555 4556 start = NULL; 4557 prev = NULL; 4558 itd = NULL; 4559 4560 KASSERT(xfer->ux_nframes != 0); 4561 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4562 KASSERT(exfer->ex_isdone); 4563 4564 exfer->ex_type = EX_ISOC; 4565 4566 /* 4567 * Step 1: Allocate and initialize itds, how many do we need? 4568 * One per transfer if interval >= 8 microframes, less if we use 4569 * multiple microframes per frame. 4570 */ 4571 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4572 if (i > 16 || i == 0) { 4573 /* Spec page 271 says intervals > 16 are invalid */ 4574 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4575 return USBD_INVAL; 4576 } 4577 4578 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4579 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4580 4581 for (i = 0, prev = NULL; i < frames; i++, prev = itd) { 4582 itd = ehci_alloc_itd(sc); 4583 if (itd == NULL) { 4584 err = ENOMEM; 4585 goto fail; 4586 } 4587 4588 if (prev != NULL) { 4589 /* Maybe not as it's updated by the scheduling? */ 4590 prev->itd.itd_next = 4591 htole32(itd->physaddr | EHCI_LINK_ITD); 4592 4593 prev->xfer_next = itd; 4594 } else { 4595 start = itd; 4596 } 4597 4598 /* 4599 * Other special values 4600 */ 4601 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4602 itd->itd.itd_bufr[0] = htole32( 4603 EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4604 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4605 4606 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4607 ? 1 : 0; 4608 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4609 itd->itd.itd_bufr[1] |= htole32( 4610 EHCI_ITD_SET_DIR(k) | 4611 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4612 4613 /* FIXME: handle invalid trans - should be done in openpipe */ 4614 itd->itd.itd_bufr[2] |= 4615 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4616 } /* End of frame */ 4617 4618 stop = itd; 4619 stop->xfer_next = NULL; 4620 4621 exfer->ex_itdstart = start; 4622 exfer->ex_itdend = stop; 4623 4624 return 0; 4625 fail: 4626 mutex_enter(&sc->sc_lock); 4627 ehci_soft_itd_t *next; 4628 for (itd = start; itd; itd = next) { 4629 next = itd->xfer_next; 4630 ehci_free_itd_locked(sc, itd); 4631 } 4632 mutex_exit(&sc->sc_lock); 4633 4634 return err; 4635 4636 } 4637 4638 Static void 4639 ehci_device_isoc_fini(struct usbd_xfer *xfer) 4640 { 4641 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4642 struct ehci_xfer *ex = EHCI_XFER2EXFER(xfer); 4643 4644 KASSERT(ex->ex_type == EX_ISOC); 4645 4646 ehci_free_itd_chain(sc, ex->ex_itdstart); 4647 } 4648 4649 Static usbd_status 4650 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4651 { 4652 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4653 usbd_status __diagused err; 4654 4655 mutex_enter(&sc->sc_lock); 4656 err = usb_insert_transfer(xfer); 4657 mutex_exit(&sc->sc_lock); 4658 4659 KASSERT(err == USBD_NORMAL_COMPLETION); 4660 4661 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4662 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4663 ehci_soft_itd_t *itd, *prev; 4664 usb_dma_t *dma_buf; 4665 int i, j; 4666 int frames, uframes, ufrperframe; 4667 int trans_count, offs, total_length; 4668 int frindex; 4669 4670 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4671 4672 prev = NULL; 4673 itd = NULL; 4674 trans_count = 0; 4675 total_length = 0; 4676 4677 DPRINTF("xfer %p flags %d", xfer, xfer->ux_flags, 0, 0); 4678 4679 if (sc->sc_dying) 4680 return USBD_IOERROR; 4681 4682 /* 4683 * To avoid complication, don't allow a request right now that'll span 4684 * the entire frame table. To within 4 frames, to allow some leeway 4685 * on either side of where the hc currently is. 4686 */ 4687 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4688 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4689 DPRINTF( 4690 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4691 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4692 return USBD_INVAL; 4693 } 4694 4695 KASSERT(xfer->ux_nframes != 0 && xfer->ux_frlengths); 4696 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4697 KASSERT(exfer->ex_isdone); 4698 #ifdef DIAGNOSTIC 4699 exfer->ex_isdone = false; 4700 #endif 4701 4702 /* 4703 * Step 1: Re-Initialize itds 4704 */ 4705 4706 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4707 if (i > 16 || i == 0) { 4708 /* Spec page 271 says intervals > 16 are invalid */ 4709 DPRINTF("bInterval %d invalid", i, 0, 0, 0); 4710 return USBD_INVAL; 4711 } 4712 4713 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4714 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4715 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4716 4717 if (frames == 0) { 4718 DPRINTF("frames == 0", 0, 0, 0, 0); 4719 return USBD_INVAL; 4720 } 4721 4722 dma_buf = &xfer->ux_dmabuf; 4723 offs = 0; 4724 4725 itd = exfer->ex_itdstart; 4726 for (i = 0; i < frames; i++, itd = itd->xfer_next) { 4727 int froffs = offs; 4728 4729 if (prev != NULL) { 4730 prev->itd.itd_next = 4731 htole32(itd->physaddr | EHCI_LINK_ITD); 4732 usb_syncmem(&prev->dma, 4733 prev->offs + offsetof(ehci_itd_t, itd_next), 4734 sizeof(prev->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4735 prev->xfer_next = itd; 4736 } 4737 4738 /* 4739 * Step 1.5, initialize uframes 4740 */ 4741 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4742 /* Calculate which page in the list this starts in */ 4743 int addr = DMAADDR(dma_buf, froffs); 4744 addr = EHCI_PAGE_OFFSET(addr); 4745 addr += (offs - froffs); 4746 addr = EHCI_PAGE(addr); 4747 addr /= EHCI_PAGE_SIZE; 4748 4749 /* 4750 * This gets the initial offset into the first page, 4751 * looks how far further along the current uframe 4752 * offset is. Works out how many pages that is. 4753 */ 4754 4755 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4756 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4757 EHCI_ITD_SET_PG(addr) | 4758 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4759 4760 total_length += xfer->ux_frlengths[trans_count]; 4761 offs += xfer->ux_frlengths[trans_count]; 4762 trans_count++; 4763 4764 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4765 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4766 break; 4767 } 4768 } 4769 4770 /* 4771 * Step 1.75, set buffer pointers. To simplify matters, all 4772 * pointers are filled out for the next 7 hardware pages in 4773 * the dma block, so no need to worry what pages to cover 4774 * and what to not. 4775 */ 4776 4777 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4778 /* 4779 * Don't try to lookup a page that's past the end 4780 * of buffer 4781 */ 4782 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4783 if (page_offs >= dma_buf->udma_block->size) 4784 break; 4785 4786 uint64_t page = DMAADDR(dma_buf, page_offs); 4787 page = EHCI_PAGE(page); 4788 itd->itd.itd_bufr[j] = htole32(EHCI_ITD_SET_BPTR(page)); 4789 itd->itd.itd_bufr_hi[j] = htole32(page >> 32); 4790 } 4791 /* 4792 * Other special values 4793 */ 4794 4795 int k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4796 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4797 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4798 4799 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4800 ? 1 : 0; 4801 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4802 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4803 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4804 4805 /* FIXME: handle invalid trans */ 4806 itd->itd.itd_bufr[2] |= 4807 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4808 4809 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4810 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4811 4812 prev = itd; 4813 } /* End of frame */ 4814 4815 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4816 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4817 4818 /* 4819 * Part 2: Transfer descriptors have now been set up, now they must 4820 * be scheduled into the period frame list. Erk. Not wanting to 4821 * complicate matters, transfer is denied if the transfer spans 4822 * more than the period frame list. 4823 */ 4824 4825 mutex_enter(&sc->sc_lock); 4826 4827 /* Start inserting frames */ 4828 if (epipe->isoc.cur_xfers > 0) { 4829 frindex = epipe->isoc.next_frame; 4830 } else { 4831 frindex = EOREAD4(sc, EHCI_FRINDEX); 4832 frindex = frindex >> 3; /* Erase microframe index */ 4833 frindex += 2; 4834 } 4835 4836 if (frindex >= sc->sc_flsize) 4837 frindex &= (sc->sc_flsize - 1); 4838 4839 /* What's the frame interval? */ 4840 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4841 if (i / USB_UFRAMES_PER_FRAME == 0) 4842 i = 1; 4843 else 4844 i /= USB_UFRAMES_PER_FRAME; 4845 4846 itd = exfer->ex_itdstart; 4847 for (j = 0; j < frames; j++) { 4848 KASSERTMSG(itd != NULL, "frame %d\n", j); 4849 4850 usb_syncmem(&sc->sc_fldma, 4851 sizeof(ehci_link_t) * frindex, 4852 sizeof(ehci_link_t), 4853 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4854 4855 itd->itd.itd_next = sc->sc_flist[frindex]; 4856 if (itd->itd.itd_next == 0) 4857 /* 4858 * FIXME: frindex table gets initialized to NULL 4859 * or EHCI_NULL? 4860 */ 4861 itd->itd.itd_next = EHCI_NULL; 4862 4863 usb_syncmem(&itd->dma, 4864 itd->offs + offsetof(ehci_itd_t, itd_next), 4865 sizeof(itd->itd.itd_next), 4866 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4867 4868 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4869 4870 usb_syncmem(&sc->sc_fldma, 4871 sizeof(ehci_link_t) * frindex, 4872 sizeof(ehci_link_t), 4873 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4874 4875 itd->frame_list.next = sc->sc_softitds[frindex]; 4876 sc->sc_softitds[frindex] = itd; 4877 if (itd->frame_list.next != NULL) 4878 itd->frame_list.next->frame_list.prev = itd; 4879 itd->slot = frindex; 4880 itd->frame_list.prev = NULL; 4881 4882 frindex += i; 4883 if (frindex >= sc->sc_flsize) 4884 frindex -= sc->sc_flsize; 4885 4886 itd = itd->xfer_next; 4887 } 4888 4889 epipe->isoc.cur_xfers++; 4890 epipe->isoc.next_frame = frindex; 4891 4892 ehci_add_intr_list(sc, exfer); 4893 xfer->ux_status = USBD_IN_PROGRESS; 4894 mutex_exit(&sc->sc_lock); 4895 4896 return USBD_IN_PROGRESS; 4897 } 4898 4899 Static void 4900 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4901 { 4902 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4903 4904 DPRINTF("xfer = %p", xfer, 0, 0, 0); 4905 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4906 } 4907 4908 Static void 4909 ehci_device_isoc_close(struct usbd_pipe *pipe) 4910 { 4911 EHCIHIST_FUNC(); EHCIHIST_CALLED(); 4912 4913 DPRINTF("nothing in the pipe to free?", 0, 0, 0, 0); 4914 } 4915 4916 Static void 4917 ehci_device_isoc_done(struct usbd_xfer *xfer) 4918 { 4919 struct ehci_xfer *exfer = EHCI_XFER2EXFER(xfer); 4920 ehci_softc_t *sc = EHCI_XFER2SC(xfer); 4921 struct ehci_pipe *epipe = EHCI_XFER2EPIPE(xfer); 4922 4923 KASSERT(mutex_owned(&sc->sc_lock)); 4924 4925 epipe->isoc.cur_xfers--; 4926 ehci_remove_itd_chain(sc, exfer->ex_sitdstart); 4927 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4928 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4929 } 4930
Indexes created Thu Oct 02 01:09:59 GMT 2025