ehci.c revision 1.234.2.14
1 /* $NetBSD: ehci.c,v 1.234.2.14 2014/12/05 09:37:49 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.14 2014/12/05 09:37:49 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 85 #include <dev/usb/ehcireg.h> 86 #include <dev/usb/ehcivar.h> 87 #include <dev/usb/usbroothub.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 /* ehci_soft_sitd_t *sitd; */ 135 } tail; 136 union { 137 /* Control pipe */ 138 struct { 139 usb_dma_t reqdma; 140 } ctl; 141 /* Interrupt pipe */ 142 struct { 143 u_int length; 144 } intr; 145 /* Bulk pipe */ 146 struct { 147 u_int length; 148 } bulk; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 } u; 155 }; 156 157 Static usbd_status ehci_open(usbd_pipe_handle); 158 Static void ehci_poll(struct usbd_bus *); 159 Static void ehci_softintr(void *); 160 Static int ehci_intr1(ehci_softc_t *); 161 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 162 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 166 Static void ehci_idone(struct ehci_xfer *); 167 Static void ehci_timeout(void *); 168 Static void ehci_timeout_task(void *); 169 Static void ehci_intrlist_timeout(void *); 170 Static void ehci_doorbell(void *); 171 Static void ehci_pcd(void *); 172 173 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 174 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 Static int ehci_roothub_ctrl(struct usbd_bus *, 177 usb_device_request_t *, void *, int); 178 179 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 180 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 181 Static void ehci_root_intr_abort(usbd_xfer_handle); 182 Static void ehci_root_intr_close(usbd_pipe_handle); 183 Static void ehci_root_intr_done(usbd_xfer_handle); 184 185 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 186 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 187 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 188 Static void ehci_device_ctrl_close(usbd_pipe_handle); 189 Static void ehci_device_ctrl_done(usbd_xfer_handle); 190 191 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 192 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 193 Static void ehci_device_bulk_abort(usbd_xfer_handle); 194 Static void ehci_device_bulk_close(usbd_pipe_handle); 195 Static void ehci_device_bulk_done(usbd_xfer_handle); 196 197 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 198 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 199 Static void ehci_device_intr_abort(usbd_xfer_handle); 200 Static void ehci_device_intr_close(usbd_pipe_handle); 201 Static void ehci_device_intr_done(usbd_xfer_handle); 202 203 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 204 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 205 Static void ehci_device_isoc_abort(usbd_xfer_handle); 206 Static void ehci_device_isoc_close(usbd_pipe_handle); 207 Static void ehci_device_isoc_done(usbd_xfer_handle); 208 209 Static usbd_status ehci_device_fs_isoc_transfer(usbd_xfer_handle); 210 Static usbd_status ehci_device_fs_isoc_start(usbd_xfer_handle); 211 Static void ehci_device_fs_isoc_abort(usbd_xfer_handle); 212 Static void ehci_device_fs_isoc_close(usbd_pipe_handle); 213 Static void ehci_device_fs_isoc_done(usbd_xfer_handle); 214 215 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe); 216 Static void ehci_noop(usbd_pipe_handle pipe); 217 218 Static void ehci_disown(ehci_softc_t *, int, int); 219 220 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 221 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 222 223 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 224 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 225 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 226 ehci_softc_t *, int, int, usbd_xfer_handle, 227 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 228 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 229 ehci_soft_qtd_t *); 230 231 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *sc); 232 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *sc); 233 Static void ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd); 234 Static void ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *); 235 Static void ehci_rem_free_itd_chain(ehci_softc_t *sc, 236 struct ehci_xfer *exfer); 237 Static void ehci_rem_free_sitd_chain(ehci_softc_t *sc, 238 struct ehci_xfer *exfer); 239 Static void ehci_abort_isoc_xfer(usbd_xfer_handle xfer, 240 usbd_status status); 241 242 Static usbd_status ehci_device_request(usbd_xfer_handle xfer); 243 244 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 245 int ival); 246 247 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 248 ehci_soft_qh_t *); 249 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 250 ehci_soft_qh_t *); 251 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 252 Static void ehci_sync_hc(ehci_softc_t *); 253 254 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 255 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 256 257 #ifdef EHCI_DEBUG 258 Static ehci_softc_t *theehci; 259 void ehci_dump(void); 260 #endif 261 262 #ifdef EHCI_DEBUG 263 Static void ehci_dump_regs(ehci_softc_t *); 264 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 265 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 266 Static void ehci_dump_qtd(ehci_qtd_t *); 267 Static void ehci_dump_sqh(ehci_soft_qh_t *); 268 Static void ehci_dump_sitd(struct ehci_soft_itd *itd); 269 Static void ehci_dump_itd(struct ehci_soft_itd *); 270 Static void ehci_dump_exfer(struct ehci_xfer *); 271 #endif 272 273 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 274 275 #define ehci_add_intr_list(sc, ex) \ 276 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 277 #define ehci_del_intr_list(sc, ex) \ 278 do { \ 279 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 280 (ex)->inext.tqe_prev = NULL; \ 281 } while (0) 282 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 283 284 Static const struct usbd_bus_methods ehci_bus_methods = { 285 .ubm_open = ehci_open, 286 .ubm_softint = ehci_softintr, 287 .ubm_dopoll = ehci_poll, 288 .ubm_allocx = ehci_allocx, 289 .ubm_freex = ehci_freex, 290 .ubm_getlock = ehci_get_lock, 291 .ubm_rhctrl = ehci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 295 .upm_transfer = ehci_root_intr_transfer, 296 .upm_start = ehci_root_intr_start, 297 .upm_abort = ehci_root_intr_abort, 298 .upm_close = ehci_root_intr_close, 299 .upm_cleartoggle = ehci_noop, 300 .upm_done = ehci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 304 .upm_transfer = ehci_device_ctrl_transfer, 305 .upm_start = ehci_device_ctrl_start, 306 .upm_abort = ehci_device_ctrl_abort, 307 .upm_close = ehci_device_ctrl_close, 308 .upm_cleartoggle = ehci_noop, 309 .upm_done = ehci_device_ctrl_done, 310 }; 311 312 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 313 .upm_transfer = ehci_device_intr_transfer, 314 .upm_start = ehci_device_intr_start, 315 .upm_abort = ehci_device_intr_abort, 316 .upm_close = ehci_device_intr_close, 317 .upm_cleartoggle = ehci_device_clear_toggle, 318 .upm_done = ehci_device_intr_done, 319 }; 320 321 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 322 .upm_transfer = ehci_device_bulk_transfer, 323 .upm_start = ehci_device_bulk_start, 324 .upm_abort = ehci_device_bulk_abort, 325 .upm_close = ehci_device_bulk_close, 326 .upm_cleartoggle = ehci_device_clear_toggle, 327 .upm_done = ehci_device_bulk_done, 328 }; 329 330 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 331 .upm_transfer = ehci_device_isoc_transfer, 332 .upm_start = ehci_device_isoc_start, 333 .upm_abort = ehci_device_isoc_abort, 334 .upm_close = ehci_device_isoc_close, 335 .upm_cleartoggle = ehci_noop, 336 .upm_done = ehci_device_isoc_done, 337 }; 338 339 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 340 .upm_transfer = ehci_device_fs_isoc_transfer, 341 .upm_start = ehci_device_fs_isoc_start, 342 .upm_abort = ehci_device_fs_isoc_abort, 343 .upm_close = ehci_device_fs_isoc_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_fs_isoc_done, 346 }; 347 348 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 349 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 350 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 351 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 352 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 353 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 354 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 355 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 356 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 357 }; 358 359 usbd_status 360 ehci_init(ehci_softc_t *sc) 361 { 362 uint32_t vers, sparams, cparams, hcr; 363 u_int i; 364 usbd_status err; 365 ehci_soft_qh_t *sqh; 366 u_int ncomp; 367 368 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 369 #ifdef EHCI_DEBUG 370 theehci = sc; 371 #endif 372 373 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 374 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 375 cv_init(&sc->sc_softwake_cv, "ehciab"); 376 cv_init(&sc->sc_doorbell, "ehcidi"); 377 378 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 379 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 380 381 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 382 ehci_doorbell, sc); 383 KASSERT(sc->sc_doorbell_si != NULL); 384 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 385 ehci_pcd, sc); 386 KASSERT(sc->sc_pcd_si != NULL); 387 388 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 389 390 vers = EREAD2(sc, EHCI_HCIVERSION); 391 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 392 vers >> 8, vers & 0xff); 393 394 sparams = EREAD4(sc, EHCI_HCSPARAMS); 395 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 396 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 397 ncomp = EHCI_HCS_N_CC(sparams); 398 if (ncomp != sc->sc_ncomp) { 399 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 400 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 401 #if NOHCI == 0 || NUHCI == 0 402 aprint_error("%s: ohci or uhci probably not configured\n", 403 device_xname(sc->sc_dev)); 404 #endif 405 if (ncomp < sc->sc_ncomp) 406 sc->sc_ncomp = ncomp; 407 } 408 if (sc->sc_ncomp > 0) { 409 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 410 aprint_normal("%s: companion controller%s, %d port%s each:", 411 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 412 EHCI_HCS_N_PCC(sparams), 413 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 414 for (i = 0; i < sc->sc_ncomp; i++) 415 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 416 aprint_normal("\n"); 417 } 418 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 419 cparams = EREAD4(sc, EHCI_HCCPARAMS); 420 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 421 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 422 423 if (EHCI_HCC_64BIT(cparams)) { 424 /* MUST clear segment register if 64 bit capable. */ 425 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 426 } 427 428 sc->sc_bus.ub_revision = USBREV_2_0; 429 sc->sc_bus.ub_usedma = true; 430 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 431 432 /* Reset the controller */ 433 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 434 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 435 usb_delay_ms(&sc->sc_bus, 1); 436 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 437 for (i = 0; i < 100; i++) { 438 usb_delay_ms(&sc->sc_bus, 1); 439 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 440 if (!hcr) 441 break; 442 } 443 if (hcr) { 444 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 445 return USBD_IOERROR; 446 } 447 if (sc->sc_vendor_init) 448 sc->sc_vendor_init(sc); 449 450 /* 451 * If we are doing embedded transaction translation function, force 452 * the controller to host mode. 453 */ 454 if (sc->sc_flags & EHCIF_ETTF) { 455 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 456 usbmode &= ~EHCI_USBMODE_CM; 457 usbmode |= EHCI_USBMODE_CM_HOST; 458 EWRITE4(sc, EHCI_USBMODE, usbmode); 459 } 460 461 /* XXX need proper intr scheduling */ 462 sc->sc_rand = 96; 463 464 /* frame list size at default, read back what we got and use that */ 465 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 466 case 0: sc->sc_flsize = 1024; break; 467 case 1: sc->sc_flsize = 512; break; 468 case 2: sc->sc_flsize = 256; break; 469 case 3: return USBD_IOERROR; 470 } 471 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 472 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 473 if (err) 474 return err; 475 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 476 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 477 478 for (i = 0; i < sc->sc_flsize; i++) { 479 sc->sc_flist[i] = EHCI_NULL; 480 } 481 482 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 483 484 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 485 KM_SLEEP); 486 if (sc->sc_softitds == NULL) 487 return ENOMEM; 488 LIST_INIT(&sc->sc_freeitds); 489 LIST_INIT(&sc->sc_freesitds); 490 TAILQ_INIT(&sc->sc_intrhead); 491 492 /* Set up the bus struct. */ 493 sc->sc_bus.ub_methods = &ehci_bus_methods; 494 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 495 496 sc->sc_eintrs = EHCI_NORMAL_INTRS; 497 498 /* 499 * Allocate the interrupt dummy QHs. These are arranged to give poll 500 * intervals that are powers of 2 times 1ms. 501 */ 502 for (i = 0; i < EHCI_INTRQHS; i++) { 503 sqh = ehci_alloc_sqh(sc); 504 if (sqh == NULL) { 505 err = USBD_NOMEM; 506 goto bad1; 507 } 508 sc->sc_islots[i].sqh = sqh; 509 } 510 for (i = 0; i < EHCI_INTRQHS; i++) { 511 sqh = sc->sc_islots[i].sqh; 512 if (i == 0) { 513 /* The last (1ms) QH terminates. */ 514 sqh->qh.qh_link = EHCI_NULL; 515 sqh->next = NULL; 516 } else { 517 /* Otherwise the next QH has half the poll interval */ 518 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 519 sqh->qh.qh_link = htole32(sqh->next->physaddr | 520 EHCI_LINK_QH); 521 } 522 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 523 sqh->qh.qh_curqtd = EHCI_NULL; 524 sqh->next = NULL; 525 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 526 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 527 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 528 sqh->sqtd = NULL; 529 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 531 } 532 /* Point the frame list at the last level (128ms). */ 533 for (i = 0; i < sc->sc_flsize; i++) { 534 int j; 535 536 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 537 revbits[i & (EHCI_MAX_POLLRATE-1)]; 538 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 539 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 540 i)].sqh->physaddr); 541 } 542 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 543 BUS_DMASYNC_PREWRITE); 544 545 /* Allocate dummy QH that starts the async list. */ 546 sqh = ehci_alloc_sqh(sc); 547 if (sqh == NULL) { 548 err = USBD_NOMEM; 549 goto bad1; 550 } 551 /* Fill the QH */ 552 sqh->qh.qh_endp = 553 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 554 sqh->qh.qh_link = 555 htole32(sqh->physaddr | EHCI_LINK_QH); 556 sqh->qh.qh_curqtd = EHCI_NULL; 557 sqh->next = NULL; 558 /* Fill the overlay qTD */ 559 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 560 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 561 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 562 sqh->sqtd = NULL; 563 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 564 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 565 #ifdef EHCI_DEBUG 566 ehci_dump_sqh(sqh); 567 #endif 568 569 /* Point to async list */ 570 sc->sc_async_head = sqh; 571 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 572 573 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 574 575 /* Turn on controller */ 576 EOWRITE4(sc, EHCI_USBCMD, 577 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 578 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 579 EHCI_CMD_ASE | 580 EHCI_CMD_PSE | 581 EHCI_CMD_RS); 582 583 /* Take over port ownership */ 584 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 585 586 for (i = 0; i < 100; i++) { 587 usb_delay_ms(&sc->sc_bus, 1); 588 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 589 if (!hcr) 590 break; 591 } 592 if (hcr) { 593 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 594 return USBD_IOERROR; 595 } 596 597 /* Enable interrupts */ 598 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 599 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 600 601 return USBD_NORMAL_COMPLETION; 602 603 #if 0 604 bad2: 605 ehci_free_sqh(sc, sc->sc_async_head); 606 #endif 607 bad1: 608 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 609 return err; 610 } 611 612 int 613 ehci_intr(void *v) 614 { 615 ehci_softc_t *sc = v; 616 int ret = 0; 617 618 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 619 620 if (sc == NULL) 621 return 0; 622 623 mutex_spin_enter(&sc->sc_intr_lock); 624 625 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 626 goto done; 627 628 /* If we get an interrupt while polling, then just ignore it. */ 629 if (sc->sc_bus.ub_usepolling) { 630 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 631 632 if (intrs) 633 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 634 #ifdef DIAGNOSTIC 635 USBHIST_LOGN(ehcidebug, 16, 636 "ignored interrupt while polling", 0, 0, 0, 0); 637 #endif 638 goto done; 639 } 640 641 ret = ehci_intr1(sc); 642 643 done: 644 mutex_spin_exit(&sc->sc_intr_lock); 645 return ret; 646 } 647 648 Static int 649 ehci_intr1(ehci_softc_t *sc) 650 { 651 uint32_t intrs, eintrs; 652 653 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 654 655 /* In case the interrupt occurs before initialization has completed. */ 656 if (sc == NULL) { 657 #ifdef DIAGNOSTIC 658 printf("ehci_intr1: sc == NULL\n"); 659 #endif 660 return 0; 661 } 662 663 KASSERT(mutex_owned(&sc->sc_intr_lock)); 664 665 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 666 if (!intrs) 667 return 0; 668 669 eintrs = intrs & sc->sc_eintrs; 670 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 671 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 672 if (!eintrs) 673 return 0; 674 675 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 676 if (eintrs & EHCI_STS_IAA) { 677 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 678 kpreempt_disable(); 679 KASSERT(sc->sc_doorbell_si != NULL); 680 softint_schedule(sc->sc_doorbell_si); 681 kpreempt_enable(); 682 eintrs &= ~EHCI_STS_IAA; 683 } 684 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 685 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 686 eintrs & EHCI_STS_INT ? 1 : 0, 687 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 688 usb_schedsoftintr(&sc->sc_bus); 689 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 690 } 691 if (eintrs & EHCI_STS_HSE) { 692 printf("%s: unrecoverable error, controller halted\n", 693 device_xname(sc->sc_dev)); 694 /* XXX what else */ 695 } 696 if (eintrs & EHCI_STS_PCD) { 697 kpreempt_disable(); 698 KASSERT(sc->sc_pcd_si != NULL); 699 softint_schedule(sc->sc_pcd_si); 700 kpreempt_enable(); 701 eintrs &= ~EHCI_STS_PCD; 702 } 703 704 if (eintrs != 0) { 705 /* Block unprocessed interrupts. */ 706 sc->sc_eintrs &= ~eintrs; 707 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 708 printf("%s: blocking intrs 0x%x\n", 709 device_xname(sc->sc_dev), eintrs); 710 } 711 712 return 1; 713 } 714 715 Static void 716 ehci_doorbell(void *addr) 717 { 718 ehci_softc_t *sc = addr; 719 720 mutex_enter(&sc->sc_lock); 721 cv_broadcast(&sc->sc_doorbell); 722 mutex_exit(&sc->sc_lock); 723 } 724 725 Static void 726 ehci_pcd(void *addr) 727 { 728 ehci_softc_t *sc = addr; 729 usbd_xfer_handle xfer; 730 u_char *p; 731 int i, m; 732 733 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 734 735 mutex_enter(&sc->sc_lock); 736 xfer = sc->sc_intrxfer; 737 738 if (xfer == NULL) { 739 /* Just ignore the change. */ 740 goto done; 741 } 742 743 p = xfer->ux_buf; 744 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 745 memset(p, 0, xfer->ux_length); 746 for (i = 1; i <= m; i++) { 747 /* Pick out CHANGE bits from the status reg. */ 748 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 749 p[i/8] |= 1 << (i%8); 750 if (i % 8 == 7) 751 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 752 p[i/8], 0, 0); 753 } 754 xfer->ux_actlen = xfer->ux_length; 755 xfer->ux_status = USBD_NORMAL_COMPLETION; 756 757 usb_transfer_complete(xfer); 758 759 done: 760 mutex_exit(&sc->sc_lock); 761 } 762 763 Static void 764 ehci_softintr(void *v) 765 { 766 struct usbd_bus *bus = v; 767 ehci_softc_t *sc = bus->ub_hcpriv; 768 struct ehci_xfer *ex, *nextex; 769 770 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 771 772 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 773 774 /* 775 * The only explanation I can think of for why EHCI is as brain dead 776 * as UHCI interrupt-wise is that Intel was involved in both. 777 * An interrupt just tells us that something is done, we have no 778 * clue what, so we need to scan through all active transfers. :-( 779 */ 780 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 781 nextex = TAILQ_NEXT(ex, inext); 782 ehci_check_intr(sc, ex); 783 } 784 785 /* Schedule a callout to catch any dropped transactions. */ 786 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 787 !TAILQ_EMPTY(&sc->sc_intrhead)) 788 callout_reset(&sc->sc_tmo_intrlist, 789 hz, ehci_intrlist_timeout, sc); 790 791 if (sc->sc_softwake) { 792 sc->sc_softwake = 0; 793 cv_broadcast(&sc->sc_softwake_cv); 794 } 795 } 796 797 /* Check for an interrupt. */ 798 Static void 799 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 800 { 801 usbd_device_handle dev = ex->xfer.ux_pipe->up_dev; 802 int attr; 803 804 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 805 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 806 807 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 808 809 attr = ex->xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 810 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 811 if (dev->ud_speed == USB_SPEED_HIGH) 812 ehci_check_itd_intr(sc, ex); 813 else 814 ehci_check_sitd_intr(sc, ex); 815 } else 816 ehci_check_qh_intr(sc, ex); 817 818 return; 819 } 820 821 Static void 822 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 823 { 824 ehci_soft_qtd_t *sqtd, *lsqtd; 825 uint32_t status; 826 827 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 828 829 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 830 831 if (ex->sqtdstart == NULL) { 832 printf("ehci_check_qh_intr: not valid sqtd\n"); 833 return; 834 } 835 836 lsqtd = ex->sqtdend; 837 #ifdef DIAGNOSTIC 838 if (lsqtd == NULL) { 839 printf("ehci_check_qh_intr: lsqtd==0\n"); 840 return; 841 } 842 #endif 843 /* 844 * If the last TD is still active we need to check whether there 845 * is an error somewhere in the middle, or whether there was a 846 * short packet (SPD and not ACTIVE). 847 */ 848 usb_syncmem(&lsqtd->dma, 849 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 850 sizeof(lsqtd->qtd.qtd_status), 851 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 852 status = le32toh(lsqtd->qtd.qtd_status); 853 usb_syncmem(&lsqtd->dma, 854 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 855 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 856 if (status & EHCI_QTD_ACTIVE) { 857 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 858 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 859 usb_syncmem(&sqtd->dma, 860 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 861 sizeof(sqtd->qtd.qtd_status), 862 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 863 status = le32toh(sqtd->qtd.qtd_status); 864 usb_syncmem(&sqtd->dma, 865 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 866 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 867 /* If there's an active QTD the xfer isn't done. */ 868 if (status & EHCI_QTD_ACTIVE) 869 break; 870 /* Any kind of error makes the xfer done. */ 871 if (status & EHCI_QTD_HALTED) 872 goto done; 873 /* Handle short packets */ 874 if (EHCI_QTD_GET_BYTES(status) != 0) { 875 usbd_pipe_handle pipe = ex->xfer.ux_pipe; 876 usb_endpoint_descriptor_t *ed = 877 pipe->up_endpoint->ue_edesc; 878 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 879 880 /* 881 * If we get here for a control transfer then 882 * we need to let the hardware complete the 883 * status phase. That is, we're not done 884 * quite yet. 885 * 886 * Otherwise, we're done. 887 */ 888 if (xt == UE_CONTROL) { 889 break; 890 } 891 goto done; 892 } 893 } 894 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 895 ex, ex->sqtdstart, 0, 0); 896 return; 897 } 898 done: 899 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 900 callout_stop(&ex->xfer.ux_callout); 901 ehci_idone(ex); 902 } 903 904 Static void 905 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 906 { 907 ehci_soft_itd_t *itd; 908 int i; 909 910 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 911 912 KASSERT(mutex_owned(&sc->sc_lock)); 913 914 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.ux_pipe->up_queue)) 915 return; 916 917 if (ex->itdstart == NULL) { 918 printf("ehci_check_itd_intr: not valid itd\n"); 919 return; 920 } 921 922 itd = ex->itdend; 923 #ifdef DIAGNOSTIC 924 if (itd == NULL) { 925 printf("ehci_check_itd_intr: itdend == 0\n"); 926 return; 927 } 928 #endif 929 930 /* 931 * check no active transfers in last itd, meaning we're finished 932 */ 933 934 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 935 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 936 BUS_DMASYNC_POSTREAD); 937 938 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 939 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 940 break; 941 } 942 943 if (i == EHCI_ITD_NUFRAMES) { 944 goto done; /* All 8 descriptors inactive, it's done */ 945 } 946 947 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 948 ex->itdstart, 0, 0); 949 return; 950 done: 951 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 952 callout_stop(&ex->xfer.ux_callout); 953 ehci_idone(ex); 954 } 955 956 void 957 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 958 { 959 ehci_soft_sitd_t *sitd; 960 961 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 962 963 KASSERT(mutex_owned(&sc->sc_lock)); 964 965 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.ux_pipe->up_queue)) 966 return; 967 968 if (ex->sitdstart == NULL) { 969 printf("ehci_check_sitd_intr: not valid sitd\n"); 970 return; 971 } 972 973 sitd = ex->sitdend; 974 #ifdef DIAGNOSTIC 975 if (sitd == NULL) { 976 printf("ehci_check_sitd_intr: sitdend == 0\n"); 977 return; 978 } 979 #endif 980 981 /* 982 * check no active transfers in last sitd, meaning we're finished 983 */ 984 985 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 986 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 987 BUS_DMASYNC_POSTREAD); 988 989 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 990 return; 991 992 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 993 callout_stop(&(ex->xfer.ux_callout)); 994 ehci_idone(ex); 995 } 996 997 998 Static void 999 ehci_idone(struct ehci_xfer *ex) 1000 { 1001 usbd_xfer_handle xfer = &ex->xfer; 1002 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1003 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1004 ehci_soft_qtd_t *sqtd, *lsqtd; 1005 uint32_t status = 0, nstatus = 0; 1006 int actlen; 1007 1008 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1009 1010 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1011 1012 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1013 1014 #ifdef DIAGNOSTIC 1015 if (ex->isdone) { 1016 printf("ehci_idone: ex=%p is done!\n", ex); 1017 #ifdef EHCI_DEBUG 1018 ehci_dump_exfer(ex); 1019 #endif 1020 return; 1021 } 1022 ex->isdone = 1; 1023 #endif 1024 1025 if (xfer->ux_status == USBD_CANCELLED || 1026 xfer->ux_status == USBD_TIMEOUT) { 1027 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1028 return; 1029 } 1030 1031 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1032 #ifdef EHCI_DEBUG 1033 ehci_dump_sqtds(ex->sqtdstart); 1034 #endif 1035 1036 /* The transfer is done, compute actual length and status. */ 1037 1038 u_int xfertype, speed; 1039 1040 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1041 speed = xfer->ux_pipe->up_dev->ud_speed; 1042 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1043 /* HS isoc transfer */ 1044 1045 struct ehci_soft_itd *itd; 1046 int i, nframes, len, uframes; 1047 1048 nframes = 0; 1049 actlen = 0; 1050 1051 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1052 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1053 1054 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1055 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1056 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1057 BUS_DMASYNC_POSTREAD); 1058 1059 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1060 /* XXX - driver didn't fill in the frame full 1061 * of uframes. This leads to scheduling 1062 * inefficiencies, but working around 1063 * this doubles complexity of tracking 1064 * an xfer. 1065 */ 1066 if (nframes >= xfer->ux_nframes) 1067 break; 1068 1069 status = le32toh(itd->itd.itd_ctl[i]); 1070 len = EHCI_ITD_GET_LEN(status); 1071 if (EHCI_ITD_GET_STATUS(status) != 0) 1072 len = 0; /*No valid data on error*/ 1073 1074 xfer->ux_frlengths[nframes++] = len; 1075 actlen += len; 1076 } 1077 1078 if (nframes >= xfer->ux_nframes) 1079 break; 1080 } 1081 1082 xfer->ux_actlen = actlen; 1083 xfer->ux_status = USBD_NORMAL_COMPLETION; 1084 goto end; 1085 } 1086 1087 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1088 /* FS isoc transfer */ 1089 struct ehci_soft_sitd *sitd; 1090 int nframes, len; 1091 1092 nframes = 0; 1093 actlen = 0; 1094 1095 for (sitd = ex->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1096 usb_syncmem(&sitd->dma,sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 1097 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 1098 BUS_DMASYNC_POSTREAD); 1099 1100 /* XXX - driver didn't fill in the frame full 1101 * of uframes. This leads to scheduling 1102 * inefficiencies, but working around 1103 * this doubles complexity of tracking 1104 * an xfer. 1105 */ 1106 if (nframes >= xfer->ux_nframes) 1107 break; 1108 1109 status = le32toh(sitd->sitd.sitd_trans); 1110 len = EHCI_SITD_GET_LEN(status); 1111 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1112 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1113 /* No valid data on error */ 1114 len = xfer->ux_frlengths[nframes]; 1115 } 1116 1117 /* 1118 * frlengths[i]: # of bytes to send 1119 * len: # of bytes host didn't send 1120 */ 1121 xfer->ux_frlengths[nframes] -= len; 1122 /* frlengths[i]: # of bytes host sent */ 1123 actlen += xfer->ux_frlengths[nframes++]; 1124 1125 if (nframes >= xfer->ux_nframes) 1126 break; 1127 } 1128 1129 xfer->ux_actlen = actlen; 1130 xfer->ux_status = USBD_NORMAL_COMPLETION; 1131 goto end; 1132 } 1133 1134 /* Continue processing xfers using queue heads */ 1135 1136 lsqtd = ex->sqtdend; 1137 actlen = 0; 1138 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; 1139 sqtd = sqtd->nextqtd) { 1140 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1141 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1142 nstatus = le32toh(sqtd->qtd.qtd_status); 1143 if (nstatus & EHCI_QTD_ACTIVE) 1144 break; 1145 1146 status = nstatus; 1147 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1148 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1149 } 1150 1151 1152 /* 1153 * If there are left over TDs we need to update the toggle. 1154 * The default pipe doesn't need it since control transfers 1155 * start the toggle at 0 every time. 1156 * For a short transfer we need to update the toggle for the missing 1157 * packets within the qTD. 1158 */ 1159 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1160 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1161 USBHIST_LOG(ehcidebug, 1162 "toggle update status=0x%08x nstatus=0x%08x", 1163 status, nstatus, 0, 0); 1164 #if 0 1165 ehci_dump_sqh(epipe->sqh); 1166 ehci_dump_sqtds(ex->sqtdstart); 1167 #endif 1168 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1169 } 1170 1171 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1172 actlen, status, 0); 1173 xfer->ux_actlen = actlen; 1174 if (status & EHCI_QTD_HALTED) { 1175 #ifdef EHCI_DEBUG 1176 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1177 xfer->ux_pipe->up_dev->ud_addr, 1178 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1179 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d stat=%#x", 1180 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1181 status, 0); 1182 USBHIST_LOG(ehcidebug, 1183 "active =%d halted=%d buferr=%d babble=%d", 1184 status & EHCI_QTD_ACTIVE ? 1 : 0, 1185 status & EHCI_QTD_HALTED ? 1 : 0, 1186 status & EHCI_QTD_BUFERR ? 1 : 0, 1187 status & EHCI_QTD_BABBLE ? 1 : 0); 1188 1189 USBHIST_LOG(ehcidebug, 1190 "xacterr=%d missed=%d split =%d ping =%d", 1191 status & EHCI_QTD_XACTERR ? 1 : 0, 1192 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1193 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1194 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1195 1196 ehci_dump_sqh(epipe->sqh); 1197 ehci_dump_sqtds(ex->sqtdstart); 1198 #endif 1199 /* low&full speed has an extra error flag */ 1200 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1201 EHCI_QH_SPEED_HIGH) 1202 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1203 else 1204 status &= EHCI_QTD_STATERRS; 1205 if (status == 0) /* no other errors means a stall */ { 1206 xfer->ux_status = USBD_STALLED; 1207 } else { 1208 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1209 } 1210 /* XXX need to reset TT on missed microframe */ 1211 if (status & EHCI_QTD_MISSEDMICRO) { 1212 printf("%s: missed microframe, TT reset not " 1213 "implemented, hub might be inoperational\n", 1214 device_xname(sc->sc_dev)); 1215 } 1216 } else { 1217 xfer->ux_status = USBD_NORMAL_COMPLETION; 1218 } 1219 1220 end: 1221 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1222 * during this call, before methods->done is called: dma sync required 1223 * beforehand? */ 1224 usb_transfer_complete(xfer); 1225 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1226 } 1227 1228 /* 1229 * Wait here until controller claims to have an interrupt. 1230 * Then call ehci_intr and return. Use timeout to avoid waiting 1231 * too long. 1232 */ 1233 Static void 1234 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1235 { 1236 int timo; 1237 uint32_t intrs; 1238 1239 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1240 1241 xfer->ux_status = USBD_IN_PROGRESS; 1242 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1243 usb_delay_ms(&sc->sc_bus, 1); 1244 if (sc->sc_dying) 1245 break; 1246 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1247 sc->sc_eintrs; 1248 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1249 #ifdef EHCI_DEBUG 1250 if (ehcidebug > 15) 1251 ehci_dump_regs(sc); 1252 #endif 1253 if (intrs) { 1254 mutex_spin_enter(&sc->sc_intr_lock); 1255 ehci_intr1(sc); 1256 mutex_spin_exit(&sc->sc_intr_lock); 1257 if (xfer->ux_status != USBD_IN_PROGRESS) 1258 return; 1259 } 1260 } 1261 1262 /* Timeout */ 1263 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1264 xfer->ux_status = USBD_TIMEOUT; 1265 mutex_enter(&sc->sc_lock); 1266 usb_transfer_complete(xfer); 1267 mutex_exit(&sc->sc_lock); 1268 /* XXX should free TD */ 1269 } 1270 1271 Static void 1272 ehci_poll(struct usbd_bus *bus) 1273 { 1274 ehci_softc_t *sc = bus->ub_hcpriv; 1275 1276 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1277 1278 #ifdef EHCI_DEBUG 1279 static int last; 1280 int new; 1281 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1282 if (new != last) { 1283 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1284 last = new; 1285 } 1286 #endif 1287 1288 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1289 mutex_spin_enter(&sc->sc_intr_lock); 1290 ehci_intr1(sc); 1291 mutex_spin_exit(&sc->sc_intr_lock); 1292 } 1293 } 1294 1295 void 1296 ehci_childdet(device_t self, device_t child) 1297 { 1298 struct ehci_softc *sc = device_private(self); 1299 1300 KASSERT(sc->sc_child == child); 1301 sc->sc_child = NULL; 1302 } 1303 1304 int 1305 ehci_detach(struct ehci_softc *sc, int flags) 1306 { 1307 int rv = 0; 1308 1309 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1310 1311 if (sc->sc_child != NULL) 1312 rv = config_detach(sc->sc_child, flags); 1313 1314 if (rv != 0) 1315 return rv; 1316 1317 callout_halt(&sc->sc_tmo_intrlist, NULL); 1318 callout_destroy(&sc->sc_tmo_intrlist); 1319 1320 /* XXX free other data structures XXX */ 1321 if (sc->sc_softitds) 1322 kmem_free(sc->sc_softitds, 1323 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1324 cv_destroy(&sc->sc_doorbell); 1325 cv_destroy(&sc->sc_softwake_cv); 1326 1327 #if 0 1328 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1329 1330 softint_disestablish(sc->sc_doorbell_si); 1331 softint_disestablish(sc->sc_pcd_si); 1332 1333 mutex_destroy(&sc->sc_lock); 1334 mutex_destroy(&sc->sc_intr_lock); 1335 #endif 1336 1337 pool_cache_destroy(sc->sc_xferpool); 1338 1339 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1340 1341 return rv; 1342 } 1343 1344 1345 int 1346 ehci_activate(device_t self, enum devact act) 1347 { 1348 struct ehci_softc *sc = device_private(self); 1349 1350 switch (act) { 1351 case DVACT_DEACTIVATE: 1352 sc->sc_dying = 1; 1353 return 0; 1354 default: 1355 return EOPNOTSUPP; 1356 } 1357 } 1358 1359 /* 1360 * Handle suspend/resume. 1361 * 1362 * We need to switch to polling mode here, because this routine is 1363 * called from an interrupt context. This is all right since we 1364 * are almost suspended anyway. 1365 * 1366 * Note that this power handler isn't to be registered directly; the 1367 * bus glue needs to call out to it. 1368 */ 1369 bool 1370 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1371 { 1372 ehci_softc_t *sc = device_private(dv); 1373 int i; 1374 uint32_t cmd, hcr; 1375 1376 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1377 1378 mutex_spin_enter(&sc->sc_intr_lock); 1379 sc->sc_bus.ub_usepolling++; 1380 mutex_spin_exit(&sc->sc_intr_lock); 1381 1382 for (i = 1; i <= sc->sc_noport; i++) { 1383 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1384 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1385 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1386 } 1387 1388 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1389 1390 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1391 EOWRITE4(sc, EHCI_USBCMD, cmd); 1392 1393 for (i = 0; i < 100; i++) { 1394 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1395 if (hcr == 0) 1396 break; 1397 1398 usb_delay_ms(&sc->sc_bus, 1); 1399 } 1400 if (hcr != 0) 1401 printf("%s: reset timeout\n", device_xname(dv)); 1402 1403 cmd &= ~EHCI_CMD_RS; 1404 EOWRITE4(sc, EHCI_USBCMD, cmd); 1405 1406 for (i = 0; i < 100; i++) { 1407 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1408 if (hcr == EHCI_STS_HCH) 1409 break; 1410 1411 usb_delay_ms(&sc->sc_bus, 1); 1412 } 1413 if (hcr != EHCI_STS_HCH) 1414 printf("%s: config timeout\n", device_xname(dv)); 1415 1416 mutex_spin_enter(&sc->sc_intr_lock); 1417 sc->sc_bus.ub_usepolling--; 1418 mutex_spin_exit(&sc->sc_intr_lock); 1419 1420 return true; 1421 } 1422 1423 bool 1424 ehci_resume(device_t dv, const pmf_qual_t *qual) 1425 { 1426 ehci_softc_t *sc = device_private(dv); 1427 int i; 1428 uint32_t cmd, hcr; 1429 1430 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1431 1432 /* restore things in case the bios sucks */ 1433 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1434 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1435 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1436 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1437 1438 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1439 1440 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1441 1442 hcr = 0; 1443 for (i = 1; i <= sc->sc_noport; i++) { 1444 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1445 if ((cmd & EHCI_PS_PO) == 0 && 1446 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1447 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1448 hcr = 1; 1449 } 1450 } 1451 1452 if (hcr) { 1453 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1454 1455 for (i = 1; i <= sc->sc_noport; i++) { 1456 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1457 if ((cmd & EHCI_PS_PO) == 0 && 1458 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1459 EOWRITE4(sc, EHCI_PORTSC(i), 1460 cmd & ~EHCI_PS_FPR); 1461 } 1462 } 1463 1464 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1465 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1466 1467 for (i = 0; i < 100; i++) { 1468 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1469 if (hcr != EHCI_STS_HCH) 1470 break; 1471 1472 usb_delay_ms(&sc->sc_bus, 1); 1473 } 1474 if (hcr == EHCI_STS_HCH) 1475 printf("%s: config timeout\n", device_xname(dv)); 1476 1477 return true; 1478 } 1479 1480 /* 1481 * Shut down the controller when the system is going down. 1482 */ 1483 bool 1484 ehci_shutdown(device_t self, int flags) 1485 { 1486 ehci_softc_t *sc = device_private(self); 1487 1488 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1489 1490 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1491 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1492 return true; 1493 } 1494 1495 Static usbd_xfer_handle 1496 ehci_allocx(struct usbd_bus *bus) 1497 { 1498 struct ehci_softc *sc = bus->ub_hcpriv; 1499 usbd_xfer_handle xfer; 1500 1501 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1502 if (xfer != NULL) { 1503 memset(xfer, 0, sizeof(struct ehci_xfer)); 1504 #ifdef DIAGNOSTIC 1505 EXFER(xfer)->isdone = 1; 1506 xfer->ux_state = XFER_BUSY; 1507 #endif 1508 } 1509 return xfer; 1510 } 1511 1512 Static void 1513 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1514 { 1515 struct ehci_softc *sc = bus->ub_hcpriv; 1516 1517 #ifdef DIAGNOSTIC 1518 if (xfer->ux_state != XFER_BUSY) { 1519 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1520 xfer->ux_state); 1521 } 1522 xfer->ux_state = XFER_FREE; 1523 if (!EXFER(xfer)->isdone) { 1524 printf("ehci_freex: !isdone\n"); 1525 } 1526 #endif 1527 pool_cache_put(sc->sc_xferpool, xfer); 1528 } 1529 1530 Static void 1531 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1532 { 1533 struct ehci_softc *sc = bus->ub_hcpriv; 1534 1535 *lock = &sc->sc_lock; 1536 } 1537 1538 Static void 1539 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1540 { 1541 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1542 1543 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1544 1545 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1546 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1547 #ifdef EHCI_DEBUG 1548 if (ehcidebug) 1549 usbd_dump_pipe(pipe); 1550 #endif 1551 epipe->nexttoggle = 0; 1552 } 1553 1554 Static void 1555 ehci_noop(usbd_pipe_handle pipe) 1556 { 1557 } 1558 1559 #ifdef EHCI_DEBUG 1560 /* 1561 * Unused function - this is meant to be called from a kernel 1562 * debugger. 1563 */ 1564 void 1565 ehci_dump(void) 1566 { 1567 ehci_softc_t *sc = theehci; 1568 int i; 1569 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1570 EOREAD4(sc, EHCI_USBCMD), 1571 EOREAD4(sc, EHCI_USBSTS), 1572 EOREAD4(sc, EHCI_USBINTR)); 1573 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1574 EOREAD4(sc, EHCI_FRINDEX), 1575 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1576 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1577 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1578 for (i = 1; i <= sc->sc_noport; i++) 1579 printf("port %d status=0x%08x\n", i, 1580 EOREAD4(sc, EHCI_PORTSC(i))); 1581 } 1582 1583 Static void 1584 ehci_dump_regs(ehci_softc_t *sc) 1585 { 1586 int i; 1587 1588 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1589 1590 USBHIST_LOG(ehcidebug, 1591 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1592 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1593 EOREAD4(sc, EHCI_USBINTR), 0); 1594 USBHIST_LOG(ehcidebug, 1595 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1596 "async = 0x%08x", 1597 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1598 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1599 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1600 for (i = 1; i <= sc->sc_noport; i += 2) { 1601 if (i == sc->sc_noport) { 1602 USBHIST_LOG(ehcidebug, 1603 "port %d status = 0x%08x", i, 1604 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1605 } else { 1606 USBHIST_LOG(ehcidebug, 1607 "port %d status = 0x%08x port %d status = 0x%08x", 1608 i, EOREAD4(sc, EHCI_PORTSC(i)), 1609 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1610 } 1611 } 1612 } 1613 1614 #ifdef EHCI_DEBUG 1615 #define ehci_dump_link(link, type) do { \ 1616 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1617 link, \ 1618 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1619 if (type) { \ 1620 USBHIST_LOG(ehcidebug, \ 1621 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1622 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1623 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1624 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1625 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1626 } \ 1627 } while(0) 1628 #else 1629 #define ehci_dump_link(link, type) 1630 #endif 1631 1632 Static void 1633 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1634 { 1635 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1636 int i; 1637 uint32_t stop = 0; 1638 1639 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1640 ehci_dump_sqtd(sqtd); 1641 usb_syncmem(&sqtd->dma, 1642 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1643 sizeof(sqtd->qtd), 1644 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1645 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1646 usb_syncmem(&sqtd->dma, 1647 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1648 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1649 } 1650 if (sqtd) 1651 USBHIST_LOG(ehcidebug, 1652 "dump aborted, too many TDs", 0, 0, 0, 0); 1653 } 1654 1655 Static void 1656 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1657 { 1658 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1659 1660 usb_syncmem(&sqtd->dma, sqtd->offs, 1661 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1662 1663 USBHIST_LOGN(ehcidebug, 10, 1664 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1665 ehci_dump_qtd(&sqtd->qtd); 1666 1667 usb_syncmem(&sqtd->dma, sqtd->offs, 1668 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1669 } 1670 1671 Static void 1672 ehci_dump_qtd(ehci_qtd_t *qtd) 1673 { 1674 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1675 1676 #ifdef USBHIST 1677 uint32_t s = le32toh(qtd->qtd_status); 1678 #endif 1679 1680 USBHIST_LOGN(ehcidebug, 10, 1681 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1682 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1683 USBHIST_LOGN(ehcidebug, 10, 1684 " toggle = %d ioc = %d bytes = %#x " 1685 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1686 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1687 USBHIST_LOGN(ehcidebug, 10, 1688 " cerr = %d pid = %d stat = %x", 1689 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1690 0); 1691 USBHIST_LOGN(ehcidebug, 10, 1692 "active =%d halted=%d buferr=%d babble=%d", 1693 s & EHCI_QTD_ACTIVE ? 1 : 0, 1694 s & EHCI_QTD_HALTED ? 1 : 0, 1695 s & EHCI_QTD_BUFERR ? 1 : 0, 1696 s & EHCI_QTD_BABBLE ? 1 : 0); 1697 USBHIST_LOGN(ehcidebug, 10, 1698 "xacterr=%d missed=%d split =%d ping =%d", 1699 s & EHCI_QTD_XACTERR ? 1 : 0, 1700 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1701 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1702 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1703 USBHIST_LOGN(ehcidebug, 10, 1704 "buffer[0] = %#x buffer[1] = %#x " 1705 "buffer[2] = %#x buffer[3] = %#x", 1706 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1707 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1708 USBHIST_LOGN(ehcidebug, 10, 1709 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1710 } 1711 1712 Static void 1713 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1714 { 1715 #ifdef USBHIST 1716 ehci_qh_t *qh = &sqh->qh; 1717 ehci_link_t link; 1718 #endif 1719 uint32_t endp, endphub; 1720 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1721 1722 usb_syncmem(&sqh->dma, sqh->offs, 1723 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1724 1725 USBHIST_LOGN(ehcidebug, 10, 1726 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1727 link = le32toh(qh->qh_link); 1728 ehci_dump_link(link, true); 1729 1730 endp = le32toh(qh->qh_endp); 1731 USBHIST_LOGN(ehcidebug, 10, 1732 " endp = %#x", endp, 0, 0, 0); 1733 USBHIST_LOGN(ehcidebug, 10, 1734 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1735 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1736 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1737 USBHIST_LOGN(ehcidebug, 10, 1738 " dtc = %d hrecl = %d", 1739 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1740 USBHIST_LOGN(ehcidebug, 10, 1741 " ctl = %d nrl = %d mpl = %#x(%d)", 1742 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1743 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1744 1745 endphub = le32toh(qh->qh_endphub); 1746 USBHIST_LOGN(ehcidebug, 10, 1747 " endphub = %#x", endphub, 0, 0, 0); 1748 USBHIST_LOGN(ehcidebug, 10, 1749 " smask = 0x%02x cmask = 0x%02x", 1750 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1751 USBHIST_LOGN(ehcidebug, 10, 1752 " huba = 0x%02x port = %d mult = %d", 1753 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1754 EHCI_QH_GET_MULT(endphub), 0); 1755 1756 link = le32toh(qh->qh_curqtd); 1757 ehci_dump_link(link, false); 1758 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1759 ehci_dump_qtd(&qh->qh_qtd); 1760 1761 usb_syncmem(&sqh->dma, sqh->offs, 1762 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1763 } 1764 1765 Static void 1766 ehci_dump_itd(struct ehci_soft_itd *itd) 1767 { 1768 ehci_isoc_trans_t t; 1769 ehci_isoc_bufr_ptr_t b, b2, b3; 1770 int i; 1771 1772 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1773 1774 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1775 0, 0); 1776 1777 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1778 t = le32toh(itd->itd.itd_ctl[i]); 1779 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1780 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1781 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1782 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1783 EHCI_ITD_GET_OFFS(t), 0); 1784 } 1785 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1786 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1787 USBHIST_LOG(ehcidebug, " %x", 1788 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1789 1790 b = le32toh(itd->itd.itd_bufr[0]); 1791 b2 = le32toh(itd->itd.itd_bufr[1]); 1792 b3 = le32toh(itd->itd.itd_bufr[2]); 1793 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1794 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1795 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1796 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1797 } 1798 1799 Static void 1800 ehci_dump_sitd(struct ehci_soft_itd *itd) 1801 { 1802 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1803 1804 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1805 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1806 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1807 itd->xfer_next, itd->physaddr, itd->slot, 0); 1808 } 1809 1810 Static void 1811 ehci_dump_exfer(struct ehci_xfer *ex) 1812 { 1813 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1814 1815 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1816 ex, ex->sqtdstart, ex->sqtdend, 0); 1817 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1818 ex->itdstart, ex->itdend, ex->isdone, 0); 1819 } 1820 #endif 1821 1822 Static usbd_status 1823 ehci_open(usbd_pipe_handle pipe) 1824 { 1825 usbd_device_handle dev = pipe->up_dev; 1826 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1827 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1828 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1829 uint8_t addr = dev->ud_addr; 1830 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1831 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1832 ehci_soft_qh_t *sqh; 1833 usbd_status err; 1834 int ival, speed, naks; 1835 int hshubaddr, hshubport; 1836 1837 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1838 1839 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1840 pipe, addr, ed->bEndpointAddress, rhaddr); 1841 1842 if (dev->ud_myhsport) { 1843 /* 1844 * When directly attached FS/LS device while doing embedded 1845 * transaction translations and we are the hub, set the hub 1846 * address to 0 (us). 1847 */ 1848 if (!(sc->sc_flags & EHCIF_ETTF) 1849 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1850 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1851 } else { 1852 hshubaddr = 0; 1853 } 1854 hshubport = dev->ud_myhsport->up_portno; 1855 } else { 1856 hshubaddr = 0; 1857 hshubport = 0; 1858 } 1859 1860 if (sc->sc_dying) 1861 return USBD_IOERROR; 1862 1863 /* toggle state needed for bulk endpoints */ 1864 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1865 1866 if (addr == rhaddr) { 1867 switch (ed->bEndpointAddress) { 1868 case USB_CONTROL_ENDPOINT: 1869 pipe->up_methods = &roothub_ctrl_methods; 1870 break; 1871 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1872 pipe->up_methods = &ehci_root_intr_methods; 1873 break; 1874 default: 1875 USBHIST_LOG(ehcidebug, 1876 "bad bEndpointAddress 0x%02x", 1877 ed->bEndpointAddress, 0, 0, 0); 1878 return USBD_INVAL; 1879 } 1880 return USBD_NORMAL_COMPLETION; 1881 } 1882 1883 /* XXX All this stuff is only valid for async. */ 1884 switch (dev->ud_speed) { 1885 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1886 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1887 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1888 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1889 } 1890 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1891 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1892 hshubaddr, hshubport, 0, 0); 1893 return USBD_INVAL; 1894 } 1895 1896 /* 1897 * For interrupt transfer, nak throttling must be disabled, but for 1898 * the other transfer type, nak throttling should be enabled from the 1899 * viewpoint that avoids the memory thrashing. 1900 */ 1901 naks = (xfertype == UE_INTERRUPT) ? 0 1902 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1903 1904 /* Allocate sqh for everything, save isoc xfers */ 1905 if (xfertype != UE_ISOCHRONOUS) { 1906 sqh = ehci_alloc_sqh(sc); 1907 if (sqh == NULL) 1908 return USBD_NOMEM; 1909 /* qh_link filled when the QH is added */ 1910 sqh->qh.qh_endp = htole32( 1911 EHCI_QH_SET_ADDR(addr) | 1912 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1913 EHCI_QH_SET_EPS(speed) | 1914 EHCI_QH_DTC | 1915 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1916 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1917 EHCI_QH_CTL : 0) | 1918 EHCI_QH_SET_NRL(naks) 1919 ); 1920 sqh->qh.qh_endphub = htole32( 1921 EHCI_QH_SET_MULT(1) | 1922 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1923 ); 1924 if (speed != EHCI_QH_SPEED_HIGH) 1925 sqh->qh.qh_endphub |= htole32( 1926 EHCI_QH_SET_PORT(hshubport) | 1927 EHCI_QH_SET_HUBA(hshubaddr) | 1928 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1929 ); 1930 sqh->qh.qh_curqtd = EHCI_NULL; 1931 /* Fill the overlay qTD */ 1932 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1933 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1934 sqh->qh.qh_qtd.qtd_status = htole32(0); 1935 1936 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1937 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1938 epipe->sqh = sqh; 1939 } else { 1940 sqh = NULL; 1941 } /*xfertype == UE_ISOC*/ 1942 1943 switch (xfertype) { 1944 case UE_CONTROL: 1945 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1946 0, &epipe->u.ctl.reqdma); 1947 #ifdef EHCI_DEBUG 1948 if (err) 1949 printf("ehci_open: usb_allocmem()=%d\n", err); 1950 #endif 1951 if (err) 1952 goto bad; 1953 pipe->up_methods = &ehci_device_ctrl_methods; 1954 mutex_enter(&sc->sc_lock); 1955 ehci_add_qh(sc, sqh, sc->sc_async_head); 1956 mutex_exit(&sc->sc_lock); 1957 break; 1958 case UE_BULK: 1959 pipe->up_methods = &ehci_device_bulk_methods; 1960 mutex_enter(&sc->sc_lock); 1961 ehci_add_qh(sc, sqh, sc->sc_async_head); 1962 mutex_exit(&sc->sc_lock); 1963 break; 1964 case UE_INTERRUPT: 1965 pipe->up_methods = &ehci_device_intr_methods; 1966 ival = pipe->up_interval; 1967 if (ival == USBD_DEFAULT_INTERVAL) { 1968 if (speed == EHCI_QH_SPEED_HIGH) { 1969 if (ed->bInterval > 16) { 1970 /* 1971 * illegal with high-speed, but there 1972 * were documentation bugs in the spec, 1973 * so be generous 1974 */ 1975 ival = 256; 1976 } else 1977 ival = (1 << (ed->bInterval - 1)) / 8; 1978 } else 1979 ival = ed->bInterval; 1980 } 1981 err = ehci_device_setintr(sc, sqh, ival); 1982 if (err) 1983 goto bad; 1984 break; 1985 case UE_ISOCHRONOUS: 1986 if (speed == EHCI_QH_SPEED_HIGH) 1987 pipe->up_methods = &ehci_device_isoc_methods; 1988 else 1989 pipe->up_methods = &ehci_device_fs_isoc_methods; 1990 if (ed->bInterval == 0 || ed->bInterval > 16) { 1991 printf("ehci: opening pipe with invalid bInterval\n"); 1992 err = USBD_INVAL; 1993 goto bad; 1994 } 1995 if (UGETW(ed->wMaxPacketSize) == 0) { 1996 printf("ehci: zero length endpoint open request\n"); 1997 err = USBD_INVAL; 1998 goto bad; 1999 } 2000 epipe->u.isoc.next_frame = 0; 2001 epipe->u.isoc.cur_xfers = 0; 2002 break; 2003 default: 2004 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2005 err = USBD_INVAL; 2006 goto bad; 2007 } 2008 return USBD_NORMAL_COMPLETION; 2009 2010 bad: 2011 if (sqh != NULL) 2012 ehci_free_sqh(sc, sqh); 2013 return err; 2014 } 2015 2016 /* 2017 * Add an ED to the schedule. Called with USB lock held. 2018 */ 2019 Static void 2020 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2021 { 2022 2023 KASSERT(mutex_owned(&sc->sc_lock)); 2024 2025 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2026 2027 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2028 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2029 2030 sqh->next = head->next; 2031 sqh->qh.qh_link = head->qh.qh_link; 2032 2033 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2034 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2035 2036 head->next = sqh; 2037 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2038 2039 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2040 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2041 2042 #ifdef EHCI_DEBUG 2043 ehci_dump_sqh(sqh); 2044 #endif 2045 } 2046 2047 /* 2048 * Remove an ED from the schedule. Called with USB lock held. 2049 */ 2050 Static void 2051 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2052 { 2053 ehci_soft_qh_t *p; 2054 2055 KASSERT(mutex_owned(&sc->sc_lock)); 2056 2057 /* XXX */ 2058 for (p = head; p != NULL && p->next != sqh; p = p->next) 2059 ; 2060 if (p == NULL) 2061 panic("ehci_rem_qh: ED not found"); 2062 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2063 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2064 p->next = sqh->next; 2065 p->qh.qh_link = sqh->qh.qh_link; 2066 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2067 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2068 2069 ehci_sync_hc(sc); 2070 } 2071 2072 Static void 2073 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2074 { 2075 int i; 2076 uint32_t status; 2077 2078 /* Save toggle bit and ping status. */ 2079 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2080 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2081 status = sqh->qh.qh_qtd.qtd_status & 2082 htole32(EHCI_QTD_TOGGLE_MASK | 2083 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2084 /* Set HALTED to make hw leave it alone. */ 2085 sqh->qh.qh_qtd.qtd_status = 2086 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2087 usb_syncmem(&sqh->dma, 2088 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2089 sizeof(sqh->qh.qh_qtd.qtd_status), 2090 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2091 sqh->qh.qh_curqtd = 0; 2092 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2093 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2094 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2095 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2096 sqh->sqtd = sqtd; 2097 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2098 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2099 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2100 sqh->qh.qh_qtd.qtd_status = status; 2101 usb_syncmem(&sqh->dma, 2102 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2103 sizeof(sqh->qh.qh_qtd.qtd_status), 2104 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2105 } 2106 2107 /* 2108 * Ensure that the HC has released all references to the QH. We do this 2109 * by asking for a Async Advance Doorbell interrupt and then we wait for 2110 * the interrupt. 2111 * To make this easier we first obtain exclusive use of the doorbell. 2112 */ 2113 Static void 2114 ehci_sync_hc(ehci_softc_t *sc) 2115 { 2116 int error __diagused; 2117 2118 KASSERT(mutex_owned(&sc->sc_lock)); 2119 2120 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2121 2122 if (sc->sc_dying) { 2123 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2124 return; 2125 } 2126 /* ask for doorbell */ 2127 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2128 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2129 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2130 2131 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2132 2133 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2134 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2135 #ifdef DIAGNOSTIC 2136 if (error) 2137 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2138 #endif 2139 } 2140 2141 Static void 2142 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2143 { 2144 struct ehci_soft_itd *itd, *prev; 2145 2146 prev = NULL; 2147 2148 if (exfer->itdstart == NULL || exfer->itdend == NULL) 2149 panic("ehci isoc xfer being freed, but with no itd chain\n"); 2150 2151 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2152 prev = itd->u.frame_list.prev; 2153 /* Unlink itd from hardware chain, or frame array */ 2154 if (prev == NULL) { /* We're at the table head */ 2155 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2156 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2157 usb_syncmem(&sc->sc_fldma, 2158 sizeof(ehci_link_t) * itd->slot, 2159 sizeof(ehci_link_t), 2160 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2161 2162 if (itd->u.frame_list.next != NULL) 2163 itd->u.frame_list.next->u.frame_list.prev = NULL; 2164 } else { 2165 /* XXX this part is untested... */ 2166 prev->itd.itd_next = itd->itd.itd_next; 2167 usb_syncmem(&itd->dma, 2168 itd->offs + offsetof(ehci_itd_t, itd_next), 2169 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2170 2171 prev->u.frame_list.next = itd->u.frame_list.next; 2172 if (itd->u.frame_list.next != NULL) 2173 itd->u.frame_list.next->u.frame_list.prev = prev; 2174 } 2175 } 2176 2177 prev = NULL; 2178 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2179 if (prev != NULL) 2180 ehci_free_itd(sc, prev); 2181 prev = itd; 2182 } 2183 if (prev) 2184 ehci_free_itd(sc, prev); 2185 exfer->itdstart = NULL; 2186 exfer->itdend = NULL; 2187 } 2188 2189 Static void 2190 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2191 { 2192 struct ehci_soft_sitd *sitd, *prev; 2193 2194 prev = NULL; 2195 2196 if (exfer->sitdstart == NULL || exfer->sitdend == NULL) 2197 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2198 2199 for (sitd = exfer->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2200 prev = sitd->u.frame_list.prev; 2201 /* Unlink sitd from hardware chain, or frame array */ 2202 if (prev == NULL) { /* We're at the table head */ 2203 sc->sc_softsitds[sitd->slot] = sitd->u.frame_list.next; 2204 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2205 usb_syncmem(&sc->sc_fldma, 2206 sizeof(ehci_link_t) * sitd->slot, 2207 sizeof(ehci_link_t), 2208 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2209 2210 if (sitd->u.frame_list.next != NULL) 2211 sitd->u.frame_list.next->u.frame_list.prev = NULL; 2212 } else { 2213 /* XXX this part is untested... */ 2214 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2215 usb_syncmem(&sitd->dma, 2216 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2217 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2218 2219 prev->u.frame_list.next = sitd->u.frame_list.next; 2220 if (sitd->u.frame_list.next != NULL) 2221 sitd->u.frame_list.next->u.frame_list.prev = prev; 2222 } 2223 } 2224 2225 prev = NULL; 2226 for (sitd = exfer->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2227 if (prev != NULL) 2228 ehci_free_sitd(sc, prev); 2229 prev = sitd; 2230 } 2231 if (prev) 2232 ehci_free_sitd(sc, prev); 2233 exfer->sitdstart = NULL; 2234 exfer->sitdend = NULL; 2235 } 2236 2237 /***********/ 2238 2239 Static int 2240 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2241 void *buf, int buflen) 2242 { 2243 ehci_softc_t *sc = bus->ub_hcpriv; 2244 usb_hub_descriptor_t hubd; 2245 usb_port_status_t ps; 2246 uint16_t len, value, index; 2247 int l, totlen = 0; 2248 int port, i; 2249 uint32_t v; 2250 2251 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2252 2253 if (sc->sc_dying) 2254 return -1; 2255 2256 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2257 req->bmRequestType, req->bRequest, 0, 0); 2258 2259 len = UGETW(req->wLength); 2260 value = UGETW(req->wValue); 2261 index = UGETW(req->wIndex); 2262 2263 #define C(x,y) ((x) | ((y) << 8)) 2264 switch (C(req->bRequest, req->bmRequestType)) { 2265 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2266 if (len == 0) 2267 break; 2268 switch (value) { 2269 case C(0, UDESC_DEVICE): { 2270 usb_device_descriptor_t devd; 2271 totlen = min(buflen, sizeof(devd)); 2272 memcpy(&devd, buf, totlen); 2273 USETW(devd.idVendor, sc->sc_id_vendor); 2274 memcpy(buf, &devd, totlen); 2275 break; 2276 2277 } 2278 #define sd ((usb_string_descriptor_t *)buf) 2279 case C(1, UDESC_STRING): 2280 /* Vendor */ 2281 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2282 break; 2283 case C(2, UDESC_STRING): 2284 /* Product */ 2285 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2286 break; 2287 #undef sd 2288 default: 2289 /* default from usbroothub */ 2290 return buflen; 2291 } 2292 break; 2293 2294 /* Hub requests */ 2295 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2296 break; 2297 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2298 USBHIST_LOG(ehcidebug, 2299 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2300 0, 0); 2301 if (index < 1 || index > sc->sc_noport) { 2302 return -1; 2303 } 2304 port = EHCI_PORTSC(index); 2305 v = EOREAD4(sc, port); 2306 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2307 v &= ~EHCI_PS_CLEAR; 2308 switch (value) { 2309 case UHF_PORT_ENABLE: 2310 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2311 break; 2312 case UHF_PORT_SUSPEND: 2313 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2314 break; 2315 v &= ~EHCI_PS_SUSP; 2316 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2317 /* see USB2 spec ch. 7.1.7.7 */ 2318 usb_delay_ms(&sc->sc_bus, 20); 2319 EOWRITE4(sc, port, v); 2320 usb_delay_ms(&sc->sc_bus, 2); 2321 #ifdef DEBUG 2322 v = EOREAD4(sc, port); 2323 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2324 printf("ehci: resume failed: %x\n", v); 2325 #endif 2326 break; 2327 case UHF_PORT_POWER: 2328 if (sc->sc_hasppc) 2329 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2330 break; 2331 case UHF_PORT_TEST: 2332 USBHIST_LOG(ehcidebug, "clear port test " 2333 "%d", index, 0, 0, 0); 2334 break; 2335 case UHF_PORT_INDICATOR: 2336 USBHIST_LOG(ehcidebug, "clear port ind " 2337 "%d", index, 0, 0, 0); 2338 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2339 break; 2340 case UHF_C_PORT_CONNECTION: 2341 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2342 break; 2343 case UHF_C_PORT_ENABLE: 2344 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2345 break; 2346 case UHF_C_PORT_SUSPEND: 2347 /* how? */ 2348 break; 2349 case UHF_C_PORT_OVER_CURRENT: 2350 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2351 break; 2352 case UHF_C_PORT_RESET: 2353 sc->sc_isreset[index] = 0; 2354 break; 2355 default: 2356 return -1; 2357 } 2358 #if 0 2359 switch(value) { 2360 case UHF_C_PORT_CONNECTION: 2361 case UHF_C_PORT_ENABLE: 2362 case UHF_C_PORT_SUSPEND: 2363 case UHF_C_PORT_OVER_CURRENT: 2364 case UHF_C_PORT_RESET: 2365 default: 2366 break; 2367 } 2368 #endif 2369 break; 2370 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2371 if (len == 0) 2372 break; 2373 if ((value & 0xff) != 0) { 2374 return -1; 2375 } 2376 totlen = min(buflen, sizeof(hubd)); 2377 memcpy(&hubd, buf, totlen); 2378 hubd.bNbrPorts = sc->sc_noport; 2379 v = EOREAD4(sc, EHCI_HCSPARAMS); 2380 USETW(hubd.wHubCharacteristics, 2381 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2382 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2383 ? UHD_PORT_IND : 0); 2384 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2385 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2386 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2387 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2388 totlen = min(totlen, hubd.bDescLength); 2389 memcpy(buf, &hubd, totlen); 2390 break; 2391 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2392 if (len != 4) { 2393 return -1; 2394 } 2395 memset(buf, 0, len); /* ? XXX */ 2396 totlen = len; 2397 break; 2398 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2399 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2400 if (index < 1 || index > sc->sc_noport) { 2401 return -1; 2402 } 2403 if (len != 4) { 2404 return -1; 2405 } 2406 v = EOREAD4(sc, EHCI_PORTSC(index)); 2407 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2408 2409 i = UPS_HIGH_SPEED; 2410 if (sc->sc_flags & EHCIF_ETTF) { 2411 /* 2412 * If we are doing embedded transaction translation, 2413 * then directly attached LS/FS devices are reset by 2414 * the EHCI controller itself. PSPD is encoded 2415 * the same way as in USBSTATUS. 2416 */ 2417 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2418 } 2419 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2420 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2421 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2422 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2423 if (v & EHCI_PS_PR) i |= UPS_RESET; 2424 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2425 if (sc->sc_vendor_port_status) 2426 i = sc->sc_vendor_port_status(sc, v, i); 2427 USETW(ps.wPortStatus, i); 2428 i = 0; 2429 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2430 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2431 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2432 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2433 USETW(ps.wPortChange, i); 2434 totlen = min(len, sizeof(ps)); 2435 memcpy(buf, &ps, totlen); 2436 break; 2437 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2438 return -1; 2439 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2440 break; 2441 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2442 if (index < 1 || index > sc->sc_noport) { 2443 return -1; 2444 } 2445 port = EHCI_PORTSC(index); 2446 v = EOREAD4(sc, port); 2447 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2448 v &= ~EHCI_PS_CLEAR; 2449 switch(value) { 2450 case UHF_PORT_ENABLE: 2451 EOWRITE4(sc, port, v | EHCI_PS_PE); 2452 break; 2453 case UHF_PORT_SUSPEND: 2454 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2455 break; 2456 case UHF_PORT_RESET: 2457 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2458 if (EHCI_PS_IS_LOWSPEED(v) 2459 && sc->sc_ncomp > 0 2460 && !(sc->sc_flags & EHCIF_ETTF)) { 2461 /* 2462 * Low speed device on non-ETTF controller or 2463 * unaccompanied controller, give up ownership. 2464 */ 2465 ehci_disown(sc, index, 1); 2466 break; 2467 } 2468 /* Start reset sequence. */ 2469 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2470 EOWRITE4(sc, port, v | EHCI_PS_PR); 2471 /* Wait for reset to complete. */ 2472 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2473 if (sc->sc_dying) { 2474 return -1; 2475 } 2476 /* 2477 * An embedded transaction translator will automatically 2478 * terminate the reset sequence so there's no need to 2479 * it. 2480 */ 2481 v = EOREAD4(sc, port); 2482 if (v & EHCI_PS_PR) { 2483 /* Terminate reset sequence. */ 2484 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2485 /* Wait for HC to complete reset. */ 2486 usb_delay_ms(&sc->sc_bus, 2487 EHCI_PORT_RESET_COMPLETE); 2488 if (sc->sc_dying) { 2489 return -1; 2490 } 2491 } 2492 2493 v = EOREAD4(sc, port); 2494 USBHIST_LOG(ehcidebug, 2495 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2496 if (v & EHCI_PS_PR) { 2497 printf("%s: port reset timeout\n", 2498 device_xname(sc->sc_dev)); 2499 return USBD_TIMEOUT; 2500 } 2501 if (!(v & EHCI_PS_PE)) { 2502 /* Not a high speed device, give up ownership.*/ 2503 ehci_disown(sc, index, 0); 2504 break; 2505 } 2506 sc->sc_isreset[index] = 1; 2507 USBHIST_LOG(ehcidebug, 2508 "ehci port %d reset, status = 0x%08x", index, v, 0, 2509 0); 2510 break; 2511 case UHF_PORT_POWER: 2512 USBHIST_LOG(ehcidebug, 2513 "set port power %d (has PPC = %d)", index, 2514 sc->sc_hasppc, 0, 0); 2515 if (sc->sc_hasppc) 2516 EOWRITE4(sc, port, v | EHCI_PS_PP); 2517 break; 2518 case UHF_PORT_TEST: 2519 USBHIST_LOG(ehcidebug, "set port test %d", 2520 index, 0, 0, 0); 2521 break; 2522 case UHF_PORT_INDICATOR: 2523 USBHIST_LOG(ehcidebug, "set port ind %d", 2524 index, 0, 0, 0); 2525 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2526 break; 2527 default: 2528 return -1; 2529 } 2530 break; 2531 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2532 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2533 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2534 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2535 break; 2536 default: 2537 /* default from usbroothub */ 2538 return buflen; 2539 } 2540 2541 return totlen; 2542 } 2543 2544 Static void 2545 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2546 { 2547 int port; 2548 uint32_t v; 2549 2550 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2551 2552 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2553 #ifdef DIAGNOSTIC 2554 if (sc->sc_npcomp != 0) { 2555 int i = (index-1) / sc->sc_npcomp; 2556 if (i >= sc->sc_ncomp) 2557 printf("%s: strange port\n", 2558 device_xname(sc->sc_dev)); 2559 else 2560 printf("%s: handing over %s speed device on " 2561 "port %d to %s\n", 2562 device_xname(sc->sc_dev), 2563 lowspeed ? "low" : "full", 2564 index, device_xname(sc->sc_comps[i])); 2565 } else { 2566 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2567 } 2568 #endif 2569 port = EHCI_PORTSC(index); 2570 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2571 EOWRITE4(sc, port, v | EHCI_PS_PO); 2572 } 2573 2574 Static usbd_status 2575 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2576 { 2577 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2578 usbd_status err; 2579 2580 /* Insert last in queue. */ 2581 mutex_enter(&sc->sc_lock); 2582 err = usb_insert_transfer(xfer); 2583 mutex_exit(&sc->sc_lock); 2584 if (err) 2585 return err; 2586 2587 /* Pipe isn't running, start first */ 2588 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2589 } 2590 2591 Static usbd_status 2592 ehci_root_intr_start(usbd_xfer_handle xfer) 2593 { 2594 usbd_pipe_handle pipe = xfer->ux_pipe; 2595 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2596 2597 if (sc->sc_dying) 2598 return USBD_IOERROR; 2599 2600 mutex_enter(&sc->sc_lock); 2601 sc->sc_intrxfer = xfer; 2602 mutex_exit(&sc->sc_lock); 2603 2604 return USBD_IN_PROGRESS; 2605 } 2606 2607 /* Abort a root interrupt request. */ 2608 Static void 2609 ehci_root_intr_abort(usbd_xfer_handle xfer) 2610 { 2611 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2612 2613 KASSERT(mutex_owned(&sc->sc_lock)); 2614 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2615 2616 sc->sc_intrxfer = NULL; 2617 2618 xfer->ux_status = USBD_CANCELLED; 2619 usb_transfer_complete(xfer); 2620 } 2621 2622 /* Close the root pipe. */ 2623 Static void 2624 ehci_root_intr_close(usbd_pipe_handle pipe) 2625 { 2626 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2627 2628 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2629 2630 KASSERT(mutex_owned(&sc->sc_lock)); 2631 2632 sc->sc_intrxfer = NULL; 2633 } 2634 2635 Static void 2636 ehci_root_intr_done(usbd_xfer_handle xfer) 2637 { 2638 xfer->ux_hcpriv = NULL; 2639 } 2640 2641 /************************/ 2642 2643 Static ehci_soft_qh_t * 2644 ehci_alloc_sqh(ehci_softc_t *sc) 2645 { 2646 ehci_soft_qh_t *sqh; 2647 usbd_status err; 2648 int i, offs; 2649 usb_dma_t dma; 2650 2651 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2652 2653 if (sc->sc_freeqhs == NULL) { 2654 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2655 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2656 EHCI_PAGE_SIZE, &dma); 2657 #ifdef EHCI_DEBUG 2658 if (err) 2659 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2660 #endif 2661 if (err) 2662 return NULL; 2663 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2664 offs = i * EHCI_SQH_SIZE; 2665 sqh = KERNADDR(&dma, offs); 2666 sqh->physaddr = DMAADDR(&dma, offs); 2667 sqh->dma = dma; 2668 sqh->offs = offs; 2669 sqh->next = sc->sc_freeqhs; 2670 sc->sc_freeqhs = sqh; 2671 } 2672 } 2673 sqh = sc->sc_freeqhs; 2674 sc->sc_freeqhs = sqh->next; 2675 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2676 sqh->next = NULL; 2677 return sqh; 2678 } 2679 2680 Static void 2681 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2682 { 2683 sqh->next = sc->sc_freeqhs; 2684 sc->sc_freeqhs = sqh; 2685 } 2686 2687 Static ehci_soft_qtd_t * 2688 ehci_alloc_sqtd(ehci_softc_t *sc) 2689 { 2690 ehci_soft_qtd_t *sqtd = NULL; 2691 usbd_status err; 2692 int i, offs; 2693 usb_dma_t dma; 2694 2695 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2696 2697 if (sc->sc_freeqtds == NULL) { 2698 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2699 2700 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2701 EHCI_PAGE_SIZE, &dma); 2702 #ifdef EHCI_DEBUG 2703 if (err) 2704 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2705 #endif 2706 if (err) 2707 goto done; 2708 2709 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2710 offs = i * EHCI_SQTD_SIZE; 2711 sqtd = KERNADDR(&dma, offs); 2712 sqtd->physaddr = DMAADDR(&dma, offs); 2713 sqtd->dma = dma; 2714 sqtd->offs = offs; 2715 2716 sqtd->nextqtd = sc->sc_freeqtds; 2717 sc->sc_freeqtds = sqtd; 2718 } 2719 } 2720 2721 sqtd = sc->sc_freeqtds; 2722 sc->sc_freeqtds = sqtd->nextqtd; 2723 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2724 sqtd->nextqtd = NULL; 2725 sqtd->xfer = NULL; 2726 2727 done: 2728 return sqtd; 2729 } 2730 2731 Static void 2732 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2733 { 2734 2735 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2736 2737 sqtd->nextqtd = sc->sc_freeqtds; 2738 sc->sc_freeqtds = sqtd; 2739 } 2740 2741 Static usbd_status 2742 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2743 int alen, int rd, usbd_xfer_handle xfer, 2744 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2745 { 2746 ehci_soft_qtd_t *next, *cur; 2747 ehci_physaddr_t nextphys; 2748 uint32_t qtdstatus; 2749 int len, curlen, mps; 2750 int i, tog; 2751 int pages, pageoffs; 2752 bus_size_t curoffs; 2753 vaddr_t va, va_offs; 2754 usb_dma_t *dma = &xfer->ux_dmabuf; 2755 uint16_t flags = xfer->ux_flags; 2756 paddr_t a; 2757 2758 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2759 2760 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2761 2762 len = alen; 2763 qtdstatus = EHCI_QTD_ACTIVE | 2764 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2765 EHCI_QTD_SET_CERR(3) 2766 /* IOC set below */ 2767 /* BYTES set below */ 2768 ; 2769 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 2770 tog = epipe->nexttoggle; 2771 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2772 2773 cur = ehci_alloc_sqtd(sc); 2774 *sp = cur; 2775 if (cur == NULL) 2776 goto nomem; 2777 2778 usb_syncmem(dma, 0, alen, 2779 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2780 curoffs = 0; 2781 for (;;) { 2782 /* The EHCI hardware can handle at most 5 pages. */ 2783 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2784 va_offs = EHCI_PAGE_OFFSET(va_offs); 2785 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 2786 /* we can handle it in this QTD */ 2787 curlen = len - curoffs; 2788 } else { 2789 /* must use multiple TDs, fill as much as possible. */ 2790 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 2791 2792 /* the length must be a multiple of the max size */ 2793 curlen -= curlen % mps; 2794 USBHIST_LOG(ehcidebug, "multiple QTDs, " 2795 "curlen=%d", curlen, 0, 0, 0); 2796 #ifdef DIAGNOSTIC 2797 if (curlen == 0) 2798 panic("ehci_alloc_sqtd_chain: curlen == 0"); 2799 #endif 2800 } 2801 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 2802 len, curlen, (size_t)curoffs, 0); 2803 2804 /* 2805 * Allocate another transfer if there's more data left, 2806 * or if force last short transfer flag is set and we're 2807 * allocating a multiple of the max packet size. 2808 */ 2809 2810 if (curoffs + curlen != len || 2811 ((curlen % mps) == 0 && !rd && curlen != 0 && 2812 (flags & USBD_FORCE_SHORT_XFER))) { 2813 next = ehci_alloc_sqtd(sc); 2814 if (next == NULL) 2815 goto nomem; 2816 nextphys = htole32(next->physaddr); 2817 } else { 2818 next = NULL; 2819 nextphys = EHCI_NULL; 2820 } 2821 2822 /* Find number of pages we'll be using, insert dma addresses */ 2823 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2824 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2825 pageoffs = EHCI_PAGE(curoffs); 2826 for (i = 0; i < pages; i++) { 2827 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2828 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2829 /* Cast up to avoid compiler warnings */ 2830 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2831 } 2832 2833 /* First buffer pointer requires a page offset to start at */ 2834 va = (vaddr_t)KERNADDR(dma, curoffs); 2835 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2836 2837 cur->nextqtd = next; 2838 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2839 cur->qtd.qtd_status = 2840 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2841 cur->xfer = xfer; 2842 cur->len = curlen; 2843 2844 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2845 (size_t)curoffs, (size_t)(curoffs + curlen), 0, 0); 2846 2847 /* adjust the toggle based on the number of packets in this 2848 qtd */ 2849 if (((curlen + mps - 1) / mps) & 1) { 2850 tog ^= 1; 2851 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2852 } 2853 if (next == NULL) 2854 break; 2855 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2856 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2857 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2858 if (len) 2859 curoffs += curlen; 2860 cur = next; 2861 } 2862 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2863 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2864 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2865 *ep = cur; 2866 epipe->nexttoggle = tog; 2867 2868 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 2869 *sp, *ep, 0, 0); 2870 2871 return USBD_NORMAL_COMPLETION; 2872 2873 nomem: 2874 /* XXX free chain */ 2875 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2876 return USBD_NOMEM; 2877 } 2878 2879 Static void 2880 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2881 ehci_soft_qtd_t *sqtdend) 2882 { 2883 ehci_soft_qtd_t *p; 2884 int i; 2885 2886 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2887 2888 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 2889 sqtd, sqtdend, 0, 0); 2890 2891 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2892 p = sqtd->nextqtd; 2893 ehci_free_sqtd(sc, sqtd); 2894 } 2895 } 2896 2897 Static ehci_soft_itd_t * 2898 ehci_alloc_itd(ehci_softc_t *sc) 2899 { 2900 struct ehci_soft_itd *itd, *freeitd; 2901 usbd_status err; 2902 int i, offs, frindex, previndex; 2903 usb_dma_t dma; 2904 2905 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2906 2907 mutex_enter(&sc->sc_lock); 2908 2909 /* Find an itd that wasn't freed this frame or last frame. This can 2910 * discard itds that were freed before frindex wrapped around 2911 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2912 * interrupt and fiddling with list when that happens */ 2913 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2914 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2915 2916 freeitd = NULL; 2917 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2918 if (itd == NULL) 2919 break; 2920 if (itd->slot != frindex && itd->slot != previndex) { 2921 freeitd = itd; 2922 break; 2923 } 2924 } 2925 2926 if (freeitd == NULL) { 2927 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2928 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2929 EHCI_PAGE_SIZE, &dma); 2930 2931 if (err) { 2932 USBHIST_LOG(ehcidebug, 2933 "alloc returned %d", err, 0, 0, 0); 2934 mutex_exit(&sc->sc_lock); 2935 return NULL; 2936 } 2937 2938 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2939 offs = i * EHCI_ITD_SIZE; 2940 itd = KERNADDR(&dma, offs); 2941 itd->physaddr = DMAADDR(&dma, offs); 2942 itd->dma = dma; 2943 itd->offs = offs; 2944 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2945 } 2946 freeitd = LIST_FIRST(&sc->sc_freeitds); 2947 } 2948 2949 itd = freeitd; 2950 LIST_REMOVE(itd, u.free_list); 2951 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2952 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2953 sizeof(itd->itd.itd_next), 2954 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2955 2956 itd->u.frame_list.next = NULL; 2957 itd->u.frame_list.prev = NULL; 2958 itd->xfer_next = NULL; 2959 itd->slot = 0; 2960 2961 mutex_exit(&sc->sc_lock); 2962 2963 return itd; 2964 } 2965 2966 Static ehci_soft_sitd_t * 2967 ehci_alloc_sitd(ehci_softc_t *sc) 2968 { 2969 struct ehci_soft_sitd *sitd, *freesitd; 2970 usbd_status err; 2971 int i, offs, frindex, previndex; 2972 usb_dma_t dma; 2973 2974 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2975 2976 mutex_enter(&sc->sc_lock); 2977 2978 /* Find an sitd that wasn't freed this frame or last frame. This can 2979 * discard sitds that were freed before frindex wrapped around 2980 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2981 * interrupt and fiddling with list when that happens */ 2982 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2983 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2984 2985 freesitd = NULL; 2986 LIST_FOREACH(sitd, &sc->sc_freesitds, u.free_list) { 2987 if (sitd == NULL) 2988 break; 2989 if (sitd->slot != frindex && sitd->slot != previndex) { 2990 freesitd = sitd; 2991 break; 2992 } 2993 } 2994 2995 if (freesitd == NULL) { 2996 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2997 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 2998 EHCI_PAGE_SIZE, &dma); 2999 3000 if (err) { 3001 USBHIST_LOG(ehcidebug, 3002 "alloc returned %d", err, 0, 0, 0); 3003 mutex_exit(&sc->sc_lock); 3004 return NULL; 3005 } 3006 3007 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3008 offs = i * EHCI_SITD_SIZE; 3009 sitd = KERNADDR(&dma, offs); 3010 sitd->physaddr = DMAADDR(&dma, offs); 3011 sitd->dma = dma; 3012 sitd->offs = offs; 3013 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3014 } 3015 freesitd = LIST_FIRST(&sc->sc_freesitds); 3016 } 3017 3018 sitd = freesitd; 3019 LIST_REMOVE(sitd, u.free_list); 3020 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3021 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3022 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3023 BUS_DMASYNC_PREREAD); 3024 3025 sitd->u.frame_list.next = NULL; 3026 sitd->u.frame_list.prev = NULL; 3027 sitd->xfer_next = NULL; 3028 sitd->slot = 0; 3029 3030 mutex_exit(&sc->sc_lock); 3031 3032 return sitd; 3033 } 3034 3035 Static void 3036 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3037 { 3038 3039 KASSERT(mutex_owned(&sc->sc_lock)); 3040 3041 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3042 } 3043 3044 Static void 3045 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3046 { 3047 3048 KASSERT(mutex_owned(&sc->sc_lock)); 3049 3050 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3051 } 3052 3053 /****************/ 3054 3055 /* 3056 * Close a reqular pipe. 3057 * Assumes that there are no pending transactions. 3058 */ 3059 Static void 3060 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3061 { 3062 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3063 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3064 ehci_soft_qh_t *sqh = epipe->sqh; 3065 3066 KASSERT(mutex_owned(&sc->sc_lock)); 3067 3068 ehci_rem_qh(sc, sqh, head); 3069 ehci_free_sqh(sc, epipe->sqh); 3070 } 3071 3072 /* 3073 * Abort a device request. 3074 * If this routine is called at splusb() it guarantees that the request 3075 * will be removed from the hardware scheduling and that the callback 3076 * for it will be called with USBD_CANCELLED status. 3077 * It's impossible to guarantee that the requested transfer will not 3078 * have happened since the hardware runs concurrently. 3079 * If the transaction has already happened we rely on the ordinary 3080 * interrupt processing to process it. 3081 * XXX This is most probably wrong. 3082 * XXXMRG this doesn't make sense anymore. 3083 */ 3084 Static void 3085 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3086 { 3087 #define exfer EXFER(xfer) 3088 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3089 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3090 ehci_soft_qh_t *sqh = epipe->sqh; 3091 ehci_soft_qtd_t *sqtd; 3092 ehci_physaddr_t cur; 3093 uint32_t qhstatus; 3094 int hit; 3095 int wake; 3096 3097 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3098 3099 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3100 3101 KASSERT(mutex_owned(&sc->sc_lock)); 3102 ASSERT_SLEEPABLE(); 3103 3104 if (sc->sc_dying) { 3105 /* If we're dying, just do the software part. */ 3106 xfer->ux_status = status; /* make software ignore it */ 3107 callout_stop(&xfer->ux_callout); 3108 usb_transfer_complete(xfer); 3109 return; 3110 } 3111 3112 /* 3113 * If an abort is already in progress then just wait for it to 3114 * complete and return. 3115 */ 3116 if (xfer->ux_hcflags & UXFER_ABORTING) { 3117 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3118 #ifdef DIAGNOSTIC 3119 if (status == USBD_TIMEOUT) 3120 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3121 #endif 3122 /* Override the status which might be USBD_TIMEOUT. */ 3123 xfer->ux_status = status; 3124 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3125 0, 0, 0, 0); 3126 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3127 while (xfer->ux_hcflags & UXFER_ABORTING) 3128 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3129 return; 3130 } 3131 xfer->ux_hcflags |= UXFER_ABORTING; 3132 3133 /* 3134 * Step 1: Make interrupt routine and hardware ignore xfer. 3135 */ 3136 xfer->ux_status = status; /* make software ignore it */ 3137 callout_stop(&xfer->ux_callout); 3138 3139 usb_syncmem(&sqh->dma, 3140 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3141 sizeof(sqh->qh.qh_qtd.qtd_status), 3142 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3143 qhstatus = sqh->qh.qh_qtd.qtd_status; 3144 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3145 usb_syncmem(&sqh->dma, 3146 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3147 sizeof(sqh->qh.qh_qtd.qtd_status), 3148 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3149 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3150 usb_syncmem(&sqtd->dma, 3151 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3152 sizeof(sqtd->qtd.qtd_status), 3153 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3154 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3155 usb_syncmem(&sqtd->dma, 3156 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3157 sizeof(sqtd->qtd.qtd_status), 3158 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3159 if (sqtd == exfer->sqtdend) 3160 break; 3161 } 3162 3163 /* 3164 * Step 2: Wait until we know hardware has finished any possible 3165 * use of the xfer. Also make sure the soft interrupt routine 3166 * has run. 3167 */ 3168 ehci_sync_hc(sc); 3169 sc->sc_softwake = 1; 3170 usb_schedsoftintr(&sc->sc_bus); 3171 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3172 3173 /* 3174 * Step 3: Remove any vestiges of the xfer from the hardware. 3175 * The complication here is that the hardware may have executed 3176 * beyond the xfer we're trying to abort. So as we're scanning 3177 * the TDs of this xfer we check if the hardware points to 3178 * any of them. 3179 */ 3180 3181 usb_syncmem(&sqh->dma, 3182 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3183 sizeof(sqh->qh.qh_curqtd), 3184 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3185 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3186 hit = 0; 3187 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3188 hit |= cur == sqtd->physaddr; 3189 if (sqtd == exfer->sqtdend) 3190 break; 3191 } 3192 sqtd = sqtd->nextqtd; 3193 /* Zap curqtd register if hardware pointed inside the xfer. */ 3194 if (hit && sqtd != NULL) { 3195 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3196 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3197 usb_syncmem(&sqh->dma, 3198 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3199 sizeof(sqh->qh.qh_curqtd), 3200 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3201 sqh->qh.qh_qtd.qtd_status = qhstatus; 3202 usb_syncmem(&sqh->dma, 3203 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3204 sizeof(sqh->qh.qh_qtd.qtd_status), 3205 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3206 } else { 3207 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3208 } 3209 3210 /* 3211 * Step 4: Execute callback. 3212 */ 3213 #ifdef DIAGNOSTIC 3214 exfer->isdone = 1; 3215 #endif 3216 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3217 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3218 usb_transfer_complete(xfer); 3219 if (wake) { 3220 cv_broadcast(&xfer->ux_hccv); 3221 } 3222 3223 KASSERT(mutex_owned(&sc->sc_lock)); 3224 #undef exfer 3225 } 3226 3227 Static void 3228 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3229 { 3230 ehci_isoc_trans_t trans_status; 3231 struct ehci_pipe *epipe; 3232 struct ehci_xfer *exfer; 3233 ehci_softc_t *sc; 3234 struct ehci_soft_itd *itd; 3235 struct ehci_soft_sitd *sitd; 3236 int i, wake; 3237 3238 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3239 3240 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3241 exfer = EXFER(xfer); 3242 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3243 3244 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3245 3246 KASSERT(mutex_owned(&sc->sc_lock)); 3247 3248 if (sc->sc_dying) { 3249 xfer->ux_status = status; 3250 callout_stop(&xfer->ux_callout); 3251 usb_transfer_complete(xfer); 3252 return; 3253 } 3254 3255 if (xfer->ux_hcflags & UXFER_ABORTING) { 3256 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3257 3258 #ifdef DIAGNOSTIC 3259 if (status == USBD_TIMEOUT) 3260 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3261 #endif 3262 3263 xfer->ux_status = status; 3264 USBHIST_LOG(ehcidebug, 3265 "waiting for abort to finish", 0, 0, 0, 0); 3266 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3267 while (xfer->ux_hcflags & UXFER_ABORTING) 3268 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3269 goto done; 3270 } 3271 xfer->ux_hcflags |= UXFER_ABORTING; 3272 3273 xfer->ux_status = status; 3274 callout_stop(&xfer->ux_callout); 3275 3276 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 3277 usb_syncmem(&itd->dma, 3278 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3279 sizeof(itd->itd.itd_ctl), 3280 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3281 3282 for (i = 0; i < 8; i++) { 3283 trans_status = le32toh(itd->itd.itd_ctl[i]); 3284 trans_status &= ~EHCI_ITD_ACTIVE; 3285 itd->itd.itd_ctl[i] = htole32(trans_status); 3286 } 3287 3288 usb_syncmem(&itd->dma, 3289 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3290 sizeof(itd->itd.itd_ctl), 3291 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3292 } 3293 for (sitd = exfer->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 3294 usb_syncmem(&sitd->dma, 3295 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3296 sizeof(sitd->sitd.sitd_buffer), 3297 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3298 3299 trans_status = le32toh(sitd->sitd.sitd_trans); 3300 trans_status &= ~EHCI_SITD_ACTIVE; 3301 sitd->sitd.sitd_trans = htole32(trans_status); 3302 3303 usb_syncmem(&sitd->dma, 3304 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3305 sizeof(sitd->sitd.sitd_buffer), 3306 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3307 } 3308 3309 sc->sc_softwake = 1; 3310 usb_schedsoftintr(&sc->sc_bus); 3311 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3312 3313 #ifdef DIAGNOSTIC 3314 exfer->isdone = 1; 3315 #endif 3316 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3317 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3318 usb_transfer_complete(xfer); 3319 if (wake) { 3320 cv_broadcast(&xfer->ux_hccv); 3321 } 3322 3323 done: 3324 KASSERT(mutex_owned(&sc->sc_lock)); 3325 return; 3326 } 3327 3328 Static void 3329 ehci_timeout(void *addr) 3330 { 3331 struct ehci_xfer *exfer = addr; 3332 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.ux_pipe; 3333 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3334 3335 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3336 3337 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3338 #ifdef EHCI_DEBUG 3339 if (ehcidebug > 1) 3340 usbd_dump_pipe(exfer->xfer.ux_pipe); 3341 #endif 3342 3343 if (sc->sc_dying) { 3344 mutex_enter(&sc->sc_lock); 3345 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3346 mutex_exit(&sc->sc_lock); 3347 return; 3348 } 3349 3350 /* Execute the abort in a process context. */ 3351 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr, 3352 USB_TASKQ_MPSAFE); 3353 usb_add_task(exfer->xfer.ux_pipe->up_dev, &exfer->abort_task, 3354 USB_TASKQ_HC); 3355 } 3356 3357 Static void 3358 ehci_timeout_task(void *addr) 3359 { 3360 usbd_xfer_handle xfer = addr; 3361 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3362 3363 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3364 3365 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3366 3367 mutex_enter(&sc->sc_lock); 3368 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3369 mutex_exit(&sc->sc_lock); 3370 } 3371 3372 /************************/ 3373 3374 Static usbd_status 3375 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3376 { 3377 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3378 usbd_status err; 3379 3380 /* Insert last in queue. */ 3381 mutex_enter(&sc->sc_lock); 3382 err = usb_insert_transfer(xfer); 3383 mutex_exit(&sc->sc_lock); 3384 if (err) 3385 return err; 3386 3387 /* Pipe isn't running, start first */ 3388 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3389 } 3390 3391 Static usbd_status 3392 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3393 { 3394 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3395 usbd_status err; 3396 3397 if (sc->sc_dying) 3398 return USBD_IOERROR; 3399 3400 #ifdef DIAGNOSTIC 3401 if (!(xfer->ux_rqflags & URQ_REQUEST)) { 3402 /* XXX panic */ 3403 printf("ehci_device_ctrl_transfer: not a request\n"); 3404 return USBD_INVAL; 3405 } 3406 #endif 3407 3408 err = ehci_device_request(xfer); 3409 if (err) { 3410 return err; 3411 } 3412 3413 if (sc->sc_bus.ub_usepolling) 3414 ehci_waitintr(sc, xfer); 3415 3416 return USBD_IN_PROGRESS; 3417 } 3418 3419 Static void 3420 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3421 { 3422 struct ehci_xfer *ex = EXFER(xfer); 3423 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3424 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3425 usb_device_request_t *req = &xfer->ux_request; 3426 int len = UGETW(req->wLength); 3427 int rd = req->bmRequestType & UT_READ; 3428 3429 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3430 3431 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3432 3433 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3434 3435 #ifdef DIAGNOSTIC 3436 if (!(xfer->ux_rqflags & URQ_REQUEST)) { 3437 panic("ehci_ctrl_done: not a request"); 3438 } 3439 #endif 3440 3441 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3442 ehci_del_intr_list(sc, ex); /* remove from active list */ 3443 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3444 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3445 BUS_DMASYNC_POSTWRITE); 3446 if (len) 3447 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3448 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3449 } 3450 3451 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3452 } 3453 3454 /* Abort a device control request. */ 3455 Static void 3456 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3457 { 3458 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3459 3460 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3461 ehci_abort_xfer(xfer, USBD_CANCELLED); 3462 } 3463 3464 /* Close a device control pipe. */ 3465 Static void 3466 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3467 { 3468 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3469 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3470 3471 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3472 3473 KASSERT(mutex_owned(&sc->sc_lock)); 3474 3475 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3476 3477 ehci_close_pipe(pipe, sc->sc_async_head); 3478 } 3479 3480 Static usbd_status 3481 ehci_device_request(usbd_xfer_handle xfer) 3482 { 3483 #define exfer EXFER(xfer) 3484 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3485 usb_device_request_t *req = &xfer->ux_request; 3486 usbd_device_handle dev = epipe->pipe.up_dev; 3487 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3488 ehci_soft_qtd_t *setup, *stat, *next; 3489 ehci_soft_qh_t *sqh; 3490 int isread; 3491 int len; 3492 usbd_status err; 3493 3494 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3495 3496 isread = req->bmRequestType & UT_READ; 3497 len = UGETW(req->wLength); 3498 3499 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3500 "wValue=0x%04x, wIndex=0x%04x", 3501 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3502 UGETW(req->wIndex)); 3503 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3504 len, dev->ud_addr, 3505 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3506 3507 setup = ehci_alloc_sqtd(sc); 3508 if (setup == NULL) { 3509 err = USBD_NOMEM; 3510 goto bad1; 3511 } 3512 stat = ehci_alloc_sqtd(sc); 3513 if (stat == NULL) { 3514 err = USBD_NOMEM; 3515 goto bad2; 3516 } 3517 3518 mutex_enter(&sc->sc_lock); 3519 3520 sqh = epipe->sqh; 3521 3522 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3523 "address QH %d pipe %d\n", 3524 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3525 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3526 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3527 "MPS QH %d pipe %d\n", 3528 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3529 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3530 3531 /* Set up data transaction */ 3532 if (len != 0) { 3533 ehci_soft_qtd_t *end; 3534 3535 /* Start toggle at 1. */ 3536 epipe->nexttoggle = 1; 3537 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3538 &next, &end); 3539 if (err) 3540 goto bad3; 3541 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3542 end->nextqtd = stat; 3543 end->qtd.qtd_next = end->qtd.qtd_altnext = 3544 htole32(stat->physaddr); 3545 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3546 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3547 } else { 3548 next = stat; 3549 } 3550 3551 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3552 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3553 3554 /* Clear toggle */ 3555 setup->qtd.qtd_status = htole32( 3556 EHCI_QTD_ACTIVE | 3557 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3558 EHCI_QTD_SET_CERR(3) | 3559 EHCI_QTD_SET_TOGGLE(0) | 3560 EHCI_QTD_SET_BYTES(sizeof *req) 3561 ); 3562 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3563 setup->qtd.qtd_buffer_hi[0] = 0; 3564 setup->nextqtd = next; 3565 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3566 setup->xfer = xfer; 3567 setup->len = sizeof *req; 3568 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3569 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3570 3571 stat->qtd.qtd_status = htole32( 3572 EHCI_QTD_ACTIVE | 3573 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3574 EHCI_QTD_SET_CERR(3) | 3575 EHCI_QTD_SET_TOGGLE(1) | 3576 EHCI_QTD_IOC 3577 ); 3578 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3579 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3580 stat->nextqtd = NULL; 3581 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3582 stat->xfer = xfer; 3583 stat->len = 0; 3584 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3585 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3586 3587 #ifdef EHCI_DEBUG 3588 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3589 ehci_dump_sqh(sqh); 3590 ehci_dump_sqtds(setup); 3591 #endif 3592 3593 exfer->sqtdstart = setup; 3594 exfer->sqtdend = stat; 3595 #ifdef DIAGNOSTIC 3596 if (!exfer->isdone) { 3597 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3598 } 3599 exfer->isdone = 0; 3600 #endif 3601 3602 /* Insert qTD in QH list. */ 3603 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3604 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3605 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3606 ehci_timeout, xfer); 3607 } 3608 ehci_add_intr_list(sc, exfer); 3609 xfer->ux_status = USBD_IN_PROGRESS; 3610 mutex_exit(&sc->sc_lock); 3611 3612 #ifdef EHCI_DEBUG 3613 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3614 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3615 // delay(10000); 3616 ehci_dump_regs(sc); 3617 ehci_dump_sqh(sc->sc_async_head); 3618 ehci_dump_sqh(sqh); 3619 ehci_dump_sqtds(setup); 3620 #endif 3621 3622 return USBD_NORMAL_COMPLETION; 3623 3624 bad3: 3625 mutex_exit(&sc->sc_lock); 3626 ehci_free_sqtd(sc, stat); 3627 bad2: 3628 ehci_free_sqtd(sc, setup); 3629 bad1: 3630 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3631 mutex_enter(&sc->sc_lock); 3632 xfer->ux_status = err; 3633 usb_transfer_complete(xfer); 3634 mutex_exit(&sc->sc_lock); 3635 return err; 3636 #undef exfer 3637 } 3638 3639 /* 3640 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3641 * qTD status, or miss signalling occasionally under heavy load. If the host 3642 * machine is too fast, we we can miss transaction completion - when we scan 3643 * the active list the transaction still seems to be active. This generally 3644 * exhibits itself as a umass stall that never recovers. 3645 * 3646 * We work around this behaviour by setting up this callback after any softintr 3647 * that completes with transactions still pending, giving us another chance to 3648 * check for completion after the writeback has taken place. 3649 */ 3650 Static void 3651 ehci_intrlist_timeout(void *arg) 3652 { 3653 ehci_softc_t *sc = arg; 3654 3655 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3656 3657 usb_schedsoftintr(&sc->sc_bus); 3658 } 3659 3660 /************************/ 3661 3662 Static usbd_status 3663 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3664 { 3665 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3666 usbd_status err; 3667 3668 /* Insert last in queue. */ 3669 mutex_enter(&sc->sc_lock); 3670 err = usb_insert_transfer(xfer); 3671 mutex_exit(&sc->sc_lock); 3672 if (err) 3673 return err; 3674 3675 /* Pipe isn't running, start first */ 3676 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3677 } 3678 3679 Static usbd_status 3680 ehci_device_bulk_start(usbd_xfer_handle xfer) 3681 { 3682 #define exfer EXFER(xfer) 3683 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3684 usbd_device_handle dev = epipe->pipe.up_dev; 3685 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3686 ehci_soft_qtd_t *data, *dataend; 3687 ehci_soft_qh_t *sqh; 3688 usbd_status err; 3689 int len, isread, endpt; 3690 3691 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3692 3693 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3694 xfer, xfer->ux_length, xfer->ux_flags, 0); 3695 3696 if (sc->sc_dying) 3697 return USBD_IOERROR; 3698 3699 #ifdef DIAGNOSTIC 3700 if (xfer->ux_rqflags & URQ_REQUEST) 3701 panic("ehci_device_bulk_start: a request"); 3702 #endif 3703 3704 mutex_enter(&sc->sc_lock); 3705 3706 len = xfer->ux_length; 3707 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3708 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3709 sqh = epipe->sqh; 3710 3711 epipe->u.bulk.length = len; 3712 3713 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3714 &dataend); 3715 if (err) { 3716 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3717 xfer->ux_status = err; 3718 usb_transfer_complete(xfer); 3719 mutex_exit(&sc->sc_lock); 3720 return err; 3721 } 3722 3723 #ifdef EHCI_DEBUG 3724 USBHIST_LOGN(ehcidebug, 5, "data(1):", 0, 0, 0, 0); 3725 ehci_dump_sqh(sqh); 3726 ehci_dump_sqtds(data); 3727 #endif 3728 3729 /* Set up interrupt info. */ 3730 exfer->sqtdstart = data; 3731 exfer->sqtdend = dataend; 3732 #ifdef DIAGNOSTIC 3733 if (!exfer->isdone) { 3734 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3735 } 3736 exfer->isdone = 0; 3737 #endif 3738 3739 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3740 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3741 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3742 ehci_timeout, xfer); 3743 } 3744 ehci_add_intr_list(sc, exfer); 3745 xfer->ux_status = USBD_IN_PROGRESS; 3746 mutex_exit(&sc->sc_lock); 3747 3748 #ifdef EHCI_DEBUG 3749 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3750 // delay(10000); 3751 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3752 ehci_dump_regs(sc); 3753 #if 0 3754 printf("async_head:\n"); 3755 ehci_dump_sqh(sc->sc_async_head); 3756 #endif 3757 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3758 ehci_dump_sqh(sqh); 3759 ehci_dump_sqtds(data); 3760 #endif 3761 3762 if (sc->sc_bus.ub_usepolling) 3763 ehci_waitintr(sc, xfer); 3764 3765 return USBD_IN_PROGRESS; 3766 #undef exfer 3767 } 3768 3769 Static void 3770 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3771 { 3772 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3773 3774 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3775 ehci_abort_xfer(xfer, USBD_CANCELLED); 3776 } 3777 3778 /* 3779 * Close a device bulk pipe. 3780 */ 3781 Static void 3782 ehci_device_bulk_close(usbd_pipe_handle pipe) 3783 { 3784 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3785 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3786 3787 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3788 3789 KASSERT(mutex_owned(&sc->sc_lock)); 3790 3791 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3792 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3793 ehci_close_pipe(pipe, sc->sc_async_head); 3794 } 3795 3796 Static void 3797 ehci_device_bulk_done(usbd_xfer_handle xfer) 3798 { 3799 struct ehci_xfer *ex = EXFER(xfer); 3800 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3801 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3802 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3803 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3804 3805 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3806 3807 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3808 xfer, xfer->ux_actlen, 0, 0); 3809 3810 KASSERT(mutex_owned(&sc->sc_lock)); 3811 3812 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3813 ehci_del_intr_list(sc, ex); /* remove from active list */ 3814 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3815 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3816 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3817 } 3818 3819 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3820 } 3821 3822 /************************/ 3823 3824 Static usbd_status 3825 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3826 { 3827 struct ehci_soft_islot *isp; 3828 int islot, lev; 3829 3830 /* Find a poll rate that is large enough. */ 3831 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3832 if (EHCI_ILEV_IVAL(lev) <= ival) 3833 break; 3834 3835 /* Pick an interrupt slot at the right level. */ 3836 /* XXX could do better than picking at random */ 3837 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3838 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3839 3840 sqh->islot = islot; 3841 isp = &sc->sc_islots[islot]; 3842 mutex_enter(&sc->sc_lock); 3843 ehci_add_qh(sc, sqh, isp->sqh); 3844 mutex_exit(&sc->sc_lock); 3845 3846 return USBD_NORMAL_COMPLETION; 3847 } 3848 3849 Static usbd_status 3850 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3851 { 3852 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3853 usbd_status err; 3854 3855 /* Insert last in queue. */ 3856 mutex_enter(&sc->sc_lock); 3857 err = usb_insert_transfer(xfer); 3858 mutex_exit(&sc->sc_lock); 3859 if (err) 3860 return err; 3861 3862 /* 3863 * Pipe isn't running (otherwise err would be USBD_INPROG), 3864 * so start it first. 3865 */ 3866 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3867 } 3868 3869 Static usbd_status 3870 ehci_device_intr_start(usbd_xfer_handle xfer) 3871 { 3872 #define exfer EXFER(xfer) 3873 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3874 usbd_device_handle dev = xfer->ux_pipe->up_dev; 3875 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3876 ehci_soft_qtd_t *data, *dataend; 3877 ehci_soft_qh_t *sqh; 3878 usbd_status err; 3879 int len, isread, endpt; 3880 3881 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3882 3883 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3884 xfer, xfer->ux_length, xfer->ux_flags, 0); 3885 3886 if (sc->sc_dying) 3887 return USBD_IOERROR; 3888 3889 #ifdef DIAGNOSTIC 3890 if (xfer->ux_rqflags & URQ_REQUEST) 3891 panic("ehci_device_intr_start: a request"); 3892 #endif 3893 3894 mutex_enter(&sc->sc_lock); 3895 3896 len = xfer->ux_length; 3897 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3898 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3899 sqh = epipe->sqh; 3900 3901 epipe->u.intr.length = len; 3902 3903 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3904 &dataend); 3905 if (err) { 3906 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3907 xfer->ux_status = err; 3908 usb_transfer_complete(xfer); 3909 mutex_exit(&sc->sc_lock); 3910 return err; 3911 } 3912 3913 #ifdef EHCI_DEBUG 3914 USBHIST_LOGN(ehcidebug, 5, "data(1)", 0, 0, 0, 0); 3915 ehci_dump_sqh(sqh); 3916 ehci_dump_sqtds(data); 3917 #endif 3918 3919 /* Set up interrupt info. */ 3920 exfer->sqtdstart = data; 3921 exfer->sqtdend = dataend; 3922 #ifdef DIAGNOSTIC 3923 if (!exfer->isdone) { 3924 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3925 } 3926 exfer->isdone = 0; 3927 #endif 3928 3929 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3930 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3931 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3932 ehci_timeout, xfer); 3933 } 3934 ehci_add_intr_list(sc, exfer); 3935 xfer->ux_status = USBD_IN_PROGRESS; 3936 mutex_exit(&sc->sc_lock); 3937 3938 #ifdef EHCI_DEBUG 3939 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3940 // delay(10000); 3941 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3942 ehci_dump_regs(sc); 3943 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3944 ehci_dump_sqh(sqh); 3945 ehci_dump_sqtds(data); 3946 #endif 3947 3948 if (sc->sc_bus.ub_usepolling) 3949 ehci_waitintr(sc, xfer); 3950 3951 return USBD_IN_PROGRESS; 3952 #undef exfer 3953 } 3954 3955 Static void 3956 ehci_device_intr_abort(usbd_xfer_handle xfer) 3957 { 3958 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3959 3960 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3961 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3962 3963 /* 3964 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3965 * async doorbell. That's dependent on the async list, wheras 3966 * intr xfers are periodic, should not use this? 3967 */ 3968 ehci_abort_xfer(xfer, USBD_CANCELLED); 3969 } 3970 3971 Static void 3972 ehci_device_intr_close(usbd_pipe_handle pipe) 3973 { 3974 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3975 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3976 struct ehci_soft_islot *isp; 3977 3978 KASSERT(mutex_owned(&sc->sc_lock)); 3979 3980 isp = &sc->sc_islots[epipe->sqh->islot]; 3981 ehci_close_pipe(pipe, isp->sqh); 3982 } 3983 3984 Static void 3985 ehci_device_intr_done(usbd_xfer_handle xfer) 3986 { 3987 #define exfer EXFER(xfer) 3988 struct ehci_xfer *ex = EXFER(xfer); 3989 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3990 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3991 ehci_soft_qtd_t *data, *dataend; 3992 ehci_soft_qh_t *sqh; 3993 usbd_status err; 3994 int len, isread, endpt; 3995 3996 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3997 3998 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3999 xfer, xfer->ux_actlen, 0, 0); 4000 4001 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4002 4003 if (xfer->ux_pipe->up_repeat) { 4004 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4005 4006 len = epipe->u.intr.length; 4007 xfer->ux_length = len; 4008 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4009 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4010 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4011 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4012 sqh = epipe->sqh; 4013 4014 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4015 &data, &dataend); 4016 if (err) { 4017 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4018 xfer->ux_status = err; 4019 return; 4020 } 4021 4022 /* Set up interrupt info. */ 4023 exfer->sqtdstart = data; 4024 exfer->sqtdend = dataend; 4025 #ifdef DIAGNOSTIC 4026 if (!exfer->isdone) { 4027 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", 4028 exfer, 0, 0, 0); 4029 printf("ehci_device_intr_done: not done, ex=%p\n", 4030 exfer); 4031 } 4032 exfer->isdone = 0; 4033 #endif 4034 4035 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4036 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4037 callout_reset(&xfer->ux_callout, 4038 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4039 } 4040 4041 xfer->ux_status = USBD_IN_PROGRESS; 4042 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4043 ehci_del_intr_list(sc, ex); /* remove from active list */ 4044 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4045 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4046 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4047 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4048 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4049 } 4050 #undef exfer 4051 } 4052 4053 /************************/ 4054 4055 Static usbd_status 4056 ehci_device_fs_isoc_transfer(usbd_xfer_handle xfer) 4057 { 4058 usbd_status err; 4059 4060 err = usb_insert_transfer(xfer); 4061 if (err && err != USBD_IN_PROGRESS) 4062 return err; 4063 4064 return ehci_device_fs_isoc_start(xfer); 4065 } 4066 4067 Static usbd_status 4068 ehci_device_fs_isoc_start(usbd_xfer_handle xfer) 4069 { 4070 struct ehci_pipe *epipe; 4071 usbd_device_handle dev; 4072 ehci_softc_t *sc; 4073 struct ehci_xfer *exfer; 4074 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4075 usb_dma_t *dma_buf; 4076 int i, j, k, frames; 4077 int offs, total_length; 4078 int frindex; 4079 u_int huba, dir; 4080 4081 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4082 4083 start = NULL; 4084 prev = NULL; 4085 sitd = NULL; 4086 total_length = 0; 4087 exfer = (struct ehci_xfer *) xfer; 4088 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4089 dev = xfer->ux_pipe->up_dev; 4090 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4091 4092 /* 4093 * To allow continuous transfers, above we start all transfers 4094 * immediately. However, we're still going to get usbd_start_next call 4095 * this when another xfer completes. So, check if this is already 4096 * in progress or not 4097 */ 4098 4099 if (exfer->sitdstart != NULL) 4100 return USBD_IN_PROGRESS; 4101 4102 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4103 xfer, xfer->ux_length, xfer->ux_flags, 0); 4104 4105 if (sc->sc_dying) 4106 return USBD_IOERROR; 4107 4108 /* 4109 * To avoid complication, don't allow a request right now that'll span 4110 * the entire frame table. To within 4 frames, to allow some leeway 4111 * on either side of where the hc currently is. 4112 */ 4113 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4114 xfer->ux_nframes >= sc->sc_flsize - 4) { 4115 printf("ehci: isoc descriptor requested that spans the entire" 4116 "frametable, too many frames\n"); 4117 return USBD_INVAL; 4118 } 4119 4120 #ifdef DIAGNOSTIC 4121 if (xfer->ux_rqflags & URQ_REQUEST) 4122 panic("ehci_device_fs_isoc_start: request\n"); 4123 4124 if (!exfer->isdone) 4125 printf("ehci_device_fs_isoc_start: not done, ex = %p\n", exfer); 4126 exfer->isdone = 0; 4127 #endif 4128 4129 /* 4130 * Step 1: Allocate and initialize sitds. 4131 */ 4132 4133 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4134 if (i > 16 || i == 0) { 4135 /* Spec page 271 says intervals > 16 are invalid */ 4136 USBHIST_LOG(ehcidebug, "bInverval %d invalid\n", 0, 0, 0, 0); 4137 4138 return USBD_INVAL; 4139 } 4140 4141 frames = xfer->ux_nframes; 4142 4143 if (frames == 0) { 4144 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4145 4146 return USBD_INVAL; 4147 } 4148 4149 dma_buf = &xfer->ux_dmabuf; 4150 offs = 0; 4151 4152 for (i = 0; i < frames; i++) { 4153 sitd = ehci_alloc_sitd(sc); 4154 4155 if (prev) 4156 prev->xfer_next = sitd; 4157 else 4158 start = sitd; 4159 4160 #ifdef DIAGNOSTIC 4161 if (xfer->ux_frlengths[i] > 0x3ff) { 4162 printf("ehci: invalid frame length\n"); 4163 xfer->ux_frlengths[i] = 0x3ff; 4164 } 4165 #endif 4166 4167 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4168 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4169 4170 /* Set page0 index and offset. */ 4171 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4172 4173 total_length += xfer->ux_frlengths[i]; 4174 offs += xfer->ux_frlengths[i]; 4175 4176 sitd->sitd.sitd_buffer[1] = 4177 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4178 4179 huba = dev->ud_myhsport->up_parent->ud_addr; 4180 4181 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4182 // Set hub address to 0 if embedded TT is used. 4183 if (huba == sc->sc_addr) 4184 huba = 0; 4185 } 4186 */ 4187 4188 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4189 dir = UE_GET_DIR(k) ? 1 : 0; 4190 sitd->sitd.sitd_endp = 4191 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4192 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4193 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4194 EHCI_SITD_SET_HUBA(huba) | 4195 EHCI_SITD_SET_DIR(dir)); 4196 4197 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4198 4199 /* XXX */ 4200 u_char sa, sb; 4201 u_int temp, tlen; 4202 sa = 0; 4203 4204 if (dir == 0) { /* OUT */ 4205 temp = 0; 4206 tlen = xfer->ux_frlengths[i]; 4207 if (tlen <= 188) { 4208 temp |= 1; /* T-count = 1, TP = ALL */ 4209 tlen = 1; 4210 } else { 4211 tlen += 187; 4212 tlen /= 188; 4213 temp |= tlen; /* T-count = [1..6] */ 4214 temp |= 8; /* TP = Begin */ 4215 } 4216 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4217 4218 tlen += sa; 4219 4220 if (tlen >= 8) { 4221 sb = 0; 4222 } else { 4223 sb = (1 << tlen); 4224 } 4225 4226 sa = (1 << sa); 4227 sa = (sb - sa) & 0x3F; 4228 sb = 0; 4229 } else { 4230 sb = (-(4 << sa)) & 0xFE; 4231 sa = (1 << sa) & 0x3F; 4232 sa = 0x01; 4233 sb = 0xfc; 4234 } 4235 4236 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4237 EHCI_SITD_SET_CMASK(sb)); 4238 4239 prev = sitd; 4240 } /* End of frame */ 4241 4242 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4243 4244 stop = sitd; 4245 stop->xfer_next = NULL; 4246 exfer->isoc_len = total_length; 4247 4248 usb_syncmem(&exfer->xfer.ux_dmabuf, 0, total_length, 4249 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4250 4251 /* 4252 * Part 2: Transfer descriptors have now been set up, now they must 4253 * be scheduled into the periodic frame list. Erk. Not wanting to 4254 * complicate matters, transfer is denied if the transfer spans 4255 * more than the period frame list. 4256 */ 4257 4258 mutex_enter(&sc->sc_lock); 4259 4260 /* Start inserting frames */ 4261 if (epipe->u.isoc.cur_xfers > 0) { 4262 frindex = epipe->u.isoc.next_frame; 4263 } else { 4264 frindex = EOREAD4(sc, EHCI_FRINDEX); 4265 frindex = frindex >> 3; /* Erase microframe index */ 4266 frindex += 2; 4267 } 4268 4269 if (frindex >= sc->sc_flsize) 4270 frindex &= (sc->sc_flsize - 1); 4271 4272 /* Whats the frame interval? */ 4273 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4274 4275 sitd = start; 4276 for (j = 0; j < frames; j++) { 4277 if (sitd == NULL) 4278 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4279 4280 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4281 if (sitd->sitd.sitd_next == 0) 4282 /* FIXME: frindex table gets initialized to NULL 4283 * or EHCI_NULL? */ 4284 sitd->sitd.sitd_next = EHCI_NULL; 4285 4286 usb_syncmem(&sitd->dma, 4287 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4288 sizeof(ehci_sitd_t), 4289 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4290 4291 sc->sc_flist[frindex] = 4292 htole32(EHCI_LINK_SITD | sitd->physaddr); 4293 4294 usb_syncmem(&sc->sc_fldma, 4295 sizeof(ehci_link_t) * frindex, 4296 sizeof(ehci_link_t), 4297 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4298 4299 sitd->u.frame_list.next = sc->sc_softsitds[frindex]; 4300 sc->sc_softsitds[frindex] = sitd; 4301 if (sitd->u.frame_list.next != NULL) 4302 sitd->u.frame_list.next->u.frame_list.prev = sitd; 4303 sitd->slot = frindex; 4304 sitd->u.frame_list.prev = NULL; 4305 4306 frindex += i; 4307 if (frindex >= sc->sc_flsize) 4308 frindex -= sc->sc_flsize; 4309 4310 sitd = sitd->xfer_next; 4311 } 4312 4313 epipe->u.isoc.cur_xfers++; 4314 epipe->u.isoc.next_frame = frindex; 4315 4316 exfer->sitdstart = start; 4317 exfer->sitdend = stop; 4318 exfer->sqtdstart = NULL; 4319 exfer->sqtdstart = NULL; 4320 4321 ehci_add_intr_list(sc, exfer); 4322 xfer->ux_status = USBD_IN_PROGRESS; 4323 xfer->ux_done = 0; 4324 4325 mutex_exit(&sc->sc_lock); 4326 4327 if (sc->sc_bus.ub_usepolling) { 4328 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4329 ehci_waitintr(sc, xfer); 4330 } 4331 4332 return USBD_IN_PROGRESS; 4333 } 4334 4335 Static void 4336 ehci_device_fs_isoc_abort(usbd_xfer_handle xfer) 4337 { 4338 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4339 4340 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4341 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4342 } 4343 4344 Static void 4345 ehci_device_fs_isoc_close(usbd_pipe_handle pipe) 4346 { 4347 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4348 4349 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4350 } 4351 4352 Static void 4353 ehci_device_fs_isoc_done(usbd_xfer_handle xfer) 4354 { 4355 struct ehci_xfer *exfer; 4356 ehci_softc_t *sc; 4357 struct ehci_pipe *epipe; 4358 4359 exfer = EXFER(xfer); 4360 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4361 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4362 4363 KASSERT(mutex_owned(&sc->sc_lock)); 4364 4365 epipe->u.isoc.cur_xfers--; 4366 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4367 ehci_del_intr_list(sc, exfer); 4368 ehci_rem_free_sitd_chain(sc, exfer); 4369 } 4370 4371 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4372 BUS_DMASYNC_POSTREAD); 4373 } 4374 Static usbd_status 4375 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 4376 { 4377 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4378 usbd_status err; 4379 4380 mutex_enter(&sc->sc_lock); 4381 err = usb_insert_transfer(xfer); 4382 mutex_exit(&sc->sc_lock); 4383 if (err && err != USBD_IN_PROGRESS) 4384 return err; 4385 4386 return ehci_device_isoc_start(xfer); 4387 } 4388 4389 Static usbd_status 4390 ehci_device_isoc_start(usbd_xfer_handle xfer) 4391 { 4392 struct ehci_pipe *epipe; 4393 ehci_softc_t *sc; 4394 struct ehci_xfer *exfer; 4395 ehci_soft_itd_t *itd, *prev, *start, *stop; 4396 usb_dma_t *dma_buf; 4397 int i, j, k, frames, uframes, ufrperframe; 4398 int trans_count, offs, total_length; 4399 int frindex; 4400 4401 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4402 4403 start = NULL; 4404 prev = NULL; 4405 itd = NULL; 4406 trans_count = 0; 4407 total_length = 0; 4408 exfer = (struct ehci_xfer *) xfer; 4409 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4410 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4411 4412 /* 4413 * To allow continuous transfers, above we start all transfers 4414 * immediately. However, we're still going to get usbd_start_next call 4415 * this when another xfer completes. So, check if this is already 4416 * in progress or not 4417 */ 4418 4419 if (exfer->itdstart != NULL) 4420 return USBD_IN_PROGRESS; 4421 4422 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4423 xfer, xfer->ux_length, xfer->ux_flags, 0); 4424 4425 if (sc->sc_dying) 4426 return USBD_IOERROR; 4427 4428 /* 4429 * To avoid complication, don't allow a request right now that'll span 4430 * the entire frame table. To within 4 frames, to allow some leeway 4431 * on either side of where the hc currently is. 4432 */ 4433 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4434 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4435 USBHIST_LOG(ehcidebug, 4436 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4437 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4438 return USBD_INVAL; 4439 } 4440 4441 #ifdef DIAGNOSTIC 4442 if (xfer->ux_rqflags & URQ_REQUEST) 4443 panic("ehci_device_isoc_start: request\n"); 4444 4445 if (!exfer->isdone) { 4446 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", exfer, 4447 0, 0, 0); 4448 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 4449 } 4450 exfer->isdone = 0; 4451 #endif 4452 4453 /* 4454 * Step 1: Allocate and initialize itds, how many do we need? 4455 * One per transfer if interval >= 8 microframes, fewer if we use 4456 * multiple microframes per frame. 4457 */ 4458 4459 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4460 if (i > 16 || i == 0) { 4461 /* Spec page 271 says intervals > 16 are invalid */ 4462 USBHIST_LOG(ehcidebug, "bInvertal %d invalid", i, 0, 0, 0); 4463 return USBD_INVAL; 4464 } 4465 4466 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4467 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4468 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4469 4470 if (frames == 0) { 4471 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4472 return USBD_INVAL; 4473 } 4474 4475 dma_buf = &xfer->ux_dmabuf; 4476 offs = 0; 4477 4478 for (i = 0; i < frames; i++) { 4479 int froffs = offs; 4480 itd = ehci_alloc_itd(sc); 4481 4482 if (prev != NULL) { 4483 prev->itd.itd_next = 4484 htole32(itd->physaddr | EHCI_LINK_ITD); 4485 usb_syncmem(&itd->dma, 4486 itd->offs + offsetof(ehci_itd_t, itd_next), 4487 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4488 4489 prev->xfer_next = itd; 4490 } else { 4491 start = itd; 4492 } 4493 4494 /* 4495 * Step 1.5, initialize uframes 4496 */ 4497 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4498 /* Calculate which page in the list this starts in */ 4499 int addr = DMAADDR(dma_buf, froffs); 4500 addr = EHCI_PAGE_OFFSET(addr); 4501 addr += (offs - froffs); 4502 addr = EHCI_PAGE(addr); 4503 addr /= EHCI_PAGE_SIZE; 4504 4505 /* This gets the initial offset into the first page, 4506 * looks how far further along the current uframe 4507 * offset is. Works out how many pages that is. 4508 */ 4509 4510 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4511 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4512 EHCI_ITD_SET_PG(addr) | 4513 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4514 4515 total_length += xfer->ux_frlengths[trans_count]; 4516 offs += xfer->ux_frlengths[trans_count]; 4517 trans_count++; 4518 4519 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4520 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4521 break; 4522 } 4523 } 4524 4525 /* Step 1.75, set buffer pointers. To simplify matters, all 4526 * pointers are filled out for the next 7 hardware pages in 4527 * the dma block, so no need to worry what pages to cover 4528 * and what to not. 4529 */ 4530 4531 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4532 /* 4533 * Don't try to lookup a page that's past the end 4534 * of buffer 4535 */ 4536 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4537 if (page_offs >= dma_buf->udma_block->size) 4538 break; 4539 4540 unsigned long long page = DMAADDR(dma_buf, page_offs); 4541 page = EHCI_PAGE(page); 4542 itd->itd.itd_bufr[j] = 4543 htole32(EHCI_ITD_SET_BPTR(page)); 4544 itd->itd.itd_bufr_hi[j] = 4545 htole32(page >> 32); 4546 } 4547 4548 /* 4549 * Other special values 4550 */ 4551 4552 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4553 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4554 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4555 4556 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4557 ? 1 : 0; 4558 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4559 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4560 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4561 4562 /* FIXME: handle invalid trans */ 4563 itd->itd.itd_bufr[2] |= 4564 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4565 4566 usb_syncmem(&itd->dma, 4567 itd->offs + offsetof(ehci_itd_t, itd_next), 4568 sizeof(ehci_itd_t), 4569 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4570 4571 prev = itd; 4572 } /* End of frame */ 4573 4574 stop = itd; 4575 stop->xfer_next = NULL; 4576 exfer->isoc_len = total_length; 4577 4578 usb_syncmem(&exfer->xfer.ux_dmabuf, 0, total_length, 4579 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4580 4581 /* 4582 * Part 2: Transfer descriptors have now been set up, now they must 4583 * be scheduled into the period frame list. Erk. Not wanting to 4584 * complicate matters, transfer is denied if the transfer spans 4585 * more than the period frame list. 4586 */ 4587 4588 mutex_enter(&sc->sc_lock); 4589 4590 /* Start inserting frames */ 4591 if (epipe->u.isoc.cur_xfers > 0) { 4592 frindex = epipe->u.isoc.next_frame; 4593 } else { 4594 frindex = EOREAD4(sc, EHCI_FRINDEX); 4595 frindex = frindex >> 3; /* Erase microframe index */ 4596 frindex += 2; 4597 } 4598 4599 if (frindex >= sc->sc_flsize) 4600 frindex &= (sc->sc_flsize - 1); 4601 4602 /* What's the frame interval? */ 4603 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4604 if (i / USB_UFRAMES_PER_FRAME == 0) 4605 i = 1; 4606 else 4607 i /= USB_UFRAMES_PER_FRAME; 4608 4609 itd = start; 4610 for (j = 0; j < frames; j++) { 4611 if (itd == NULL) 4612 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4613 4614 itd->itd.itd_next = sc->sc_flist[frindex]; 4615 if (itd->itd.itd_next == 0) 4616 /* FIXME: frindex table gets initialized to NULL 4617 * or EHCI_NULL? */ 4618 itd->itd.itd_next = EHCI_NULL; 4619 4620 usb_syncmem(&itd->dma, 4621 itd->offs + offsetof(ehci_itd_t, itd_next), 4622 sizeof(itd->itd.itd_next), 4623 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4624 4625 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4626 4627 usb_syncmem(&sc->sc_fldma, 4628 sizeof(ehci_link_t) * frindex, 4629 sizeof(ehci_link_t), 4630 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4631 4632 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4633 sc->sc_softitds[frindex] = itd; 4634 if (itd->u.frame_list.next != NULL) 4635 itd->u.frame_list.next->u.frame_list.prev = itd; 4636 itd->slot = frindex; 4637 itd->u.frame_list.prev = NULL; 4638 4639 frindex += i; 4640 if (frindex >= sc->sc_flsize) 4641 frindex -= sc->sc_flsize; 4642 4643 itd = itd->xfer_next; 4644 } 4645 4646 epipe->u.isoc.cur_xfers++; 4647 epipe->u.isoc.next_frame = frindex; 4648 4649 exfer->itdstart = start; 4650 exfer->itdend = stop; 4651 exfer->sqtdstart = NULL; 4652 exfer->sqtdend = NULL; 4653 4654 ehci_add_intr_list(sc, exfer); 4655 xfer->ux_status = USBD_IN_PROGRESS; 4656 xfer->ux_done = 0; 4657 mutex_exit(&sc->sc_lock); 4658 4659 if (sc->sc_bus.ub_usepolling) { 4660 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4661 ehci_waitintr(sc, xfer); 4662 } 4663 4664 return USBD_IN_PROGRESS; 4665 } 4666 4667 Static void 4668 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4669 { 4670 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4671 4672 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4673 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4674 } 4675 4676 Static void 4677 ehci_device_isoc_close(usbd_pipe_handle pipe) 4678 { 4679 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4680 4681 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4682 } 4683 4684 Static void 4685 ehci_device_isoc_done(usbd_xfer_handle xfer) 4686 { 4687 struct ehci_xfer *exfer; 4688 ehci_softc_t *sc; 4689 struct ehci_pipe *epipe; 4690 4691 exfer = EXFER(xfer); 4692 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4693 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4694 4695 KASSERT(mutex_owned(&sc->sc_lock)); 4696 4697 epipe->u.isoc.cur_xfers--; 4698 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4699 ehci_del_intr_list(sc, exfer); 4700 ehci_rem_free_itd_chain(sc, exfer); 4701 } 4702 4703 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4704 BUS_DMASYNC_POSTREAD); 4705 4706 } 4707
Indexes created Wed Oct 01 19:09:53 GMT 2025