ehci.c revision 1.234.2.19
1 /* $NetBSD: ehci.c,v 1.234.2.19 2014/12/23 19:31:44 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.19 2014/12/23 19:31:44 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 85 #include <dev/usb/ehcireg.h> 86 #include <dev/usb/ehcivar.h> 87 #include <dev/usb/usbroothub.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 /* ehci_soft_sitd_t *sitd; */ 135 } tail; 136 union { 137 /* Control pipe */ 138 struct { 139 usb_dma_t reqdma; 140 } ctl; 141 /* Interrupt pipe */ 142 struct { 143 u_int length; 144 } intr; 145 /* Bulk pipe */ 146 struct { 147 u_int length; 148 } bulk; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 } u; 155 }; 156 157 Static usbd_status ehci_open(usbd_pipe_handle); 158 Static void ehci_poll(struct usbd_bus *); 159 Static void ehci_softintr(void *); 160 Static int ehci_intr1(ehci_softc_t *); 161 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 162 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 166 Static void ehci_idone(struct ehci_xfer *); 167 Static void ehci_timeout(void *); 168 Static void ehci_timeout_task(void *); 169 Static void ehci_intrlist_timeout(void *); 170 Static void ehci_doorbell(void *); 171 Static void ehci_pcd(void *); 172 173 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 174 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 Static int ehci_roothub_ctrl(struct usbd_bus *, 177 usb_device_request_t *, void *, int); 178 179 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 180 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 181 Static void ehci_root_intr_abort(usbd_xfer_handle); 182 Static void ehci_root_intr_close(usbd_pipe_handle); 183 Static void ehci_root_intr_done(usbd_xfer_handle); 184 185 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 186 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 187 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 188 Static void ehci_device_ctrl_close(usbd_pipe_handle); 189 Static void ehci_device_ctrl_done(usbd_xfer_handle); 190 191 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 192 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 193 Static void ehci_device_bulk_abort(usbd_xfer_handle); 194 Static void ehci_device_bulk_close(usbd_pipe_handle); 195 Static void ehci_device_bulk_done(usbd_xfer_handle); 196 197 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 198 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 199 Static void ehci_device_intr_abort(usbd_xfer_handle); 200 Static void ehci_device_intr_close(usbd_pipe_handle); 201 Static void ehci_device_intr_done(usbd_xfer_handle); 202 203 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 204 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 205 Static void ehci_device_isoc_abort(usbd_xfer_handle); 206 Static void ehci_device_isoc_close(usbd_pipe_handle); 207 Static void ehci_device_isoc_done(usbd_xfer_handle); 208 209 Static usbd_status ehci_device_fs_isoc_transfer(usbd_xfer_handle); 210 Static usbd_status ehci_device_fs_isoc_start(usbd_xfer_handle); 211 Static void ehci_device_fs_isoc_abort(usbd_xfer_handle); 212 Static void ehci_device_fs_isoc_close(usbd_pipe_handle); 213 Static void ehci_device_fs_isoc_done(usbd_xfer_handle); 214 215 Static void ehci_device_clear_toggle(usbd_pipe_handle); 216 Static void ehci_noop(usbd_pipe_handle); 217 218 Static void ehci_disown(ehci_softc_t *, int, int); 219 220 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 221 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 222 223 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 224 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 225 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 226 ehci_softc_t *, int, int, usbd_xfer_handle, 227 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 228 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 229 ehci_soft_qtd_t *); 230 231 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 232 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *); 233 Static void ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *); 234 Static void ehci_free_sitd(ehci_softc_t *, ehci_soft_sitd_t *); 235 Static void ehci_rem_free_itd_chain(ehci_softc_t *, 236 struct ehci_xfer *); 237 Static void ehci_rem_free_sitd_chain(ehci_softc_t *, 238 struct ehci_xfer *); 239 Static void ehci_abort_isoc_xfer(usbd_xfer_handle, 240 usbd_status); 241 242 Static usbd_status ehci_device_request(usbd_xfer_handle); 243 244 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 245 int); 246 247 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 248 ehci_soft_qh_t *); 249 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 250 ehci_soft_qh_t *); 251 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 252 Static void ehci_sync_hc(ehci_softc_t *); 253 254 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 255 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 256 257 #ifdef EHCI_DEBUG 258 Static ehci_softc_t *theehci; 259 void ehci_dump(void); 260 #endif 261 262 #ifdef EHCI_DEBUG 263 Static void ehci_dump_regs(ehci_softc_t *); 264 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 265 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 266 Static void ehci_dump_qtd(ehci_qtd_t *); 267 Static void ehci_dump_sqh(ehci_soft_qh_t *); 268 Static void ehci_dump_sitd(struct ehci_soft_itd *); 269 Static void ehci_dump_itd(struct ehci_soft_itd *); 270 Static void ehci_dump_exfer(struct ehci_xfer *); 271 #endif 272 273 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 274 275 #define ehci_add_intr_list(sc, ex) \ 276 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), inext); 277 #define ehci_del_intr_list(sc, ex) \ 278 do { \ 279 TAILQ_REMOVE(&sc->sc_intrhead, (ex), inext); \ 280 (ex)->inext.tqe_prev = NULL; \ 281 } while (0) 282 #define ehci_active_intr_list(ex) ((ex)->inext.tqe_prev != NULL) 283 284 Static const struct usbd_bus_methods ehci_bus_methods = { 285 .ubm_open = ehci_open, 286 .ubm_softint = ehci_softintr, 287 .ubm_dopoll = ehci_poll, 288 .ubm_allocx = ehci_allocx, 289 .ubm_freex = ehci_freex, 290 .ubm_getlock = ehci_get_lock, 291 .ubm_rhctrl = ehci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 295 .upm_transfer = ehci_root_intr_transfer, 296 .upm_start = ehci_root_intr_start, 297 .upm_abort = ehci_root_intr_abort, 298 .upm_close = ehci_root_intr_close, 299 .upm_cleartoggle = ehci_noop, 300 .upm_done = ehci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 304 .upm_transfer = ehci_device_ctrl_transfer, 305 .upm_start = ehci_device_ctrl_start, 306 .upm_abort = ehci_device_ctrl_abort, 307 .upm_close = ehci_device_ctrl_close, 308 .upm_cleartoggle = ehci_noop, 309 .upm_done = ehci_device_ctrl_done, 310 }; 311 312 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 313 .upm_transfer = ehci_device_intr_transfer, 314 .upm_start = ehci_device_intr_start, 315 .upm_abort = ehci_device_intr_abort, 316 .upm_close = ehci_device_intr_close, 317 .upm_cleartoggle = ehci_device_clear_toggle, 318 .upm_done = ehci_device_intr_done, 319 }; 320 321 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 322 .upm_transfer = ehci_device_bulk_transfer, 323 .upm_start = ehci_device_bulk_start, 324 .upm_abort = ehci_device_bulk_abort, 325 .upm_close = ehci_device_bulk_close, 326 .upm_cleartoggle = ehci_device_clear_toggle, 327 .upm_done = ehci_device_bulk_done, 328 }; 329 330 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 331 .upm_transfer = ehci_device_isoc_transfer, 332 .upm_start = ehci_device_isoc_start, 333 .upm_abort = ehci_device_isoc_abort, 334 .upm_close = ehci_device_isoc_close, 335 .upm_cleartoggle = ehci_noop, 336 .upm_done = ehci_device_isoc_done, 337 }; 338 339 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 340 .upm_transfer = ehci_device_fs_isoc_transfer, 341 .upm_start = ehci_device_fs_isoc_start, 342 .upm_abort = ehci_device_fs_isoc_abort, 343 .upm_close = ehci_device_fs_isoc_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_fs_isoc_done, 346 }; 347 348 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 349 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 350 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 351 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 352 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 353 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 354 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 355 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 356 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 357 }; 358 359 int 360 ehci_init(ehci_softc_t *sc) 361 { 362 uint32_t vers, sparams, cparams, hcr; 363 u_int i; 364 usbd_status err; 365 ehci_soft_qh_t *sqh; 366 u_int ncomp; 367 368 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 369 #ifdef EHCI_DEBUG 370 theehci = sc; 371 #endif 372 373 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 374 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 375 cv_init(&sc->sc_softwake_cv, "ehciab"); 376 cv_init(&sc->sc_doorbell, "ehcidi"); 377 378 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 379 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 380 381 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 382 ehci_doorbell, sc); 383 KASSERT(sc->sc_doorbell_si != NULL); 384 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 385 ehci_pcd, sc); 386 KASSERT(sc->sc_pcd_si != NULL); 387 388 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 389 390 vers = EREAD2(sc, EHCI_HCIVERSION); 391 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 392 vers >> 8, vers & 0xff); 393 394 sparams = EREAD4(sc, EHCI_HCSPARAMS); 395 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 396 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 397 ncomp = EHCI_HCS_N_CC(sparams); 398 if (ncomp != sc->sc_ncomp) { 399 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 400 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 401 #if NOHCI == 0 || NUHCI == 0 402 aprint_error("%s: ohci or uhci probably not configured\n", 403 device_xname(sc->sc_dev)); 404 #endif 405 if (ncomp < sc->sc_ncomp) 406 sc->sc_ncomp = ncomp; 407 } 408 if (sc->sc_ncomp > 0) { 409 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 410 aprint_normal("%s: companion controller%s, %d port%s each:", 411 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 412 EHCI_HCS_N_PCC(sparams), 413 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 414 for (i = 0; i < sc->sc_ncomp; i++) 415 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 416 aprint_normal("\n"); 417 } 418 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 419 cparams = EREAD4(sc, EHCI_HCCPARAMS); 420 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 421 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 422 423 if (EHCI_HCC_64BIT(cparams)) { 424 /* MUST clear segment register if 64 bit capable. */ 425 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 426 } 427 428 sc->sc_bus.ub_revision = USBREV_2_0; 429 sc->sc_bus.ub_usedma = true; 430 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 431 432 /* Reset the controller */ 433 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 434 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 435 usb_delay_ms(&sc->sc_bus, 1); 436 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 437 for (i = 0; i < 100; i++) { 438 usb_delay_ms(&sc->sc_bus, 1); 439 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 440 if (!hcr) 441 break; 442 } 443 if (hcr) { 444 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 445 return EIO; 446 } 447 if (sc->sc_vendor_init) 448 sc->sc_vendor_init(sc); 449 450 /* 451 * If we are doing embedded transaction translation function, force 452 * the controller to host mode. 453 */ 454 if (sc->sc_flags & EHCIF_ETTF) { 455 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 456 usbmode &= ~EHCI_USBMODE_CM; 457 usbmode |= EHCI_USBMODE_CM_HOST; 458 EWRITE4(sc, EHCI_USBMODE, usbmode); 459 } 460 461 /* XXX need proper intr scheduling */ 462 sc->sc_rand = 96; 463 464 /* frame list size at default, read back what we got and use that */ 465 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 466 case 0: sc->sc_flsize = 1024; break; 467 case 1: sc->sc_flsize = 512; break; 468 case 2: sc->sc_flsize = 256; break; 469 case 3: return EIO; 470 } 471 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 472 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 473 if (err) 474 return err; 475 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 476 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 477 478 for (i = 0; i < sc->sc_flsize; i++) { 479 sc->sc_flist[i] = EHCI_NULL; 480 } 481 482 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 483 484 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 485 KM_SLEEP); 486 if (sc->sc_softitds == NULL) 487 return ENOMEM; 488 LIST_INIT(&sc->sc_freeitds); 489 LIST_INIT(&sc->sc_freesitds); 490 TAILQ_INIT(&sc->sc_intrhead); 491 492 /* Set up the bus struct. */ 493 sc->sc_bus.ub_methods = &ehci_bus_methods; 494 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 495 496 sc->sc_eintrs = EHCI_NORMAL_INTRS; 497 498 /* 499 * Allocate the interrupt dummy QHs. These are arranged to give poll 500 * intervals that are powers of 2 times 1ms. 501 */ 502 for (i = 0; i < EHCI_INTRQHS; i++) { 503 sqh = ehci_alloc_sqh(sc); 504 if (sqh == NULL) { 505 err = ENOMEM; 506 goto bad1; 507 } 508 sc->sc_islots[i].sqh = sqh; 509 } 510 for (i = 0; i < EHCI_INTRQHS; i++) { 511 sqh = sc->sc_islots[i].sqh; 512 if (i == 0) { 513 /* The last (1ms) QH terminates. */ 514 sqh->qh.qh_link = EHCI_NULL; 515 sqh->next = NULL; 516 } else { 517 /* Otherwise the next QH has half the poll interval */ 518 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 519 sqh->qh.qh_link = htole32(sqh->next->physaddr | 520 EHCI_LINK_QH); 521 } 522 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 523 sqh->qh.qh_curqtd = EHCI_NULL; 524 sqh->next = NULL; 525 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 526 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 527 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 528 sqh->sqtd = NULL; 529 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 531 } 532 /* Point the frame list at the last level (128ms). */ 533 for (i = 0; i < sc->sc_flsize; i++) { 534 int j; 535 536 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 537 revbits[i & (EHCI_MAX_POLLRATE-1)]; 538 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 539 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 540 i)].sqh->physaddr); 541 } 542 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 543 BUS_DMASYNC_PREWRITE); 544 545 /* Allocate dummy QH that starts the async list. */ 546 sqh = ehci_alloc_sqh(sc); 547 if (sqh == NULL) { 548 err = ENOMEM; 549 goto bad1; 550 } 551 /* Fill the QH */ 552 sqh->qh.qh_endp = 553 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 554 sqh->qh.qh_link = 555 htole32(sqh->physaddr | EHCI_LINK_QH); 556 sqh->qh.qh_curqtd = EHCI_NULL; 557 sqh->next = NULL; 558 /* Fill the overlay qTD */ 559 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 560 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 561 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 562 sqh->sqtd = NULL; 563 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 564 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 565 #ifdef EHCI_DEBUG 566 ehci_dump_sqh(sqh); 567 #endif 568 569 /* Point to async list */ 570 sc->sc_async_head = sqh; 571 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 572 573 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 574 575 /* Turn on controller */ 576 EOWRITE4(sc, EHCI_USBCMD, 577 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 578 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 579 EHCI_CMD_ASE | 580 EHCI_CMD_PSE | 581 EHCI_CMD_RS); 582 583 /* Take over port ownership */ 584 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 585 586 for (i = 0; i < 100; i++) { 587 usb_delay_ms(&sc->sc_bus, 1); 588 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 589 if (!hcr) 590 break; 591 } 592 if (hcr) { 593 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 594 return EIO; 595 } 596 597 /* Enable interrupts */ 598 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 599 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 600 601 return 0; 602 603 #if 0 604 bad2: 605 ehci_free_sqh(sc, sc->sc_async_head); 606 #endif 607 bad1: 608 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 609 return err; 610 } 611 612 int 613 ehci_intr(void *v) 614 { 615 ehci_softc_t *sc = v; 616 int ret = 0; 617 618 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 619 620 if (sc == NULL) 621 return 0; 622 623 mutex_spin_enter(&sc->sc_intr_lock); 624 625 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 626 goto done; 627 628 /* If we get an interrupt while polling, then just ignore it. */ 629 if (sc->sc_bus.ub_usepolling) { 630 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 631 632 if (intrs) 633 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 634 #ifdef DIAGNOSTIC 635 USBHIST_LOGN(ehcidebug, 16, 636 "ignored interrupt while polling", 0, 0, 0, 0); 637 #endif 638 goto done; 639 } 640 641 ret = ehci_intr1(sc); 642 643 done: 644 mutex_spin_exit(&sc->sc_intr_lock); 645 return ret; 646 } 647 648 Static int 649 ehci_intr1(ehci_softc_t *sc) 650 { 651 uint32_t intrs, eintrs; 652 653 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 654 655 /* In case the interrupt occurs before initialization has completed. */ 656 if (sc == NULL) { 657 #ifdef DIAGNOSTIC 658 printf("ehci_intr1: sc == NULL\n"); 659 #endif 660 return 0; 661 } 662 663 KASSERT(mutex_owned(&sc->sc_intr_lock)); 664 665 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 666 if (!intrs) 667 return 0; 668 669 eintrs = intrs & sc->sc_eintrs; 670 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 671 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 672 if (!eintrs) 673 return 0; 674 675 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 676 if (eintrs & EHCI_STS_IAA) { 677 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 678 kpreempt_disable(); 679 KASSERT(sc->sc_doorbell_si != NULL); 680 softint_schedule(sc->sc_doorbell_si); 681 kpreempt_enable(); 682 eintrs &= ~EHCI_STS_IAA; 683 } 684 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 685 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 686 eintrs & EHCI_STS_INT ? 1 : 0, 687 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 688 usb_schedsoftintr(&sc->sc_bus); 689 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 690 } 691 if (eintrs & EHCI_STS_HSE) { 692 printf("%s: unrecoverable error, controller halted\n", 693 device_xname(sc->sc_dev)); 694 /* XXX what else */ 695 } 696 if (eintrs & EHCI_STS_PCD) { 697 kpreempt_disable(); 698 KASSERT(sc->sc_pcd_si != NULL); 699 softint_schedule(sc->sc_pcd_si); 700 kpreempt_enable(); 701 eintrs &= ~EHCI_STS_PCD; 702 } 703 704 if (eintrs != 0) { 705 /* Block unprocessed interrupts. */ 706 sc->sc_eintrs &= ~eintrs; 707 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 708 printf("%s: blocking intrs 0x%x\n", 709 device_xname(sc->sc_dev), eintrs); 710 } 711 712 return 1; 713 } 714 715 Static void 716 ehci_doorbell(void *addr) 717 { 718 ehci_softc_t *sc = addr; 719 720 mutex_enter(&sc->sc_lock); 721 cv_broadcast(&sc->sc_doorbell); 722 mutex_exit(&sc->sc_lock); 723 } 724 725 Static void 726 ehci_pcd(void *addr) 727 { 728 ehci_softc_t *sc = addr; 729 usbd_xfer_handle xfer; 730 u_char *p; 731 int i, m; 732 733 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 734 735 mutex_enter(&sc->sc_lock); 736 xfer = sc->sc_intrxfer; 737 738 if (xfer == NULL) { 739 /* Just ignore the change. */ 740 goto done; 741 } 742 743 p = xfer->ux_buf; 744 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 745 memset(p, 0, xfer->ux_length); 746 for (i = 1; i <= m; i++) { 747 /* Pick out CHANGE bits from the status reg. */ 748 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 749 p[i/8] |= 1 << (i%8); 750 if (i % 8 == 7) 751 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 752 p[i/8], 0, 0); 753 } 754 xfer->ux_actlen = xfer->ux_length; 755 xfer->ux_status = USBD_NORMAL_COMPLETION; 756 757 usb_transfer_complete(xfer); 758 759 done: 760 mutex_exit(&sc->sc_lock); 761 } 762 763 Static void 764 ehci_softintr(void *v) 765 { 766 struct usbd_bus *bus = v; 767 ehci_softc_t *sc = bus->ub_hcpriv; 768 struct ehci_xfer *ex, *nextex; 769 770 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 771 772 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 773 774 /* 775 * The only explanation I can think of for why EHCI is as brain dead 776 * as UHCI interrupt-wise is that Intel was involved in both. 777 * An interrupt just tells us that something is done, we have no 778 * clue what, so we need to scan through all active transfers. :-( 779 */ 780 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 781 nextex = TAILQ_NEXT(ex, inext); 782 ehci_check_intr(sc, ex); 783 } 784 785 /* Schedule a callout to catch any dropped transactions. */ 786 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 787 !TAILQ_EMPTY(&sc->sc_intrhead)) 788 callout_reset(&sc->sc_tmo_intrlist, 789 hz, ehci_intrlist_timeout, sc); 790 791 if (sc->sc_softwake) { 792 sc->sc_softwake = 0; 793 cv_broadcast(&sc->sc_softwake_cv); 794 } 795 } 796 797 /* Check for an interrupt. */ 798 Static void 799 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 800 { 801 usbd_device_handle dev = ex->xfer.ux_pipe->up_dev; 802 int attr; 803 804 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 805 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 806 807 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 808 809 attr = ex->xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 810 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 811 if (dev->ud_speed == USB_SPEED_HIGH) 812 ehci_check_itd_intr(sc, ex); 813 else 814 ehci_check_sitd_intr(sc, ex); 815 } else 816 ehci_check_qh_intr(sc, ex); 817 818 return; 819 } 820 821 Static void 822 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 823 { 824 ehci_soft_qtd_t *sqtd, *lsqtd; 825 uint32_t status; 826 827 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 828 829 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 830 831 if (ex->sqtdstart == NULL) { 832 printf("ehci_check_qh_intr: not valid sqtd\n"); 833 return; 834 } 835 836 lsqtd = ex->sqtdend; 837 #ifdef DIAGNOSTIC 838 if (lsqtd == NULL) { 839 printf("ehci_check_qh_intr: lsqtd==0\n"); 840 return; 841 } 842 #endif 843 /* 844 * If the last TD is still active we need to check whether there 845 * is an error somewhere in the middle, or whether there was a 846 * short packet (SPD and not ACTIVE). 847 */ 848 usb_syncmem(&lsqtd->dma, 849 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 850 sizeof(lsqtd->qtd.qtd_status), 851 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 852 status = le32toh(lsqtd->qtd.qtd_status); 853 usb_syncmem(&lsqtd->dma, 854 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 855 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 856 if (status & EHCI_QTD_ACTIVE) { 857 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 858 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) { 859 usb_syncmem(&sqtd->dma, 860 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 861 sizeof(sqtd->qtd.qtd_status), 862 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 863 status = le32toh(sqtd->qtd.qtd_status); 864 usb_syncmem(&sqtd->dma, 865 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 866 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 867 /* If there's an active QTD the xfer isn't done. */ 868 if (status & EHCI_QTD_ACTIVE) 869 break; 870 /* Any kind of error makes the xfer done. */ 871 if (status & EHCI_QTD_HALTED) 872 goto done; 873 /* Handle short packets */ 874 if (EHCI_QTD_GET_BYTES(status) != 0) { 875 usbd_pipe_handle pipe = ex->xfer.ux_pipe; 876 usb_endpoint_descriptor_t *ed = 877 pipe->up_endpoint->ue_edesc; 878 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 879 880 /* 881 * If we get here for a control transfer then 882 * we need to let the hardware complete the 883 * status phase. That is, we're not done 884 * quite yet. 885 * 886 * Otherwise, we're done. 887 */ 888 if (xt == UE_CONTROL) { 889 break; 890 } 891 goto done; 892 } 893 } 894 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 895 ex, ex->sqtdstart, 0, 0); 896 return; 897 } 898 done: 899 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 900 callout_stop(&ex->xfer.ux_callout); 901 ehci_idone(ex); 902 } 903 904 Static void 905 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 906 { 907 ehci_soft_itd_t *itd; 908 int i; 909 910 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 911 912 KASSERT(mutex_owned(&sc->sc_lock)); 913 914 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.ux_pipe->up_queue)) 915 return; 916 917 if (ex->itdstart == NULL) { 918 printf("ehci_check_itd_intr: not valid itd\n"); 919 return; 920 } 921 922 itd = ex->itdend; 923 #ifdef DIAGNOSTIC 924 if (itd == NULL) { 925 printf("ehci_check_itd_intr: itdend == 0\n"); 926 return; 927 } 928 #endif 929 930 /* 931 * check no active transfers in last itd, meaning we're finished 932 */ 933 934 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 935 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 936 BUS_DMASYNC_POSTREAD); 937 938 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 939 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 940 break; 941 } 942 943 if (i == EHCI_ITD_NUFRAMES) { 944 goto done; /* All 8 descriptors inactive, it's done */ 945 } 946 947 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 948 ex->itdstart, 0, 0); 949 return; 950 done: 951 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 952 callout_stop(&ex->xfer.ux_callout); 953 ehci_idone(ex); 954 } 955 956 void 957 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 958 { 959 ehci_soft_sitd_t *sitd; 960 961 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 962 963 KASSERT(mutex_owned(&sc->sc_lock)); 964 965 if (&ex->xfer != SIMPLEQ_FIRST(&ex->xfer.ux_pipe->up_queue)) 966 return; 967 968 if (ex->sitdstart == NULL) { 969 printf("ehci_check_sitd_intr: not valid sitd\n"); 970 return; 971 } 972 973 sitd = ex->sitdend; 974 #ifdef DIAGNOSTIC 975 if (sitd == NULL) { 976 printf("ehci_check_sitd_intr: sitdend == 0\n"); 977 return; 978 } 979 #endif 980 981 /* 982 * check no active transfers in last sitd, meaning we're finished 983 */ 984 985 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 986 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 987 BUS_DMASYNC_POSTREAD); 988 989 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 990 return; 991 992 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 993 callout_stop(&(ex->xfer.ux_callout)); 994 ehci_idone(ex); 995 } 996 997 998 Static void 999 ehci_idone(struct ehci_xfer *ex) 1000 { 1001 usbd_xfer_handle xfer = &ex->xfer; 1002 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1003 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1004 ehci_soft_qtd_t *sqtd, *lsqtd; 1005 uint32_t status = 0, nstatus = 0; 1006 int actlen; 1007 1008 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1009 1010 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1011 1012 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1013 1014 #ifdef DIAGNOSTIC 1015 if (ex->isdone) { 1016 printf("ehci_idone: ex=%p is done!\n", ex); 1017 #ifdef EHCI_DEBUG 1018 ehci_dump_exfer(ex); 1019 #endif 1020 return; 1021 } 1022 ex->isdone = 1; 1023 #endif 1024 1025 if (xfer->ux_status == USBD_CANCELLED || 1026 xfer->ux_status == USBD_TIMEOUT) { 1027 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1028 return; 1029 } 1030 1031 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1032 #ifdef EHCI_DEBUG 1033 ehci_dump_sqtds(ex->sqtdstart); 1034 #endif 1035 1036 /* The transfer is done, compute actual length and status. */ 1037 1038 u_int xfertype, speed; 1039 1040 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1041 speed = xfer->ux_pipe->up_dev->ud_speed; 1042 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1043 /* HS isoc transfer */ 1044 1045 struct ehci_soft_itd *itd; 1046 int i, nframes, len, uframes; 1047 1048 nframes = 0; 1049 actlen = 0; 1050 1051 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1052 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1053 1054 for (itd = ex->itdstart; itd != NULL; itd = itd->xfer_next) { 1055 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1056 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1057 BUS_DMASYNC_POSTREAD); 1058 1059 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1060 /* XXX - driver didn't fill in the frame full 1061 * of uframes. This leads to scheduling 1062 * inefficiencies, but working around 1063 * this doubles complexity of tracking 1064 * an xfer. 1065 */ 1066 if (nframes >= xfer->ux_nframes) 1067 break; 1068 1069 status = le32toh(itd->itd.itd_ctl[i]); 1070 len = EHCI_ITD_GET_LEN(status); 1071 if (EHCI_ITD_GET_STATUS(status) != 0) 1072 len = 0; /*No valid data on error*/ 1073 1074 xfer->ux_frlengths[nframes++] = len; 1075 actlen += len; 1076 } 1077 1078 if (nframes >= xfer->ux_nframes) 1079 break; 1080 } 1081 1082 xfer->ux_actlen = actlen; 1083 xfer->ux_status = USBD_NORMAL_COMPLETION; 1084 goto end; 1085 } 1086 1087 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1088 /* FS isoc transfer */ 1089 struct ehci_soft_sitd *sitd; 1090 int nframes, len; 1091 1092 nframes = 0; 1093 actlen = 0; 1094 1095 for (sitd = ex->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1096 usb_syncmem(&sitd->dma,sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 1097 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 1098 BUS_DMASYNC_POSTREAD); 1099 1100 /* XXX - driver didn't fill in the frame full 1101 * of uframes. This leads to scheduling 1102 * inefficiencies, but working around 1103 * this doubles complexity of tracking 1104 * an xfer. 1105 */ 1106 if (nframes >= xfer->ux_nframes) 1107 break; 1108 1109 status = le32toh(sitd->sitd.sitd_trans); 1110 len = EHCI_SITD_GET_LEN(status); 1111 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1112 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1113 /* No valid data on error */ 1114 len = xfer->ux_frlengths[nframes]; 1115 } 1116 1117 /* 1118 * frlengths[i]: # of bytes to send 1119 * len: # of bytes host didn't send 1120 */ 1121 xfer->ux_frlengths[nframes] -= len; 1122 /* frlengths[i]: # of bytes host sent */ 1123 actlen += xfer->ux_frlengths[nframes++]; 1124 1125 if (nframes >= xfer->ux_nframes) 1126 break; 1127 } 1128 1129 xfer->ux_actlen = actlen; 1130 xfer->ux_status = USBD_NORMAL_COMPLETION; 1131 goto end; 1132 } 1133 KASSERT(xfertype != UE_ISOCHRONOUS); 1134 1135 /* Continue processing xfers using queue heads */ 1136 1137 lsqtd = ex->sqtdend; 1138 actlen = 0; 1139 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd; 1140 sqtd = sqtd->nextqtd) { 1141 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1142 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1143 nstatus = le32toh(sqtd->qtd.qtd_status); 1144 if (nstatus & EHCI_QTD_ACTIVE) 1145 break; 1146 1147 status = nstatus; 1148 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1149 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1150 } 1151 1152 1153 /* 1154 * If there are left over TDs we need to update the toggle. 1155 * The default pipe doesn't need it since control transfers 1156 * start the toggle at 0 every time. 1157 * For a short transfer we need to update the toggle for the missing 1158 * packets within the qTD. 1159 */ 1160 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1161 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1162 USBHIST_LOG(ehcidebug, 1163 "toggle update status=0x%08x nstatus=0x%08x", 1164 status, nstatus, 0, 0); 1165 #if 0 1166 ehci_dump_sqh(epipe->sqh); 1167 ehci_dump_sqtds(ex->sqtdstart); 1168 #endif 1169 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1170 } 1171 1172 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1173 actlen, status, 0); 1174 xfer->ux_actlen = actlen; 1175 if (status & EHCI_QTD_HALTED) { 1176 #ifdef EHCI_DEBUG 1177 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1178 xfer->ux_pipe->up_dev->ud_addr, 1179 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1180 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d stat=%#x", 1181 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1182 status, 0); 1183 USBHIST_LOG(ehcidebug, 1184 "active =%d halted=%d buferr=%d babble=%d", 1185 status & EHCI_QTD_ACTIVE ? 1 : 0, 1186 status & EHCI_QTD_HALTED ? 1 : 0, 1187 status & EHCI_QTD_BUFERR ? 1 : 0, 1188 status & EHCI_QTD_BABBLE ? 1 : 0); 1189 1190 USBHIST_LOG(ehcidebug, 1191 "xacterr=%d missed=%d split =%d ping =%d", 1192 status & EHCI_QTD_XACTERR ? 1 : 0, 1193 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1194 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1195 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1196 1197 ehci_dump_sqh(epipe->sqh); 1198 ehci_dump_sqtds(ex->sqtdstart); 1199 #endif 1200 /* low&full speed has an extra error flag */ 1201 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1202 EHCI_QH_SPEED_HIGH) 1203 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1204 else 1205 status &= EHCI_QTD_STATERRS; 1206 if (status == 0) /* no other errors means a stall */ { 1207 xfer->ux_status = USBD_STALLED; 1208 } else { 1209 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1210 } 1211 /* XXX need to reset TT on missed microframe */ 1212 if (status & EHCI_QTD_MISSEDMICRO) { 1213 printf("%s: missed microframe, TT reset not " 1214 "implemented, hub might be inoperational\n", 1215 device_xname(sc->sc_dev)); 1216 } 1217 } else { 1218 xfer->ux_status = USBD_NORMAL_COMPLETION; 1219 } 1220 1221 end: 1222 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1223 * during this call, before methods->done is called: dma sync required 1224 * beforehand? */ 1225 usb_transfer_complete(xfer); 1226 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1227 } 1228 1229 /* 1230 * Wait here until controller claims to have an interrupt. 1231 * Then call ehci_intr and return. Use timeout to avoid waiting 1232 * too long. 1233 */ 1234 Static void 1235 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1236 { 1237 int timo; 1238 uint32_t intrs; 1239 1240 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1241 1242 xfer->ux_status = USBD_IN_PROGRESS; 1243 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1244 usb_delay_ms(&sc->sc_bus, 1); 1245 if (sc->sc_dying) 1246 break; 1247 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1248 sc->sc_eintrs; 1249 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1250 #ifdef EHCI_DEBUG 1251 if (ehcidebug > 15) 1252 ehci_dump_regs(sc); 1253 #endif 1254 if (intrs) { 1255 mutex_spin_enter(&sc->sc_intr_lock); 1256 ehci_intr1(sc); 1257 mutex_spin_exit(&sc->sc_intr_lock); 1258 if (xfer->ux_status != USBD_IN_PROGRESS) 1259 return; 1260 } 1261 } 1262 1263 /* Timeout */ 1264 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1265 xfer->ux_status = USBD_TIMEOUT; 1266 mutex_enter(&sc->sc_lock); 1267 usb_transfer_complete(xfer); 1268 mutex_exit(&sc->sc_lock); 1269 /* XXX should free TD */ 1270 } 1271 1272 Static void 1273 ehci_poll(struct usbd_bus *bus) 1274 { 1275 ehci_softc_t *sc = bus->ub_hcpriv; 1276 1277 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1278 1279 #ifdef EHCI_DEBUG 1280 static int last; 1281 int new; 1282 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1283 if (new != last) { 1284 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1285 last = new; 1286 } 1287 #endif 1288 1289 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1290 mutex_spin_enter(&sc->sc_intr_lock); 1291 ehci_intr1(sc); 1292 mutex_spin_exit(&sc->sc_intr_lock); 1293 } 1294 } 1295 1296 void 1297 ehci_childdet(device_t self, device_t child) 1298 { 1299 struct ehci_softc *sc = device_private(self); 1300 1301 KASSERT(sc->sc_child == child); 1302 sc->sc_child = NULL; 1303 } 1304 1305 int 1306 ehci_detach(struct ehci_softc *sc, int flags) 1307 { 1308 int rv = 0; 1309 1310 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1311 1312 if (sc->sc_child != NULL) 1313 rv = config_detach(sc->sc_child, flags); 1314 1315 if (rv != 0) 1316 return rv; 1317 1318 callout_halt(&sc->sc_tmo_intrlist, NULL); 1319 callout_destroy(&sc->sc_tmo_intrlist); 1320 1321 /* XXX free other data structures XXX */ 1322 if (sc->sc_softitds) 1323 kmem_free(sc->sc_softitds, 1324 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1325 cv_destroy(&sc->sc_doorbell); 1326 cv_destroy(&sc->sc_softwake_cv); 1327 1328 #if 0 1329 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1330 1331 softint_disestablish(sc->sc_doorbell_si); 1332 softint_disestablish(sc->sc_pcd_si); 1333 1334 mutex_destroy(&sc->sc_lock); 1335 mutex_destroy(&sc->sc_intr_lock); 1336 #endif 1337 1338 pool_cache_destroy(sc->sc_xferpool); 1339 1340 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1341 1342 return rv; 1343 } 1344 1345 1346 int 1347 ehci_activate(device_t self, enum devact act) 1348 { 1349 struct ehci_softc *sc = device_private(self); 1350 1351 switch (act) { 1352 case DVACT_DEACTIVATE: 1353 sc->sc_dying = 1; 1354 return 0; 1355 default: 1356 return EOPNOTSUPP; 1357 } 1358 } 1359 1360 /* 1361 * Handle suspend/resume. 1362 * 1363 * We need to switch to polling mode here, because this routine is 1364 * called from an interrupt context. This is all right since we 1365 * are almost suspended anyway. 1366 * 1367 * Note that this power handler isn't to be registered directly; the 1368 * bus glue needs to call out to it. 1369 */ 1370 bool 1371 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1372 { 1373 ehci_softc_t *sc = device_private(dv); 1374 int i; 1375 uint32_t cmd, hcr; 1376 1377 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1378 1379 mutex_spin_enter(&sc->sc_intr_lock); 1380 sc->sc_bus.ub_usepolling++; 1381 mutex_spin_exit(&sc->sc_intr_lock); 1382 1383 for (i = 1; i <= sc->sc_noport; i++) { 1384 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1385 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1386 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1387 } 1388 1389 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1390 1391 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1392 EOWRITE4(sc, EHCI_USBCMD, cmd); 1393 1394 for (i = 0; i < 100; i++) { 1395 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1396 if (hcr == 0) 1397 break; 1398 1399 usb_delay_ms(&sc->sc_bus, 1); 1400 } 1401 if (hcr != 0) 1402 printf("%s: reset timeout\n", device_xname(dv)); 1403 1404 cmd &= ~EHCI_CMD_RS; 1405 EOWRITE4(sc, EHCI_USBCMD, cmd); 1406 1407 for (i = 0; i < 100; i++) { 1408 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1409 if (hcr == EHCI_STS_HCH) 1410 break; 1411 1412 usb_delay_ms(&sc->sc_bus, 1); 1413 } 1414 if (hcr != EHCI_STS_HCH) 1415 printf("%s: config timeout\n", device_xname(dv)); 1416 1417 mutex_spin_enter(&sc->sc_intr_lock); 1418 sc->sc_bus.ub_usepolling--; 1419 mutex_spin_exit(&sc->sc_intr_lock); 1420 1421 return true; 1422 } 1423 1424 bool 1425 ehci_resume(device_t dv, const pmf_qual_t *qual) 1426 { 1427 ehci_softc_t *sc = device_private(dv); 1428 int i; 1429 uint32_t cmd, hcr; 1430 1431 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1432 1433 /* restore things in case the bios sucks */ 1434 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1435 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1436 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1437 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1438 1439 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1440 1441 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1442 1443 hcr = 0; 1444 for (i = 1; i <= sc->sc_noport; i++) { 1445 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1446 if ((cmd & EHCI_PS_PO) == 0 && 1447 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1448 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1449 hcr = 1; 1450 } 1451 } 1452 1453 if (hcr) { 1454 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1455 1456 for (i = 1; i <= sc->sc_noport; i++) { 1457 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1458 if ((cmd & EHCI_PS_PO) == 0 && 1459 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1460 EOWRITE4(sc, EHCI_PORTSC(i), 1461 cmd & ~EHCI_PS_FPR); 1462 } 1463 } 1464 1465 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1466 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1467 1468 for (i = 0; i < 100; i++) { 1469 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1470 if (hcr != EHCI_STS_HCH) 1471 break; 1472 1473 usb_delay_ms(&sc->sc_bus, 1); 1474 } 1475 if (hcr == EHCI_STS_HCH) 1476 printf("%s: config timeout\n", device_xname(dv)); 1477 1478 return true; 1479 } 1480 1481 /* 1482 * Shut down the controller when the system is going down. 1483 */ 1484 bool 1485 ehci_shutdown(device_t self, int flags) 1486 { 1487 ehci_softc_t *sc = device_private(self); 1488 1489 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1490 1491 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1492 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1493 return true; 1494 } 1495 1496 Static usbd_xfer_handle 1497 ehci_allocx(struct usbd_bus *bus) 1498 { 1499 struct ehci_softc *sc = bus->ub_hcpriv; 1500 usbd_xfer_handle xfer; 1501 1502 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1503 if (xfer != NULL) { 1504 memset(xfer, 0, sizeof(struct ehci_xfer)); 1505 #ifdef DIAGNOSTIC 1506 EXFER(xfer)->isdone = 1; 1507 xfer->ux_state = XFER_BUSY; 1508 #endif 1509 } 1510 return xfer; 1511 } 1512 1513 Static void 1514 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1515 { 1516 struct ehci_softc *sc = bus->ub_hcpriv; 1517 1518 #ifdef DIAGNOSTIC 1519 if (xfer->ux_state != XFER_BUSY) { 1520 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1521 xfer->ux_state); 1522 } 1523 xfer->ux_state = XFER_FREE; 1524 if (!EXFER(xfer)->isdone) { 1525 printf("ehci_freex: !isdone\n"); 1526 } 1527 #endif 1528 pool_cache_put(sc->sc_xferpool, xfer); 1529 } 1530 1531 Static void 1532 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1533 { 1534 struct ehci_softc *sc = bus->ub_hcpriv; 1535 1536 *lock = &sc->sc_lock; 1537 } 1538 1539 Static void 1540 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1541 { 1542 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1543 1544 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1545 1546 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1547 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1548 #ifdef EHCI_DEBUG 1549 if (ehcidebug) 1550 usbd_dump_pipe(pipe); 1551 #endif 1552 epipe->nexttoggle = 0; 1553 } 1554 1555 Static void 1556 ehci_noop(usbd_pipe_handle pipe) 1557 { 1558 } 1559 1560 #ifdef EHCI_DEBUG 1561 /* 1562 * Unused function - this is meant to be called from a kernel 1563 * debugger. 1564 */ 1565 void 1566 ehci_dump(void) 1567 { 1568 ehci_softc_t *sc = theehci; 1569 int i; 1570 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1571 EOREAD4(sc, EHCI_USBCMD), 1572 EOREAD4(sc, EHCI_USBSTS), 1573 EOREAD4(sc, EHCI_USBINTR)); 1574 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1575 EOREAD4(sc, EHCI_FRINDEX), 1576 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1577 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1578 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1579 for (i = 1; i <= sc->sc_noport; i++) 1580 printf("port %d status=0x%08x\n", i, 1581 EOREAD4(sc, EHCI_PORTSC(i))); 1582 } 1583 1584 Static void 1585 ehci_dump_regs(ehci_softc_t *sc) 1586 { 1587 int i; 1588 1589 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1590 1591 USBHIST_LOG(ehcidebug, 1592 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1593 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1594 EOREAD4(sc, EHCI_USBINTR), 0); 1595 USBHIST_LOG(ehcidebug, 1596 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1597 "async = 0x%08x", 1598 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1599 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1600 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1601 for (i = 1; i <= sc->sc_noport; i += 2) { 1602 if (i == sc->sc_noport) { 1603 USBHIST_LOG(ehcidebug, 1604 "port %d status = 0x%08x", i, 1605 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1606 } else { 1607 USBHIST_LOG(ehcidebug, 1608 "port %d status = 0x%08x port %d status = 0x%08x", 1609 i, EOREAD4(sc, EHCI_PORTSC(i)), 1610 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1611 } 1612 } 1613 } 1614 1615 #ifdef EHCI_DEBUG 1616 #define ehci_dump_link(link, type) do { \ 1617 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1618 link, \ 1619 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1620 if (type) { \ 1621 USBHIST_LOG(ehcidebug, \ 1622 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1623 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1624 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1625 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1626 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1627 } \ 1628 } while(0) 1629 #else 1630 #define ehci_dump_link(link, type) 1631 #endif 1632 1633 Static void 1634 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1635 { 1636 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1637 int i; 1638 uint32_t stop = 0; 1639 1640 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1641 ehci_dump_sqtd(sqtd); 1642 usb_syncmem(&sqtd->dma, 1643 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1644 sizeof(sqtd->qtd), 1645 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1646 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1647 usb_syncmem(&sqtd->dma, 1648 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1649 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1650 } 1651 if (sqtd) 1652 USBHIST_LOG(ehcidebug, 1653 "dump aborted, too many TDs", 0, 0, 0, 0); 1654 } 1655 1656 Static void 1657 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1658 { 1659 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1660 1661 usb_syncmem(&sqtd->dma, sqtd->offs, 1662 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1663 1664 USBHIST_LOGN(ehcidebug, 10, 1665 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1666 ehci_dump_qtd(&sqtd->qtd); 1667 1668 usb_syncmem(&sqtd->dma, sqtd->offs, 1669 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1670 } 1671 1672 Static void 1673 ehci_dump_qtd(ehci_qtd_t *qtd) 1674 { 1675 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1676 1677 #ifdef USBHIST 1678 uint32_t s = le32toh(qtd->qtd_status); 1679 #endif 1680 1681 USBHIST_LOGN(ehcidebug, 10, 1682 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1683 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1684 USBHIST_LOGN(ehcidebug, 10, 1685 " toggle = %d ioc = %d bytes = %#x " 1686 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1687 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1688 USBHIST_LOGN(ehcidebug, 10, 1689 " cerr = %d pid = %d stat = %x", 1690 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1691 0); 1692 USBHIST_LOGN(ehcidebug, 10, 1693 "active =%d halted=%d buferr=%d babble=%d", 1694 s & EHCI_QTD_ACTIVE ? 1 : 0, 1695 s & EHCI_QTD_HALTED ? 1 : 0, 1696 s & EHCI_QTD_BUFERR ? 1 : 0, 1697 s & EHCI_QTD_BABBLE ? 1 : 0); 1698 USBHIST_LOGN(ehcidebug, 10, 1699 "xacterr=%d missed=%d split =%d ping =%d", 1700 s & EHCI_QTD_XACTERR ? 1 : 0, 1701 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1702 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1703 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1704 USBHIST_LOGN(ehcidebug, 10, 1705 "buffer[0] = %#x buffer[1] = %#x " 1706 "buffer[2] = %#x buffer[3] = %#x", 1707 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1708 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1709 USBHIST_LOGN(ehcidebug, 10, 1710 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1711 } 1712 1713 Static void 1714 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1715 { 1716 #ifdef USBHIST 1717 ehci_qh_t *qh = &sqh->qh; 1718 ehci_link_t link; 1719 #endif 1720 uint32_t endp, endphub; 1721 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1722 1723 usb_syncmem(&sqh->dma, sqh->offs, 1724 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1725 1726 USBHIST_LOGN(ehcidebug, 10, 1727 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1728 link = le32toh(qh->qh_link); 1729 ehci_dump_link(link, true); 1730 1731 endp = le32toh(qh->qh_endp); 1732 USBHIST_LOGN(ehcidebug, 10, 1733 " endp = %#x", endp, 0, 0, 0); 1734 USBHIST_LOGN(ehcidebug, 10, 1735 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1736 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1737 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1738 USBHIST_LOGN(ehcidebug, 10, 1739 " dtc = %d hrecl = %d", 1740 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1741 USBHIST_LOGN(ehcidebug, 10, 1742 " ctl = %d nrl = %d mpl = %#x(%d)", 1743 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1744 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1745 1746 endphub = le32toh(qh->qh_endphub); 1747 USBHIST_LOGN(ehcidebug, 10, 1748 " endphub = %#x", endphub, 0, 0, 0); 1749 USBHIST_LOGN(ehcidebug, 10, 1750 " smask = 0x%02x cmask = 0x%02x", 1751 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1752 USBHIST_LOGN(ehcidebug, 10, 1753 " huba = 0x%02x port = %d mult = %d", 1754 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1755 EHCI_QH_GET_MULT(endphub), 0); 1756 1757 link = le32toh(qh->qh_curqtd); 1758 ehci_dump_link(link, false); 1759 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1760 ehci_dump_qtd(&qh->qh_qtd); 1761 1762 usb_syncmem(&sqh->dma, sqh->offs, 1763 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1764 } 1765 1766 Static void 1767 ehci_dump_itd(struct ehci_soft_itd *itd) 1768 { 1769 ehci_isoc_trans_t t; 1770 ehci_isoc_bufr_ptr_t b, b2, b3; 1771 int i; 1772 1773 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1774 1775 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1776 0, 0); 1777 1778 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1779 t = le32toh(itd->itd.itd_ctl[i]); 1780 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1781 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1782 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1783 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1784 EHCI_ITD_GET_OFFS(t), 0); 1785 } 1786 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1787 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1788 USBHIST_LOG(ehcidebug, " %x", 1789 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1790 1791 b = le32toh(itd->itd.itd_bufr[0]); 1792 b2 = le32toh(itd->itd.itd_bufr[1]); 1793 b3 = le32toh(itd->itd.itd_bufr[2]); 1794 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1795 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1796 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1797 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1798 } 1799 1800 Static void 1801 ehci_dump_sitd(struct ehci_soft_itd *itd) 1802 { 1803 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1804 1805 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1806 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1807 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1808 itd->xfer_next, itd->physaddr, itd->slot, 0); 1809 } 1810 1811 Static void 1812 ehci_dump_exfer(struct ehci_xfer *ex) 1813 { 1814 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1815 1816 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1817 ex, ex->sqtdstart, ex->sqtdend, 0); 1818 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1819 ex->itdstart, ex->itdend, ex->isdone, 0); 1820 } 1821 #endif 1822 1823 Static usbd_status 1824 ehci_open(usbd_pipe_handle pipe) 1825 { 1826 usbd_device_handle dev = pipe->up_dev; 1827 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1828 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1829 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1830 uint8_t addr = dev->ud_addr; 1831 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1832 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1833 ehci_soft_qh_t *sqh; 1834 usbd_status err; 1835 int ival, speed, naks; 1836 int hshubaddr, hshubport; 1837 1838 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1839 1840 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1841 pipe, addr, ed->bEndpointAddress, rhaddr); 1842 1843 if (dev->ud_myhsport) { 1844 /* 1845 * When directly attached FS/LS device while doing embedded 1846 * transaction translations and we are the hub, set the hub 1847 * address to 0 (us). 1848 */ 1849 if (!(sc->sc_flags & EHCIF_ETTF) 1850 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1851 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1852 } else { 1853 hshubaddr = 0; 1854 } 1855 hshubport = dev->ud_myhsport->up_portno; 1856 } else { 1857 hshubaddr = 0; 1858 hshubport = 0; 1859 } 1860 1861 if (sc->sc_dying) 1862 return USBD_IOERROR; 1863 1864 /* toggle state needed for bulk endpoints */ 1865 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1866 1867 if (addr == rhaddr) { 1868 switch (ed->bEndpointAddress) { 1869 case USB_CONTROL_ENDPOINT: 1870 pipe->up_methods = &roothub_ctrl_methods; 1871 break; 1872 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1873 pipe->up_methods = &ehci_root_intr_methods; 1874 break; 1875 default: 1876 USBHIST_LOG(ehcidebug, 1877 "bad bEndpointAddress 0x%02x", 1878 ed->bEndpointAddress, 0, 0, 0); 1879 return USBD_INVAL; 1880 } 1881 return USBD_NORMAL_COMPLETION; 1882 } 1883 1884 /* XXX All this stuff is only valid for async. */ 1885 switch (dev->ud_speed) { 1886 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1887 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1888 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1889 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1890 } 1891 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1892 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1893 hshubaddr, hshubport, 0, 0); 1894 return USBD_INVAL; 1895 } 1896 1897 /* 1898 * For interrupt transfer, nak throttling must be disabled, but for 1899 * the other transfer type, nak throttling should be enabled from the 1900 * viewpoint that avoids the memory thrashing. 1901 */ 1902 naks = (xfertype == UE_INTERRUPT) ? 0 1903 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1904 1905 /* Allocate sqh for everything, save isoc xfers */ 1906 if (xfertype != UE_ISOCHRONOUS) { 1907 sqh = ehci_alloc_sqh(sc); 1908 if (sqh == NULL) 1909 return USBD_NOMEM; 1910 /* qh_link filled when the QH is added */ 1911 sqh->qh.qh_endp = htole32( 1912 EHCI_QH_SET_ADDR(addr) | 1913 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1914 EHCI_QH_SET_EPS(speed) | 1915 EHCI_QH_DTC | 1916 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1917 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1918 EHCI_QH_CTL : 0) | 1919 EHCI_QH_SET_NRL(naks) 1920 ); 1921 sqh->qh.qh_endphub = htole32( 1922 EHCI_QH_SET_MULT(1) | 1923 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1924 ); 1925 if (speed != EHCI_QH_SPEED_HIGH) 1926 sqh->qh.qh_endphub |= htole32( 1927 EHCI_QH_SET_PORT(hshubport) | 1928 EHCI_QH_SET_HUBA(hshubaddr) | 1929 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1930 ); 1931 sqh->qh.qh_curqtd = EHCI_NULL; 1932 /* Fill the overlay qTD */ 1933 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1934 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1935 sqh->qh.qh_qtd.qtd_status = htole32(0); 1936 1937 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1938 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1939 epipe->sqh = sqh; 1940 } else { 1941 sqh = NULL; 1942 } /*xfertype == UE_ISOC*/ 1943 1944 switch (xfertype) { 1945 case UE_CONTROL: 1946 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1947 0, &epipe->u.ctl.reqdma); 1948 #ifdef EHCI_DEBUG 1949 if (err) 1950 printf("ehci_open: usb_allocmem()=%d\n", err); 1951 #endif 1952 if (err) 1953 goto bad; 1954 pipe->up_methods = &ehci_device_ctrl_methods; 1955 mutex_enter(&sc->sc_lock); 1956 ehci_add_qh(sc, sqh, sc->sc_async_head); 1957 mutex_exit(&sc->sc_lock); 1958 break; 1959 case UE_BULK: 1960 pipe->up_methods = &ehci_device_bulk_methods; 1961 mutex_enter(&sc->sc_lock); 1962 ehci_add_qh(sc, sqh, sc->sc_async_head); 1963 mutex_exit(&sc->sc_lock); 1964 break; 1965 case UE_INTERRUPT: 1966 pipe->up_methods = &ehci_device_intr_methods; 1967 ival = pipe->up_interval; 1968 if (ival == USBD_DEFAULT_INTERVAL) { 1969 if (speed == EHCI_QH_SPEED_HIGH) { 1970 if (ed->bInterval > 16) { 1971 /* 1972 * illegal with high-speed, but there 1973 * were documentation bugs in the spec, 1974 * so be generous 1975 */ 1976 ival = 256; 1977 } else 1978 ival = (1 << (ed->bInterval - 1)) / 8; 1979 } else 1980 ival = ed->bInterval; 1981 } 1982 err = ehci_device_setintr(sc, sqh, ival); 1983 if (err) 1984 goto bad; 1985 break; 1986 case UE_ISOCHRONOUS: 1987 if (speed == EHCI_QH_SPEED_HIGH) 1988 pipe->up_methods = &ehci_device_isoc_methods; 1989 else 1990 pipe->up_methods = &ehci_device_fs_isoc_methods; 1991 if (ed->bInterval == 0 || ed->bInterval > 16) { 1992 printf("ehci: opening pipe with invalid bInterval\n"); 1993 err = USBD_INVAL; 1994 goto bad; 1995 } 1996 if (UGETW(ed->wMaxPacketSize) == 0) { 1997 printf("ehci: zero length endpoint open request\n"); 1998 err = USBD_INVAL; 1999 goto bad; 2000 } 2001 epipe->u.isoc.next_frame = 0; 2002 epipe->u.isoc.cur_xfers = 0; 2003 break; 2004 default: 2005 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2006 err = USBD_INVAL; 2007 goto bad; 2008 } 2009 return USBD_NORMAL_COMPLETION; 2010 2011 bad: 2012 if (sqh != NULL) 2013 ehci_free_sqh(sc, sqh); 2014 return err; 2015 } 2016 2017 /* 2018 * Add an ED to the schedule. Called with USB lock held. 2019 */ 2020 Static void 2021 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2022 { 2023 2024 KASSERT(mutex_owned(&sc->sc_lock)); 2025 2026 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2027 2028 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2029 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2030 2031 sqh->next = head->next; 2032 sqh->qh.qh_link = head->qh.qh_link; 2033 2034 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2035 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2036 2037 head->next = sqh; 2038 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2039 2040 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2041 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2042 2043 #ifdef EHCI_DEBUG 2044 ehci_dump_sqh(sqh); 2045 #endif 2046 } 2047 2048 /* 2049 * Remove an ED from the schedule. Called with USB lock held. 2050 */ 2051 Static void 2052 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2053 { 2054 ehci_soft_qh_t *p; 2055 2056 KASSERT(mutex_owned(&sc->sc_lock)); 2057 2058 /* XXX */ 2059 for (p = head; p != NULL && p->next != sqh; p = p->next) 2060 ; 2061 if (p == NULL) 2062 panic("ehci_rem_qh: ED not found"); 2063 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2064 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2065 p->next = sqh->next; 2066 p->qh.qh_link = sqh->qh.qh_link; 2067 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2068 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2069 2070 ehci_sync_hc(sc); 2071 } 2072 2073 Static void 2074 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2075 { 2076 int i; 2077 uint32_t status; 2078 2079 /* Save toggle bit and ping status. */ 2080 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2081 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2082 status = sqh->qh.qh_qtd.qtd_status & 2083 htole32(EHCI_QTD_TOGGLE_MASK | 2084 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2085 /* Set HALTED to make hw leave it alone. */ 2086 sqh->qh.qh_qtd.qtd_status = 2087 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2088 usb_syncmem(&sqh->dma, 2089 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2090 sizeof(sqh->qh.qh_qtd.qtd_status), 2091 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2092 sqh->qh.qh_curqtd = 0; 2093 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2094 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2095 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2096 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2097 sqh->sqtd = sqtd; 2098 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2099 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2100 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2101 sqh->qh.qh_qtd.qtd_status = status; 2102 usb_syncmem(&sqh->dma, 2103 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2104 sizeof(sqh->qh.qh_qtd.qtd_status), 2105 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2106 } 2107 2108 /* 2109 * Ensure that the HC has released all references to the QH. We do this 2110 * by asking for a Async Advance Doorbell interrupt and then we wait for 2111 * the interrupt. 2112 * To make this easier we first obtain exclusive use of the doorbell. 2113 */ 2114 Static void 2115 ehci_sync_hc(ehci_softc_t *sc) 2116 { 2117 int error __diagused; 2118 2119 KASSERT(mutex_owned(&sc->sc_lock)); 2120 2121 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2122 2123 if (sc->sc_dying) { 2124 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2125 return; 2126 } 2127 /* ask for doorbell */ 2128 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2129 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2130 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2131 2132 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2133 2134 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2135 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2136 #ifdef DIAGNOSTIC 2137 if (error) 2138 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2139 #endif 2140 } 2141 2142 Static void 2143 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2144 { 2145 struct ehci_soft_itd *itd, *prev; 2146 2147 prev = NULL; 2148 2149 if (exfer->itdstart == NULL || exfer->itdend == NULL) 2150 panic("ehci isoc xfer being freed, but with no itd chain\n"); 2151 2152 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2153 prev = itd->u.frame_list.prev; 2154 /* Unlink itd from hardware chain, or frame array */ 2155 if (prev == NULL) { /* We're at the table head */ 2156 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2157 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2158 usb_syncmem(&sc->sc_fldma, 2159 sizeof(ehci_link_t) * itd->slot, 2160 sizeof(ehci_link_t), 2161 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2162 2163 if (itd->u.frame_list.next != NULL) 2164 itd->u.frame_list.next->u.frame_list.prev = NULL; 2165 } else { 2166 /* XXX this part is untested... */ 2167 prev->itd.itd_next = itd->itd.itd_next; 2168 usb_syncmem(&itd->dma, 2169 itd->offs + offsetof(ehci_itd_t, itd_next), 2170 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2171 2172 prev->u.frame_list.next = itd->u.frame_list.next; 2173 if (itd->u.frame_list.next != NULL) 2174 itd->u.frame_list.next->u.frame_list.prev = prev; 2175 } 2176 } 2177 2178 prev = NULL; 2179 for (itd = exfer->itdstart; itd != NULL; itd = itd->xfer_next) { 2180 if (prev != NULL) 2181 ehci_free_itd(sc, prev); 2182 prev = itd; 2183 } 2184 if (prev) 2185 ehci_free_itd(sc, prev); 2186 exfer->itdstart = NULL; 2187 exfer->itdend = NULL; 2188 } 2189 2190 Static void 2191 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2192 { 2193 struct ehci_soft_sitd *sitd, *prev; 2194 2195 prev = NULL; 2196 2197 if (exfer->sitdstart == NULL || exfer->sitdend == NULL) 2198 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2199 2200 for (sitd = exfer->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2201 prev = sitd->u.frame_list.prev; 2202 /* Unlink sitd from hardware chain, or frame array */ 2203 if (prev == NULL) { /* We're at the table head */ 2204 sc->sc_softsitds[sitd->slot] = sitd->u.frame_list.next; 2205 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2206 usb_syncmem(&sc->sc_fldma, 2207 sizeof(ehci_link_t) * sitd->slot, 2208 sizeof(ehci_link_t), 2209 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2210 2211 if (sitd->u.frame_list.next != NULL) 2212 sitd->u.frame_list.next->u.frame_list.prev = NULL; 2213 } else { 2214 /* XXX this part is untested... */ 2215 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2216 usb_syncmem(&sitd->dma, 2217 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2218 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2219 2220 prev->u.frame_list.next = sitd->u.frame_list.next; 2221 if (sitd->u.frame_list.next != NULL) 2222 sitd->u.frame_list.next->u.frame_list.prev = prev; 2223 } 2224 } 2225 2226 prev = NULL; 2227 for (sitd = exfer->sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2228 if (prev != NULL) 2229 ehci_free_sitd(sc, prev); 2230 prev = sitd; 2231 } 2232 if (prev) 2233 ehci_free_sitd(sc, prev); 2234 exfer->sitdstart = NULL; 2235 exfer->sitdend = NULL; 2236 } 2237 2238 /***********/ 2239 2240 Static int 2241 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2242 void *buf, int buflen) 2243 { 2244 ehci_softc_t *sc = bus->ub_hcpriv; 2245 usb_hub_descriptor_t hubd; 2246 usb_port_status_t ps; 2247 uint16_t len, value, index; 2248 int l, totlen = 0; 2249 int port, i; 2250 uint32_t v; 2251 2252 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2253 2254 if (sc->sc_dying) 2255 return -1; 2256 2257 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2258 req->bmRequestType, req->bRequest, 0, 0); 2259 2260 len = UGETW(req->wLength); 2261 value = UGETW(req->wValue); 2262 index = UGETW(req->wIndex); 2263 2264 #define C(x,y) ((x) | ((y) << 8)) 2265 switch (C(req->bRequest, req->bmRequestType)) { 2266 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2267 if (len == 0) 2268 break; 2269 switch (value) { 2270 case C(0, UDESC_DEVICE): { 2271 usb_device_descriptor_t devd; 2272 totlen = min(buflen, sizeof(devd)); 2273 memcpy(&devd, buf, totlen); 2274 USETW(devd.idVendor, sc->sc_id_vendor); 2275 memcpy(buf, &devd, totlen); 2276 break; 2277 2278 } 2279 #define sd ((usb_string_descriptor_t *)buf) 2280 case C(1, UDESC_STRING): 2281 /* Vendor */ 2282 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2283 break; 2284 case C(2, UDESC_STRING): 2285 /* Product */ 2286 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2287 break; 2288 #undef sd 2289 default: 2290 /* default from usbroothub */ 2291 return buflen; 2292 } 2293 break; 2294 2295 /* Hub requests */ 2296 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2297 break; 2298 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2299 USBHIST_LOG(ehcidebug, 2300 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2301 0, 0); 2302 if (index < 1 || index > sc->sc_noport) { 2303 return -1; 2304 } 2305 port = EHCI_PORTSC(index); 2306 v = EOREAD4(sc, port); 2307 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2308 v &= ~EHCI_PS_CLEAR; 2309 switch (value) { 2310 case UHF_PORT_ENABLE: 2311 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2312 break; 2313 case UHF_PORT_SUSPEND: 2314 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2315 break; 2316 v &= ~EHCI_PS_SUSP; 2317 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2318 /* see USB2 spec ch. 7.1.7.7 */ 2319 usb_delay_ms(&sc->sc_bus, 20); 2320 EOWRITE4(sc, port, v); 2321 usb_delay_ms(&sc->sc_bus, 2); 2322 #ifdef DEBUG 2323 v = EOREAD4(sc, port); 2324 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2325 printf("ehci: resume failed: %x\n", v); 2326 #endif 2327 break; 2328 case UHF_PORT_POWER: 2329 if (sc->sc_hasppc) 2330 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2331 break; 2332 case UHF_PORT_TEST: 2333 USBHIST_LOG(ehcidebug, "clear port test " 2334 "%d", index, 0, 0, 0); 2335 break; 2336 case UHF_PORT_INDICATOR: 2337 USBHIST_LOG(ehcidebug, "clear port ind " 2338 "%d", index, 0, 0, 0); 2339 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2340 break; 2341 case UHF_C_PORT_CONNECTION: 2342 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2343 break; 2344 case UHF_C_PORT_ENABLE: 2345 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2346 break; 2347 case UHF_C_PORT_SUSPEND: 2348 /* how? */ 2349 break; 2350 case UHF_C_PORT_OVER_CURRENT: 2351 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2352 break; 2353 case UHF_C_PORT_RESET: 2354 sc->sc_isreset[index] = 0; 2355 break; 2356 default: 2357 return -1; 2358 } 2359 #if 0 2360 switch(value) { 2361 case UHF_C_PORT_CONNECTION: 2362 case UHF_C_PORT_ENABLE: 2363 case UHF_C_PORT_SUSPEND: 2364 case UHF_C_PORT_OVER_CURRENT: 2365 case UHF_C_PORT_RESET: 2366 default: 2367 break; 2368 } 2369 #endif 2370 break; 2371 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2372 if (len == 0) 2373 break; 2374 if ((value & 0xff) != 0) { 2375 return -1; 2376 } 2377 totlen = min(buflen, sizeof(hubd)); 2378 memcpy(&hubd, buf, totlen); 2379 hubd.bNbrPorts = sc->sc_noport; 2380 v = EOREAD4(sc, EHCI_HCSPARAMS); 2381 USETW(hubd.wHubCharacteristics, 2382 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2383 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2384 ? UHD_PORT_IND : 0); 2385 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2386 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2387 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2388 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2389 totlen = min(totlen, hubd.bDescLength); 2390 memcpy(buf, &hubd, totlen); 2391 break; 2392 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2393 if (len != 4) { 2394 return -1; 2395 } 2396 memset(buf, 0, len); /* ? XXX */ 2397 totlen = len; 2398 break; 2399 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2400 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2401 if (index < 1 || index > sc->sc_noport) { 2402 return -1; 2403 } 2404 if (len != 4) { 2405 return -1; 2406 } 2407 v = EOREAD4(sc, EHCI_PORTSC(index)); 2408 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2409 2410 i = UPS_HIGH_SPEED; 2411 if (sc->sc_flags & EHCIF_ETTF) { 2412 /* 2413 * If we are doing embedded transaction translation, 2414 * then directly attached LS/FS devices are reset by 2415 * the EHCI controller itself. PSPD is encoded 2416 * the same way as in USBSTATUS. 2417 */ 2418 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2419 } 2420 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2421 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2422 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2423 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2424 if (v & EHCI_PS_PR) i |= UPS_RESET; 2425 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2426 if (sc->sc_vendor_port_status) 2427 i = sc->sc_vendor_port_status(sc, v, i); 2428 USETW(ps.wPortStatus, i); 2429 i = 0; 2430 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2431 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2432 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2433 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2434 USETW(ps.wPortChange, i); 2435 totlen = min(len, sizeof(ps)); 2436 memcpy(buf, &ps, totlen); 2437 break; 2438 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2439 return -1; 2440 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2441 break; 2442 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2443 if (index < 1 || index > sc->sc_noport) { 2444 return -1; 2445 } 2446 port = EHCI_PORTSC(index); 2447 v = EOREAD4(sc, port); 2448 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2449 v &= ~EHCI_PS_CLEAR; 2450 switch(value) { 2451 case UHF_PORT_ENABLE: 2452 EOWRITE4(sc, port, v | EHCI_PS_PE); 2453 break; 2454 case UHF_PORT_SUSPEND: 2455 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2456 break; 2457 case UHF_PORT_RESET: 2458 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2459 if (EHCI_PS_IS_LOWSPEED(v) 2460 && sc->sc_ncomp > 0 2461 && !(sc->sc_flags & EHCIF_ETTF)) { 2462 /* 2463 * Low speed device on non-ETTF controller or 2464 * unaccompanied controller, give up ownership. 2465 */ 2466 ehci_disown(sc, index, 1); 2467 break; 2468 } 2469 /* Start reset sequence. */ 2470 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2471 EOWRITE4(sc, port, v | EHCI_PS_PR); 2472 /* Wait for reset to complete. */ 2473 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2474 if (sc->sc_dying) { 2475 return -1; 2476 } 2477 /* 2478 * An embedded transaction translator will automatically 2479 * terminate the reset sequence so there's no need to 2480 * it. 2481 */ 2482 v = EOREAD4(sc, port); 2483 if (v & EHCI_PS_PR) { 2484 /* Terminate reset sequence. */ 2485 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2486 /* Wait for HC to complete reset. */ 2487 usb_delay_ms(&sc->sc_bus, 2488 EHCI_PORT_RESET_COMPLETE); 2489 if (sc->sc_dying) { 2490 return -1; 2491 } 2492 } 2493 2494 v = EOREAD4(sc, port); 2495 USBHIST_LOG(ehcidebug, 2496 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2497 if (v & EHCI_PS_PR) { 2498 printf("%s: port reset timeout\n", 2499 device_xname(sc->sc_dev)); 2500 return USBD_TIMEOUT; 2501 } 2502 if (!(v & EHCI_PS_PE)) { 2503 /* Not a high speed device, give up ownership.*/ 2504 ehci_disown(sc, index, 0); 2505 break; 2506 } 2507 sc->sc_isreset[index] = 1; 2508 USBHIST_LOG(ehcidebug, 2509 "ehci port %d reset, status = 0x%08x", index, v, 0, 2510 0); 2511 break; 2512 case UHF_PORT_POWER: 2513 USBHIST_LOG(ehcidebug, 2514 "set port power %d (has PPC = %d)", index, 2515 sc->sc_hasppc, 0, 0); 2516 if (sc->sc_hasppc) 2517 EOWRITE4(sc, port, v | EHCI_PS_PP); 2518 break; 2519 case UHF_PORT_TEST: 2520 USBHIST_LOG(ehcidebug, "set port test %d", 2521 index, 0, 0, 0); 2522 break; 2523 case UHF_PORT_INDICATOR: 2524 USBHIST_LOG(ehcidebug, "set port ind %d", 2525 index, 0, 0, 0); 2526 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2527 break; 2528 default: 2529 return -1; 2530 } 2531 break; 2532 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2533 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2534 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2535 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2536 break; 2537 default: 2538 /* default from usbroothub */ 2539 return buflen; 2540 } 2541 2542 return totlen; 2543 } 2544 2545 Static void 2546 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2547 { 2548 int port; 2549 uint32_t v; 2550 2551 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2552 2553 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2554 #ifdef DIAGNOSTIC 2555 if (sc->sc_npcomp != 0) { 2556 int i = (index-1) / sc->sc_npcomp; 2557 if (i >= sc->sc_ncomp) 2558 printf("%s: strange port\n", 2559 device_xname(sc->sc_dev)); 2560 else 2561 printf("%s: handing over %s speed device on " 2562 "port %d to %s\n", 2563 device_xname(sc->sc_dev), 2564 lowspeed ? "low" : "full", 2565 index, device_xname(sc->sc_comps[i])); 2566 } else { 2567 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2568 } 2569 #endif 2570 port = EHCI_PORTSC(index); 2571 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2572 EOWRITE4(sc, port, v | EHCI_PS_PO); 2573 } 2574 2575 Static usbd_status 2576 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2577 { 2578 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2579 usbd_status err; 2580 2581 /* Insert last in queue. */ 2582 mutex_enter(&sc->sc_lock); 2583 err = usb_insert_transfer(xfer); 2584 mutex_exit(&sc->sc_lock); 2585 if (err) 2586 return err; 2587 2588 /* Pipe isn't running, start first */ 2589 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2590 } 2591 2592 Static usbd_status 2593 ehci_root_intr_start(usbd_xfer_handle xfer) 2594 { 2595 usbd_pipe_handle pipe = xfer->ux_pipe; 2596 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2597 2598 if (sc->sc_dying) 2599 return USBD_IOERROR; 2600 2601 mutex_enter(&sc->sc_lock); 2602 sc->sc_intrxfer = xfer; 2603 mutex_exit(&sc->sc_lock); 2604 2605 return USBD_IN_PROGRESS; 2606 } 2607 2608 /* Abort a root interrupt request. */ 2609 Static void 2610 ehci_root_intr_abort(usbd_xfer_handle xfer) 2611 { 2612 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2613 2614 KASSERT(mutex_owned(&sc->sc_lock)); 2615 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2616 2617 sc->sc_intrxfer = NULL; 2618 2619 xfer->ux_status = USBD_CANCELLED; 2620 usb_transfer_complete(xfer); 2621 } 2622 2623 /* Close the root pipe. */ 2624 Static void 2625 ehci_root_intr_close(usbd_pipe_handle pipe) 2626 { 2627 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2628 2629 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2630 2631 KASSERT(mutex_owned(&sc->sc_lock)); 2632 2633 sc->sc_intrxfer = NULL; 2634 } 2635 2636 Static void 2637 ehci_root_intr_done(usbd_xfer_handle xfer) 2638 { 2639 xfer->ux_hcpriv = NULL; 2640 } 2641 2642 /************************/ 2643 2644 Static ehci_soft_qh_t * 2645 ehci_alloc_sqh(ehci_softc_t *sc) 2646 { 2647 ehci_soft_qh_t *sqh; 2648 usbd_status err; 2649 int i, offs; 2650 usb_dma_t dma; 2651 2652 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2653 2654 if (sc->sc_freeqhs == NULL) { 2655 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2656 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2657 EHCI_PAGE_SIZE, &dma); 2658 #ifdef EHCI_DEBUG 2659 if (err) 2660 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2661 #endif 2662 if (err) 2663 return NULL; 2664 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2665 offs = i * EHCI_SQH_SIZE; 2666 sqh = KERNADDR(&dma, offs); 2667 sqh->physaddr = DMAADDR(&dma, offs); 2668 sqh->dma = dma; 2669 sqh->offs = offs; 2670 sqh->next = sc->sc_freeqhs; 2671 sc->sc_freeqhs = sqh; 2672 } 2673 } 2674 sqh = sc->sc_freeqhs; 2675 sc->sc_freeqhs = sqh->next; 2676 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2677 sqh->next = NULL; 2678 return sqh; 2679 } 2680 2681 Static void 2682 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2683 { 2684 sqh->next = sc->sc_freeqhs; 2685 sc->sc_freeqhs = sqh; 2686 } 2687 2688 Static ehci_soft_qtd_t * 2689 ehci_alloc_sqtd(ehci_softc_t *sc) 2690 { 2691 ehci_soft_qtd_t *sqtd = NULL; 2692 usbd_status err; 2693 int i, offs; 2694 usb_dma_t dma; 2695 2696 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2697 2698 if (sc->sc_freeqtds == NULL) { 2699 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2700 2701 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2702 EHCI_PAGE_SIZE, &dma); 2703 #ifdef EHCI_DEBUG 2704 if (err) 2705 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2706 #endif 2707 if (err) 2708 goto done; 2709 2710 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2711 offs = i * EHCI_SQTD_SIZE; 2712 sqtd = KERNADDR(&dma, offs); 2713 sqtd->physaddr = DMAADDR(&dma, offs); 2714 sqtd->dma = dma; 2715 sqtd->offs = offs; 2716 2717 sqtd->nextqtd = sc->sc_freeqtds; 2718 sc->sc_freeqtds = sqtd; 2719 } 2720 } 2721 2722 sqtd = sc->sc_freeqtds; 2723 sc->sc_freeqtds = sqtd->nextqtd; 2724 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2725 sqtd->nextqtd = NULL; 2726 sqtd->xfer = NULL; 2727 2728 done: 2729 return sqtd; 2730 } 2731 2732 Static void 2733 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2734 { 2735 2736 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2737 2738 sqtd->nextqtd = sc->sc_freeqtds; 2739 sc->sc_freeqtds = sqtd; 2740 } 2741 2742 Static usbd_status 2743 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2744 int alen, int rd, usbd_xfer_handle xfer, 2745 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2746 { 2747 ehci_soft_qtd_t *next, *cur; 2748 ehci_physaddr_t nextphys; 2749 uint32_t qtdstatus; 2750 int len, curlen, mps; 2751 int i, tog; 2752 int pages, pageoffs; 2753 bus_size_t curoffs; 2754 vaddr_t va, va_offs; 2755 usb_dma_t *dma = &xfer->ux_dmabuf; 2756 uint16_t flags = xfer->ux_flags; 2757 paddr_t a; 2758 2759 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2760 2761 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2762 2763 len = alen; 2764 qtdstatus = EHCI_QTD_ACTIVE | 2765 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2766 EHCI_QTD_SET_CERR(3) 2767 /* IOC set below */ 2768 /* BYTES set below */ 2769 ; 2770 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 2771 tog = epipe->nexttoggle; 2772 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2773 2774 cur = ehci_alloc_sqtd(sc); 2775 *sp = cur; 2776 if (cur == NULL) 2777 goto nomem; 2778 2779 usb_syncmem(dma, 0, alen, 2780 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2781 curoffs = 0; 2782 for (;;) { 2783 /* The EHCI hardware can handle at most 5 pages. */ 2784 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2785 va_offs = EHCI_PAGE_OFFSET(va_offs); 2786 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 2787 /* we can handle it in this QTD */ 2788 curlen = len - curoffs; 2789 } else { 2790 /* must use multiple TDs, fill as much as possible. */ 2791 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 2792 2793 /* the length must be a multiple of the max size */ 2794 curlen -= curlen % mps; 2795 USBHIST_LOG(ehcidebug, "multiple QTDs, " 2796 "curlen=%d", curlen, 0, 0, 0); 2797 KASSERT(curlen != 0); 2798 } 2799 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 2800 len, curlen, (size_t)curoffs, 0); 2801 2802 /* 2803 * Allocate another transfer if there's more data left, 2804 * or if force last short transfer flag is set and we're 2805 * allocating a multiple of the max packet size. 2806 */ 2807 2808 if (curoffs + curlen != len || 2809 ((curlen % mps) == 0 && !rd && curlen != 0 && 2810 (flags & USBD_FORCE_SHORT_XFER))) { 2811 next = ehci_alloc_sqtd(sc); 2812 if (next == NULL) 2813 goto nomem; 2814 nextphys = htole32(next->physaddr); 2815 } else { 2816 next = NULL; 2817 nextphys = EHCI_NULL; 2818 } 2819 2820 /* Find number of pages we'll be using, insert dma addresses */ 2821 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2822 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2823 pageoffs = EHCI_PAGE(curoffs); 2824 for (i = 0; i < pages; i++) { 2825 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2826 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2827 /* Cast up to avoid compiler warnings */ 2828 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2829 } 2830 2831 /* First buffer pointer requires a page offset to start at */ 2832 va = (vaddr_t)KERNADDR(dma, curoffs); 2833 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2834 2835 cur->nextqtd = next; 2836 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2837 cur->qtd.qtd_status = 2838 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2839 cur->xfer = xfer; 2840 cur->len = curlen; 2841 2842 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2843 (size_t)curoffs, (size_t)(curoffs + curlen), 0, 0); 2844 2845 /* 2846 * adjust the toggle based on the number of packets in this 2847 * qtd 2848 */ 2849 if (((curlen + mps - 1) / mps) & 1) { 2850 tog ^= 1; 2851 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2852 } 2853 if (next == NULL) 2854 break; 2855 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2856 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2857 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2858 if (len) 2859 curoffs += curlen; 2860 cur = next; 2861 } 2862 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2863 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2864 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2865 *ep = cur; 2866 epipe->nexttoggle = tog; 2867 2868 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 2869 *sp, *ep, 0, 0); 2870 2871 return USBD_NORMAL_COMPLETION; 2872 2873 nomem: 2874 /* XXX free chain */ 2875 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2876 return USBD_NOMEM; 2877 } 2878 2879 Static void 2880 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2881 ehci_soft_qtd_t *sqtdend) 2882 { 2883 ehci_soft_qtd_t *p; 2884 int i; 2885 2886 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2887 2888 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 2889 sqtd, sqtdend, 0, 0); 2890 2891 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2892 p = sqtd->nextqtd; 2893 ehci_free_sqtd(sc, sqtd); 2894 } 2895 } 2896 2897 Static ehci_soft_itd_t * 2898 ehci_alloc_itd(ehci_softc_t *sc) 2899 { 2900 struct ehci_soft_itd *itd, *freeitd; 2901 usbd_status err; 2902 int i, offs, frindex, previndex; 2903 usb_dma_t dma; 2904 2905 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2906 2907 mutex_enter(&sc->sc_lock); 2908 2909 /* Find an itd that wasn't freed this frame or last frame. This can 2910 * discard itds that were freed before frindex wrapped around 2911 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2912 * interrupt and fiddling with list when that happens */ 2913 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2914 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2915 2916 freeitd = NULL; 2917 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2918 if (itd == NULL) 2919 break; 2920 if (itd->slot != frindex && itd->slot != previndex) { 2921 freeitd = itd; 2922 break; 2923 } 2924 } 2925 2926 if (freeitd == NULL) { 2927 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2928 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2929 EHCI_PAGE_SIZE, &dma); 2930 2931 if (err) { 2932 USBHIST_LOG(ehcidebug, 2933 "alloc returned %d", err, 0, 0, 0); 2934 mutex_exit(&sc->sc_lock); 2935 return NULL; 2936 } 2937 2938 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2939 offs = i * EHCI_ITD_SIZE; 2940 itd = KERNADDR(&dma, offs); 2941 itd->physaddr = DMAADDR(&dma, offs); 2942 itd->dma = dma; 2943 itd->offs = offs; 2944 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2945 } 2946 freeitd = LIST_FIRST(&sc->sc_freeitds); 2947 } 2948 2949 itd = freeitd; 2950 LIST_REMOVE(itd, u.free_list); 2951 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2952 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2953 sizeof(itd->itd.itd_next), 2954 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2955 2956 itd->u.frame_list.next = NULL; 2957 itd->u.frame_list.prev = NULL; 2958 itd->xfer_next = NULL; 2959 itd->slot = 0; 2960 2961 mutex_exit(&sc->sc_lock); 2962 2963 return itd; 2964 } 2965 2966 Static ehci_soft_sitd_t * 2967 ehci_alloc_sitd(ehci_softc_t *sc) 2968 { 2969 struct ehci_soft_sitd *sitd, *freesitd; 2970 usbd_status err; 2971 int i, offs, frindex, previndex; 2972 usb_dma_t dma; 2973 2974 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2975 2976 mutex_enter(&sc->sc_lock); 2977 2978 /* Find an sitd that wasn't freed this frame or last frame. This can 2979 * discard sitds that were freed before frindex wrapped around 2980 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2981 * interrupt and fiddling with list when that happens */ 2982 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2983 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2984 2985 freesitd = NULL; 2986 LIST_FOREACH(sitd, &sc->sc_freesitds, u.free_list) { 2987 if (sitd == NULL) 2988 break; 2989 if (sitd->slot != frindex && sitd->slot != previndex) { 2990 freesitd = sitd; 2991 break; 2992 } 2993 } 2994 2995 if (freesitd == NULL) { 2996 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2997 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 2998 EHCI_PAGE_SIZE, &dma); 2999 3000 if (err) { 3001 USBHIST_LOG(ehcidebug, 3002 "alloc returned %d", err, 0, 0, 0); 3003 mutex_exit(&sc->sc_lock); 3004 return NULL; 3005 } 3006 3007 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3008 offs = i * EHCI_SITD_SIZE; 3009 sitd = KERNADDR(&dma, offs); 3010 sitd->physaddr = DMAADDR(&dma, offs); 3011 sitd->dma = dma; 3012 sitd->offs = offs; 3013 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3014 } 3015 freesitd = LIST_FIRST(&sc->sc_freesitds); 3016 } 3017 3018 sitd = freesitd; 3019 LIST_REMOVE(sitd, u.free_list); 3020 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3021 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3022 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3023 BUS_DMASYNC_PREREAD); 3024 3025 sitd->u.frame_list.next = NULL; 3026 sitd->u.frame_list.prev = NULL; 3027 sitd->xfer_next = NULL; 3028 sitd->slot = 0; 3029 3030 mutex_exit(&sc->sc_lock); 3031 3032 return sitd; 3033 } 3034 3035 Static void 3036 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3037 { 3038 3039 KASSERT(mutex_owned(&sc->sc_lock)); 3040 3041 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3042 } 3043 3044 Static void 3045 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3046 { 3047 3048 KASSERT(mutex_owned(&sc->sc_lock)); 3049 3050 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3051 } 3052 3053 /****************/ 3054 3055 /* 3056 * Close a reqular pipe. 3057 * Assumes that there are no pending transactions. 3058 */ 3059 Static void 3060 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3061 { 3062 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3063 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3064 ehci_soft_qh_t *sqh = epipe->sqh; 3065 3066 KASSERT(mutex_owned(&sc->sc_lock)); 3067 3068 ehci_rem_qh(sc, sqh, head); 3069 ehci_free_sqh(sc, epipe->sqh); 3070 } 3071 3072 /* 3073 * Abort a device request. 3074 * If this routine is called at splusb() it guarantees that the request 3075 * will be removed from the hardware scheduling and that the callback 3076 * for it will be called with USBD_CANCELLED status. 3077 * It's impossible to guarantee that the requested transfer will not 3078 * have happened since the hardware runs concurrently. 3079 * If the transaction has already happened we rely on the ordinary 3080 * interrupt processing to process it. 3081 * XXX This is most probably wrong. 3082 * XXXMRG this doesn't make sense anymore. 3083 */ 3084 Static void 3085 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3086 { 3087 #define exfer EXFER(xfer) 3088 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3089 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3090 ehci_soft_qh_t *sqh = epipe->sqh; 3091 ehci_soft_qtd_t *sqtd; 3092 ehci_physaddr_t cur; 3093 uint32_t qhstatus; 3094 int hit; 3095 int wake; 3096 3097 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3098 3099 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3100 3101 KASSERT(mutex_owned(&sc->sc_lock)); 3102 ASSERT_SLEEPABLE(); 3103 3104 if (sc->sc_dying) { 3105 /* If we're dying, just do the software part. */ 3106 xfer->ux_status = status; /* make software ignore it */ 3107 callout_stop(&xfer->ux_callout); 3108 usb_transfer_complete(xfer); 3109 return; 3110 } 3111 3112 /* 3113 * If an abort is already in progress then just wait for it to 3114 * complete and return. 3115 */ 3116 if (xfer->ux_hcflags & UXFER_ABORTING) { 3117 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3118 #ifdef DIAGNOSTIC 3119 if (status == USBD_TIMEOUT) 3120 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3121 #endif 3122 /* Override the status which might be USBD_TIMEOUT. */ 3123 xfer->ux_status = status; 3124 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3125 0, 0, 0, 0); 3126 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3127 while (xfer->ux_hcflags & UXFER_ABORTING) 3128 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3129 return; 3130 } 3131 xfer->ux_hcflags |= UXFER_ABORTING; 3132 3133 /* 3134 * Step 1: Make interrupt routine and hardware ignore xfer. 3135 */ 3136 xfer->ux_status = status; /* make software ignore it */ 3137 callout_stop(&xfer->ux_callout); 3138 3139 usb_syncmem(&sqh->dma, 3140 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3141 sizeof(sqh->qh.qh_qtd.qtd_status), 3142 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3143 qhstatus = sqh->qh.qh_qtd.qtd_status; 3144 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3145 usb_syncmem(&sqh->dma, 3146 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3147 sizeof(sqh->qh.qh_qtd.qtd_status), 3148 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3149 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3150 usb_syncmem(&sqtd->dma, 3151 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3152 sizeof(sqtd->qtd.qtd_status), 3153 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3154 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3155 usb_syncmem(&sqtd->dma, 3156 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3157 sizeof(sqtd->qtd.qtd_status), 3158 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3159 if (sqtd == exfer->sqtdend) 3160 break; 3161 } 3162 3163 /* 3164 * Step 2: Wait until we know hardware has finished any possible 3165 * use of the xfer. Also make sure the soft interrupt routine 3166 * has run. 3167 */ 3168 ehci_sync_hc(sc); 3169 sc->sc_softwake = 1; 3170 usb_schedsoftintr(&sc->sc_bus); 3171 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3172 3173 /* 3174 * Step 3: Remove any vestiges of the xfer from the hardware. 3175 * The complication here is that the hardware may have executed 3176 * beyond the xfer we're trying to abort. So as we're scanning 3177 * the TDs of this xfer we check if the hardware points to 3178 * any of them. 3179 */ 3180 3181 usb_syncmem(&sqh->dma, 3182 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3183 sizeof(sqh->qh.qh_curqtd), 3184 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3185 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3186 hit = 0; 3187 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) { 3188 hit |= cur == sqtd->physaddr; 3189 if (sqtd == exfer->sqtdend) 3190 break; 3191 } 3192 sqtd = sqtd->nextqtd; 3193 /* Zap curqtd register if hardware pointed inside the xfer. */ 3194 if (hit && sqtd != NULL) { 3195 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3196 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3197 usb_syncmem(&sqh->dma, 3198 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3199 sizeof(sqh->qh.qh_curqtd), 3200 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3201 sqh->qh.qh_qtd.qtd_status = qhstatus; 3202 usb_syncmem(&sqh->dma, 3203 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3204 sizeof(sqh->qh.qh_qtd.qtd_status), 3205 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3206 } else { 3207 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3208 } 3209 3210 /* 3211 * Step 4: Execute callback. 3212 */ 3213 #ifdef DIAGNOSTIC 3214 exfer->isdone = 1; 3215 #endif 3216 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3217 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3218 usb_transfer_complete(xfer); 3219 if (wake) { 3220 cv_broadcast(&xfer->ux_hccv); 3221 } 3222 3223 KASSERT(mutex_owned(&sc->sc_lock)); 3224 #undef exfer 3225 } 3226 3227 Static void 3228 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3229 { 3230 ehci_isoc_trans_t trans_status; 3231 struct ehci_pipe *epipe; 3232 struct ehci_xfer *exfer; 3233 ehci_softc_t *sc; 3234 struct ehci_soft_itd *itd; 3235 struct ehci_soft_sitd *sitd; 3236 int i, wake; 3237 3238 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3239 3240 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3241 exfer = EXFER(xfer); 3242 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3243 3244 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3245 3246 KASSERT(mutex_owned(&sc->sc_lock)); 3247 3248 if (sc->sc_dying) { 3249 xfer->ux_status = status; 3250 callout_stop(&xfer->ux_callout); 3251 usb_transfer_complete(xfer); 3252 return; 3253 } 3254 3255 if (xfer->ux_hcflags & UXFER_ABORTING) { 3256 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3257 3258 #ifdef DIAGNOSTIC 3259 if (status == USBD_TIMEOUT) 3260 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3261 #endif 3262 3263 xfer->ux_status = status; 3264 USBHIST_LOG(ehcidebug, 3265 "waiting for abort to finish", 0, 0, 0, 0); 3266 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3267 while (xfer->ux_hcflags & UXFER_ABORTING) 3268 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3269 goto done; 3270 } 3271 xfer->ux_hcflags |= UXFER_ABORTING; 3272 3273 xfer->ux_status = status; 3274 callout_stop(&xfer->ux_callout); 3275 3276 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3277 for (itd = exfer->itdstart; itd != NULL; 3278 itd = itd->xfer_next) { 3279 usb_syncmem(&itd->dma, 3280 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3281 sizeof(itd->itd.itd_ctl), 3282 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3283 3284 for (i = 0; i < 8; i++) { 3285 trans_status = le32toh(itd->itd.itd_ctl[i]); 3286 trans_status &= ~EHCI_ITD_ACTIVE; 3287 itd->itd.itd_ctl[i] = htole32(trans_status); 3288 } 3289 3290 usb_syncmem(&itd->dma, 3291 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3292 sizeof(itd->itd.itd_ctl), 3293 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3294 } 3295 } else { 3296 for (sitd = exfer->sitdstart; sitd != NULL; 3297 sitd = sitd->xfer_next) { 3298 usb_syncmem(&sitd->dma, 3299 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3300 sizeof(sitd->sitd.sitd_buffer), 3301 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3302 3303 trans_status = le32toh(sitd->sitd.sitd_trans); 3304 trans_status &= ~EHCI_SITD_ACTIVE; 3305 sitd->sitd.sitd_trans = htole32(trans_status); 3306 3307 usb_syncmem(&sitd->dma, 3308 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3309 sizeof(sitd->sitd.sitd_buffer), 3310 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3311 } 3312 } 3313 3314 sc->sc_softwake = 1; 3315 usb_schedsoftintr(&sc->sc_bus); 3316 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3317 3318 #ifdef DIAGNOSTIC 3319 exfer->isdone = 1; 3320 #endif 3321 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3322 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3323 usb_transfer_complete(xfer); 3324 if (wake) { 3325 cv_broadcast(&xfer->ux_hccv); 3326 } 3327 3328 done: 3329 KASSERT(mutex_owned(&sc->sc_lock)); 3330 return; 3331 } 3332 3333 Static void 3334 ehci_timeout(void *addr) 3335 { 3336 struct ehci_xfer *exfer = addr; 3337 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.ux_pipe; 3338 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3339 3340 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3341 3342 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3343 #ifdef EHCI_DEBUG 3344 if (ehcidebug > 1) 3345 usbd_dump_pipe(exfer->xfer.ux_pipe); 3346 #endif 3347 3348 if (sc->sc_dying) { 3349 mutex_enter(&sc->sc_lock); 3350 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT); 3351 mutex_exit(&sc->sc_lock); 3352 return; 3353 } 3354 3355 /* Execute the abort in a process context. */ 3356 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr, 3357 USB_TASKQ_MPSAFE); 3358 usb_add_task(exfer->xfer.ux_pipe->up_dev, &exfer->abort_task, 3359 USB_TASKQ_HC); 3360 } 3361 3362 Static void 3363 ehci_timeout_task(void *addr) 3364 { 3365 usbd_xfer_handle xfer = addr; 3366 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3367 3368 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3369 3370 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3371 3372 mutex_enter(&sc->sc_lock); 3373 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3374 mutex_exit(&sc->sc_lock); 3375 } 3376 3377 /************************/ 3378 3379 Static usbd_status 3380 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3381 { 3382 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3383 usbd_status err; 3384 3385 /* Insert last in queue. */ 3386 mutex_enter(&sc->sc_lock); 3387 err = usb_insert_transfer(xfer); 3388 mutex_exit(&sc->sc_lock); 3389 if (err) 3390 return err; 3391 3392 /* Pipe isn't running, start first */ 3393 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3394 } 3395 3396 Static usbd_status 3397 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3398 { 3399 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3400 usbd_status err; 3401 3402 if (sc->sc_dying) 3403 return USBD_IOERROR; 3404 3405 #ifdef DIAGNOSTIC 3406 if (!(xfer->ux_rqflags & URQ_REQUEST)) { 3407 /* XXX panic */ 3408 printf("ehci_device_ctrl_transfer: not a request\n"); 3409 return USBD_INVAL; 3410 } 3411 #endif 3412 3413 err = ehci_device_request(xfer); 3414 if (err) { 3415 return err; 3416 } 3417 3418 if (sc->sc_bus.ub_usepolling) 3419 ehci_waitintr(sc, xfer); 3420 3421 return USBD_IN_PROGRESS; 3422 } 3423 3424 Static void 3425 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3426 { 3427 struct ehci_xfer *ex = EXFER(xfer); 3428 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3429 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3430 usb_device_request_t *req = &xfer->ux_request; 3431 int len = UGETW(req->wLength); 3432 int rd = req->bmRequestType & UT_READ; 3433 3434 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3435 3436 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3437 3438 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3439 3440 #ifdef DIAGNOSTIC 3441 if (!(xfer->ux_rqflags & URQ_REQUEST)) { 3442 panic("ehci_ctrl_done: not a request"); 3443 } 3444 #endif 3445 3446 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3447 ehci_del_intr_list(sc, ex); /* remove from active list */ 3448 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3449 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3450 BUS_DMASYNC_POSTWRITE); 3451 if (len) 3452 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3453 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3454 } 3455 3456 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3457 } 3458 3459 /* Abort a device control request. */ 3460 Static void 3461 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3462 { 3463 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3464 3465 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3466 ehci_abort_xfer(xfer, USBD_CANCELLED); 3467 } 3468 3469 /* Close a device control pipe. */ 3470 Static void 3471 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3472 { 3473 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3474 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3475 3476 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3477 3478 KASSERT(mutex_owned(&sc->sc_lock)); 3479 3480 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3481 3482 ehci_close_pipe(pipe, sc->sc_async_head); 3483 } 3484 3485 Static usbd_status 3486 ehci_device_request(usbd_xfer_handle xfer) 3487 { 3488 #define exfer EXFER(xfer) 3489 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3490 usb_device_request_t *req = &xfer->ux_request; 3491 usbd_device_handle dev = epipe->pipe.up_dev; 3492 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3493 ehci_soft_qtd_t *setup, *stat, *next; 3494 ehci_soft_qh_t *sqh; 3495 int isread; 3496 int len; 3497 usbd_status err; 3498 3499 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3500 3501 isread = req->bmRequestType & UT_READ; 3502 len = UGETW(req->wLength); 3503 3504 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3505 "wValue=0x%04x, wIndex=0x%04x", 3506 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3507 UGETW(req->wIndex)); 3508 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3509 len, dev->ud_addr, 3510 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3511 3512 setup = ehci_alloc_sqtd(sc); 3513 if (setup == NULL) { 3514 err = USBD_NOMEM; 3515 goto bad1; 3516 } 3517 stat = ehci_alloc_sqtd(sc); 3518 if (stat == NULL) { 3519 err = USBD_NOMEM; 3520 goto bad2; 3521 } 3522 3523 mutex_enter(&sc->sc_lock); 3524 3525 sqh = epipe->sqh; 3526 3527 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3528 "address QH %d pipe %d\n", 3529 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3530 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3531 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3532 "MPS QH %d pipe %d\n", 3533 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3534 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3535 3536 /* Set up data transaction */ 3537 if (len != 0) { 3538 ehci_soft_qtd_t *end; 3539 3540 /* Start toggle at 1. */ 3541 epipe->nexttoggle = 1; 3542 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3543 &next, &end); 3544 if (err) 3545 goto bad3; 3546 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3547 end->nextqtd = stat; 3548 end->qtd.qtd_next = end->qtd.qtd_altnext = 3549 htole32(stat->physaddr); 3550 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3551 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3552 } else { 3553 next = stat; 3554 } 3555 3556 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3557 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3558 3559 /* Clear toggle */ 3560 setup->qtd.qtd_status = htole32( 3561 EHCI_QTD_ACTIVE | 3562 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3563 EHCI_QTD_SET_CERR(3) | 3564 EHCI_QTD_SET_TOGGLE(0) | 3565 EHCI_QTD_SET_BYTES(sizeof *req) 3566 ); 3567 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3568 setup->qtd.qtd_buffer_hi[0] = 0; 3569 setup->nextqtd = next; 3570 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3571 setup->xfer = xfer; 3572 setup->len = sizeof *req; 3573 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3574 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3575 3576 stat->qtd.qtd_status = htole32( 3577 EHCI_QTD_ACTIVE | 3578 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3579 EHCI_QTD_SET_CERR(3) | 3580 EHCI_QTD_SET_TOGGLE(1) | 3581 EHCI_QTD_IOC 3582 ); 3583 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3584 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3585 stat->nextqtd = NULL; 3586 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3587 stat->xfer = xfer; 3588 stat->len = 0; 3589 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3590 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3591 3592 #ifdef EHCI_DEBUG 3593 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3594 ehci_dump_sqh(sqh); 3595 ehci_dump_sqtds(setup); 3596 #endif 3597 3598 exfer->sqtdstart = setup; 3599 exfer->sqtdend = stat; 3600 #ifdef DIAGNOSTIC 3601 if (!exfer->isdone) { 3602 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3603 } 3604 exfer->isdone = 0; 3605 #endif 3606 3607 /* Insert qTD in QH list. */ 3608 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3609 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3610 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3611 ehci_timeout, xfer); 3612 } 3613 ehci_add_intr_list(sc, exfer); 3614 xfer->ux_status = USBD_IN_PROGRESS; 3615 mutex_exit(&sc->sc_lock); 3616 3617 #ifdef EHCI_DEBUG 3618 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3619 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3620 // delay(10000); 3621 ehci_dump_regs(sc); 3622 ehci_dump_sqh(sc->sc_async_head); 3623 ehci_dump_sqh(sqh); 3624 ehci_dump_sqtds(setup); 3625 #endif 3626 3627 return USBD_NORMAL_COMPLETION; 3628 3629 bad3: 3630 mutex_exit(&sc->sc_lock); 3631 ehci_free_sqtd(sc, stat); 3632 bad2: 3633 ehci_free_sqtd(sc, setup); 3634 bad1: 3635 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3636 mutex_enter(&sc->sc_lock); 3637 xfer->ux_status = err; 3638 usb_transfer_complete(xfer); 3639 mutex_exit(&sc->sc_lock); 3640 return err; 3641 #undef exfer 3642 } 3643 3644 /* 3645 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3646 * qTD status, or miss signalling occasionally under heavy load. If the host 3647 * machine is too fast, we we can miss transaction completion - when we scan 3648 * the active list the transaction still seems to be active. This generally 3649 * exhibits itself as a umass stall that never recovers. 3650 * 3651 * We work around this behaviour by setting up this callback after any softintr 3652 * that completes with transactions still pending, giving us another chance to 3653 * check for completion after the writeback has taken place. 3654 */ 3655 Static void 3656 ehci_intrlist_timeout(void *arg) 3657 { 3658 ehci_softc_t *sc = arg; 3659 3660 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3661 3662 usb_schedsoftintr(&sc->sc_bus); 3663 } 3664 3665 /************************/ 3666 3667 Static usbd_status 3668 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3669 { 3670 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3671 usbd_status err; 3672 3673 /* Insert last in queue. */ 3674 mutex_enter(&sc->sc_lock); 3675 err = usb_insert_transfer(xfer); 3676 mutex_exit(&sc->sc_lock); 3677 if (err) 3678 return err; 3679 3680 /* Pipe isn't running, start first */ 3681 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3682 } 3683 3684 Static usbd_status 3685 ehci_device_bulk_start(usbd_xfer_handle xfer) 3686 { 3687 #define exfer EXFER(xfer) 3688 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3689 usbd_device_handle dev = epipe->pipe.up_dev; 3690 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3691 ehci_soft_qtd_t *data, *dataend; 3692 ehci_soft_qh_t *sqh; 3693 usbd_status err; 3694 int len, isread, endpt; 3695 3696 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3697 3698 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3699 xfer, xfer->ux_length, xfer->ux_flags, 0); 3700 3701 if (sc->sc_dying) 3702 return USBD_IOERROR; 3703 3704 #ifdef DIAGNOSTIC 3705 if (xfer->ux_rqflags & URQ_REQUEST) 3706 panic("ehci_device_bulk_start: a request"); 3707 #endif 3708 3709 mutex_enter(&sc->sc_lock); 3710 3711 len = xfer->ux_length; 3712 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3713 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3714 sqh = epipe->sqh; 3715 3716 epipe->u.bulk.length = len; 3717 3718 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3719 &dataend); 3720 if (err) { 3721 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3722 xfer->ux_status = err; 3723 usb_transfer_complete(xfer); 3724 mutex_exit(&sc->sc_lock); 3725 return err; 3726 } 3727 3728 #ifdef EHCI_DEBUG 3729 USBHIST_LOGN(ehcidebug, 5, "data(1):", 0, 0, 0, 0); 3730 ehci_dump_sqh(sqh); 3731 ehci_dump_sqtds(data); 3732 #endif 3733 3734 /* Set up interrupt info. */ 3735 exfer->sqtdstart = data; 3736 exfer->sqtdend = dataend; 3737 #ifdef DIAGNOSTIC 3738 if (!exfer->isdone) { 3739 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3740 } 3741 exfer->isdone = 0; 3742 #endif 3743 3744 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3745 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3746 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3747 ehci_timeout, xfer); 3748 } 3749 ehci_add_intr_list(sc, exfer); 3750 xfer->ux_status = USBD_IN_PROGRESS; 3751 mutex_exit(&sc->sc_lock); 3752 3753 #ifdef EHCI_DEBUG 3754 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3755 // delay(10000); 3756 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3757 ehci_dump_regs(sc); 3758 #if 0 3759 printf("async_head:\n"); 3760 ehci_dump_sqh(sc->sc_async_head); 3761 #endif 3762 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3763 ehci_dump_sqh(sqh); 3764 ehci_dump_sqtds(data); 3765 #endif 3766 3767 if (sc->sc_bus.ub_usepolling) 3768 ehci_waitintr(sc, xfer); 3769 3770 return USBD_IN_PROGRESS; 3771 #undef exfer 3772 } 3773 3774 Static void 3775 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3776 { 3777 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3778 3779 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3780 ehci_abort_xfer(xfer, USBD_CANCELLED); 3781 } 3782 3783 /* 3784 * Close a device bulk pipe. 3785 */ 3786 Static void 3787 ehci_device_bulk_close(usbd_pipe_handle pipe) 3788 { 3789 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3790 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3791 3792 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3793 3794 KASSERT(mutex_owned(&sc->sc_lock)); 3795 3796 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3797 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3798 ehci_close_pipe(pipe, sc->sc_async_head); 3799 } 3800 3801 Static void 3802 ehci_device_bulk_done(usbd_xfer_handle xfer) 3803 { 3804 struct ehci_xfer *ex = EXFER(xfer); 3805 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3806 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3807 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3808 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3809 3810 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3811 3812 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3813 xfer, xfer->ux_actlen, 0, 0); 3814 3815 KASSERT(mutex_owned(&sc->sc_lock)); 3816 3817 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3818 ehci_del_intr_list(sc, ex); /* remove from active list */ 3819 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 3820 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3821 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3822 } 3823 3824 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3825 } 3826 3827 /************************/ 3828 3829 Static usbd_status 3830 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3831 { 3832 struct ehci_soft_islot *isp; 3833 int islot, lev; 3834 3835 /* Find a poll rate that is large enough. */ 3836 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3837 if (EHCI_ILEV_IVAL(lev) <= ival) 3838 break; 3839 3840 /* Pick an interrupt slot at the right level. */ 3841 /* XXX could do better than picking at random */ 3842 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3843 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3844 3845 sqh->islot = islot; 3846 isp = &sc->sc_islots[islot]; 3847 mutex_enter(&sc->sc_lock); 3848 ehci_add_qh(sc, sqh, isp->sqh); 3849 mutex_exit(&sc->sc_lock); 3850 3851 return USBD_NORMAL_COMPLETION; 3852 } 3853 3854 Static usbd_status 3855 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3856 { 3857 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3858 usbd_status err; 3859 3860 /* Insert last in queue. */ 3861 mutex_enter(&sc->sc_lock); 3862 err = usb_insert_transfer(xfer); 3863 mutex_exit(&sc->sc_lock); 3864 if (err) 3865 return err; 3866 3867 /* 3868 * Pipe isn't running (otherwise err would be USBD_INPROG), 3869 * so start it first. 3870 */ 3871 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3872 } 3873 3874 Static usbd_status 3875 ehci_device_intr_start(usbd_xfer_handle xfer) 3876 { 3877 #define exfer EXFER(xfer) 3878 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3879 usbd_device_handle dev = xfer->ux_pipe->up_dev; 3880 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3881 ehci_soft_qtd_t *data, *dataend; 3882 ehci_soft_qh_t *sqh; 3883 usbd_status err; 3884 int len, isread, endpt; 3885 3886 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3887 3888 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3889 xfer, xfer->ux_length, xfer->ux_flags, 0); 3890 3891 if (sc->sc_dying) 3892 return USBD_IOERROR; 3893 3894 #ifdef DIAGNOSTIC 3895 if (xfer->ux_rqflags & URQ_REQUEST) 3896 panic("ehci_device_intr_start: a request"); 3897 #endif 3898 3899 mutex_enter(&sc->sc_lock); 3900 3901 len = xfer->ux_length; 3902 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3903 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3904 sqh = epipe->sqh; 3905 3906 epipe->u.intr.length = len; 3907 3908 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3909 &dataend); 3910 if (err) { 3911 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3912 xfer->ux_status = err; 3913 usb_transfer_complete(xfer); 3914 mutex_exit(&sc->sc_lock); 3915 return err; 3916 } 3917 3918 #ifdef EHCI_DEBUG 3919 USBHIST_LOGN(ehcidebug, 5, "data(1)", 0, 0, 0, 0); 3920 ehci_dump_sqh(sqh); 3921 ehci_dump_sqtds(data); 3922 #endif 3923 3924 /* Set up interrupt info. */ 3925 exfer->sqtdstart = data; 3926 exfer->sqtdend = dataend; 3927 #ifdef DIAGNOSTIC 3928 if (!exfer->isdone) { 3929 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3930 } 3931 exfer->isdone = 0; 3932 #endif 3933 3934 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3935 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3936 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3937 ehci_timeout, xfer); 3938 } 3939 ehci_add_intr_list(sc, exfer); 3940 xfer->ux_status = USBD_IN_PROGRESS; 3941 mutex_exit(&sc->sc_lock); 3942 3943 #ifdef EHCI_DEBUG 3944 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3945 // delay(10000); 3946 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3947 ehci_dump_regs(sc); 3948 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3949 ehci_dump_sqh(sqh); 3950 ehci_dump_sqtds(data); 3951 #endif 3952 3953 if (sc->sc_bus.ub_usepolling) 3954 ehci_waitintr(sc, xfer); 3955 3956 return USBD_IN_PROGRESS; 3957 #undef exfer 3958 } 3959 3960 Static void 3961 ehci_device_intr_abort(usbd_xfer_handle xfer) 3962 { 3963 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3964 3965 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3966 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3967 3968 /* 3969 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3970 * async doorbell. That's dependent on the async list, wheras 3971 * intr xfers are periodic, should not use this? 3972 */ 3973 ehci_abort_xfer(xfer, USBD_CANCELLED); 3974 } 3975 3976 Static void 3977 ehci_device_intr_close(usbd_pipe_handle pipe) 3978 { 3979 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3980 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3981 struct ehci_soft_islot *isp; 3982 3983 KASSERT(mutex_owned(&sc->sc_lock)); 3984 3985 isp = &sc->sc_islots[epipe->sqh->islot]; 3986 ehci_close_pipe(pipe, isp->sqh); 3987 } 3988 3989 Static void 3990 ehci_device_intr_done(usbd_xfer_handle xfer) 3991 { 3992 #define exfer EXFER(xfer) 3993 struct ehci_xfer *ex = EXFER(xfer); 3994 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3995 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3996 ehci_soft_qtd_t *data, *dataend; 3997 ehci_soft_qh_t *sqh; 3998 usbd_status err; 3999 int len, isread, endpt; 4000 4001 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4002 4003 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4004 xfer, xfer->ux_actlen, 0, 0); 4005 4006 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4007 4008 if (xfer->ux_pipe->up_repeat) { 4009 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4010 4011 len = epipe->u.intr.length; 4012 xfer->ux_length = len; 4013 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4014 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4015 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4016 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4017 sqh = epipe->sqh; 4018 4019 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4020 &data, &dataend); 4021 if (err) { 4022 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4023 xfer->ux_status = err; 4024 return; 4025 } 4026 4027 /* Set up interrupt info. */ 4028 exfer->sqtdstart = data; 4029 exfer->sqtdend = dataend; 4030 #ifdef DIAGNOSTIC 4031 if (!exfer->isdone) { 4032 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", 4033 exfer, 0, 0, 0); 4034 printf("ehci_device_intr_done: not done, ex=%p\n", 4035 exfer); 4036 } 4037 exfer->isdone = 0; 4038 #endif 4039 4040 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4041 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4042 callout_reset(&xfer->ux_callout, 4043 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4044 } 4045 4046 xfer->ux_status = USBD_IN_PROGRESS; 4047 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4048 ehci_del_intr_list(sc, ex); /* remove from active list */ 4049 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL); 4050 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4051 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4052 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4053 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4054 } 4055 #undef exfer 4056 } 4057 4058 /************************/ 4059 4060 Static usbd_status 4061 ehci_device_fs_isoc_transfer(usbd_xfer_handle xfer) 4062 { 4063 usbd_status err; 4064 4065 err = usb_insert_transfer(xfer); 4066 if (err && err != USBD_IN_PROGRESS) 4067 return err; 4068 4069 return ehci_device_fs_isoc_start(xfer); 4070 } 4071 4072 Static usbd_status 4073 ehci_device_fs_isoc_start(usbd_xfer_handle xfer) 4074 { 4075 struct ehci_pipe *epipe; 4076 usbd_device_handle dev; 4077 ehci_softc_t *sc; 4078 struct ehci_xfer *exfer; 4079 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4080 usb_dma_t *dma_buf; 4081 int i, j, k, frames; 4082 int offs, total_length; 4083 int frindex; 4084 u_int huba, dir; 4085 4086 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4087 4088 start = NULL; 4089 prev = NULL; 4090 sitd = NULL; 4091 total_length = 0; 4092 exfer = (struct ehci_xfer *) xfer; 4093 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4094 dev = xfer->ux_pipe->up_dev; 4095 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4096 4097 /* 4098 * To allow continuous transfers, above we start all transfers 4099 * immediately. However, we're still going to get usbd_start_next call 4100 * this when another xfer completes. So, check if this is already 4101 * in progress or not 4102 */ 4103 4104 if (exfer->sitdstart != NULL) 4105 return USBD_IN_PROGRESS; 4106 4107 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4108 xfer, xfer->ux_length, xfer->ux_flags, 0); 4109 4110 if (sc->sc_dying) 4111 return USBD_IOERROR; 4112 4113 /* 4114 * To avoid complication, don't allow a request right now that'll span 4115 * the entire frame table. To within 4 frames, to allow some leeway 4116 * on either side of where the hc currently is. 4117 */ 4118 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4119 xfer->ux_nframes >= sc->sc_flsize - 4) { 4120 printf("ehci: isoc descriptor requested that spans the entire" 4121 "frametable, too many frames\n"); 4122 return USBD_INVAL; 4123 } 4124 4125 #ifdef DIAGNOSTIC 4126 if (xfer->ux_rqflags & URQ_REQUEST) 4127 panic("ehci_device_fs_isoc_start: request\n"); 4128 4129 if (!exfer->isdone) 4130 printf("ehci_device_fs_isoc_start: not done, ex = %p\n", exfer); 4131 exfer->isdone = 0; 4132 #endif 4133 4134 /* 4135 * Step 1: Allocate and initialize sitds. 4136 */ 4137 4138 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4139 if (i > 16 || i == 0) { 4140 /* Spec page 271 says intervals > 16 are invalid */ 4141 USBHIST_LOG(ehcidebug, "bInverval %d invalid\n", 0, 0, 0, 0); 4142 4143 return USBD_INVAL; 4144 } 4145 4146 frames = xfer->ux_nframes; 4147 4148 if (frames == 0) { 4149 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4150 4151 return USBD_INVAL; 4152 } 4153 4154 dma_buf = &xfer->ux_dmabuf; 4155 offs = 0; 4156 4157 for (i = 0; i < frames; i++) { 4158 sitd = ehci_alloc_sitd(sc); 4159 4160 if (prev) 4161 prev->xfer_next = sitd; 4162 else 4163 start = sitd; 4164 4165 #ifdef DIAGNOSTIC 4166 if (xfer->ux_frlengths[i] > 0x3ff) { 4167 printf("ehci: invalid frame length\n"); 4168 xfer->ux_frlengths[i] = 0x3ff; 4169 } 4170 #endif 4171 4172 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4173 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4174 4175 /* Set page0 index and offset. */ 4176 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4177 4178 total_length += xfer->ux_frlengths[i]; 4179 offs += xfer->ux_frlengths[i]; 4180 4181 sitd->sitd.sitd_buffer[1] = 4182 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4183 4184 huba = dev->ud_myhsport->up_parent->ud_addr; 4185 4186 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4187 // Set hub address to 0 if embedded TT is used. 4188 if (huba == sc->sc_addr) 4189 huba = 0; 4190 } 4191 */ 4192 4193 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4194 dir = UE_GET_DIR(k) ? 1 : 0; 4195 sitd->sitd.sitd_endp = 4196 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4197 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4198 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4199 EHCI_SITD_SET_HUBA(huba) | 4200 EHCI_SITD_SET_DIR(dir)); 4201 4202 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4203 4204 /* XXX */ 4205 u_char sa, sb; 4206 u_int temp, tlen; 4207 sa = 0; 4208 4209 if (dir == 0) { /* OUT */ 4210 temp = 0; 4211 tlen = xfer->ux_frlengths[i]; 4212 if (tlen <= 188) { 4213 temp |= 1; /* T-count = 1, TP = ALL */ 4214 tlen = 1; 4215 } else { 4216 tlen += 187; 4217 tlen /= 188; 4218 temp |= tlen; /* T-count = [1..6] */ 4219 temp |= 8; /* TP = Begin */ 4220 } 4221 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4222 4223 tlen += sa; 4224 4225 if (tlen >= 8) { 4226 sb = 0; 4227 } else { 4228 sb = (1 << tlen); 4229 } 4230 4231 sa = (1 << sa); 4232 sa = (sb - sa) & 0x3F; 4233 sb = 0; 4234 } else { 4235 sb = (-(4 << sa)) & 0xFE; 4236 sa = (1 << sa) & 0x3F; 4237 sa = 0x01; 4238 sb = 0xfc; 4239 } 4240 4241 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4242 EHCI_SITD_SET_CMASK(sb)); 4243 4244 prev = sitd; 4245 } /* End of frame */ 4246 4247 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4248 4249 stop = sitd; 4250 stop->xfer_next = NULL; 4251 4252 usb_syncmem(&exfer->xfer.ux_dmabuf, 0, total_length, 4253 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4254 4255 /* 4256 * Part 2: Transfer descriptors have now been set up, now they must 4257 * be scheduled into the periodic frame list. Erk. Not wanting to 4258 * complicate matters, transfer is denied if the transfer spans 4259 * more than the period frame list. 4260 */ 4261 4262 mutex_enter(&sc->sc_lock); 4263 4264 /* Start inserting frames */ 4265 if (epipe->u.isoc.cur_xfers > 0) { 4266 frindex = epipe->u.isoc.next_frame; 4267 } else { 4268 frindex = EOREAD4(sc, EHCI_FRINDEX); 4269 frindex = frindex >> 3; /* Erase microframe index */ 4270 frindex += 2; 4271 } 4272 4273 if (frindex >= sc->sc_flsize) 4274 frindex &= (sc->sc_flsize - 1); 4275 4276 /* Whats the frame interval? */ 4277 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4278 4279 sitd = start; 4280 for (j = 0; j < frames; j++) { 4281 if (sitd == NULL) 4282 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4283 4284 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4285 if (sitd->sitd.sitd_next == 0) 4286 /* FIXME: frindex table gets initialized to NULL 4287 * or EHCI_NULL? */ 4288 sitd->sitd.sitd_next = EHCI_NULL; 4289 4290 usb_syncmem(&sitd->dma, 4291 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4292 sizeof(ehci_sitd_t), 4293 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4294 4295 sc->sc_flist[frindex] = 4296 htole32(EHCI_LINK_SITD | sitd->physaddr); 4297 4298 usb_syncmem(&sc->sc_fldma, 4299 sizeof(ehci_link_t) * frindex, 4300 sizeof(ehci_link_t), 4301 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4302 4303 sitd->u.frame_list.next = sc->sc_softsitds[frindex]; 4304 sc->sc_softsitds[frindex] = sitd; 4305 if (sitd->u.frame_list.next != NULL) 4306 sitd->u.frame_list.next->u.frame_list.prev = sitd; 4307 sitd->slot = frindex; 4308 sitd->u.frame_list.prev = NULL; 4309 4310 frindex += i; 4311 if (frindex >= sc->sc_flsize) 4312 frindex -= sc->sc_flsize; 4313 4314 sitd = sitd->xfer_next; 4315 } 4316 4317 epipe->u.isoc.cur_xfers++; 4318 epipe->u.isoc.next_frame = frindex; 4319 4320 exfer->sitdstart = start; 4321 exfer->sitdend = stop; 4322 4323 ehci_add_intr_list(sc, exfer); 4324 xfer->ux_status = USBD_IN_PROGRESS; 4325 xfer->ux_done = 0; 4326 4327 mutex_exit(&sc->sc_lock); 4328 4329 if (sc->sc_bus.ub_usepolling) { 4330 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4331 ehci_waitintr(sc, xfer); 4332 } 4333 4334 return USBD_IN_PROGRESS; 4335 } 4336 4337 Static void 4338 ehci_device_fs_isoc_abort(usbd_xfer_handle xfer) 4339 { 4340 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4341 4342 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4343 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4344 } 4345 4346 Static void 4347 ehci_device_fs_isoc_close(usbd_pipe_handle pipe) 4348 { 4349 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4350 4351 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4352 } 4353 4354 Static void 4355 ehci_device_fs_isoc_done(usbd_xfer_handle xfer) 4356 { 4357 struct ehci_xfer *exfer; 4358 ehci_softc_t *sc; 4359 struct ehci_pipe *epipe; 4360 4361 exfer = EXFER(xfer); 4362 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4363 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4364 4365 KASSERT(mutex_owned(&sc->sc_lock)); 4366 4367 epipe->u.isoc.cur_xfers--; 4368 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4369 ehci_del_intr_list(sc, exfer); 4370 ehci_rem_free_sitd_chain(sc, exfer); 4371 } 4372 4373 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4374 BUS_DMASYNC_POSTREAD); 4375 } 4376 Static usbd_status 4377 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 4378 { 4379 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4380 usbd_status err; 4381 4382 mutex_enter(&sc->sc_lock); 4383 err = usb_insert_transfer(xfer); 4384 mutex_exit(&sc->sc_lock); 4385 if (err && err != USBD_IN_PROGRESS) 4386 return err; 4387 4388 return ehci_device_isoc_start(xfer); 4389 } 4390 4391 Static usbd_status 4392 ehci_device_isoc_start(usbd_xfer_handle xfer) 4393 { 4394 struct ehci_pipe *epipe; 4395 ehci_softc_t *sc; 4396 struct ehci_xfer *exfer; 4397 ehci_soft_itd_t *itd, *prev, *start, *stop; 4398 usb_dma_t *dma_buf; 4399 int i, j, k, frames, uframes, ufrperframe; 4400 int trans_count, offs, total_length; 4401 int frindex; 4402 4403 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4404 4405 start = NULL; 4406 prev = NULL; 4407 itd = NULL; 4408 trans_count = 0; 4409 total_length = 0; 4410 exfer = (struct ehci_xfer *) xfer; 4411 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4412 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4413 4414 /* 4415 * To allow continuous transfers, above we start all transfers 4416 * immediately. However, we're still going to get usbd_start_next call 4417 * this when another xfer completes. So, check if this is already 4418 * in progress or not 4419 */ 4420 4421 if (exfer->itdstart != NULL) 4422 return USBD_IN_PROGRESS; 4423 4424 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4425 xfer, xfer->ux_length, xfer->ux_flags, 0); 4426 4427 if (sc->sc_dying) 4428 return USBD_IOERROR; 4429 4430 /* 4431 * To avoid complication, don't allow a request right now that'll span 4432 * the entire frame table. To within 4 frames, to allow some leeway 4433 * on either side of where the hc currently is. 4434 */ 4435 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4436 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4437 USBHIST_LOG(ehcidebug, 4438 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4439 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4440 return USBD_INVAL; 4441 } 4442 4443 #ifdef DIAGNOSTIC 4444 if (xfer->ux_rqflags & URQ_REQUEST) 4445 panic("ehci_device_isoc_start: request\n"); 4446 4447 if (!exfer->isdone) { 4448 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", exfer, 4449 0, 0, 0); 4450 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 4451 } 4452 exfer->isdone = 0; 4453 #endif 4454 4455 /* 4456 * Step 1: Allocate and initialize itds, how many do we need? 4457 * One per transfer if interval >= 8 microframes, fewer if we use 4458 * multiple microframes per frame. 4459 */ 4460 4461 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4462 if (i > 16 || i == 0) { 4463 /* Spec page 271 says intervals > 16 are invalid */ 4464 USBHIST_LOG(ehcidebug, "bInvertal %d invalid", i, 0, 0, 0); 4465 return USBD_INVAL; 4466 } 4467 4468 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4469 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4470 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4471 4472 if (frames == 0) { 4473 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4474 return USBD_INVAL; 4475 } 4476 4477 dma_buf = &xfer->ux_dmabuf; 4478 offs = 0; 4479 4480 for (i = 0; i < frames; i++) { 4481 int froffs = offs; 4482 itd = ehci_alloc_itd(sc); 4483 4484 if (prev != NULL) { 4485 prev->itd.itd_next = 4486 htole32(itd->physaddr | EHCI_LINK_ITD); 4487 usb_syncmem(&itd->dma, 4488 itd->offs + offsetof(ehci_itd_t, itd_next), 4489 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4490 4491 prev->xfer_next = itd; 4492 } else { 4493 start = itd; 4494 } 4495 4496 /* 4497 * Step 1.5, initialize uframes 4498 */ 4499 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4500 /* Calculate which page in the list this starts in */ 4501 int addr = DMAADDR(dma_buf, froffs); 4502 addr = EHCI_PAGE_OFFSET(addr); 4503 addr += (offs - froffs); 4504 addr = EHCI_PAGE(addr); 4505 addr /= EHCI_PAGE_SIZE; 4506 4507 /* This gets the initial offset into the first page, 4508 * looks how far further along the current uframe 4509 * offset is. Works out how many pages that is. 4510 */ 4511 4512 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4513 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4514 EHCI_ITD_SET_PG(addr) | 4515 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4516 4517 total_length += xfer->ux_frlengths[trans_count]; 4518 offs += xfer->ux_frlengths[trans_count]; 4519 trans_count++; 4520 4521 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4522 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4523 break; 4524 } 4525 } 4526 4527 /* Step 1.75, set buffer pointers. To simplify matters, all 4528 * pointers are filled out for the next 7 hardware pages in 4529 * the dma block, so no need to worry what pages to cover 4530 * and what to not. 4531 */ 4532 4533 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4534 /* 4535 * Don't try to lookup a page that's past the end 4536 * of buffer 4537 */ 4538 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4539 if (page_offs >= dma_buf->udma_block->size) 4540 break; 4541 4542 unsigned long long page = DMAADDR(dma_buf, page_offs); 4543 page = EHCI_PAGE(page); 4544 itd->itd.itd_bufr[j] = 4545 htole32(EHCI_ITD_SET_BPTR(page)); 4546 itd->itd.itd_bufr_hi[j] = 4547 htole32(page >> 32); 4548 } 4549 4550 /* 4551 * Other special values 4552 */ 4553 4554 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4555 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4556 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4557 4558 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4559 ? 1 : 0; 4560 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4561 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4562 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4563 4564 /* FIXME: handle invalid trans */ 4565 itd->itd.itd_bufr[2] |= 4566 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4567 4568 usb_syncmem(&itd->dma, 4569 itd->offs + offsetof(ehci_itd_t, itd_next), 4570 sizeof(ehci_itd_t), 4571 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4572 4573 prev = itd; 4574 } /* End of frame */ 4575 4576 stop = itd; 4577 stop->xfer_next = NULL; 4578 4579 usb_syncmem(&exfer->xfer.ux_dmabuf, 0, total_length, 4580 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4581 4582 /* 4583 * Part 2: Transfer descriptors have now been set up, now they must 4584 * be scheduled into the period frame list. Erk. Not wanting to 4585 * complicate matters, transfer is denied if the transfer spans 4586 * more than the period frame list. 4587 */ 4588 4589 mutex_enter(&sc->sc_lock); 4590 4591 /* Start inserting frames */ 4592 if (epipe->u.isoc.cur_xfers > 0) { 4593 frindex = epipe->u.isoc.next_frame; 4594 } else { 4595 frindex = EOREAD4(sc, EHCI_FRINDEX); 4596 frindex = frindex >> 3; /* Erase microframe index */ 4597 frindex += 2; 4598 } 4599 4600 if (frindex >= sc->sc_flsize) 4601 frindex &= (sc->sc_flsize - 1); 4602 4603 /* What's the frame interval? */ 4604 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4605 if (i / USB_UFRAMES_PER_FRAME == 0) 4606 i = 1; 4607 else 4608 i /= USB_UFRAMES_PER_FRAME; 4609 4610 itd = start; 4611 for (j = 0; j < frames; j++) { 4612 if (itd == NULL) 4613 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4614 4615 itd->itd.itd_next = sc->sc_flist[frindex]; 4616 if (itd->itd.itd_next == 0) 4617 /* FIXME: frindex table gets initialized to NULL 4618 * or EHCI_NULL? */ 4619 itd->itd.itd_next = EHCI_NULL; 4620 4621 usb_syncmem(&itd->dma, 4622 itd->offs + offsetof(ehci_itd_t, itd_next), 4623 sizeof(itd->itd.itd_next), 4624 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4625 4626 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4627 4628 usb_syncmem(&sc->sc_fldma, 4629 sizeof(ehci_link_t) * frindex, 4630 sizeof(ehci_link_t), 4631 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4632 4633 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4634 sc->sc_softitds[frindex] = itd; 4635 if (itd->u.frame_list.next != NULL) 4636 itd->u.frame_list.next->u.frame_list.prev = itd; 4637 itd->slot = frindex; 4638 itd->u.frame_list.prev = NULL; 4639 4640 frindex += i; 4641 if (frindex >= sc->sc_flsize) 4642 frindex -= sc->sc_flsize; 4643 4644 itd = itd->xfer_next; 4645 } 4646 4647 epipe->u.isoc.cur_xfers++; 4648 epipe->u.isoc.next_frame = frindex; 4649 4650 exfer->itdstart = start; 4651 exfer->itdend = stop; 4652 4653 ehci_add_intr_list(sc, exfer); 4654 xfer->ux_status = USBD_IN_PROGRESS; 4655 xfer->ux_done = 0; 4656 mutex_exit(&sc->sc_lock); 4657 4658 if (sc->sc_bus.ub_usepolling) { 4659 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4660 ehci_waitintr(sc, xfer); 4661 } 4662 4663 return USBD_IN_PROGRESS; 4664 } 4665 4666 Static void 4667 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4668 { 4669 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4670 4671 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4672 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4673 } 4674 4675 Static void 4676 ehci_device_isoc_close(usbd_pipe_handle pipe) 4677 { 4678 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4679 4680 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4681 } 4682 4683 Static void 4684 ehci_device_isoc_done(usbd_xfer_handle xfer) 4685 { 4686 struct ehci_xfer *exfer; 4687 ehci_softc_t *sc; 4688 struct ehci_pipe *epipe; 4689 4690 exfer = EXFER(xfer); 4691 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4692 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4693 4694 KASSERT(mutex_owned(&sc->sc_lock)); 4695 4696 epipe->u.isoc.cur_xfers--; 4697 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4698 ehci_del_intr_list(sc, exfer); 4699 ehci_rem_free_itd_chain(sc, exfer); 4700 } 4701 4702 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4703 BUS_DMASYNC_POSTREAD); 4704 4705 } 4706
Indexes created Wed Oct 01 19:09:53 GMT 2025