ehci.c revision 1.234.2.21
1 /* $NetBSD: ehci.c,v 1.234.2.21 2014/12/24 14:12:16 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.21 2014/12/24 14:12:16 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 85 #include <dev/usb/ehcireg.h> 86 #include <dev/usb/ehcivar.h> 87 #include <dev/usb/usbroothub.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 /* ehci_soft_sitd_t *sitd; */ 135 } tail; 136 union { 137 /* Control pipe */ 138 struct { 139 usb_dma_t reqdma; 140 } ctl; 141 /* Interrupt pipe */ 142 struct { 143 u_int length; 144 } intr; 145 /* Bulk pipe */ 146 struct { 147 u_int length; 148 } bulk; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 } u; 155 }; 156 157 Static usbd_status ehci_open(usbd_pipe_handle); 158 Static void ehci_poll(struct usbd_bus *); 159 Static void ehci_softintr(void *); 160 Static int ehci_intr1(ehci_softc_t *); 161 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 162 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 166 Static void ehci_idone(struct ehci_xfer *); 167 Static void ehci_timeout(void *); 168 Static void ehci_timeout_task(void *); 169 Static void ehci_intrlist_timeout(void *); 170 Static void ehci_doorbell(void *); 171 Static void ehci_pcd(void *); 172 173 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 174 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 Static int ehci_roothub_ctrl(struct usbd_bus *, 177 usb_device_request_t *, void *, int); 178 179 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 180 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 181 Static void ehci_root_intr_abort(usbd_xfer_handle); 182 Static void ehci_root_intr_close(usbd_pipe_handle); 183 Static void ehci_root_intr_done(usbd_xfer_handle); 184 185 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 186 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 187 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 188 Static void ehci_device_ctrl_close(usbd_pipe_handle); 189 Static void ehci_device_ctrl_done(usbd_xfer_handle); 190 191 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 192 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 193 Static void ehci_device_bulk_abort(usbd_xfer_handle); 194 Static void ehci_device_bulk_close(usbd_pipe_handle); 195 Static void ehci_device_bulk_done(usbd_xfer_handle); 196 197 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 198 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 199 Static void ehci_device_intr_abort(usbd_xfer_handle); 200 Static void ehci_device_intr_close(usbd_pipe_handle); 201 Static void ehci_device_intr_done(usbd_xfer_handle); 202 203 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 204 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 205 Static void ehci_device_isoc_abort(usbd_xfer_handle); 206 Static void ehci_device_isoc_close(usbd_pipe_handle); 207 Static void ehci_device_isoc_done(usbd_xfer_handle); 208 209 Static usbd_status ehci_device_fs_isoc_transfer(usbd_xfer_handle); 210 Static usbd_status ehci_device_fs_isoc_start(usbd_xfer_handle); 211 Static void ehci_device_fs_isoc_abort(usbd_xfer_handle); 212 Static void ehci_device_fs_isoc_close(usbd_pipe_handle); 213 Static void ehci_device_fs_isoc_done(usbd_xfer_handle); 214 215 Static void ehci_device_clear_toggle(usbd_pipe_handle); 216 Static void ehci_noop(usbd_pipe_handle); 217 218 Static void ehci_disown(ehci_softc_t *, int, int); 219 220 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 221 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 222 223 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 224 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 225 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 226 ehci_softc_t *, int, int, usbd_xfer_handle, 227 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 228 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 229 ehci_soft_qtd_t *); 230 231 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 232 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *); 233 Static void ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *); 234 Static void ehci_free_sitd(ehci_softc_t *, ehci_soft_sitd_t *); 235 Static void ehci_rem_free_itd_chain(ehci_softc_t *, 236 struct ehci_xfer *); 237 Static void ehci_rem_free_sitd_chain(ehci_softc_t *, 238 struct ehci_xfer *); 239 Static void ehci_abort_isoc_xfer(usbd_xfer_handle, 240 usbd_status); 241 242 Static usbd_status ehci_device_request(usbd_xfer_handle); 243 244 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 245 int); 246 247 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 248 ehci_soft_qh_t *); 249 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 250 ehci_soft_qh_t *); 251 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 252 Static void ehci_sync_hc(ehci_softc_t *); 253 254 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 255 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 256 257 #ifdef EHCI_DEBUG 258 Static ehci_softc_t *theehci; 259 void ehci_dump(void); 260 #endif 261 262 #ifdef EHCI_DEBUG 263 Static void ehci_dump_regs(ehci_softc_t *); 264 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 265 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 266 Static void ehci_dump_qtd(ehci_qtd_t *); 267 Static void ehci_dump_sqh(ehci_soft_qh_t *); 268 Static void ehci_dump_sitd(struct ehci_soft_itd *); 269 Static void ehci_dump_itd(struct ehci_soft_itd *); 270 Static void ehci_dump_exfer(struct ehci_xfer *); 271 #endif 272 273 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 274 275 #define ehci_add_intr_list(sc, ex) \ 276 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 277 #define ehci_del_intr_list(sc, ex) \ 278 do { \ 279 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 280 (ex)->ex_next.tqe_prev = NULL; \ 281 } while (0) 282 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 283 284 Static const struct usbd_bus_methods ehci_bus_methods = { 285 .ubm_open = ehci_open, 286 .ubm_softint = ehci_softintr, 287 .ubm_dopoll = ehci_poll, 288 .ubm_allocx = ehci_allocx, 289 .ubm_freex = ehci_freex, 290 .ubm_getlock = ehci_get_lock, 291 .ubm_rhctrl = ehci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 295 .upm_transfer = ehci_root_intr_transfer, 296 .upm_start = ehci_root_intr_start, 297 .upm_abort = ehci_root_intr_abort, 298 .upm_close = ehci_root_intr_close, 299 .upm_cleartoggle = ehci_noop, 300 .upm_done = ehci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 304 .upm_transfer = ehci_device_ctrl_transfer, 305 .upm_start = ehci_device_ctrl_start, 306 .upm_abort = ehci_device_ctrl_abort, 307 .upm_close = ehci_device_ctrl_close, 308 .upm_cleartoggle = ehci_noop, 309 .upm_done = ehci_device_ctrl_done, 310 }; 311 312 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 313 .upm_transfer = ehci_device_intr_transfer, 314 .upm_start = ehci_device_intr_start, 315 .upm_abort = ehci_device_intr_abort, 316 .upm_close = ehci_device_intr_close, 317 .upm_cleartoggle = ehci_device_clear_toggle, 318 .upm_done = ehci_device_intr_done, 319 }; 320 321 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 322 .upm_transfer = ehci_device_bulk_transfer, 323 .upm_start = ehci_device_bulk_start, 324 .upm_abort = ehci_device_bulk_abort, 325 .upm_close = ehci_device_bulk_close, 326 .upm_cleartoggle = ehci_device_clear_toggle, 327 .upm_done = ehci_device_bulk_done, 328 }; 329 330 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 331 .upm_transfer = ehci_device_isoc_transfer, 332 .upm_start = ehci_device_isoc_start, 333 .upm_abort = ehci_device_isoc_abort, 334 .upm_close = ehci_device_isoc_close, 335 .upm_cleartoggle = ehci_noop, 336 .upm_done = ehci_device_isoc_done, 337 }; 338 339 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 340 .upm_transfer = ehci_device_fs_isoc_transfer, 341 .upm_start = ehci_device_fs_isoc_start, 342 .upm_abort = ehci_device_fs_isoc_abort, 343 .upm_close = ehci_device_fs_isoc_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_fs_isoc_done, 346 }; 347 348 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 349 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 350 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 351 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 352 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 353 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 354 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 355 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 356 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 357 }; 358 359 int 360 ehci_init(ehci_softc_t *sc) 361 { 362 uint32_t vers, sparams, cparams, hcr; 363 u_int i; 364 usbd_status err; 365 ehci_soft_qh_t *sqh; 366 u_int ncomp; 367 368 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 369 #ifdef EHCI_DEBUG 370 theehci = sc; 371 #endif 372 373 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 374 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 375 cv_init(&sc->sc_softwake_cv, "ehciab"); 376 cv_init(&sc->sc_doorbell, "ehcidi"); 377 378 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 379 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 380 381 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 382 ehci_doorbell, sc); 383 KASSERT(sc->sc_doorbell_si != NULL); 384 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 385 ehci_pcd, sc); 386 KASSERT(sc->sc_pcd_si != NULL); 387 388 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 389 390 vers = EREAD2(sc, EHCI_HCIVERSION); 391 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 392 vers >> 8, vers & 0xff); 393 394 sparams = EREAD4(sc, EHCI_HCSPARAMS); 395 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 396 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 397 ncomp = EHCI_HCS_N_CC(sparams); 398 if (ncomp != sc->sc_ncomp) { 399 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 400 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 401 #if NOHCI == 0 || NUHCI == 0 402 aprint_error("%s: ohci or uhci probably not configured\n", 403 device_xname(sc->sc_dev)); 404 #endif 405 if (ncomp < sc->sc_ncomp) 406 sc->sc_ncomp = ncomp; 407 } 408 if (sc->sc_ncomp > 0) { 409 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 410 aprint_normal("%s: companion controller%s, %d port%s each:", 411 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 412 EHCI_HCS_N_PCC(sparams), 413 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 414 for (i = 0; i < sc->sc_ncomp; i++) 415 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 416 aprint_normal("\n"); 417 } 418 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 419 cparams = EREAD4(sc, EHCI_HCCPARAMS); 420 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 421 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 422 423 if (EHCI_HCC_64BIT(cparams)) { 424 /* MUST clear segment register if 64 bit capable. */ 425 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 426 } 427 428 sc->sc_bus.ub_revision = USBREV_2_0; 429 sc->sc_bus.ub_usedma = true; 430 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 431 432 /* Reset the controller */ 433 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 434 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 435 usb_delay_ms(&sc->sc_bus, 1); 436 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 437 for (i = 0; i < 100; i++) { 438 usb_delay_ms(&sc->sc_bus, 1); 439 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 440 if (!hcr) 441 break; 442 } 443 if (hcr) { 444 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 445 return EIO; 446 } 447 if (sc->sc_vendor_init) 448 sc->sc_vendor_init(sc); 449 450 /* 451 * If we are doing embedded transaction translation function, force 452 * the controller to host mode. 453 */ 454 if (sc->sc_flags & EHCIF_ETTF) { 455 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 456 usbmode &= ~EHCI_USBMODE_CM; 457 usbmode |= EHCI_USBMODE_CM_HOST; 458 EWRITE4(sc, EHCI_USBMODE, usbmode); 459 } 460 461 /* XXX need proper intr scheduling */ 462 sc->sc_rand = 96; 463 464 /* frame list size at default, read back what we got and use that */ 465 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 466 case 0: sc->sc_flsize = 1024; break; 467 case 1: sc->sc_flsize = 512; break; 468 case 2: sc->sc_flsize = 256; break; 469 case 3: return EIO; 470 } 471 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 472 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 473 if (err) 474 return err; 475 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 476 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 477 478 for (i = 0; i < sc->sc_flsize; i++) { 479 sc->sc_flist[i] = EHCI_NULL; 480 } 481 482 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 483 484 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 485 KM_SLEEP); 486 if (sc->sc_softitds == NULL) 487 return ENOMEM; 488 LIST_INIT(&sc->sc_freeitds); 489 LIST_INIT(&sc->sc_freesitds); 490 TAILQ_INIT(&sc->sc_intrhead); 491 492 /* Set up the bus struct. */ 493 sc->sc_bus.ub_methods = &ehci_bus_methods; 494 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 495 496 sc->sc_eintrs = EHCI_NORMAL_INTRS; 497 498 /* 499 * Allocate the interrupt dummy QHs. These are arranged to give poll 500 * intervals that are powers of 2 times 1ms. 501 */ 502 for (i = 0; i < EHCI_INTRQHS; i++) { 503 sqh = ehci_alloc_sqh(sc); 504 if (sqh == NULL) { 505 err = ENOMEM; 506 goto bad1; 507 } 508 sc->sc_islots[i].sqh = sqh; 509 } 510 for (i = 0; i < EHCI_INTRQHS; i++) { 511 sqh = sc->sc_islots[i].sqh; 512 if (i == 0) { 513 /* The last (1ms) QH terminates. */ 514 sqh->qh.qh_link = EHCI_NULL; 515 sqh->next = NULL; 516 } else { 517 /* Otherwise the next QH has half the poll interval */ 518 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 519 sqh->qh.qh_link = htole32(sqh->next->physaddr | 520 EHCI_LINK_QH); 521 } 522 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 523 sqh->qh.qh_curqtd = EHCI_NULL; 524 sqh->next = NULL; 525 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 526 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 527 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 528 sqh->sqtd = NULL; 529 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 531 } 532 /* Point the frame list at the last level (128ms). */ 533 for (i = 0; i < sc->sc_flsize; i++) { 534 int j; 535 536 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 537 revbits[i & (EHCI_MAX_POLLRATE-1)]; 538 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 539 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 540 i)].sqh->physaddr); 541 } 542 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 543 BUS_DMASYNC_PREWRITE); 544 545 /* Allocate dummy QH that starts the async list. */ 546 sqh = ehci_alloc_sqh(sc); 547 if (sqh == NULL) { 548 err = ENOMEM; 549 goto bad1; 550 } 551 /* Fill the QH */ 552 sqh->qh.qh_endp = 553 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 554 sqh->qh.qh_link = 555 htole32(sqh->physaddr | EHCI_LINK_QH); 556 sqh->qh.qh_curqtd = EHCI_NULL; 557 sqh->next = NULL; 558 /* Fill the overlay qTD */ 559 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 560 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 561 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 562 sqh->sqtd = NULL; 563 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 564 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 565 #ifdef EHCI_DEBUG 566 ehci_dump_sqh(sqh); 567 #endif 568 569 /* Point to async list */ 570 sc->sc_async_head = sqh; 571 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 572 573 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 574 575 /* Turn on controller */ 576 EOWRITE4(sc, EHCI_USBCMD, 577 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 578 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 579 EHCI_CMD_ASE | 580 EHCI_CMD_PSE | 581 EHCI_CMD_RS); 582 583 /* Take over port ownership */ 584 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 585 586 for (i = 0; i < 100; i++) { 587 usb_delay_ms(&sc->sc_bus, 1); 588 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 589 if (!hcr) 590 break; 591 } 592 if (hcr) { 593 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 594 return EIO; 595 } 596 597 /* Enable interrupts */ 598 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 599 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 600 601 return 0; 602 603 #if 0 604 bad2: 605 ehci_free_sqh(sc, sc->sc_async_head); 606 #endif 607 bad1: 608 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 609 return err; 610 } 611 612 int 613 ehci_intr(void *v) 614 { 615 ehci_softc_t *sc = v; 616 int ret = 0; 617 618 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 619 620 if (sc == NULL) 621 return 0; 622 623 mutex_spin_enter(&sc->sc_intr_lock); 624 625 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 626 goto done; 627 628 /* If we get an interrupt while polling, then just ignore it. */ 629 if (sc->sc_bus.ub_usepolling) { 630 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 631 632 if (intrs) 633 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 634 #ifdef DIAGNOSTIC 635 USBHIST_LOGN(ehcidebug, 16, 636 "ignored interrupt while polling", 0, 0, 0, 0); 637 #endif 638 goto done; 639 } 640 641 ret = ehci_intr1(sc); 642 643 done: 644 mutex_spin_exit(&sc->sc_intr_lock); 645 return ret; 646 } 647 648 Static int 649 ehci_intr1(ehci_softc_t *sc) 650 { 651 uint32_t intrs, eintrs; 652 653 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 654 655 /* In case the interrupt occurs before initialization has completed. */ 656 if (sc == NULL) { 657 #ifdef DIAGNOSTIC 658 printf("ehci_intr1: sc == NULL\n"); 659 #endif 660 return 0; 661 } 662 663 KASSERT(mutex_owned(&sc->sc_intr_lock)); 664 665 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 666 if (!intrs) 667 return 0; 668 669 eintrs = intrs & sc->sc_eintrs; 670 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 671 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 672 if (!eintrs) 673 return 0; 674 675 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 676 if (eintrs & EHCI_STS_IAA) { 677 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 678 kpreempt_disable(); 679 KASSERT(sc->sc_doorbell_si != NULL); 680 softint_schedule(sc->sc_doorbell_si); 681 kpreempt_enable(); 682 eintrs &= ~EHCI_STS_IAA; 683 } 684 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 685 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 686 eintrs & EHCI_STS_INT ? 1 : 0, 687 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 688 usb_schedsoftintr(&sc->sc_bus); 689 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 690 } 691 if (eintrs & EHCI_STS_HSE) { 692 printf("%s: unrecoverable error, controller halted\n", 693 device_xname(sc->sc_dev)); 694 /* XXX what else */ 695 } 696 if (eintrs & EHCI_STS_PCD) { 697 kpreempt_disable(); 698 KASSERT(sc->sc_pcd_si != NULL); 699 softint_schedule(sc->sc_pcd_si); 700 kpreempt_enable(); 701 eintrs &= ~EHCI_STS_PCD; 702 } 703 704 if (eintrs != 0) { 705 /* Block unprocessed interrupts. */ 706 sc->sc_eintrs &= ~eintrs; 707 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 708 printf("%s: blocking intrs 0x%x\n", 709 device_xname(sc->sc_dev), eintrs); 710 } 711 712 return 1; 713 } 714 715 Static void 716 ehci_doorbell(void *addr) 717 { 718 ehci_softc_t *sc = addr; 719 720 mutex_enter(&sc->sc_lock); 721 cv_broadcast(&sc->sc_doorbell); 722 mutex_exit(&sc->sc_lock); 723 } 724 725 Static void 726 ehci_pcd(void *addr) 727 { 728 ehci_softc_t *sc = addr; 729 usbd_xfer_handle xfer; 730 u_char *p; 731 int i, m; 732 733 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 734 735 mutex_enter(&sc->sc_lock); 736 xfer = sc->sc_intrxfer; 737 738 if (xfer == NULL) { 739 /* Just ignore the change. */ 740 goto done; 741 } 742 743 p = xfer->ux_buf; 744 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 745 memset(p, 0, xfer->ux_length); 746 for (i = 1; i <= m; i++) { 747 /* Pick out CHANGE bits from the status reg. */ 748 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 749 p[i/8] |= 1 << (i%8); 750 if (i % 8 == 7) 751 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 752 p[i/8], 0, 0); 753 } 754 xfer->ux_actlen = xfer->ux_length; 755 xfer->ux_status = USBD_NORMAL_COMPLETION; 756 757 usb_transfer_complete(xfer); 758 759 done: 760 mutex_exit(&sc->sc_lock); 761 } 762 763 Static void 764 ehci_softintr(void *v) 765 { 766 struct usbd_bus *bus = v; 767 ehci_softc_t *sc = bus->ub_hcpriv; 768 struct ehci_xfer *ex, *nextex; 769 770 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 771 772 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 773 774 /* 775 * The only explanation I can think of for why EHCI is as brain dead 776 * as UHCI interrupt-wise is that Intel was involved in both. 777 * An interrupt just tells us that something is done, we have no 778 * clue what, so we need to scan through all active transfers. :-( 779 */ 780 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 781 nextex = TAILQ_NEXT(ex, ex_next); 782 ehci_check_intr(sc, ex); 783 } 784 785 /* Schedule a callout to catch any dropped transactions. */ 786 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 787 !TAILQ_EMPTY(&sc->sc_intrhead)) 788 callout_reset(&sc->sc_tmo_intrlist, 789 hz, ehci_intrlist_timeout, sc); 790 791 if (sc->sc_softwake) { 792 sc->sc_softwake = 0; 793 cv_broadcast(&sc->sc_softwake_cv); 794 } 795 } 796 797 /* Check for an interrupt. */ 798 Static void 799 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 800 { 801 usbd_device_handle dev = ex->ex_xfer.ux_pipe->up_dev; 802 int attr; 803 804 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 805 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 806 807 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 808 809 attr = ex->ex_xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 810 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 811 if (dev->ud_speed == USB_SPEED_HIGH) 812 ehci_check_itd_intr(sc, ex); 813 else 814 ehci_check_sitd_intr(sc, ex); 815 } else 816 ehci_check_qh_intr(sc, ex); 817 818 return; 819 } 820 821 Static void 822 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 823 { 824 ehci_soft_qtd_t *sqtd, *lsqtd; 825 uint32_t status; 826 827 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 828 829 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 830 831 if (ex->ex_sqtdstart == NULL) { 832 printf("ehci_check_qh_intr: not valid sqtd\n"); 833 return; 834 } 835 836 lsqtd = ex->ex_sqtdend; 837 #ifdef DIAGNOSTIC 838 if (lsqtd == NULL) { 839 printf("ehci_check_qh_intr: lsqtd==0\n"); 840 return; 841 } 842 #endif 843 /* 844 * If the last TD is still active we need to check whether there 845 * is an error somewhere in the middle, or whether there was a 846 * short packet (SPD and not ACTIVE). 847 */ 848 usb_syncmem(&lsqtd->dma, 849 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 850 sizeof(lsqtd->qtd.qtd_status), 851 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 852 status = le32toh(lsqtd->qtd.qtd_status); 853 usb_syncmem(&lsqtd->dma, 854 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 855 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 856 if (status & EHCI_QTD_ACTIVE) { 857 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 858 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd; 859 sqtd = sqtd->nextqtd) { 860 usb_syncmem(&sqtd->dma, 861 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 862 sizeof(sqtd->qtd.qtd_status), 863 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 864 status = le32toh(sqtd->qtd.qtd_status); 865 usb_syncmem(&sqtd->dma, 866 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 867 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 868 /* If there's an active QTD the xfer isn't done. */ 869 if (status & EHCI_QTD_ACTIVE) 870 break; 871 /* Any kind of error makes the xfer done. */ 872 if (status & EHCI_QTD_HALTED) 873 goto done; 874 /* Handle short packets */ 875 if (EHCI_QTD_GET_BYTES(status) != 0) { 876 usbd_pipe_handle pipe = ex->ex_xfer.ux_pipe; 877 usb_endpoint_descriptor_t *ed = 878 pipe->up_endpoint->ue_edesc; 879 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 880 881 /* 882 * If we get here for a control transfer then 883 * we need to let the hardware complete the 884 * status phase. That is, we're not done 885 * quite yet. 886 * 887 * Otherwise, we're done. 888 */ 889 if (xt == UE_CONTROL) { 890 break; 891 } 892 goto done; 893 } 894 } 895 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 896 ex, ex->ex_sqtdstart, 0, 0); 897 return; 898 } 899 done: 900 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 901 callout_stop(&ex->ex_xfer.ux_callout); 902 ehci_idone(ex); 903 } 904 905 Static void 906 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 907 { 908 ehci_soft_itd_t *itd; 909 int i; 910 911 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 912 913 KASSERT(mutex_owned(&sc->sc_lock)); 914 915 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 916 return; 917 918 if (ex->ex_itdstart == NULL) { 919 printf("ehci_check_itd_intr: not valid itd\n"); 920 return; 921 } 922 923 itd = ex->ex_itdend; 924 #ifdef DIAGNOSTIC 925 if (itd == NULL) { 926 printf("ehci_check_itd_intr: itdend == 0\n"); 927 return; 928 } 929 #endif 930 931 /* 932 * check no active transfers in last itd, meaning we're finished 933 */ 934 935 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 936 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 937 BUS_DMASYNC_POSTREAD); 938 939 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 940 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 941 break; 942 } 943 944 if (i == EHCI_ITD_NUFRAMES) { 945 goto done; /* All 8 descriptors inactive, it's done */ 946 } 947 948 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 949 ex->ex_itdstart, 0, 0); 950 return; 951 done: 952 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 953 callout_stop(&ex->ex_xfer.ux_callout); 954 ehci_idone(ex); 955 } 956 957 void 958 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 959 { 960 ehci_soft_sitd_t *sitd; 961 962 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 963 964 KASSERT(mutex_owned(&sc->sc_lock)); 965 966 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 967 return; 968 969 if (ex->ex_sitdstart == NULL) { 970 printf("ehci_check_sitd_intr: not valid sitd\n"); 971 return; 972 } 973 974 sitd = ex->ex_sitdend; 975 #ifdef DIAGNOSTIC 976 if (sitd == NULL) { 977 printf("ehci_check_sitd_intr: sitdend == 0\n"); 978 return; 979 } 980 #endif 981 982 /* 983 * check no active transfers in last sitd, meaning we're finished 984 */ 985 986 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 987 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 988 BUS_DMASYNC_POSTREAD); 989 990 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 991 return; 992 993 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 994 callout_stop(&(ex->ex_xfer.ux_callout)); 995 ehci_idone(ex); 996 } 997 998 999 Static void 1000 ehci_idone(struct ehci_xfer *ex) 1001 { 1002 usbd_xfer_handle xfer = &ex->ex_xfer; 1003 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1004 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1005 ehci_soft_qtd_t *sqtd, *lsqtd; 1006 uint32_t status = 0, nstatus = 0; 1007 int actlen; 1008 1009 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1010 1011 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1012 1013 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1014 1015 #ifdef DIAGNOSTIC 1016 if (ex->ex_isdone) { 1017 printf("ehci_idone: ex=%p is done!\n", ex); 1018 #ifdef EHCI_DEBUG 1019 ehci_dump_exfer(ex); 1020 #endif 1021 return; 1022 } 1023 ex->ex_isdone = 1; 1024 #endif 1025 1026 if (xfer->ux_status == USBD_CANCELLED || 1027 xfer->ux_status == USBD_TIMEOUT) { 1028 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1029 return; 1030 } 1031 1032 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1033 #ifdef EHCI_DEBUG 1034 ehci_dump_sqtds(ex->ex_sqtdstart); 1035 #endif 1036 1037 /* The transfer is done, compute actual length and status. */ 1038 1039 u_int xfertype, speed; 1040 1041 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1042 speed = xfer->ux_pipe->up_dev->ud_speed; 1043 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1044 /* HS isoc transfer */ 1045 1046 struct ehci_soft_itd *itd; 1047 int i, nframes, len, uframes; 1048 1049 nframes = 0; 1050 actlen = 0; 1051 1052 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1053 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1054 1055 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1056 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1057 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1058 BUS_DMASYNC_POSTREAD); 1059 1060 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1061 /* XXX - driver didn't fill in the frame full 1062 * of uframes. This leads to scheduling 1063 * inefficiencies, but working around 1064 * this doubles complexity of tracking 1065 * an xfer. 1066 */ 1067 if (nframes >= xfer->ux_nframes) 1068 break; 1069 1070 status = le32toh(itd->itd.itd_ctl[i]); 1071 len = EHCI_ITD_GET_LEN(status); 1072 if (EHCI_ITD_GET_STATUS(status) != 0) 1073 len = 0; /*No valid data on error*/ 1074 1075 xfer->ux_frlengths[nframes++] = len; 1076 actlen += len; 1077 } 1078 1079 if (nframes >= xfer->ux_nframes) 1080 break; 1081 } 1082 1083 xfer->ux_actlen = actlen; 1084 xfer->ux_status = USBD_NORMAL_COMPLETION; 1085 goto end; 1086 } 1087 1088 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1089 /* FS isoc transfer */ 1090 struct ehci_soft_sitd *sitd; 1091 int nframes, len; 1092 1093 nframes = 0; 1094 actlen = 0; 1095 1096 for (sitd = ex->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1097 usb_syncmem(&sitd->dma,sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 1098 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 1099 BUS_DMASYNC_POSTREAD); 1100 1101 /* XXX - driver didn't fill in the frame full 1102 * of uframes. This leads to scheduling 1103 * inefficiencies, but working around 1104 * this doubles complexity of tracking 1105 * an xfer. 1106 */ 1107 if (nframes >= xfer->ux_nframes) 1108 break; 1109 1110 status = le32toh(sitd->sitd.sitd_trans); 1111 len = EHCI_SITD_GET_LEN(status); 1112 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1113 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1114 /* No valid data on error */ 1115 len = xfer->ux_frlengths[nframes]; 1116 } 1117 1118 /* 1119 * frlengths[i]: # of bytes to send 1120 * len: # of bytes host didn't send 1121 */ 1122 xfer->ux_frlengths[nframes] -= len; 1123 /* frlengths[i]: # of bytes host sent */ 1124 actlen += xfer->ux_frlengths[nframes++]; 1125 1126 if (nframes >= xfer->ux_nframes) 1127 break; 1128 } 1129 1130 xfer->ux_actlen = actlen; 1131 xfer->ux_status = USBD_NORMAL_COMPLETION; 1132 goto end; 1133 } 1134 KASSERT(xfertype != UE_ISOCHRONOUS); 1135 1136 /* Continue processing xfers using queue heads */ 1137 1138 lsqtd = ex->ex_sqtdend; 1139 actlen = 0; 1140 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd->nextqtd; 1141 sqtd = sqtd->nextqtd) { 1142 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1143 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1144 nstatus = le32toh(sqtd->qtd.qtd_status); 1145 if (nstatus & EHCI_QTD_ACTIVE) 1146 break; 1147 1148 status = nstatus; 1149 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1150 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1151 } 1152 1153 1154 /* 1155 * If there are left over TDs we need to update the toggle. 1156 * The default pipe doesn't need it since control transfers 1157 * start the toggle at 0 every time. 1158 * For a short transfer we need to update the toggle for the missing 1159 * packets within the qTD. 1160 */ 1161 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1162 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1163 USBHIST_LOG(ehcidebug, 1164 "toggle update status=0x%08x nstatus=0x%08x", 1165 status, nstatus, 0, 0); 1166 #if 0 1167 ehci_dump_sqh(epipe->sqh); 1168 ehci_dump_sqtds(ex->ex_sqtdstart); 1169 #endif 1170 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1171 } 1172 1173 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1174 actlen, status, 0); 1175 xfer->ux_actlen = actlen; 1176 if (status & EHCI_QTD_HALTED) { 1177 #ifdef EHCI_DEBUG 1178 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1179 xfer->ux_pipe->up_dev->ud_addr, 1180 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1181 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d stat=%#x", 1182 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1183 status, 0); 1184 USBHIST_LOG(ehcidebug, 1185 "active =%d halted=%d buferr=%d babble=%d", 1186 status & EHCI_QTD_ACTIVE ? 1 : 0, 1187 status & EHCI_QTD_HALTED ? 1 : 0, 1188 status & EHCI_QTD_BUFERR ? 1 : 0, 1189 status & EHCI_QTD_BABBLE ? 1 : 0); 1190 1191 USBHIST_LOG(ehcidebug, 1192 "xacterr=%d missed=%d split =%d ping =%d", 1193 status & EHCI_QTD_XACTERR ? 1 : 0, 1194 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1195 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1196 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1197 1198 ehci_dump_sqh(epipe->sqh); 1199 ehci_dump_sqtds(ex->ex_sqtdstart); 1200 #endif 1201 /* low&full speed has an extra error flag */ 1202 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1203 EHCI_QH_SPEED_HIGH) 1204 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1205 else 1206 status &= EHCI_QTD_STATERRS; 1207 if (status == 0) /* no other errors means a stall */ { 1208 xfer->ux_status = USBD_STALLED; 1209 } else { 1210 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1211 } 1212 /* XXX need to reset TT on missed microframe */ 1213 if (status & EHCI_QTD_MISSEDMICRO) { 1214 printf("%s: missed microframe, TT reset not " 1215 "implemented, hub might be inoperational\n", 1216 device_xname(sc->sc_dev)); 1217 } 1218 } else { 1219 xfer->ux_status = USBD_NORMAL_COMPLETION; 1220 } 1221 1222 end: 1223 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1224 * during this call, before methods->done is called: dma sync required 1225 * beforehand? */ 1226 usb_transfer_complete(xfer); 1227 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1228 } 1229 1230 /* 1231 * Wait here until controller claims to have an interrupt. 1232 * Then call ehci_intr and return. Use timeout to avoid waiting 1233 * too long. 1234 */ 1235 Static void 1236 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1237 { 1238 int timo; 1239 uint32_t intrs; 1240 1241 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1242 1243 xfer->ux_status = USBD_IN_PROGRESS; 1244 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1245 usb_delay_ms(&sc->sc_bus, 1); 1246 if (sc->sc_dying) 1247 break; 1248 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1249 sc->sc_eintrs; 1250 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1251 #ifdef EHCI_DEBUG 1252 if (ehcidebug > 15) 1253 ehci_dump_regs(sc); 1254 #endif 1255 if (intrs) { 1256 mutex_spin_enter(&sc->sc_intr_lock); 1257 ehci_intr1(sc); 1258 mutex_spin_exit(&sc->sc_intr_lock); 1259 if (xfer->ux_status != USBD_IN_PROGRESS) 1260 return; 1261 } 1262 } 1263 1264 /* Timeout */ 1265 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1266 xfer->ux_status = USBD_TIMEOUT; 1267 mutex_enter(&sc->sc_lock); 1268 usb_transfer_complete(xfer); 1269 mutex_exit(&sc->sc_lock); 1270 /* XXX should free TD */ 1271 } 1272 1273 Static void 1274 ehci_poll(struct usbd_bus *bus) 1275 { 1276 ehci_softc_t *sc = bus->ub_hcpriv; 1277 1278 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1279 1280 #ifdef EHCI_DEBUG 1281 static int last; 1282 int new; 1283 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1284 if (new != last) { 1285 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1286 last = new; 1287 } 1288 #endif 1289 1290 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1291 mutex_spin_enter(&sc->sc_intr_lock); 1292 ehci_intr1(sc); 1293 mutex_spin_exit(&sc->sc_intr_lock); 1294 } 1295 } 1296 1297 void 1298 ehci_childdet(device_t self, device_t child) 1299 { 1300 struct ehci_softc *sc = device_private(self); 1301 1302 KASSERT(sc->sc_child == child); 1303 sc->sc_child = NULL; 1304 } 1305 1306 int 1307 ehci_detach(struct ehci_softc *sc, int flags) 1308 { 1309 int rv = 0; 1310 1311 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1312 1313 if (sc->sc_child != NULL) 1314 rv = config_detach(sc->sc_child, flags); 1315 1316 if (rv != 0) 1317 return rv; 1318 1319 callout_halt(&sc->sc_tmo_intrlist, NULL); 1320 callout_destroy(&sc->sc_tmo_intrlist); 1321 1322 /* XXX free other data structures XXX */ 1323 if (sc->sc_softitds) 1324 kmem_free(sc->sc_softitds, 1325 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1326 cv_destroy(&sc->sc_doorbell); 1327 cv_destroy(&sc->sc_softwake_cv); 1328 1329 #if 0 1330 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1331 1332 softint_disestablish(sc->sc_doorbell_si); 1333 softint_disestablish(sc->sc_pcd_si); 1334 1335 mutex_destroy(&sc->sc_lock); 1336 mutex_destroy(&sc->sc_intr_lock); 1337 #endif 1338 1339 pool_cache_destroy(sc->sc_xferpool); 1340 1341 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1342 1343 return rv; 1344 } 1345 1346 1347 int 1348 ehci_activate(device_t self, enum devact act) 1349 { 1350 struct ehci_softc *sc = device_private(self); 1351 1352 switch (act) { 1353 case DVACT_DEACTIVATE: 1354 sc->sc_dying = 1; 1355 return 0; 1356 default: 1357 return EOPNOTSUPP; 1358 } 1359 } 1360 1361 /* 1362 * Handle suspend/resume. 1363 * 1364 * We need to switch to polling mode here, because this routine is 1365 * called from an interrupt context. This is all right since we 1366 * are almost suspended anyway. 1367 * 1368 * Note that this power handler isn't to be registered directly; the 1369 * bus glue needs to call out to it. 1370 */ 1371 bool 1372 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1373 { 1374 ehci_softc_t *sc = device_private(dv); 1375 int i; 1376 uint32_t cmd, hcr; 1377 1378 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1379 1380 mutex_spin_enter(&sc->sc_intr_lock); 1381 sc->sc_bus.ub_usepolling++; 1382 mutex_spin_exit(&sc->sc_intr_lock); 1383 1384 for (i = 1; i <= sc->sc_noport; i++) { 1385 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1386 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1387 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1388 } 1389 1390 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1391 1392 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1393 EOWRITE4(sc, EHCI_USBCMD, cmd); 1394 1395 for (i = 0; i < 100; i++) { 1396 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1397 if (hcr == 0) 1398 break; 1399 1400 usb_delay_ms(&sc->sc_bus, 1); 1401 } 1402 if (hcr != 0) 1403 printf("%s: reset timeout\n", device_xname(dv)); 1404 1405 cmd &= ~EHCI_CMD_RS; 1406 EOWRITE4(sc, EHCI_USBCMD, cmd); 1407 1408 for (i = 0; i < 100; i++) { 1409 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1410 if (hcr == EHCI_STS_HCH) 1411 break; 1412 1413 usb_delay_ms(&sc->sc_bus, 1); 1414 } 1415 if (hcr != EHCI_STS_HCH) 1416 printf("%s: config timeout\n", device_xname(dv)); 1417 1418 mutex_spin_enter(&sc->sc_intr_lock); 1419 sc->sc_bus.ub_usepolling--; 1420 mutex_spin_exit(&sc->sc_intr_lock); 1421 1422 return true; 1423 } 1424 1425 bool 1426 ehci_resume(device_t dv, const pmf_qual_t *qual) 1427 { 1428 ehci_softc_t *sc = device_private(dv); 1429 int i; 1430 uint32_t cmd, hcr; 1431 1432 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1433 1434 /* restore things in case the bios sucks */ 1435 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1436 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1437 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1438 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1439 1440 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1441 1442 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1443 1444 hcr = 0; 1445 for (i = 1; i <= sc->sc_noport; i++) { 1446 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1447 if ((cmd & EHCI_PS_PO) == 0 && 1448 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1449 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1450 hcr = 1; 1451 } 1452 } 1453 1454 if (hcr) { 1455 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1456 1457 for (i = 1; i <= sc->sc_noport; i++) { 1458 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1459 if ((cmd & EHCI_PS_PO) == 0 && 1460 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1461 EOWRITE4(sc, EHCI_PORTSC(i), 1462 cmd & ~EHCI_PS_FPR); 1463 } 1464 } 1465 1466 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1467 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1468 1469 for (i = 0; i < 100; i++) { 1470 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1471 if (hcr != EHCI_STS_HCH) 1472 break; 1473 1474 usb_delay_ms(&sc->sc_bus, 1); 1475 } 1476 if (hcr == EHCI_STS_HCH) 1477 printf("%s: config timeout\n", device_xname(dv)); 1478 1479 return true; 1480 } 1481 1482 /* 1483 * Shut down the controller when the system is going down. 1484 */ 1485 bool 1486 ehci_shutdown(device_t self, int flags) 1487 { 1488 ehci_softc_t *sc = device_private(self); 1489 1490 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1491 1492 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1493 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1494 return true; 1495 } 1496 1497 Static usbd_xfer_handle 1498 ehci_allocx(struct usbd_bus *bus) 1499 { 1500 struct ehci_softc *sc = bus->ub_hcpriv; 1501 usbd_xfer_handle xfer; 1502 1503 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1504 if (xfer != NULL) { 1505 memset(xfer, 0, sizeof(struct ehci_xfer)); 1506 #ifdef DIAGNOSTIC 1507 EXFER(xfer)->ex_isdone = 1; 1508 xfer->ux_state = XFER_BUSY; 1509 #endif 1510 } 1511 return xfer; 1512 } 1513 1514 Static void 1515 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1516 { 1517 struct ehci_softc *sc = bus->ub_hcpriv; 1518 1519 #ifdef DIAGNOSTIC 1520 if (xfer->ux_state != XFER_BUSY) { 1521 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1522 xfer->ux_state); 1523 } 1524 xfer->ux_state = XFER_FREE; 1525 if (!EXFER(xfer)->ex_isdone) { 1526 printf("ehci_freex: !isdone\n"); 1527 } 1528 #endif 1529 pool_cache_put(sc->sc_xferpool, xfer); 1530 } 1531 1532 Static void 1533 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1534 { 1535 struct ehci_softc *sc = bus->ub_hcpriv; 1536 1537 *lock = &sc->sc_lock; 1538 } 1539 1540 Static void 1541 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1542 { 1543 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1544 1545 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1546 1547 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1548 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1549 #ifdef EHCI_DEBUG 1550 if (ehcidebug) 1551 usbd_dump_pipe(pipe); 1552 #endif 1553 epipe->nexttoggle = 0; 1554 } 1555 1556 Static void 1557 ehci_noop(usbd_pipe_handle pipe) 1558 { 1559 } 1560 1561 #ifdef EHCI_DEBUG 1562 /* 1563 * Unused function - this is meant to be called from a kernel 1564 * debugger. 1565 */ 1566 void 1567 ehci_dump(void) 1568 { 1569 ehci_softc_t *sc = theehci; 1570 int i; 1571 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1572 EOREAD4(sc, EHCI_USBCMD), 1573 EOREAD4(sc, EHCI_USBSTS), 1574 EOREAD4(sc, EHCI_USBINTR)); 1575 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1576 EOREAD4(sc, EHCI_FRINDEX), 1577 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1578 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1579 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1580 for (i = 1; i <= sc->sc_noport; i++) 1581 printf("port %d status=0x%08x\n", i, 1582 EOREAD4(sc, EHCI_PORTSC(i))); 1583 } 1584 1585 Static void 1586 ehci_dump_regs(ehci_softc_t *sc) 1587 { 1588 int i; 1589 1590 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1591 1592 USBHIST_LOG(ehcidebug, 1593 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1594 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1595 EOREAD4(sc, EHCI_USBINTR), 0); 1596 USBHIST_LOG(ehcidebug, 1597 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1598 "async = 0x%08x", 1599 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1600 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1601 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1602 for (i = 1; i <= sc->sc_noport; i += 2) { 1603 if (i == sc->sc_noport) { 1604 USBHIST_LOG(ehcidebug, 1605 "port %d status = 0x%08x", i, 1606 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1607 } else { 1608 USBHIST_LOG(ehcidebug, 1609 "port %d status = 0x%08x port %d status = 0x%08x", 1610 i, EOREAD4(sc, EHCI_PORTSC(i)), 1611 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1612 } 1613 } 1614 } 1615 1616 #ifdef EHCI_DEBUG 1617 #define ehci_dump_link(link, type) do { \ 1618 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1619 link, \ 1620 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1621 if (type) { \ 1622 USBHIST_LOG(ehcidebug, \ 1623 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1624 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1625 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1626 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1627 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1628 } \ 1629 } while(0) 1630 #else 1631 #define ehci_dump_link(link, type) 1632 #endif 1633 1634 Static void 1635 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1636 { 1637 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1638 int i; 1639 uint32_t stop = 0; 1640 1641 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1642 ehci_dump_sqtd(sqtd); 1643 usb_syncmem(&sqtd->dma, 1644 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1645 sizeof(sqtd->qtd), 1646 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1647 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1648 usb_syncmem(&sqtd->dma, 1649 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1650 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1651 } 1652 if (sqtd) 1653 USBHIST_LOG(ehcidebug, 1654 "dump aborted, too many TDs", 0, 0, 0, 0); 1655 } 1656 1657 Static void 1658 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1659 { 1660 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1661 1662 usb_syncmem(&sqtd->dma, sqtd->offs, 1663 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1664 1665 USBHIST_LOGN(ehcidebug, 10, 1666 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1667 ehci_dump_qtd(&sqtd->qtd); 1668 1669 usb_syncmem(&sqtd->dma, sqtd->offs, 1670 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1671 } 1672 1673 Static void 1674 ehci_dump_qtd(ehci_qtd_t *qtd) 1675 { 1676 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1677 1678 #ifdef USBHIST 1679 uint32_t s = le32toh(qtd->qtd_status); 1680 #endif 1681 1682 USBHIST_LOGN(ehcidebug, 10, 1683 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1684 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1685 USBHIST_LOGN(ehcidebug, 10, 1686 " toggle = %d ioc = %d bytes = %#x " 1687 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1688 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1689 USBHIST_LOGN(ehcidebug, 10, 1690 " cerr = %d pid = %d stat = %x", 1691 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1692 0); 1693 USBHIST_LOGN(ehcidebug, 10, 1694 "active =%d halted=%d buferr=%d babble=%d", 1695 s & EHCI_QTD_ACTIVE ? 1 : 0, 1696 s & EHCI_QTD_HALTED ? 1 : 0, 1697 s & EHCI_QTD_BUFERR ? 1 : 0, 1698 s & EHCI_QTD_BABBLE ? 1 : 0); 1699 USBHIST_LOGN(ehcidebug, 10, 1700 "xacterr=%d missed=%d split =%d ping =%d", 1701 s & EHCI_QTD_XACTERR ? 1 : 0, 1702 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1703 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1704 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1705 USBHIST_LOGN(ehcidebug, 10, 1706 "buffer[0] = %#x buffer[1] = %#x " 1707 "buffer[2] = %#x buffer[3] = %#x", 1708 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1709 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1710 USBHIST_LOGN(ehcidebug, 10, 1711 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1712 } 1713 1714 Static void 1715 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1716 { 1717 #ifdef USBHIST 1718 ehci_qh_t *qh = &sqh->qh; 1719 ehci_link_t link; 1720 #endif 1721 uint32_t endp, endphub; 1722 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1723 1724 usb_syncmem(&sqh->dma, sqh->offs, 1725 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1726 1727 USBHIST_LOGN(ehcidebug, 10, 1728 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1729 link = le32toh(qh->qh_link); 1730 ehci_dump_link(link, true); 1731 1732 endp = le32toh(qh->qh_endp); 1733 USBHIST_LOGN(ehcidebug, 10, 1734 " endp = %#x", endp, 0, 0, 0); 1735 USBHIST_LOGN(ehcidebug, 10, 1736 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1737 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1738 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1739 USBHIST_LOGN(ehcidebug, 10, 1740 " dtc = %d hrecl = %d", 1741 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1742 USBHIST_LOGN(ehcidebug, 10, 1743 " ctl = %d nrl = %d mpl = %#x(%d)", 1744 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1745 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1746 1747 endphub = le32toh(qh->qh_endphub); 1748 USBHIST_LOGN(ehcidebug, 10, 1749 " endphub = %#x", endphub, 0, 0, 0); 1750 USBHIST_LOGN(ehcidebug, 10, 1751 " smask = 0x%02x cmask = 0x%02x", 1752 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1753 USBHIST_LOGN(ehcidebug, 10, 1754 " huba = 0x%02x port = %d mult = %d", 1755 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1756 EHCI_QH_GET_MULT(endphub), 0); 1757 1758 link = le32toh(qh->qh_curqtd); 1759 ehci_dump_link(link, false); 1760 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1761 ehci_dump_qtd(&qh->qh_qtd); 1762 1763 usb_syncmem(&sqh->dma, sqh->offs, 1764 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1765 } 1766 1767 Static void 1768 ehci_dump_itd(struct ehci_soft_itd *itd) 1769 { 1770 ehci_isoc_trans_t t; 1771 ehci_isoc_bufr_ptr_t b, b2, b3; 1772 int i; 1773 1774 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1775 1776 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1777 0, 0); 1778 1779 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1780 t = le32toh(itd->itd.itd_ctl[i]); 1781 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1782 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1783 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1784 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1785 EHCI_ITD_GET_OFFS(t), 0); 1786 } 1787 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1788 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1789 USBHIST_LOG(ehcidebug, " %x", 1790 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1791 1792 b = le32toh(itd->itd.itd_bufr[0]); 1793 b2 = le32toh(itd->itd.itd_bufr[1]); 1794 b3 = le32toh(itd->itd.itd_bufr[2]); 1795 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1796 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1797 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1798 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1799 } 1800 1801 Static void 1802 ehci_dump_sitd(struct ehci_soft_itd *itd) 1803 { 1804 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1805 1806 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1807 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1808 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1809 itd->xfer_next, itd->physaddr, itd->slot, 0); 1810 } 1811 1812 Static void 1813 ehci_dump_exfer(struct ehci_xfer *ex) 1814 { 1815 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1816 1817 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1818 ex, ex->ex_sqtdstart, ex->ex_sqtdend, 0); 1819 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1820 ex->ex_itdstart, ex->ex_itdend, ex->ex_isdone, 0); 1821 } 1822 #endif 1823 1824 Static usbd_status 1825 ehci_open(usbd_pipe_handle pipe) 1826 { 1827 usbd_device_handle dev = pipe->up_dev; 1828 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1829 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1830 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1831 uint8_t addr = dev->ud_addr; 1832 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1833 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1834 ehci_soft_qh_t *sqh; 1835 usbd_status err; 1836 int ival, speed, naks; 1837 int hshubaddr, hshubport; 1838 1839 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1840 1841 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1842 pipe, addr, ed->bEndpointAddress, rhaddr); 1843 1844 if (dev->ud_myhsport) { 1845 /* 1846 * When directly attached FS/LS device while doing embedded 1847 * transaction translations and we are the hub, set the hub 1848 * address to 0 (us). 1849 */ 1850 if (!(sc->sc_flags & EHCIF_ETTF) 1851 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1852 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1853 } else { 1854 hshubaddr = 0; 1855 } 1856 hshubport = dev->ud_myhsport->up_portno; 1857 } else { 1858 hshubaddr = 0; 1859 hshubport = 0; 1860 } 1861 1862 if (sc->sc_dying) 1863 return USBD_IOERROR; 1864 1865 /* toggle state needed for bulk endpoints */ 1866 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1867 1868 if (addr == rhaddr) { 1869 switch (ed->bEndpointAddress) { 1870 case USB_CONTROL_ENDPOINT: 1871 pipe->up_methods = &roothub_ctrl_methods; 1872 break; 1873 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1874 pipe->up_methods = &ehci_root_intr_methods; 1875 break; 1876 default: 1877 USBHIST_LOG(ehcidebug, 1878 "bad bEndpointAddress 0x%02x", 1879 ed->bEndpointAddress, 0, 0, 0); 1880 return USBD_INVAL; 1881 } 1882 return USBD_NORMAL_COMPLETION; 1883 } 1884 1885 /* XXX All this stuff is only valid for async. */ 1886 switch (dev->ud_speed) { 1887 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1888 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1889 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1890 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1891 } 1892 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1893 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1894 hshubaddr, hshubport, 0, 0); 1895 return USBD_INVAL; 1896 } 1897 1898 /* 1899 * For interrupt transfer, nak throttling must be disabled, but for 1900 * the other transfer type, nak throttling should be enabled from the 1901 * viewpoint that avoids the memory thrashing. 1902 */ 1903 naks = (xfertype == UE_INTERRUPT) ? 0 1904 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1905 1906 /* Allocate sqh for everything, save isoc xfers */ 1907 if (xfertype != UE_ISOCHRONOUS) { 1908 sqh = ehci_alloc_sqh(sc); 1909 if (sqh == NULL) 1910 return USBD_NOMEM; 1911 /* qh_link filled when the QH is added */ 1912 sqh->qh.qh_endp = htole32( 1913 EHCI_QH_SET_ADDR(addr) | 1914 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1915 EHCI_QH_SET_EPS(speed) | 1916 EHCI_QH_DTC | 1917 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1918 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1919 EHCI_QH_CTL : 0) | 1920 EHCI_QH_SET_NRL(naks) 1921 ); 1922 sqh->qh.qh_endphub = htole32( 1923 EHCI_QH_SET_MULT(1) | 1924 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1925 ); 1926 if (speed != EHCI_QH_SPEED_HIGH) 1927 sqh->qh.qh_endphub |= htole32( 1928 EHCI_QH_SET_PORT(hshubport) | 1929 EHCI_QH_SET_HUBA(hshubaddr) | 1930 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1931 ); 1932 sqh->qh.qh_curqtd = EHCI_NULL; 1933 /* Fill the overlay qTD */ 1934 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1935 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1936 sqh->qh.qh_qtd.qtd_status = htole32(0); 1937 1938 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1939 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1940 epipe->sqh = sqh; 1941 } else { 1942 sqh = NULL; 1943 } /*xfertype == UE_ISOC*/ 1944 1945 switch (xfertype) { 1946 case UE_CONTROL: 1947 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1948 0, &epipe->u.ctl.reqdma); 1949 #ifdef EHCI_DEBUG 1950 if (err) 1951 printf("ehci_open: usb_allocmem()=%d\n", err); 1952 #endif 1953 if (err) 1954 goto bad; 1955 pipe->up_methods = &ehci_device_ctrl_methods; 1956 mutex_enter(&sc->sc_lock); 1957 ehci_add_qh(sc, sqh, sc->sc_async_head); 1958 mutex_exit(&sc->sc_lock); 1959 break; 1960 case UE_BULK: 1961 pipe->up_methods = &ehci_device_bulk_methods; 1962 mutex_enter(&sc->sc_lock); 1963 ehci_add_qh(sc, sqh, sc->sc_async_head); 1964 mutex_exit(&sc->sc_lock); 1965 break; 1966 case UE_INTERRUPT: 1967 pipe->up_methods = &ehci_device_intr_methods; 1968 ival = pipe->up_interval; 1969 if (ival == USBD_DEFAULT_INTERVAL) { 1970 if (speed == EHCI_QH_SPEED_HIGH) { 1971 if (ed->bInterval > 16) { 1972 /* 1973 * illegal with high-speed, but there 1974 * were documentation bugs in the spec, 1975 * so be generous 1976 */ 1977 ival = 256; 1978 } else 1979 ival = (1 << (ed->bInterval - 1)) / 8; 1980 } else 1981 ival = ed->bInterval; 1982 } 1983 err = ehci_device_setintr(sc, sqh, ival); 1984 if (err) 1985 goto bad; 1986 break; 1987 case UE_ISOCHRONOUS: 1988 if (speed == EHCI_QH_SPEED_HIGH) 1989 pipe->up_methods = &ehci_device_isoc_methods; 1990 else 1991 pipe->up_methods = &ehci_device_fs_isoc_methods; 1992 if (ed->bInterval == 0 || ed->bInterval > 16) { 1993 printf("ehci: opening pipe with invalid bInterval\n"); 1994 err = USBD_INVAL; 1995 goto bad; 1996 } 1997 if (UGETW(ed->wMaxPacketSize) == 0) { 1998 printf("ehci: zero length endpoint open request\n"); 1999 err = USBD_INVAL; 2000 goto bad; 2001 } 2002 epipe->u.isoc.next_frame = 0; 2003 epipe->u.isoc.cur_xfers = 0; 2004 break; 2005 default: 2006 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2007 err = USBD_INVAL; 2008 goto bad; 2009 } 2010 return USBD_NORMAL_COMPLETION; 2011 2012 bad: 2013 if (sqh != NULL) 2014 ehci_free_sqh(sc, sqh); 2015 return err; 2016 } 2017 2018 /* 2019 * Add an ED to the schedule. Called with USB lock held. 2020 */ 2021 Static void 2022 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2023 { 2024 2025 KASSERT(mutex_owned(&sc->sc_lock)); 2026 2027 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2028 2029 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2030 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2031 2032 sqh->next = head->next; 2033 sqh->qh.qh_link = head->qh.qh_link; 2034 2035 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2036 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2037 2038 head->next = sqh; 2039 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2040 2041 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2042 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2043 2044 #ifdef EHCI_DEBUG 2045 ehci_dump_sqh(sqh); 2046 #endif 2047 } 2048 2049 /* 2050 * Remove an ED from the schedule. Called with USB lock held. 2051 */ 2052 Static void 2053 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2054 { 2055 ehci_soft_qh_t *p; 2056 2057 KASSERT(mutex_owned(&sc->sc_lock)); 2058 2059 /* XXX */ 2060 for (p = head; p != NULL && p->next != sqh; p = p->next) 2061 ; 2062 if (p == NULL) 2063 panic("ehci_rem_qh: ED not found"); 2064 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2065 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2066 p->next = sqh->next; 2067 p->qh.qh_link = sqh->qh.qh_link; 2068 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2069 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2070 2071 ehci_sync_hc(sc); 2072 } 2073 2074 Static void 2075 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2076 { 2077 int i; 2078 uint32_t status; 2079 2080 /* Save toggle bit and ping status. */ 2081 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2082 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2083 status = sqh->qh.qh_qtd.qtd_status & 2084 htole32(EHCI_QTD_TOGGLE_MASK | 2085 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2086 /* Set HALTED to make hw leave it alone. */ 2087 sqh->qh.qh_qtd.qtd_status = 2088 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2089 usb_syncmem(&sqh->dma, 2090 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2091 sizeof(sqh->qh.qh_qtd.qtd_status), 2092 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2093 sqh->qh.qh_curqtd = 0; 2094 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2095 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2096 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2097 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2098 sqh->sqtd = sqtd; 2099 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2100 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2101 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2102 sqh->qh.qh_qtd.qtd_status = status; 2103 usb_syncmem(&sqh->dma, 2104 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2105 sizeof(sqh->qh.qh_qtd.qtd_status), 2106 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2107 } 2108 2109 /* 2110 * Ensure that the HC has released all references to the QH. We do this 2111 * by asking for a Async Advance Doorbell interrupt and then we wait for 2112 * the interrupt. 2113 * To make this easier we first obtain exclusive use of the doorbell. 2114 */ 2115 Static void 2116 ehci_sync_hc(ehci_softc_t *sc) 2117 { 2118 int error __diagused; 2119 2120 KASSERT(mutex_owned(&sc->sc_lock)); 2121 2122 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2123 2124 if (sc->sc_dying) { 2125 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2126 return; 2127 } 2128 /* ask for doorbell */ 2129 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2130 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2131 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2132 2133 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2134 2135 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2136 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2137 #ifdef DIAGNOSTIC 2138 if (error) 2139 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2140 #endif 2141 } 2142 2143 Static void 2144 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2145 { 2146 struct ehci_soft_itd *itd, *prev; 2147 2148 prev = NULL; 2149 2150 if (exfer->ex_itdstart == NULL || exfer->ex_itdend == NULL) 2151 panic("ehci isoc xfer being freed, but with no itd chain\n"); 2152 2153 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2154 prev = itd->u.frame_list.prev; 2155 /* Unlink itd from hardware chain, or frame array */ 2156 if (prev == NULL) { /* We're at the table head */ 2157 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2158 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2159 usb_syncmem(&sc->sc_fldma, 2160 sizeof(ehci_link_t) * itd->slot, 2161 sizeof(ehci_link_t), 2162 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2163 2164 if (itd->u.frame_list.next != NULL) 2165 itd->u.frame_list.next->u.frame_list.prev = NULL; 2166 } else { 2167 /* XXX this part is untested... */ 2168 prev->itd.itd_next = itd->itd.itd_next; 2169 usb_syncmem(&itd->dma, 2170 itd->offs + offsetof(ehci_itd_t, itd_next), 2171 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2172 2173 prev->u.frame_list.next = itd->u.frame_list.next; 2174 if (itd->u.frame_list.next != NULL) 2175 itd->u.frame_list.next->u.frame_list.prev = prev; 2176 } 2177 } 2178 2179 prev = NULL; 2180 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2181 if (prev != NULL) 2182 ehci_free_itd(sc, prev); 2183 prev = itd; 2184 } 2185 if (prev) 2186 ehci_free_itd(sc, prev); 2187 exfer->ex_itdstart = NULL; 2188 exfer->ex_itdend = NULL; 2189 } 2190 2191 Static void 2192 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2193 { 2194 struct ehci_soft_sitd *sitd, *prev; 2195 2196 prev = NULL; 2197 2198 if (exfer->ex_sitdstart == NULL || exfer->ex_sitdend == NULL) 2199 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2200 2201 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2202 prev = sitd->u.frame_list.prev; 2203 /* Unlink sitd from hardware chain, or frame array */ 2204 if (prev == NULL) { /* We're at the table head */ 2205 sc->sc_softsitds[sitd->slot] = sitd->u.frame_list.next; 2206 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2207 usb_syncmem(&sc->sc_fldma, 2208 sizeof(ehci_link_t) * sitd->slot, 2209 sizeof(ehci_link_t), 2210 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2211 2212 if (sitd->u.frame_list.next != NULL) 2213 sitd->u.frame_list.next->u.frame_list.prev = NULL; 2214 } else { 2215 /* XXX this part is untested... */ 2216 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2217 usb_syncmem(&sitd->dma, 2218 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2219 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2220 2221 prev->u.frame_list.next = sitd->u.frame_list.next; 2222 if (sitd->u.frame_list.next != NULL) 2223 sitd->u.frame_list.next->u.frame_list.prev = prev; 2224 } 2225 } 2226 2227 prev = NULL; 2228 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2229 if (prev != NULL) 2230 ehci_free_sitd(sc, prev); 2231 prev = sitd; 2232 } 2233 if (prev) 2234 ehci_free_sitd(sc, prev); 2235 exfer->ex_sitdstart = NULL; 2236 exfer->ex_sitdend = NULL; 2237 } 2238 2239 /***********/ 2240 2241 Static int 2242 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2243 void *buf, int buflen) 2244 { 2245 ehci_softc_t *sc = bus->ub_hcpriv; 2246 usb_hub_descriptor_t hubd; 2247 usb_port_status_t ps; 2248 uint16_t len, value, index; 2249 int l, totlen = 0; 2250 int port, i; 2251 uint32_t v; 2252 2253 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2254 2255 if (sc->sc_dying) 2256 return -1; 2257 2258 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2259 req->bmRequestType, req->bRequest, 0, 0); 2260 2261 len = UGETW(req->wLength); 2262 value = UGETW(req->wValue); 2263 index = UGETW(req->wIndex); 2264 2265 #define C(x,y) ((x) | ((y) << 8)) 2266 switch (C(req->bRequest, req->bmRequestType)) { 2267 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2268 if (len == 0) 2269 break; 2270 switch (value) { 2271 case C(0, UDESC_DEVICE): { 2272 usb_device_descriptor_t devd; 2273 totlen = min(buflen, sizeof(devd)); 2274 memcpy(&devd, buf, totlen); 2275 USETW(devd.idVendor, sc->sc_id_vendor); 2276 memcpy(buf, &devd, totlen); 2277 break; 2278 2279 } 2280 #define sd ((usb_string_descriptor_t *)buf) 2281 case C(1, UDESC_STRING): 2282 /* Vendor */ 2283 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2284 break; 2285 case C(2, UDESC_STRING): 2286 /* Product */ 2287 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2288 break; 2289 #undef sd 2290 default: 2291 /* default from usbroothub */ 2292 return buflen; 2293 } 2294 break; 2295 2296 /* Hub requests */ 2297 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2298 break; 2299 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2300 USBHIST_LOG(ehcidebug, 2301 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2302 0, 0); 2303 if (index < 1 || index > sc->sc_noport) { 2304 return -1; 2305 } 2306 port = EHCI_PORTSC(index); 2307 v = EOREAD4(sc, port); 2308 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2309 v &= ~EHCI_PS_CLEAR; 2310 switch (value) { 2311 case UHF_PORT_ENABLE: 2312 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2313 break; 2314 case UHF_PORT_SUSPEND: 2315 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2316 break; 2317 v &= ~EHCI_PS_SUSP; 2318 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2319 /* see USB2 spec ch. 7.1.7.7 */ 2320 usb_delay_ms(&sc->sc_bus, 20); 2321 EOWRITE4(sc, port, v); 2322 usb_delay_ms(&sc->sc_bus, 2); 2323 #ifdef DEBUG 2324 v = EOREAD4(sc, port); 2325 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2326 printf("ehci: resume failed: %x\n", v); 2327 #endif 2328 break; 2329 case UHF_PORT_POWER: 2330 if (sc->sc_hasppc) 2331 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2332 break; 2333 case UHF_PORT_TEST: 2334 USBHIST_LOG(ehcidebug, "clear port test " 2335 "%d", index, 0, 0, 0); 2336 break; 2337 case UHF_PORT_INDICATOR: 2338 USBHIST_LOG(ehcidebug, "clear port ind " 2339 "%d", index, 0, 0, 0); 2340 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2341 break; 2342 case UHF_C_PORT_CONNECTION: 2343 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2344 break; 2345 case UHF_C_PORT_ENABLE: 2346 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2347 break; 2348 case UHF_C_PORT_SUSPEND: 2349 /* how? */ 2350 break; 2351 case UHF_C_PORT_OVER_CURRENT: 2352 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2353 break; 2354 case UHF_C_PORT_RESET: 2355 sc->sc_isreset[index] = 0; 2356 break; 2357 default: 2358 return -1; 2359 } 2360 #if 0 2361 switch(value) { 2362 case UHF_C_PORT_CONNECTION: 2363 case UHF_C_PORT_ENABLE: 2364 case UHF_C_PORT_SUSPEND: 2365 case UHF_C_PORT_OVER_CURRENT: 2366 case UHF_C_PORT_RESET: 2367 default: 2368 break; 2369 } 2370 #endif 2371 break; 2372 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2373 if (len == 0) 2374 break; 2375 if ((value & 0xff) != 0) { 2376 return -1; 2377 } 2378 totlen = min(buflen, sizeof(hubd)); 2379 memcpy(&hubd, buf, totlen); 2380 hubd.bNbrPorts = sc->sc_noport; 2381 v = EOREAD4(sc, EHCI_HCSPARAMS); 2382 USETW(hubd.wHubCharacteristics, 2383 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2384 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2385 ? UHD_PORT_IND : 0); 2386 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2387 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2388 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2389 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2390 totlen = min(totlen, hubd.bDescLength); 2391 memcpy(buf, &hubd, totlen); 2392 break; 2393 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2394 if (len != 4) { 2395 return -1; 2396 } 2397 memset(buf, 0, len); /* ? XXX */ 2398 totlen = len; 2399 break; 2400 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2401 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2402 if (index < 1 || index > sc->sc_noport) { 2403 return -1; 2404 } 2405 if (len != 4) { 2406 return -1; 2407 } 2408 v = EOREAD4(sc, EHCI_PORTSC(index)); 2409 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2410 2411 i = UPS_HIGH_SPEED; 2412 if (sc->sc_flags & EHCIF_ETTF) { 2413 /* 2414 * If we are doing embedded transaction translation, 2415 * then directly attached LS/FS devices are reset by 2416 * the EHCI controller itself. PSPD is encoded 2417 * the same way as in USBSTATUS. 2418 */ 2419 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2420 } 2421 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2422 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2423 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2424 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2425 if (v & EHCI_PS_PR) i |= UPS_RESET; 2426 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2427 if (sc->sc_vendor_port_status) 2428 i = sc->sc_vendor_port_status(sc, v, i); 2429 USETW(ps.wPortStatus, i); 2430 i = 0; 2431 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2432 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2433 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2434 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2435 USETW(ps.wPortChange, i); 2436 totlen = min(len, sizeof(ps)); 2437 memcpy(buf, &ps, totlen); 2438 break; 2439 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2440 return -1; 2441 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2442 break; 2443 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2444 if (index < 1 || index > sc->sc_noport) { 2445 return -1; 2446 } 2447 port = EHCI_PORTSC(index); 2448 v = EOREAD4(sc, port); 2449 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2450 v &= ~EHCI_PS_CLEAR; 2451 switch(value) { 2452 case UHF_PORT_ENABLE: 2453 EOWRITE4(sc, port, v | EHCI_PS_PE); 2454 break; 2455 case UHF_PORT_SUSPEND: 2456 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2457 break; 2458 case UHF_PORT_RESET: 2459 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2460 if (EHCI_PS_IS_LOWSPEED(v) 2461 && sc->sc_ncomp > 0 2462 && !(sc->sc_flags & EHCIF_ETTF)) { 2463 /* 2464 * Low speed device on non-ETTF controller or 2465 * unaccompanied controller, give up ownership. 2466 */ 2467 ehci_disown(sc, index, 1); 2468 break; 2469 } 2470 /* Start reset sequence. */ 2471 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2472 EOWRITE4(sc, port, v | EHCI_PS_PR); 2473 /* Wait for reset to complete. */ 2474 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2475 if (sc->sc_dying) { 2476 return -1; 2477 } 2478 /* 2479 * An embedded transaction translator will automatically 2480 * terminate the reset sequence so there's no need to 2481 * it. 2482 */ 2483 v = EOREAD4(sc, port); 2484 if (v & EHCI_PS_PR) { 2485 /* Terminate reset sequence. */ 2486 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2487 /* Wait for HC to complete reset. */ 2488 usb_delay_ms(&sc->sc_bus, 2489 EHCI_PORT_RESET_COMPLETE); 2490 if (sc->sc_dying) { 2491 return -1; 2492 } 2493 } 2494 2495 v = EOREAD4(sc, port); 2496 USBHIST_LOG(ehcidebug, 2497 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2498 if (v & EHCI_PS_PR) { 2499 printf("%s: port reset timeout\n", 2500 device_xname(sc->sc_dev)); 2501 return USBD_TIMEOUT; 2502 } 2503 if (!(v & EHCI_PS_PE)) { 2504 /* Not a high speed device, give up ownership.*/ 2505 ehci_disown(sc, index, 0); 2506 break; 2507 } 2508 sc->sc_isreset[index] = 1; 2509 USBHIST_LOG(ehcidebug, 2510 "ehci port %d reset, status = 0x%08x", index, v, 0, 2511 0); 2512 break; 2513 case UHF_PORT_POWER: 2514 USBHIST_LOG(ehcidebug, 2515 "set port power %d (has PPC = %d)", index, 2516 sc->sc_hasppc, 0, 0); 2517 if (sc->sc_hasppc) 2518 EOWRITE4(sc, port, v | EHCI_PS_PP); 2519 break; 2520 case UHF_PORT_TEST: 2521 USBHIST_LOG(ehcidebug, "set port test %d", 2522 index, 0, 0, 0); 2523 break; 2524 case UHF_PORT_INDICATOR: 2525 USBHIST_LOG(ehcidebug, "set port ind %d", 2526 index, 0, 0, 0); 2527 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2528 break; 2529 default: 2530 return -1; 2531 } 2532 break; 2533 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2534 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2535 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2536 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2537 break; 2538 default: 2539 /* default from usbroothub */ 2540 return buflen; 2541 } 2542 2543 return totlen; 2544 } 2545 2546 Static void 2547 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2548 { 2549 int port; 2550 uint32_t v; 2551 2552 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2553 2554 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2555 #ifdef DIAGNOSTIC 2556 if (sc->sc_npcomp != 0) { 2557 int i = (index-1) / sc->sc_npcomp; 2558 if (i >= sc->sc_ncomp) 2559 printf("%s: strange port\n", 2560 device_xname(sc->sc_dev)); 2561 else 2562 printf("%s: handing over %s speed device on " 2563 "port %d to %s\n", 2564 device_xname(sc->sc_dev), 2565 lowspeed ? "low" : "full", 2566 index, device_xname(sc->sc_comps[i])); 2567 } else { 2568 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2569 } 2570 #endif 2571 port = EHCI_PORTSC(index); 2572 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2573 EOWRITE4(sc, port, v | EHCI_PS_PO); 2574 } 2575 2576 Static usbd_status 2577 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2578 { 2579 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2580 usbd_status err; 2581 2582 /* Insert last in queue. */ 2583 mutex_enter(&sc->sc_lock); 2584 err = usb_insert_transfer(xfer); 2585 mutex_exit(&sc->sc_lock); 2586 if (err) 2587 return err; 2588 2589 /* Pipe isn't running, start first */ 2590 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2591 } 2592 2593 Static usbd_status 2594 ehci_root_intr_start(usbd_xfer_handle xfer) 2595 { 2596 usbd_pipe_handle pipe = xfer->ux_pipe; 2597 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2598 2599 if (sc->sc_dying) 2600 return USBD_IOERROR; 2601 2602 mutex_enter(&sc->sc_lock); 2603 sc->sc_intrxfer = xfer; 2604 mutex_exit(&sc->sc_lock); 2605 2606 return USBD_IN_PROGRESS; 2607 } 2608 2609 /* Abort a root interrupt request. */ 2610 Static void 2611 ehci_root_intr_abort(usbd_xfer_handle xfer) 2612 { 2613 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2614 2615 KASSERT(mutex_owned(&sc->sc_lock)); 2616 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2617 2618 sc->sc_intrxfer = NULL; 2619 2620 xfer->ux_status = USBD_CANCELLED; 2621 usb_transfer_complete(xfer); 2622 } 2623 2624 /* Close the root pipe. */ 2625 Static void 2626 ehci_root_intr_close(usbd_pipe_handle pipe) 2627 { 2628 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2629 2630 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2631 2632 KASSERT(mutex_owned(&sc->sc_lock)); 2633 2634 sc->sc_intrxfer = NULL; 2635 } 2636 2637 Static void 2638 ehci_root_intr_done(usbd_xfer_handle xfer) 2639 { 2640 xfer->ux_hcpriv = NULL; 2641 } 2642 2643 /************************/ 2644 2645 Static ehci_soft_qh_t * 2646 ehci_alloc_sqh(ehci_softc_t *sc) 2647 { 2648 ehci_soft_qh_t *sqh; 2649 usbd_status err; 2650 int i, offs; 2651 usb_dma_t dma; 2652 2653 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2654 2655 if (sc->sc_freeqhs == NULL) { 2656 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2657 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2658 EHCI_PAGE_SIZE, &dma); 2659 #ifdef EHCI_DEBUG 2660 if (err) 2661 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2662 #endif 2663 if (err) 2664 return NULL; 2665 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2666 offs = i * EHCI_SQH_SIZE; 2667 sqh = KERNADDR(&dma, offs); 2668 sqh->physaddr = DMAADDR(&dma, offs); 2669 sqh->dma = dma; 2670 sqh->offs = offs; 2671 sqh->next = sc->sc_freeqhs; 2672 sc->sc_freeqhs = sqh; 2673 } 2674 } 2675 sqh = sc->sc_freeqhs; 2676 sc->sc_freeqhs = sqh->next; 2677 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2678 sqh->next = NULL; 2679 return sqh; 2680 } 2681 2682 Static void 2683 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2684 { 2685 sqh->next = sc->sc_freeqhs; 2686 sc->sc_freeqhs = sqh; 2687 } 2688 2689 Static ehci_soft_qtd_t * 2690 ehci_alloc_sqtd(ehci_softc_t *sc) 2691 { 2692 ehci_soft_qtd_t *sqtd = NULL; 2693 usbd_status err; 2694 int i, offs; 2695 usb_dma_t dma; 2696 2697 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2698 2699 if (sc->sc_freeqtds == NULL) { 2700 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2701 2702 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2703 EHCI_PAGE_SIZE, &dma); 2704 #ifdef EHCI_DEBUG 2705 if (err) 2706 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2707 #endif 2708 if (err) 2709 goto done; 2710 2711 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2712 offs = i * EHCI_SQTD_SIZE; 2713 sqtd = KERNADDR(&dma, offs); 2714 sqtd->physaddr = DMAADDR(&dma, offs); 2715 sqtd->dma = dma; 2716 sqtd->offs = offs; 2717 2718 sqtd->nextqtd = sc->sc_freeqtds; 2719 sc->sc_freeqtds = sqtd; 2720 } 2721 } 2722 2723 sqtd = sc->sc_freeqtds; 2724 sc->sc_freeqtds = sqtd->nextqtd; 2725 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2726 sqtd->nextqtd = NULL; 2727 sqtd->xfer = NULL; 2728 2729 done: 2730 return sqtd; 2731 } 2732 2733 Static void 2734 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2735 { 2736 2737 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2738 2739 sqtd->nextqtd = sc->sc_freeqtds; 2740 sc->sc_freeqtds = sqtd; 2741 } 2742 2743 Static usbd_status 2744 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2745 int alen, int rd, usbd_xfer_handle xfer, 2746 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2747 { 2748 ehci_soft_qtd_t *next, *cur; 2749 ehci_physaddr_t nextphys; 2750 uint32_t qtdstatus; 2751 int len, curlen, mps; 2752 int i, tog; 2753 int pages, pageoffs; 2754 bus_size_t curoffs; 2755 vaddr_t va, va_offs; 2756 usb_dma_t *dma = &xfer->ux_dmabuf; 2757 uint16_t flags = xfer->ux_flags; 2758 paddr_t a; 2759 2760 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2761 2762 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2763 2764 len = alen; 2765 qtdstatus = EHCI_QTD_ACTIVE | 2766 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2767 EHCI_QTD_SET_CERR(3) 2768 /* IOC set below */ 2769 /* BYTES set below */ 2770 ; 2771 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 2772 tog = epipe->nexttoggle; 2773 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2774 2775 cur = ehci_alloc_sqtd(sc); 2776 *sp = cur; 2777 if (cur == NULL) 2778 goto nomem; 2779 2780 usb_syncmem(dma, 0, alen, 2781 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2782 curoffs = 0; 2783 for (;;) { 2784 /* The EHCI hardware can handle at most 5 pages. */ 2785 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2786 va_offs = EHCI_PAGE_OFFSET(va_offs); 2787 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 2788 /* we can handle it in this QTD */ 2789 curlen = len - curoffs; 2790 } else { 2791 /* must use multiple TDs, fill as much as possible. */ 2792 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 2793 2794 /* the length must be a multiple of the max size */ 2795 curlen -= curlen % mps; 2796 USBHIST_LOG(ehcidebug, "multiple QTDs, " 2797 "curlen=%d", curlen, 0, 0, 0); 2798 KASSERT(curlen != 0); 2799 } 2800 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 2801 len, curlen, (size_t)curoffs, 0); 2802 2803 /* 2804 * Allocate another transfer if there's more data left, 2805 * or if force last short transfer flag is set and we're 2806 * allocating a multiple of the max packet size. 2807 */ 2808 2809 if (curoffs + curlen != len || 2810 ((curlen % mps) == 0 && !rd && curlen != 0 && 2811 (flags & USBD_FORCE_SHORT_XFER))) { 2812 next = ehci_alloc_sqtd(sc); 2813 if (next == NULL) 2814 goto nomem; 2815 nextphys = htole32(next->physaddr); 2816 } else { 2817 next = NULL; 2818 nextphys = EHCI_NULL; 2819 } 2820 2821 /* Find number of pages we'll be using, insert dma addresses */ 2822 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2823 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2824 pageoffs = EHCI_PAGE(curoffs); 2825 for (i = 0; i < pages; i++) { 2826 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2827 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2828 /* Cast up to avoid compiler warnings */ 2829 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2830 } 2831 2832 /* First buffer pointer requires a page offset to start at */ 2833 va = (vaddr_t)KERNADDR(dma, curoffs); 2834 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2835 2836 cur->nextqtd = next; 2837 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2838 cur->qtd.qtd_status = 2839 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2840 cur->xfer = xfer; 2841 cur->len = curlen; 2842 2843 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2844 (size_t)curoffs, (size_t)(curoffs + curlen), 0, 0); 2845 2846 /* 2847 * adjust the toggle based on the number of packets in this 2848 * qtd 2849 */ 2850 if (((curlen + mps - 1) / mps) & 1) { 2851 tog ^= 1; 2852 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2853 } 2854 if (next == NULL) 2855 break; 2856 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2857 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2858 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2859 if (len) 2860 curoffs += curlen; 2861 cur = next; 2862 } 2863 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2864 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2865 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2866 *ep = cur; 2867 epipe->nexttoggle = tog; 2868 2869 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 2870 *sp, *ep, 0, 0); 2871 2872 return USBD_NORMAL_COMPLETION; 2873 2874 nomem: 2875 /* XXX free chain */ 2876 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2877 return USBD_NOMEM; 2878 } 2879 2880 Static void 2881 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2882 ehci_soft_qtd_t *sqtdend) 2883 { 2884 ehci_soft_qtd_t *p; 2885 int i; 2886 2887 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2888 2889 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 2890 sqtd, sqtdend, 0, 0); 2891 2892 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2893 p = sqtd->nextqtd; 2894 ehci_free_sqtd(sc, sqtd); 2895 } 2896 } 2897 2898 Static ehci_soft_itd_t * 2899 ehci_alloc_itd(ehci_softc_t *sc) 2900 { 2901 struct ehci_soft_itd *itd, *freeitd; 2902 usbd_status err; 2903 int i, offs, frindex, previndex; 2904 usb_dma_t dma; 2905 2906 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2907 2908 mutex_enter(&sc->sc_lock); 2909 2910 /* Find an itd that wasn't freed this frame or last frame. This can 2911 * discard itds that were freed before frindex wrapped around 2912 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2913 * interrupt and fiddling with list when that happens */ 2914 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2915 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2916 2917 freeitd = NULL; 2918 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2919 if (itd == NULL) 2920 break; 2921 if (itd->slot != frindex && itd->slot != previndex) { 2922 freeitd = itd; 2923 break; 2924 } 2925 } 2926 2927 if (freeitd == NULL) { 2928 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2929 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2930 EHCI_PAGE_SIZE, &dma); 2931 2932 if (err) { 2933 USBHIST_LOG(ehcidebug, 2934 "alloc returned %d", err, 0, 0, 0); 2935 mutex_exit(&sc->sc_lock); 2936 return NULL; 2937 } 2938 2939 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2940 offs = i * EHCI_ITD_SIZE; 2941 itd = KERNADDR(&dma, offs); 2942 itd->physaddr = DMAADDR(&dma, offs); 2943 itd->dma = dma; 2944 itd->offs = offs; 2945 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2946 } 2947 freeitd = LIST_FIRST(&sc->sc_freeitds); 2948 } 2949 2950 itd = freeitd; 2951 LIST_REMOVE(itd, u.free_list); 2952 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2953 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2954 sizeof(itd->itd.itd_next), 2955 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2956 2957 itd->u.frame_list.next = NULL; 2958 itd->u.frame_list.prev = NULL; 2959 itd->xfer_next = NULL; 2960 itd->slot = 0; 2961 2962 mutex_exit(&sc->sc_lock); 2963 2964 return itd; 2965 } 2966 2967 Static ehci_soft_sitd_t * 2968 ehci_alloc_sitd(ehci_softc_t *sc) 2969 { 2970 struct ehci_soft_sitd *sitd, *freesitd; 2971 usbd_status err; 2972 int i, offs, frindex, previndex; 2973 usb_dma_t dma; 2974 2975 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2976 2977 mutex_enter(&sc->sc_lock); 2978 2979 /* Find an sitd that wasn't freed this frame or last frame. This can 2980 * discard sitds that were freed before frindex wrapped around 2981 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2982 * interrupt and fiddling with list when that happens */ 2983 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2984 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2985 2986 freesitd = NULL; 2987 LIST_FOREACH(sitd, &sc->sc_freesitds, u.free_list) { 2988 if (sitd == NULL) 2989 break; 2990 if (sitd->slot != frindex && sitd->slot != previndex) { 2991 freesitd = sitd; 2992 break; 2993 } 2994 } 2995 2996 if (freesitd == NULL) { 2997 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2998 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 2999 EHCI_PAGE_SIZE, &dma); 3000 3001 if (err) { 3002 USBHIST_LOG(ehcidebug, 3003 "alloc returned %d", err, 0, 0, 0); 3004 mutex_exit(&sc->sc_lock); 3005 return NULL; 3006 } 3007 3008 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3009 offs = i * EHCI_SITD_SIZE; 3010 sitd = KERNADDR(&dma, offs); 3011 sitd->physaddr = DMAADDR(&dma, offs); 3012 sitd->dma = dma; 3013 sitd->offs = offs; 3014 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3015 } 3016 freesitd = LIST_FIRST(&sc->sc_freesitds); 3017 } 3018 3019 sitd = freesitd; 3020 LIST_REMOVE(sitd, u.free_list); 3021 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3022 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3023 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3024 BUS_DMASYNC_PREREAD); 3025 3026 sitd->u.frame_list.next = NULL; 3027 sitd->u.frame_list.prev = NULL; 3028 sitd->xfer_next = NULL; 3029 sitd->slot = 0; 3030 3031 mutex_exit(&sc->sc_lock); 3032 3033 return sitd; 3034 } 3035 3036 Static void 3037 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3038 { 3039 3040 KASSERT(mutex_owned(&sc->sc_lock)); 3041 3042 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3043 } 3044 3045 Static void 3046 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3047 { 3048 3049 KASSERT(mutex_owned(&sc->sc_lock)); 3050 3051 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3052 } 3053 3054 /****************/ 3055 3056 /* 3057 * Close a reqular pipe. 3058 * Assumes that there are no pending transactions. 3059 */ 3060 Static void 3061 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3062 { 3063 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3064 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3065 ehci_soft_qh_t *sqh = epipe->sqh; 3066 3067 KASSERT(mutex_owned(&sc->sc_lock)); 3068 3069 ehci_rem_qh(sc, sqh, head); 3070 ehci_free_sqh(sc, epipe->sqh); 3071 } 3072 3073 /* 3074 * Abort a device request. 3075 * If this routine is called at splusb() it guarantees that the request 3076 * will be removed from the hardware scheduling and that the callback 3077 * for it will be called with USBD_CANCELLED status. 3078 * It's impossible to guarantee that the requested transfer will not 3079 * have happened since the hardware runs concurrently. 3080 * If the transaction has already happened we rely on the ordinary 3081 * interrupt processing to process it. 3082 * XXX This is most probably wrong. 3083 * XXXMRG this doesn't make sense anymore. 3084 */ 3085 Static void 3086 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3087 { 3088 #define exfer EXFER(xfer) 3089 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3090 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3091 ehci_soft_qh_t *sqh = epipe->sqh; 3092 ehci_soft_qtd_t *sqtd; 3093 ehci_physaddr_t cur; 3094 uint32_t qhstatus; 3095 int hit; 3096 int wake; 3097 3098 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3099 3100 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3101 3102 KASSERT(mutex_owned(&sc->sc_lock)); 3103 ASSERT_SLEEPABLE(); 3104 3105 if (sc->sc_dying) { 3106 /* If we're dying, just do the software part. */ 3107 xfer->ux_status = status; /* make software ignore it */ 3108 callout_stop(&xfer->ux_callout); 3109 usb_transfer_complete(xfer); 3110 return; 3111 } 3112 3113 /* 3114 * If an abort is already in progress then just wait for it to 3115 * complete and return. 3116 */ 3117 if (xfer->ux_hcflags & UXFER_ABORTING) { 3118 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3119 #ifdef DIAGNOSTIC 3120 if (status == USBD_TIMEOUT) 3121 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3122 #endif 3123 /* Override the status which might be USBD_TIMEOUT. */ 3124 xfer->ux_status = status; 3125 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3126 0, 0, 0, 0); 3127 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3128 while (xfer->ux_hcflags & UXFER_ABORTING) 3129 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3130 return; 3131 } 3132 xfer->ux_hcflags |= UXFER_ABORTING; 3133 3134 /* 3135 * Step 1: Make interrupt routine and hardware ignore xfer. 3136 */ 3137 xfer->ux_status = status; /* make software ignore it */ 3138 callout_stop(&xfer->ux_callout); 3139 3140 usb_syncmem(&sqh->dma, 3141 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3142 sizeof(sqh->qh.qh_qtd.qtd_status), 3143 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3144 qhstatus = sqh->qh.qh_qtd.qtd_status; 3145 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3146 usb_syncmem(&sqh->dma, 3147 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3148 sizeof(sqh->qh.qh_qtd.qtd_status), 3149 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3150 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3151 usb_syncmem(&sqtd->dma, 3152 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3153 sizeof(sqtd->qtd.qtd_status), 3154 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3155 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3156 usb_syncmem(&sqtd->dma, 3157 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3158 sizeof(sqtd->qtd.qtd_status), 3159 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3160 if (sqtd == exfer->ex_sqtdend) 3161 break; 3162 } 3163 3164 /* 3165 * Step 2: Wait until we know hardware has finished any possible 3166 * use of the xfer. Also make sure the soft interrupt routine 3167 * has run. 3168 */ 3169 ehci_sync_hc(sc); 3170 sc->sc_softwake = 1; 3171 usb_schedsoftintr(&sc->sc_bus); 3172 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3173 3174 /* 3175 * Step 3: Remove any vestiges of the xfer from the hardware. 3176 * The complication here is that the hardware may have executed 3177 * beyond the xfer we're trying to abort. So as we're scanning 3178 * the TDs of this xfer we check if the hardware points to 3179 * any of them. 3180 */ 3181 3182 usb_syncmem(&sqh->dma, 3183 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3184 sizeof(sqh->qh.qh_curqtd), 3185 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3186 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3187 hit = 0; 3188 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3189 hit |= cur == sqtd->physaddr; 3190 if (sqtd == exfer->ex_sqtdend) 3191 break; 3192 } 3193 sqtd = sqtd->nextqtd; 3194 /* Zap curqtd register if hardware pointed inside the xfer. */ 3195 if (hit && sqtd != NULL) { 3196 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3197 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3198 usb_syncmem(&sqh->dma, 3199 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3200 sizeof(sqh->qh.qh_curqtd), 3201 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3202 sqh->qh.qh_qtd.qtd_status = qhstatus; 3203 usb_syncmem(&sqh->dma, 3204 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3205 sizeof(sqh->qh.qh_qtd.qtd_status), 3206 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3207 } else { 3208 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3209 } 3210 3211 /* 3212 * Step 4: Execute callback. 3213 */ 3214 #ifdef DIAGNOSTIC 3215 exfer->ex_isdone = 1; 3216 #endif 3217 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3218 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3219 usb_transfer_complete(xfer); 3220 if (wake) { 3221 cv_broadcast(&xfer->ux_hccv); 3222 } 3223 3224 KASSERT(mutex_owned(&sc->sc_lock)); 3225 #undef exfer 3226 } 3227 3228 Static void 3229 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3230 { 3231 ehci_isoc_trans_t trans_status; 3232 struct ehci_pipe *epipe; 3233 struct ehci_xfer *exfer; 3234 ehci_softc_t *sc; 3235 struct ehci_soft_itd *itd; 3236 struct ehci_soft_sitd *sitd; 3237 int i, wake; 3238 3239 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3240 3241 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3242 exfer = EXFER(xfer); 3243 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3244 3245 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3246 3247 KASSERT(mutex_owned(&sc->sc_lock)); 3248 3249 if (sc->sc_dying) { 3250 xfer->ux_status = status; 3251 callout_stop(&xfer->ux_callout); 3252 usb_transfer_complete(xfer); 3253 return; 3254 } 3255 3256 if (xfer->ux_hcflags & UXFER_ABORTING) { 3257 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3258 3259 #ifdef DIAGNOSTIC 3260 if (status == USBD_TIMEOUT) 3261 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3262 #endif 3263 3264 xfer->ux_status = status; 3265 USBHIST_LOG(ehcidebug, 3266 "waiting for abort to finish", 0, 0, 0, 0); 3267 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3268 while (xfer->ux_hcflags & UXFER_ABORTING) 3269 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3270 goto done; 3271 } 3272 xfer->ux_hcflags |= UXFER_ABORTING; 3273 3274 xfer->ux_status = status; 3275 callout_stop(&xfer->ux_callout); 3276 3277 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3278 for (itd = exfer->ex_itdstart; itd != NULL; 3279 itd = itd->xfer_next) { 3280 usb_syncmem(&itd->dma, 3281 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3282 sizeof(itd->itd.itd_ctl), 3283 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3284 3285 for (i = 0; i < 8; i++) { 3286 trans_status = le32toh(itd->itd.itd_ctl[i]); 3287 trans_status &= ~EHCI_ITD_ACTIVE; 3288 itd->itd.itd_ctl[i] = htole32(trans_status); 3289 } 3290 3291 usb_syncmem(&itd->dma, 3292 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3293 sizeof(itd->itd.itd_ctl), 3294 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3295 } 3296 } else { 3297 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3298 sitd = sitd->xfer_next) { 3299 usb_syncmem(&sitd->dma, 3300 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3301 sizeof(sitd->sitd.sitd_buffer), 3302 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3303 3304 trans_status = le32toh(sitd->sitd.sitd_trans); 3305 trans_status &= ~EHCI_SITD_ACTIVE; 3306 sitd->sitd.sitd_trans = htole32(trans_status); 3307 3308 usb_syncmem(&sitd->dma, 3309 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3310 sizeof(sitd->sitd.sitd_buffer), 3311 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3312 } 3313 } 3314 3315 sc->sc_softwake = 1; 3316 usb_schedsoftintr(&sc->sc_bus); 3317 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3318 3319 #ifdef DIAGNOSTIC 3320 exfer->ex_isdone = 1; 3321 #endif 3322 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3323 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3324 usb_transfer_complete(xfer); 3325 if (wake) { 3326 cv_broadcast(&xfer->ux_hccv); 3327 } 3328 3329 done: 3330 KASSERT(mutex_owned(&sc->sc_lock)); 3331 return; 3332 } 3333 3334 Static void 3335 ehci_timeout(void *addr) 3336 { 3337 struct ehci_xfer *exfer = addr; 3338 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->ex_xfer.ux_pipe; 3339 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3340 3341 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3342 3343 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3344 #ifdef EHCI_DEBUG 3345 if (ehcidebug > 1) 3346 usbd_dump_pipe(exfer->ex_xfer.ux_pipe); 3347 #endif 3348 3349 if (sc->sc_dying) { 3350 mutex_enter(&sc->sc_lock); 3351 ehci_abort_xfer(&exfer->ex_xfer, USBD_TIMEOUT); 3352 mutex_exit(&sc->sc_lock); 3353 return; 3354 } 3355 3356 /* Execute the abort in a process context. */ 3357 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, addr, 3358 USB_TASKQ_MPSAFE); 3359 usb_add_task(exfer->ex_xfer.ux_pipe->up_dev, &exfer->ex_aborttask, 3360 USB_TASKQ_HC); 3361 } 3362 3363 Static void 3364 ehci_timeout_task(void *addr) 3365 { 3366 usbd_xfer_handle xfer = addr; 3367 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3368 3369 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3370 3371 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3372 3373 mutex_enter(&sc->sc_lock); 3374 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3375 mutex_exit(&sc->sc_lock); 3376 } 3377 3378 /************************/ 3379 3380 Static usbd_status 3381 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3382 { 3383 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3384 usbd_status err; 3385 3386 /* Insert last in queue. */ 3387 mutex_enter(&sc->sc_lock); 3388 err = usb_insert_transfer(xfer); 3389 mutex_exit(&sc->sc_lock); 3390 if (err) 3391 return err; 3392 3393 /* Pipe isn't running, start first */ 3394 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3395 } 3396 3397 Static usbd_status 3398 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3399 { 3400 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3401 usbd_status err; 3402 3403 if (sc->sc_dying) 3404 return USBD_IOERROR; 3405 3406 #ifdef DIAGNOSTIC 3407 if (!(xfer->ux_rqflags & URQ_REQUEST)) { 3408 /* XXX panic */ 3409 printf("ehci_device_ctrl_transfer: not a request\n"); 3410 return USBD_INVAL; 3411 } 3412 #endif 3413 3414 err = ehci_device_request(xfer); 3415 if (err) { 3416 return err; 3417 } 3418 3419 if (sc->sc_bus.ub_usepolling) 3420 ehci_waitintr(sc, xfer); 3421 3422 return USBD_IN_PROGRESS; 3423 } 3424 3425 Static void 3426 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3427 { 3428 struct ehci_xfer *ex = EXFER(xfer); 3429 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3430 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3431 usb_device_request_t *req = &xfer->ux_request; 3432 int len = UGETW(req->wLength); 3433 int rd = req->bmRequestType & UT_READ; 3434 3435 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3436 3437 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3438 3439 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3440 3441 #ifdef DIAGNOSTIC 3442 if (!(xfer->ux_rqflags & URQ_REQUEST)) { 3443 panic("ehci_ctrl_done: not a request"); 3444 } 3445 #endif 3446 3447 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3448 ehci_del_intr_list(sc, ex); /* remove from active list */ 3449 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3450 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3451 BUS_DMASYNC_POSTWRITE); 3452 if (len) 3453 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3454 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3455 } 3456 3457 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3458 } 3459 3460 /* Abort a device control request. */ 3461 Static void 3462 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3463 { 3464 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3465 3466 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3467 ehci_abort_xfer(xfer, USBD_CANCELLED); 3468 } 3469 3470 /* Close a device control pipe. */ 3471 Static void 3472 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3473 { 3474 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3475 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3476 3477 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3478 3479 KASSERT(mutex_owned(&sc->sc_lock)); 3480 3481 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3482 3483 ehci_close_pipe(pipe, sc->sc_async_head); 3484 } 3485 3486 Static usbd_status 3487 ehci_device_request(usbd_xfer_handle xfer) 3488 { 3489 #define exfer EXFER(xfer) 3490 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3491 usb_device_request_t *req = &xfer->ux_request; 3492 usbd_device_handle dev = epipe->pipe.up_dev; 3493 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3494 ehci_soft_qtd_t *setup, *stat, *next; 3495 ehci_soft_qh_t *sqh; 3496 int isread; 3497 int len; 3498 usbd_status err; 3499 3500 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3501 3502 isread = req->bmRequestType & UT_READ; 3503 len = UGETW(req->wLength); 3504 3505 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3506 "wValue=0x%04x, wIndex=0x%04x", 3507 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3508 UGETW(req->wIndex)); 3509 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3510 len, dev->ud_addr, 3511 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3512 3513 setup = ehci_alloc_sqtd(sc); 3514 if (setup == NULL) { 3515 err = USBD_NOMEM; 3516 goto bad1; 3517 } 3518 stat = ehci_alloc_sqtd(sc); 3519 if (stat == NULL) { 3520 err = USBD_NOMEM; 3521 goto bad2; 3522 } 3523 3524 mutex_enter(&sc->sc_lock); 3525 3526 sqh = epipe->sqh; 3527 3528 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3529 "address QH %d pipe %d\n", 3530 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3531 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3532 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3533 "MPS QH %d pipe %d\n", 3534 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3535 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3536 3537 /* Set up data transaction */ 3538 if (len != 0) { 3539 ehci_soft_qtd_t *end; 3540 3541 /* Start toggle at 1. */ 3542 epipe->nexttoggle = 1; 3543 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3544 &next, &end); 3545 if (err) 3546 goto bad3; 3547 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3548 end->nextqtd = stat; 3549 end->qtd.qtd_next = end->qtd.qtd_altnext = 3550 htole32(stat->physaddr); 3551 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3552 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3553 } else { 3554 next = stat; 3555 } 3556 3557 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3558 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3559 3560 /* Clear toggle */ 3561 setup->qtd.qtd_status = htole32( 3562 EHCI_QTD_ACTIVE | 3563 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3564 EHCI_QTD_SET_CERR(3) | 3565 EHCI_QTD_SET_TOGGLE(0) | 3566 EHCI_QTD_SET_BYTES(sizeof *req) 3567 ); 3568 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3569 setup->qtd.qtd_buffer_hi[0] = 0; 3570 setup->nextqtd = next; 3571 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3572 setup->xfer = xfer; 3573 setup->len = sizeof *req; 3574 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3575 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3576 3577 stat->qtd.qtd_status = htole32( 3578 EHCI_QTD_ACTIVE | 3579 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3580 EHCI_QTD_SET_CERR(3) | 3581 EHCI_QTD_SET_TOGGLE(1) | 3582 EHCI_QTD_IOC 3583 ); 3584 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3585 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3586 stat->nextqtd = NULL; 3587 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3588 stat->xfer = xfer; 3589 stat->len = 0; 3590 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3591 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3592 3593 #ifdef EHCI_DEBUG 3594 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3595 ehci_dump_sqh(sqh); 3596 ehci_dump_sqtds(setup); 3597 #endif 3598 3599 exfer->ex_sqtdstart = setup; 3600 exfer->ex_sqtdend = stat; 3601 #ifdef DIAGNOSTIC 3602 if (!exfer->ex_isdone) { 3603 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3604 } 3605 exfer->ex_isdone = 0; 3606 #endif 3607 3608 /* Insert qTD in QH list. */ 3609 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3610 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3611 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3612 ehci_timeout, xfer); 3613 } 3614 ehci_add_intr_list(sc, exfer); 3615 xfer->ux_status = USBD_IN_PROGRESS; 3616 mutex_exit(&sc->sc_lock); 3617 3618 #ifdef EHCI_DEBUG 3619 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3620 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3621 // delay(10000); 3622 ehci_dump_regs(sc); 3623 ehci_dump_sqh(sc->sc_async_head); 3624 ehci_dump_sqh(sqh); 3625 ehci_dump_sqtds(setup); 3626 #endif 3627 3628 return USBD_NORMAL_COMPLETION; 3629 3630 bad3: 3631 mutex_exit(&sc->sc_lock); 3632 ehci_free_sqtd(sc, stat); 3633 bad2: 3634 ehci_free_sqtd(sc, setup); 3635 bad1: 3636 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3637 mutex_enter(&sc->sc_lock); 3638 xfer->ux_status = err; 3639 usb_transfer_complete(xfer); 3640 mutex_exit(&sc->sc_lock); 3641 return err; 3642 #undef exfer 3643 } 3644 3645 /* 3646 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3647 * qTD status, or miss signalling occasionally under heavy load. If the host 3648 * machine is too fast, we we can miss transaction completion - when we scan 3649 * the active list the transaction still seems to be active. This generally 3650 * exhibits itself as a umass stall that never recovers. 3651 * 3652 * We work around this behaviour by setting up this callback after any softintr 3653 * that completes with transactions still pending, giving us another chance to 3654 * check for completion after the writeback has taken place. 3655 */ 3656 Static void 3657 ehci_intrlist_timeout(void *arg) 3658 { 3659 ehci_softc_t *sc = arg; 3660 3661 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3662 3663 usb_schedsoftintr(&sc->sc_bus); 3664 } 3665 3666 /************************/ 3667 3668 Static usbd_status 3669 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3670 { 3671 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3672 usbd_status err; 3673 3674 /* Insert last in queue. */ 3675 mutex_enter(&sc->sc_lock); 3676 err = usb_insert_transfer(xfer); 3677 mutex_exit(&sc->sc_lock); 3678 if (err) 3679 return err; 3680 3681 /* Pipe isn't running, start first */ 3682 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3683 } 3684 3685 Static usbd_status 3686 ehci_device_bulk_start(usbd_xfer_handle xfer) 3687 { 3688 #define exfer EXFER(xfer) 3689 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3690 usbd_device_handle dev = epipe->pipe.up_dev; 3691 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3692 ehci_soft_qtd_t *data, *dataend; 3693 ehci_soft_qh_t *sqh; 3694 usbd_status err; 3695 int len, isread, endpt; 3696 3697 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3698 3699 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3700 xfer, xfer->ux_length, xfer->ux_flags, 0); 3701 3702 if (sc->sc_dying) 3703 return USBD_IOERROR; 3704 3705 #ifdef DIAGNOSTIC 3706 if (xfer->ux_rqflags & URQ_REQUEST) 3707 panic("ehci_device_bulk_start: a request"); 3708 #endif 3709 3710 mutex_enter(&sc->sc_lock); 3711 3712 len = xfer->ux_length; 3713 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3714 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3715 sqh = epipe->sqh; 3716 3717 epipe->u.bulk.length = len; 3718 3719 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3720 &dataend); 3721 if (err) { 3722 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3723 xfer->ux_status = err; 3724 usb_transfer_complete(xfer); 3725 mutex_exit(&sc->sc_lock); 3726 return err; 3727 } 3728 3729 #ifdef EHCI_DEBUG 3730 USBHIST_LOGN(ehcidebug, 5, "data(1):", 0, 0, 0, 0); 3731 ehci_dump_sqh(sqh); 3732 ehci_dump_sqtds(data); 3733 #endif 3734 3735 /* Set up interrupt info. */ 3736 exfer->ex_sqtdstart = data; 3737 exfer->ex_sqtdend = dataend; 3738 #ifdef DIAGNOSTIC 3739 if (!exfer->ex_isdone) { 3740 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3741 } 3742 exfer->ex_isdone = 0; 3743 #endif 3744 3745 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3746 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3747 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3748 ehci_timeout, xfer); 3749 } 3750 ehci_add_intr_list(sc, exfer); 3751 xfer->ux_status = USBD_IN_PROGRESS; 3752 mutex_exit(&sc->sc_lock); 3753 3754 #ifdef EHCI_DEBUG 3755 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3756 // delay(10000); 3757 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3758 ehci_dump_regs(sc); 3759 #if 0 3760 printf("async_head:\n"); 3761 ehci_dump_sqh(sc->sc_async_head); 3762 #endif 3763 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3764 ehci_dump_sqh(sqh); 3765 ehci_dump_sqtds(data); 3766 #endif 3767 3768 if (sc->sc_bus.ub_usepolling) 3769 ehci_waitintr(sc, xfer); 3770 3771 return USBD_IN_PROGRESS; 3772 #undef exfer 3773 } 3774 3775 Static void 3776 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3777 { 3778 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3779 3780 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3781 ehci_abort_xfer(xfer, USBD_CANCELLED); 3782 } 3783 3784 /* 3785 * Close a device bulk pipe. 3786 */ 3787 Static void 3788 ehci_device_bulk_close(usbd_pipe_handle pipe) 3789 { 3790 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3791 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3792 3793 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3794 3795 KASSERT(mutex_owned(&sc->sc_lock)); 3796 3797 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3798 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3799 ehci_close_pipe(pipe, sc->sc_async_head); 3800 } 3801 3802 Static void 3803 ehci_device_bulk_done(usbd_xfer_handle xfer) 3804 { 3805 struct ehci_xfer *ex = EXFER(xfer); 3806 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3807 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3808 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3809 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3810 3811 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3812 3813 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3814 xfer, xfer->ux_actlen, 0, 0); 3815 3816 KASSERT(mutex_owned(&sc->sc_lock)); 3817 3818 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3819 ehci_del_intr_list(sc, ex); /* remove from active list */ 3820 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3821 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3822 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3823 } 3824 3825 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3826 } 3827 3828 /************************/ 3829 3830 Static usbd_status 3831 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3832 { 3833 struct ehci_soft_islot *isp; 3834 int islot, lev; 3835 3836 /* Find a poll rate that is large enough. */ 3837 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3838 if (EHCI_ILEV_IVAL(lev) <= ival) 3839 break; 3840 3841 /* Pick an interrupt slot at the right level. */ 3842 /* XXX could do better than picking at random */ 3843 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3844 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3845 3846 sqh->islot = islot; 3847 isp = &sc->sc_islots[islot]; 3848 mutex_enter(&sc->sc_lock); 3849 ehci_add_qh(sc, sqh, isp->sqh); 3850 mutex_exit(&sc->sc_lock); 3851 3852 return USBD_NORMAL_COMPLETION; 3853 } 3854 3855 Static usbd_status 3856 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3857 { 3858 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3859 usbd_status err; 3860 3861 /* Insert last in queue. */ 3862 mutex_enter(&sc->sc_lock); 3863 err = usb_insert_transfer(xfer); 3864 mutex_exit(&sc->sc_lock); 3865 if (err) 3866 return err; 3867 3868 /* 3869 * Pipe isn't running (otherwise err would be USBD_INPROG), 3870 * so start it first. 3871 */ 3872 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3873 } 3874 3875 Static usbd_status 3876 ehci_device_intr_start(usbd_xfer_handle xfer) 3877 { 3878 #define exfer EXFER(xfer) 3879 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3880 usbd_device_handle dev = xfer->ux_pipe->up_dev; 3881 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3882 ehci_soft_qtd_t *data, *dataend; 3883 ehci_soft_qh_t *sqh; 3884 usbd_status err; 3885 int len, isread, endpt; 3886 3887 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3888 3889 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3890 xfer, xfer->ux_length, xfer->ux_flags, 0); 3891 3892 if (sc->sc_dying) 3893 return USBD_IOERROR; 3894 3895 #ifdef DIAGNOSTIC 3896 if (xfer->ux_rqflags & URQ_REQUEST) 3897 panic("ehci_device_intr_start: a request"); 3898 #endif 3899 3900 mutex_enter(&sc->sc_lock); 3901 3902 len = xfer->ux_length; 3903 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3904 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3905 sqh = epipe->sqh; 3906 3907 epipe->u.intr.length = len; 3908 3909 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3910 &dataend); 3911 if (err) { 3912 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3913 xfer->ux_status = err; 3914 usb_transfer_complete(xfer); 3915 mutex_exit(&sc->sc_lock); 3916 return err; 3917 } 3918 3919 #ifdef EHCI_DEBUG 3920 USBHIST_LOGN(ehcidebug, 5, "data(1)", 0, 0, 0, 0); 3921 ehci_dump_sqh(sqh); 3922 ehci_dump_sqtds(data); 3923 #endif 3924 3925 /* Set up interrupt info. */ 3926 exfer->ex_sqtdstart = data; 3927 exfer->ex_sqtdend = dataend; 3928 #ifdef DIAGNOSTIC 3929 if (!exfer->ex_isdone) { 3930 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3931 } 3932 exfer->ex_isdone = 0; 3933 #endif 3934 3935 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3936 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3937 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3938 ehci_timeout, xfer); 3939 } 3940 ehci_add_intr_list(sc, exfer); 3941 xfer->ux_status = USBD_IN_PROGRESS; 3942 mutex_exit(&sc->sc_lock); 3943 3944 #ifdef EHCI_DEBUG 3945 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3946 // delay(10000); 3947 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3948 ehci_dump_regs(sc); 3949 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3950 ehci_dump_sqh(sqh); 3951 ehci_dump_sqtds(data); 3952 #endif 3953 3954 if (sc->sc_bus.ub_usepolling) 3955 ehci_waitintr(sc, xfer); 3956 3957 return USBD_IN_PROGRESS; 3958 #undef exfer 3959 } 3960 3961 Static void 3962 ehci_device_intr_abort(usbd_xfer_handle xfer) 3963 { 3964 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3965 3966 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3967 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3968 3969 /* 3970 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3971 * async doorbell. That's dependent on the async list, wheras 3972 * intr xfers are periodic, should not use this? 3973 */ 3974 ehci_abort_xfer(xfer, USBD_CANCELLED); 3975 } 3976 3977 Static void 3978 ehci_device_intr_close(usbd_pipe_handle pipe) 3979 { 3980 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3981 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3982 struct ehci_soft_islot *isp; 3983 3984 KASSERT(mutex_owned(&sc->sc_lock)); 3985 3986 isp = &sc->sc_islots[epipe->sqh->islot]; 3987 ehci_close_pipe(pipe, isp->sqh); 3988 } 3989 3990 Static void 3991 ehci_device_intr_done(usbd_xfer_handle xfer) 3992 { 3993 #define exfer EXFER(xfer) 3994 struct ehci_xfer *ex = EXFER(xfer); 3995 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3996 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3997 ehci_soft_qtd_t *data, *dataend; 3998 ehci_soft_qh_t *sqh; 3999 usbd_status err; 4000 int len, isread, endpt; 4001 4002 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4003 4004 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4005 xfer, xfer->ux_actlen, 0, 0); 4006 4007 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4008 4009 if (xfer->ux_pipe->up_repeat) { 4010 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 4011 4012 len = epipe->u.intr.length; 4013 xfer->ux_length = len; 4014 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4015 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4016 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4017 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4018 sqh = epipe->sqh; 4019 4020 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4021 &data, &dataend); 4022 if (err) { 4023 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4024 xfer->ux_status = err; 4025 return; 4026 } 4027 4028 /* Set up interrupt info. */ 4029 exfer->ex_sqtdstart = data; 4030 exfer->ex_sqtdend = dataend; 4031 #ifdef DIAGNOSTIC 4032 if (!exfer->ex_isdone) { 4033 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", 4034 exfer, 0, 0, 0); 4035 printf("ehci_device_intr_done: not done, ex=%p\n", 4036 exfer); 4037 } 4038 exfer->ex_isdone = 0; 4039 #endif 4040 4041 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4042 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4043 callout_reset(&xfer->ux_callout, 4044 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4045 } 4046 4047 xfer->ux_status = USBD_IN_PROGRESS; 4048 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4049 ehci_del_intr_list(sc, ex); /* remove from active list */ 4050 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 4051 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4052 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4053 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4054 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4055 } 4056 #undef exfer 4057 } 4058 4059 /************************/ 4060 4061 Static usbd_status 4062 ehci_device_fs_isoc_transfer(usbd_xfer_handle xfer) 4063 { 4064 usbd_status err; 4065 4066 err = usb_insert_transfer(xfer); 4067 if (err && err != USBD_IN_PROGRESS) 4068 return err; 4069 4070 return ehci_device_fs_isoc_start(xfer); 4071 } 4072 4073 Static usbd_status 4074 ehci_device_fs_isoc_start(usbd_xfer_handle xfer) 4075 { 4076 struct ehci_pipe *epipe; 4077 usbd_device_handle dev; 4078 ehci_softc_t *sc; 4079 struct ehci_xfer *exfer; 4080 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4081 usb_dma_t *dma_buf; 4082 int i, j, k, frames; 4083 int offs, total_length; 4084 int frindex; 4085 u_int huba, dir; 4086 4087 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4088 4089 start = NULL; 4090 prev = NULL; 4091 sitd = NULL; 4092 total_length = 0; 4093 exfer = (struct ehci_xfer *) xfer; 4094 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4095 dev = xfer->ux_pipe->up_dev; 4096 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4097 4098 /* 4099 * To allow continuous transfers, above we start all transfers 4100 * immediately. However, we're still going to get usbd_start_next call 4101 * this when another xfer completes. So, check if this is already 4102 * in progress or not 4103 */ 4104 4105 if (exfer->ex_sitdstart != NULL) 4106 return USBD_IN_PROGRESS; 4107 4108 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4109 xfer, xfer->ux_length, xfer->ux_flags, 0); 4110 4111 if (sc->sc_dying) 4112 return USBD_IOERROR; 4113 4114 /* 4115 * To avoid complication, don't allow a request right now that'll span 4116 * the entire frame table. To within 4 frames, to allow some leeway 4117 * on either side of where the hc currently is. 4118 */ 4119 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4120 xfer->ux_nframes >= sc->sc_flsize - 4) { 4121 printf("ehci: isoc descriptor requested that spans the entire" 4122 "frametable, too many frames\n"); 4123 return USBD_INVAL; 4124 } 4125 4126 #ifdef DIAGNOSTIC 4127 if (xfer->ux_rqflags & URQ_REQUEST) 4128 panic("ehci_device_fs_isoc_start: request\n"); 4129 4130 if (!exfer->ex_isdone) 4131 printf("ehci_device_fs_isoc_start: not done, ex = %p\n", exfer); 4132 exfer->ex_isdone = 0; 4133 #endif 4134 4135 /* 4136 * Step 1: Allocate and initialize sitds. 4137 */ 4138 4139 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4140 if (i > 16 || i == 0) { 4141 /* Spec page 271 says intervals > 16 are invalid */ 4142 USBHIST_LOG(ehcidebug, "bInterval %d invalid\n", 0, 0, 0, 0); 4143 4144 return USBD_INVAL; 4145 } 4146 4147 frames = xfer->ux_nframes; 4148 4149 if (frames == 0) { 4150 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4151 4152 return USBD_INVAL; 4153 } 4154 4155 dma_buf = &xfer->ux_dmabuf; 4156 offs = 0; 4157 4158 for (i = 0; i < frames; i++) { 4159 sitd = ehci_alloc_sitd(sc); 4160 4161 if (prev) 4162 prev->xfer_next = sitd; 4163 else 4164 start = sitd; 4165 4166 #ifdef DIAGNOSTIC 4167 if (xfer->ux_frlengths[i] > 0x3ff) { 4168 printf("ehci: invalid frame length\n"); 4169 xfer->ux_frlengths[i] = 0x3ff; 4170 } 4171 #endif 4172 4173 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4174 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4175 4176 /* Set page0 index and offset. */ 4177 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4178 4179 total_length += xfer->ux_frlengths[i]; 4180 offs += xfer->ux_frlengths[i]; 4181 4182 sitd->sitd.sitd_buffer[1] = 4183 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4184 4185 huba = dev->ud_myhsport->up_parent->ud_addr; 4186 4187 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4188 // Set hub address to 0 if embedded TT is used. 4189 if (huba == sc->sc_addr) 4190 huba = 0; 4191 } 4192 */ 4193 4194 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4195 dir = UE_GET_DIR(k) ? 1 : 0; 4196 sitd->sitd.sitd_endp = 4197 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4198 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4199 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4200 EHCI_SITD_SET_HUBA(huba) | 4201 EHCI_SITD_SET_DIR(dir)); 4202 4203 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4204 4205 /* XXX */ 4206 u_char sa, sb; 4207 u_int temp, tlen; 4208 sa = 0; 4209 4210 if (dir == 0) { /* OUT */ 4211 temp = 0; 4212 tlen = xfer->ux_frlengths[i]; 4213 if (tlen <= 188) { 4214 temp |= 1; /* T-count = 1, TP = ALL */ 4215 tlen = 1; 4216 } else { 4217 tlen += 187; 4218 tlen /= 188; 4219 temp |= tlen; /* T-count = [1..6] */ 4220 temp |= 8; /* TP = Begin */ 4221 } 4222 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4223 4224 tlen += sa; 4225 4226 if (tlen >= 8) { 4227 sb = 0; 4228 } else { 4229 sb = (1 << tlen); 4230 } 4231 4232 sa = (1 << sa); 4233 sa = (sb - sa) & 0x3F; 4234 sb = 0; 4235 } else { 4236 sb = (-(4 << sa)) & 0xFE; 4237 sa = (1 << sa) & 0x3F; 4238 sa = 0x01; 4239 sb = 0xfc; 4240 } 4241 4242 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4243 EHCI_SITD_SET_CMASK(sb)); 4244 4245 prev = sitd; 4246 } /* End of frame */ 4247 4248 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4249 4250 stop = sitd; 4251 stop->xfer_next = NULL; 4252 4253 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4254 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4255 4256 /* 4257 * Part 2: Transfer descriptors have now been set up, now they must 4258 * be scheduled into the periodic frame list. Erk. Not wanting to 4259 * complicate matters, transfer is denied if the transfer spans 4260 * more than the period frame list. 4261 */ 4262 4263 mutex_enter(&sc->sc_lock); 4264 4265 /* Start inserting frames */ 4266 if (epipe->u.isoc.cur_xfers > 0) { 4267 frindex = epipe->u.isoc.next_frame; 4268 } else { 4269 frindex = EOREAD4(sc, EHCI_FRINDEX); 4270 frindex = frindex >> 3; /* Erase microframe index */ 4271 frindex += 2; 4272 } 4273 4274 if (frindex >= sc->sc_flsize) 4275 frindex &= (sc->sc_flsize - 1); 4276 4277 /* Whats the frame interval? */ 4278 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4279 4280 sitd = start; 4281 for (j = 0; j < frames; j++) { 4282 if (sitd == NULL) 4283 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4284 4285 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4286 if (sitd->sitd.sitd_next == 0) 4287 /* FIXME: frindex table gets initialized to NULL 4288 * or EHCI_NULL? */ 4289 sitd->sitd.sitd_next = EHCI_NULL; 4290 4291 usb_syncmem(&sitd->dma, 4292 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4293 sizeof(ehci_sitd_t), 4294 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4295 4296 sc->sc_flist[frindex] = 4297 htole32(EHCI_LINK_SITD | sitd->physaddr); 4298 4299 usb_syncmem(&sc->sc_fldma, 4300 sizeof(ehci_link_t) * frindex, 4301 sizeof(ehci_link_t), 4302 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4303 4304 sitd->u.frame_list.next = sc->sc_softsitds[frindex]; 4305 sc->sc_softsitds[frindex] = sitd; 4306 if (sitd->u.frame_list.next != NULL) 4307 sitd->u.frame_list.next->u.frame_list.prev = sitd; 4308 sitd->slot = frindex; 4309 sitd->u.frame_list.prev = NULL; 4310 4311 frindex += i; 4312 if (frindex >= sc->sc_flsize) 4313 frindex -= sc->sc_flsize; 4314 4315 sitd = sitd->xfer_next; 4316 } 4317 4318 epipe->u.isoc.cur_xfers++; 4319 epipe->u.isoc.next_frame = frindex; 4320 4321 exfer->ex_sitdstart = start; 4322 exfer->ex_sitdend = stop; 4323 4324 ehci_add_intr_list(sc, exfer); 4325 xfer->ux_status = USBD_IN_PROGRESS; 4326 xfer->ux_done = 0; 4327 4328 mutex_exit(&sc->sc_lock); 4329 4330 if (sc->sc_bus.ub_usepolling) { 4331 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4332 ehci_waitintr(sc, xfer); 4333 } 4334 4335 return USBD_IN_PROGRESS; 4336 } 4337 4338 Static void 4339 ehci_device_fs_isoc_abort(usbd_xfer_handle xfer) 4340 { 4341 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4342 4343 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4344 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4345 } 4346 4347 Static void 4348 ehci_device_fs_isoc_close(usbd_pipe_handle pipe) 4349 { 4350 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4351 4352 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4353 } 4354 4355 Static void 4356 ehci_device_fs_isoc_done(usbd_xfer_handle xfer) 4357 { 4358 struct ehci_xfer *exfer; 4359 ehci_softc_t *sc; 4360 struct ehci_pipe *epipe; 4361 4362 exfer = EXFER(xfer); 4363 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4364 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4365 4366 KASSERT(mutex_owned(&sc->sc_lock)); 4367 4368 epipe->u.isoc.cur_xfers--; 4369 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4370 ehci_del_intr_list(sc, exfer); 4371 ehci_rem_free_sitd_chain(sc, exfer); 4372 } 4373 4374 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4375 BUS_DMASYNC_POSTREAD); 4376 } 4377 Static usbd_status 4378 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 4379 { 4380 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4381 usbd_status err; 4382 4383 mutex_enter(&sc->sc_lock); 4384 err = usb_insert_transfer(xfer); 4385 mutex_exit(&sc->sc_lock); 4386 if (err && err != USBD_IN_PROGRESS) 4387 return err; 4388 4389 return ehci_device_isoc_start(xfer); 4390 } 4391 4392 Static usbd_status 4393 ehci_device_isoc_start(usbd_xfer_handle xfer) 4394 { 4395 struct ehci_pipe *epipe; 4396 ehci_softc_t *sc; 4397 struct ehci_xfer *exfer; 4398 ehci_soft_itd_t *itd, *prev, *start, *stop; 4399 usb_dma_t *dma_buf; 4400 int i, j, k, frames, uframes, ufrperframe; 4401 int trans_count, offs, total_length; 4402 int frindex; 4403 4404 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4405 4406 start = NULL; 4407 prev = NULL; 4408 itd = NULL; 4409 trans_count = 0; 4410 total_length = 0; 4411 exfer = (struct ehci_xfer *) xfer; 4412 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4413 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4414 4415 /* 4416 * To allow continuous transfers, above we start all transfers 4417 * immediately. However, we're still going to get usbd_start_next call 4418 * this when another xfer completes. So, check if this is already 4419 * in progress or not 4420 */ 4421 4422 if (exfer->ex_itdstart != NULL) 4423 return USBD_IN_PROGRESS; 4424 4425 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4426 xfer, xfer->ux_length, xfer->ux_flags, 0); 4427 4428 if (sc->sc_dying) 4429 return USBD_IOERROR; 4430 4431 /* 4432 * To avoid complication, don't allow a request right now that'll span 4433 * the entire frame table. To within 4 frames, to allow some leeway 4434 * on either side of where the hc currently is. 4435 */ 4436 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4437 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4438 USBHIST_LOG(ehcidebug, 4439 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4440 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4441 return USBD_INVAL; 4442 } 4443 4444 #ifdef DIAGNOSTIC 4445 if (xfer->ux_rqflags & URQ_REQUEST) 4446 panic("ehci_device_isoc_start: request\n"); 4447 4448 if (!exfer->ex_isdone) { 4449 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", exfer, 4450 0, 0, 0); 4451 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 4452 } 4453 exfer->ex_isdone = 0; 4454 #endif 4455 4456 /* 4457 * Step 1: Allocate and initialize itds, how many do we need? 4458 * One per transfer if interval >= 8 microframes, fewer if we use 4459 * multiple microframes per frame. 4460 */ 4461 4462 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4463 if (i > 16 || i == 0) { 4464 /* Spec page 271 says intervals > 16 are invalid */ 4465 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4466 return USBD_INVAL; 4467 } 4468 4469 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4470 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4471 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4472 4473 if (frames == 0) { 4474 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4475 return USBD_INVAL; 4476 } 4477 4478 dma_buf = &xfer->ux_dmabuf; 4479 offs = 0; 4480 4481 for (i = 0; i < frames; i++) { 4482 int froffs = offs; 4483 itd = ehci_alloc_itd(sc); 4484 4485 if (prev != NULL) { 4486 prev->itd.itd_next = 4487 htole32(itd->physaddr | EHCI_LINK_ITD); 4488 usb_syncmem(&itd->dma, 4489 itd->offs + offsetof(ehci_itd_t, itd_next), 4490 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4491 4492 prev->xfer_next = itd; 4493 } else { 4494 start = itd; 4495 } 4496 4497 /* 4498 * Step 1.5, initialize uframes 4499 */ 4500 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4501 /* Calculate which page in the list this starts in */ 4502 int addr = DMAADDR(dma_buf, froffs); 4503 addr = EHCI_PAGE_OFFSET(addr); 4504 addr += (offs - froffs); 4505 addr = EHCI_PAGE(addr); 4506 addr /= EHCI_PAGE_SIZE; 4507 4508 /* This gets the initial offset into the first page, 4509 * looks how far further along the current uframe 4510 * offset is. Works out how many pages that is. 4511 */ 4512 4513 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4514 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4515 EHCI_ITD_SET_PG(addr) | 4516 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4517 4518 total_length += xfer->ux_frlengths[trans_count]; 4519 offs += xfer->ux_frlengths[trans_count]; 4520 trans_count++; 4521 4522 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4523 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4524 break; 4525 } 4526 } 4527 4528 /* Step 1.75, set buffer pointers. To simplify matters, all 4529 * pointers are filled out for the next 7 hardware pages in 4530 * the dma block, so no need to worry what pages to cover 4531 * and what to not. 4532 */ 4533 4534 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4535 /* 4536 * Don't try to lookup a page that's past the end 4537 * of buffer 4538 */ 4539 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4540 if (page_offs >= dma_buf->udma_block->size) 4541 break; 4542 4543 unsigned long long page = DMAADDR(dma_buf, page_offs); 4544 page = EHCI_PAGE(page); 4545 itd->itd.itd_bufr[j] = 4546 htole32(EHCI_ITD_SET_BPTR(page)); 4547 itd->itd.itd_bufr_hi[j] = 4548 htole32(page >> 32); 4549 } 4550 4551 /* 4552 * Other special values 4553 */ 4554 4555 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4556 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4557 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4558 4559 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4560 ? 1 : 0; 4561 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4562 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4563 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4564 4565 /* FIXME: handle invalid trans */ 4566 itd->itd.itd_bufr[2] |= 4567 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4568 4569 usb_syncmem(&itd->dma, 4570 itd->offs + offsetof(ehci_itd_t, itd_next), 4571 sizeof(ehci_itd_t), 4572 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4573 4574 prev = itd; 4575 } /* End of frame */ 4576 4577 stop = itd; 4578 stop->xfer_next = NULL; 4579 4580 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4581 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4582 4583 /* 4584 * Part 2: Transfer descriptors have now been set up, now they must 4585 * be scheduled into the period frame list. Erk. Not wanting to 4586 * complicate matters, transfer is denied if the transfer spans 4587 * more than the period frame list. 4588 */ 4589 4590 mutex_enter(&sc->sc_lock); 4591 4592 /* Start inserting frames */ 4593 if (epipe->u.isoc.cur_xfers > 0) { 4594 frindex = epipe->u.isoc.next_frame; 4595 } else { 4596 frindex = EOREAD4(sc, EHCI_FRINDEX); 4597 frindex = frindex >> 3; /* Erase microframe index */ 4598 frindex += 2; 4599 } 4600 4601 if (frindex >= sc->sc_flsize) 4602 frindex &= (sc->sc_flsize - 1); 4603 4604 /* What's the frame interval? */ 4605 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4606 if (i / USB_UFRAMES_PER_FRAME == 0) 4607 i = 1; 4608 else 4609 i /= USB_UFRAMES_PER_FRAME; 4610 4611 itd = start; 4612 for (j = 0; j < frames; j++) { 4613 if (itd == NULL) 4614 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4615 4616 itd->itd.itd_next = sc->sc_flist[frindex]; 4617 if (itd->itd.itd_next == 0) 4618 /* FIXME: frindex table gets initialized to NULL 4619 * or EHCI_NULL? */ 4620 itd->itd.itd_next = EHCI_NULL; 4621 4622 usb_syncmem(&itd->dma, 4623 itd->offs + offsetof(ehci_itd_t, itd_next), 4624 sizeof(itd->itd.itd_next), 4625 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4626 4627 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4628 4629 usb_syncmem(&sc->sc_fldma, 4630 sizeof(ehci_link_t) * frindex, 4631 sizeof(ehci_link_t), 4632 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4633 4634 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4635 sc->sc_softitds[frindex] = itd; 4636 if (itd->u.frame_list.next != NULL) 4637 itd->u.frame_list.next->u.frame_list.prev = itd; 4638 itd->slot = frindex; 4639 itd->u.frame_list.prev = NULL; 4640 4641 frindex += i; 4642 if (frindex >= sc->sc_flsize) 4643 frindex -= sc->sc_flsize; 4644 4645 itd = itd->xfer_next; 4646 } 4647 4648 epipe->u.isoc.cur_xfers++; 4649 epipe->u.isoc.next_frame = frindex; 4650 4651 exfer->ex_itdstart = start; 4652 exfer->ex_itdend = stop; 4653 4654 ehci_add_intr_list(sc, exfer); 4655 xfer->ux_status = USBD_IN_PROGRESS; 4656 xfer->ux_done = 0; 4657 mutex_exit(&sc->sc_lock); 4658 4659 if (sc->sc_bus.ub_usepolling) { 4660 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4661 ehci_waitintr(sc, xfer); 4662 } 4663 4664 return USBD_IN_PROGRESS; 4665 } 4666 4667 Static void 4668 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4669 { 4670 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4671 4672 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4673 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4674 } 4675 4676 Static void 4677 ehci_device_isoc_close(usbd_pipe_handle pipe) 4678 { 4679 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4680 4681 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4682 } 4683 4684 Static void 4685 ehci_device_isoc_done(usbd_xfer_handle xfer) 4686 { 4687 struct ehci_xfer *exfer; 4688 ehci_softc_t *sc; 4689 struct ehci_pipe *epipe; 4690 4691 exfer = EXFER(xfer); 4692 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4693 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4694 4695 KASSERT(mutex_owned(&sc->sc_lock)); 4696 4697 epipe->u.isoc.cur_xfers--; 4698 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4699 ehci_del_intr_list(sc, exfer); 4700 ehci_rem_free_itd_chain(sc, exfer); 4701 } 4702 4703 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4704 BUS_DMASYNC_POSTREAD); 4705 4706 } 4707
Indexes created Wed Oct 01 19:09:53 GMT 2025