ehci.c revision 1.234.2.26
1 /* $NetBSD: ehci.c,v 1.234.2.26 2015/01/02 08:43:06 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.26 2015/01/02 08:43:06 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 85 #include <dev/usb/ehcireg.h> 86 #include <dev/usb/ehcivar.h> 87 #include <dev/usb/usbroothub.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 /* ehci_soft_sitd_t *sitd; */ 135 } tail; 136 union { 137 /* Control pipe */ 138 struct { 139 usb_dma_t reqdma; 140 } ctl; 141 /* Interrupt pipe */ 142 struct { 143 u_int length; 144 } intr; 145 /* Bulk pipe */ 146 struct { 147 u_int length; 148 } bulk; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 } u; 155 }; 156 157 Static usbd_status ehci_open(usbd_pipe_handle); 158 Static void ehci_poll(struct usbd_bus *); 159 Static void ehci_softintr(void *); 160 Static int ehci_intr1(ehci_softc_t *); 161 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 162 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 166 Static void ehci_idone(struct ehci_xfer *); 167 Static void ehci_timeout(void *); 168 Static void ehci_timeout_task(void *); 169 Static void ehci_intrlist_timeout(void *); 170 Static void ehci_doorbell(void *); 171 Static void ehci_pcd(void *); 172 173 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 174 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 Static int ehci_roothub_ctrl(struct usbd_bus *, 177 usb_device_request_t *, void *, int); 178 179 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 180 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 181 Static void ehci_root_intr_abort(usbd_xfer_handle); 182 Static void ehci_root_intr_close(usbd_pipe_handle); 183 Static void ehci_root_intr_done(usbd_xfer_handle); 184 185 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 186 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 187 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 188 Static void ehci_device_ctrl_close(usbd_pipe_handle); 189 Static void ehci_device_ctrl_done(usbd_xfer_handle); 190 191 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 192 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 193 Static void ehci_device_bulk_abort(usbd_xfer_handle); 194 Static void ehci_device_bulk_close(usbd_pipe_handle); 195 Static void ehci_device_bulk_done(usbd_xfer_handle); 196 197 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 198 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 199 Static void ehci_device_intr_abort(usbd_xfer_handle); 200 Static void ehci_device_intr_close(usbd_pipe_handle); 201 Static void ehci_device_intr_done(usbd_xfer_handle); 202 203 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 204 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 205 Static void ehci_device_isoc_abort(usbd_xfer_handle); 206 Static void ehci_device_isoc_close(usbd_pipe_handle); 207 Static void ehci_device_isoc_done(usbd_xfer_handle); 208 209 Static usbd_status ehci_device_fs_isoc_transfer(usbd_xfer_handle); 210 Static usbd_status ehci_device_fs_isoc_start(usbd_xfer_handle); 211 Static void ehci_device_fs_isoc_abort(usbd_xfer_handle); 212 Static void ehci_device_fs_isoc_close(usbd_pipe_handle); 213 Static void ehci_device_fs_isoc_done(usbd_xfer_handle); 214 215 Static void ehci_device_clear_toggle(usbd_pipe_handle); 216 Static void ehci_noop(usbd_pipe_handle); 217 218 Static void ehci_disown(ehci_softc_t *, int, int); 219 220 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 221 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 222 223 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 224 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 225 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 226 ehci_softc_t *, int, int, usbd_xfer_handle, 227 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 228 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 229 ehci_soft_qtd_t *); 230 231 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 232 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *); 233 Static void ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *); 234 Static void ehci_free_sitd(ehci_softc_t *, ehci_soft_sitd_t *); 235 Static void ehci_rem_free_itd_chain(ehci_softc_t *, 236 struct ehci_xfer *); 237 Static void ehci_rem_free_sitd_chain(ehci_softc_t *, 238 struct ehci_xfer *); 239 Static void ehci_abort_isoc_xfer(usbd_xfer_handle, 240 usbd_status); 241 242 Static usbd_status ehci_device_request(usbd_xfer_handle); 243 244 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 245 int); 246 247 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 248 ehci_soft_qh_t *); 249 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 250 ehci_soft_qh_t *); 251 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 252 Static void ehci_sync_hc(ehci_softc_t *); 253 254 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 255 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 256 257 #ifdef EHCI_DEBUG 258 Static ehci_softc_t *theehci; 259 void ehci_dump(void); 260 #endif 261 262 #ifdef EHCI_DEBUG 263 Static void ehci_dump_regs(ehci_softc_t *); 264 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 265 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 266 Static void ehci_dump_qtd(ehci_qtd_t *); 267 Static void ehci_dump_sqh(ehci_soft_qh_t *); 268 Static void ehci_dump_sitd(struct ehci_soft_itd *); 269 Static void ehci_dump_itd(struct ehci_soft_itd *); 270 Static void ehci_dump_exfer(struct ehci_xfer *); 271 #endif 272 273 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 274 275 #define ehci_add_intr_list(sc, ex) \ 276 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 277 #define ehci_del_intr_list(sc, ex) \ 278 do { \ 279 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 280 (ex)->ex_next.tqe_prev = NULL; \ 281 } while (0) 282 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 283 284 Static const struct usbd_bus_methods ehci_bus_methods = { 285 .ubm_open = ehci_open, 286 .ubm_softint = ehci_softintr, 287 .ubm_dopoll = ehci_poll, 288 .ubm_allocx = ehci_allocx, 289 .ubm_freex = ehci_freex, 290 .ubm_getlock = ehci_get_lock, 291 .ubm_rhctrl = ehci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 295 .upm_transfer = ehci_root_intr_transfer, 296 .upm_start = ehci_root_intr_start, 297 .upm_abort = ehci_root_intr_abort, 298 .upm_close = ehci_root_intr_close, 299 .upm_cleartoggle = ehci_noop, 300 .upm_done = ehci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 304 .upm_transfer = ehci_device_ctrl_transfer, 305 .upm_start = ehci_device_ctrl_start, 306 .upm_abort = ehci_device_ctrl_abort, 307 .upm_close = ehci_device_ctrl_close, 308 .upm_cleartoggle = ehci_noop, 309 .upm_done = ehci_device_ctrl_done, 310 }; 311 312 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 313 .upm_transfer = ehci_device_intr_transfer, 314 .upm_start = ehci_device_intr_start, 315 .upm_abort = ehci_device_intr_abort, 316 .upm_close = ehci_device_intr_close, 317 .upm_cleartoggle = ehci_device_clear_toggle, 318 .upm_done = ehci_device_intr_done, 319 }; 320 321 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 322 .upm_transfer = ehci_device_bulk_transfer, 323 .upm_start = ehci_device_bulk_start, 324 .upm_abort = ehci_device_bulk_abort, 325 .upm_close = ehci_device_bulk_close, 326 .upm_cleartoggle = ehci_device_clear_toggle, 327 .upm_done = ehci_device_bulk_done, 328 }; 329 330 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 331 .upm_transfer = ehci_device_isoc_transfer, 332 .upm_start = ehci_device_isoc_start, 333 .upm_abort = ehci_device_isoc_abort, 334 .upm_close = ehci_device_isoc_close, 335 .upm_cleartoggle = ehci_noop, 336 .upm_done = ehci_device_isoc_done, 337 }; 338 339 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 340 .upm_transfer = ehci_device_fs_isoc_transfer, 341 .upm_start = ehci_device_fs_isoc_start, 342 .upm_abort = ehci_device_fs_isoc_abort, 343 .upm_close = ehci_device_fs_isoc_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_fs_isoc_done, 346 }; 347 348 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 349 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 350 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 351 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 352 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 353 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 354 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 355 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 356 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 357 }; 358 359 int 360 ehci_init(ehci_softc_t *sc) 361 { 362 uint32_t vers, sparams, cparams, hcr; 363 u_int i; 364 usbd_status err; 365 ehci_soft_qh_t *sqh; 366 u_int ncomp; 367 368 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 369 #ifdef EHCI_DEBUG 370 theehci = sc; 371 #endif 372 373 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 374 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 375 cv_init(&sc->sc_softwake_cv, "ehciab"); 376 cv_init(&sc->sc_doorbell, "ehcidi"); 377 378 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 379 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 380 381 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 382 ehci_doorbell, sc); 383 KASSERT(sc->sc_doorbell_si != NULL); 384 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 385 ehci_pcd, sc); 386 KASSERT(sc->sc_pcd_si != NULL); 387 388 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 389 390 vers = EREAD2(sc, EHCI_HCIVERSION); 391 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 392 vers >> 8, vers & 0xff); 393 394 sparams = EREAD4(sc, EHCI_HCSPARAMS); 395 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 396 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 397 ncomp = EHCI_HCS_N_CC(sparams); 398 if (ncomp != sc->sc_ncomp) { 399 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 400 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 401 #if NOHCI == 0 || NUHCI == 0 402 aprint_error("%s: ohci or uhci probably not configured\n", 403 device_xname(sc->sc_dev)); 404 #endif 405 if (ncomp < sc->sc_ncomp) 406 sc->sc_ncomp = ncomp; 407 } 408 if (sc->sc_ncomp > 0) { 409 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 410 aprint_normal("%s: companion controller%s, %d port%s each:", 411 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 412 EHCI_HCS_N_PCC(sparams), 413 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 414 for (i = 0; i < sc->sc_ncomp; i++) 415 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 416 aprint_normal("\n"); 417 } 418 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 419 cparams = EREAD4(sc, EHCI_HCCPARAMS); 420 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 421 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 422 423 if (EHCI_HCC_64BIT(cparams)) { 424 /* MUST clear segment register if 64 bit capable. */ 425 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 426 } 427 428 sc->sc_bus.ub_revision = USBREV_2_0; 429 sc->sc_bus.ub_usedma = true; 430 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 431 432 /* Reset the controller */ 433 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 434 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 435 usb_delay_ms(&sc->sc_bus, 1); 436 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 437 for (i = 0; i < 100; i++) { 438 usb_delay_ms(&sc->sc_bus, 1); 439 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 440 if (!hcr) 441 break; 442 } 443 if (hcr) { 444 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 445 return EIO; 446 } 447 if (sc->sc_vendor_init) 448 sc->sc_vendor_init(sc); 449 450 /* 451 * If we are doing embedded transaction translation function, force 452 * the controller to host mode. 453 */ 454 if (sc->sc_flags & EHCIF_ETTF) { 455 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 456 usbmode &= ~EHCI_USBMODE_CM; 457 usbmode |= EHCI_USBMODE_CM_HOST; 458 EWRITE4(sc, EHCI_USBMODE, usbmode); 459 } 460 461 /* XXX need proper intr scheduling */ 462 sc->sc_rand = 96; 463 464 /* frame list size at default, read back what we got and use that */ 465 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 466 case 0: sc->sc_flsize = 1024; break; 467 case 1: sc->sc_flsize = 512; break; 468 case 2: sc->sc_flsize = 256; break; 469 case 3: return EIO; 470 } 471 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 472 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 473 if (err) 474 return err; 475 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 476 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 477 478 for (i = 0; i < sc->sc_flsize; i++) { 479 sc->sc_flist[i] = EHCI_NULL; 480 } 481 482 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 483 484 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 485 KM_SLEEP); 486 if (sc->sc_softitds == NULL) 487 return ENOMEM; 488 LIST_INIT(&sc->sc_freeitds); 489 LIST_INIT(&sc->sc_freesitds); 490 TAILQ_INIT(&sc->sc_intrhead); 491 492 /* Set up the bus struct. */ 493 sc->sc_bus.ub_methods = &ehci_bus_methods; 494 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 495 496 sc->sc_eintrs = EHCI_NORMAL_INTRS; 497 498 /* 499 * Allocate the interrupt dummy QHs. These are arranged to give poll 500 * intervals that are powers of 2 times 1ms. 501 */ 502 for (i = 0; i < EHCI_INTRQHS; i++) { 503 sqh = ehci_alloc_sqh(sc); 504 if (sqh == NULL) { 505 err = ENOMEM; 506 goto bad1; 507 } 508 sc->sc_islots[i].sqh = sqh; 509 } 510 for (i = 0; i < EHCI_INTRQHS; i++) { 511 sqh = sc->sc_islots[i].sqh; 512 if (i == 0) { 513 /* The last (1ms) QH terminates. */ 514 sqh->qh.qh_link = EHCI_NULL; 515 sqh->next = NULL; 516 } else { 517 /* Otherwise the next QH has half the poll interval */ 518 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 519 sqh->qh.qh_link = htole32(sqh->next->physaddr | 520 EHCI_LINK_QH); 521 } 522 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 523 sqh->qh.qh_curqtd = EHCI_NULL; 524 sqh->next = NULL; 525 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 526 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 527 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 528 sqh->sqtd = NULL; 529 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 531 } 532 /* Point the frame list at the last level (128ms). */ 533 for (i = 0; i < sc->sc_flsize; i++) { 534 int j; 535 536 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 537 revbits[i & (EHCI_MAX_POLLRATE-1)]; 538 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 539 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 540 i)].sqh->physaddr); 541 } 542 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 543 BUS_DMASYNC_PREWRITE); 544 545 /* Allocate dummy QH that starts the async list. */ 546 sqh = ehci_alloc_sqh(sc); 547 if (sqh == NULL) { 548 err = ENOMEM; 549 goto bad1; 550 } 551 /* Fill the QH */ 552 sqh->qh.qh_endp = 553 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 554 sqh->qh.qh_link = 555 htole32(sqh->physaddr | EHCI_LINK_QH); 556 sqh->qh.qh_curqtd = EHCI_NULL; 557 sqh->next = NULL; 558 /* Fill the overlay qTD */ 559 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 560 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 561 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 562 sqh->sqtd = NULL; 563 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 564 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 565 #ifdef EHCI_DEBUG 566 ehci_dump_sqh(sqh); 567 #endif 568 569 /* Point to async list */ 570 sc->sc_async_head = sqh; 571 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 572 573 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 574 575 /* Turn on controller */ 576 EOWRITE4(sc, EHCI_USBCMD, 577 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 578 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 579 EHCI_CMD_ASE | 580 EHCI_CMD_PSE | 581 EHCI_CMD_RS); 582 583 /* Take over port ownership */ 584 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 585 586 for (i = 0; i < 100; i++) { 587 usb_delay_ms(&sc->sc_bus, 1); 588 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 589 if (!hcr) 590 break; 591 } 592 if (hcr) { 593 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 594 return EIO; 595 } 596 597 /* Enable interrupts */ 598 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 599 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 600 601 return 0; 602 603 #if 0 604 bad2: 605 ehci_free_sqh(sc, sc->sc_async_head); 606 #endif 607 bad1: 608 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 609 return err; 610 } 611 612 int 613 ehci_intr(void *v) 614 { 615 ehci_softc_t *sc = v; 616 int ret = 0; 617 618 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 619 620 if (sc == NULL) 621 return 0; 622 623 mutex_spin_enter(&sc->sc_intr_lock); 624 625 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 626 goto done; 627 628 /* If we get an interrupt while polling, then just ignore it. */ 629 if (sc->sc_bus.ub_usepolling) { 630 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 631 632 if (intrs) 633 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 634 USBHIST_LOGN(ehcidebug, 16, 635 "ignored interrupt while polling", 0, 0, 0, 0); 636 goto done; 637 } 638 639 ret = ehci_intr1(sc); 640 641 done: 642 mutex_spin_exit(&sc->sc_intr_lock); 643 return ret; 644 } 645 646 Static int 647 ehci_intr1(ehci_softc_t *sc) 648 { 649 uint32_t intrs, eintrs; 650 651 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 652 653 /* In case the interrupt occurs before initialization has completed. */ 654 if (sc == NULL) { 655 #ifdef DIAGNOSTIC 656 printf("ehci_intr1: sc == NULL\n"); 657 #endif 658 return 0; 659 } 660 661 KASSERT(mutex_owned(&sc->sc_intr_lock)); 662 663 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 664 if (!intrs) 665 return 0; 666 667 eintrs = intrs & sc->sc_eintrs; 668 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 669 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 670 if (!eintrs) 671 return 0; 672 673 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 674 if (eintrs & EHCI_STS_IAA) { 675 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 676 kpreempt_disable(); 677 KASSERT(sc->sc_doorbell_si != NULL); 678 softint_schedule(sc->sc_doorbell_si); 679 kpreempt_enable(); 680 eintrs &= ~EHCI_STS_IAA; 681 } 682 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 683 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 684 eintrs & EHCI_STS_INT ? 1 : 0, 685 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 686 usb_schedsoftintr(&sc->sc_bus); 687 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 688 } 689 if (eintrs & EHCI_STS_HSE) { 690 printf("%s: unrecoverable error, controller halted\n", 691 device_xname(sc->sc_dev)); 692 /* XXX what else */ 693 } 694 if (eintrs & EHCI_STS_PCD) { 695 kpreempt_disable(); 696 KASSERT(sc->sc_pcd_si != NULL); 697 softint_schedule(sc->sc_pcd_si); 698 kpreempt_enable(); 699 eintrs &= ~EHCI_STS_PCD; 700 } 701 702 if (eintrs != 0) { 703 /* Block unprocessed interrupts. */ 704 sc->sc_eintrs &= ~eintrs; 705 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 706 printf("%s: blocking intrs 0x%x\n", 707 device_xname(sc->sc_dev), eintrs); 708 } 709 710 return 1; 711 } 712 713 Static void 714 ehci_doorbell(void *addr) 715 { 716 ehci_softc_t *sc = addr; 717 718 mutex_enter(&sc->sc_lock); 719 cv_broadcast(&sc->sc_doorbell); 720 mutex_exit(&sc->sc_lock); 721 } 722 723 Static void 724 ehci_pcd(void *addr) 725 { 726 ehci_softc_t *sc = addr; 727 usbd_xfer_handle xfer; 728 u_char *p; 729 int i, m; 730 731 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 732 733 mutex_enter(&sc->sc_lock); 734 xfer = sc->sc_intrxfer; 735 736 if (xfer == NULL) { 737 /* Just ignore the change. */ 738 goto done; 739 } 740 741 p = xfer->ux_buf; 742 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 743 memset(p, 0, xfer->ux_length); 744 for (i = 1; i <= m; i++) { 745 /* Pick out CHANGE bits from the status reg. */ 746 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 747 p[i/8] |= 1 << (i%8); 748 if (i % 8 == 7) 749 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 750 p[i/8], 0, 0); 751 } 752 xfer->ux_actlen = xfer->ux_length; 753 xfer->ux_status = USBD_NORMAL_COMPLETION; 754 755 usb_transfer_complete(xfer); 756 757 done: 758 mutex_exit(&sc->sc_lock); 759 } 760 761 Static void 762 ehci_softintr(void *v) 763 { 764 struct usbd_bus *bus = v; 765 ehci_softc_t *sc = bus->ub_hcpriv; 766 struct ehci_xfer *ex, *nextex; 767 768 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 769 770 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 771 772 /* 773 * The only explanation I can think of for why EHCI is as brain dead 774 * as UHCI interrupt-wise is that Intel was involved in both. 775 * An interrupt just tells us that something is done, we have no 776 * clue what, so we need to scan through all active transfers. :-( 777 */ 778 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 779 nextex = TAILQ_NEXT(ex, ex_next); 780 ehci_check_intr(sc, ex); 781 } 782 783 /* Schedule a callout to catch any dropped transactions. */ 784 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 785 !TAILQ_EMPTY(&sc->sc_intrhead)) 786 callout_reset(&sc->sc_tmo_intrlist, 787 hz, ehci_intrlist_timeout, sc); 788 789 if (sc->sc_softwake) { 790 sc->sc_softwake = 0; 791 cv_broadcast(&sc->sc_softwake_cv); 792 } 793 } 794 795 /* Check for an interrupt. */ 796 Static void 797 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 798 { 799 usbd_device_handle dev = ex->ex_xfer.ux_pipe->up_dev; 800 int attr; 801 802 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 803 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 804 805 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 806 807 attr = ex->ex_xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 808 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 809 if (dev->ud_speed == USB_SPEED_HIGH) 810 ehci_check_itd_intr(sc, ex); 811 else 812 ehci_check_sitd_intr(sc, ex); 813 } else 814 ehci_check_qh_intr(sc, ex); 815 816 return; 817 } 818 819 Static void 820 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 821 { 822 ehci_soft_qtd_t *sqtd, *lsqtd; 823 uint32_t status; 824 825 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 826 827 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 828 829 if (ex->ex_sqtdstart == NULL) { 830 printf("ehci_check_qh_intr: not valid sqtd\n"); 831 return; 832 } 833 834 lsqtd = ex->ex_sqtdend; 835 #ifdef DIAGNOSTIC 836 if (lsqtd == NULL) { 837 printf("ehci_check_qh_intr: lsqtd==0\n"); 838 return; 839 } 840 #endif 841 /* 842 * If the last TD is still active we need to check whether there 843 * is an error somewhere in the middle, or whether there was a 844 * short packet (SPD and not ACTIVE). 845 */ 846 usb_syncmem(&lsqtd->dma, 847 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 848 sizeof(lsqtd->qtd.qtd_status), 849 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 850 status = le32toh(lsqtd->qtd.qtd_status); 851 usb_syncmem(&lsqtd->dma, 852 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 853 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 854 if (status & EHCI_QTD_ACTIVE) { 855 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 856 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd; 857 sqtd = sqtd->nextqtd) { 858 usb_syncmem(&sqtd->dma, 859 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 860 sizeof(sqtd->qtd.qtd_status), 861 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 862 status = le32toh(sqtd->qtd.qtd_status); 863 usb_syncmem(&sqtd->dma, 864 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 865 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 866 /* If there's an active QTD the xfer isn't done. */ 867 if (status & EHCI_QTD_ACTIVE) 868 break; 869 /* Any kind of error makes the xfer done. */ 870 if (status & EHCI_QTD_HALTED) 871 goto done; 872 /* Handle short packets */ 873 if (EHCI_QTD_GET_BYTES(status) != 0) { 874 usbd_pipe_handle pipe = ex->ex_xfer.ux_pipe; 875 usb_endpoint_descriptor_t *ed = 876 pipe->up_endpoint->ue_edesc; 877 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 878 879 /* 880 * If we get here for a control transfer then 881 * we need to let the hardware complete the 882 * status phase. That is, we're not done 883 * quite yet. 884 * 885 * Otherwise, we're done. 886 */ 887 if (xt == UE_CONTROL) { 888 break; 889 } 890 goto done; 891 } 892 } 893 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 894 ex, ex->ex_sqtdstart, 0, 0); 895 return; 896 } 897 done: 898 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 899 callout_stop(&ex->ex_xfer.ux_callout); 900 ehci_idone(ex); 901 } 902 903 Static void 904 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 905 { 906 ehci_soft_itd_t *itd; 907 int i; 908 909 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 910 911 KASSERT(mutex_owned(&sc->sc_lock)); 912 913 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 914 return; 915 916 if (ex->ex_itdstart == NULL) { 917 printf("ehci_check_itd_intr: not valid itd\n"); 918 return; 919 } 920 921 itd = ex->ex_itdend; 922 #ifdef DIAGNOSTIC 923 if (itd == NULL) { 924 printf("ehci_check_itd_intr: itdend == 0\n"); 925 return; 926 } 927 #endif 928 929 /* 930 * check no active transfers in last itd, meaning we're finished 931 */ 932 933 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 934 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 935 BUS_DMASYNC_POSTREAD); 936 937 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 938 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 939 break; 940 } 941 942 if (i == EHCI_ITD_NUFRAMES) { 943 goto done; /* All 8 descriptors inactive, it's done */ 944 } 945 946 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 947 ex->ex_itdstart, 0, 0); 948 return; 949 done: 950 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 951 callout_stop(&ex->ex_xfer.ux_callout); 952 ehci_idone(ex); 953 } 954 955 void 956 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 957 { 958 ehci_soft_sitd_t *sitd; 959 960 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 961 962 KASSERT(mutex_owned(&sc->sc_lock)); 963 964 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 965 return; 966 967 if (ex->ex_sitdstart == NULL) { 968 printf("ehci_check_sitd_intr: not valid sitd\n"); 969 return; 970 } 971 972 sitd = ex->ex_sitdend; 973 #ifdef DIAGNOSTIC 974 if (sitd == NULL) { 975 printf("ehci_check_sitd_intr: sitdend == 0\n"); 976 return; 977 } 978 #endif 979 980 /* 981 * check no active transfers in last sitd, meaning we're finished 982 */ 983 984 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 985 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 986 BUS_DMASYNC_POSTREAD); 987 988 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 989 return; 990 991 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 992 callout_stop(&(ex->ex_xfer.ux_callout)); 993 ehci_idone(ex); 994 } 995 996 997 Static void 998 ehci_idone(struct ehci_xfer *ex) 999 { 1000 usbd_xfer_handle xfer = &ex->ex_xfer; 1001 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1002 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1003 ehci_soft_qtd_t *sqtd, *lsqtd; 1004 uint32_t status = 0, nstatus = 0; 1005 int actlen; 1006 1007 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1008 1009 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1010 1011 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1012 1013 #ifdef DIAGNOSTIC 1014 if (ex->ex_isdone) { 1015 printf("ehci_idone: ex=%p is done!\n", ex); 1016 #ifdef EHCI_DEBUG 1017 ehci_dump_exfer(ex); 1018 #endif 1019 return; 1020 } 1021 ex->ex_isdone = 1; 1022 #endif 1023 1024 if (xfer->ux_status == USBD_CANCELLED || 1025 xfer->ux_status == USBD_TIMEOUT) { 1026 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1027 return; 1028 } 1029 1030 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1031 #ifdef EHCI_DEBUG 1032 ehci_dump_sqtds(ex->ex_sqtdstart); 1033 #endif 1034 1035 /* The transfer is done, compute actual length and status. */ 1036 1037 u_int xfertype, speed; 1038 1039 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1040 speed = xfer->ux_pipe->up_dev->ud_speed; 1041 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1042 /* HS isoc transfer */ 1043 1044 struct ehci_soft_itd *itd; 1045 int i, nframes, len, uframes; 1046 1047 nframes = 0; 1048 actlen = 0; 1049 1050 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1051 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1052 1053 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1054 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1055 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1056 BUS_DMASYNC_POSTREAD); 1057 1058 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1059 /* XXX - driver didn't fill in the frame full 1060 * of uframes. This leads to scheduling 1061 * inefficiencies, but working around 1062 * this doubles complexity of tracking 1063 * an xfer. 1064 */ 1065 if (nframes >= xfer->ux_nframes) 1066 break; 1067 1068 status = le32toh(itd->itd.itd_ctl[i]); 1069 len = EHCI_ITD_GET_LEN(status); 1070 if (EHCI_ITD_GET_STATUS(status) != 0) 1071 len = 0; /*No valid data on error*/ 1072 1073 xfer->ux_frlengths[nframes++] = len; 1074 actlen += len; 1075 } 1076 1077 if (nframes >= xfer->ux_nframes) 1078 break; 1079 } 1080 1081 xfer->ux_actlen = actlen; 1082 xfer->ux_status = USBD_NORMAL_COMPLETION; 1083 goto end; 1084 } 1085 1086 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1087 /* FS isoc transfer */ 1088 struct ehci_soft_sitd *sitd; 1089 int nframes, len; 1090 1091 nframes = 0; 1092 actlen = 0; 1093 1094 for (sitd = ex->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1095 usb_syncmem(&sitd->dma,sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 1096 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 1097 BUS_DMASYNC_POSTREAD); 1098 1099 /* XXX - driver didn't fill in the frame full 1100 * of uframes. This leads to scheduling 1101 * inefficiencies, but working around 1102 * this doubles complexity of tracking 1103 * an xfer. 1104 */ 1105 if (nframes >= xfer->ux_nframes) 1106 break; 1107 1108 status = le32toh(sitd->sitd.sitd_trans); 1109 len = EHCI_SITD_GET_LEN(status); 1110 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1111 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1112 /* No valid data on error */ 1113 len = xfer->ux_frlengths[nframes]; 1114 } 1115 1116 /* 1117 * frlengths[i]: # of bytes to send 1118 * len: # of bytes host didn't send 1119 */ 1120 xfer->ux_frlengths[nframes] -= len; 1121 /* frlengths[i]: # of bytes host sent */ 1122 actlen += xfer->ux_frlengths[nframes++]; 1123 1124 if (nframes >= xfer->ux_nframes) 1125 break; 1126 } 1127 1128 xfer->ux_actlen = actlen; 1129 xfer->ux_status = USBD_NORMAL_COMPLETION; 1130 goto end; 1131 } 1132 KASSERT(xfertype != UE_ISOCHRONOUS); 1133 1134 /* Continue processing xfers using queue heads */ 1135 1136 lsqtd = ex->ex_sqtdend; 1137 actlen = 0; 1138 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd->nextqtd; 1139 sqtd = sqtd->nextqtd) { 1140 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1141 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1142 nstatus = le32toh(sqtd->qtd.qtd_status); 1143 if (nstatus & EHCI_QTD_ACTIVE) 1144 break; 1145 1146 status = nstatus; 1147 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1148 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1149 } 1150 1151 1152 /* 1153 * If there are left over TDs we need to update the toggle. 1154 * The default pipe doesn't need it since control transfers 1155 * start the toggle at 0 every time. 1156 * For a short transfer we need to update the toggle for the missing 1157 * packets within the qTD. 1158 */ 1159 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1160 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1161 USBHIST_LOG(ehcidebug, 1162 "toggle update status=0x%08x nstatus=0x%08x", 1163 status, nstatus, 0, 0); 1164 #if 0 1165 ehci_dump_sqh(epipe->sqh); 1166 ehci_dump_sqtds(ex->ex_sqtdstart); 1167 #endif 1168 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1169 } 1170 1171 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1172 actlen, status, 0); 1173 xfer->ux_actlen = actlen; 1174 if (status & EHCI_QTD_HALTED) { 1175 #ifdef EHCI_DEBUG 1176 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1177 xfer->ux_pipe->up_dev->ud_addr, 1178 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1179 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d stat=%#x", 1180 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1181 status, 0); 1182 USBHIST_LOG(ehcidebug, 1183 "active =%d halted=%d buferr=%d babble=%d", 1184 status & EHCI_QTD_ACTIVE ? 1 : 0, 1185 status & EHCI_QTD_HALTED ? 1 : 0, 1186 status & EHCI_QTD_BUFERR ? 1 : 0, 1187 status & EHCI_QTD_BABBLE ? 1 : 0); 1188 1189 USBHIST_LOG(ehcidebug, 1190 "xacterr=%d missed=%d split =%d ping =%d", 1191 status & EHCI_QTD_XACTERR ? 1 : 0, 1192 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1193 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1194 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1195 1196 ehci_dump_sqh(epipe->sqh); 1197 ehci_dump_sqtds(ex->ex_sqtdstart); 1198 #endif 1199 /* low&full speed has an extra error flag */ 1200 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1201 EHCI_QH_SPEED_HIGH) 1202 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1203 else 1204 status &= EHCI_QTD_STATERRS; 1205 if (status == 0) /* no other errors means a stall */ { 1206 xfer->ux_status = USBD_STALLED; 1207 } else { 1208 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1209 } 1210 /* XXX need to reset TT on missed microframe */ 1211 if (status & EHCI_QTD_MISSEDMICRO) { 1212 printf("%s: missed microframe, TT reset not " 1213 "implemented, hub might be inoperational\n", 1214 device_xname(sc->sc_dev)); 1215 } 1216 } else { 1217 xfer->ux_status = USBD_NORMAL_COMPLETION; 1218 } 1219 1220 end: 1221 /* XXX transfer_complete memcpys out transfer data (for in endpoints) 1222 * during this call, before methods->done is called: dma sync required 1223 * beforehand? */ 1224 usb_transfer_complete(xfer); 1225 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1226 } 1227 1228 /* 1229 * Wait here until controller claims to have an interrupt. 1230 * Then call ehci_intr and return. Use timeout to avoid waiting 1231 * too long. 1232 */ 1233 Static void 1234 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1235 { 1236 int timo; 1237 uint32_t intrs; 1238 1239 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1240 1241 xfer->ux_status = USBD_IN_PROGRESS; 1242 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1243 usb_delay_ms(&sc->sc_bus, 1); 1244 if (sc->sc_dying) 1245 break; 1246 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1247 sc->sc_eintrs; 1248 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1249 #ifdef EHCI_DEBUG 1250 if (ehcidebug > 15) 1251 ehci_dump_regs(sc); 1252 #endif 1253 if (intrs) { 1254 mutex_spin_enter(&sc->sc_intr_lock); 1255 ehci_intr1(sc); 1256 mutex_spin_exit(&sc->sc_intr_lock); 1257 if (xfer->ux_status != USBD_IN_PROGRESS) 1258 return; 1259 } 1260 } 1261 1262 /* Timeout */ 1263 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1264 xfer->ux_status = USBD_TIMEOUT; 1265 mutex_enter(&sc->sc_lock); 1266 usb_transfer_complete(xfer); 1267 mutex_exit(&sc->sc_lock); 1268 /* XXX should free TD */ 1269 } 1270 1271 Static void 1272 ehci_poll(struct usbd_bus *bus) 1273 { 1274 ehci_softc_t *sc = bus->ub_hcpriv; 1275 1276 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1277 1278 #ifdef EHCI_DEBUG 1279 static int last; 1280 int new; 1281 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1282 if (new != last) { 1283 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1284 last = new; 1285 } 1286 #endif 1287 1288 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1289 mutex_spin_enter(&sc->sc_intr_lock); 1290 ehci_intr1(sc); 1291 mutex_spin_exit(&sc->sc_intr_lock); 1292 } 1293 } 1294 1295 void 1296 ehci_childdet(device_t self, device_t child) 1297 { 1298 struct ehci_softc *sc = device_private(self); 1299 1300 KASSERT(sc->sc_child == child); 1301 sc->sc_child = NULL; 1302 } 1303 1304 int 1305 ehci_detach(struct ehci_softc *sc, int flags) 1306 { 1307 int rv = 0; 1308 1309 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1310 1311 if (sc->sc_child != NULL) 1312 rv = config_detach(sc->sc_child, flags); 1313 1314 if (rv != 0) 1315 return rv; 1316 1317 callout_halt(&sc->sc_tmo_intrlist, NULL); 1318 callout_destroy(&sc->sc_tmo_intrlist); 1319 1320 /* XXX free other data structures XXX */ 1321 if (sc->sc_softitds) 1322 kmem_free(sc->sc_softitds, 1323 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1324 cv_destroy(&sc->sc_doorbell); 1325 cv_destroy(&sc->sc_softwake_cv); 1326 1327 #if 0 1328 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1329 1330 softint_disestablish(sc->sc_doorbell_si); 1331 softint_disestablish(sc->sc_pcd_si); 1332 1333 mutex_destroy(&sc->sc_lock); 1334 mutex_destroy(&sc->sc_intr_lock); 1335 #endif 1336 1337 pool_cache_destroy(sc->sc_xferpool); 1338 1339 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1340 1341 return rv; 1342 } 1343 1344 1345 int 1346 ehci_activate(device_t self, enum devact act) 1347 { 1348 struct ehci_softc *sc = device_private(self); 1349 1350 switch (act) { 1351 case DVACT_DEACTIVATE: 1352 sc->sc_dying = 1; 1353 return 0; 1354 default: 1355 return EOPNOTSUPP; 1356 } 1357 } 1358 1359 /* 1360 * Handle suspend/resume. 1361 * 1362 * We need to switch to polling mode here, because this routine is 1363 * called from an interrupt context. This is all right since we 1364 * are almost suspended anyway. 1365 * 1366 * Note that this power handler isn't to be registered directly; the 1367 * bus glue needs to call out to it. 1368 */ 1369 bool 1370 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1371 { 1372 ehci_softc_t *sc = device_private(dv); 1373 int i; 1374 uint32_t cmd, hcr; 1375 1376 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1377 1378 mutex_spin_enter(&sc->sc_intr_lock); 1379 sc->sc_bus.ub_usepolling++; 1380 mutex_spin_exit(&sc->sc_intr_lock); 1381 1382 for (i = 1; i <= sc->sc_noport; i++) { 1383 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1384 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1385 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1386 } 1387 1388 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1389 1390 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1391 EOWRITE4(sc, EHCI_USBCMD, cmd); 1392 1393 for (i = 0; i < 100; i++) { 1394 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1395 if (hcr == 0) 1396 break; 1397 1398 usb_delay_ms(&sc->sc_bus, 1); 1399 } 1400 if (hcr != 0) 1401 printf("%s: reset timeout\n", device_xname(dv)); 1402 1403 cmd &= ~EHCI_CMD_RS; 1404 EOWRITE4(sc, EHCI_USBCMD, cmd); 1405 1406 for (i = 0; i < 100; i++) { 1407 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1408 if (hcr == EHCI_STS_HCH) 1409 break; 1410 1411 usb_delay_ms(&sc->sc_bus, 1); 1412 } 1413 if (hcr != EHCI_STS_HCH) 1414 printf("%s: config timeout\n", device_xname(dv)); 1415 1416 mutex_spin_enter(&sc->sc_intr_lock); 1417 sc->sc_bus.ub_usepolling--; 1418 mutex_spin_exit(&sc->sc_intr_lock); 1419 1420 return true; 1421 } 1422 1423 bool 1424 ehci_resume(device_t dv, const pmf_qual_t *qual) 1425 { 1426 ehci_softc_t *sc = device_private(dv); 1427 int i; 1428 uint32_t cmd, hcr; 1429 1430 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1431 1432 /* restore things in case the bios sucks */ 1433 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1434 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1435 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1436 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1437 1438 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1439 1440 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1441 1442 hcr = 0; 1443 for (i = 1; i <= sc->sc_noport; i++) { 1444 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1445 if ((cmd & EHCI_PS_PO) == 0 && 1446 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1447 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1448 hcr = 1; 1449 } 1450 } 1451 1452 if (hcr) { 1453 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1454 1455 for (i = 1; i <= sc->sc_noport; i++) { 1456 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1457 if ((cmd & EHCI_PS_PO) == 0 && 1458 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1459 EOWRITE4(sc, EHCI_PORTSC(i), 1460 cmd & ~EHCI_PS_FPR); 1461 } 1462 } 1463 1464 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1465 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1466 1467 for (i = 0; i < 100; i++) { 1468 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1469 if (hcr != EHCI_STS_HCH) 1470 break; 1471 1472 usb_delay_ms(&sc->sc_bus, 1); 1473 } 1474 if (hcr == EHCI_STS_HCH) 1475 printf("%s: config timeout\n", device_xname(dv)); 1476 1477 return true; 1478 } 1479 1480 /* 1481 * Shut down the controller when the system is going down. 1482 */ 1483 bool 1484 ehci_shutdown(device_t self, int flags) 1485 { 1486 ehci_softc_t *sc = device_private(self); 1487 1488 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1489 1490 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1491 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1492 return true; 1493 } 1494 1495 Static usbd_xfer_handle 1496 ehci_allocx(struct usbd_bus *bus) 1497 { 1498 struct ehci_softc *sc = bus->ub_hcpriv; 1499 usbd_xfer_handle xfer; 1500 1501 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1502 if (xfer != NULL) { 1503 memset(xfer, 0, sizeof(struct ehci_xfer)); 1504 #ifdef DIAGNOSTIC 1505 EXFER(xfer)->ex_isdone = 1; 1506 xfer->ux_state = XFER_BUSY; 1507 #endif 1508 } 1509 return xfer; 1510 } 1511 1512 Static void 1513 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1514 { 1515 struct ehci_softc *sc = bus->ub_hcpriv; 1516 1517 #ifdef DIAGNOSTIC 1518 if (xfer->ux_state != XFER_BUSY) { 1519 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1520 xfer->ux_state); 1521 } 1522 xfer->ux_state = XFER_FREE; 1523 if (!EXFER(xfer)->ex_isdone) { 1524 printf("ehci_freex: !isdone\n"); 1525 } 1526 #endif 1527 pool_cache_put(sc->sc_xferpool, xfer); 1528 } 1529 1530 Static void 1531 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1532 { 1533 struct ehci_softc *sc = bus->ub_hcpriv; 1534 1535 *lock = &sc->sc_lock; 1536 } 1537 1538 Static void 1539 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1540 { 1541 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1542 1543 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1544 1545 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1546 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1547 #ifdef EHCI_DEBUG 1548 if (ehcidebug) 1549 usbd_dump_pipe(pipe); 1550 #endif 1551 epipe->nexttoggle = 0; 1552 } 1553 1554 Static void 1555 ehci_noop(usbd_pipe_handle pipe) 1556 { 1557 } 1558 1559 #ifdef EHCI_DEBUG 1560 /* 1561 * Unused function - this is meant to be called from a kernel 1562 * debugger. 1563 */ 1564 void 1565 ehci_dump(void) 1566 { 1567 ehci_softc_t *sc = theehci; 1568 int i; 1569 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1570 EOREAD4(sc, EHCI_USBCMD), 1571 EOREAD4(sc, EHCI_USBSTS), 1572 EOREAD4(sc, EHCI_USBINTR)); 1573 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1574 EOREAD4(sc, EHCI_FRINDEX), 1575 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1576 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1577 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1578 for (i = 1; i <= sc->sc_noport; i++) 1579 printf("port %d status=0x%08x\n", i, 1580 EOREAD4(sc, EHCI_PORTSC(i))); 1581 } 1582 1583 Static void 1584 ehci_dump_regs(ehci_softc_t *sc) 1585 { 1586 int i; 1587 1588 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1589 1590 USBHIST_LOG(ehcidebug, 1591 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1592 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1593 EOREAD4(sc, EHCI_USBINTR), 0); 1594 USBHIST_LOG(ehcidebug, 1595 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1596 "async = 0x%08x", 1597 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1598 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1599 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1600 for (i = 1; i <= sc->sc_noport; i += 2) { 1601 if (i == sc->sc_noport) { 1602 USBHIST_LOG(ehcidebug, 1603 "port %d status = 0x%08x", i, 1604 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1605 } else { 1606 USBHIST_LOG(ehcidebug, 1607 "port %d status = 0x%08x port %d status = 0x%08x", 1608 i, EOREAD4(sc, EHCI_PORTSC(i)), 1609 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1610 } 1611 } 1612 } 1613 1614 #ifdef EHCI_DEBUG 1615 #define ehci_dump_link(link, type) do { \ 1616 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1617 link, \ 1618 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1619 if (type) { \ 1620 USBHIST_LOG(ehcidebug, \ 1621 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1622 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1623 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1624 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1625 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1626 } \ 1627 } while(0) 1628 #else 1629 #define ehci_dump_link(link, type) 1630 #endif 1631 1632 Static void 1633 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1634 { 1635 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1636 int i; 1637 uint32_t stop = 0; 1638 1639 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1640 ehci_dump_sqtd(sqtd); 1641 usb_syncmem(&sqtd->dma, 1642 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1643 sizeof(sqtd->qtd), 1644 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1645 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1646 usb_syncmem(&sqtd->dma, 1647 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1648 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1649 } 1650 if (sqtd) 1651 USBHIST_LOG(ehcidebug, 1652 "dump aborted, too many TDs", 0, 0, 0, 0); 1653 } 1654 1655 Static void 1656 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1657 { 1658 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1659 1660 usb_syncmem(&sqtd->dma, sqtd->offs, 1661 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1662 1663 USBHIST_LOGN(ehcidebug, 10, 1664 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1665 ehci_dump_qtd(&sqtd->qtd); 1666 1667 usb_syncmem(&sqtd->dma, sqtd->offs, 1668 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1669 } 1670 1671 Static void 1672 ehci_dump_qtd(ehci_qtd_t *qtd) 1673 { 1674 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1675 1676 #ifdef USBHIST 1677 uint32_t s = le32toh(qtd->qtd_status); 1678 #endif 1679 1680 USBHIST_LOGN(ehcidebug, 10, 1681 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1682 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1683 USBHIST_LOGN(ehcidebug, 10, 1684 " toggle = %d ioc = %d bytes = %#x " 1685 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1686 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1687 USBHIST_LOGN(ehcidebug, 10, 1688 " cerr = %d pid = %d stat = %x", 1689 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1690 0); 1691 USBHIST_LOGN(ehcidebug, 10, 1692 "active =%d halted=%d buferr=%d babble=%d", 1693 s & EHCI_QTD_ACTIVE ? 1 : 0, 1694 s & EHCI_QTD_HALTED ? 1 : 0, 1695 s & EHCI_QTD_BUFERR ? 1 : 0, 1696 s & EHCI_QTD_BABBLE ? 1 : 0); 1697 USBHIST_LOGN(ehcidebug, 10, 1698 "xacterr=%d missed=%d split =%d ping =%d", 1699 s & EHCI_QTD_XACTERR ? 1 : 0, 1700 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1701 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1702 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1703 USBHIST_LOGN(ehcidebug, 10, 1704 "buffer[0] = %#x buffer[1] = %#x " 1705 "buffer[2] = %#x buffer[3] = %#x", 1706 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1707 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1708 USBHIST_LOGN(ehcidebug, 10, 1709 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1710 } 1711 1712 Static void 1713 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1714 { 1715 #ifdef USBHIST 1716 ehci_qh_t *qh = &sqh->qh; 1717 ehci_link_t link; 1718 #endif 1719 uint32_t endp, endphub; 1720 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1721 1722 usb_syncmem(&sqh->dma, sqh->offs, 1723 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1724 1725 USBHIST_LOGN(ehcidebug, 10, 1726 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1727 link = le32toh(qh->qh_link); 1728 ehci_dump_link(link, true); 1729 1730 endp = le32toh(qh->qh_endp); 1731 USBHIST_LOGN(ehcidebug, 10, 1732 " endp = %#x", endp, 0, 0, 0); 1733 USBHIST_LOGN(ehcidebug, 10, 1734 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1735 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1736 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1737 USBHIST_LOGN(ehcidebug, 10, 1738 " dtc = %d hrecl = %d", 1739 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1740 USBHIST_LOGN(ehcidebug, 10, 1741 " ctl = %d nrl = %d mpl = %#x(%d)", 1742 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1743 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1744 1745 endphub = le32toh(qh->qh_endphub); 1746 USBHIST_LOGN(ehcidebug, 10, 1747 " endphub = %#x", endphub, 0, 0, 0); 1748 USBHIST_LOGN(ehcidebug, 10, 1749 " smask = 0x%02x cmask = 0x%02x", 1750 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1751 USBHIST_LOGN(ehcidebug, 10, 1752 " huba = 0x%02x port = %d mult = %d", 1753 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1754 EHCI_QH_GET_MULT(endphub), 0); 1755 1756 link = le32toh(qh->qh_curqtd); 1757 ehci_dump_link(link, false); 1758 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1759 ehci_dump_qtd(&qh->qh_qtd); 1760 1761 usb_syncmem(&sqh->dma, sqh->offs, 1762 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1763 } 1764 1765 Static void 1766 ehci_dump_itd(struct ehci_soft_itd *itd) 1767 { 1768 ehci_isoc_trans_t t; 1769 ehci_isoc_bufr_ptr_t b, b2, b3; 1770 int i; 1771 1772 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1773 1774 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1775 0, 0); 1776 1777 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1778 t = le32toh(itd->itd.itd_ctl[i]); 1779 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1780 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1781 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1782 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1783 EHCI_ITD_GET_OFFS(t), 0); 1784 } 1785 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1786 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1787 USBHIST_LOG(ehcidebug, " %x", 1788 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1789 1790 b = le32toh(itd->itd.itd_bufr[0]); 1791 b2 = le32toh(itd->itd.itd_bufr[1]); 1792 b3 = le32toh(itd->itd.itd_bufr[2]); 1793 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1794 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1795 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1796 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1797 } 1798 1799 Static void 1800 ehci_dump_sitd(struct ehci_soft_itd *itd) 1801 { 1802 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1803 1804 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1805 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1806 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1807 itd->xfer_next, itd->physaddr, itd->slot, 0); 1808 } 1809 1810 Static void 1811 ehci_dump_exfer(struct ehci_xfer *ex) 1812 { 1813 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1814 1815 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1816 ex, ex->ex_sqtdstart, ex->ex_sqtdend, 0); 1817 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1818 ex->ex_itdstart, ex->ex_itdend, ex->ex_isdone, 0); 1819 } 1820 #endif 1821 1822 Static usbd_status 1823 ehci_open(usbd_pipe_handle pipe) 1824 { 1825 usbd_device_handle dev = pipe->up_dev; 1826 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1827 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1828 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1829 uint8_t addr = dev->ud_addr; 1830 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1831 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1832 ehci_soft_qh_t *sqh; 1833 usbd_status err; 1834 int ival, speed, naks; 1835 int hshubaddr, hshubport; 1836 1837 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1838 1839 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1840 pipe, addr, ed->bEndpointAddress, rhaddr); 1841 1842 if (dev->ud_myhsport) { 1843 /* 1844 * When directly attached FS/LS device while doing embedded 1845 * transaction translations and we are the hub, set the hub 1846 * address to 0 (us). 1847 */ 1848 if (!(sc->sc_flags & EHCIF_ETTF) 1849 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1850 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1851 } else { 1852 hshubaddr = 0; 1853 } 1854 hshubport = dev->ud_myhsport->up_portno; 1855 } else { 1856 hshubaddr = 0; 1857 hshubport = 0; 1858 } 1859 1860 if (sc->sc_dying) 1861 return USBD_IOERROR; 1862 1863 /* toggle state needed for bulk endpoints */ 1864 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1865 1866 if (addr == rhaddr) { 1867 switch (ed->bEndpointAddress) { 1868 case USB_CONTROL_ENDPOINT: 1869 pipe->up_methods = &roothub_ctrl_methods; 1870 break; 1871 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1872 pipe->up_methods = &ehci_root_intr_methods; 1873 break; 1874 default: 1875 USBHIST_LOG(ehcidebug, 1876 "bad bEndpointAddress 0x%02x", 1877 ed->bEndpointAddress, 0, 0, 0); 1878 return USBD_INVAL; 1879 } 1880 return USBD_NORMAL_COMPLETION; 1881 } 1882 1883 /* XXX All this stuff is only valid for async. */ 1884 switch (dev->ud_speed) { 1885 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1886 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1887 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1888 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1889 } 1890 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1891 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1892 hshubaddr, hshubport, 0, 0); 1893 return USBD_INVAL; 1894 } 1895 1896 /* 1897 * For interrupt transfer, nak throttling must be disabled, but for 1898 * the other transfer type, nak throttling should be enabled from the 1899 * viewpoint that avoids the memory thrashing. 1900 */ 1901 naks = (xfertype == UE_INTERRUPT) ? 0 1902 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1903 1904 /* Allocate sqh for everything, save isoc xfers */ 1905 if (xfertype != UE_ISOCHRONOUS) { 1906 sqh = ehci_alloc_sqh(sc); 1907 if (sqh == NULL) 1908 return USBD_NOMEM; 1909 /* qh_link filled when the QH is added */ 1910 sqh->qh.qh_endp = htole32( 1911 EHCI_QH_SET_ADDR(addr) | 1912 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1913 EHCI_QH_SET_EPS(speed) | 1914 EHCI_QH_DTC | 1915 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1916 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1917 EHCI_QH_CTL : 0) | 1918 EHCI_QH_SET_NRL(naks) 1919 ); 1920 sqh->qh.qh_endphub = htole32( 1921 EHCI_QH_SET_MULT(1) | 1922 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1923 ); 1924 if (speed != EHCI_QH_SPEED_HIGH) 1925 sqh->qh.qh_endphub |= htole32( 1926 EHCI_QH_SET_PORT(hshubport) | 1927 EHCI_QH_SET_HUBA(hshubaddr) | 1928 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1929 ); 1930 sqh->qh.qh_curqtd = EHCI_NULL; 1931 /* Fill the overlay qTD */ 1932 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1933 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1934 sqh->qh.qh_qtd.qtd_status = htole32(0); 1935 1936 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1937 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1938 epipe->sqh = sqh; 1939 } else { 1940 sqh = NULL; 1941 } /*xfertype == UE_ISOC*/ 1942 1943 switch (xfertype) { 1944 case UE_CONTROL: 1945 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1946 0, &epipe->u.ctl.reqdma); 1947 #ifdef EHCI_DEBUG 1948 if (err) 1949 printf("ehci_open: usb_allocmem()=%d\n", err); 1950 #endif 1951 if (err) 1952 goto bad; 1953 pipe->up_methods = &ehci_device_ctrl_methods; 1954 mutex_enter(&sc->sc_lock); 1955 ehci_add_qh(sc, sqh, sc->sc_async_head); 1956 mutex_exit(&sc->sc_lock); 1957 break; 1958 case UE_BULK: 1959 pipe->up_methods = &ehci_device_bulk_methods; 1960 mutex_enter(&sc->sc_lock); 1961 ehci_add_qh(sc, sqh, sc->sc_async_head); 1962 mutex_exit(&sc->sc_lock); 1963 break; 1964 case UE_INTERRUPT: 1965 pipe->up_methods = &ehci_device_intr_methods; 1966 ival = pipe->up_interval; 1967 if (ival == USBD_DEFAULT_INTERVAL) { 1968 if (speed == EHCI_QH_SPEED_HIGH) { 1969 if (ed->bInterval > 16) { 1970 /* 1971 * illegal with high-speed, but there 1972 * were documentation bugs in the spec, 1973 * so be generous 1974 */ 1975 ival = 256; 1976 } else 1977 ival = (1 << (ed->bInterval - 1)) / 8; 1978 } else 1979 ival = ed->bInterval; 1980 } 1981 err = ehci_device_setintr(sc, sqh, ival); 1982 if (err) 1983 goto bad; 1984 break; 1985 case UE_ISOCHRONOUS: 1986 if (speed == EHCI_QH_SPEED_HIGH) 1987 pipe->up_methods = &ehci_device_isoc_methods; 1988 else 1989 pipe->up_methods = &ehci_device_fs_isoc_methods; 1990 if (ed->bInterval == 0 || ed->bInterval > 16) { 1991 printf("ehci: opening pipe with invalid bInterval\n"); 1992 err = USBD_INVAL; 1993 goto bad; 1994 } 1995 if (UGETW(ed->wMaxPacketSize) == 0) { 1996 printf("ehci: zero length endpoint open request\n"); 1997 err = USBD_INVAL; 1998 goto bad; 1999 } 2000 epipe->u.isoc.next_frame = 0; 2001 epipe->u.isoc.cur_xfers = 0; 2002 break; 2003 default: 2004 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2005 err = USBD_INVAL; 2006 goto bad; 2007 } 2008 return USBD_NORMAL_COMPLETION; 2009 2010 bad: 2011 if (sqh != NULL) 2012 ehci_free_sqh(sc, sqh); 2013 return err; 2014 } 2015 2016 /* 2017 * Add an ED to the schedule. Called with USB lock held. 2018 */ 2019 Static void 2020 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2021 { 2022 2023 KASSERT(mutex_owned(&sc->sc_lock)); 2024 2025 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2026 2027 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2028 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2029 2030 sqh->next = head->next; 2031 sqh->qh.qh_link = head->qh.qh_link; 2032 2033 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2034 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2035 2036 head->next = sqh; 2037 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2038 2039 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2040 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2041 2042 #ifdef EHCI_DEBUG 2043 ehci_dump_sqh(sqh); 2044 #endif 2045 } 2046 2047 /* 2048 * Remove an ED from the schedule. Called with USB lock held. 2049 */ 2050 Static void 2051 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2052 { 2053 ehci_soft_qh_t *p; 2054 2055 KASSERT(mutex_owned(&sc->sc_lock)); 2056 2057 /* XXX */ 2058 for (p = head; p != NULL && p->next != sqh; p = p->next) 2059 ; 2060 if (p == NULL) 2061 panic("ehci_rem_qh: ED not found"); 2062 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2063 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2064 p->next = sqh->next; 2065 p->qh.qh_link = sqh->qh.qh_link; 2066 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2067 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2068 2069 ehci_sync_hc(sc); 2070 } 2071 2072 Static void 2073 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2074 { 2075 int i; 2076 uint32_t status; 2077 2078 /* Save toggle bit and ping status. */ 2079 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2080 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2081 status = sqh->qh.qh_qtd.qtd_status & 2082 htole32(EHCI_QTD_TOGGLE_MASK | 2083 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2084 /* Set HALTED to make hw leave it alone. */ 2085 sqh->qh.qh_qtd.qtd_status = 2086 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2087 usb_syncmem(&sqh->dma, 2088 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2089 sizeof(sqh->qh.qh_qtd.qtd_status), 2090 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2091 sqh->qh.qh_curqtd = 0; 2092 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2093 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2094 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2095 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2096 sqh->sqtd = sqtd; 2097 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2098 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2099 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2100 sqh->qh.qh_qtd.qtd_status = status; 2101 usb_syncmem(&sqh->dma, 2102 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2103 sizeof(sqh->qh.qh_qtd.qtd_status), 2104 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2105 } 2106 2107 /* 2108 * Ensure that the HC has released all references to the QH. We do this 2109 * by asking for a Async Advance Doorbell interrupt and then we wait for 2110 * the interrupt. 2111 * To make this easier we first obtain exclusive use of the doorbell. 2112 */ 2113 Static void 2114 ehci_sync_hc(ehci_softc_t *sc) 2115 { 2116 int error __diagused; 2117 2118 KASSERT(mutex_owned(&sc->sc_lock)); 2119 2120 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2121 2122 if (sc->sc_dying) { 2123 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2124 return; 2125 } 2126 /* ask for doorbell */ 2127 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2128 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2129 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2130 2131 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2132 2133 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2134 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2135 #ifdef DIAGNOSTIC 2136 if (error) 2137 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2138 #endif 2139 } 2140 2141 Static void 2142 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2143 { 2144 struct ehci_soft_itd *itd, *prev; 2145 2146 prev = NULL; 2147 2148 if (exfer->ex_itdstart == NULL || exfer->ex_itdend == NULL) 2149 panic("ehci isoc xfer being freed, but with no itd chain\n"); 2150 2151 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2152 prev = itd->u.frame_list.prev; 2153 /* Unlink itd from hardware chain, or frame array */ 2154 if (prev == NULL) { /* We're at the table head */ 2155 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2156 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2157 usb_syncmem(&sc->sc_fldma, 2158 sizeof(ehci_link_t) * itd->slot, 2159 sizeof(ehci_link_t), 2160 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2161 2162 if (itd->u.frame_list.next != NULL) 2163 itd->u.frame_list.next->u.frame_list.prev = NULL; 2164 } else { 2165 /* XXX this part is untested... */ 2166 prev->itd.itd_next = itd->itd.itd_next; 2167 usb_syncmem(&itd->dma, 2168 itd->offs + offsetof(ehci_itd_t, itd_next), 2169 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2170 2171 prev->u.frame_list.next = itd->u.frame_list.next; 2172 if (itd->u.frame_list.next != NULL) 2173 itd->u.frame_list.next->u.frame_list.prev = prev; 2174 } 2175 } 2176 2177 prev = NULL; 2178 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2179 if (prev != NULL) 2180 ehci_free_itd(sc, prev); 2181 prev = itd; 2182 } 2183 if (prev) 2184 ehci_free_itd(sc, prev); 2185 exfer->ex_itdstart = NULL; 2186 exfer->ex_itdend = NULL; 2187 } 2188 2189 Static void 2190 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2191 { 2192 struct ehci_soft_sitd *sitd, *prev; 2193 2194 prev = NULL; 2195 2196 if (exfer->ex_sitdstart == NULL || exfer->ex_sitdend == NULL) 2197 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2198 2199 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2200 prev = sitd->u.frame_list.prev; 2201 /* Unlink sitd from hardware chain, or frame array */ 2202 if (prev == NULL) { /* We're at the table head */ 2203 sc->sc_softsitds[sitd->slot] = sitd->u.frame_list.next; 2204 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2205 usb_syncmem(&sc->sc_fldma, 2206 sizeof(ehci_link_t) * sitd->slot, 2207 sizeof(ehci_link_t), 2208 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2209 2210 if (sitd->u.frame_list.next != NULL) 2211 sitd->u.frame_list.next->u.frame_list.prev = NULL; 2212 } else { 2213 /* XXX this part is untested... */ 2214 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2215 usb_syncmem(&sitd->dma, 2216 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2217 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2218 2219 prev->u.frame_list.next = sitd->u.frame_list.next; 2220 if (sitd->u.frame_list.next != NULL) 2221 sitd->u.frame_list.next->u.frame_list.prev = prev; 2222 } 2223 } 2224 2225 prev = NULL; 2226 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2227 if (prev != NULL) 2228 ehci_free_sitd(sc, prev); 2229 prev = sitd; 2230 } 2231 if (prev) 2232 ehci_free_sitd(sc, prev); 2233 exfer->ex_sitdstart = NULL; 2234 exfer->ex_sitdend = NULL; 2235 } 2236 2237 /***********/ 2238 2239 Static int 2240 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2241 void *buf, int buflen) 2242 { 2243 ehci_softc_t *sc = bus->ub_hcpriv; 2244 usb_hub_descriptor_t hubd; 2245 usb_port_status_t ps; 2246 uint16_t len, value, index; 2247 int l, totlen = 0; 2248 int port, i; 2249 uint32_t v; 2250 2251 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2252 2253 if (sc->sc_dying) 2254 return -1; 2255 2256 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2257 req->bmRequestType, req->bRequest, 0, 0); 2258 2259 len = UGETW(req->wLength); 2260 value = UGETW(req->wValue); 2261 index = UGETW(req->wIndex); 2262 2263 #define C(x,y) ((x) | ((y) << 8)) 2264 switch (C(req->bRequest, req->bmRequestType)) { 2265 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2266 if (len == 0) 2267 break; 2268 switch (value) { 2269 case C(0, UDESC_DEVICE): { 2270 usb_device_descriptor_t devd; 2271 totlen = min(buflen, sizeof(devd)); 2272 memcpy(&devd, buf, totlen); 2273 USETW(devd.idVendor, sc->sc_id_vendor); 2274 memcpy(buf, &devd, totlen); 2275 break; 2276 2277 } 2278 #define sd ((usb_string_descriptor_t *)buf) 2279 case C(1, UDESC_STRING): 2280 /* Vendor */ 2281 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2282 break; 2283 case C(2, UDESC_STRING): 2284 /* Product */ 2285 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2286 break; 2287 #undef sd 2288 default: 2289 /* default from usbroothub */ 2290 return buflen; 2291 } 2292 break; 2293 2294 /* Hub requests */ 2295 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2296 break; 2297 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2298 USBHIST_LOG(ehcidebug, 2299 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2300 0, 0); 2301 if (index < 1 || index > sc->sc_noport) { 2302 return -1; 2303 } 2304 port = EHCI_PORTSC(index); 2305 v = EOREAD4(sc, port); 2306 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2307 v &= ~EHCI_PS_CLEAR; 2308 switch (value) { 2309 case UHF_PORT_ENABLE: 2310 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2311 break; 2312 case UHF_PORT_SUSPEND: 2313 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2314 break; 2315 v &= ~EHCI_PS_SUSP; 2316 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2317 /* see USB2 spec ch. 7.1.7.7 */ 2318 usb_delay_ms(&sc->sc_bus, 20); 2319 EOWRITE4(sc, port, v); 2320 usb_delay_ms(&sc->sc_bus, 2); 2321 #ifdef DEBUG 2322 v = EOREAD4(sc, port); 2323 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2324 printf("ehci: resume failed: %x\n", v); 2325 #endif 2326 break; 2327 case UHF_PORT_POWER: 2328 if (sc->sc_hasppc) 2329 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2330 break; 2331 case UHF_PORT_TEST: 2332 USBHIST_LOG(ehcidebug, "clear port test " 2333 "%d", index, 0, 0, 0); 2334 break; 2335 case UHF_PORT_INDICATOR: 2336 USBHIST_LOG(ehcidebug, "clear port ind " 2337 "%d", index, 0, 0, 0); 2338 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2339 break; 2340 case UHF_C_PORT_CONNECTION: 2341 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2342 break; 2343 case UHF_C_PORT_ENABLE: 2344 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2345 break; 2346 case UHF_C_PORT_SUSPEND: 2347 /* how? */ 2348 break; 2349 case UHF_C_PORT_OVER_CURRENT: 2350 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2351 break; 2352 case UHF_C_PORT_RESET: 2353 sc->sc_isreset[index] = 0; 2354 break; 2355 default: 2356 return -1; 2357 } 2358 #if 0 2359 switch(value) { 2360 case UHF_C_PORT_CONNECTION: 2361 case UHF_C_PORT_ENABLE: 2362 case UHF_C_PORT_SUSPEND: 2363 case UHF_C_PORT_OVER_CURRENT: 2364 case UHF_C_PORT_RESET: 2365 default: 2366 break; 2367 } 2368 #endif 2369 break; 2370 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2371 if (len == 0) 2372 break; 2373 if ((value & 0xff) != 0) { 2374 return -1; 2375 } 2376 totlen = min(buflen, sizeof(hubd)); 2377 memcpy(&hubd, buf, totlen); 2378 hubd.bNbrPorts = sc->sc_noport; 2379 v = EOREAD4(sc, EHCI_HCSPARAMS); 2380 USETW(hubd.wHubCharacteristics, 2381 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2382 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2383 ? UHD_PORT_IND : 0); 2384 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2385 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2386 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2387 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2388 totlen = min(totlen, hubd.bDescLength); 2389 memcpy(buf, &hubd, totlen); 2390 break; 2391 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2392 if (len != 4) { 2393 return -1; 2394 } 2395 memset(buf, 0, len); /* ? XXX */ 2396 totlen = len; 2397 break; 2398 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2399 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2400 if (index < 1 || index > sc->sc_noport) { 2401 return -1; 2402 } 2403 if (len != 4) { 2404 return -1; 2405 } 2406 v = EOREAD4(sc, EHCI_PORTSC(index)); 2407 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2408 2409 i = UPS_HIGH_SPEED; 2410 if (sc->sc_flags & EHCIF_ETTF) { 2411 /* 2412 * If we are doing embedded transaction translation, 2413 * then directly attached LS/FS devices are reset by 2414 * the EHCI controller itself. PSPD is encoded 2415 * the same way as in USBSTATUS. 2416 */ 2417 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2418 } 2419 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2420 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2421 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2422 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2423 if (v & EHCI_PS_PR) i |= UPS_RESET; 2424 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2425 if (sc->sc_vendor_port_status) 2426 i = sc->sc_vendor_port_status(sc, v, i); 2427 USETW(ps.wPortStatus, i); 2428 i = 0; 2429 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2430 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2431 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2432 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2433 USETW(ps.wPortChange, i); 2434 totlen = min(len, sizeof(ps)); 2435 memcpy(buf, &ps, totlen); 2436 break; 2437 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2438 return -1; 2439 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2440 break; 2441 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2442 if (index < 1 || index > sc->sc_noport) { 2443 return -1; 2444 } 2445 port = EHCI_PORTSC(index); 2446 v = EOREAD4(sc, port); 2447 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2448 v &= ~EHCI_PS_CLEAR; 2449 switch(value) { 2450 case UHF_PORT_ENABLE: 2451 EOWRITE4(sc, port, v | EHCI_PS_PE); 2452 break; 2453 case UHF_PORT_SUSPEND: 2454 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2455 break; 2456 case UHF_PORT_RESET: 2457 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2458 if (EHCI_PS_IS_LOWSPEED(v) 2459 && sc->sc_ncomp > 0 2460 && !(sc->sc_flags & EHCIF_ETTF)) { 2461 /* 2462 * Low speed device on non-ETTF controller or 2463 * unaccompanied controller, give up ownership. 2464 */ 2465 ehci_disown(sc, index, 1); 2466 break; 2467 } 2468 /* Start reset sequence. */ 2469 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2470 EOWRITE4(sc, port, v | EHCI_PS_PR); 2471 /* Wait for reset to complete. */ 2472 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2473 if (sc->sc_dying) { 2474 return -1; 2475 } 2476 /* 2477 * An embedded transaction translator will automatically 2478 * terminate the reset sequence so there's no need to 2479 * it. 2480 */ 2481 v = EOREAD4(sc, port); 2482 if (v & EHCI_PS_PR) { 2483 /* Terminate reset sequence. */ 2484 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2485 /* Wait for HC to complete reset. */ 2486 usb_delay_ms(&sc->sc_bus, 2487 EHCI_PORT_RESET_COMPLETE); 2488 if (sc->sc_dying) { 2489 return -1; 2490 } 2491 } 2492 2493 v = EOREAD4(sc, port); 2494 USBHIST_LOG(ehcidebug, 2495 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2496 if (v & EHCI_PS_PR) { 2497 printf("%s: port reset timeout\n", 2498 device_xname(sc->sc_dev)); 2499 return USBD_TIMEOUT; 2500 } 2501 if (!(v & EHCI_PS_PE)) { 2502 /* Not a high speed device, give up ownership.*/ 2503 ehci_disown(sc, index, 0); 2504 break; 2505 } 2506 sc->sc_isreset[index] = 1; 2507 USBHIST_LOG(ehcidebug, 2508 "ehci port %d reset, status = 0x%08x", index, v, 0, 2509 0); 2510 break; 2511 case UHF_PORT_POWER: 2512 USBHIST_LOG(ehcidebug, 2513 "set port power %d (has PPC = %d)", index, 2514 sc->sc_hasppc, 0, 0); 2515 if (sc->sc_hasppc) 2516 EOWRITE4(sc, port, v | EHCI_PS_PP); 2517 break; 2518 case UHF_PORT_TEST: 2519 USBHIST_LOG(ehcidebug, "set port test %d", 2520 index, 0, 0, 0); 2521 break; 2522 case UHF_PORT_INDICATOR: 2523 USBHIST_LOG(ehcidebug, "set port ind %d", 2524 index, 0, 0, 0); 2525 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2526 break; 2527 default: 2528 return -1; 2529 } 2530 break; 2531 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2532 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2533 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2534 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2535 break; 2536 default: 2537 /* default from usbroothub */ 2538 return buflen; 2539 } 2540 2541 return totlen; 2542 } 2543 2544 Static void 2545 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2546 { 2547 int port; 2548 uint32_t v; 2549 2550 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2551 2552 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2553 #ifdef DIAGNOSTIC 2554 if (sc->sc_npcomp != 0) { 2555 int i = (index-1) / sc->sc_npcomp; 2556 if (i >= sc->sc_ncomp) 2557 printf("%s: strange port\n", 2558 device_xname(sc->sc_dev)); 2559 else 2560 printf("%s: handing over %s speed device on " 2561 "port %d to %s\n", 2562 device_xname(sc->sc_dev), 2563 lowspeed ? "low" : "full", 2564 index, device_xname(sc->sc_comps[i])); 2565 } else { 2566 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2567 } 2568 #endif 2569 port = EHCI_PORTSC(index); 2570 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2571 EOWRITE4(sc, port, v | EHCI_PS_PO); 2572 } 2573 2574 Static usbd_status 2575 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2576 { 2577 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2578 usbd_status err; 2579 2580 /* Insert last in queue. */ 2581 mutex_enter(&sc->sc_lock); 2582 err = usb_insert_transfer(xfer); 2583 mutex_exit(&sc->sc_lock); 2584 if (err) 2585 return err; 2586 2587 /* Pipe isn't running, start first */ 2588 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2589 } 2590 2591 Static usbd_status 2592 ehci_root_intr_start(usbd_xfer_handle xfer) 2593 { 2594 usbd_pipe_handle pipe = xfer->ux_pipe; 2595 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2596 2597 if (sc->sc_dying) 2598 return USBD_IOERROR; 2599 2600 mutex_enter(&sc->sc_lock); 2601 sc->sc_intrxfer = xfer; 2602 mutex_exit(&sc->sc_lock); 2603 2604 return USBD_IN_PROGRESS; 2605 } 2606 2607 /* Abort a root interrupt request. */ 2608 Static void 2609 ehci_root_intr_abort(usbd_xfer_handle xfer) 2610 { 2611 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2612 2613 KASSERT(mutex_owned(&sc->sc_lock)); 2614 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2615 2616 sc->sc_intrxfer = NULL; 2617 2618 xfer->ux_status = USBD_CANCELLED; 2619 usb_transfer_complete(xfer); 2620 } 2621 2622 /* Close the root pipe. */ 2623 Static void 2624 ehci_root_intr_close(usbd_pipe_handle pipe) 2625 { 2626 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2627 2628 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2629 2630 KASSERT(mutex_owned(&sc->sc_lock)); 2631 2632 sc->sc_intrxfer = NULL; 2633 } 2634 2635 Static void 2636 ehci_root_intr_done(usbd_xfer_handle xfer) 2637 { 2638 xfer->ux_hcpriv = NULL; 2639 } 2640 2641 /************************/ 2642 2643 Static ehci_soft_qh_t * 2644 ehci_alloc_sqh(ehci_softc_t *sc) 2645 { 2646 ehci_soft_qh_t *sqh; 2647 usbd_status err; 2648 int i, offs; 2649 usb_dma_t dma; 2650 2651 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2652 2653 if (sc->sc_freeqhs == NULL) { 2654 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2655 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2656 EHCI_PAGE_SIZE, &dma); 2657 #ifdef EHCI_DEBUG 2658 if (err) 2659 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2660 #endif 2661 if (err) 2662 return NULL; 2663 for(i = 0; i < EHCI_SQH_CHUNK; i++) { 2664 offs = i * EHCI_SQH_SIZE; 2665 sqh = KERNADDR(&dma, offs); 2666 sqh->physaddr = DMAADDR(&dma, offs); 2667 sqh->dma = dma; 2668 sqh->offs = offs; 2669 sqh->next = sc->sc_freeqhs; 2670 sc->sc_freeqhs = sqh; 2671 } 2672 } 2673 sqh = sc->sc_freeqhs; 2674 sc->sc_freeqhs = sqh->next; 2675 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2676 sqh->next = NULL; 2677 return sqh; 2678 } 2679 2680 Static void 2681 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2682 { 2683 sqh->next = sc->sc_freeqhs; 2684 sc->sc_freeqhs = sqh; 2685 } 2686 2687 Static ehci_soft_qtd_t * 2688 ehci_alloc_sqtd(ehci_softc_t *sc) 2689 { 2690 ehci_soft_qtd_t *sqtd = NULL; 2691 usbd_status err; 2692 int i, offs; 2693 usb_dma_t dma; 2694 2695 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2696 2697 if (sc->sc_freeqtds == NULL) { 2698 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2699 2700 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2701 EHCI_PAGE_SIZE, &dma); 2702 #ifdef EHCI_DEBUG 2703 if (err) 2704 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2705 #endif 2706 if (err) 2707 goto done; 2708 2709 for(i = 0; i < EHCI_SQTD_CHUNK; i++) { 2710 offs = i * EHCI_SQTD_SIZE; 2711 sqtd = KERNADDR(&dma, offs); 2712 sqtd->physaddr = DMAADDR(&dma, offs); 2713 sqtd->dma = dma; 2714 sqtd->offs = offs; 2715 2716 sqtd->nextqtd = sc->sc_freeqtds; 2717 sc->sc_freeqtds = sqtd; 2718 } 2719 } 2720 2721 sqtd = sc->sc_freeqtds; 2722 sc->sc_freeqtds = sqtd->nextqtd; 2723 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2724 sqtd->nextqtd = NULL; 2725 sqtd->xfer = NULL; 2726 2727 done: 2728 return sqtd; 2729 } 2730 2731 Static void 2732 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2733 { 2734 2735 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2736 2737 sqtd->nextqtd = sc->sc_freeqtds; 2738 sc->sc_freeqtds = sqtd; 2739 } 2740 2741 Static usbd_status 2742 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2743 int alen, int rd, usbd_xfer_handle xfer, 2744 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2745 { 2746 ehci_soft_qtd_t *next, *cur; 2747 ehci_physaddr_t nextphys; 2748 uint32_t qtdstatus; 2749 int len, curlen, mps; 2750 int i, tog; 2751 int pages, pageoffs; 2752 bus_size_t curoffs; 2753 vaddr_t va, va_offs; 2754 usb_dma_t *dma = &xfer->ux_dmabuf; 2755 uint16_t flags = xfer->ux_flags; 2756 paddr_t a; 2757 2758 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2759 2760 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2761 2762 len = alen; 2763 qtdstatus = EHCI_QTD_ACTIVE | 2764 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2765 EHCI_QTD_SET_CERR(3) 2766 /* IOC set below */ 2767 /* BYTES set below */ 2768 ; 2769 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 2770 tog = epipe->nexttoggle; 2771 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2772 2773 cur = ehci_alloc_sqtd(sc); 2774 *sp = cur; 2775 if (cur == NULL) 2776 goto nomem; 2777 2778 usb_syncmem(dma, 0, alen, 2779 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2780 curoffs = 0; 2781 for (;;) { 2782 /* The EHCI hardware can handle at most 5 pages. */ 2783 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2784 va_offs = EHCI_PAGE_OFFSET(va_offs); 2785 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 2786 /* we can handle it in this QTD */ 2787 curlen = len - curoffs; 2788 } else { 2789 /* must use multiple TDs, fill as much as possible. */ 2790 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 2791 2792 /* the length must be a multiple of the max size */ 2793 curlen -= curlen % mps; 2794 USBHIST_LOG(ehcidebug, "multiple QTDs, " 2795 "curlen=%d", curlen, 0, 0, 0); 2796 KASSERT(curlen != 0); 2797 } 2798 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 2799 len, curlen, (size_t)curoffs, 0); 2800 2801 /* 2802 * Allocate another transfer if there's more data left, 2803 * or if force last short transfer flag is set and we're 2804 * allocating a multiple of the max packet size. 2805 */ 2806 2807 if (curoffs + curlen != len || 2808 ((curlen % mps) == 0 && !rd && curlen != 0 && 2809 (flags & USBD_FORCE_SHORT_XFER))) { 2810 next = ehci_alloc_sqtd(sc); 2811 if (next == NULL) 2812 goto nomem; 2813 nextphys = htole32(next->physaddr); 2814 } else { 2815 next = NULL; 2816 nextphys = EHCI_NULL; 2817 } 2818 2819 /* Find number of pages we'll be using, insert dma addresses */ 2820 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2821 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2822 pageoffs = EHCI_PAGE(curoffs); 2823 for (i = 0; i < pages; i++) { 2824 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2825 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2826 /* Cast up to avoid compiler warnings */ 2827 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2828 } 2829 2830 /* First buffer pointer requires a page offset to start at */ 2831 va = (vaddr_t)KERNADDR(dma, curoffs); 2832 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2833 2834 cur->nextqtd = next; 2835 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2836 cur->qtd.qtd_status = 2837 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2838 cur->xfer = xfer; 2839 cur->len = curlen; 2840 2841 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2842 (size_t)curoffs, (size_t)(curoffs + curlen), 0, 0); 2843 2844 /* 2845 * adjust the toggle based on the number of packets in this 2846 * qtd 2847 */ 2848 if (((curlen + mps - 1) / mps) & 1) { 2849 tog ^= 1; 2850 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2851 } 2852 if (next == NULL) 2853 break; 2854 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2855 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2856 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2857 if (len) 2858 curoffs += curlen; 2859 cur = next; 2860 } 2861 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2862 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2863 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2864 *ep = cur; 2865 epipe->nexttoggle = tog; 2866 2867 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 2868 *sp, *ep, 0, 0); 2869 2870 return USBD_NORMAL_COMPLETION; 2871 2872 nomem: 2873 /* XXX free chain */ 2874 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2875 return USBD_NOMEM; 2876 } 2877 2878 Static void 2879 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2880 ehci_soft_qtd_t *sqtdend) 2881 { 2882 ehci_soft_qtd_t *p; 2883 int i; 2884 2885 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2886 2887 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 2888 sqtd, sqtdend, 0, 0); 2889 2890 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2891 p = sqtd->nextqtd; 2892 ehci_free_sqtd(sc, sqtd); 2893 } 2894 } 2895 2896 Static ehci_soft_itd_t * 2897 ehci_alloc_itd(ehci_softc_t *sc) 2898 { 2899 struct ehci_soft_itd *itd, *freeitd; 2900 usbd_status err; 2901 int i, offs, frindex, previndex; 2902 usb_dma_t dma; 2903 2904 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2905 2906 mutex_enter(&sc->sc_lock); 2907 2908 /* Find an itd that wasn't freed this frame or last frame. This can 2909 * discard itds that were freed before frindex wrapped around 2910 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2911 * interrupt and fiddling with list when that happens */ 2912 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2913 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2914 2915 freeitd = NULL; 2916 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2917 if (itd == NULL) 2918 break; 2919 if (itd->slot != frindex && itd->slot != previndex) { 2920 freeitd = itd; 2921 break; 2922 } 2923 } 2924 2925 if (freeitd == NULL) { 2926 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2927 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2928 EHCI_PAGE_SIZE, &dma); 2929 2930 if (err) { 2931 USBHIST_LOG(ehcidebug, 2932 "alloc returned %d", err, 0, 0, 0); 2933 mutex_exit(&sc->sc_lock); 2934 return NULL; 2935 } 2936 2937 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2938 offs = i * EHCI_ITD_SIZE; 2939 itd = KERNADDR(&dma, offs); 2940 itd->physaddr = DMAADDR(&dma, offs); 2941 itd->dma = dma; 2942 itd->offs = offs; 2943 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2944 } 2945 freeitd = LIST_FIRST(&sc->sc_freeitds); 2946 } 2947 2948 itd = freeitd; 2949 LIST_REMOVE(itd, u.free_list); 2950 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2951 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2952 sizeof(itd->itd.itd_next), 2953 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2954 2955 itd->u.frame_list.next = NULL; 2956 itd->u.frame_list.prev = NULL; 2957 itd->xfer_next = NULL; 2958 itd->slot = 0; 2959 2960 mutex_exit(&sc->sc_lock); 2961 2962 return itd; 2963 } 2964 2965 Static ehci_soft_sitd_t * 2966 ehci_alloc_sitd(ehci_softc_t *sc) 2967 { 2968 struct ehci_soft_sitd *sitd, *freesitd; 2969 usbd_status err; 2970 int i, offs, frindex, previndex; 2971 usb_dma_t dma; 2972 2973 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2974 2975 mutex_enter(&sc->sc_lock); 2976 2977 /* Find an sitd that wasn't freed this frame or last frame. This can 2978 * discard sitds that were freed before frindex wrapped around 2979 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2980 * interrupt and fiddling with list when that happens */ 2981 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2982 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2983 2984 freesitd = NULL; 2985 LIST_FOREACH(sitd, &sc->sc_freesitds, u.free_list) { 2986 if (sitd == NULL) 2987 break; 2988 if (sitd->slot != frindex && sitd->slot != previndex) { 2989 freesitd = sitd; 2990 break; 2991 } 2992 } 2993 2994 if (freesitd == NULL) { 2995 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2996 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 2997 EHCI_PAGE_SIZE, &dma); 2998 2999 if (err) { 3000 USBHIST_LOG(ehcidebug, 3001 "alloc returned %d", err, 0, 0, 0); 3002 mutex_exit(&sc->sc_lock); 3003 return NULL; 3004 } 3005 3006 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3007 offs = i * EHCI_SITD_SIZE; 3008 sitd = KERNADDR(&dma, offs); 3009 sitd->physaddr = DMAADDR(&dma, offs); 3010 sitd->dma = dma; 3011 sitd->offs = offs; 3012 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3013 } 3014 freesitd = LIST_FIRST(&sc->sc_freesitds); 3015 } 3016 3017 sitd = freesitd; 3018 LIST_REMOVE(sitd, u.free_list); 3019 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3020 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3021 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3022 BUS_DMASYNC_PREREAD); 3023 3024 sitd->u.frame_list.next = NULL; 3025 sitd->u.frame_list.prev = NULL; 3026 sitd->xfer_next = NULL; 3027 sitd->slot = 0; 3028 3029 mutex_exit(&sc->sc_lock); 3030 3031 return sitd; 3032 } 3033 3034 Static void 3035 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3036 { 3037 3038 KASSERT(mutex_owned(&sc->sc_lock)); 3039 3040 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3041 } 3042 3043 Static void 3044 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3045 { 3046 3047 KASSERT(mutex_owned(&sc->sc_lock)); 3048 3049 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3050 } 3051 3052 /****************/ 3053 3054 /* 3055 * Close a reqular pipe. 3056 * Assumes that there are no pending transactions. 3057 */ 3058 Static void 3059 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3060 { 3061 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3062 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3063 ehci_soft_qh_t *sqh = epipe->sqh; 3064 3065 KASSERT(mutex_owned(&sc->sc_lock)); 3066 3067 ehci_rem_qh(sc, sqh, head); 3068 ehci_free_sqh(sc, epipe->sqh); 3069 } 3070 3071 /* 3072 * Abort a device request. 3073 * If this routine is called at splusb() it guarantees that the request 3074 * will be removed from the hardware scheduling and that the callback 3075 * for it will be called with USBD_CANCELLED status. 3076 * It's impossible to guarantee that the requested transfer will not 3077 * have happened since the hardware runs concurrently. 3078 * If the transaction has already happened we rely on the ordinary 3079 * interrupt processing to process it. 3080 * XXX This is most probably wrong. 3081 * XXXMRG this doesn't make sense anymore. 3082 */ 3083 Static void 3084 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3085 { 3086 #define exfer EXFER(xfer) 3087 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3088 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3089 ehci_soft_qh_t *sqh = epipe->sqh; 3090 ehci_soft_qtd_t *sqtd; 3091 ehci_physaddr_t cur; 3092 uint32_t qhstatus; 3093 int hit; 3094 int wake; 3095 3096 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3097 3098 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3099 3100 KASSERT(mutex_owned(&sc->sc_lock)); 3101 ASSERT_SLEEPABLE(); 3102 3103 if (sc->sc_dying) { 3104 /* If we're dying, just do the software part. */ 3105 xfer->ux_status = status; /* make software ignore it */ 3106 callout_stop(&xfer->ux_callout); 3107 usb_transfer_complete(xfer); 3108 return; 3109 } 3110 3111 /* 3112 * If an abort is already in progress then just wait for it to 3113 * complete and return. 3114 */ 3115 if (xfer->ux_hcflags & UXFER_ABORTING) { 3116 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3117 #ifdef DIAGNOSTIC 3118 if (status == USBD_TIMEOUT) 3119 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3120 #endif 3121 /* Override the status which might be USBD_TIMEOUT. */ 3122 xfer->ux_status = status; 3123 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3124 0, 0, 0, 0); 3125 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3126 while (xfer->ux_hcflags & UXFER_ABORTING) 3127 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3128 return; 3129 } 3130 xfer->ux_hcflags |= UXFER_ABORTING; 3131 3132 /* 3133 * Step 1: Make interrupt routine and hardware ignore xfer. 3134 */ 3135 xfer->ux_status = status; /* make software ignore it */ 3136 callout_stop(&xfer->ux_callout); 3137 3138 usb_syncmem(&sqh->dma, 3139 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3140 sizeof(sqh->qh.qh_qtd.qtd_status), 3141 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3142 qhstatus = sqh->qh.qh_qtd.qtd_status; 3143 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3144 usb_syncmem(&sqh->dma, 3145 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3146 sizeof(sqh->qh.qh_qtd.qtd_status), 3147 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3148 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3149 usb_syncmem(&sqtd->dma, 3150 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3151 sizeof(sqtd->qtd.qtd_status), 3152 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3153 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3154 usb_syncmem(&sqtd->dma, 3155 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3156 sizeof(sqtd->qtd.qtd_status), 3157 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3158 if (sqtd == exfer->ex_sqtdend) 3159 break; 3160 } 3161 3162 /* 3163 * Step 2: Wait until we know hardware has finished any possible 3164 * use of the xfer. Also make sure the soft interrupt routine 3165 * has run. 3166 */ 3167 ehci_sync_hc(sc); 3168 sc->sc_softwake = 1; 3169 usb_schedsoftintr(&sc->sc_bus); 3170 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3171 3172 /* 3173 * Step 3: Remove any vestiges of the xfer from the hardware. 3174 * The complication here is that the hardware may have executed 3175 * beyond the xfer we're trying to abort. So as we're scanning 3176 * the TDs of this xfer we check if the hardware points to 3177 * any of them. 3178 */ 3179 3180 usb_syncmem(&sqh->dma, 3181 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3182 sizeof(sqh->qh.qh_curqtd), 3183 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3184 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3185 hit = 0; 3186 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3187 hit |= cur == sqtd->physaddr; 3188 if (sqtd == exfer->ex_sqtdend) 3189 break; 3190 } 3191 sqtd = sqtd->nextqtd; 3192 /* Zap curqtd register if hardware pointed inside the xfer. */ 3193 if (hit && sqtd != NULL) { 3194 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3195 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3196 usb_syncmem(&sqh->dma, 3197 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3198 sizeof(sqh->qh.qh_curqtd), 3199 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3200 sqh->qh.qh_qtd.qtd_status = qhstatus; 3201 usb_syncmem(&sqh->dma, 3202 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3203 sizeof(sqh->qh.qh_qtd.qtd_status), 3204 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3205 } else { 3206 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3207 } 3208 3209 /* 3210 * Step 4: Execute callback. 3211 */ 3212 #ifdef DIAGNOSTIC 3213 exfer->ex_isdone = 1; 3214 #endif 3215 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3216 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3217 usb_transfer_complete(xfer); 3218 if (wake) { 3219 cv_broadcast(&xfer->ux_hccv); 3220 } 3221 3222 KASSERT(mutex_owned(&sc->sc_lock)); 3223 #undef exfer 3224 } 3225 3226 Static void 3227 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3228 { 3229 ehci_isoc_trans_t trans_status; 3230 struct ehci_pipe *epipe; 3231 struct ehci_xfer *exfer; 3232 ehci_softc_t *sc; 3233 struct ehci_soft_itd *itd; 3234 struct ehci_soft_sitd *sitd; 3235 int i, wake; 3236 3237 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3238 3239 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3240 exfer = EXFER(xfer); 3241 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3242 3243 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3244 3245 KASSERT(mutex_owned(&sc->sc_lock)); 3246 3247 if (sc->sc_dying) { 3248 xfer->ux_status = status; 3249 callout_stop(&xfer->ux_callout); 3250 usb_transfer_complete(xfer); 3251 return; 3252 } 3253 3254 if (xfer->ux_hcflags & UXFER_ABORTING) { 3255 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3256 3257 #ifdef DIAGNOSTIC 3258 if (status == USBD_TIMEOUT) 3259 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3260 #endif 3261 3262 xfer->ux_status = status; 3263 USBHIST_LOG(ehcidebug, 3264 "waiting for abort to finish", 0, 0, 0, 0); 3265 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3266 while (xfer->ux_hcflags & UXFER_ABORTING) 3267 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3268 goto done; 3269 } 3270 xfer->ux_hcflags |= UXFER_ABORTING; 3271 3272 xfer->ux_status = status; 3273 callout_stop(&xfer->ux_callout); 3274 3275 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3276 for (itd = exfer->ex_itdstart; itd != NULL; 3277 itd = itd->xfer_next) { 3278 usb_syncmem(&itd->dma, 3279 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3280 sizeof(itd->itd.itd_ctl), 3281 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3282 3283 for (i = 0; i < 8; i++) { 3284 trans_status = le32toh(itd->itd.itd_ctl[i]); 3285 trans_status &= ~EHCI_ITD_ACTIVE; 3286 itd->itd.itd_ctl[i] = htole32(trans_status); 3287 } 3288 3289 usb_syncmem(&itd->dma, 3290 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3291 sizeof(itd->itd.itd_ctl), 3292 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3293 } 3294 } else { 3295 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3296 sitd = sitd->xfer_next) { 3297 usb_syncmem(&sitd->dma, 3298 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3299 sizeof(sitd->sitd.sitd_buffer), 3300 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3301 3302 trans_status = le32toh(sitd->sitd.sitd_trans); 3303 trans_status &= ~EHCI_SITD_ACTIVE; 3304 sitd->sitd.sitd_trans = htole32(trans_status); 3305 3306 usb_syncmem(&sitd->dma, 3307 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3308 sizeof(sitd->sitd.sitd_buffer), 3309 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3310 } 3311 } 3312 3313 sc->sc_softwake = 1; 3314 usb_schedsoftintr(&sc->sc_bus); 3315 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3316 3317 #ifdef DIAGNOSTIC 3318 exfer->ex_isdone = 1; 3319 #endif 3320 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3321 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3322 usb_transfer_complete(xfer); 3323 if (wake) { 3324 cv_broadcast(&xfer->ux_hccv); 3325 } 3326 3327 done: 3328 KASSERT(mutex_owned(&sc->sc_lock)); 3329 return; 3330 } 3331 3332 Static void 3333 ehci_timeout(void *addr) 3334 { 3335 struct ehci_xfer *exfer = addr; 3336 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->ex_xfer.ux_pipe; 3337 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3338 3339 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3340 3341 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3342 #ifdef EHCI_DEBUG 3343 if (ehcidebug > 1) 3344 usbd_dump_pipe(exfer->ex_xfer.ux_pipe); 3345 #endif 3346 3347 if (sc->sc_dying) { 3348 mutex_enter(&sc->sc_lock); 3349 ehci_abort_xfer(&exfer->ex_xfer, USBD_TIMEOUT); 3350 mutex_exit(&sc->sc_lock); 3351 return; 3352 } 3353 3354 /* Execute the abort in a process context. */ 3355 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, addr, 3356 USB_TASKQ_MPSAFE); 3357 usb_add_task(exfer->ex_xfer.ux_pipe->up_dev, &exfer->ex_aborttask, 3358 USB_TASKQ_HC); 3359 } 3360 3361 Static void 3362 ehci_timeout_task(void *addr) 3363 { 3364 usbd_xfer_handle xfer = addr; 3365 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3366 3367 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3368 3369 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3370 3371 mutex_enter(&sc->sc_lock); 3372 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3373 mutex_exit(&sc->sc_lock); 3374 } 3375 3376 /************************/ 3377 3378 Static usbd_status 3379 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3380 { 3381 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3382 usbd_status err; 3383 3384 /* Insert last in queue. */ 3385 mutex_enter(&sc->sc_lock); 3386 err = usb_insert_transfer(xfer); 3387 mutex_exit(&sc->sc_lock); 3388 if (err) 3389 return err; 3390 3391 /* Pipe isn't running, start first */ 3392 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3393 } 3394 3395 Static usbd_status 3396 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3397 { 3398 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3399 usbd_status err; 3400 3401 if (sc->sc_dying) 3402 return USBD_IOERROR; 3403 3404 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3405 3406 err = ehci_device_request(xfer); 3407 if (err) { 3408 return err; 3409 } 3410 3411 if (sc->sc_bus.ub_usepolling) 3412 ehci_waitintr(sc, xfer); 3413 3414 return USBD_IN_PROGRESS; 3415 } 3416 3417 Static void 3418 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3419 { 3420 struct ehci_xfer *ex = EXFER(xfer); 3421 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3422 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3423 usb_device_request_t *req = &xfer->ux_request; 3424 int len = UGETW(req->wLength); 3425 int rd = req->bmRequestType & UT_READ; 3426 3427 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3428 3429 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3430 3431 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3432 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3433 3434 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3435 ehci_del_intr_list(sc, ex); /* remove from active list */ 3436 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3437 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3438 BUS_DMASYNC_POSTWRITE); 3439 if (len) 3440 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3441 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3442 } 3443 3444 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3445 } 3446 3447 /* Abort a device control request. */ 3448 Static void 3449 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3450 { 3451 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3452 3453 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3454 ehci_abort_xfer(xfer, USBD_CANCELLED); 3455 } 3456 3457 /* Close a device control pipe. */ 3458 Static void 3459 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3460 { 3461 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3462 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3463 3464 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3465 3466 KASSERT(mutex_owned(&sc->sc_lock)); 3467 3468 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3469 3470 ehci_close_pipe(pipe, sc->sc_async_head); 3471 } 3472 3473 Static usbd_status 3474 ehci_device_request(usbd_xfer_handle xfer) 3475 { 3476 #define exfer EXFER(xfer) 3477 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3478 usb_device_request_t *req = &xfer->ux_request; 3479 usbd_device_handle dev = epipe->pipe.up_dev; 3480 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3481 ehci_soft_qtd_t *setup, *stat, *next; 3482 ehci_soft_qh_t *sqh; 3483 int isread; 3484 int len; 3485 usbd_status err; 3486 3487 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3488 3489 isread = req->bmRequestType & UT_READ; 3490 len = UGETW(req->wLength); 3491 3492 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3493 "wValue=0x%04x, wIndex=0x%04x", 3494 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3495 UGETW(req->wIndex)); 3496 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3497 len, dev->ud_addr, 3498 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3499 3500 setup = ehci_alloc_sqtd(sc); 3501 if (setup == NULL) { 3502 err = USBD_NOMEM; 3503 goto bad1; 3504 } 3505 stat = ehci_alloc_sqtd(sc); 3506 if (stat == NULL) { 3507 err = USBD_NOMEM; 3508 goto bad2; 3509 } 3510 3511 mutex_enter(&sc->sc_lock); 3512 3513 sqh = epipe->sqh; 3514 3515 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3516 "address QH %d pipe %d\n", 3517 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3518 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3519 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3520 "MPS QH %d pipe %d\n", 3521 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3522 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3523 3524 /* Set up data transaction */ 3525 if (len != 0) { 3526 ehci_soft_qtd_t *end; 3527 3528 /* Start toggle at 1. */ 3529 epipe->nexttoggle = 1; 3530 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3531 &next, &end); 3532 if (err) 3533 goto bad3; 3534 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3535 end->nextqtd = stat; 3536 end->qtd.qtd_next = end->qtd.qtd_altnext = 3537 htole32(stat->physaddr); 3538 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3539 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3540 } else { 3541 next = stat; 3542 } 3543 3544 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3545 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3546 3547 /* Clear toggle */ 3548 setup->qtd.qtd_status = htole32( 3549 EHCI_QTD_ACTIVE | 3550 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3551 EHCI_QTD_SET_CERR(3) | 3552 EHCI_QTD_SET_TOGGLE(0) | 3553 EHCI_QTD_SET_BYTES(sizeof *req) 3554 ); 3555 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3556 setup->qtd.qtd_buffer_hi[0] = 0; 3557 setup->nextqtd = next; 3558 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3559 setup->xfer = xfer; 3560 setup->len = sizeof *req; 3561 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3562 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3563 3564 stat->qtd.qtd_status = htole32( 3565 EHCI_QTD_ACTIVE | 3566 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3567 EHCI_QTD_SET_CERR(3) | 3568 EHCI_QTD_SET_TOGGLE(1) | 3569 EHCI_QTD_IOC 3570 ); 3571 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3572 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3573 stat->nextqtd = NULL; 3574 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3575 stat->xfer = xfer; 3576 stat->len = 0; 3577 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3578 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3579 3580 #ifdef EHCI_DEBUG 3581 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3582 ehci_dump_sqh(sqh); 3583 ehci_dump_sqtds(setup); 3584 #endif 3585 3586 exfer->ex_sqtdstart = setup; 3587 exfer->ex_sqtdend = stat; 3588 #ifdef DIAGNOSTIC 3589 if (!exfer->ex_isdone) { 3590 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3591 } 3592 exfer->ex_isdone = 0; 3593 #endif 3594 3595 /* Insert qTD in QH list. */ 3596 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3597 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3598 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3599 ehci_timeout, xfer); 3600 } 3601 ehci_add_intr_list(sc, exfer); 3602 xfer->ux_status = USBD_IN_PROGRESS; 3603 mutex_exit(&sc->sc_lock); 3604 3605 #ifdef EHCI_DEBUG 3606 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3607 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3608 // delay(10000); 3609 ehci_dump_regs(sc); 3610 ehci_dump_sqh(sc->sc_async_head); 3611 ehci_dump_sqh(sqh); 3612 ehci_dump_sqtds(setup); 3613 #endif 3614 3615 return USBD_NORMAL_COMPLETION; 3616 3617 bad3: 3618 mutex_exit(&sc->sc_lock); 3619 ehci_free_sqtd(sc, stat); 3620 bad2: 3621 ehci_free_sqtd(sc, setup); 3622 bad1: 3623 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3624 mutex_enter(&sc->sc_lock); 3625 xfer->ux_status = err; 3626 usb_transfer_complete(xfer); 3627 mutex_exit(&sc->sc_lock); 3628 return err; 3629 #undef exfer 3630 } 3631 3632 /* 3633 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3634 * qTD status, or miss signalling occasionally under heavy load. If the host 3635 * machine is too fast, we we can miss transaction completion - when we scan 3636 * the active list the transaction still seems to be active. This generally 3637 * exhibits itself as a umass stall that never recovers. 3638 * 3639 * We work around this behaviour by setting up this callback after any softintr 3640 * that completes with transactions still pending, giving us another chance to 3641 * check for completion after the writeback has taken place. 3642 */ 3643 Static void 3644 ehci_intrlist_timeout(void *arg) 3645 { 3646 ehci_softc_t *sc = arg; 3647 3648 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3649 3650 usb_schedsoftintr(&sc->sc_bus); 3651 } 3652 3653 /************************/ 3654 3655 Static usbd_status 3656 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3657 { 3658 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3659 usbd_status err; 3660 3661 /* Insert last in queue. */ 3662 mutex_enter(&sc->sc_lock); 3663 err = usb_insert_transfer(xfer); 3664 mutex_exit(&sc->sc_lock); 3665 if (err) 3666 return err; 3667 3668 /* Pipe isn't running, start first */ 3669 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3670 } 3671 3672 Static usbd_status 3673 ehci_device_bulk_start(usbd_xfer_handle xfer) 3674 { 3675 #define exfer EXFER(xfer) 3676 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3677 usbd_device_handle dev = epipe->pipe.up_dev; 3678 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3679 ehci_soft_qtd_t *data, *dataend; 3680 ehci_soft_qh_t *sqh; 3681 usbd_status err; 3682 int len, isread, endpt; 3683 3684 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3685 3686 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3687 xfer, xfer->ux_length, xfer->ux_flags, 0); 3688 3689 if (sc->sc_dying) 3690 return USBD_IOERROR; 3691 3692 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3693 3694 mutex_enter(&sc->sc_lock); 3695 3696 len = xfer->ux_length; 3697 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3698 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3699 sqh = epipe->sqh; 3700 3701 epipe->u.bulk.length = len; 3702 3703 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3704 &dataend); 3705 if (err) { 3706 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3707 xfer->ux_status = err; 3708 usb_transfer_complete(xfer); 3709 mutex_exit(&sc->sc_lock); 3710 return err; 3711 } 3712 3713 #ifdef EHCI_DEBUG 3714 USBHIST_LOGN(ehcidebug, 5, "data(1):", 0, 0, 0, 0); 3715 ehci_dump_sqh(sqh); 3716 ehci_dump_sqtds(data); 3717 #endif 3718 3719 /* Set up interrupt info. */ 3720 exfer->ex_sqtdstart = data; 3721 exfer->ex_sqtdend = dataend; 3722 #ifdef DIAGNOSTIC 3723 if (!exfer->ex_isdone) { 3724 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3725 } 3726 exfer->ex_isdone = 0; 3727 #endif 3728 3729 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3730 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3731 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3732 ehci_timeout, xfer); 3733 } 3734 ehci_add_intr_list(sc, exfer); 3735 xfer->ux_status = USBD_IN_PROGRESS; 3736 mutex_exit(&sc->sc_lock); 3737 3738 #ifdef EHCI_DEBUG 3739 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3740 // delay(10000); 3741 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3742 ehci_dump_regs(sc); 3743 #if 0 3744 printf("async_head:\n"); 3745 ehci_dump_sqh(sc->sc_async_head); 3746 #endif 3747 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3748 ehci_dump_sqh(sqh); 3749 ehci_dump_sqtds(data); 3750 #endif 3751 3752 if (sc->sc_bus.ub_usepolling) 3753 ehci_waitintr(sc, xfer); 3754 3755 return USBD_IN_PROGRESS; 3756 #undef exfer 3757 } 3758 3759 Static void 3760 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3761 { 3762 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3763 3764 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3765 ehci_abort_xfer(xfer, USBD_CANCELLED); 3766 } 3767 3768 /* 3769 * Close a device bulk pipe. 3770 */ 3771 Static void 3772 ehci_device_bulk_close(usbd_pipe_handle pipe) 3773 { 3774 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3775 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3776 3777 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3778 3779 KASSERT(mutex_owned(&sc->sc_lock)); 3780 3781 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3782 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3783 ehci_close_pipe(pipe, sc->sc_async_head); 3784 } 3785 3786 Static void 3787 ehci_device_bulk_done(usbd_xfer_handle xfer) 3788 { 3789 struct ehci_xfer *ex = EXFER(xfer); 3790 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3791 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3792 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3793 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3794 3795 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3796 3797 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3798 xfer, xfer->ux_actlen, 0, 0); 3799 3800 KASSERT(mutex_owned(&sc->sc_lock)); 3801 3802 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3803 ehci_del_intr_list(sc, ex); /* remove from active list */ 3804 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3805 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3806 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3807 } 3808 3809 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3810 } 3811 3812 /************************/ 3813 3814 Static usbd_status 3815 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3816 { 3817 struct ehci_soft_islot *isp; 3818 int islot, lev; 3819 3820 /* Find a poll rate that is large enough. */ 3821 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3822 if (EHCI_ILEV_IVAL(lev) <= ival) 3823 break; 3824 3825 /* Pick an interrupt slot at the right level. */ 3826 /* XXX could do better than picking at random */ 3827 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3828 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3829 3830 sqh->islot = islot; 3831 isp = &sc->sc_islots[islot]; 3832 mutex_enter(&sc->sc_lock); 3833 ehci_add_qh(sc, sqh, isp->sqh); 3834 mutex_exit(&sc->sc_lock); 3835 3836 return USBD_NORMAL_COMPLETION; 3837 } 3838 3839 Static usbd_status 3840 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3841 { 3842 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3843 usbd_status err; 3844 3845 /* Insert last in queue. */ 3846 mutex_enter(&sc->sc_lock); 3847 err = usb_insert_transfer(xfer); 3848 mutex_exit(&sc->sc_lock); 3849 if (err) 3850 return err; 3851 3852 /* 3853 * Pipe isn't running (otherwise err would be USBD_INPROG), 3854 * so start it first. 3855 */ 3856 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3857 } 3858 3859 Static usbd_status 3860 ehci_device_intr_start(usbd_xfer_handle xfer) 3861 { 3862 #define exfer EXFER(xfer) 3863 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3864 usbd_device_handle dev = xfer->ux_pipe->up_dev; 3865 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3866 ehci_soft_qtd_t *data, *dataend; 3867 ehci_soft_qh_t *sqh; 3868 usbd_status err; 3869 int len, isread, endpt; 3870 3871 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3872 3873 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3874 xfer, xfer->ux_length, xfer->ux_flags, 0); 3875 3876 if (sc->sc_dying) 3877 return USBD_IOERROR; 3878 3879 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3880 3881 mutex_enter(&sc->sc_lock); 3882 3883 len = xfer->ux_length; 3884 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3885 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3886 sqh = epipe->sqh; 3887 3888 epipe->u.intr.length = len; 3889 3890 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3891 &dataend); 3892 if (err) { 3893 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3894 xfer->ux_status = err; 3895 usb_transfer_complete(xfer); 3896 mutex_exit(&sc->sc_lock); 3897 return err; 3898 } 3899 3900 #ifdef EHCI_DEBUG 3901 USBHIST_LOGN(ehcidebug, 5, "data(1)", 0, 0, 0, 0); 3902 ehci_dump_sqh(sqh); 3903 ehci_dump_sqtds(data); 3904 #endif 3905 3906 /* Set up interrupt info. */ 3907 exfer->ex_sqtdstart = data; 3908 exfer->ex_sqtdend = dataend; 3909 #ifdef DIAGNOSTIC 3910 if (!exfer->ex_isdone) { 3911 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3912 } 3913 exfer->ex_isdone = 0; 3914 #endif 3915 3916 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3917 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3918 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3919 ehci_timeout, xfer); 3920 } 3921 ehci_add_intr_list(sc, exfer); 3922 xfer->ux_status = USBD_IN_PROGRESS; 3923 mutex_exit(&sc->sc_lock); 3924 3925 #ifdef EHCI_DEBUG 3926 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3927 // delay(10000); 3928 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3929 ehci_dump_regs(sc); 3930 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3931 ehci_dump_sqh(sqh); 3932 ehci_dump_sqtds(data); 3933 #endif 3934 3935 if (sc->sc_bus.ub_usepolling) 3936 ehci_waitintr(sc, xfer); 3937 3938 return USBD_IN_PROGRESS; 3939 #undef exfer 3940 } 3941 3942 Static void 3943 ehci_device_intr_abort(usbd_xfer_handle xfer) 3944 { 3945 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3946 3947 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3948 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3949 3950 /* 3951 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3952 * async doorbell. That's dependent on the async list, wheras 3953 * intr xfers are periodic, should not use this? 3954 */ 3955 ehci_abort_xfer(xfer, USBD_CANCELLED); 3956 } 3957 3958 Static void 3959 ehci_device_intr_close(usbd_pipe_handle pipe) 3960 { 3961 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3962 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3963 struct ehci_soft_islot *isp; 3964 3965 KASSERT(mutex_owned(&sc->sc_lock)); 3966 3967 isp = &sc->sc_islots[epipe->sqh->islot]; 3968 ehci_close_pipe(pipe, isp->sqh); 3969 } 3970 3971 Static void 3972 ehci_device_intr_done(usbd_xfer_handle xfer) 3973 { 3974 #define exfer EXFER(xfer) 3975 struct ehci_xfer *ex = EXFER(xfer); 3976 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3977 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3978 ehci_soft_qtd_t *data, *dataend; 3979 ehci_soft_qh_t *sqh; 3980 usbd_status err; 3981 int len, isread, endpt; 3982 3983 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3984 3985 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3986 xfer, xfer->ux_actlen, 0, 0); 3987 3988 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3989 3990 if (xfer->ux_pipe->up_repeat) { 3991 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3992 3993 len = epipe->u.intr.length; 3994 xfer->ux_length = len; 3995 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3996 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3997 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3998 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3999 sqh = epipe->sqh; 4000 4001 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4002 &data, &dataend); 4003 if (err) { 4004 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4005 xfer->ux_status = err; 4006 return; 4007 } 4008 4009 /* Set up interrupt info. */ 4010 exfer->ex_sqtdstart = data; 4011 exfer->ex_sqtdend = dataend; 4012 #ifdef DIAGNOSTIC 4013 if (!exfer->ex_isdone) { 4014 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", 4015 exfer, 0, 0, 0); 4016 printf("ehci_device_intr_done: not done, ex=%p\n", 4017 exfer); 4018 } 4019 exfer->ex_isdone = 0; 4020 #endif 4021 4022 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4023 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4024 callout_reset(&xfer->ux_callout, 4025 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4026 } 4027 4028 xfer->ux_status = USBD_IN_PROGRESS; 4029 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4030 ehci_del_intr_list(sc, ex); /* remove from active list */ 4031 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 4032 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4033 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4034 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4035 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4036 } 4037 #undef exfer 4038 } 4039 4040 /************************/ 4041 4042 Static usbd_status 4043 ehci_device_fs_isoc_transfer(usbd_xfer_handle xfer) 4044 { 4045 usbd_status err; 4046 4047 err = usb_insert_transfer(xfer); 4048 if (err && err != USBD_IN_PROGRESS) 4049 return err; 4050 4051 return ehci_device_fs_isoc_start(xfer); 4052 } 4053 4054 Static usbd_status 4055 ehci_device_fs_isoc_start(usbd_xfer_handle xfer) 4056 { 4057 struct ehci_pipe *epipe; 4058 usbd_device_handle dev; 4059 ehci_softc_t *sc; 4060 struct ehci_xfer *exfer; 4061 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4062 usb_dma_t *dma_buf; 4063 int i, j, k, frames; 4064 int offs, total_length; 4065 int frindex; 4066 u_int huba, dir; 4067 4068 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4069 4070 start = NULL; 4071 prev = NULL; 4072 sitd = NULL; 4073 total_length = 0; 4074 exfer = (struct ehci_xfer *) xfer; 4075 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4076 dev = xfer->ux_pipe->up_dev; 4077 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4078 4079 /* 4080 * To allow continuous transfers, above we start all transfers 4081 * immediately. However, we're still going to get usbd_start_next call 4082 * this when another xfer completes. So, check if this is already 4083 * in progress or not 4084 */ 4085 4086 if (exfer->ex_sitdstart != NULL) 4087 return USBD_IN_PROGRESS; 4088 4089 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4090 xfer, xfer->ux_length, xfer->ux_flags, 0); 4091 4092 if (sc->sc_dying) 4093 return USBD_IOERROR; 4094 4095 /* 4096 * To avoid complication, don't allow a request right now that'll span 4097 * the entire frame table. To within 4 frames, to allow some leeway 4098 * on either side of where the hc currently is. 4099 */ 4100 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4101 xfer->ux_nframes >= sc->sc_flsize - 4) { 4102 printf("ehci: isoc descriptor requested that spans the entire" 4103 "frametable, too many frames\n"); 4104 return USBD_INVAL; 4105 } 4106 4107 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4108 4109 #ifdef DIAGNOSTIC 4110 if (!exfer->ex_isdone) 4111 printf("ehci_device_fs_isoc_start: not done, ex = %p\n", exfer); 4112 exfer->ex_isdone = 0; 4113 #endif 4114 4115 /* 4116 * Step 1: Allocate and initialize sitds. 4117 */ 4118 4119 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4120 if (i > 16 || i == 0) { 4121 /* Spec page 271 says intervals > 16 are invalid */ 4122 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4123 4124 return USBD_INVAL; 4125 } 4126 4127 frames = xfer->ux_nframes; 4128 4129 if (frames == 0) { 4130 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4131 4132 return USBD_INVAL; 4133 } 4134 4135 dma_buf = &xfer->ux_dmabuf; 4136 offs = 0; 4137 4138 for (i = 0; i < frames; i++) { 4139 sitd = ehci_alloc_sitd(sc); 4140 4141 if (prev) 4142 prev->xfer_next = sitd; 4143 else 4144 start = sitd; 4145 4146 #ifdef DIAGNOSTIC 4147 if (xfer->ux_frlengths[i] > 0x3ff) { 4148 printf("ehci: invalid frame length\n"); 4149 xfer->ux_frlengths[i] = 0x3ff; 4150 } 4151 #endif 4152 4153 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4154 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4155 4156 /* Set page0 index and offset. */ 4157 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4158 4159 total_length += xfer->ux_frlengths[i]; 4160 offs += xfer->ux_frlengths[i]; 4161 4162 sitd->sitd.sitd_buffer[1] = 4163 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4164 4165 huba = dev->ud_myhsport->up_parent->ud_addr; 4166 4167 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4168 // Set hub address to 0 if embedded TT is used. 4169 if (huba == sc->sc_addr) 4170 huba = 0; 4171 } 4172 */ 4173 4174 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4175 dir = UE_GET_DIR(k) ? 1 : 0; 4176 sitd->sitd.sitd_endp = 4177 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4178 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4179 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4180 EHCI_SITD_SET_HUBA(huba) | 4181 EHCI_SITD_SET_DIR(dir)); 4182 4183 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4184 4185 /* XXX */ 4186 u_char sa, sb; 4187 u_int temp, tlen; 4188 sa = 0; 4189 4190 if (dir == 0) { /* OUT */ 4191 temp = 0; 4192 tlen = xfer->ux_frlengths[i]; 4193 if (tlen <= 188) { 4194 temp |= 1; /* T-count = 1, TP = ALL */ 4195 tlen = 1; 4196 } else { 4197 tlen += 187; 4198 tlen /= 188; 4199 temp |= tlen; /* T-count = [1..6] */ 4200 temp |= 8; /* TP = Begin */ 4201 } 4202 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4203 4204 tlen += sa; 4205 4206 if (tlen >= 8) { 4207 sb = 0; 4208 } else { 4209 sb = (1 << tlen); 4210 } 4211 4212 sa = (1 << sa); 4213 sa = (sb - sa) & 0x3F; 4214 sb = 0; 4215 } else { 4216 sb = (-(4 << sa)) & 0xFE; 4217 sa = (1 << sa) & 0x3F; 4218 sa = 0x01; 4219 sb = 0xfc; 4220 } 4221 4222 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4223 EHCI_SITD_SET_CMASK(sb)); 4224 4225 prev = sitd; 4226 } /* End of frame */ 4227 4228 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4229 4230 stop = sitd; 4231 stop->xfer_next = NULL; 4232 4233 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4234 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4235 4236 /* 4237 * Part 2: Transfer descriptors have now been set up, now they must 4238 * be scheduled into the periodic frame list. Erk. Not wanting to 4239 * complicate matters, transfer is denied if the transfer spans 4240 * more than the period frame list. 4241 */ 4242 4243 mutex_enter(&sc->sc_lock); 4244 4245 /* Start inserting frames */ 4246 if (epipe->u.isoc.cur_xfers > 0) { 4247 frindex = epipe->u.isoc.next_frame; 4248 } else { 4249 frindex = EOREAD4(sc, EHCI_FRINDEX); 4250 frindex = frindex >> 3; /* Erase microframe index */ 4251 frindex += 2; 4252 } 4253 4254 if (frindex >= sc->sc_flsize) 4255 frindex &= (sc->sc_flsize - 1); 4256 4257 /* Whats the frame interval? */ 4258 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4259 4260 sitd = start; 4261 for (j = 0; j < frames; j++) { 4262 if (sitd == NULL) 4263 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4264 4265 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4266 if (sitd->sitd.sitd_next == 0) 4267 /* FIXME: frindex table gets initialized to NULL 4268 * or EHCI_NULL? */ 4269 sitd->sitd.sitd_next = EHCI_NULL; 4270 4271 usb_syncmem(&sitd->dma, 4272 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4273 sizeof(ehci_sitd_t), 4274 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4275 4276 sc->sc_flist[frindex] = 4277 htole32(EHCI_LINK_SITD | sitd->physaddr); 4278 4279 usb_syncmem(&sc->sc_fldma, 4280 sizeof(ehci_link_t) * frindex, 4281 sizeof(ehci_link_t), 4282 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4283 4284 sitd->u.frame_list.next = sc->sc_softsitds[frindex]; 4285 sc->sc_softsitds[frindex] = sitd; 4286 if (sitd->u.frame_list.next != NULL) 4287 sitd->u.frame_list.next->u.frame_list.prev = sitd; 4288 sitd->slot = frindex; 4289 sitd->u.frame_list.prev = NULL; 4290 4291 frindex += i; 4292 if (frindex >= sc->sc_flsize) 4293 frindex -= sc->sc_flsize; 4294 4295 sitd = sitd->xfer_next; 4296 } 4297 4298 epipe->u.isoc.cur_xfers++; 4299 epipe->u.isoc.next_frame = frindex; 4300 4301 exfer->ex_sitdstart = start; 4302 exfer->ex_sitdend = stop; 4303 4304 ehci_add_intr_list(sc, exfer); 4305 xfer->ux_status = USBD_IN_PROGRESS; 4306 xfer->ux_done = 0; 4307 4308 mutex_exit(&sc->sc_lock); 4309 4310 if (sc->sc_bus.ub_usepolling) { 4311 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4312 ehci_waitintr(sc, xfer); 4313 } 4314 4315 return USBD_IN_PROGRESS; 4316 } 4317 4318 Static void 4319 ehci_device_fs_isoc_abort(usbd_xfer_handle xfer) 4320 { 4321 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4322 4323 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4324 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4325 } 4326 4327 Static void 4328 ehci_device_fs_isoc_close(usbd_pipe_handle pipe) 4329 { 4330 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4331 4332 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4333 } 4334 4335 Static void 4336 ehci_device_fs_isoc_done(usbd_xfer_handle xfer) 4337 { 4338 struct ehci_xfer *exfer; 4339 ehci_softc_t *sc; 4340 struct ehci_pipe *epipe; 4341 4342 exfer = EXFER(xfer); 4343 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4344 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4345 4346 KASSERT(mutex_owned(&sc->sc_lock)); 4347 4348 epipe->u.isoc.cur_xfers--; 4349 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4350 ehci_del_intr_list(sc, exfer); 4351 ehci_rem_free_sitd_chain(sc, exfer); 4352 } 4353 4354 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4355 BUS_DMASYNC_POSTREAD); 4356 } 4357 Static usbd_status 4358 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 4359 { 4360 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4361 usbd_status err; 4362 4363 mutex_enter(&sc->sc_lock); 4364 err = usb_insert_transfer(xfer); 4365 mutex_exit(&sc->sc_lock); 4366 if (err && err != USBD_IN_PROGRESS) 4367 return err; 4368 4369 return ehci_device_isoc_start(xfer); 4370 } 4371 4372 Static usbd_status 4373 ehci_device_isoc_start(usbd_xfer_handle xfer) 4374 { 4375 struct ehci_pipe *epipe; 4376 ehci_softc_t *sc; 4377 struct ehci_xfer *exfer; 4378 ehci_soft_itd_t *itd, *prev, *start, *stop; 4379 usb_dma_t *dma_buf; 4380 int i, j, k, frames, uframes, ufrperframe; 4381 int trans_count, offs, total_length; 4382 int frindex; 4383 4384 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4385 4386 start = NULL; 4387 prev = NULL; 4388 itd = NULL; 4389 trans_count = 0; 4390 total_length = 0; 4391 exfer = (struct ehci_xfer *) xfer; 4392 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4393 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4394 4395 /* 4396 * To allow continuous transfers, above we start all transfers 4397 * immediately. However, we're still going to get usbd_start_next call 4398 * this when another xfer completes. So, check if this is already 4399 * in progress or not 4400 */ 4401 4402 if (exfer->ex_itdstart != NULL) 4403 return USBD_IN_PROGRESS; 4404 4405 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4406 xfer, xfer->ux_length, xfer->ux_flags, 0); 4407 4408 if (sc->sc_dying) 4409 return USBD_IOERROR; 4410 4411 /* 4412 * To avoid complication, don't allow a request right now that'll span 4413 * the entire frame table. To within 4 frames, to allow some leeway 4414 * on either side of where the hc currently is. 4415 */ 4416 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4417 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4418 USBHIST_LOG(ehcidebug, 4419 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4420 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4421 return USBD_INVAL; 4422 } 4423 4424 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4425 4426 #ifdef DIAGNOSTIC 4427 if (!exfer->ex_isdone) { 4428 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", exfer, 4429 0, 0, 0); 4430 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 4431 } 4432 exfer->ex_isdone = 0; 4433 #endif 4434 4435 /* 4436 * Step 1: Allocate and initialize itds, how many do we need? 4437 * One per transfer if interval >= 8 microframes, fewer if we use 4438 * multiple microframes per frame. 4439 */ 4440 4441 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4442 if (i > 16 || i == 0) { 4443 /* Spec page 271 says intervals > 16 are invalid */ 4444 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4445 return USBD_INVAL; 4446 } 4447 4448 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4449 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4450 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4451 4452 if (frames == 0) { 4453 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4454 return USBD_INVAL; 4455 } 4456 4457 dma_buf = &xfer->ux_dmabuf; 4458 offs = 0; 4459 4460 for (i = 0; i < frames; i++) { 4461 int froffs = offs; 4462 itd = ehci_alloc_itd(sc); 4463 4464 if (prev != NULL) { 4465 prev->itd.itd_next = 4466 htole32(itd->physaddr | EHCI_LINK_ITD); 4467 usb_syncmem(&itd->dma, 4468 itd->offs + offsetof(ehci_itd_t, itd_next), 4469 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4470 4471 prev->xfer_next = itd; 4472 } else { 4473 start = itd; 4474 } 4475 4476 /* 4477 * Step 1.5, initialize uframes 4478 */ 4479 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4480 /* Calculate which page in the list this starts in */ 4481 int addr = DMAADDR(dma_buf, froffs); 4482 addr = EHCI_PAGE_OFFSET(addr); 4483 addr += (offs - froffs); 4484 addr = EHCI_PAGE(addr); 4485 addr /= EHCI_PAGE_SIZE; 4486 4487 /* This gets the initial offset into the first page, 4488 * looks how far further along the current uframe 4489 * offset is. Works out how many pages that is. 4490 */ 4491 4492 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4493 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4494 EHCI_ITD_SET_PG(addr) | 4495 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4496 4497 total_length += xfer->ux_frlengths[trans_count]; 4498 offs += xfer->ux_frlengths[trans_count]; 4499 trans_count++; 4500 4501 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4502 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4503 break; 4504 } 4505 } 4506 4507 /* Step 1.75, set buffer pointers. To simplify matters, all 4508 * pointers are filled out for the next 7 hardware pages in 4509 * the dma block, so no need to worry what pages to cover 4510 * and what to not. 4511 */ 4512 4513 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4514 /* 4515 * Don't try to lookup a page that's past the end 4516 * of buffer 4517 */ 4518 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4519 if (page_offs >= dma_buf->udma_block->size) 4520 break; 4521 4522 unsigned long long page = DMAADDR(dma_buf, page_offs); 4523 page = EHCI_PAGE(page); 4524 itd->itd.itd_bufr[j] = 4525 htole32(EHCI_ITD_SET_BPTR(page)); 4526 itd->itd.itd_bufr_hi[j] = 4527 htole32(page >> 32); 4528 } 4529 4530 /* 4531 * Other special values 4532 */ 4533 4534 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4535 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4536 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4537 4538 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4539 ? 1 : 0; 4540 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4541 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4542 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4543 4544 /* FIXME: handle invalid trans */ 4545 itd->itd.itd_bufr[2] |= 4546 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4547 4548 usb_syncmem(&itd->dma, 4549 itd->offs + offsetof(ehci_itd_t, itd_next), 4550 sizeof(ehci_itd_t), 4551 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4552 4553 prev = itd; 4554 } /* End of frame */ 4555 4556 stop = itd; 4557 stop->xfer_next = NULL; 4558 4559 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4560 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4561 4562 /* 4563 * Part 2: Transfer descriptors have now been set up, now they must 4564 * be scheduled into the period frame list. Erk. Not wanting to 4565 * complicate matters, transfer is denied if the transfer spans 4566 * more than the period frame list. 4567 */ 4568 4569 mutex_enter(&sc->sc_lock); 4570 4571 /* Start inserting frames */ 4572 if (epipe->u.isoc.cur_xfers > 0) { 4573 frindex = epipe->u.isoc.next_frame; 4574 } else { 4575 frindex = EOREAD4(sc, EHCI_FRINDEX); 4576 frindex = frindex >> 3; /* Erase microframe index */ 4577 frindex += 2; 4578 } 4579 4580 if (frindex >= sc->sc_flsize) 4581 frindex &= (sc->sc_flsize - 1); 4582 4583 /* What's the frame interval? */ 4584 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4585 if (i / USB_UFRAMES_PER_FRAME == 0) 4586 i = 1; 4587 else 4588 i /= USB_UFRAMES_PER_FRAME; 4589 4590 itd = start; 4591 for (j = 0; j < frames; j++) { 4592 if (itd == NULL) 4593 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4594 4595 itd->itd.itd_next = sc->sc_flist[frindex]; 4596 if (itd->itd.itd_next == 0) 4597 /* FIXME: frindex table gets initialized to NULL 4598 * or EHCI_NULL? */ 4599 itd->itd.itd_next = EHCI_NULL; 4600 4601 usb_syncmem(&itd->dma, 4602 itd->offs + offsetof(ehci_itd_t, itd_next), 4603 sizeof(itd->itd.itd_next), 4604 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4605 4606 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4607 4608 usb_syncmem(&sc->sc_fldma, 4609 sizeof(ehci_link_t) * frindex, 4610 sizeof(ehci_link_t), 4611 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4612 4613 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4614 sc->sc_softitds[frindex] = itd; 4615 if (itd->u.frame_list.next != NULL) 4616 itd->u.frame_list.next->u.frame_list.prev = itd; 4617 itd->slot = frindex; 4618 itd->u.frame_list.prev = NULL; 4619 4620 frindex += i; 4621 if (frindex >= sc->sc_flsize) 4622 frindex -= sc->sc_flsize; 4623 4624 itd = itd->xfer_next; 4625 } 4626 4627 epipe->u.isoc.cur_xfers++; 4628 epipe->u.isoc.next_frame = frindex; 4629 4630 exfer->ex_itdstart = start; 4631 exfer->ex_itdend = stop; 4632 4633 ehci_add_intr_list(sc, exfer); 4634 xfer->ux_status = USBD_IN_PROGRESS; 4635 xfer->ux_done = 0; 4636 mutex_exit(&sc->sc_lock); 4637 4638 if (sc->sc_bus.ub_usepolling) { 4639 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4640 ehci_waitintr(sc, xfer); 4641 } 4642 4643 return USBD_IN_PROGRESS; 4644 } 4645 4646 Static void 4647 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4648 { 4649 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4650 4651 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4652 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4653 } 4654 4655 Static void 4656 ehci_device_isoc_close(usbd_pipe_handle pipe) 4657 { 4658 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4659 4660 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4661 } 4662 4663 Static void 4664 ehci_device_isoc_done(usbd_xfer_handle xfer) 4665 { 4666 struct ehci_xfer *exfer; 4667 ehci_softc_t *sc; 4668 struct ehci_pipe *epipe; 4669 4670 exfer = EXFER(xfer); 4671 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4672 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4673 4674 KASSERT(mutex_owned(&sc->sc_lock)); 4675 4676 epipe->u.isoc.cur_xfers--; 4677 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4678 ehci_del_intr_list(sc, exfer); 4679 ehci_rem_free_itd_chain(sc, exfer); 4680 } 4681 4682 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4683 BUS_DMASYNC_POSTREAD); 4684 4685 } 4686
Indexes created Wed Oct 01 19:09:53 GMT 2025