ehci.c revision 1.234.2.28
1 /* $NetBSD: ehci.c,v 1.234.2.28 2015/01/02 08:52:14 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.28 2015/01/02 08:52:14 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 85 #include <dev/usb/ehcireg.h> 86 #include <dev/usb/ehcivar.h> 87 #include <dev/usb/usbroothub.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 /* ehci_soft_sitd_t *sitd; */ 135 } tail; 136 union { 137 /* Control pipe */ 138 struct { 139 usb_dma_t reqdma; 140 } ctl; 141 /* Interrupt pipe */ 142 struct { 143 u_int length; 144 } intr; 145 /* Bulk pipe */ 146 struct { 147 u_int length; 148 } bulk; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 } u; 155 }; 156 157 Static usbd_status ehci_open(usbd_pipe_handle); 158 Static void ehci_poll(struct usbd_bus *); 159 Static void ehci_softintr(void *); 160 Static int ehci_intr1(ehci_softc_t *); 161 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 162 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 166 Static void ehci_idone(struct ehci_xfer *); 167 Static void ehci_timeout(void *); 168 Static void ehci_timeout_task(void *); 169 Static void ehci_intrlist_timeout(void *); 170 Static void ehci_doorbell(void *); 171 Static void ehci_pcd(void *); 172 173 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 174 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 Static int ehci_roothub_ctrl(struct usbd_bus *, 177 usb_device_request_t *, void *, int); 178 179 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 180 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 181 Static void ehci_root_intr_abort(usbd_xfer_handle); 182 Static void ehci_root_intr_close(usbd_pipe_handle); 183 Static void ehci_root_intr_done(usbd_xfer_handle); 184 185 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 186 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 187 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 188 Static void ehci_device_ctrl_close(usbd_pipe_handle); 189 Static void ehci_device_ctrl_done(usbd_xfer_handle); 190 191 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 192 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 193 Static void ehci_device_bulk_abort(usbd_xfer_handle); 194 Static void ehci_device_bulk_close(usbd_pipe_handle); 195 Static void ehci_device_bulk_done(usbd_xfer_handle); 196 197 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 198 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 199 Static void ehci_device_intr_abort(usbd_xfer_handle); 200 Static void ehci_device_intr_close(usbd_pipe_handle); 201 Static void ehci_device_intr_done(usbd_xfer_handle); 202 203 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 204 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 205 Static void ehci_device_isoc_abort(usbd_xfer_handle); 206 Static void ehci_device_isoc_close(usbd_pipe_handle); 207 Static void ehci_device_isoc_done(usbd_xfer_handle); 208 209 Static usbd_status ehci_device_fs_isoc_transfer(usbd_xfer_handle); 210 Static usbd_status ehci_device_fs_isoc_start(usbd_xfer_handle); 211 Static void ehci_device_fs_isoc_abort(usbd_xfer_handle); 212 Static void ehci_device_fs_isoc_close(usbd_pipe_handle); 213 Static void ehci_device_fs_isoc_done(usbd_xfer_handle); 214 215 Static void ehci_device_clear_toggle(usbd_pipe_handle); 216 Static void ehci_noop(usbd_pipe_handle); 217 218 Static void ehci_disown(ehci_softc_t *, int, int); 219 220 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 221 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 222 223 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 224 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 225 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 226 ehci_softc_t *, int, int, usbd_xfer_handle, 227 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 228 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 229 ehci_soft_qtd_t *); 230 231 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 232 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *); 233 Static void ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *); 234 Static void ehci_free_sitd(ehci_softc_t *, ehci_soft_sitd_t *); 235 Static void ehci_rem_free_itd_chain(ehci_softc_t *, 236 struct ehci_xfer *); 237 Static void ehci_rem_free_sitd_chain(ehci_softc_t *, 238 struct ehci_xfer *); 239 Static void ehci_abort_isoc_xfer(usbd_xfer_handle, 240 usbd_status); 241 242 Static usbd_status ehci_device_request(usbd_xfer_handle); 243 244 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 245 int); 246 247 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 248 ehci_soft_qh_t *); 249 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 250 ehci_soft_qh_t *); 251 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 252 Static void ehci_sync_hc(ehci_softc_t *); 253 254 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 255 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 256 257 #ifdef EHCI_DEBUG 258 Static ehci_softc_t *theehci; 259 void ehci_dump(void); 260 #endif 261 262 #ifdef EHCI_DEBUG 263 Static void ehci_dump_regs(ehci_softc_t *); 264 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 265 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 266 Static void ehci_dump_qtd(ehci_qtd_t *); 267 Static void ehci_dump_sqh(ehci_soft_qh_t *); 268 Static void ehci_dump_sitd(struct ehci_soft_itd *); 269 Static void ehci_dump_itd(struct ehci_soft_itd *); 270 Static void ehci_dump_exfer(struct ehci_xfer *); 271 #endif 272 273 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 274 275 #define ehci_add_intr_list(sc, ex) \ 276 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 277 #define ehci_del_intr_list(sc, ex) \ 278 do { \ 279 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 280 (ex)->ex_next.tqe_prev = NULL; \ 281 } while (0) 282 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 283 284 Static const struct usbd_bus_methods ehci_bus_methods = { 285 .ubm_open = ehci_open, 286 .ubm_softint = ehci_softintr, 287 .ubm_dopoll = ehci_poll, 288 .ubm_allocx = ehci_allocx, 289 .ubm_freex = ehci_freex, 290 .ubm_getlock = ehci_get_lock, 291 .ubm_rhctrl = ehci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 295 .upm_transfer = ehci_root_intr_transfer, 296 .upm_start = ehci_root_intr_start, 297 .upm_abort = ehci_root_intr_abort, 298 .upm_close = ehci_root_intr_close, 299 .upm_cleartoggle = ehci_noop, 300 .upm_done = ehci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 304 .upm_transfer = ehci_device_ctrl_transfer, 305 .upm_start = ehci_device_ctrl_start, 306 .upm_abort = ehci_device_ctrl_abort, 307 .upm_close = ehci_device_ctrl_close, 308 .upm_cleartoggle = ehci_noop, 309 .upm_done = ehci_device_ctrl_done, 310 }; 311 312 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 313 .upm_transfer = ehci_device_intr_transfer, 314 .upm_start = ehci_device_intr_start, 315 .upm_abort = ehci_device_intr_abort, 316 .upm_close = ehci_device_intr_close, 317 .upm_cleartoggle = ehci_device_clear_toggle, 318 .upm_done = ehci_device_intr_done, 319 }; 320 321 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 322 .upm_transfer = ehci_device_bulk_transfer, 323 .upm_start = ehci_device_bulk_start, 324 .upm_abort = ehci_device_bulk_abort, 325 .upm_close = ehci_device_bulk_close, 326 .upm_cleartoggle = ehci_device_clear_toggle, 327 .upm_done = ehci_device_bulk_done, 328 }; 329 330 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 331 .upm_transfer = ehci_device_isoc_transfer, 332 .upm_start = ehci_device_isoc_start, 333 .upm_abort = ehci_device_isoc_abort, 334 .upm_close = ehci_device_isoc_close, 335 .upm_cleartoggle = ehci_noop, 336 .upm_done = ehci_device_isoc_done, 337 }; 338 339 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 340 .upm_transfer = ehci_device_fs_isoc_transfer, 341 .upm_start = ehci_device_fs_isoc_start, 342 .upm_abort = ehci_device_fs_isoc_abort, 343 .upm_close = ehci_device_fs_isoc_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_fs_isoc_done, 346 }; 347 348 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 349 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 350 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 351 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 352 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 353 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 354 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 355 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 356 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 357 }; 358 359 int 360 ehci_init(ehci_softc_t *sc) 361 { 362 uint32_t vers, sparams, cparams, hcr; 363 u_int i; 364 usbd_status err; 365 ehci_soft_qh_t *sqh; 366 u_int ncomp; 367 368 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 369 #ifdef EHCI_DEBUG 370 theehci = sc; 371 #endif 372 373 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 374 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 375 cv_init(&sc->sc_softwake_cv, "ehciab"); 376 cv_init(&sc->sc_doorbell, "ehcidi"); 377 378 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 379 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 380 381 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 382 ehci_doorbell, sc); 383 KASSERT(sc->sc_doorbell_si != NULL); 384 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 385 ehci_pcd, sc); 386 KASSERT(sc->sc_pcd_si != NULL); 387 388 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 389 390 vers = EREAD2(sc, EHCI_HCIVERSION); 391 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 392 vers >> 8, vers & 0xff); 393 394 sparams = EREAD4(sc, EHCI_HCSPARAMS); 395 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 396 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 397 ncomp = EHCI_HCS_N_CC(sparams); 398 if (ncomp != sc->sc_ncomp) { 399 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 400 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 401 #if NOHCI == 0 || NUHCI == 0 402 aprint_error("%s: ohci or uhci probably not configured\n", 403 device_xname(sc->sc_dev)); 404 #endif 405 if (ncomp < sc->sc_ncomp) 406 sc->sc_ncomp = ncomp; 407 } 408 if (sc->sc_ncomp > 0) { 409 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 410 aprint_normal("%s: companion controller%s, %d port%s each:", 411 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 412 EHCI_HCS_N_PCC(sparams), 413 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 414 for (i = 0; i < sc->sc_ncomp; i++) 415 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 416 aprint_normal("\n"); 417 } 418 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 419 cparams = EREAD4(sc, EHCI_HCCPARAMS); 420 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 421 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 422 423 if (EHCI_HCC_64BIT(cparams)) { 424 /* MUST clear segment register if 64 bit capable. */ 425 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 426 } 427 428 sc->sc_bus.ub_revision = USBREV_2_0; 429 sc->sc_bus.ub_usedma = true; 430 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 431 432 /* Reset the controller */ 433 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 434 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 435 usb_delay_ms(&sc->sc_bus, 1); 436 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 437 for (i = 0; i < 100; i++) { 438 usb_delay_ms(&sc->sc_bus, 1); 439 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 440 if (!hcr) 441 break; 442 } 443 if (hcr) { 444 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 445 return EIO; 446 } 447 if (sc->sc_vendor_init) 448 sc->sc_vendor_init(sc); 449 450 /* 451 * If we are doing embedded transaction translation function, force 452 * the controller to host mode. 453 */ 454 if (sc->sc_flags & EHCIF_ETTF) { 455 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 456 usbmode &= ~EHCI_USBMODE_CM; 457 usbmode |= EHCI_USBMODE_CM_HOST; 458 EWRITE4(sc, EHCI_USBMODE, usbmode); 459 } 460 461 /* XXX need proper intr scheduling */ 462 sc->sc_rand = 96; 463 464 /* frame list size at default, read back what we got and use that */ 465 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 466 case 0: sc->sc_flsize = 1024; break; 467 case 1: sc->sc_flsize = 512; break; 468 case 2: sc->sc_flsize = 256; break; 469 case 3: return EIO; 470 } 471 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 472 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 473 if (err) 474 return err; 475 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 476 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 477 478 for (i = 0; i < sc->sc_flsize; i++) { 479 sc->sc_flist[i] = EHCI_NULL; 480 } 481 482 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 483 484 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 485 KM_SLEEP); 486 if (sc->sc_softitds == NULL) 487 return ENOMEM; 488 LIST_INIT(&sc->sc_freeitds); 489 LIST_INIT(&sc->sc_freesitds); 490 TAILQ_INIT(&sc->sc_intrhead); 491 492 /* Set up the bus struct. */ 493 sc->sc_bus.ub_methods = &ehci_bus_methods; 494 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 495 496 sc->sc_eintrs = EHCI_NORMAL_INTRS; 497 498 /* 499 * Allocate the interrupt dummy QHs. These are arranged to give poll 500 * intervals that are powers of 2 times 1ms. 501 */ 502 for (i = 0; i < EHCI_INTRQHS; i++) { 503 sqh = ehci_alloc_sqh(sc); 504 if (sqh == NULL) { 505 err = ENOMEM; 506 goto bad1; 507 } 508 sc->sc_islots[i].sqh = sqh; 509 } 510 for (i = 0; i < EHCI_INTRQHS; i++) { 511 sqh = sc->sc_islots[i].sqh; 512 if (i == 0) { 513 /* The last (1ms) QH terminates. */ 514 sqh->qh.qh_link = EHCI_NULL; 515 sqh->next = NULL; 516 } else { 517 /* Otherwise the next QH has half the poll interval */ 518 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 519 sqh->qh.qh_link = htole32(sqh->next->physaddr | 520 EHCI_LINK_QH); 521 } 522 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 523 sqh->qh.qh_curqtd = EHCI_NULL; 524 sqh->next = NULL; 525 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 526 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 527 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 528 sqh->sqtd = NULL; 529 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 531 } 532 /* Point the frame list at the last level (128ms). */ 533 for (i = 0; i < sc->sc_flsize; i++) { 534 int j; 535 536 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 537 revbits[i & (EHCI_MAX_POLLRATE-1)]; 538 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 539 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 540 i)].sqh->physaddr); 541 } 542 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 543 BUS_DMASYNC_PREWRITE); 544 545 /* Allocate dummy QH that starts the async list. */ 546 sqh = ehci_alloc_sqh(sc); 547 if (sqh == NULL) { 548 err = ENOMEM; 549 goto bad1; 550 } 551 /* Fill the QH */ 552 sqh->qh.qh_endp = 553 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 554 sqh->qh.qh_link = 555 htole32(sqh->physaddr | EHCI_LINK_QH); 556 sqh->qh.qh_curqtd = EHCI_NULL; 557 sqh->next = NULL; 558 /* Fill the overlay qTD */ 559 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 560 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 561 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 562 sqh->sqtd = NULL; 563 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 564 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 565 #ifdef EHCI_DEBUG 566 ehci_dump_sqh(sqh); 567 #endif 568 569 /* Point to async list */ 570 sc->sc_async_head = sqh; 571 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 572 573 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 574 575 /* Turn on controller */ 576 EOWRITE4(sc, EHCI_USBCMD, 577 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 578 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 579 EHCI_CMD_ASE | 580 EHCI_CMD_PSE | 581 EHCI_CMD_RS); 582 583 /* Take over port ownership */ 584 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 585 586 for (i = 0; i < 100; i++) { 587 usb_delay_ms(&sc->sc_bus, 1); 588 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 589 if (!hcr) 590 break; 591 } 592 if (hcr) { 593 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 594 return EIO; 595 } 596 597 /* Enable interrupts */ 598 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 599 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 600 601 return 0; 602 603 #if 0 604 bad2: 605 ehci_free_sqh(sc, sc->sc_async_head); 606 #endif 607 bad1: 608 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 609 return err; 610 } 611 612 int 613 ehci_intr(void *v) 614 { 615 ehci_softc_t *sc = v; 616 int ret = 0; 617 618 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 619 620 if (sc == NULL) 621 return 0; 622 623 mutex_spin_enter(&sc->sc_intr_lock); 624 625 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 626 goto done; 627 628 /* If we get an interrupt while polling, then just ignore it. */ 629 if (sc->sc_bus.ub_usepolling) { 630 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 631 632 if (intrs) 633 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 634 USBHIST_LOGN(ehcidebug, 16, 635 "ignored interrupt while polling", 0, 0, 0, 0); 636 goto done; 637 } 638 639 ret = ehci_intr1(sc); 640 641 done: 642 mutex_spin_exit(&sc->sc_intr_lock); 643 return ret; 644 } 645 646 Static int 647 ehci_intr1(ehci_softc_t *sc) 648 { 649 uint32_t intrs, eintrs; 650 651 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 652 653 /* In case the interrupt occurs before initialization has completed. */ 654 if (sc == NULL) { 655 #ifdef DIAGNOSTIC 656 printf("ehci_intr1: sc == NULL\n"); 657 #endif 658 return 0; 659 } 660 661 KASSERT(mutex_owned(&sc->sc_intr_lock)); 662 663 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 664 if (!intrs) 665 return 0; 666 667 eintrs = intrs & sc->sc_eintrs; 668 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 669 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 670 if (!eintrs) 671 return 0; 672 673 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 674 if (eintrs & EHCI_STS_IAA) { 675 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 676 kpreempt_disable(); 677 KASSERT(sc->sc_doorbell_si != NULL); 678 softint_schedule(sc->sc_doorbell_si); 679 kpreempt_enable(); 680 eintrs &= ~EHCI_STS_IAA; 681 } 682 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 683 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 684 eintrs & EHCI_STS_INT ? 1 : 0, 685 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 686 usb_schedsoftintr(&sc->sc_bus); 687 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 688 } 689 if (eintrs & EHCI_STS_HSE) { 690 printf("%s: unrecoverable error, controller halted\n", 691 device_xname(sc->sc_dev)); 692 /* XXX what else */ 693 } 694 if (eintrs & EHCI_STS_PCD) { 695 kpreempt_disable(); 696 KASSERT(sc->sc_pcd_si != NULL); 697 softint_schedule(sc->sc_pcd_si); 698 kpreempt_enable(); 699 eintrs &= ~EHCI_STS_PCD; 700 } 701 702 if (eintrs != 0) { 703 /* Block unprocessed interrupts. */ 704 sc->sc_eintrs &= ~eintrs; 705 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 706 printf("%s: blocking intrs 0x%x\n", 707 device_xname(sc->sc_dev), eintrs); 708 } 709 710 return 1; 711 } 712 713 Static void 714 ehci_doorbell(void *addr) 715 { 716 ehci_softc_t *sc = addr; 717 718 mutex_enter(&sc->sc_lock); 719 cv_broadcast(&sc->sc_doorbell); 720 mutex_exit(&sc->sc_lock); 721 } 722 723 Static void 724 ehci_pcd(void *addr) 725 { 726 ehci_softc_t *sc = addr; 727 usbd_xfer_handle xfer; 728 u_char *p; 729 int i, m; 730 731 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 732 733 mutex_enter(&sc->sc_lock); 734 xfer = sc->sc_intrxfer; 735 736 if (xfer == NULL) { 737 /* Just ignore the change. */ 738 goto done; 739 } 740 741 p = xfer->ux_buf; 742 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 743 memset(p, 0, xfer->ux_length); 744 for (i = 1; i <= m; i++) { 745 /* Pick out CHANGE bits from the status reg. */ 746 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 747 p[i/8] |= 1 << (i%8); 748 if (i % 8 == 7) 749 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 750 p[i/8], 0, 0); 751 } 752 xfer->ux_actlen = xfer->ux_length; 753 xfer->ux_status = USBD_NORMAL_COMPLETION; 754 755 usb_transfer_complete(xfer); 756 757 done: 758 mutex_exit(&sc->sc_lock); 759 } 760 761 Static void 762 ehci_softintr(void *v) 763 { 764 struct usbd_bus *bus = v; 765 ehci_softc_t *sc = bus->ub_hcpriv; 766 struct ehci_xfer *ex, *nextex; 767 768 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 769 770 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 771 772 /* 773 * The only explanation I can think of for why EHCI is as brain dead 774 * as UHCI interrupt-wise is that Intel was involved in both. 775 * An interrupt just tells us that something is done, we have no 776 * clue what, so we need to scan through all active transfers. :-( 777 */ 778 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 779 nextex = TAILQ_NEXT(ex, ex_next); 780 ehci_check_intr(sc, ex); 781 } 782 783 /* Schedule a callout to catch any dropped transactions. */ 784 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 785 !TAILQ_EMPTY(&sc->sc_intrhead)) 786 callout_reset(&sc->sc_tmo_intrlist, 787 hz, ehci_intrlist_timeout, sc); 788 789 if (sc->sc_softwake) { 790 sc->sc_softwake = 0; 791 cv_broadcast(&sc->sc_softwake_cv); 792 } 793 } 794 795 /* Check for an interrupt. */ 796 Static void 797 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 798 { 799 usbd_device_handle dev = ex->ex_xfer.ux_pipe->up_dev; 800 int attr; 801 802 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 803 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 804 805 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 806 807 attr = ex->ex_xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 808 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 809 if (dev->ud_speed == USB_SPEED_HIGH) 810 ehci_check_itd_intr(sc, ex); 811 else 812 ehci_check_sitd_intr(sc, ex); 813 } else 814 ehci_check_qh_intr(sc, ex); 815 816 return; 817 } 818 819 Static void 820 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 821 { 822 ehci_soft_qtd_t *sqtd, *lsqtd; 823 uint32_t status; 824 825 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 826 827 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 828 829 if (ex->ex_sqtdstart == NULL) { 830 printf("ehci_check_qh_intr: not valid sqtd\n"); 831 return; 832 } 833 834 lsqtd = ex->ex_sqtdend; 835 #ifdef DIAGNOSTIC 836 if (lsqtd == NULL) { 837 printf("ehci_check_qh_intr: lsqtd==0\n"); 838 return; 839 } 840 #endif 841 /* 842 * If the last TD is still active we need to check whether there 843 * is an error somewhere in the middle, or whether there was a 844 * short packet (SPD and not ACTIVE). 845 */ 846 usb_syncmem(&lsqtd->dma, 847 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 848 sizeof(lsqtd->qtd.qtd_status), 849 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 850 status = le32toh(lsqtd->qtd.qtd_status); 851 usb_syncmem(&lsqtd->dma, 852 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 853 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 854 if (status & EHCI_QTD_ACTIVE) { 855 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 856 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd; 857 sqtd = sqtd->nextqtd) { 858 usb_syncmem(&sqtd->dma, 859 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 860 sizeof(sqtd->qtd.qtd_status), 861 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 862 status = le32toh(sqtd->qtd.qtd_status); 863 usb_syncmem(&sqtd->dma, 864 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 865 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 866 /* If there's an active QTD the xfer isn't done. */ 867 if (status & EHCI_QTD_ACTIVE) 868 break; 869 /* Any kind of error makes the xfer done. */ 870 if (status & EHCI_QTD_HALTED) 871 goto done; 872 /* Handle short packets */ 873 if (EHCI_QTD_GET_BYTES(status) != 0) { 874 usbd_pipe_handle pipe = ex->ex_xfer.ux_pipe; 875 usb_endpoint_descriptor_t *ed = 876 pipe->up_endpoint->ue_edesc; 877 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 878 879 /* 880 * If we get here for a control transfer then 881 * we need to let the hardware complete the 882 * status phase. That is, we're not done 883 * quite yet. 884 * 885 * Otherwise, we're done. 886 */ 887 if (xt == UE_CONTROL) { 888 break; 889 } 890 goto done; 891 } 892 } 893 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 894 ex, ex->ex_sqtdstart, 0, 0); 895 return; 896 } 897 done: 898 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 899 callout_stop(&ex->ex_xfer.ux_callout); 900 ehci_idone(ex); 901 } 902 903 Static void 904 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 905 { 906 ehci_soft_itd_t *itd; 907 int i; 908 909 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 910 911 KASSERT(mutex_owned(&sc->sc_lock)); 912 913 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 914 return; 915 916 if (ex->ex_itdstart == NULL) { 917 printf("ehci_check_itd_intr: not valid itd\n"); 918 return; 919 } 920 921 itd = ex->ex_itdend; 922 #ifdef DIAGNOSTIC 923 if (itd == NULL) { 924 printf("ehci_check_itd_intr: itdend == 0\n"); 925 return; 926 } 927 #endif 928 929 /* 930 * check no active transfers in last itd, meaning we're finished 931 */ 932 933 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 934 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 935 BUS_DMASYNC_POSTREAD); 936 937 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 938 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 939 break; 940 } 941 942 if (i == EHCI_ITD_NUFRAMES) { 943 goto done; /* All 8 descriptors inactive, it's done */ 944 } 945 946 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 947 ex->ex_itdstart, 0, 0); 948 return; 949 done: 950 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 951 callout_stop(&ex->ex_xfer.ux_callout); 952 ehci_idone(ex); 953 } 954 955 void 956 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 957 { 958 ehci_soft_sitd_t *sitd; 959 960 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 961 962 KASSERT(mutex_owned(&sc->sc_lock)); 963 964 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 965 return; 966 967 if (ex->ex_sitdstart == NULL) { 968 printf("ehci_check_sitd_intr: not valid sitd\n"); 969 return; 970 } 971 972 sitd = ex->ex_sitdend; 973 #ifdef DIAGNOSTIC 974 if (sitd == NULL) { 975 printf("ehci_check_sitd_intr: sitdend == 0\n"); 976 return; 977 } 978 #endif 979 980 /* 981 * check no active transfers in last sitd, meaning we're finished 982 */ 983 984 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 985 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 986 BUS_DMASYNC_POSTREAD); 987 988 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 989 return; 990 991 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 992 callout_stop(&(ex->ex_xfer.ux_callout)); 993 ehci_idone(ex); 994 } 995 996 997 Static void 998 ehci_idone(struct ehci_xfer *ex) 999 { 1000 usbd_xfer_handle xfer = &ex->ex_xfer; 1001 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1002 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1003 ehci_soft_qtd_t *sqtd, *lsqtd; 1004 uint32_t status = 0, nstatus = 0; 1005 int actlen; 1006 1007 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1008 1009 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1010 1011 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1012 1013 #ifdef DIAGNOSTIC 1014 if (ex->ex_isdone) { 1015 printf("ehci_idone: ex=%p is done!\n", ex); 1016 #ifdef EHCI_DEBUG 1017 ehci_dump_exfer(ex); 1018 #endif 1019 return; 1020 } 1021 ex->ex_isdone = 1; 1022 #endif 1023 1024 if (xfer->ux_status == USBD_CANCELLED || 1025 xfer->ux_status == USBD_TIMEOUT) { 1026 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1027 return; 1028 } 1029 1030 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1031 #ifdef EHCI_DEBUG 1032 ehci_dump_sqtds(ex->ex_sqtdstart); 1033 #endif 1034 1035 /* The transfer is done, compute actual length and status. */ 1036 1037 u_int xfertype, speed; 1038 1039 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1040 speed = xfer->ux_pipe->up_dev->ud_speed; 1041 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1042 /* HS isoc transfer */ 1043 1044 struct ehci_soft_itd *itd; 1045 int i, nframes, len, uframes; 1046 1047 nframes = 0; 1048 actlen = 0; 1049 1050 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1051 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1052 1053 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1054 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1055 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1056 BUS_DMASYNC_POSTREAD); 1057 1058 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1059 /* 1060 * XXX - driver didn't fill in the frame full 1061 * of uframes. This leads to scheduling 1062 * inefficiencies, but working around 1063 * this doubles complexity of tracking 1064 * an xfer. 1065 */ 1066 if (nframes >= xfer->ux_nframes) 1067 break; 1068 1069 status = le32toh(itd->itd.itd_ctl[i]); 1070 len = EHCI_ITD_GET_LEN(status); 1071 if (EHCI_ITD_GET_STATUS(status) != 0) 1072 len = 0; /*No valid data on error*/ 1073 1074 xfer->ux_frlengths[nframes++] = len; 1075 actlen += len; 1076 } 1077 1078 if (nframes >= xfer->ux_nframes) 1079 break; 1080 } 1081 1082 xfer->ux_actlen = actlen; 1083 xfer->ux_status = USBD_NORMAL_COMPLETION; 1084 goto end; 1085 } 1086 1087 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1088 /* FS isoc transfer */ 1089 struct ehci_soft_sitd *sitd; 1090 int nframes, len; 1091 1092 nframes = 0; 1093 actlen = 0; 1094 1095 for (sitd = ex->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1096 usb_syncmem(&sitd->dma,sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 1097 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 1098 BUS_DMASYNC_POSTREAD); 1099 1100 /* 1101 * XXX - driver didn't fill in the frame full 1102 * of uframes. This leads to scheduling 1103 * inefficiencies, but working around 1104 * this doubles complexity of tracking 1105 * an xfer. 1106 */ 1107 if (nframes >= xfer->ux_nframes) 1108 break; 1109 1110 status = le32toh(sitd->sitd.sitd_trans); 1111 len = EHCI_SITD_GET_LEN(status); 1112 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1113 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1114 /* No valid data on error */ 1115 len = xfer->ux_frlengths[nframes]; 1116 } 1117 1118 /* 1119 * frlengths[i]: # of bytes to send 1120 * len: # of bytes host didn't send 1121 */ 1122 xfer->ux_frlengths[nframes] -= len; 1123 /* frlengths[i]: # of bytes host sent */ 1124 actlen += xfer->ux_frlengths[nframes++]; 1125 1126 if (nframes >= xfer->ux_nframes) 1127 break; 1128 } 1129 1130 xfer->ux_actlen = actlen; 1131 xfer->ux_status = USBD_NORMAL_COMPLETION; 1132 goto end; 1133 } 1134 KASSERT(xfertype != UE_ISOCHRONOUS); 1135 1136 /* Continue processing xfers using queue heads */ 1137 1138 lsqtd = ex->ex_sqtdend; 1139 actlen = 0; 1140 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd->nextqtd; 1141 sqtd = sqtd->nextqtd) { 1142 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1143 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1144 nstatus = le32toh(sqtd->qtd.qtd_status); 1145 if (nstatus & EHCI_QTD_ACTIVE) 1146 break; 1147 1148 status = nstatus; 1149 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1150 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1151 } 1152 1153 1154 /* 1155 * If there are left over TDs we need to update the toggle. 1156 * The default pipe doesn't need it since control transfers 1157 * start the toggle at 0 every time. 1158 * For a short transfer we need to update the toggle for the missing 1159 * packets within the qTD. 1160 */ 1161 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1162 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1163 USBHIST_LOG(ehcidebug, 1164 "toggle update status=0x%08x nstatus=0x%08x", 1165 status, nstatus, 0, 0); 1166 #if 0 1167 ehci_dump_sqh(epipe->sqh); 1168 ehci_dump_sqtds(ex->ex_sqtdstart); 1169 #endif 1170 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1171 } 1172 1173 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1174 actlen, status, 0); 1175 xfer->ux_actlen = actlen; 1176 if (status & EHCI_QTD_HALTED) { 1177 #ifdef EHCI_DEBUG 1178 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1179 xfer->ux_pipe->up_dev->ud_addr, 1180 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1181 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d stat=%#x", 1182 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1183 status, 0); 1184 USBHIST_LOG(ehcidebug, 1185 "active =%d halted=%d buferr=%d babble=%d", 1186 status & EHCI_QTD_ACTIVE ? 1 : 0, 1187 status & EHCI_QTD_HALTED ? 1 : 0, 1188 status & EHCI_QTD_BUFERR ? 1 : 0, 1189 status & EHCI_QTD_BABBLE ? 1 : 0); 1190 1191 USBHIST_LOG(ehcidebug, 1192 "xacterr=%d missed=%d split =%d ping =%d", 1193 status & EHCI_QTD_XACTERR ? 1 : 0, 1194 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1195 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1196 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1197 1198 ehci_dump_sqh(epipe->sqh); 1199 ehci_dump_sqtds(ex->ex_sqtdstart); 1200 #endif 1201 /* low&full speed has an extra error flag */ 1202 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1203 EHCI_QH_SPEED_HIGH) 1204 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1205 else 1206 status &= EHCI_QTD_STATERRS; 1207 if (status == 0) /* no other errors means a stall */ { 1208 xfer->ux_status = USBD_STALLED; 1209 } else { 1210 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1211 } 1212 /* XXX need to reset TT on missed microframe */ 1213 if (status & EHCI_QTD_MISSEDMICRO) { 1214 printf("%s: missed microframe, TT reset not " 1215 "implemented, hub might be inoperational\n", 1216 device_xname(sc->sc_dev)); 1217 } 1218 } else { 1219 xfer->ux_status = USBD_NORMAL_COMPLETION; 1220 } 1221 1222 end: 1223 /* 1224 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1225 * during this call, before methods->done is called: dma sync required 1226 * beforehand? 1227 */ 1228 usb_transfer_complete(xfer); 1229 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1230 } 1231 1232 /* 1233 * Wait here until controller claims to have an interrupt. 1234 * Then call ehci_intr and return. Use timeout to avoid waiting 1235 * too long. 1236 */ 1237 Static void 1238 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1239 { 1240 int timo; 1241 uint32_t intrs; 1242 1243 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1244 1245 xfer->ux_status = USBD_IN_PROGRESS; 1246 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1247 usb_delay_ms(&sc->sc_bus, 1); 1248 if (sc->sc_dying) 1249 break; 1250 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1251 sc->sc_eintrs; 1252 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1253 #ifdef EHCI_DEBUG 1254 if (ehcidebug > 15) 1255 ehci_dump_regs(sc); 1256 #endif 1257 if (intrs) { 1258 mutex_spin_enter(&sc->sc_intr_lock); 1259 ehci_intr1(sc); 1260 mutex_spin_exit(&sc->sc_intr_lock); 1261 if (xfer->ux_status != USBD_IN_PROGRESS) 1262 return; 1263 } 1264 } 1265 1266 /* Timeout */ 1267 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1268 xfer->ux_status = USBD_TIMEOUT; 1269 mutex_enter(&sc->sc_lock); 1270 usb_transfer_complete(xfer); 1271 mutex_exit(&sc->sc_lock); 1272 /* XXX should free TD */ 1273 } 1274 1275 Static void 1276 ehci_poll(struct usbd_bus *bus) 1277 { 1278 ehci_softc_t *sc = bus->ub_hcpriv; 1279 1280 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1281 1282 #ifdef EHCI_DEBUG 1283 static int last; 1284 int new; 1285 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1286 if (new != last) { 1287 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1288 last = new; 1289 } 1290 #endif 1291 1292 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1293 mutex_spin_enter(&sc->sc_intr_lock); 1294 ehci_intr1(sc); 1295 mutex_spin_exit(&sc->sc_intr_lock); 1296 } 1297 } 1298 1299 void 1300 ehci_childdet(device_t self, device_t child) 1301 { 1302 struct ehci_softc *sc = device_private(self); 1303 1304 KASSERT(sc->sc_child == child); 1305 sc->sc_child = NULL; 1306 } 1307 1308 int 1309 ehci_detach(struct ehci_softc *sc, int flags) 1310 { 1311 int rv = 0; 1312 1313 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1314 1315 if (sc->sc_child != NULL) 1316 rv = config_detach(sc->sc_child, flags); 1317 1318 if (rv != 0) 1319 return rv; 1320 1321 callout_halt(&sc->sc_tmo_intrlist, NULL); 1322 callout_destroy(&sc->sc_tmo_intrlist); 1323 1324 /* XXX free other data structures XXX */ 1325 if (sc->sc_softitds) 1326 kmem_free(sc->sc_softitds, 1327 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1328 cv_destroy(&sc->sc_doorbell); 1329 cv_destroy(&sc->sc_softwake_cv); 1330 1331 #if 0 1332 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1333 1334 softint_disestablish(sc->sc_doorbell_si); 1335 softint_disestablish(sc->sc_pcd_si); 1336 1337 mutex_destroy(&sc->sc_lock); 1338 mutex_destroy(&sc->sc_intr_lock); 1339 #endif 1340 1341 pool_cache_destroy(sc->sc_xferpool); 1342 1343 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1344 1345 return rv; 1346 } 1347 1348 1349 int 1350 ehci_activate(device_t self, enum devact act) 1351 { 1352 struct ehci_softc *sc = device_private(self); 1353 1354 switch (act) { 1355 case DVACT_DEACTIVATE: 1356 sc->sc_dying = 1; 1357 return 0; 1358 default: 1359 return EOPNOTSUPP; 1360 } 1361 } 1362 1363 /* 1364 * Handle suspend/resume. 1365 * 1366 * We need to switch to polling mode here, because this routine is 1367 * called from an interrupt context. This is all right since we 1368 * are almost suspended anyway. 1369 * 1370 * Note that this power handler isn't to be registered directly; the 1371 * bus glue needs to call out to it. 1372 */ 1373 bool 1374 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1375 { 1376 ehci_softc_t *sc = device_private(dv); 1377 int i; 1378 uint32_t cmd, hcr; 1379 1380 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1381 1382 mutex_spin_enter(&sc->sc_intr_lock); 1383 sc->sc_bus.ub_usepolling++; 1384 mutex_spin_exit(&sc->sc_intr_lock); 1385 1386 for (i = 1; i <= sc->sc_noport; i++) { 1387 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1388 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1389 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1390 } 1391 1392 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1393 1394 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1395 EOWRITE4(sc, EHCI_USBCMD, cmd); 1396 1397 for (i = 0; i < 100; i++) { 1398 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1399 if (hcr == 0) 1400 break; 1401 1402 usb_delay_ms(&sc->sc_bus, 1); 1403 } 1404 if (hcr != 0) 1405 printf("%s: reset timeout\n", device_xname(dv)); 1406 1407 cmd &= ~EHCI_CMD_RS; 1408 EOWRITE4(sc, EHCI_USBCMD, cmd); 1409 1410 for (i = 0; i < 100; i++) { 1411 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1412 if (hcr == EHCI_STS_HCH) 1413 break; 1414 1415 usb_delay_ms(&sc->sc_bus, 1); 1416 } 1417 if (hcr != EHCI_STS_HCH) 1418 printf("%s: config timeout\n", device_xname(dv)); 1419 1420 mutex_spin_enter(&sc->sc_intr_lock); 1421 sc->sc_bus.ub_usepolling--; 1422 mutex_spin_exit(&sc->sc_intr_lock); 1423 1424 return true; 1425 } 1426 1427 bool 1428 ehci_resume(device_t dv, const pmf_qual_t *qual) 1429 { 1430 ehci_softc_t *sc = device_private(dv); 1431 int i; 1432 uint32_t cmd, hcr; 1433 1434 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1435 1436 /* restore things in case the bios sucks */ 1437 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1438 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1439 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1440 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1441 1442 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1443 1444 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1445 1446 hcr = 0; 1447 for (i = 1; i <= sc->sc_noport; i++) { 1448 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1449 if ((cmd & EHCI_PS_PO) == 0 && 1450 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1451 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1452 hcr = 1; 1453 } 1454 } 1455 1456 if (hcr) { 1457 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1458 1459 for (i = 1; i <= sc->sc_noport; i++) { 1460 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1461 if ((cmd & EHCI_PS_PO) == 0 && 1462 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1463 EOWRITE4(sc, EHCI_PORTSC(i), 1464 cmd & ~EHCI_PS_FPR); 1465 } 1466 } 1467 1468 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1469 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1470 1471 for (i = 0; i < 100; i++) { 1472 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1473 if (hcr != EHCI_STS_HCH) 1474 break; 1475 1476 usb_delay_ms(&sc->sc_bus, 1); 1477 } 1478 if (hcr == EHCI_STS_HCH) 1479 printf("%s: config timeout\n", device_xname(dv)); 1480 1481 return true; 1482 } 1483 1484 /* 1485 * Shut down the controller when the system is going down. 1486 */ 1487 bool 1488 ehci_shutdown(device_t self, int flags) 1489 { 1490 ehci_softc_t *sc = device_private(self); 1491 1492 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1493 1494 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1495 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1496 return true; 1497 } 1498 1499 Static usbd_xfer_handle 1500 ehci_allocx(struct usbd_bus *bus) 1501 { 1502 struct ehci_softc *sc = bus->ub_hcpriv; 1503 usbd_xfer_handle xfer; 1504 1505 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1506 if (xfer != NULL) { 1507 memset(xfer, 0, sizeof(struct ehci_xfer)); 1508 #ifdef DIAGNOSTIC 1509 EXFER(xfer)->ex_isdone = 1; 1510 xfer->ux_state = XFER_BUSY; 1511 #endif 1512 } 1513 return xfer; 1514 } 1515 1516 Static void 1517 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1518 { 1519 struct ehci_softc *sc = bus->ub_hcpriv; 1520 1521 #ifdef DIAGNOSTIC 1522 if (xfer->ux_state != XFER_BUSY) { 1523 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1524 xfer->ux_state); 1525 } 1526 xfer->ux_state = XFER_FREE; 1527 if (!EXFER(xfer)->ex_isdone) { 1528 printf("ehci_freex: !isdone\n"); 1529 } 1530 #endif 1531 pool_cache_put(sc->sc_xferpool, xfer); 1532 } 1533 1534 Static void 1535 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1536 { 1537 struct ehci_softc *sc = bus->ub_hcpriv; 1538 1539 *lock = &sc->sc_lock; 1540 } 1541 1542 Static void 1543 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1544 { 1545 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1546 1547 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1548 1549 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1550 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1551 #ifdef EHCI_DEBUG 1552 if (ehcidebug) 1553 usbd_dump_pipe(pipe); 1554 #endif 1555 epipe->nexttoggle = 0; 1556 } 1557 1558 Static void 1559 ehci_noop(usbd_pipe_handle pipe) 1560 { 1561 } 1562 1563 #ifdef EHCI_DEBUG 1564 /* 1565 * Unused function - this is meant to be called from a kernel 1566 * debugger. 1567 */ 1568 void 1569 ehci_dump(void) 1570 { 1571 ehci_softc_t *sc = theehci; 1572 int i; 1573 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1574 EOREAD4(sc, EHCI_USBCMD), 1575 EOREAD4(sc, EHCI_USBSTS), 1576 EOREAD4(sc, EHCI_USBINTR)); 1577 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1578 EOREAD4(sc, EHCI_FRINDEX), 1579 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1580 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1581 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1582 for (i = 1; i <= sc->sc_noport; i++) 1583 printf("port %d status=0x%08x\n", i, 1584 EOREAD4(sc, EHCI_PORTSC(i))); 1585 } 1586 1587 Static void 1588 ehci_dump_regs(ehci_softc_t *sc) 1589 { 1590 int i; 1591 1592 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1593 1594 USBHIST_LOG(ehcidebug, 1595 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1596 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1597 EOREAD4(sc, EHCI_USBINTR), 0); 1598 USBHIST_LOG(ehcidebug, 1599 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1600 "async = 0x%08x", 1601 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1602 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1603 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1604 for (i = 1; i <= sc->sc_noport; i += 2) { 1605 if (i == sc->sc_noport) { 1606 USBHIST_LOG(ehcidebug, 1607 "port %d status = 0x%08x", i, 1608 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1609 } else { 1610 USBHIST_LOG(ehcidebug, 1611 "port %d status = 0x%08x port %d status = 0x%08x", 1612 i, EOREAD4(sc, EHCI_PORTSC(i)), 1613 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1614 } 1615 } 1616 } 1617 1618 #ifdef EHCI_DEBUG 1619 #define ehci_dump_link(link, type) do { \ 1620 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1621 link, \ 1622 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1623 if (type) { \ 1624 USBHIST_LOG(ehcidebug, \ 1625 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1626 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1627 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1628 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1629 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1630 } \ 1631 } while(0) 1632 #else 1633 #define ehci_dump_link(link, type) 1634 #endif 1635 1636 Static void 1637 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1638 { 1639 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1640 int i; 1641 uint32_t stop = 0; 1642 1643 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1644 ehci_dump_sqtd(sqtd); 1645 usb_syncmem(&sqtd->dma, 1646 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1647 sizeof(sqtd->qtd), 1648 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1649 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1650 usb_syncmem(&sqtd->dma, 1651 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1652 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1653 } 1654 if (sqtd) 1655 USBHIST_LOG(ehcidebug, 1656 "dump aborted, too many TDs", 0, 0, 0, 0); 1657 } 1658 1659 Static void 1660 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1661 { 1662 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1663 1664 usb_syncmem(&sqtd->dma, sqtd->offs, 1665 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1666 1667 USBHIST_LOGN(ehcidebug, 10, 1668 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1669 ehci_dump_qtd(&sqtd->qtd); 1670 1671 usb_syncmem(&sqtd->dma, sqtd->offs, 1672 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1673 } 1674 1675 Static void 1676 ehci_dump_qtd(ehci_qtd_t *qtd) 1677 { 1678 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1679 1680 #ifdef USBHIST 1681 uint32_t s = le32toh(qtd->qtd_status); 1682 #endif 1683 1684 USBHIST_LOGN(ehcidebug, 10, 1685 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1686 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1687 USBHIST_LOGN(ehcidebug, 10, 1688 " toggle = %d ioc = %d bytes = %#x " 1689 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1690 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1691 USBHIST_LOGN(ehcidebug, 10, 1692 " cerr = %d pid = %d stat = %x", 1693 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1694 0); 1695 USBHIST_LOGN(ehcidebug, 10, 1696 "active =%d halted=%d buferr=%d babble=%d", 1697 s & EHCI_QTD_ACTIVE ? 1 : 0, 1698 s & EHCI_QTD_HALTED ? 1 : 0, 1699 s & EHCI_QTD_BUFERR ? 1 : 0, 1700 s & EHCI_QTD_BABBLE ? 1 : 0); 1701 USBHIST_LOGN(ehcidebug, 10, 1702 "xacterr=%d missed=%d split =%d ping =%d", 1703 s & EHCI_QTD_XACTERR ? 1 : 0, 1704 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1705 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1706 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1707 USBHIST_LOGN(ehcidebug, 10, 1708 "buffer[0] = %#x buffer[1] = %#x " 1709 "buffer[2] = %#x buffer[3] = %#x", 1710 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1711 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1712 USBHIST_LOGN(ehcidebug, 10, 1713 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1714 } 1715 1716 Static void 1717 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1718 { 1719 #ifdef USBHIST 1720 ehci_qh_t *qh = &sqh->qh; 1721 ehci_link_t link; 1722 #endif 1723 uint32_t endp, endphub; 1724 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1725 1726 usb_syncmem(&sqh->dma, sqh->offs, 1727 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1728 1729 USBHIST_LOGN(ehcidebug, 10, 1730 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1731 link = le32toh(qh->qh_link); 1732 ehci_dump_link(link, true); 1733 1734 endp = le32toh(qh->qh_endp); 1735 USBHIST_LOGN(ehcidebug, 10, 1736 " endp = %#x", endp, 0, 0, 0); 1737 USBHIST_LOGN(ehcidebug, 10, 1738 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1739 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1740 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1741 USBHIST_LOGN(ehcidebug, 10, 1742 " dtc = %d hrecl = %d", 1743 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1744 USBHIST_LOGN(ehcidebug, 10, 1745 " ctl = %d nrl = %d mpl = %#x(%d)", 1746 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1747 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1748 1749 endphub = le32toh(qh->qh_endphub); 1750 USBHIST_LOGN(ehcidebug, 10, 1751 " endphub = %#x", endphub, 0, 0, 0); 1752 USBHIST_LOGN(ehcidebug, 10, 1753 " smask = 0x%02x cmask = 0x%02x", 1754 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1755 USBHIST_LOGN(ehcidebug, 10, 1756 " huba = 0x%02x port = %d mult = %d", 1757 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1758 EHCI_QH_GET_MULT(endphub), 0); 1759 1760 link = le32toh(qh->qh_curqtd); 1761 ehci_dump_link(link, false); 1762 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1763 ehci_dump_qtd(&qh->qh_qtd); 1764 1765 usb_syncmem(&sqh->dma, sqh->offs, 1766 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1767 } 1768 1769 Static void 1770 ehci_dump_itd(struct ehci_soft_itd *itd) 1771 { 1772 ehci_isoc_trans_t t; 1773 ehci_isoc_bufr_ptr_t b, b2, b3; 1774 int i; 1775 1776 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1777 1778 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1779 0, 0); 1780 1781 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1782 t = le32toh(itd->itd.itd_ctl[i]); 1783 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1784 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1785 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1786 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1787 EHCI_ITD_GET_OFFS(t), 0); 1788 } 1789 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1790 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1791 USBHIST_LOG(ehcidebug, " %x", 1792 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1793 1794 b = le32toh(itd->itd.itd_bufr[0]); 1795 b2 = le32toh(itd->itd.itd_bufr[1]); 1796 b3 = le32toh(itd->itd.itd_bufr[2]); 1797 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1798 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1799 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1800 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1801 } 1802 1803 Static void 1804 ehci_dump_sitd(struct ehci_soft_itd *itd) 1805 { 1806 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1807 1808 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1809 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1810 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1811 itd->xfer_next, itd->physaddr, itd->slot, 0); 1812 } 1813 1814 Static void 1815 ehci_dump_exfer(struct ehci_xfer *ex) 1816 { 1817 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1818 1819 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1820 ex, ex->ex_sqtdstart, ex->ex_sqtdend, 0); 1821 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1822 ex->ex_itdstart, ex->ex_itdend, ex->ex_isdone, 0); 1823 } 1824 #endif 1825 1826 Static usbd_status 1827 ehci_open(usbd_pipe_handle pipe) 1828 { 1829 usbd_device_handle dev = pipe->up_dev; 1830 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1831 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1832 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1833 uint8_t addr = dev->ud_addr; 1834 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1835 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1836 ehci_soft_qh_t *sqh; 1837 usbd_status err; 1838 int ival, speed, naks; 1839 int hshubaddr, hshubport; 1840 1841 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1842 1843 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1844 pipe, addr, ed->bEndpointAddress, rhaddr); 1845 1846 if (dev->ud_myhsport) { 1847 /* 1848 * When directly attached FS/LS device while doing embedded 1849 * transaction translations and we are the hub, set the hub 1850 * address to 0 (us). 1851 */ 1852 if (!(sc->sc_flags & EHCIF_ETTF) 1853 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1854 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1855 } else { 1856 hshubaddr = 0; 1857 } 1858 hshubport = dev->ud_myhsport->up_portno; 1859 } else { 1860 hshubaddr = 0; 1861 hshubport = 0; 1862 } 1863 1864 if (sc->sc_dying) 1865 return USBD_IOERROR; 1866 1867 /* toggle state needed for bulk endpoints */ 1868 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1869 1870 if (addr == rhaddr) { 1871 switch (ed->bEndpointAddress) { 1872 case USB_CONTROL_ENDPOINT: 1873 pipe->up_methods = &roothub_ctrl_methods; 1874 break; 1875 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1876 pipe->up_methods = &ehci_root_intr_methods; 1877 break; 1878 default: 1879 USBHIST_LOG(ehcidebug, 1880 "bad bEndpointAddress 0x%02x", 1881 ed->bEndpointAddress, 0, 0, 0); 1882 return USBD_INVAL; 1883 } 1884 return USBD_NORMAL_COMPLETION; 1885 } 1886 1887 /* XXX All this stuff is only valid for async. */ 1888 switch (dev->ud_speed) { 1889 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1890 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1891 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1892 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1893 } 1894 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1895 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1896 hshubaddr, hshubport, 0, 0); 1897 return USBD_INVAL; 1898 } 1899 1900 /* 1901 * For interrupt transfer, nak throttling must be disabled, but for 1902 * the other transfer type, nak throttling should be enabled from the 1903 * viewpoint that avoids the memory thrashing. 1904 */ 1905 naks = (xfertype == UE_INTERRUPT) ? 0 1906 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1907 1908 /* Allocate sqh for everything, save isoc xfers */ 1909 if (xfertype != UE_ISOCHRONOUS) { 1910 sqh = ehci_alloc_sqh(sc); 1911 if (sqh == NULL) 1912 return USBD_NOMEM; 1913 /* qh_link filled when the QH is added */ 1914 sqh->qh.qh_endp = htole32( 1915 EHCI_QH_SET_ADDR(addr) | 1916 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1917 EHCI_QH_SET_EPS(speed) | 1918 EHCI_QH_DTC | 1919 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1920 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1921 EHCI_QH_CTL : 0) | 1922 EHCI_QH_SET_NRL(naks) 1923 ); 1924 sqh->qh.qh_endphub = htole32( 1925 EHCI_QH_SET_MULT(1) | 1926 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1927 ); 1928 if (speed != EHCI_QH_SPEED_HIGH) 1929 sqh->qh.qh_endphub |= htole32( 1930 EHCI_QH_SET_PORT(hshubport) | 1931 EHCI_QH_SET_HUBA(hshubaddr) | 1932 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1933 ); 1934 sqh->qh.qh_curqtd = EHCI_NULL; 1935 /* Fill the overlay qTD */ 1936 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1937 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1938 sqh->qh.qh_qtd.qtd_status = htole32(0); 1939 1940 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1941 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1942 epipe->sqh = sqh; 1943 } else { 1944 sqh = NULL; 1945 } /*xfertype == UE_ISOC*/ 1946 1947 switch (xfertype) { 1948 case UE_CONTROL: 1949 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1950 0, &epipe->u.ctl.reqdma); 1951 #ifdef EHCI_DEBUG 1952 if (err) 1953 printf("ehci_open: usb_allocmem()=%d\n", err); 1954 #endif 1955 if (err) 1956 goto bad; 1957 pipe->up_methods = &ehci_device_ctrl_methods; 1958 mutex_enter(&sc->sc_lock); 1959 ehci_add_qh(sc, sqh, sc->sc_async_head); 1960 mutex_exit(&sc->sc_lock); 1961 break; 1962 case UE_BULK: 1963 pipe->up_methods = &ehci_device_bulk_methods; 1964 mutex_enter(&sc->sc_lock); 1965 ehci_add_qh(sc, sqh, sc->sc_async_head); 1966 mutex_exit(&sc->sc_lock); 1967 break; 1968 case UE_INTERRUPT: 1969 pipe->up_methods = &ehci_device_intr_methods; 1970 ival = pipe->up_interval; 1971 if (ival == USBD_DEFAULT_INTERVAL) { 1972 if (speed == EHCI_QH_SPEED_HIGH) { 1973 if (ed->bInterval > 16) { 1974 /* 1975 * illegal with high-speed, but there 1976 * were documentation bugs in the spec, 1977 * so be generous 1978 */ 1979 ival = 256; 1980 } else 1981 ival = (1 << (ed->bInterval - 1)) / 8; 1982 } else 1983 ival = ed->bInterval; 1984 } 1985 err = ehci_device_setintr(sc, sqh, ival); 1986 if (err) 1987 goto bad; 1988 break; 1989 case UE_ISOCHRONOUS: 1990 if (speed == EHCI_QH_SPEED_HIGH) 1991 pipe->up_methods = &ehci_device_isoc_methods; 1992 else 1993 pipe->up_methods = &ehci_device_fs_isoc_methods; 1994 if (ed->bInterval == 0 || ed->bInterval > 16) { 1995 printf("ehci: opening pipe with invalid bInterval\n"); 1996 err = USBD_INVAL; 1997 goto bad; 1998 } 1999 if (UGETW(ed->wMaxPacketSize) == 0) { 2000 printf("ehci: zero length endpoint open request\n"); 2001 err = USBD_INVAL; 2002 goto bad; 2003 } 2004 epipe->u.isoc.next_frame = 0; 2005 epipe->u.isoc.cur_xfers = 0; 2006 break; 2007 default: 2008 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2009 err = USBD_INVAL; 2010 goto bad; 2011 } 2012 return USBD_NORMAL_COMPLETION; 2013 2014 bad: 2015 if (sqh != NULL) 2016 ehci_free_sqh(sc, sqh); 2017 return err; 2018 } 2019 2020 /* 2021 * Add an ED to the schedule. Called with USB lock held. 2022 */ 2023 Static void 2024 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2025 { 2026 2027 KASSERT(mutex_owned(&sc->sc_lock)); 2028 2029 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2030 2031 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2032 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2033 2034 sqh->next = head->next; 2035 sqh->qh.qh_link = head->qh.qh_link; 2036 2037 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2038 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2039 2040 head->next = sqh; 2041 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2042 2043 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2044 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2045 2046 #ifdef EHCI_DEBUG 2047 ehci_dump_sqh(sqh); 2048 #endif 2049 } 2050 2051 /* 2052 * Remove an ED from the schedule. Called with USB lock held. 2053 */ 2054 Static void 2055 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2056 { 2057 ehci_soft_qh_t *p; 2058 2059 KASSERT(mutex_owned(&sc->sc_lock)); 2060 2061 /* XXX */ 2062 for (p = head; p != NULL && p->next != sqh; p = p->next) 2063 ; 2064 if (p == NULL) 2065 panic("ehci_rem_qh: ED not found"); 2066 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2067 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2068 p->next = sqh->next; 2069 p->qh.qh_link = sqh->qh.qh_link; 2070 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2071 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2072 2073 ehci_sync_hc(sc); 2074 } 2075 2076 Static void 2077 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2078 { 2079 int i; 2080 uint32_t status; 2081 2082 /* Save toggle bit and ping status. */ 2083 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2084 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2085 status = sqh->qh.qh_qtd.qtd_status & 2086 htole32(EHCI_QTD_TOGGLE_MASK | 2087 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2088 /* Set HALTED to make hw leave it alone. */ 2089 sqh->qh.qh_qtd.qtd_status = 2090 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2091 usb_syncmem(&sqh->dma, 2092 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2093 sizeof(sqh->qh.qh_qtd.qtd_status), 2094 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2095 sqh->qh.qh_curqtd = 0; 2096 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2097 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2098 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2099 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2100 sqh->sqtd = sqtd; 2101 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2102 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2103 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2104 sqh->qh.qh_qtd.qtd_status = status; 2105 usb_syncmem(&sqh->dma, 2106 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2107 sizeof(sqh->qh.qh_qtd.qtd_status), 2108 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2109 } 2110 2111 /* 2112 * Ensure that the HC has released all references to the QH. We do this 2113 * by asking for a Async Advance Doorbell interrupt and then we wait for 2114 * the interrupt. 2115 * To make this easier we first obtain exclusive use of the doorbell. 2116 */ 2117 Static void 2118 ehci_sync_hc(ehci_softc_t *sc) 2119 { 2120 int error __diagused; 2121 2122 KASSERT(mutex_owned(&sc->sc_lock)); 2123 2124 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2125 2126 if (sc->sc_dying) { 2127 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2128 return; 2129 } 2130 /* ask for doorbell */ 2131 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2132 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2133 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2134 2135 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2136 2137 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2138 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2139 #ifdef DIAGNOSTIC 2140 if (error) 2141 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2142 #endif 2143 } 2144 2145 Static void 2146 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2147 { 2148 struct ehci_soft_itd *itd, *prev; 2149 2150 prev = NULL; 2151 2152 if (exfer->ex_itdstart == NULL || exfer->ex_itdend == NULL) 2153 panic("ehci isoc xfer being freed, but with no itd chain\n"); 2154 2155 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2156 prev = itd->u.frame_list.prev; 2157 /* Unlink itd from hardware chain, or frame array */ 2158 if (prev == NULL) { /* We're at the table head */ 2159 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2160 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2161 usb_syncmem(&sc->sc_fldma, 2162 sizeof(ehci_link_t) * itd->slot, 2163 sizeof(ehci_link_t), 2164 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2165 2166 if (itd->u.frame_list.next != NULL) 2167 itd->u.frame_list.next->u.frame_list.prev = NULL; 2168 } else { 2169 /* XXX this part is untested... */ 2170 prev->itd.itd_next = itd->itd.itd_next; 2171 usb_syncmem(&itd->dma, 2172 itd->offs + offsetof(ehci_itd_t, itd_next), 2173 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2174 2175 prev->u.frame_list.next = itd->u.frame_list.next; 2176 if (itd->u.frame_list.next != NULL) 2177 itd->u.frame_list.next->u.frame_list.prev = prev; 2178 } 2179 } 2180 2181 prev = NULL; 2182 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2183 if (prev != NULL) 2184 ehci_free_itd(sc, prev); 2185 prev = itd; 2186 } 2187 if (prev) 2188 ehci_free_itd(sc, prev); 2189 exfer->ex_itdstart = NULL; 2190 exfer->ex_itdend = NULL; 2191 } 2192 2193 Static void 2194 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2195 { 2196 struct ehci_soft_sitd *sitd, *prev; 2197 2198 prev = NULL; 2199 2200 if (exfer->ex_sitdstart == NULL || exfer->ex_sitdend == NULL) 2201 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2202 2203 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2204 prev = sitd->u.frame_list.prev; 2205 /* Unlink sitd from hardware chain, or frame array */ 2206 if (prev == NULL) { /* We're at the table head */ 2207 sc->sc_softsitds[sitd->slot] = sitd->u.frame_list.next; 2208 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2209 usb_syncmem(&sc->sc_fldma, 2210 sizeof(ehci_link_t) * sitd->slot, 2211 sizeof(ehci_link_t), 2212 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2213 2214 if (sitd->u.frame_list.next != NULL) 2215 sitd->u.frame_list.next->u.frame_list.prev = NULL; 2216 } else { 2217 /* XXX this part is untested... */ 2218 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2219 usb_syncmem(&sitd->dma, 2220 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2221 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2222 2223 prev->u.frame_list.next = sitd->u.frame_list.next; 2224 if (sitd->u.frame_list.next != NULL) 2225 sitd->u.frame_list.next->u.frame_list.prev = prev; 2226 } 2227 } 2228 2229 prev = NULL; 2230 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2231 if (prev != NULL) 2232 ehci_free_sitd(sc, prev); 2233 prev = sitd; 2234 } 2235 if (prev) 2236 ehci_free_sitd(sc, prev); 2237 exfer->ex_sitdstart = NULL; 2238 exfer->ex_sitdend = NULL; 2239 } 2240 2241 /***********/ 2242 2243 Static int 2244 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2245 void *buf, int buflen) 2246 { 2247 ehci_softc_t *sc = bus->ub_hcpriv; 2248 usb_hub_descriptor_t hubd; 2249 usb_port_status_t ps; 2250 uint16_t len, value, index; 2251 int l, totlen = 0; 2252 int port, i; 2253 uint32_t v; 2254 2255 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2256 2257 if (sc->sc_dying) 2258 return -1; 2259 2260 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2261 req->bmRequestType, req->bRequest, 0, 0); 2262 2263 len = UGETW(req->wLength); 2264 value = UGETW(req->wValue); 2265 index = UGETW(req->wIndex); 2266 2267 #define C(x,y) ((x) | ((y) << 8)) 2268 switch (C(req->bRequest, req->bmRequestType)) { 2269 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2270 if (len == 0) 2271 break; 2272 switch (value) { 2273 case C(0, UDESC_DEVICE): { 2274 usb_device_descriptor_t devd; 2275 totlen = min(buflen, sizeof(devd)); 2276 memcpy(&devd, buf, totlen); 2277 USETW(devd.idVendor, sc->sc_id_vendor); 2278 memcpy(buf, &devd, totlen); 2279 break; 2280 2281 } 2282 #define sd ((usb_string_descriptor_t *)buf) 2283 case C(1, UDESC_STRING): 2284 /* Vendor */ 2285 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2286 break; 2287 case C(2, UDESC_STRING): 2288 /* Product */ 2289 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2290 break; 2291 #undef sd 2292 default: 2293 /* default from usbroothub */ 2294 return buflen; 2295 } 2296 break; 2297 2298 /* Hub requests */ 2299 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2300 break; 2301 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2302 USBHIST_LOG(ehcidebug, 2303 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2304 0, 0); 2305 if (index < 1 || index > sc->sc_noport) { 2306 return -1; 2307 } 2308 port = EHCI_PORTSC(index); 2309 v = EOREAD4(sc, port); 2310 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2311 v &= ~EHCI_PS_CLEAR; 2312 switch (value) { 2313 case UHF_PORT_ENABLE: 2314 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2315 break; 2316 case UHF_PORT_SUSPEND: 2317 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2318 break; 2319 v &= ~EHCI_PS_SUSP; 2320 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2321 /* see USB2 spec ch. 7.1.7.7 */ 2322 usb_delay_ms(&sc->sc_bus, 20); 2323 EOWRITE4(sc, port, v); 2324 usb_delay_ms(&sc->sc_bus, 2); 2325 #ifdef DEBUG 2326 v = EOREAD4(sc, port); 2327 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2328 printf("ehci: resume failed: %x\n", v); 2329 #endif 2330 break; 2331 case UHF_PORT_POWER: 2332 if (sc->sc_hasppc) 2333 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2334 break; 2335 case UHF_PORT_TEST: 2336 USBHIST_LOG(ehcidebug, "clear port test " 2337 "%d", index, 0, 0, 0); 2338 break; 2339 case UHF_PORT_INDICATOR: 2340 USBHIST_LOG(ehcidebug, "clear port ind " 2341 "%d", index, 0, 0, 0); 2342 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2343 break; 2344 case UHF_C_PORT_CONNECTION: 2345 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2346 break; 2347 case UHF_C_PORT_ENABLE: 2348 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2349 break; 2350 case UHF_C_PORT_SUSPEND: 2351 /* how? */ 2352 break; 2353 case UHF_C_PORT_OVER_CURRENT: 2354 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2355 break; 2356 case UHF_C_PORT_RESET: 2357 sc->sc_isreset[index] = 0; 2358 break; 2359 default: 2360 return -1; 2361 } 2362 #if 0 2363 switch(value) { 2364 case UHF_C_PORT_CONNECTION: 2365 case UHF_C_PORT_ENABLE: 2366 case UHF_C_PORT_SUSPEND: 2367 case UHF_C_PORT_OVER_CURRENT: 2368 case UHF_C_PORT_RESET: 2369 default: 2370 break; 2371 } 2372 #endif 2373 break; 2374 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2375 if (len == 0) 2376 break; 2377 if ((value & 0xff) != 0) { 2378 return -1; 2379 } 2380 totlen = min(buflen, sizeof(hubd)); 2381 memcpy(&hubd, buf, totlen); 2382 hubd.bNbrPorts = sc->sc_noport; 2383 v = EOREAD4(sc, EHCI_HCSPARAMS); 2384 USETW(hubd.wHubCharacteristics, 2385 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2386 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2387 ? UHD_PORT_IND : 0); 2388 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2389 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2390 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2391 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2392 totlen = min(totlen, hubd.bDescLength); 2393 memcpy(buf, &hubd, totlen); 2394 break; 2395 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2396 if (len != 4) { 2397 return -1; 2398 } 2399 memset(buf, 0, len); /* ? XXX */ 2400 totlen = len; 2401 break; 2402 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2403 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2404 if (index < 1 || index > sc->sc_noport) { 2405 return -1; 2406 } 2407 if (len != 4) { 2408 return -1; 2409 } 2410 v = EOREAD4(sc, EHCI_PORTSC(index)); 2411 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2412 2413 i = UPS_HIGH_SPEED; 2414 if (sc->sc_flags & EHCIF_ETTF) { 2415 /* 2416 * If we are doing embedded transaction translation, 2417 * then directly attached LS/FS devices are reset by 2418 * the EHCI controller itself. PSPD is encoded 2419 * the same way as in USBSTATUS. 2420 */ 2421 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2422 } 2423 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2424 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2425 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2426 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2427 if (v & EHCI_PS_PR) i |= UPS_RESET; 2428 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2429 if (sc->sc_vendor_port_status) 2430 i = sc->sc_vendor_port_status(sc, v, i); 2431 USETW(ps.wPortStatus, i); 2432 i = 0; 2433 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2434 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2435 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2436 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2437 USETW(ps.wPortChange, i); 2438 totlen = min(len, sizeof(ps)); 2439 memcpy(buf, &ps, totlen); 2440 break; 2441 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2442 return -1; 2443 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2444 break; 2445 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2446 if (index < 1 || index > sc->sc_noport) { 2447 return -1; 2448 } 2449 port = EHCI_PORTSC(index); 2450 v = EOREAD4(sc, port); 2451 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2452 v &= ~EHCI_PS_CLEAR; 2453 switch(value) { 2454 case UHF_PORT_ENABLE: 2455 EOWRITE4(sc, port, v | EHCI_PS_PE); 2456 break; 2457 case UHF_PORT_SUSPEND: 2458 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2459 break; 2460 case UHF_PORT_RESET: 2461 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2462 if (EHCI_PS_IS_LOWSPEED(v) 2463 && sc->sc_ncomp > 0 2464 && !(sc->sc_flags & EHCIF_ETTF)) { 2465 /* 2466 * Low speed device on non-ETTF controller or 2467 * unaccompanied controller, give up ownership. 2468 */ 2469 ehci_disown(sc, index, 1); 2470 break; 2471 } 2472 /* Start reset sequence. */ 2473 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2474 EOWRITE4(sc, port, v | EHCI_PS_PR); 2475 /* Wait for reset to complete. */ 2476 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2477 if (sc->sc_dying) { 2478 return -1; 2479 } 2480 /* 2481 * An embedded transaction translator will automatically 2482 * terminate the reset sequence so there's no need to 2483 * it. 2484 */ 2485 v = EOREAD4(sc, port); 2486 if (v & EHCI_PS_PR) { 2487 /* Terminate reset sequence. */ 2488 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2489 /* Wait for HC to complete reset. */ 2490 usb_delay_ms(&sc->sc_bus, 2491 EHCI_PORT_RESET_COMPLETE); 2492 if (sc->sc_dying) { 2493 return -1; 2494 } 2495 } 2496 2497 v = EOREAD4(sc, port); 2498 USBHIST_LOG(ehcidebug, 2499 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2500 if (v & EHCI_PS_PR) { 2501 printf("%s: port reset timeout\n", 2502 device_xname(sc->sc_dev)); 2503 return USBD_TIMEOUT; 2504 } 2505 if (!(v & EHCI_PS_PE)) { 2506 /* Not a high speed device, give up ownership.*/ 2507 ehci_disown(sc, index, 0); 2508 break; 2509 } 2510 sc->sc_isreset[index] = 1; 2511 USBHIST_LOG(ehcidebug, 2512 "ehci port %d reset, status = 0x%08x", index, v, 0, 2513 0); 2514 break; 2515 case UHF_PORT_POWER: 2516 USBHIST_LOG(ehcidebug, 2517 "set port power %d (has PPC = %d)", index, 2518 sc->sc_hasppc, 0, 0); 2519 if (sc->sc_hasppc) 2520 EOWRITE4(sc, port, v | EHCI_PS_PP); 2521 break; 2522 case UHF_PORT_TEST: 2523 USBHIST_LOG(ehcidebug, "set port test %d", 2524 index, 0, 0, 0); 2525 break; 2526 case UHF_PORT_INDICATOR: 2527 USBHIST_LOG(ehcidebug, "set port ind %d", 2528 index, 0, 0, 0); 2529 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2530 break; 2531 default: 2532 return -1; 2533 } 2534 break; 2535 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2536 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2537 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2538 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2539 break; 2540 default: 2541 /* default from usbroothub */ 2542 return buflen; 2543 } 2544 2545 return totlen; 2546 } 2547 2548 Static void 2549 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2550 { 2551 int port; 2552 uint32_t v; 2553 2554 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2555 2556 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2557 #ifdef DIAGNOSTIC 2558 if (sc->sc_npcomp != 0) { 2559 int i = (index-1) / sc->sc_npcomp; 2560 if (i >= sc->sc_ncomp) 2561 printf("%s: strange port\n", 2562 device_xname(sc->sc_dev)); 2563 else 2564 printf("%s: handing over %s speed device on " 2565 "port %d to %s\n", 2566 device_xname(sc->sc_dev), 2567 lowspeed ? "low" : "full", 2568 index, device_xname(sc->sc_comps[i])); 2569 } else { 2570 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2571 } 2572 #endif 2573 port = EHCI_PORTSC(index); 2574 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2575 EOWRITE4(sc, port, v | EHCI_PS_PO); 2576 } 2577 2578 Static usbd_status 2579 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2580 { 2581 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2582 usbd_status err; 2583 2584 /* Insert last in queue. */ 2585 mutex_enter(&sc->sc_lock); 2586 err = usb_insert_transfer(xfer); 2587 mutex_exit(&sc->sc_lock); 2588 if (err) 2589 return err; 2590 2591 /* Pipe isn't running, start first */ 2592 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2593 } 2594 2595 Static usbd_status 2596 ehci_root_intr_start(usbd_xfer_handle xfer) 2597 { 2598 usbd_pipe_handle pipe = xfer->ux_pipe; 2599 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2600 2601 if (sc->sc_dying) 2602 return USBD_IOERROR; 2603 2604 mutex_enter(&sc->sc_lock); 2605 sc->sc_intrxfer = xfer; 2606 mutex_exit(&sc->sc_lock); 2607 2608 return USBD_IN_PROGRESS; 2609 } 2610 2611 /* Abort a root interrupt request. */ 2612 Static void 2613 ehci_root_intr_abort(usbd_xfer_handle xfer) 2614 { 2615 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2616 2617 KASSERT(mutex_owned(&sc->sc_lock)); 2618 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2619 2620 sc->sc_intrxfer = NULL; 2621 2622 xfer->ux_status = USBD_CANCELLED; 2623 usb_transfer_complete(xfer); 2624 } 2625 2626 /* Close the root pipe. */ 2627 Static void 2628 ehci_root_intr_close(usbd_pipe_handle pipe) 2629 { 2630 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2631 2632 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2633 2634 KASSERT(mutex_owned(&sc->sc_lock)); 2635 2636 sc->sc_intrxfer = NULL; 2637 } 2638 2639 Static void 2640 ehci_root_intr_done(usbd_xfer_handle xfer) 2641 { 2642 xfer->ux_hcpriv = NULL; 2643 } 2644 2645 /************************/ 2646 2647 Static ehci_soft_qh_t * 2648 ehci_alloc_sqh(ehci_softc_t *sc) 2649 { 2650 ehci_soft_qh_t *sqh; 2651 usbd_status err; 2652 int i, offs; 2653 usb_dma_t dma; 2654 2655 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2656 2657 if (sc->sc_freeqhs == NULL) { 2658 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2659 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2660 EHCI_PAGE_SIZE, &dma); 2661 #ifdef EHCI_DEBUG 2662 if (err) 2663 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2664 #endif 2665 if (err) 2666 return NULL; 2667 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2668 offs = i * EHCI_SQH_SIZE; 2669 sqh = KERNADDR(&dma, offs); 2670 sqh->physaddr = DMAADDR(&dma, offs); 2671 sqh->dma = dma; 2672 sqh->offs = offs; 2673 sqh->next = sc->sc_freeqhs; 2674 sc->sc_freeqhs = sqh; 2675 } 2676 } 2677 sqh = sc->sc_freeqhs; 2678 sc->sc_freeqhs = sqh->next; 2679 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2680 sqh->next = NULL; 2681 return sqh; 2682 } 2683 2684 Static void 2685 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2686 { 2687 sqh->next = sc->sc_freeqhs; 2688 sc->sc_freeqhs = sqh; 2689 } 2690 2691 Static ehci_soft_qtd_t * 2692 ehci_alloc_sqtd(ehci_softc_t *sc) 2693 { 2694 ehci_soft_qtd_t *sqtd = NULL; 2695 usbd_status err; 2696 int i, offs; 2697 usb_dma_t dma; 2698 2699 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2700 2701 if (sc->sc_freeqtds == NULL) { 2702 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2703 2704 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2705 EHCI_PAGE_SIZE, &dma); 2706 #ifdef EHCI_DEBUG 2707 if (err) 2708 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2709 #endif 2710 if (err) 2711 goto done; 2712 2713 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2714 offs = i * EHCI_SQTD_SIZE; 2715 sqtd = KERNADDR(&dma, offs); 2716 sqtd->physaddr = DMAADDR(&dma, offs); 2717 sqtd->dma = dma; 2718 sqtd->offs = offs; 2719 2720 sqtd->nextqtd = sc->sc_freeqtds; 2721 sc->sc_freeqtds = sqtd; 2722 } 2723 } 2724 2725 sqtd = sc->sc_freeqtds; 2726 sc->sc_freeqtds = sqtd->nextqtd; 2727 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2728 sqtd->nextqtd = NULL; 2729 sqtd->xfer = NULL; 2730 2731 done: 2732 return sqtd; 2733 } 2734 2735 Static void 2736 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2737 { 2738 2739 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2740 2741 sqtd->nextqtd = sc->sc_freeqtds; 2742 sc->sc_freeqtds = sqtd; 2743 } 2744 2745 Static usbd_status 2746 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2747 int alen, int rd, usbd_xfer_handle xfer, 2748 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2749 { 2750 ehci_soft_qtd_t *next, *cur; 2751 ehci_physaddr_t nextphys; 2752 uint32_t qtdstatus; 2753 int len, curlen, mps; 2754 int i, tog; 2755 int pages, pageoffs; 2756 bus_size_t curoffs; 2757 vaddr_t va, va_offs; 2758 usb_dma_t *dma = &xfer->ux_dmabuf; 2759 uint16_t flags = xfer->ux_flags; 2760 paddr_t a; 2761 2762 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2763 2764 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2765 2766 len = alen; 2767 qtdstatus = EHCI_QTD_ACTIVE | 2768 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2769 EHCI_QTD_SET_CERR(3) 2770 /* IOC set below */ 2771 /* BYTES set below */ 2772 ; 2773 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 2774 tog = epipe->nexttoggle; 2775 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2776 2777 cur = ehci_alloc_sqtd(sc); 2778 *sp = cur; 2779 if (cur == NULL) 2780 goto nomem; 2781 2782 usb_syncmem(dma, 0, alen, 2783 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2784 curoffs = 0; 2785 for (;;) { 2786 /* The EHCI hardware can handle at most 5 pages. */ 2787 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2788 va_offs = EHCI_PAGE_OFFSET(va_offs); 2789 if (len-curoffs < EHCI_QTD_NBUFFERS*EHCI_PAGE_SIZE - va_offs) { 2790 /* we can handle it in this QTD */ 2791 curlen = len - curoffs; 2792 } else { 2793 /* must use multiple TDs, fill as much as possible. */ 2794 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE - va_offs; 2795 2796 /* the length must be a multiple of the max size */ 2797 curlen -= curlen % mps; 2798 USBHIST_LOG(ehcidebug, "multiple QTDs, " 2799 "curlen=%d", curlen, 0, 0, 0); 2800 KASSERT(curlen != 0); 2801 } 2802 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 2803 len, curlen, (size_t)curoffs, 0); 2804 2805 /* 2806 * Allocate another transfer if there's more data left, 2807 * or if force last short transfer flag is set and we're 2808 * allocating a multiple of the max packet size. 2809 */ 2810 2811 if (curoffs + curlen != len || 2812 ((curlen % mps) == 0 && !rd && curlen != 0 && 2813 (flags & USBD_FORCE_SHORT_XFER))) { 2814 next = ehci_alloc_sqtd(sc); 2815 if (next == NULL) 2816 goto nomem; 2817 nextphys = htole32(next->physaddr); 2818 } else { 2819 next = NULL; 2820 nextphys = EHCI_NULL; 2821 } 2822 2823 /* Find number of pages we'll be using, insert dma addresses */ 2824 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2825 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2826 pageoffs = EHCI_PAGE(curoffs); 2827 for (i = 0; i < pages; i++) { 2828 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2829 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2830 /* Cast up to avoid compiler warnings */ 2831 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2832 } 2833 2834 /* First buffer pointer requires a page offset to start at */ 2835 va = (vaddr_t)KERNADDR(dma, curoffs); 2836 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2837 2838 cur->nextqtd = next; 2839 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2840 cur->qtd.qtd_status = 2841 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2842 cur->xfer = xfer; 2843 cur->len = curlen; 2844 2845 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2846 (size_t)curoffs, (size_t)(curoffs + curlen), 0, 0); 2847 2848 /* 2849 * adjust the toggle based on the number of packets in this 2850 * qtd 2851 */ 2852 if (((curlen + mps - 1) / mps) & 1) { 2853 tog ^= 1; 2854 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2855 } 2856 if (next == NULL) 2857 break; 2858 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2859 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2860 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2861 if (len) 2862 curoffs += curlen; 2863 cur = next; 2864 } 2865 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2866 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2867 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2868 *ep = cur; 2869 epipe->nexttoggle = tog; 2870 2871 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 2872 *sp, *ep, 0, 0); 2873 2874 return USBD_NORMAL_COMPLETION; 2875 2876 nomem: 2877 /* XXX free chain */ 2878 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2879 return USBD_NOMEM; 2880 } 2881 2882 Static void 2883 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2884 ehci_soft_qtd_t *sqtdend) 2885 { 2886 ehci_soft_qtd_t *p; 2887 int i; 2888 2889 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2890 2891 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 2892 sqtd, sqtdend, 0, 0); 2893 2894 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2895 p = sqtd->nextqtd; 2896 ehci_free_sqtd(sc, sqtd); 2897 } 2898 } 2899 2900 Static ehci_soft_itd_t * 2901 ehci_alloc_itd(ehci_softc_t *sc) 2902 { 2903 struct ehci_soft_itd *itd, *freeitd; 2904 usbd_status err; 2905 int i, offs, frindex, previndex; 2906 usb_dma_t dma; 2907 2908 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2909 2910 mutex_enter(&sc->sc_lock); 2911 2912 /* 2913 * Find an itd that wasn't freed this frame or last frame. This can 2914 * discard itds that were freed before frindex wrapped around 2915 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2916 * interrupt and fiddling with list when that happens 2917 */ 2918 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2919 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2920 2921 freeitd = NULL; 2922 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2923 if (itd == NULL) 2924 break; 2925 if (itd->slot != frindex && itd->slot != previndex) { 2926 freeitd = itd; 2927 break; 2928 } 2929 } 2930 2931 if (freeitd == NULL) { 2932 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2933 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2934 EHCI_PAGE_SIZE, &dma); 2935 2936 if (err) { 2937 USBHIST_LOG(ehcidebug, 2938 "alloc returned %d", err, 0, 0, 0); 2939 mutex_exit(&sc->sc_lock); 2940 return NULL; 2941 } 2942 2943 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2944 offs = i * EHCI_ITD_SIZE; 2945 itd = KERNADDR(&dma, offs); 2946 itd->physaddr = DMAADDR(&dma, offs); 2947 itd->dma = dma; 2948 itd->offs = offs; 2949 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2950 } 2951 freeitd = LIST_FIRST(&sc->sc_freeitds); 2952 } 2953 2954 itd = freeitd; 2955 LIST_REMOVE(itd, u.free_list); 2956 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2957 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2958 sizeof(itd->itd.itd_next), 2959 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2960 2961 itd->u.frame_list.next = NULL; 2962 itd->u.frame_list.prev = NULL; 2963 itd->xfer_next = NULL; 2964 itd->slot = 0; 2965 2966 mutex_exit(&sc->sc_lock); 2967 2968 return itd; 2969 } 2970 2971 Static ehci_soft_sitd_t * 2972 ehci_alloc_sitd(ehci_softc_t *sc) 2973 { 2974 struct ehci_soft_sitd *sitd, *freesitd; 2975 usbd_status err; 2976 int i, offs, frindex, previndex; 2977 usb_dma_t dma; 2978 2979 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2980 2981 mutex_enter(&sc->sc_lock); 2982 2983 /* 2984 * Find an sitd that wasn't freed this frame or last frame. This can 2985 * discard sitds that were freed before frindex wrapped around 2986 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2987 * interrupt and fiddling with list when that happens 2988 */ 2989 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2990 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2991 2992 freesitd = NULL; 2993 LIST_FOREACH(sitd, &sc->sc_freesitds, u.free_list) { 2994 if (sitd == NULL) 2995 break; 2996 if (sitd->slot != frindex && sitd->slot != previndex) { 2997 freesitd = sitd; 2998 break; 2999 } 3000 } 3001 3002 if (freesitd == NULL) { 3003 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3004 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3005 EHCI_PAGE_SIZE, &dma); 3006 3007 if (err) { 3008 USBHIST_LOG(ehcidebug, 3009 "alloc returned %d", err, 0, 0, 0); 3010 mutex_exit(&sc->sc_lock); 3011 return NULL; 3012 } 3013 3014 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3015 offs = i * EHCI_SITD_SIZE; 3016 sitd = KERNADDR(&dma, offs); 3017 sitd->physaddr = DMAADDR(&dma, offs); 3018 sitd->dma = dma; 3019 sitd->offs = offs; 3020 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3021 } 3022 freesitd = LIST_FIRST(&sc->sc_freesitds); 3023 } 3024 3025 sitd = freesitd; 3026 LIST_REMOVE(sitd, u.free_list); 3027 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3028 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3029 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3030 BUS_DMASYNC_PREREAD); 3031 3032 sitd->u.frame_list.next = NULL; 3033 sitd->u.frame_list.prev = NULL; 3034 sitd->xfer_next = NULL; 3035 sitd->slot = 0; 3036 3037 mutex_exit(&sc->sc_lock); 3038 3039 return sitd; 3040 } 3041 3042 Static void 3043 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3044 { 3045 3046 KASSERT(mutex_owned(&sc->sc_lock)); 3047 3048 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3049 } 3050 3051 Static void 3052 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3053 { 3054 3055 KASSERT(mutex_owned(&sc->sc_lock)); 3056 3057 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3058 } 3059 3060 /****************/ 3061 3062 /* 3063 * Close a reqular pipe. 3064 * Assumes that there are no pending transactions. 3065 */ 3066 Static void 3067 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3068 { 3069 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3070 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3071 ehci_soft_qh_t *sqh = epipe->sqh; 3072 3073 KASSERT(mutex_owned(&sc->sc_lock)); 3074 3075 ehci_rem_qh(sc, sqh, head); 3076 ehci_free_sqh(sc, epipe->sqh); 3077 } 3078 3079 /* 3080 * Abort a device request. 3081 * If this routine is called at splusb() it guarantees that the request 3082 * will be removed from the hardware scheduling and that the callback 3083 * for it will be called with USBD_CANCELLED status. 3084 * It's impossible to guarantee that the requested transfer will not 3085 * have happened since the hardware runs concurrently. 3086 * If the transaction has already happened we rely on the ordinary 3087 * interrupt processing to process it. 3088 * XXX This is most probably wrong. 3089 * XXXMRG this doesn't make sense anymore. 3090 */ 3091 Static void 3092 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3093 { 3094 #define exfer EXFER(xfer) 3095 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3096 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3097 ehci_soft_qh_t *sqh = epipe->sqh; 3098 ehci_soft_qtd_t *sqtd; 3099 ehci_physaddr_t cur; 3100 uint32_t qhstatus; 3101 int hit; 3102 int wake; 3103 3104 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3105 3106 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3107 3108 KASSERT(mutex_owned(&sc->sc_lock)); 3109 ASSERT_SLEEPABLE(); 3110 3111 if (sc->sc_dying) { 3112 /* If we're dying, just do the software part. */ 3113 xfer->ux_status = status; /* make software ignore it */ 3114 callout_stop(&xfer->ux_callout); 3115 usb_transfer_complete(xfer); 3116 return; 3117 } 3118 3119 /* 3120 * If an abort is already in progress then just wait for it to 3121 * complete and return. 3122 */ 3123 if (xfer->ux_hcflags & UXFER_ABORTING) { 3124 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3125 #ifdef DIAGNOSTIC 3126 if (status == USBD_TIMEOUT) 3127 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3128 #endif 3129 /* Override the status which might be USBD_TIMEOUT. */ 3130 xfer->ux_status = status; 3131 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3132 0, 0, 0, 0); 3133 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3134 while (xfer->ux_hcflags & UXFER_ABORTING) 3135 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3136 return; 3137 } 3138 xfer->ux_hcflags |= UXFER_ABORTING; 3139 3140 /* 3141 * Step 1: Make interrupt routine and hardware ignore xfer. 3142 */ 3143 xfer->ux_status = status; /* make software ignore it */ 3144 callout_stop(&xfer->ux_callout); 3145 3146 usb_syncmem(&sqh->dma, 3147 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3148 sizeof(sqh->qh.qh_qtd.qtd_status), 3149 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3150 qhstatus = sqh->qh.qh_qtd.qtd_status; 3151 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3152 usb_syncmem(&sqh->dma, 3153 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3154 sizeof(sqh->qh.qh_qtd.qtd_status), 3155 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3156 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3157 usb_syncmem(&sqtd->dma, 3158 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3159 sizeof(sqtd->qtd.qtd_status), 3160 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3161 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3162 usb_syncmem(&sqtd->dma, 3163 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3164 sizeof(sqtd->qtd.qtd_status), 3165 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3166 if (sqtd == exfer->ex_sqtdend) 3167 break; 3168 } 3169 3170 /* 3171 * Step 2: Wait until we know hardware has finished any possible 3172 * use of the xfer. Also make sure the soft interrupt routine 3173 * has run. 3174 */ 3175 ehci_sync_hc(sc); 3176 sc->sc_softwake = 1; 3177 usb_schedsoftintr(&sc->sc_bus); 3178 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3179 3180 /* 3181 * Step 3: Remove any vestiges of the xfer from the hardware. 3182 * The complication here is that the hardware may have executed 3183 * beyond the xfer we're trying to abort. So as we're scanning 3184 * the TDs of this xfer we check if the hardware points to 3185 * any of them. 3186 */ 3187 3188 usb_syncmem(&sqh->dma, 3189 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3190 sizeof(sqh->qh.qh_curqtd), 3191 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3192 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3193 hit = 0; 3194 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3195 hit |= cur == sqtd->physaddr; 3196 if (sqtd == exfer->ex_sqtdend) 3197 break; 3198 } 3199 sqtd = sqtd->nextqtd; 3200 /* Zap curqtd register if hardware pointed inside the xfer. */ 3201 if (hit && sqtd != NULL) { 3202 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3203 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3204 usb_syncmem(&sqh->dma, 3205 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3206 sizeof(sqh->qh.qh_curqtd), 3207 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3208 sqh->qh.qh_qtd.qtd_status = qhstatus; 3209 usb_syncmem(&sqh->dma, 3210 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3211 sizeof(sqh->qh.qh_qtd.qtd_status), 3212 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3213 } else { 3214 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3215 } 3216 3217 /* 3218 * Step 4: Execute callback. 3219 */ 3220 #ifdef DIAGNOSTIC 3221 exfer->ex_isdone = 1; 3222 #endif 3223 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3224 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3225 usb_transfer_complete(xfer); 3226 if (wake) { 3227 cv_broadcast(&xfer->ux_hccv); 3228 } 3229 3230 KASSERT(mutex_owned(&sc->sc_lock)); 3231 #undef exfer 3232 } 3233 3234 Static void 3235 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3236 { 3237 ehci_isoc_trans_t trans_status; 3238 struct ehci_pipe *epipe; 3239 struct ehci_xfer *exfer; 3240 ehci_softc_t *sc; 3241 struct ehci_soft_itd *itd; 3242 struct ehci_soft_sitd *sitd; 3243 int i, wake; 3244 3245 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3246 3247 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3248 exfer = EXFER(xfer); 3249 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3250 3251 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3252 3253 KASSERT(mutex_owned(&sc->sc_lock)); 3254 3255 if (sc->sc_dying) { 3256 xfer->ux_status = status; 3257 callout_stop(&xfer->ux_callout); 3258 usb_transfer_complete(xfer); 3259 return; 3260 } 3261 3262 if (xfer->ux_hcflags & UXFER_ABORTING) { 3263 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3264 3265 #ifdef DIAGNOSTIC 3266 if (status == USBD_TIMEOUT) 3267 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3268 #endif 3269 3270 xfer->ux_status = status; 3271 USBHIST_LOG(ehcidebug, 3272 "waiting for abort to finish", 0, 0, 0, 0); 3273 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3274 while (xfer->ux_hcflags & UXFER_ABORTING) 3275 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3276 goto done; 3277 } 3278 xfer->ux_hcflags |= UXFER_ABORTING; 3279 3280 xfer->ux_status = status; 3281 callout_stop(&xfer->ux_callout); 3282 3283 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3284 for (itd = exfer->ex_itdstart; itd != NULL; 3285 itd = itd->xfer_next) { 3286 usb_syncmem(&itd->dma, 3287 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3288 sizeof(itd->itd.itd_ctl), 3289 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3290 3291 for (i = 0; i < 8; i++) { 3292 trans_status = le32toh(itd->itd.itd_ctl[i]); 3293 trans_status &= ~EHCI_ITD_ACTIVE; 3294 itd->itd.itd_ctl[i] = htole32(trans_status); 3295 } 3296 3297 usb_syncmem(&itd->dma, 3298 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3299 sizeof(itd->itd.itd_ctl), 3300 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3301 } 3302 } else { 3303 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3304 sitd = sitd->xfer_next) { 3305 usb_syncmem(&sitd->dma, 3306 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3307 sizeof(sitd->sitd.sitd_buffer), 3308 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3309 3310 trans_status = le32toh(sitd->sitd.sitd_trans); 3311 trans_status &= ~EHCI_SITD_ACTIVE; 3312 sitd->sitd.sitd_trans = htole32(trans_status); 3313 3314 usb_syncmem(&sitd->dma, 3315 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3316 sizeof(sitd->sitd.sitd_buffer), 3317 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3318 } 3319 } 3320 3321 sc->sc_softwake = 1; 3322 usb_schedsoftintr(&sc->sc_bus); 3323 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3324 3325 #ifdef DIAGNOSTIC 3326 exfer->ex_isdone = 1; 3327 #endif 3328 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3329 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3330 usb_transfer_complete(xfer); 3331 if (wake) { 3332 cv_broadcast(&xfer->ux_hccv); 3333 } 3334 3335 done: 3336 KASSERT(mutex_owned(&sc->sc_lock)); 3337 return; 3338 } 3339 3340 Static void 3341 ehci_timeout(void *addr) 3342 { 3343 struct ehci_xfer *exfer = addr; 3344 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->ex_xfer.ux_pipe; 3345 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3346 3347 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3348 3349 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3350 #ifdef EHCI_DEBUG 3351 if (ehcidebug > 1) 3352 usbd_dump_pipe(exfer->ex_xfer.ux_pipe); 3353 #endif 3354 3355 if (sc->sc_dying) { 3356 mutex_enter(&sc->sc_lock); 3357 ehci_abort_xfer(&exfer->ex_xfer, USBD_TIMEOUT); 3358 mutex_exit(&sc->sc_lock); 3359 return; 3360 } 3361 3362 /* Execute the abort in a process context. */ 3363 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, addr, 3364 USB_TASKQ_MPSAFE); 3365 usb_add_task(exfer->ex_xfer.ux_pipe->up_dev, &exfer->ex_aborttask, 3366 USB_TASKQ_HC); 3367 } 3368 3369 Static void 3370 ehci_timeout_task(void *addr) 3371 { 3372 usbd_xfer_handle xfer = addr; 3373 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3374 3375 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3376 3377 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3378 3379 mutex_enter(&sc->sc_lock); 3380 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3381 mutex_exit(&sc->sc_lock); 3382 } 3383 3384 /************************/ 3385 3386 Static usbd_status 3387 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3388 { 3389 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3390 usbd_status err; 3391 3392 /* Insert last in queue. */ 3393 mutex_enter(&sc->sc_lock); 3394 err = usb_insert_transfer(xfer); 3395 mutex_exit(&sc->sc_lock); 3396 if (err) 3397 return err; 3398 3399 /* Pipe isn't running, start first */ 3400 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3401 } 3402 3403 Static usbd_status 3404 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3405 { 3406 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3407 usbd_status err; 3408 3409 if (sc->sc_dying) 3410 return USBD_IOERROR; 3411 3412 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3413 3414 err = ehci_device_request(xfer); 3415 if (err) { 3416 return err; 3417 } 3418 3419 if (sc->sc_bus.ub_usepolling) 3420 ehci_waitintr(sc, xfer); 3421 3422 return USBD_IN_PROGRESS; 3423 } 3424 3425 Static void 3426 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3427 { 3428 struct ehci_xfer *ex = EXFER(xfer); 3429 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3430 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3431 usb_device_request_t *req = &xfer->ux_request; 3432 int len = UGETW(req->wLength); 3433 int rd = req->bmRequestType & UT_READ; 3434 3435 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3436 3437 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3438 3439 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3440 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3441 3442 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3443 ehci_del_intr_list(sc, ex); /* remove from active list */ 3444 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3445 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, 3446 BUS_DMASYNC_POSTWRITE); 3447 if (len) 3448 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3449 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3450 } 3451 3452 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3453 } 3454 3455 /* Abort a device control request. */ 3456 Static void 3457 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3458 { 3459 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3460 3461 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3462 ehci_abort_xfer(xfer, USBD_CANCELLED); 3463 } 3464 3465 /* Close a device control pipe. */ 3466 Static void 3467 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3468 { 3469 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3470 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3471 3472 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3473 3474 KASSERT(mutex_owned(&sc->sc_lock)); 3475 3476 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3477 3478 ehci_close_pipe(pipe, sc->sc_async_head); 3479 } 3480 3481 Static usbd_status 3482 ehci_device_request(usbd_xfer_handle xfer) 3483 { 3484 #define exfer EXFER(xfer) 3485 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3486 usb_device_request_t *req = &xfer->ux_request; 3487 usbd_device_handle dev = epipe->pipe.up_dev; 3488 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3489 ehci_soft_qtd_t *setup, *stat, *next; 3490 ehci_soft_qh_t *sqh; 3491 int isread; 3492 int len; 3493 usbd_status err; 3494 3495 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3496 3497 isread = req->bmRequestType & UT_READ; 3498 len = UGETW(req->wLength); 3499 3500 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3501 "wValue=0x%04x, wIndex=0x%04x", 3502 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3503 UGETW(req->wIndex)); 3504 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3505 len, dev->ud_addr, 3506 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3507 3508 setup = ehci_alloc_sqtd(sc); 3509 if (setup == NULL) { 3510 err = USBD_NOMEM; 3511 goto bad1; 3512 } 3513 stat = ehci_alloc_sqtd(sc); 3514 if (stat == NULL) { 3515 err = USBD_NOMEM; 3516 goto bad2; 3517 } 3518 3519 mutex_enter(&sc->sc_lock); 3520 3521 sqh = epipe->sqh; 3522 3523 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3524 "address QH %d pipe %d\n", 3525 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3526 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3527 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3528 "MPS QH %d pipe %d\n", 3529 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3530 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3531 3532 /* Set up data transaction */ 3533 if (len != 0) { 3534 ehci_soft_qtd_t *end; 3535 3536 /* Start toggle at 1. */ 3537 epipe->nexttoggle = 1; 3538 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3539 &next, &end); 3540 if (err) 3541 goto bad3; 3542 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3543 end->nextqtd = stat; 3544 end->qtd.qtd_next = end->qtd.qtd_altnext = 3545 htole32(stat->physaddr); 3546 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3547 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3548 } else { 3549 next = stat; 3550 } 3551 3552 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof *req); 3553 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof *req, BUS_DMASYNC_PREWRITE); 3554 3555 /* Clear toggle */ 3556 setup->qtd.qtd_status = htole32( 3557 EHCI_QTD_ACTIVE | 3558 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3559 EHCI_QTD_SET_CERR(3) | 3560 EHCI_QTD_SET_TOGGLE(0) | 3561 EHCI_QTD_SET_BYTES(sizeof *req) 3562 ); 3563 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3564 setup->qtd.qtd_buffer_hi[0] = 0; 3565 setup->nextqtd = next; 3566 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3567 setup->xfer = xfer; 3568 setup->len = sizeof *req; 3569 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3570 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3571 3572 stat->qtd.qtd_status = htole32( 3573 EHCI_QTD_ACTIVE | 3574 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3575 EHCI_QTD_SET_CERR(3) | 3576 EHCI_QTD_SET_TOGGLE(1) | 3577 EHCI_QTD_IOC 3578 ); 3579 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3580 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3581 stat->nextqtd = NULL; 3582 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3583 stat->xfer = xfer; 3584 stat->len = 0; 3585 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3586 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3587 3588 #ifdef EHCI_DEBUG 3589 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3590 ehci_dump_sqh(sqh); 3591 ehci_dump_sqtds(setup); 3592 #endif 3593 3594 exfer->ex_sqtdstart = setup; 3595 exfer->ex_sqtdend = stat; 3596 #ifdef DIAGNOSTIC 3597 if (!exfer->ex_isdone) { 3598 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3599 } 3600 exfer->ex_isdone = 0; 3601 #endif 3602 3603 /* Insert qTD in QH list. */ 3604 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3605 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3606 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3607 ehci_timeout, xfer); 3608 } 3609 ehci_add_intr_list(sc, exfer); 3610 xfer->ux_status = USBD_IN_PROGRESS; 3611 mutex_exit(&sc->sc_lock); 3612 3613 #ifdef EHCI_DEBUG 3614 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3615 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3616 // delay(10000); 3617 ehci_dump_regs(sc); 3618 ehci_dump_sqh(sc->sc_async_head); 3619 ehci_dump_sqh(sqh); 3620 ehci_dump_sqtds(setup); 3621 #endif 3622 3623 return USBD_NORMAL_COMPLETION; 3624 3625 bad3: 3626 mutex_exit(&sc->sc_lock); 3627 ehci_free_sqtd(sc, stat); 3628 bad2: 3629 ehci_free_sqtd(sc, setup); 3630 bad1: 3631 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3632 mutex_enter(&sc->sc_lock); 3633 xfer->ux_status = err; 3634 usb_transfer_complete(xfer); 3635 mutex_exit(&sc->sc_lock); 3636 return err; 3637 #undef exfer 3638 } 3639 3640 /* 3641 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3642 * qTD status, or miss signalling occasionally under heavy load. If the host 3643 * machine is too fast, we we can miss transaction completion - when we scan 3644 * the active list the transaction still seems to be active. This generally 3645 * exhibits itself as a umass stall that never recovers. 3646 * 3647 * We work around this behaviour by setting up this callback after any softintr 3648 * that completes with transactions still pending, giving us another chance to 3649 * check for completion after the writeback has taken place. 3650 */ 3651 Static void 3652 ehci_intrlist_timeout(void *arg) 3653 { 3654 ehci_softc_t *sc = arg; 3655 3656 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3657 3658 usb_schedsoftintr(&sc->sc_bus); 3659 } 3660 3661 /************************/ 3662 3663 Static usbd_status 3664 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3665 { 3666 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3667 usbd_status err; 3668 3669 /* Insert last in queue. */ 3670 mutex_enter(&sc->sc_lock); 3671 err = usb_insert_transfer(xfer); 3672 mutex_exit(&sc->sc_lock); 3673 if (err) 3674 return err; 3675 3676 /* Pipe isn't running, start first */ 3677 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3678 } 3679 3680 Static usbd_status 3681 ehci_device_bulk_start(usbd_xfer_handle xfer) 3682 { 3683 #define exfer EXFER(xfer) 3684 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3685 usbd_device_handle dev = epipe->pipe.up_dev; 3686 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3687 ehci_soft_qtd_t *data, *dataend; 3688 ehci_soft_qh_t *sqh; 3689 usbd_status err; 3690 int len, isread, endpt; 3691 3692 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3693 3694 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3695 xfer, xfer->ux_length, xfer->ux_flags, 0); 3696 3697 if (sc->sc_dying) 3698 return USBD_IOERROR; 3699 3700 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3701 3702 mutex_enter(&sc->sc_lock); 3703 3704 len = xfer->ux_length; 3705 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3706 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3707 sqh = epipe->sqh; 3708 3709 epipe->u.bulk.length = len; 3710 3711 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3712 &dataend); 3713 if (err) { 3714 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3715 xfer->ux_status = err; 3716 usb_transfer_complete(xfer); 3717 mutex_exit(&sc->sc_lock); 3718 return err; 3719 } 3720 3721 #ifdef EHCI_DEBUG 3722 USBHIST_LOGN(ehcidebug, 5, "data(1):", 0, 0, 0, 0); 3723 ehci_dump_sqh(sqh); 3724 ehci_dump_sqtds(data); 3725 #endif 3726 3727 /* Set up interrupt info. */ 3728 exfer->ex_sqtdstart = data; 3729 exfer->ex_sqtdend = dataend; 3730 #ifdef DIAGNOSTIC 3731 if (!exfer->ex_isdone) { 3732 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3733 } 3734 exfer->ex_isdone = 0; 3735 #endif 3736 3737 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3738 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3739 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3740 ehci_timeout, xfer); 3741 } 3742 ehci_add_intr_list(sc, exfer); 3743 xfer->ux_status = USBD_IN_PROGRESS; 3744 mutex_exit(&sc->sc_lock); 3745 3746 #ifdef EHCI_DEBUG 3747 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3748 // delay(10000); 3749 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3750 ehci_dump_regs(sc); 3751 #if 0 3752 printf("async_head:\n"); 3753 ehci_dump_sqh(sc->sc_async_head); 3754 #endif 3755 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3756 ehci_dump_sqh(sqh); 3757 ehci_dump_sqtds(data); 3758 #endif 3759 3760 if (sc->sc_bus.ub_usepolling) 3761 ehci_waitintr(sc, xfer); 3762 3763 return USBD_IN_PROGRESS; 3764 #undef exfer 3765 } 3766 3767 Static void 3768 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3769 { 3770 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3771 3772 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3773 ehci_abort_xfer(xfer, USBD_CANCELLED); 3774 } 3775 3776 /* 3777 * Close a device bulk pipe. 3778 */ 3779 Static void 3780 ehci_device_bulk_close(usbd_pipe_handle pipe) 3781 { 3782 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3783 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3784 3785 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3786 3787 KASSERT(mutex_owned(&sc->sc_lock)); 3788 3789 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3790 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3791 ehci_close_pipe(pipe, sc->sc_async_head); 3792 } 3793 3794 Static void 3795 ehci_device_bulk_done(usbd_xfer_handle xfer) 3796 { 3797 struct ehci_xfer *ex = EXFER(xfer); 3798 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3799 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3800 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3801 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3802 3803 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3804 3805 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3806 xfer, xfer->ux_actlen, 0, 0); 3807 3808 KASSERT(mutex_owned(&sc->sc_lock)); 3809 3810 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3811 ehci_del_intr_list(sc, ex); /* remove from active list */ 3812 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3813 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3814 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3815 } 3816 3817 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3818 } 3819 3820 /************************/ 3821 3822 Static usbd_status 3823 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3824 { 3825 struct ehci_soft_islot *isp; 3826 int islot, lev; 3827 3828 /* Find a poll rate that is large enough. */ 3829 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3830 if (EHCI_ILEV_IVAL(lev) <= ival) 3831 break; 3832 3833 /* Pick an interrupt slot at the right level. */ 3834 /* XXX could do better than picking at random */ 3835 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3836 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3837 3838 sqh->islot = islot; 3839 isp = &sc->sc_islots[islot]; 3840 mutex_enter(&sc->sc_lock); 3841 ehci_add_qh(sc, sqh, isp->sqh); 3842 mutex_exit(&sc->sc_lock); 3843 3844 return USBD_NORMAL_COMPLETION; 3845 } 3846 3847 Static usbd_status 3848 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3849 { 3850 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3851 usbd_status err; 3852 3853 /* Insert last in queue. */ 3854 mutex_enter(&sc->sc_lock); 3855 err = usb_insert_transfer(xfer); 3856 mutex_exit(&sc->sc_lock); 3857 if (err) 3858 return err; 3859 3860 /* 3861 * Pipe isn't running (otherwise err would be USBD_INPROG), 3862 * so start it first. 3863 */ 3864 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3865 } 3866 3867 Static usbd_status 3868 ehci_device_intr_start(usbd_xfer_handle xfer) 3869 { 3870 #define exfer EXFER(xfer) 3871 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3872 usbd_device_handle dev = xfer->ux_pipe->up_dev; 3873 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3874 ehci_soft_qtd_t *data, *dataend; 3875 ehci_soft_qh_t *sqh; 3876 usbd_status err; 3877 int len, isread, endpt; 3878 3879 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3880 3881 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3882 xfer, xfer->ux_length, xfer->ux_flags, 0); 3883 3884 if (sc->sc_dying) 3885 return USBD_IOERROR; 3886 3887 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3888 3889 mutex_enter(&sc->sc_lock); 3890 3891 len = xfer->ux_length; 3892 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3893 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3894 sqh = epipe->sqh; 3895 3896 epipe->u.intr.length = len; 3897 3898 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3899 &dataend); 3900 if (err) { 3901 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3902 xfer->ux_status = err; 3903 usb_transfer_complete(xfer); 3904 mutex_exit(&sc->sc_lock); 3905 return err; 3906 } 3907 3908 #ifdef EHCI_DEBUG 3909 USBHIST_LOGN(ehcidebug, 5, "data(1)", 0, 0, 0, 0); 3910 ehci_dump_sqh(sqh); 3911 ehci_dump_sqtds(data); 3912 #endif 3913 3914 /* Set up interrupt info. */ 3915 exfer->ex_sqtdstart = data; 3916 exfer->ex_sqtdend = dataend; 3917 #ifdef DIAGNOSTIC 3918 if (!exfer->ex_isdone) { 3919 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3920 } 3921 exfer->ex_isdone = 0; 3922 #endif 3923 3924 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3925 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3926 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3927 ehci_timeout, xfer); 3928 } 3929 ehci_add_intr_list(sc, exfer); 3930 xfer->ux_status = USBD_IN_PROGRESS; 3931 mutex_exit(&sc->sc_lock); 3932 3933 #ifdef EHCI_DEBUG 3934 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3935 // delay(10000); 3936 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3937 ehci_dump_regs(sc); 3938 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3939 ehci_dump_sqh(sqh); 3940 ehci_dump_sqtds(data); 3941 #endif 3942 3943 if (sc->sc_bus.ub_usepolling) 3944 ehci_waitintr(sc, xfer); 3945 3946 return USBD_IN_PROGRESS; 3947 #undef exfer 3948 } 3949 3950 Static void 3951 ehci_device_intr_abort(usbd_xfer_handle xfer) 3952 { 3953 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3954 3955 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3956 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3957 3958 /* 3959 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3960 * async doorbell. That's dependent on the async list, wheras 3961 * intr xfers are periodic, should not use this? 3962 */ 3963 ehci_abort_xfer(xfer, USBD_CANCELLED); 3964 } 3965 3966 Static void 3967 ehci_device_intr_close(usbd_pipe_handle pipe) 3968 { 3969 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3970 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3971 struct ehci_soft_islot *isp; 3972 3973 KASSERT(mutex_owned(&sc->sc_lock)); 3974 3975 isp = &sc->sc_islots[epipe->sqh->islot]; 3976 ehci_close_pipe(pipe, isp->sqh); 3977 } 3978 3979 Static void 3980 ehci_device_intr_done(usbd_xfer_handle xfer) 3981 { 3982 #define exfer EXFER(xfer) 3983 struct ehci_xfer *ex = EXFER(xfer); 3984 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3985 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3986 ehci_soft_qtd_t *data, *dataend; 3987 ehci_soft_qh_t *sqh; 3988 usbd_status err; 3989 int len, isread, endpt; 3990 3991 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3992 3993 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3994 xfer, xfer->ux_actlen, 0, 0); 3995 3996 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3997 3998 if (xfer->ux_pipe->up_repeat) { 3999 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 4000 4001 len = epipe->u.intr.length; 4002 xfer->ux_length = len; 4003 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4004 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4005 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4006 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4007 sqh = epipe->sqh; 4008 4009 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4010 &data, &dataend); 4011 if (err) { 4012 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4013 xfer->ux_status = err; 4014 return; 4015 } 4016 4017 /* Set up interrupt info. */ 4018 exfer->ex_sqtdstart = data; 4019 exfer->ex_sqtdend = dataend; 4020 #ifdef DIAGNOSTIC 4021 if (!exfer->ex_isdone) { 4022 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", 4023 exfer, 0, 0, 0); 4024 printf("ehci_device_intr_done: not done, ex=%p\n", 4025 exfer); 4026 } 4027 exfer->ex_isdone = 0; 4028 #endif 4029 4030 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4031 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4032 callout_reset(&xfer->ux_callout, 4033 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4034 } 4035 4036 xfer->ux_status = USBD_IN_PROGRESS; 4037 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4038 ehci_del_intr_list(sc, ex); /* remove from active list */ 4039 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 4040 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4041 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4042 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4043 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4044 } 4045 #undef exfer 4046 } 4047 4048 /************************/ 4049 4050 Static usbd_status 4051 ehci_device_fs_isoc_transfer(usbd_xfer_handle xfer) 4052 { 4053 usbd_status err; 4054 4055 err = usb_insert_transfer(xfer); 4056 if (err && err != USBD_IN_PROGRESS) 4057 return err; 4058 4059 return ehci_device_fs_isoc_start(xfer); 4060 } 4061 4062 Static usbd_status 4063 ehci_device_fs_isoc_start(usbd_xfer_handle xfer) 4064 { 4065 struct ehci_pipe *epipe; 4066 usbd_device_handle dev; 4067 ehci_softc_t *sc; 4068 struct ehci_xfer *exfer; 4069 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4070 usb_dma_t *dma_buf; 4071 int i, j, k, frames; 4072 int offs, total_length; 4073 int frindex; 4074 u_int huba, dir; 4075 4076 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4077 4078 start = NULL; 4079 prev = NULL; 4080 sitd = NULL; 4081 total_length = 0; 4082 exfer = (struct ehci_xfer *) xfer; 4083 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4084 dev = xfer->ux_pipe->up_dev; 4085 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4086 4087 /* 4088 * To allow continuous transfers, above we start all transfers 4089 * immediately. However, we're still going to get usbd_start_next call 4090 * this when another xfer completes. So, check if this is already 4091 * in progress or not 4092 */ 4093 4094 if (exfer->ex_sitdstart != NULL) 4095 return USBD_IN_PROGRESS; 4096 4097 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4098 xfer, xfer->ux_length, xfer->ux_flags, 0); 4099 4100 if (sc->sc_dying) 4101 return USBD_IOERROR; 4102 4103 /* 4104 * To avoid complication, don't allow a request right now that'll span 4105 * the entire frame table. To within 4 frames, to allow some leeway 4106 * on either side of where the hc currently is. 4107 */ 4108 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4109 xfer->ux_nframes >= sc->sc_flsize - 4) { 4110 printf("ehci: isoc descriptor requested that spans the entire" 4111 "frametable, too many frames\n"); 4112 return USBD_INVAL; 4113 } 4114 4115 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4116 4117 #ifdef DIAGNOSTIC 4118 if (!exfer->ex_isdone) 4119 printf("ehci_device_fs_isoc_start: not done, ex = %p\n", exfer); 4120 exfer->ex_isdone = 0; 4121 #endif 4122 4123 /* 4124 * Step 1: Allocate and initialize sitds. 4125 */ 4126 4127 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4128 if (i > 16 || i == 0) { 4129 /* Spec page 271 says intervals > 16 are invalid */ 4130 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4131 4132 return USBD_INVAL; 4133 } 4134 4135 frames = xfer->ux_nframes; 4136 4137 if (frames == 0) { 4138 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4139 4140 return USBD_INVAL; 4141 } 4142 4143 dma_buf = &xfer->ux_dmabuf; 4144 offs = 0; 4145 4146 for (i = 0; i < frames; i++) { 4147 sitd = ehci_alloc_sitd(sc); 4148 4149 if (prev) 4150 prev->xfer_next = sitd; 4151 else 4152 start = sitd; 4153 4154 #ifdef DIAGNOSTIC 4155 if (xfer->ux_frlengths[i] > 0x3ff) { 4156 printf("ehci: invalid frame length\n"); 4157 xfer->ux_frlengths[i] = 0x3ff; 4158 } 4159 #endif 4160 4161 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4162 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4163 4164 /* Set page0 index and offset. */ 4165 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4166 4167 total_length += xfer->ux_frlengths[i]; 4168 offs += xfer->ux_frlengths[i]; 4169 4170 sitd->sitd.sitd_buffer[1] = 4171 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4172 4173 huba = dev->ud_myhsport->up_parent->ud_addr; 4174 4175 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4176 // Set hub address to 0 if embedded TT is used. 4177 if (huba == sc->sc_addr) 4178 huba = 0; 4179 } 4180 */ 4181 4182 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4183 dir = UE_GET_DIR(k) ? 1 : 0; 4184 sitd->sitd.sitd_endp = 4185 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4186 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4187 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4188 EHCI_SITD_SET_HUBA(huba) | 4189 EHCI_SITD_SET_DIR(dir)); 4190 4191 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4192 4193 /* XXX */ 4194 u_char sa, sb; 4195 u_int temp, tlen; 4196 sa = 0; 4197 4198 if (dir == 0) { /* OUT */ 4199 temp = 0; 4200 tlen = xfer->ux_frlengths[i]; 4201 if (tlen <= 188) { 4202 temp |= 1; /* T-count = 1, TP = ALL */ 4203 tlen = 1; 4204 } else { 4205 tlen += 187; 4206 tlen /= 188; 4207 temp |= tlen; /* T-count = [1..6] */ 4208 temp |= 8; /* TP = Begin */ 4209 } 4210 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4211 4212 tlen += sa; 4213 4214 if (tlen >= 8) { 4215 sb = 0; 4216 } else { 4217 sb = (1 << tlen); 4218 } 4219 4220 sa = (1 << sa); 4221 sa = (sb - sa) & 0x3F; 4222 sb = 0; 4223 } else { 4224 sb = (-(4 << sa)) & 0xFE; 4225 sa = (1 << sa) & 0x3F; 4226 sa = 0x01; 4227 sb = 0xfc; 4228 } 4229 4230 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4231 EHCI_SITD_SET_CMASK(sb)); 4232 4233 prev = sitd; 4234 } /* End of frame */ 4235 4236 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4237 4238 stop = sitd; 4239 stop->xfer_next = NULL; 4240 4241 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4242 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4243 4244 /* 4245 * Part 2: Transfer descriptors have now been set up, now they must 4246 * be scheduled into the periodic frame list. Erk. Not wanting to 4247 * complicate matters, transfer is denied if the transfer spans 4248 * more than the period frame list. 4249 */ 4250 4251 mutex_enter(&sc->sc_lock); 4252 4253 /* Start inserting frames */ 4254 if (epipe->u.isoc.cur_xfers > 0) { 4255 frindex = epipe->u.isoc.next_frame; 4256 } else { 4257 frindex = EOREAD4(sc, EHCI_FRINDEX); 4258 frindex = frindex >> 3; /* Erase microframe index */ 4259 frindex += 2; 4260 } 4261 4262 if (frindex >= sc->sc_flsize) 4263 frindex &= (sc->sc_flsize - 1); 4264 4265 /* Whats the frame interval? */ 4266 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4267 4268 sitd = start; 4269 for (j = 0; j < frames; j++) { 4270 if (sitd == NULL) 4271 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4272 4273 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4274 if (sitd->sitd.sitd_next == 0) 4275 /* FIXME: frindex table gets initialized to NULL 4276 * or EHCI_NULL? */ 4277 sitd->sitd.sitd_next = EHCI_NULL; 4278 4279 usb_syncmem(&sitd->dma, 4280 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4281 sizeof(ehci_sitd_t), 4282 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4283 4284 sc->sc_flist[frindex] = 4285 htole32(EHCI_LINK_SITD | sitd->physaddr); 4286 4287 usb_syncmem(&sc->sc_fldma, 4288 sizeof(ehci_link_t) * frindex, 4289 sizeof(ehci_link_t), 4290 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4291 4292 sitd->u.frame_list.next = sc->sc_softsitds[frindex]; 4293 sc->sc_softsitds[frindex] = sitd; 4294 if (sitd->u.frame_list.next != NULL) 4295 sitd->u.frame_list.next->u.frame_list.prev = sitd; 4296 sitd->slot = frindex; 4297 sitd->u.frame_list.prev = NULL; 4298 4299 frindex += i; 4300 if (frindex >= sc->sc_flsize) 4301 frindex -= sc->sc_flsize; 4302 4303 sitd = sitd->xfer_next; 4304 } 4305 4306 epipe->u.isoc.cur_xfers++; 4307 epipe->u.isoc.next_frame = frindex; 4308 4309 exfer->ex_sitdstart = start; 4310 exfer->ex_sitdend = stop; 4311 4312 ehci_add_intr_list(sc, exfer); 4313 xfer->ux_status = USBD_IN_PROGRESS; 4314 xfer->ux_done = 0; 4315 4316 mutex_exit(&sc->sc_lock); 4317 4318 if (sc->sc_bus.ub_usepolling) { 4319 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4320 ehci_waitintr(sc, xfer); 4321 } 4322 4323 return USBD_IN_PROGRESS; 4324 } 4325 4326 Static void 4327 ehci_device_fs_isoc_abort(usbd_xfer_handle xfer) 4328 { 4329 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4330 4331 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4332 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4333 } 4334 4335 Static void 4336 ehci_device_fs_isoc_close(usbd_pipe_handle pipe) 4337 { 4338 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4339 4340 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4341 } 4342 4343 Static void 4344 ehci_device_fs_isoc_done(usbd_xfer_handle xfer) 4345 { 4346 struct ehci_xfer *exfer; 4347 ehci_softc_t *sc; 4348 struct ehci_pipe *epipe; 4349 4350 exfer = EXFER(xfer); 4351 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4352 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4353 4354 KASSERT(mutex_owned(&sc->sc_lock)); 4355 4356 epipe->u.isoc.cur_xfers--; 4357 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4358 ehci_del_intr_list(sc, exfer); 4359 ehci_rem_free_sitd_chain(sc, exfer); 4360 } 4361 4362 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4363 BUS_DMASYNC_POSTREAD); 4364 } 4365 Static usbd_status 4366 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 4367 { 4368 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4369 usbd_status err; 4370 4371 mutex_enter(&sc->sc_lock); 4372 err = usb_insert_transfer(xfer); 4373 mutex_exit(&sc->sc_lock); 4374 if (err && err != USBD_IN_PROGRESS) 4375 return err; 4376 4377 return ehci_device_isoc_start(xfer); 4378 } 4379 4380 Static usbd_status 4381 ehci_device_isoc_start(usbd_xfer_handle xfer) 4382 { 4383 struct ehci_pipe *epipe; 4384 ehci_softc_t *sc; 4385 struct ehci_xfer *exfer; 4386 ehci_soft_itd_t *itd, *prev, *start, *stop; 4387 usb_dma_t *dma_buf; 4388 int i, j, k, frames, uframes, ufrperframe; 4389 int trans_count, offs, total_length; 4390 int frindex; 4391 4392 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4393 4394 start = NULL; 4395 prev = NULL; 4396 itd = NULL; 4397 trans_count = 0; 4398 total_length = 0; 4399 exfer = (struct ehci_xfer *) xfer; 4400 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4401 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4402 4403 /* 4404 * To allow continuous transfers, above we start all transfers 4405 * immediately. However, we're still going to get usbd_start_next call 4406 * this when another xfer completes. So, check if this is already 4407 * in progress or not 4408 */ 4409 4410 if (exfer->ex_itdstart != NULL) 4411 return USBD_IN_PROGRESS; 4412 4413 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4414 xfer, xfer->ux_length, xfer->ux_flags, 0); 4415 4416 if (sc->sc_dying) 4417 return USBD_IOERROR; 4418 4419 /* 4420 * To avoid complication, don't allow a request right now that'll span 4421 * the entire frame table. To within 4 frames, to allow some leeway 4422 * on either side of where the hc currently is. 4423 */ 4424 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4425 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4426 USBHIST_LOG(ehcidebug, 4427 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4428 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4429 return USBD_INVAL; 4430 } 4431 4432 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4433 4434 #ifdef DIAGNOSTIC 4435 if (!exfer->ex_isdone) { 4436 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", exfer, 4437 0, 0, 0); 4438 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 4439 } 4440 exfer->ex_isdone = 0; 4441 #endif 4442 4443 /* 4444 * Step 1: Allocate and initialize itds, how many do we need? 4445 * One per transfer if interval >= 8 microframes, fewer if we use 4446 * multiple microframes per frame. 4447 */ 4448 4449 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4450 if (i > 16 || i == 0) { 4451 /* Spec page 271 says intervals > 16 are invalid */ 4452 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4453 return USBD_INVAL; 4454 } 4455 4456 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4457 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4458 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4459 4460 if (frames == 0) { 4461 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4462 return USBD_INVAL; 4463 } 4464 4465 dma_buf = &xfer->ux_dmabuf; 4466 offs = 0; 4467 4468 for (i = 0; i < frames; i++) { 4469 int froffs = offs; 4470 itd = ehci_alloc_itd(sc); 4471 4472 if (prev != NULL) { 4473 prev->itd.itd_next = 4474 htole32(itd->physaddr | EHCI_LINK_ITD); 4475 usb_syncmem(&itd->dma, 4476 itd->offs + offsetof(ehci_itd_t, itd_next), 4477 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4478 4479 prev->xfer_next = itd; 4480 } else { 4481 start = itd; 4482 } 4483 4484 /* 4485 * Step 1.5, initialize uframes 4486 */ 4487 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4488 /* Calculate which page in the list this starts in */ 4489 int addr = DMAADDR(dma_buf, froffs); 4490 addr = EHCI_PAGE_OFFSET(addr); 4491 addr += (offs - froffs); 4492 addr = EHCI_PAGE(addr); 4493 addr /= EHCI_PAGE_SIZE; 4494 4495 /* 4496 * This gets the initial offset into the first page, 4497 * looks how far further along the current uframe 4498 * offset is. Works out how many pages that is. 4499 */ 4500 4501 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4502 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4503 EHCI_ITD_SET_PG(addr) | 4504 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4505 4506 total_length += xfer->ux_frlengths[trans_count]; 4507 offs += xfer->ux_frlengths[trans_count]; 4508 trans_count++; 4509 4510 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4511 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4512 break; 4513 } 4514 } 4515 4516 /* 4517 * Step 1.75, set buffer pointers. To simplify matters, all 4518 * pointers are filled out for the next 7 hardware pages in 4519 * the dma block, so no need to worry what pages to cover 4520 * and what to not. 4521 */ 4522 4523 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4524 /* 4525 * Don't try to lookup a page that's past the end 4526 * of buffer 4527 */ 4528 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4529 if (page_offs >= dma_buf->udma_block->size) 4530 break; 4531 4532 unsigned long long page = DMAADDR(dma_buf, page_offs); 4533 page = EHCI_PAGE(page); 4534 itd->itd.itd_bufr[j] = 4535 htole32(EHCI_ITD_SET_BPTR(page)); 4536 itd->itd.itd_bufr_hi[j] = 4537 htole32(page >> 32); 4538 } 4539 4540 /* 4541 * Other special values 4542 */ 4543 4544 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4545 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4546 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4547 4548 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4549 ? 1 : 0; 4550 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4551 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4552 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4553 4554 /* FIXME: handle invalid trans */ 4555 itd->itd.itd_bufr[2] |= 4556 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4557 4558 usb_syncmem(&itd->dma, 4559 itd->offs + offsetof(ehci_itd_t, itd_next), 4560 sizeof(ehci_itd_t), 4561 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4562 4563 prev = itd; 4564 } /* End of frame */ 4565 4566 stop = itd; 4567 stop->xfer_next = NULL; 4568 4569 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4570 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4571 4572 /* 4573 * Part 2: Transfer descriptors have now been set up, now they must 4574 * be scheduled into the period frame list. Erk. Not wanting to 4575 * complicate matters, transfer is denied if the transfer spans 4576 * more than the period frame list. 4577 */ 4578 4579 mutex_enter(&sc->sc_lock); 4580 4581 /* Start inserting frames */ 4582 if (epipe->u.isoc.cur_xfers > 0) { 4583 frindex = epipe->u.isoc.next_frame; 4584 } else { 4585 frindex = EOREAD4(sc, EHCI_FRINDEX); 4586 frindex = frindex >> 3; /* Erase microframe index */ 4587 frindex += 2; 4588 } 4589 4590 if (frindex >= sc->sc_flsize) 4591 frindex &= (sc->sc_flsize - 1); 4592 4593 /* What's the frame interval? */ 4594 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4595 if (i / USB_UFRAMES_PER_FRAME == 0) 4596 i = 1; 4597 else 4598 i /= USB_UFRAMES_PER_FRAME; 4599 4600 itd = start; 4601 for (j = 0; j < frames; j++) { 4602 if (itd == NULL) 4603 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4604 4605 itd->itd.itd_next = sc->sc_flist[frindex]; 4606 if (itd->itd.itd_next == 0) 4607 /* FIXME: frindex table gets initialized to NULL 4608 * or EHCI_NULL? */ 4609 itd->itd.itd_next = EHCI_NULL; 4610 4611 usb_syncmem(&itd->dma, 4612 itd->offs + offsetof(ehci_itd_t, itd_next), 4613 sizeof(itd->itd.itd_next), 4614 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4615 4616 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4617 4618 usb_syncmem(&sc->sc_fldma, 4619 sizeof(ehci_link_t) * frindex, 4620 sizeof(ehci_link_t), 4621 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4622 4623 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4624 sc->sc_softitds[frindex] = itd; 4625 if (itd->u.frame_list.next != NULL) 4626 itd->u.frame_list.next->u.frame_list.prev = itd; 4627 itd->slot = frindex; 4628 itd->u.frame_list.prev = NULL; 4629 4630 frindex += i; 4631 if (frindex >= sc->sc_flsize) 4632 frindex -= sc->sc_flsize; 4633 4634 itd = itd->xfer_next; 4635 } 4636 4637 epipe->u.isoc.cur_xfers++; 4638 epipe->u.isoc.next_frame = frindex; 4639 4640 exfer->ex_itdstart = start; 4641 exfer->ex_itdend = stop; 4642 4643 ehci_add_intr_list(sc, exfer); 4644 xfer->ux_status = USBD_IN_PROGRESS; 4645 xfer->ux_done = 0; 4646 mutex_exit(&sc->sc_lock); 4647 4648 if (sc->sc_bus.ub_usepolling) { 4649 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4650 ehci_waitintr(sc, xfer); 4651 } 4652 4653 return USBD_IN_PROGRESS; 4654 } 4655 4656 Static void 4657 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4658 { 4659 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4660 4661 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4662 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4663 } 4664 4665 Static void 4666 ehci_device_isoc_close(usbd_pipe_handle pipe) 4667 { 4668 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4669 4670 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4671 } 4672 4673 Static void 4674 ehci_device_isoc_done(usbd_xfer_handle xfer) 4675 { 4676 struct ehci_xfer *exfer; 4677 ehci_softc_t *sc; 4678 struct ehci_pipe *epipe; 4679 4680 exfer = EXFER(xfer); 4681 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4682 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4683 4684 KASSERT(mutex_owned(&sc->sc_lock)); 4685 4686 epipe->u.isoc.cur_xfers--; 4687 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4688 ehci_del_intr_list(sc, exfer); 4689 ehci_rem_free_itd_chain(sc, exfer); 4690 } 4691 4692 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4693 BUS_DMASYNC_POSTREAD); 4694 4695 } 4696
Indexes created Thu Oct 02 01:09:59 GMT 2025