ehci.c revision 1.234.2.32
1 /* $NetBSD: ehci.c,v 1.234.2.32 2015/03/01 08:17:45 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.32 2015/03/01 08:17:45 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 85 #include <dev/usb/ehcireg.h> 86 #include <dev/usb/ehcivar.h> 87 #include <dev/usb/usbroothub.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 /* ehci_soft_sitd_t *sitd; */ 135 } tail; 136 union { 137 /* Control pipe */ 138 struct { 139 usb_dma_t reqdma; 140 } ctl; 141 /* Interrupt pipe */ 142 struct { 143 u_int length; 144 } intr; 145 /* Bulk pipe */ 146 struct { 147 u_int length; 148 } bulk; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 } u; 155 }; 156 157 Static usbd_status ehci_open(usbd_pipe_handle); 158 Static void ehci_poll(struct usbd_bus *); 159 Static void ehci_softintr(void *); 160 Static int ehci_intr1(ehci_softc_t *); 161 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 162 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 166 Static void ehci_idone(struct ehci_xfer *); 167 Static void ehci_timeout(void *); 168 Static void ehci_timeout_task(void *); 169 Static void ehci_intrlist_timeout(void *); 170 Static void ehci_doorbell(void *); 171 Static void ehci_pcd(void *); 172 173 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 174 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 Static int ehci_roothub_ctrl(struct usbd_bus *, 177 usb_device_request_t *, void *, int); 178 179 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 180 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 181 Static void ehci_root_intr_abort(usbd_xfer_handle); 182 Static void ehci_root_intr_close(usbd_pipe_handle); 183 Static void ehci_root_intr_done(usbd_xfer_handle); 184 185 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 186 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 187 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 188 Static void ehci_device_ctrl_close(usbd_pipe_handle); 189 Static void ehci_device_ctrl_done(usbd_xfer_handle); 190 191 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 192 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 193 Static void ehci_device_bulk_abort(usbd_xfer_handle); 194 Static void ehci_device_bulk_close(usbd_pipe_handle); 195 Static void ehci_device_bulk_done(usbd_xfer_handle); 196 197 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 198 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 199 Static void ehci_device_intr_abort(usbd_xfer_handle); 200 Static void ehci_device_intr_close(usbd_pipe_handle); 201 Static void ehci_device_intr_done(usbd_xfer_handle); 202 203 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 204 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 205 Static void ehci_device_isoc_abort(usbd_xfer_handle); 206 Static void ehci_device_isoc_close(usbd_pipe_handle); 207 Static void ehci_device_isoc_done(usbd_xfer_handle); 208 209 Static usbd_status ehci_device_fs_isoc_transfer(usbd_xfer_handle); 210 Static usbd_status ehci_device_fs_isoc_start(usbd_xfer_handle); 211 Static void ehci_device_fs_isoc_abort(usbd_xfer_handle); 212 Static void ehci_device_fs_isoc_close(usbd_pipe_handle); 213 Static void ehci_device_fs_isoc_done(usbd_xfer_handle); 214 215 Static void ehci_device_clear_toggle(usbd_pipe_handle); 216 Static void ehci_noop(usbd_pipe_handle); 217 218 Static void ehci_disown(ehci_softc_t *, int, int); 219 220 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 221 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 222 223 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 224 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 225 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 226 ehci_softc_t *, int, int, usbd_xfer_handle, 227 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 228 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 229 ehci_soft_qtd_t *); 230 231 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 232 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *); 233 Static void ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *); 234 Static void ehci_free_sitd(ehci_softc_t *, ehci_soft_sitd_t *); 235 Static void ehci_rem_free_itd_chain(ehci_softc_t *, 236 struct ehci_xfer *); 237 Static void ehci_rem_free_sitd_chain(ehci_softc_t *, 238 struct ehci_xfer *); 239 Static void ehci_abort_isoc_xfer(usbd_xfer_handle, 240 usbd_status); 241 242 Static usbd_status ehci_device_request(usbd_xfer_handle); 243 244 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 245 int); 246 247 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 248 ehci_soft_qh_t *); 249 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 250 ehci_soft_qh_t *); 251 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 252 Static void ehci_sync_hc(ehci_softc_t *); 253 254 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 255 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 256 257 #ifdef EHCI_DEBUG 258 Static ehci_softc_t *theehci; 259 void ehci_dump(void); 260 #endif 261 262 #ifdef EHCI_DEBUG 263 Static void ehci_dump_regs(ehci_softc_t *); 264 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 265 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 266 Static void ehci_dump_qtd(ehci_qtd_t *); 267 Static void ehci_dump_sqh(ehci_soft_qh_t *); 268 Static void ehci_dump_sitd(struct ehci_soft_itd *); 269 Static void ehci_dump_itd(struct ehci_soft_itd *); 270 Static void ehci_dump_exfer(struct ehci_xfer *); 271 #endif 272 273 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 274 275 #define ehci_add_intr_list(sc, ex) \ 276 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 277 #define ehci_del_intr_list(sc, ex) \ 278 do { \ 279 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 280 (ex)->ex_next.tqe_prev = NULL; \ 281 } while (0) 282 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 283 284 Static const struct usbd_bus_methods ehci_bus_methods = { 285 .ubm_open = ehci_open, 286 .ubm_softint = ehci_softintr, 287 .ubm_dopoll = ehci_poll, 288 .ubm_allocx = ehci_allocx, 289 .ubm_freex = ehci_freex, 290 .ubm_getlock = ehci_get_lock, 291 .ubm_rhctrl = ehci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 295 .upm_transfer = ehci_root_intr_transfer, 296 .upm_start = ehci_root_intr_start, 297 .upm_abort = ehci_root_intr_abort, 298 .upm_close = ehci_root_intr_close, 299 .upm_cleartoggle = ehci_noop, 300 .upm_done = ehci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 304 .upm_transfer = ehci_device_ctrl_transfer, 305 .upm_start = ehci_device_ctrl_start, 306 .upm_abort = ehci_device_ctrl_abort, 307 .upm_close = ehci_device_ctrl_close, 308 .upm_cleartoggle = ehci_noop, 309 .upm_done = ehci_device_ctrl_done, 310 }; 311 312 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 313 .upm_transfer = ehci_device_intr_transfer, 314 .upm_start = ehci_device_intr_start, 315 .upm_abort = ehci_device_intr_abort, 316 .upm_close = ehci_device_intr_close, 317 .upm_cleartoggle = ehci_device_clear_toggle, 318 .upm_done = ehci_device_intr_done, 319 }; 320 321 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 322 .upm_transfer = ehci_device_bulk_transfer, 323 .upm_start = ehci_device_bulk_start, 324 .upm_abort = ehci_device_bulk_abort, 325 .upm_close = ehci_device_bulk_close, 326 .upm_cleartoggle = ehci_device_clear_toggle, 327 .upm_done = ehci_device_bulk_done, 328 }; 329 330 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 331 .upm_transfer = ehci_device_isoc_transfer, 332 .upm_start = ehci_device_isoc_start, 333 .upm_abort = ehci_device_isoc_abort, 334 .upm_close = ehci_device_isoc_close, 335 .upm_cleartoggle = ehci_noop, 336 .upm_done = ehci_device_isoc_done, 337 }; 338 339 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 340 .upm_transfer = ehci_device_fs_isoc_transfer, 341 .upm_start = ehci_device_fs_isoc_start, 342 .upm_abort = ehci_device_fs_isoc_abort, 343 .upm_close = ehci_device_fs_isoc_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_fs_isoc_done, 346 }; 347 348 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 349 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 350 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 351 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 352 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 353 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 354 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 355 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 356 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 357 }; 358 359 int 360 ehci_init(ehci_softc_t *sc) 361 { 362 uint32_t vers, sparams, cparams, hcr; 363 u_int i; 364 usbd_status err; 365 ehci_soft_qh_t *sqh; 366 u_int ncomp; 367 368 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 369 #ifdef EHCI_DEBUG 370 theehci = sc; 371 #endif 372 373 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 374 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 375 cv_init(&sc->sc_softwake_cv, "ehciab"); 376 cv_init(&sc->sc_doorbell, "ehcidi"); 377 378 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 379 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 380 381 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 382 ehci_doorbell, sc); 383 KASSERT(sc->sc_doorbell_si != NULL); 384 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 385 ehci_pcd, sc); 386 KASSERT(sc->sc_pcd_si != NULL); 387 388 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 389 390 vers = EREAD2(sc, EHCI_HCIVERSION); 391 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 392 vers >> 8, vers & 0xff); 393 394 sparams = EREAD4(sc, EHCI_HCSPARAMS); 395 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 396 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 397 ncomp = EHCI_HCS_N_CC(sparams); 398 if (ncomp != sc->sc_ncomp) { 399 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 400 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 401 #if NOHCI == 0 || NUHCI == 0 402 aprint_error("%s: ohci or uhci probably not configured\n", 403 device_xname(sc->sc_dev)); 404 #endif 405 if (ncomp < sc->sc_ncomp) 406 sc->sc_ncomp = ncomp; 407 } 408 if (sc->sc_ncomp > 0) { 409 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 410 aprint_normal("%s: companion controller%s, %d port%s each:", 411 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 412 EHCI_HCS_N_PCC(sparams), 413 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 414 for (i = 0; i < sc->sc_ncomp; i++) 415 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 416 aprint_normal("\n"); 417 } 418 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 419 cparams = EREAD4(sc, EHCI_HCCPARAMS); 420 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 421 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 422 423 if (EHCI_HCC_64BIT(cparams)) { 424 /* MUST clear segment register if 64 bit capable. */ 425 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 426 } 427 428 sc->sc_bus.ub_revision = USBREV_2_0; 429 sc->sc_bus.ub_usedma = true; 430 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 431 432 /* Reset the controller */ 433 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 434 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 435 usb_delay_ms(&sc->sc_bus, 1); 436 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 437 for (i = 0; i < 100; i++) { 438 usb_delay_ms(&sc->sc_bus, 1); 439 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 440 if (!hcr) 441 break; 442 } 443 if (hcr) { 444 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 445 return EIO; 446 } 447 if (sc->sc_vendor_init) 448 sc->sc_vendor_init(sc); 449 450 /* 451 * If we are doing embedded transaction translation function, force 452 * the controller to host mode. 453 */ 454 if (sc->sc_flags & EHCIF_ETTF) { 455 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 456 usbmode &= ~EHCI_USBMODE_CM; 457 usbmode |= EHCI_USBMODE_CM_HOST; 458 EWRITE4(sc, EHCI_USBMODE, usbmode); 459 } 460 461 /* XXX need proper intr scheduling */ 462 sc->sc_rand = 96; 463 464 /* frame list size at default, read back what we got and use that */ 465 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 466 case 0: sc->sc_flsize = 1024; break; 467 case 1: sc->sc_flsize = 512; break; 468 case 2: sc->sc_flsize = 256; break; 469 case 3: return EIO; 470 } 471 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 472 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 473 if (err) 474 return err; 475 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 476 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 477 478 for (i = 0; i < sc->sc_flsize; i++) { 479 sc->sc_flist[i] = EHCI_NULL; 480 } 481 482 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 483 484 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 485 KM_SLEEP); 486 if (sc->sc_softitds == NULL) 487 return ENOMEM; 488 LIST_INIT(&sc->sc_freeitds); 489 LIST_INIT(&sc->sc_freesitds); 490 TAILQ_INIT(&sc->sc_intrhead); 491 492 /* Set up the bus struct. */ 493 sc->sc_bus.ub_methods = &ehci_bus_methods; 494 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 495 496 sc->sc_eintrs = EHCI_NORMAL_INTRS; 497 498 /* 499 * Allocate the interrupt dummy QHs. These are arranged to give poll 500 * intervals that are powers of 2 times 1ms. 501 */ 502 for (i = 0; i < EHCI_INTRQHS; i++) { 503 sqh = ehci_alloc_sqh(sc); 504 if (sqh == NULL) { 505 err = ENOMEM; 506 goto bad1; 507 } 508 sc->sc_islots[i].sqh = sqh; 509 } 510 for (i = 0; i < EHCI_INTRQHS; i++) { 511 sqh = sc->sc_islots[i].sqh; 512 if (i == 0) { 513 /* The last (1ms) QH terminates. */ 514 sqh->qh.qh_link = EHCI_NULL; 515 sqh->next = NULL; 516 } else { 517 /* Otherwise the next QH has half the poll interval */ 518 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 519 sqh->qh.qh_link = htole32(sqh->next->physaddr | 520 EHCI_LINK_QH); 521 } 522 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 523 sqh->qh.qh_curqtd = EHCI_NULL; 524 sqh->next = NULL; 525 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 526 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 527 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 528 sqh->sqtd = NULL; 529 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 531 } 532 /* Point the frame list at the last level (128ms). */ 533 for (i = 0; i < sc->sc_flsize; i++) { 534 int j; 535 536 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 537 revbits[i & (EHCI_MAX_POLLRATE-1)]; 538 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 539 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 540 i)].sqh->physaddr); 541 } 542 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 543 BUS_DMASYNC_PREWRITE); 544 545 /* Allocate dummy QH that starts the async list. */ 546 sqh = ehci_alloc_sqh(sc); 547 if (sqh == NULL) { 548 err = ENOMEM; 549 goto bad1; 550 } 551 /* Fill the QH */ 552 sqh->qh.qh_endp = 553 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 554 sqh->qh.qh_link = 555 htole32(sqh->physaddr | EHCI_LINK_QH); 556 sqh->qh.qh_curqtd = EHCI_NULL; 557 sqh->next = NULL; 558 /* Fill the overlay qTD */ 559 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 560 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 561 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 562 sqh->sqtd = NULL; 563 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 564 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 565 #ifdef EHCI_DEBUG 566 ehci_dump_sqh(sqh); 567 #endif 568 569 /* Point to async list */ 570 sc->sc_async_head = sqh; 571 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 572 573 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 574 575 /* Turn on controller */ 576 EOWRITE4(sc, EHCI_USBCMD, 577 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 578 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 579 EHCI_CMD_ASE | 580 EHCI_CMD_PSE | 581 EHCI_CMD_RS); 582 583 /* Take over port ownership */ 584 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 585 586 for (i = 0; i < 100; i++) { 587 usb_delay_ms(&sc->sc_bus, 1); 588 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 589 if (!hcr) 590 break; 591 } 592 if (hcr) { 593 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 594 return EIO; 595 } 596 597 /* Enable interrupts */ 598 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 599 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 600 601 return 0; 602 603 #if 0 604 bad2: 605 ehci_free_sqh(sc, sc->sc_async_head); 606 #endif 607 bad1: 608 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 609 return err; 610 } 611 612 int 613 ehci_intr(void *v) 614 { 615 ehci_softc_t *sc = v; 616 int ret = 0; 617 618 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 619 620 if (sc == NULL) 621 return 0; 622 623 mutex_spin_enter(&sc->sc_intr_lock); 624 625 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 626 goto done; 627 628 /* If we get an interrupt while polling, then just ignore it. */ 629 if (sc->sc_bus.ub_usepolling) { 630 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 631 632 if (intrs) 633 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 634 USBHIST_LOGN(ehcidebug, 16, 635 "ignored interrupt while polling", 0, 0, 0, 0); 636 goto done; 637 } 638 639 ret = ehci_intr1(sc); 640 641 done: 642 mutex_spin_exit(&sc->sc_intr_lock); 643 return ret; 644 } 645 646 Static int 647 ehci_intr1(ehci_softc_t *sc) 648 { 649 uint32_t intrs, eintrs; 650 651 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 652 653 /* In case the interrupt occurs before initialization has completed. */ 654 if (sc == NULL) { 655 #ifdef DIAGNOSTIC 656 printf("ehci_intr1: sc == NULL\n"); 657 #endif 658 return 0; 659 } 660 661 KASSERT(mutex_owned(&sc->sc_intr_lock)); 662 663 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 664 if (!intrs) 665 return 0; 666 667 eintrs = intrs & sc->sc_eintrs; 668 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 669 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 670 if (!eintrs) 671 return 0; 672 673 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 674 if (eintrs & EHCI_STS_IAA) { 675 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 676 kpreempt_disable(); 677 KASSERT(sc->sc_doorbell_si != NULL); 678 softint_schedule(sc->sc_doorbell_si); 679 kpreempt_enable(); 680 eintrs &= ~EHCI_STS_IAA; 681 } 682 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 683 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 684 eintrs & EHCI_STS_INT ? 1 : 0, 685 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 686 usb_schedsoftintr(&sc->sc_bus); 687 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 688 } 689 if (eintrs & EHCI_STS_HSE) { 690 printf("%s: unrecoverable error, controller halted\n", 691 device_xname(sc->sc_dev)); 692 /* XXX what else */ 693 } 694 if (eintrs & EHCI_STS_PCD) { 695 kpreempt_disable(); 696 KASSERT(sc->sc_pcd_si != NULL); 697 softint_schedule(sc->sc_pcd_si); 698 kpreempt_enable(); 699 eintrs &= ~EHCI_STS_PCD; 700 } 701 702 if (eintrs != 0) { 703 /* Block unprocessed interrupts. */ 704 sc->sc_eintrs &= ~eintrs; 705 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 706 printf("%s: blocking intrs 0x%x\n", 707 device_xname(sc->sc_dev), eintrs); 708 } 709 710 return 1; 711 } 712 713 Static void 714 ehci_doorbell(void *addr) 715 { 716 ehci_softc_t *sc = addr; 717 718 mutex_enter(&sc->sc_lock); 719 cv_broadcast(&sc->sc_doorbell); 720 mutex_exit(&sc->sc_lock); 721 } 722 723 Static void 724 ehci_pcd(void *addr) 725 { 726 ehci_softc_t *sc = addr; 727 usbd_xfer_handle xfer; 728 u_char *p; 729 int i, m; 730 731 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 732 733 mutex_enter(&sc->sc_lock); 734 xfer = sc->sc_intrxfer; 735 736 if (xfer == NULL) { 737 /* Just ignore the change. */ 738 goto done; 739 } 740 741 p = xfer->ux_buf; 742 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 743 memset(p, 0, xfer->ux_length); 744 for (i = 1; i <= m; i++) { 745 /* Pick out CHANGE bits from the status reg. */ 746 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 747 p[i/8] |= 1 << (i%8); 748 if (i % 8 == 7) 749 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 750 p[i/8], 0, 0); 751 } 752 xfer->ux_actlen = xfer->ux_length; 753 xfer->ux_status = USBD_NORMAL_COMPLETION; 754 755 usb_transfer_complete(xfer); 756 757 done: 758 mutex_exit(&sc->sc_lock); 759 } 760 761 Static void 762 ehci_softintr(void *v) 763 { 764 struct usbd_bus *bus = v; 765 ehci_softc_t *sc = bus->ub_hcpriv; 766 struct ehci_xfer *ex, *nextex; 767 768 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 769 770 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 771 772 /* 773 * The only explanation I can think of for why EHCI is as brain dead 774 * as UHCI interrupt-wise is that Intel was involved in both. 775 * An interrupt just tells us that something is done, we have no 776 * clue what, so we need to scan through all active transfers. :-( 777 */ 778 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 779 nextex = TAILQ_NEXT(ex, ex_next); 780 ehci_check_intr(sc, ex); 781 } 782 783 /* Schedule a callout to catch any dropped transactions. */ 784 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 785 !TAILQ_EMPTY(&sc->sc_intrhead)) 786 callout_reset(&sc->sc_tmo_intrlist, 787 hz, ehci_intrlist_timeout, sc); 788 789 if (sc->sc_softwake) { 790 sc->sc_softwake = 0; 791 cv_broadcast(&sc->sc_softwake_cv); 792 } 793 } 794 795 /* Check for an interrupt. */ 796 Static void 797 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 798 { 799 usbd_device_handle dev = ex->ex_xfer.ux_pipe->up_dev; 800 int attr; 801 802 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 803 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 804 805 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 806 807 attr = ex->ex_xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 808 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 809 if (dev->ud_speed == USB_SPEED_HIGH) 810 ehci_check_itd_intr(sc, ex); 811 else 812 ehci_check_sitd_intr(sc, ex); 813 } else 814 ehci_check_qh_intr(sc, ex); 815 816 return; 817 } 818 819 Static void 820 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 821 { 822 ehci_soft_qtd_t *sqtd, *lsqtd; 823 uint32_t status; 824 825 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 826 827 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 828 829 if (ex->ex_sqtdstart == NULL) { 830 printf("ehci_check_qh_intr: not valid sqtd\n"); 831 return; 832 } 833 834 lsqtd = ex->ex_sqtdend; 835 #ifdef DIAGNOSTIC 836 if (lsqtd == NULL) { 837 printf("ehci_check_qh_intr: lsqtd==0\n"); 838 return; 839 } 840 #endif 841 /* 842 * If the last TD is still active we need to check whether there 843 * is an error somewhere in the middle, or whether there was a 844 * short packet (SPD and not ACTIVE). 845 */ 846 usb_syncmem(&lsqtd->dma, 847 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 848 sizeof(lsqtd->qtd.qtd_status), 849 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 850 status = le32toh(lsqtd->qtd.qtd_status); 851 usb_syncmem(&lsqtd->dma, 852 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 853 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 854 if (status & EHCI_QTD_ACTIVE) { 855 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 856 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd; 857 sqtd = sqtd->nextqtd) { 858 usb_syncmem(&sqtd->dma, 859 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 860 sizeof(sqtd->qtd.qtd_status), 861 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 862 status = le32toh(sqtd->qtd.qtd_status); 863 usb_syncmem(&sqtd->dma, 864 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 865 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 866 /* If there's an active QTD the xfer isn't done. */ 867 if (status & EHCI_QTD_ACTIVE) 868 break; 869 /* Any kind of error makes the xfer done. */ 870 if (status & EHCI_QTD_HALTED) 871 goto done; 872 /* Handle short packets */ 873 if (EHCI_QTD_GET_BYTES(status) != 0) { 874 usbd_pipe_handle pipe = ex->ex_xfer.ux_pipe; 875 usb_endpoint_descriptor_t *ed = 876 pipe->up_endpoint->ue_edesc; 877 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 878 879 /* 880 * If we get here for a control transfer then 881 * we need to let the hardware complete the 882 * status phase. That is, we're not done 883 * quite yet. 884 * 885 * Otherwise, we're done. 886 */ 887 if (xt == UE_CONTROL) { 888 break; 889 } 890 goto done; 891 } 892 } 893 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 894 ex, ex->ex_sqtdstart, 0, 0); 895 return; 896 } 897 done: 898 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 899 callout_stop(&ex->ex_xfer.ux_callout); 900 ehci_idone(ex); 901 } 902 903 Static void 904 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 905 { 906 ehci_soft_itd_t *itd; 907 int i; 908 909 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 910 911 KASSERT(mutex_owned(&sc->sc_lock)); 912 913 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 914 return; 915 916 if (ex->ex_itdstart == NULL) { 917 printf("ehci_check_itd_intr: not valid itd\n"); 918 return; 919 } 920 921 itd = ex->ex_itdend; 922 #ifdef DIAGNOSTIC 923 if (itd == NULL) { 924 printf("ehci_check_itd_intr: itdend == 0\n"); 925 return; 926 } 927 #endif 928 929 /* 930 * check no active transfers in last itd, meaning we're finished 931 */ 932 933 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 934 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 935 BUS_DMASYNC_POSTREAD); 936 937 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 938 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 939 break; 940 } 941 942 if (i == EHCI_ITD_NUFRAMES) { 943 goto done; /* All 8 descriptors inactive, it's done */ 944 } 945 946 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 947 ex->ex_itdstart, 0, 0); 948 return; 949 done: 950 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 951 callout_stop(&ex->ex_xfer.ux_callout); 952 ehci_idone(ex); 953 } 954 955 void 956 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 957 { 958 ehci_soft_sitd_t *sitd; 959 960 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 961 962 KASSERT(mutex_owned(&sc->sc_lock)); 963 964 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 965 return; 966 967 if (ex->ex_sitdstart == NULL) { 968 printf("ehci_check_sitd_intr: not valid sitd\n"); 969 return; 970 } 971 972 sitd = ex->ex_sitdend; 973 #ifdef DIAGNOSTIC 974 if (sitd == NULL) { 975 printf("ehci_check_sitd_intr: sitdend == 0\n"); 976 return; 977 } 978 #endif 979 980 /* 981 * check no active transfers in last sitd, meaning we're finished 982 */ 983 984 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 985 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 986 BUS_DMASYNC_POSTREAD); 987 988 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 989 return; 990 991 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 992 callout_stop(&(ex->ex_xfer.ux_callout)); 993 ehci_idone(ex); 994 } 995 996 997 Static void 998 ehci_idone(struct ehci_xfer *ex) 999 { 1000 usbd_xfer_handle xfer = &ex->ex_xfer; 1001 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1002 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1003 ehci_soft_qtd_t *sqtd, *lsqtd; 1004 uint32_t status = 0, nstatus = 0; 1005 int actlen; 1006 1007 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1008 1009 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1010 1011 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1012 1013 #ifdef DIAGNOSTIC 1014 if (ex->ex_isdone) { 1015 printf("ehci_idone: ex=%p is done!\n", ex); 1016 #ifdef EHCI_DEBUG 1017 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1018 ehci_dump_exfer(ex); 1019 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1020 #endif 1021 return; 1022 } 1023 ex->ex_isdone = 1; 1024 #endif 1025 1026 if (xfer->ux_status == USBD_CANCELLED || 1027 xfer->ux_status == USBD_TIMEOUT) { 1028 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1029 return; 1030 } 1031 1032 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1033 #ifdef EHCI_DEBUG 1034 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1035 ehci_dump_sqtds(ex->ex_sqtdstart); 1036 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1037 #endif 1038 1039 /* The transfer is done, compute actual length and status. */ 1040 1041 u_int xfertype, speed; 1042 1043 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1044 speed = xfer->ux_pipe->up_dev->ud_speed; 1045 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1046 /* HS isoc transfer */ 1047 1048 struct ehci_soft_itd *itd; 1049 int i, nframes, len, uframes; 1050 1051 nframes = 0; 1052 actlen = 0; 1053 1054 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1055 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1056 1057 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1058 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1059 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1060 BUS_DMASYNC_POSTREAD); 1061 1062 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1063 /* 1064 * XXX - driver didn't fill in the frame full 1065 * of uframes. This leads to scheduling 1066 * inefficiencies, but working around 1067 * this doubles complexity of tracking 1068 * an xfer. 1069 */ 1070 if (nframes >= xfer->ux_nframes) 1071 break; 1072 1073 status = le32toh(itd->itd.itd_ctl[i]); 1074 len = EHCI_ITD_GET_LEN(status); 1075 if (EHCI_ITD_GET_STATUS(status) != 0) 1076 len = 0; /*No valid data on error*/ 1077 1078 xfer->ux_frlengths[nframes++] = len; 1079 actlen += len; 1080 } 1081 1082 if (nframes >= xfer->ux_nframes) 1083 break; 1084 } 1085 1086 xfer->ux_actlen = actlen; 1087 xfer->ux_status = USBD_NORMAL_COMPLETION; 1088 goto end; 1089 } 1090 1091 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1092 /* FS isoc transfer */ 1093 struct ehci_soft_sitd *sitd; 1094 int nframes, len; 1095 1096 nframes = 0; 1097 actlen = 0; 1098 1099 for (sitd = ex->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1100 usb_syncmem(&sitd->dma,sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 1101 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 1102 BUS_DMASYNC_POSTREAD); 1103 1104 /* 1105 * XXX - driver didn't fill in the frame full 1106 * of uframes. This leads to scheduling 1107 * inefficiencies, but working around 1108 * this doubles complexity of tracking 1109 * an xfer. 1110 */ 1111 if (nframes >= xfer->ux_nframes) 1112 break; 1113 1114 status = le32toh(sitd->sitd.sitd_trans); 1115 len = EHCI_SITD_GET_LEN(status); 1116 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1117 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1118 /* No valid data on error */ 1119 len = xfer->ux_frlengths[nframes]; 1120 } 1121 1122 /* 1123 * frlengths[i]: # of bytes to send 1124 * len: # of bytes host didn't send 1125 */ 1126 xfer->ux_frlengths[nframes] -= len; 1127 /* frlengths[i]: # of bytes host sent */ 1128 actlen += xfer->ux_frlengths[nframes++]; 1129 1130 if (nframes >= xfer->ux_nframes) 1131 break; 1132 } 1133 1134 xfer->ux_actlen = actlen; 1135 xfer->ux_status = USBD_NORMAL_COMPLETION; 1136 goto end; 1137 } 1138 KASSERT(xfertype != UE_ISOCHRONOUS); 1139 1140 /* Continue processing xfers using queue heads */ 1141 1142 lsqtd = ex->ex_sqtdend; 1143 actlen = 0; 1144 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd->nextqtd; 1145 sqtd = sqtd->nextqtd) { 1146 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1147 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1148 nstatus = le32toh(sqtd->qtd.qtd_status); 1149 if (nstatus & EHCI_QTD_ACTIVE) 1150 break; 1151 1152 status = nstatus; 1153 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1154 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1155 } 1156 1157 1158 /* 1159 * If there are left over TDs we need to update the toggle. 1160 * The default pipe doesn't need it since control transfers 1161 * start the toggle at 0 every time. 1162 * For a short transfer we need to update the toggle for the missing 1163 * packets within the qTD. 1164 */ 1165 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1166 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1167 USBHIST_LOG(ehcidebug, 1168 "toggle update status=0x%08x nstatus=0x%08x", 1169 status, nstatus, 0, 0); 1170 #if 0 1171 ehci_dump_sqh(epipe->sqh); 1172 ehci_dump_sqtds(ex->ex_sqtdstart); 1173 #endif 1174 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1175 } 1176 1177 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1178 actlen, status, 0); 1179 xfer->ux_actlen = actlen; 1180 if (status & EHCI_QTD_HALTED) { 1181 #ifdef EHCI_DEBUG 1182 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1183 xfer->ux_pipe->up_dev->ud_addr, 1184 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1185 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1186 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1187 0, 0); 1188 USBHIST_LOG(ehcidebug, 1189 "active =%d halted=%d buferr=%d babble=%d", 1190 status & EHCI_QTD_ACTIVE ? 1 : 0, 1191 status & EHCI_QTD_HALTED ? 1 : 0, 1192 status & EHCI_QTD_BUFERR ? 1 : 0, 1193 status & EHCI_QTD_BABBLE ? 1 : 0); 1194 1195 USBHIST_LOG(ehcidebug, 1196 "xacterr=%d missed=%d split =%d ping =%d", 1197 status & EHCI_QTD_XACTERR ? 1 : 0, 1198 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1199 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1200 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1201 1202 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1203 ehci_dump_sqh(epipe->sqh); 1204 ehci_dump_sqtds(ex->ex_sqtdstart); 1205 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1206 #endif 1207 /* low&full speed has an extra error flag */ 1208 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1209 EHCI_QH_SPEED_HIGH) 1210 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1211 else 1212 status &= EHCI_QTD_STATERRS; 1213 if (status == 0) /* no other errors means a stall */ { 1214 xfer->ux_status = USBD_STALLED; 1215 } else { 1216 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1217 } 1218 /* XXX need to reset TT on missed microframe */ 1219 if (status & EHCI_QTD_MISSEDMICRO) { 1220 printf("%s: missed microframe, TT reset not " 1221 "implemented, hub might be inoperational\n", 1222 device_xname(sc->sc_dev)); 1223 } 1224 } else { 1225 xfer->ux_status = USBD_NORMAL_COMPLETION; 1226 } 1227 1228 end: 1229 /* 1230 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1231 * during this call, before methods->done is called: dma sync required 1232 * beforehand? 1233 */ 1234 usb_transfer_complete(xfer); 1235 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1236 } 1237 1238 /* 1239 * Wait here until controller claims to have an interrupt. 1240 * Then call ehci_intr and return. Use timeout to avoid waiting 1241 * too long. 1242 */ 1243 Static void 1244 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1245 { 1246 int timo; 1247 uint32_t intrs; 1248 1249 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1250 1251 xfer->ux_status = USBD_IN_PROGRESS; 1252 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1253 usb_delay_ms(&sc->sc_bus, 1); 1254 if (sc->sc_dying) 1255 break; 1256 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1257 sc->sc_eintrs; 1258 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1259 #ifdef EHCI_DEBUG 1260 if (ehcidebug > 15) 1261 ehci_dump_regs(sc); 1262 #endif 1263 if (intrs) { 1264 mutex_spin_enter(&sc->sc_intr_lock); 1265 ehci_intr1(sc); 1266 mutex_spin_exit(&sc->sc_intr_lock); 1267 if (xfer->ux_status != USBD_IN_PROGRESS) 1268 return; 1269 } 1270 } 1271 1272 /* Timeout */ 1273 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1274 xfer->ux_status = USBD_TIMEOUT; 1275 mutex_enter(&sc->sc_lock); 1276 usb_transfer_complete(xfer); 1277 mutex_exit(&sc->sc_lock); 1278 /* XXX should free TD */ 1279 } 1280 1281 Static void 1282 ehci_poll(struct usbd_bus *bus) 1283 { 1284 ehci_softc_t *sc = bus->ub_hcpriv; 1285 1286 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1287 1288 #ifdef EHCI_DEBUG 1289 static int last; 1290 int new; 1291 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1292 if (new != last) { 1293 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1294 last = new; 1295 } 1296 #endif 1297 1298 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1299 mutex_spin_enter(&sc->sc_intr_lock); 1300 ehci_intr1(sc); 1301 mutex_spin_exit(&sc->sc_intr_lock); 1302 } 1303 } 1304 1305 void 1306 ehci_childdet(device_t self, device_t child) 1307 { 1308 struct ehci_softc *sc = device_private(self); 1309 1310 KASSERT(sc->sc_child == child); 1311 sc->sc_child = NULL; 1312 } 1313 1314 int 1315 ehci_detach(struct ehci_softc *sc, int flags) 1316 { 1317 int rv = 0; 1318 1319 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1320 1321 if (sc->sc_child != NULL) 1322 rv = config_detach(sc->sc_child, flags); 1323 1324 if (rv != 0) 1325 return rv; 1326 1327 callout_halt(&sc->sc_tmo_intrlist, NULL); 1328 callout_destroy(&sc->sc_tmo_intrlist); 1329 1330 /* XXX free other data structures XXX */ 1331 if (sc->sc_softitds) 1332 kmem_free(sc->sc_softitds, 1333 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1334 cv_destroy(&sc->sc_doorbell); 1335 cv_destroy(&sc->sc_softwake_cv); 1336 1337 #if 0 1338 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1339 1340 softint_disestablish(sc->sc_doorbell_si); 1341 softint_disestablish(sc->sc_pcd_si); 1342 1343 mutex_destroy(&sc->sc_lock); 1344 mutex_destroy(&sc->sc_intr_lock); 1345 #endif 1346 1347 pool_cache_destroy(sc->sc_xferpool); 1348 1349 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1350 1351 return rv; 1352 } 1353 1354 1355 int 1356 ehci_activate(device_t self, enum devact act) 1357 { 1358 struct ehci_softc *sc = device_private(self); 1359 1360 switch (act) { 1361 case DVACT_DEACTIVATE: 1362 sc->sc_dying = 1; 1363 return 0; 1364 default: 1365 return EOPNOTSUPP; 1366 } 1367 } 1368 1369 /* 1370 * Handle suspend/resume. 1371 * 1372 * We need to switch to polling mode here, because this routine is 1373 * called from an interrupt context. This is all right since we 1374 * are almost suspended anyway. 1375 * 1376 * Note that this power handler isn't to be registered directly; the 1377 * bus glue needs to call out to it. 1378 */ 1379 bool 1380 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1381 { 1382 ehci_softc_t *sc = device_private(dv); 1383 int i; 1384 uint32_t cmd, hcr; 1385 1386 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1387 1388 mutex_spin_enter(&sc->sc_intr_lock); 1389 sc->sc_bus.ub_usepolling++; 1390 mutex_spin_exit(&sc->sc_intr_lock); 1391 1392 for (i = 1; i <= sc->sc_noport; i++) { 1393 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1394 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1395 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1396 } 1397 1398 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1399 1400 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1401 EOWRITE4(sc, EHCI_USBCMD, cmd); 1402 1403 for (i = 0; i < 100; i++) { 1404 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1405 if (hcr == 0) 1406 break; 1407 1408 usb_delay_ms(&sc->sc_bus, 1); 1409 } 1410 if (hcr != 0) 1411 printf("%s: reset timeout\n", device_xname(dv)); 1412 1413 cmd &= ~EHCI_CMD_RS; 1414 EOWRITE4(sc, EHCI_USBCMD, cmd); 1415 1416 for (i = 0; i < 100; i++) { 1417 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1418 if (hcr == EHCI_STS_HCH) 1419 break; 1420 1421 usb_delay_ms(&sc->sc_bus, 1); 1422 } 1423 if (hcr != EHCI_STS_HCH) 1424 printf("%s: config timeout\n", device_xname(dv)); 1425 1426 mutex_spin_enter(&sc->sc_intr_lock); 1427 sc->sc_bus.ub_usepolling--; 1428 mutex_spin_exit(&sc->sc_intr_lock); 1429 1430 return true; 1431 } 1432 1433 bool 1434 ehci_resume(device_t dv, const pmf_qual_t *qual) 1435 { 1436 ehci_softc_t *sc = device_private(dv); 1437 int i; 1438 uint32_t cmd, hcr; 1439 1440 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1441 1442 /* restore things in case the bios sucks */ 1443 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1444 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1445 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1446 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1447 1448 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1449 1450 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1451 1452 hcr = 0; 1453 for (i = 1; i <= sc->sc_noport; i++) { 1454 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1455 if ((cmd & EHCI_PS_PO) == 0 && 1456 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1457 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1458 hcr = 1; 1459 } 1460 } 1461 1462 if (hcr) { 1463 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1464 1465 for (i = 1; i <= sc->sc_noport; i++) { 1466 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1467 if ((cmd & EHCI_PS_PO) == 0 && 1468 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1469 EOWRITE4(sc, EHCI_PORTSC(i), 1470 cmd & ~EHCI_PS_FPR); 1471 } 1472 } 1473 1474 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1475 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1476 1477 for (i = 0; i < 100; i++) { 1478 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1479 if (hcr != EHCI_STS_HCH) 1480 break; 1481 1482 usb_delay_ms(&sc->sc_bus, 1); 1483 } 1484 if (hcr == EHCI_STS_HCH) 1485 printf("%s: config timeout\n", device_xname(dv)); 1486 1487 return true; 1488 } 1489 1490 /* 1491 * Shut down the controller when the system is going down. 1492 */ 1493 bool 1494 ehci_shutdown(device_t self, int flags) 1495 { 1496 ehci_softc_t *sc = device_private(self); 1497 1498 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1499 1500 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1501 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1502 return true; 1503 } 1504 1505 Static usbd_xfer_handle 1506 ehci_allocx(struct usbd_bus *bus) 1507 { 1508 struct ehci_softc *sc = bus->ub_hcpriv; 1509 usbd_xfer_handle xfer; 1510 1511 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1512 if (xfer != NULL) { 1513 memset(xfer, 0, sizeof(struct ehci_xfer)); 1514 #ifdef DIAGNOSTIC 1515 EXFER(xfer)->ex_isdone = 1; 1516 xfer->ux_state = XFER_BUSY; 1517 #endif 1518 } 1519 return xfer; 1520 } 1521 1522 Static void 1523 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1524 { 1525 struct ehci_softc *sc = bus->ub_hcpriv; 1526 1527 #ifdef DIAGNOSTIC 1528 if (xfer->ux_state != XFER_BUSY) { 1529 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1530 xfer->ux_state); 1531 } 1532 xfer->ux_state = XFER_FREE; 1533 if (!EXFER(xfer)->ex_isdone) { 1534 printf("ehci_freex: !isdone\n"); 1535 } 1536 #endif 1537 pool_cache_put(sc->sc_xferpool, xfer); 1538 } 1539 1540 Static void 1541 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1542 { 1543 struct ehci_softc *sc = bus->ub_hcpriv; 1544 1545 *lock = &sc->sc_lock; 1546 } 1547 1548 Static void 1549 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1550 { 1551 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1552 1553 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1554 1555 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1556 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1557 #ifdef EHCI_DEBUG 1558 if (ehcidebug) 1559 usbd_dump_pipe(pipe); 1560 #endif 1561 epipe->nexttoggle = 0; 1562 } 1563 1564 Static void 1565 ehci_noop(usbd_pipe_handle pipe) 1566 { 1567 } 1568 1569 #ifdef EHCI_DEBUG 1570 /* 1571 * Unused function - this is meant to be called from a kernel 1572 * debugger. 1573 */ 1574 void 1575 ehci_dump(void) 1576 { 1577 ehci_softc_t *sc = theehci; 1578 int i; 1579 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1580 EOREAD4(sc, EHCI_USBCMD), 1581 EOREAD4(sc, EHCI_USBSTS), 1582 EOREAD4(sc, EHCI_USBINTR)); 1583 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1584 EOREAD4(sc, EHCI_FRINDEX), 1585 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1586 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1587 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1588 for (i = 1; i <= sc->sc_noport; i++) 1589 printf("port %d status=0x%08x\n", i, 1590 EOREAD4(sc, EHCI_PORTSC(i))); 1591 } 1592 1593 Static void 1594 ehci_dump_regs(ehci_softc_t *sc) 1595 { 1596 int i; 1597 1598 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1599 1600 USBHIST_LOG(ehcidebug, 1601 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1602 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1603 EOREAD4(sc, EHCI_USBINTR), 0); 1604 USBHIST_LOG(ehcidebug, 1605 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1606 "async = 0x%08x", 1607 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1608 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1609 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1610 for (i = 1; i <= sc->sc_noport; i += 2) { 1611 if (i == sc->sc_noport) { 1612 USBHIST_LOG(ehcidebug, 1613 "port %d status = 0x%08x", i, 1614 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1615 } else { 1616 USBHIST_LOG(ehcidebug, 1617 "port %d status = 0x%08x port %d status = 0x%08x", 1618 i, EOREAD4(sc, EHCI_PORTSC(i)), 1619 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1620 } 1621 } 1622 } 1623 1624 #ifdef EHCI_DEBUG 1625 #define ehci_dump_link(link, type) do { \ 1626 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1627 link, \ 1628 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1629 if (type) { \ 1630 USBHIST_LOG(ehcidebug, \ 1631 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1632 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1633 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1634 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1635 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1636 } \ 1637 } while(0) 1638 #else 1639 #define ehci_dump_link(link, type) 1640 #endif 1641 1642 Static void 1643 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1644 { 1645 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1646 int i; 1647 uint32_t stop = 0; 1648 1649 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1650 ehci_dump_sqtd(sqtd); 1651 usb_syncmem(&sqtd->dma, 1652 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1653 sizeof(sqtd->qtd), 1654 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1655 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1656 usb_syncmem(&sqtd->dma, 1657 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1658 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1659 } 1660 if (sqtd) 1661 USBHIST_LOG(ehcidebug, 1662 "dump aborted, too many TDs", 0, 0, 0, 0); 1663 } 1664 1665 Static void 1666 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1667 { 1668 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1669 1670 usb_syncmem(&sqtd->dma, sqtd->offs, 1671 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1672 1673 USBHIST_LOGN(ehcidebug, 10, 1674 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1675 ehci_dump_qtd(&sqtd->qtd); 1676 1677 usb_syncmem(&sqtd->dma, sqtd->offs, 1678 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1679 } 1680 1681 Static void 1682 ehci_dump_qtd(ehci_qtd_t *qtd) 1683 { 1684 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1685 1686 #ifdef USBHIST 1687 uint32_t s = le32toh(qtd->qtd_status); 1688 #endif 1689 1690 USBHIST_LOGN(ehcidebug, 10, 1691 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1692 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1693 USBHIST_LOGN(ehcidebug, 10, 1694 " toggle = %d ioc = %d bytes = %#x " 1695 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1696 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1697 USBHIST_LOGN(ehcidebug, 10, 1698 " cerr = %d pid = %d stat = %x", 1699 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1700 0); 1701 USBHIST_LOGN(ehcidebug, 10, 1702 "active =%d halted=%d buferr=%d babble=%d", 1703 s & EHCI_QTD_ACTIVE ? 1 : 0, 1704 s & EHCI_QTD_HALTED ? 1 : 0, 1705 s & EHCI_QTD_BUFERR ? 1 : 0, 1706 s & EHCI_QTD_BABBLE ? 1 : 0); 1707 USBHIST_LOGN(ehcidebug, 10, 1708 "xacterr=%d missed=%d split =%d ping =%d", 1709 s & EHCI_QTD_XACTERR ? 1 : 0, 1710 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1711 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1712 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1713 USBHIST_LOGN(ehcidebug, 10, 1714 "buffer[0] = %#x buffer[1] = %#x " 1715 "buffer[2] = %#x buffer[3] = %#x", 1716 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1717 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1718 USBHIST_LOGN(ehcidebug, 10, 1719 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1720 } 1721 1722 Static void 1723 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1724 { 1725 #ifdef USBHIST 1726 ehci_qh_t *qh = &sqh->qh; 1727 ehci_link_t link; 1728 #endif 1729 uint32_t endp, endphub; 1730 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1731 1732 usb_syncmem(&sqh->dma, sqh->offs, 1733 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1734 1735 USBHIST_LOGN(ehcidebug, 10, 1736 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1737 link = le32toh(qh->qh_link); 1738 ehci_dump_link(link, true); 1739 1740 endp = le32toh(qh->qh_endp); 1741 USBHIST_LOGN(ehcidebug, 10, 1742 " endp = %#x", endp, 0, 0, 0); 1743 USBHIST_LOGN(ehcidebug, 10, 1744 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1745 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1746 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1747 USBHIST_LOGN(ehcidebug, 10, 1748 " dtc = %d hrecl = %d", 1749 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1750 USBHIST_LOGN(ehcidebug, 10, 1751 " ctl = %d nrl = %d mpl = %#x(%d)", 1752 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1753 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1754 1755 endphub = le32toh(qh->qh_endphub); 1756 USBHIST_LOGN(ehcidebug, 10, 1757 " endphub = %#x", endphub, 0, 0, 0); 1758 USBHIST_LOGN(ehcidebug, 10, 1759 " smask = 0x%02x cmask = 0x%02x", 1760 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1761 USBHIST_LOGN(ehcidebug, 10, 1762 " huba = 0x%02x port = %d mult = %d", 1763 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1764 EHCI_QH_GET_MULT(endphub), 0); 1765 1766 link = le32toh(qh->qh_curqtd); 1767 ehci_dump_link(link, false); 1768 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1769 ehci_dump_qtd(&qh->qh_qtd); 1770 1771 usb_syncmem(&sqh->dma, sqh->offs, 1772 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1773 } 1774 1775 Static void 1776 ehci_dump_itd(struct ehci_soft_itd *itd) 1777 { 1778 ehci_isoc_trans_t t; 1779 ehci_isoc_bufr_ptr_t b, b2, b3; 1780 int i; 1781 1782 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1783 1784 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1785 0, 0); 1786 1787 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1788 t = le32toh(itd->itd.itd_ctl[i]); 1789 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1790 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1791 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1792 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1793 EHCI_ITD_GET_OFFS(t), 0); 1794 } 1795 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1796 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1797 USBHIST_LOG(ehcidebug, " %x", 1798 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1799 1800 b = le32toh(itd->itd.itd_bufr[0]); 1801 b2 = le32toh(itd->itd.itd_bufr[1]); 1802 b3 = le32toh(itd->itd.itd_bufr[2]); 1803 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1804 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1805 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1806 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1807 } 1808 1809 Static void 1810 ehci_dump_sitd(struct ehci_soft_itd *itd) 1811 { 1812 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1813 1814 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1815 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1816 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1817 itd->xfer_next, itd->physaddr, itd->slot, 0); 1818 } 1819 1820 Static void 1821 ehci_dump_exfer(struct ehci_xfer *ex) 1822 { 1823 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1824 1825 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1826 ex, ex->ex_sqtdstart, ex->ex_sqtdend, 0); 1827 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1828 ex->ex_itdstart, ex->ex_itdend, ex->ex_isdone, 0); 1829 } 1830 #endif 1831 1832 Static usbd_status 1833 ehci_open(usbd_pipe_handle pipe) 1834 { 1835 usbd_device_handle dev = pipe->up_dev; 1836 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1837 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1838 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1839 uint8_t addr = dev->ud_addr; 1840 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1841 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1842 ehci_soft_qh_t *sqh; 1843 usbd_status err; 1844 int ival, speed, naks; 1845 int hshubaddr, hshubport; 1846 1847 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1848 1849 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1850 pipe, addr, ed->bEndpointAddress, rhaddr); 1851 1852 if (dev->ud_myhsport) { 1853 /* 1854 * When directly attached FS/LS device while doing embedded 1855 * transaction translations and we are the hub, set the hub 1856 * address to 0 (us). 1857 */ 1858 if (!(sc->sc_flags & EHCIF_ETTF) 1859 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1860 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1861 } else { 1862 hshubaddr = 0; 1863 } 1864 hshubport = dev->ud_myhsport->up_portno; 1865 } else { 1866 hshubaddr = 0; 1867 hshubport = 0; 1868 } 1869 1870 if (sc->sc_dying) 1871 return USBD_IOERROR; 1872 1873 /* toggle state needed for bulk endpoints */ 1874 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1875 1876 if (addr == rhaddr) { 1877 switch (ed->bEndpointAddress) { 1878 case USB_CONTROL_ENDPOINT: 1879 pipe->up_methods = &roothub_ctrl_methods; 1880 break; 1881 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1882 pipe->up_methods = &ehci_root_intr_methods; 1883 break; 1884 default: 1885 USBHIST_LOG(ehcidebug, 1886 "bad bEndpointAddress 0x%02x", 1887 ed->bEndpointAddress, 0, 0, 0); 1888 return USBD_INVAL; 1889 } 1890 return USBD_NORMAL_COMPLETION; 1891 } 1892 1893 /* XXX All this stuff is only valid for async. */ 1894 switch (dev->ud_speed) { 1895 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1896 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1897 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1898 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1899 } 1900 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1901 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1902 hshubaddr, hshubport, 0, 0); 1903 return USBD_INVAL; 1904 } 1905 1906 /* 1907 * For interrupt transfer, nak throttling must be disabled, but for 1908 * the other transfer type, nak throttling should be enabled from the 1909 * viewpoint that avoids the memory thrashing. 1910 */ 1911 naks = (xfertype == UE_INTERRUPT) ? 0 1912 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1913 1914 /* Allocate sqh for everything, save isoc xfers */ 1915 if (xfertype != UE_ISOCHRONOUS) { 1916 sqh = ehci_alloc_sqh(sc); 1917 if (sqh == NULL) 1918 return USBD_NOMEM; 1919 /* qh_link filled when the QH is added */ 1920 sqh->qh.qh_endp = htole32( 1921 EHCI_QH_SET_ADDR(addr) | 1922 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1923 EHCI_QH_SET_EPS(speed) | 1924 EHCI_QH_DTC | 1925 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1926 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1927 EHCI_QH_CTL : 0) | 1928 EHCI_QH_SET_NRL(naks) 1929 ); 1930 sqh->qh.qh_endphub = htole32( 1931 EHCI_QH_SET_MULT(1) | 1932 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1933 ); 1934 if (speed != EHCI_QH_SPEED_HIGH) 1935 sqh->qh.qh_endphub |= htole32( 1936 EHCI_QH_SET_PORT(hshubport) | 1937 EHCI_QH_SET_HUBA(hshubaddr) | 1938 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1939 ); 1940 sqh->qh.qh_curqtd = EHCI_NULL; 1941 /* Fill the overlay qTD */ 1942 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1943 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1944 sqh->qh.qh_qtd.qtd_status = htole32(0); 1945 1946 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1947 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1948 epipe->sqh = sqh; 1949 } else { 1950 sqh = NULL; 1951 } /*xfertype == UE_ISOC*/ 1952 1953 switch (xfertype) { 1954 case UE_CONTROL: 1955 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1956 0, &epipe->u.ctl.reqdma); 1957 #ifdef EHCI_DEBUG 1958 if (err) 1959 printf("ehci_open: usb_allocmem()=%d\n", err); 1960 #endif 1961 if (err) 1962 goto bad; 1963 pipe->up_methods = &ehci_device_ctrl_methods; 1964 mutex_enter(&sc->sc_lock); 1965 ehci_add_qh(sc, sqh, sc->sc_async_head); 1966 mutex_exit(&sc->sc_lock); 1967 break; 1968 case UE_BULK: 1969 pipe->up_methods = &ehci_device_bulk_methods; 1970 mutex_enter(&sc->sc_lock); 1971 ehci_add_qh(sc, sqh, sc->sc_async_head); 1972 mutex_exit(&sc->sc_lock); 1973 break; 1974 case UE_INTERRUPT: 1975 pipe->up_methods = &ehci_device_intr_methods; 1976 ival = pipe->up_interval; 1977 if (ival == USBD_DEFAULT_INTERVAL) { 1978 if (speed == EHCI_QH_SPEED_HIGH) { 1979 if (ed->bInterval > 16) { 1980 /* 1981 * illegal with high-speed, but there 1982 * were documentation bugs in the spec, 1983 * so be generous 1984 */ 1985 ival = 256; 1986 } else 1987 ival = (1 << (ed->bInterval - 1)) / 8; 1988 } else 1989 ival = ed->bInterval; 1990 } 1991 err = ehci_device_setintr(sc, sqh, ival); 1992 if (err) 1993 goto bad; 1994 break; 1995 case UE_ISOCHRONOUS: 1996 if (speed == EHCI_QH_SPEED_HIGH) 1997 pipe->up_methods = &ehci_device_isoc_methods; 1998 else 1999 pipe->up_methods = &ehci_device_fs_isoc_methods; 2000 if (ed->bInterval == 0 || ed->bInterval > 16) { 2001 printf("ehci: opening pipe with invalid bInterval\n"); 2002 err = USBD_INVAL; 2003 goto bad; 2004 } 2005 if (UGETW(ed->wMaxPacketSize) == 0) { 2006 printf("ehci: zero length endpoint open request\n"); 2007 err = USBD_INVAL; 2008 goto bad; 2009 } 2010 epipe->u.isoc.next_frame = 0; 2011 epipe->u.isoc.cur_xfers = 0; 2012 break; 2013 default: 2014 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2015 err = USBD_INVAL; 2016 goto bad; 2017 } 2018 return USBD_NORMAL_COMPLETION; 2019 2020 bad: 2021 if (sqh != NULL) 2022 ehci_free_sqh(sc, sqh); 2023 return err; 2024 } 2025 2026 /* 2027 * Add an ED to the schedule. Called with USB lock held. 2028 */ 2029 Static void 2030 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2031 { 2032 2033 KASSERT(mutex_owned(&sc->sc_lock)); 2034 2035 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2036 2037 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2038 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2039 2040 sqh->next = head->next; 2041 sqh->qh.qh_link = head->qh.qh_link; 2042 2043 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2044 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2045 2046 head->next = sqh; 2047 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2048 2049 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2050 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2051 2052 #ifdef EHCI_DEBUG 2053 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2054 ehci_dump_sqh(sqh); 2055 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2056 #endif 2057 } 2058 2059 /* 2060 * Remove an ED from the schedule. Called with USB lock held. 2061 */ 2062 Static void 2063 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2064 { 2065 ehci_soft_qh_t *p; 2066 2067 KASSERT(mutex_owned(&sc->sc_lock)); 2068 2069 /* XXX */ 2070 for (p = head; p != NULL && p->next != sqh; p = p->next) 2071 ; 2072 if (p == NULL) 2073 panic("ehci_rem_qh: ED not found"); 2074 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2075 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2076 p->next = sqh->next; 2077 p->qh.qh_link = sqh->qh.qh_link; 2078 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2079 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2080 2081 ehci_sync_hc(sc); 2082 } 2083 2084 Static void 2085 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2086 { 2087 int i; 2088 uint32_t status; 2089 2090 /* Save toggle bit and ping status. */ 2091 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2092 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2093 status = sqh->qh.qh_qtd.qtd_status & 2094 htole32(EHCI_QTD_TOGGLE_MASK | 2095 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2096 /* Set HALTED to make hw leave it alone. */ 2097 sqh->qh.qh_qtd.qtd_status = 2098 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2099 usb_syncmem(&sqh->dma, 2100 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2101 sizeof(sqh->qh.qh_qtd.qtd_status), 2102 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2103 sqh->qh.qh_curqtd = 0; 2104 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2105 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2106 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2107 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2108 sqh->sqtd = sqtd; 2109 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2110 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2111 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2112 sqh->qh.qh_qtd.qtd_status = status; 2113 usb_syncmem(&sqh->dma, 2114 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2115 sizeof(sqh->qh.qh_qtd.qtd_status), 2116 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2117 } 2118 2119 /* 2120 * Ensure that the HC has released all references to the QH. We do this 2121 * by asking for a Async Advance Doorbell interrupt and then we wait for 2122 * the interrupt. 2123 * To make this easier we first obtain exclusive use of the doorbell. 2124 */ 2125 Static void 2126 ehci_sync_hc(ehci_softc_t *sc) 2127 { 2128 int error __diagused; 2129 2130 KASSERT(mutex_owned(&sc->sc_lock)); 2131 2132 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2133 2134 if (sc->sc_dying) { 2135 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2136 return; 2137 } 2138 /* ask for doorbell */ 2139 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2140 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2141 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2142 2143 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2144 2145 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2146 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2147 #ifdef DIAGNOSTIC 2148 if (error) 2149 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2150 #endif 2151 } 2152 2153 Static void 2154 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2155 { 2156 struct ehci_soft_itd *itd, *prev; 2157 2158 prev = NULL; 2159 2160 if (exfer->ex_itdstart == NULL || exfer->ex_itdend == NULL) 2161 panic("ehci isoc xfer being freed, but with no itd chain\n"); 2162 2163 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2164 prev = itd->u.frame_list.prev; 2165 /* Unlink itd from hardware chain, or frame array */ 2166 if (prev == NULL) { /* We're at the table head */ 2167 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2168 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2169 usb_syncmem(&sc->sc_fldma, 2170 sizeof(ehci_link_t) * itd->slot, 2171 sizeof(ehci_link_t), 2172 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2173 2174 if (itd->u.frame_list.next != NULL) 2175 itd->u.frame_list.next->u.frame_list.prev = NULL; 2176 } else { 2177 /* XXX this part is untested... */ 2178 prev->itd.itd_next = itd->itd.itd_next; 2179 usb_syncmem(&itd->dma, 2180 itd->offs + offsetof(ehci_itd_t, itd_next), 2181 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2182 2183 prev->u.frame_list.next = itd->u.frame_list.next; 2184 if (itd->u.frame_list.next != NULL) 2185 itd->u.frame_list.next->u.frame_list.prev = prev; 2186 } 2187 } 2188 2189 prev = NULL; 2190 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2191 if (prev != NULL) 2192 ehci_free_itd(sc, prev); 2193 prev = itd; 2194 } 2195 if (prev) 2196 ehci_free_itd(sc, prev); 2197 exfer->ex_itdstart = NULL; 2198 exfer->ex_itdend = NULL; 2199 } 2200 2201 Static void 2202 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2203 { 2204 struct ehci_soft_sitd *sitd, *prev; 2205 2206 prev = NULL; 2207 2208 if (exfer->ex_sitdstart == NULL || exfer->ex_sitdend == NULL) 2209 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2210 2211 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2212 prev = sitd->u.frame_list.prev; 2213 /* Unlink sitd from hardware chain, or frame array */ 2214 if (prev == NULL) { /* We're at the table head */ 2215 sc->sc_softsitds[sitd->slot] = sitd->u.frame_list.next; 2216 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2217 usb_syncmem(&sc->sc_fldma, 2218 sizeof(ehci_link_t) * sitd->slot, 2219 sizeof(ehci_link_t), 2220 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2221 2222 if (sitd->u.frame_list.next != NULL) 2223 sitd->u.frame_list.next->u.frame_list.prev = NULL; 2224 } else { 2225 /* XXX this part is untested... */ 2226 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2227 usb_syncmem(&sitd->dma, 2228 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2229 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2230 2231 prev->u.frame_list.next = sitd->u.frame_list.next; 2232 if (sitd->u.frame_list.next != NULL) 2233 sitd->u.frame_list.next->u.frame_list.prev = prev; 2234 } 2235 } 2236 2237 prev = NULL; 2238 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2239 if (prev != NULL) 2240 ehci_free_sitd(sc, prev); 2241 prev = sitd; 2242 } 2243 if (prev) 2244 ehci_free_sitd(sc, prev); 2245 exfer->ex_sitdstart = NULL; 2246 exfer->ex_sitdend = NULL; 2247 } 2248 2249 /***********/ 2250 2251 Static int 2252 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2253 void *buf, int buflen) 2254 { 2255 ehci_softc_t *sc = bus->ub_hcpriv; 2256 usb_hub_descriptor_t hubd; 2257 usb_port_status_t ps; 2258 uint16_t len, value, index; 2259 int l, totlen = 0; 2260 int port, i; 2261 uint32_t v; 2262 2263 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2264 2265 if (sc->sc_dying) 2266 return -1; 2267 2268 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2269 req->bmRequestType, req->bRequest, 0, 0); 2270 2271 len = UGETW(req->wLength); 2272 value = UGETW(req->wValue); 2273 index = UGETW(req->wIndex); 2274 2275 #define C(x,y) ((x) | ((y) << 8)) 2276 switch (C(req->bRequest, req->bmRequestType)) { 2277 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2278 if (len == 0) 2279 break; 2280 switch (value) { 2281 case C(0, UDESC_DEVICE): { 2282 usb_device_descriptor_t devd; 2283 totlen = min(buflen, sizeof(devd)); 2284 memcpy(&devd, buf, totlen); 2285 USETW(devd.idVendor, sc->sc_id_vendor); 2286 memcpy(buf, &devd, totlen); 2287 break; 2288 2289 } 2290 #define sd ((usb_string_descriptor_t *)buf) 2291 case C(1, UDESC_STRING): 2292 /* Vendor */ 2293 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2294 break; 2295 case C(2, UDESC_STRING): 2296 /* Product */ 2297 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2298 break; 2299 #undef sd 2300 default: 2301 /* default from usbroothub */ 2302 return buflen; 2303 } 2304 break; 2305 2306 /* Hub requests */ 2307 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2308 break; 2309 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2310 USBHIST_LOG(ehcidebug, 2311 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2312 0, 0); 2313 if (index < 1 || index > sc->sc_noport) { 2314 return -1; 2315 } 2316 port = EHCI_PORTSC(index); 2317 v = EOREAD4(sc, port); 2318 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2319 v &= ~EHCI_PS_CLEAR; 2320 switch (value) { 2321 case UHF_PORT_ENABLE: 2322 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2323 break; 2324 case UHF_PORT_SUSPEND: 2325 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2326 break; 2327 v &= ~EHCI_PS_SUSP; 2328 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2329 /* see USB2 spec ch. 7.1.7.7 */ 2330 usb_delay_ms(&sc->sc_bus, 20); 2331 EOWRITE4(sc, port, v); 2332 usb_delay_ms(&sc->sc_bus, 2); 2333 #ifdef DEBUG 2334 v = EOREAD4(sc, port); 2335 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2336 printf("ehci: resume failed: %x\n", v); 2337 #endif 2338 break; 2339 case UHF_PORT_POWER: 2340 if (sc->sc_hasppc) 2341 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2342 break; 2343 case UHF_PORT_TEST: 2344 USBHIST_LOG(ehcidebug, "clear port test " 2345 "%d", index, 0, 0, 0); 2346 break; 2347 case UHF_PORT_INDICATOR: 2348 USBHIST_LOG(ehcidebug, "clear port ind " 2349 "%d", index, 0, 0, 0); 2350 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2351 break; 2352 case UHF_C_PORT_CONNECTION: 2353 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2354 break; 2355 case UHF_C_PORT_ENABLE: 2356 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2357 break; 2358 case UHF_C_PORT_SUSPEND: 2359 /* how? */ 2360 break; 2361 case UHF_C_PORT_OVER_CURRENT: 2362 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2363 break; 2364 case UHF_C_PORT_RESET: 2365 sc->sc_isreset[index] = 0; 2366 break; 2367 default: 2368 return -1; 2369 } 2370 #if 0 2371 switch(value) { 2372 case UHF_C_PORT_CONNECTION: 2373 case UHF_C_PORT_ENABLE: 2374 case UHF_C_PORT_SUSPEND: 2375 case UHF_C_PORT_OVER_CURRENT: 2376 case UHF_C_PORT_RESET: 2377 default: 2378 break; 2379 } 2380 #endif 2381 break; 2382 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2383 if (len == 0) 2384 break; 2385 if ((value & 0xff) != 0) { 2386 return -1; 2387 } 2388 totlen = min(buflen, sizeof(hubd)); 2389 memcpy(&hubd, buf, totlen); 2390 hubd.bNbrPorts = sc->sc_noport; 2391 v = EOREAD4(sc, EHCI_HCSPARAMS); 2392 USETW(hubd.wHubCharacteristics, 2393 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2394 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2395 ? UHD_PORT_IND : 0); 2396 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2397 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2398 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2399 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2400 totlen = min(totlen, hubd.bDescLength); 2401 memcpy(buf, &hubd, totlen); 2402 break; 2403 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2404 if (len != 4) { 2405 return -1; 2406 } 2407 memset(buf, 0, len); /* ? XXX */ 2408 totlen = len; 2409 break; 2410 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2411 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2412 if (index < 1 || index > sc->sc_noport) { 2413 return -1; 2414 } 2415 if (len != 4) { 2416 return -1; 2417 } 2418 v = EOREAD4(sc, EHCI_PORTSC(index)); 2419 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2420 2421 i = UPS_HIGH_SPEED; 2422 if (sc->sc_flags & EHCIF_ETTF) { 2423 /* 2424 * If we are doing embedded transaction translation, 2425 * then directly attached LS/FS devices are reset by 2426 * the EHCI controller itself. PSPD is encoded 2427 * the same way as in USBSTATUS. 2428 */ 2429 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2430 } 2431 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2432 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2433 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2434 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2435 if (v & EHCI_PS_PR) i |= UPS_RESET; 2436 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2437 if (sc->sc_vendor_port_status) 2438 i = sc->sc_vendor_port_status(sc, v, i); 2439 USETW(ps.wPortStatus, i); 2440 i = 0; 2441 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2442 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2443 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2444 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2445 USETW(ps.wPortChange, i); 2446 totlen = min(len, sizeof(ps)); 2447 memcpy(buf, &ps, totlen); 2448 break; 2449 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2450 return -1; 2451 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2452 break; 2453 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2454 if (index < 1 || index > sc->sc_noport) { 2455 return -1; 2456 } 2457 port = EHCI_PORTSC(index); 2458 v = EOREAD4(sc, port); 2459 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2460 v &= ~EHCI_PS_CLEAR; 2461 switch(value) { 2462 case UHF_PORT_ENABLE: 2463 EOWRITE4(sc, port, v | EHCI_PS_PE); 2464 break; 2465 case UHF_PORT_SUSPEND: 2466 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2467 break; 2468 case UHF_PORT_RESET: 2469 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2470 if (EHCI_PS_IS_LOWSPEED(v) 2471 && sc->sc_ncomp > 0 2472 && !(sc->sc_flags & EHCIF_ETTF)) { 2473 /* 2474 * Low speed device on non-ETTF controller or 2475 * unaccompanied controller, give up ownership. 2476 */ 2477 ehci_disown(sc, index, 1); 2478 break; 2479 } 2480 /* Start reset sequence. */ 2481 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2482 EOWRITE4(sc, port, v | EHCI_PS_PR); 2483 /* Wait for reset to complete. */ 2484 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2485 if (sc->sc_dying) { 2486 return -1; 2487 } 2488 /* 2489 * An embedded transaction translator will automatically 2490 * terminate the reset sequence so there's no need to 2491 * it. 2492 */ 2493 v = EOREAD4(sc, port); 2494 if (v & EHCI_PS_PR) { 2495 /* Terminate reset sequence. */ 2496 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2497 /* Wait for HC to complete reset. */ 2498 usb_delay_ms(&sc->sc_bus, 2499 EHCI_PORT_RESET_COMPLETE); 2500 if (sc->sc_dying) { 2501 return -1; 2502 } 2503 } 2504 2505 v = EOREAD4(sc, port); 2506 USBHIST_LOG(ehcidebug, 2507 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2508 if (v & EHCI_PS_PR) { 2509 printf("%s: port reset timeout\n", 2510 device_xname(sc->sc_dev)); 2511 return USBD_TIMEOUT; 2512 } 2513 if (!(v & EHCI_PS_PE)) { 2514 /* Not a high speed device, give up ownership.*/ 2515 ehci_disown(sc, index, 0); 2516 break; 2517 } 2518 sc->sc_isreset[index] = 1; 2519 USBHIST_LOG(ehcidebug, 2520 "ehci port %d reset, status = 0x%08x", index, v, 0, 2521 0); 2522 break; 2523 case UHF_PORT_POWER: 2524 USBHIST_LOG(ehcidebug, 2525 "set port power %d (has PPC = %d)", index, 2526 sc->sc_hasppc, 0, 0); 2527 if (sc->sc_hasppc) 2528 EOWRITE4(sc, port, v | EHCI_PS_PP); 2529 break; 2530 case UHF_PORT_TEST: 2531 USBHIST_LOG(ehcidebug, "set port test %d", 2532 index, 0, 0, 0); 2533 break; 2534 case UHF_PORT_INDICATOR: 2535 USBHIST_LOG(ehcidebug, "set port ind %d", 2536 index, 0, 0, 0); 2537 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2538 break; 2539 default: 2540 return -1; 2541 } 2542 break; 2543 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2544 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2545 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2546 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2547 break; 2548 default: 2549 /* default from usbroothub */ 2550 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2551 buflen, 0, 0, 0); 2552 2553 return buflen; 2554 } 2555 2556 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2557 2558 return totlen; 2559 } 2560 2561 Static void 2562 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2563 { 2564 int port; 2565 uint32_t v; 2566 2567 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2568 2569 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2570 #ifdef DIAGNOSTIC 2571 if (sc->sc_npcomp != 0) { 2572 int i = (index-1) / sc->sc_npcomp; 2573 if (i >= sc->sc_ncomp) 2574 printf("%s: strange port\n", 2575 device_xname(sc->sc_dev)); 2576 else 2577 printf("%s: handing over %s speed device on " 2578 "port %d to %s\n", 2579 device_xname(sc->sc_dev), 2580 lowspeed ? "low" : "full", 2581 index, device_xname(sc->sc_comps[i])); 2582 } else { 2583 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2584 } 2585 #endif 2586 port = EHCI_PORTSC(index); 2587 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2588 EOWRITE4(sc, port, v | EHCI_PS_PO); 2589 } 2590 2591 Static usbd_status 2592 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2593 { 2594 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2595 usbd_status err; 2596 2597 /* Insert last in queue. */ 2598 mutex_enter(&sc->sc_lock); 2599 err = usb_insert_transfer(xfer); 2600 mutex_exit(&sc->sc_lock); 2601 if (err) 2602 return err; 2603 2604 /* Pipe isn't running, start first */ 2605 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2606 } 2607 2608 Static usbd_status 2609 ehci_root_intr_start(usbd_xfer_handle xfer) 2610 { 2611 usbd_pipe_handle pipe = xfer->ux_pipe; 2612 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2613 2614 if (sc->sc_dying) 2615 return USBD_IOERROR; 2616 2617 mutex_enter(&sc->sc_lock); 2618 sc->sc_intrxfer = xfer; 2619 mutex_exit(&sc->sc_lock); 2620 2621 return USBD_IN_PROGRESS; 2622 } 2623 2624 /* Abort a root interrupt request. */ 2625 Static void 2626 ehci_root_intr_abort(usbd_xfer_handle xfer) 2627 { 2628 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2629 2630 KASSERT(mutex_owned(&sc->sc_lock)); 2631 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2632 2633 sc->sc_intrxfer = NULL; 2634 2635 xfer->ux_status = USBD_CANCELLED; 2636 usb_transfer_complete(xfer); 2637 } 2638 2639 /* Close the root pipe. */ 2640 Static void 2641 ehci_root_intr_close(usbd_pipe_handle pipe) 2642 { 2643 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2644 2645 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2646 2647 KASSERT(mutex_owned(&sc->sc_lock)); 2648 2649 sc->sc_intrxfer = NULL; 2650 } 2651 2652 Static void 2653 ehci_root_intr_done(usbd_xfer_handle xfer) 2654 { 2655 xfer->ux_hcpriv = NULL; 2656 } 2657 2658 /************************/ 2659 2660 Static ehci_soft_qh_t * 2661 ehci_alloc_sqh(ehci_softc_t *sc) 2662 { 2663 ehci_soft_qh_t *sqh; 2664 usbd_status err; 2665 int i, offs; 2666 usb_dma_t dma; 2667 2668 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2669 2670 if (sc->sc_freeqhs == NULL) { 2671 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2672 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2673 EHCI_PAGE_SIZE, &dma); 2674 #ifdef EHCI_DEBUG 2675 if (err) 2676 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2677 #endif 2678 if (err) 2679 return NULL; 2680 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2681 offs = i * EHCI_SQH_SIZE; 2682 sqh = KERNADDR(&dma, offs); 2683 sqh->physaddr = DMAADDR(&dma, offs); 2684 sqh->dma = dma; 2685 sqh->offs = offs; 2686 sqh->next = sc->sc_freeqhs; 2687 sc->sc_freeqhs = sqh; 2688 } 2689 } 2690 sqh = sc->sc_freeqhs; 2691 sc->sc_freeqhs = sqh->next; 2692 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2693 sqh->next = NULL; 2694 return sqh; 2695 } 2696 2697 Static void 2698 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2699 { 2700 sqh->next = sc->sc_freeqhs; 2701 sc->sc_freeqhs = sqh; 2702 } 2703 2704 Static ehci_soft_qtd_t * 2705 ehci_alloc_sqtd(ehci_softc_t *sc) 2706 { 2707 ehci_soft_qtd_t *sqtd = NULL; 2708 usbd_status err; 2709 int i, offs; 2710 usb_dma_t dma; 2711 2712 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2713 2714 if (sc->sc_freeqtds == NULL) { 2715 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2716 2717 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2718 EHCI_PAGE_SIZE, &dma); 2719 #ifdef EHCI_DEBUG 2720 if (err) 2721 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2722 #endif 2723 if (err) 2724 goto done; 2725 2726 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2727 offs = i * EHCI_SQTD_SIZE; 2728 sqtd = KERNADDR(&dma, offs); 2729 sqtd->physaddr = DMAADDR(&dma, offs); 2730 sqtd->dma = dma; 2731 sqtd->offs = offs; 2732 2733 sqtd->nextqtd = sc->sc_freeqtds; 2734 sc->sc_freeqtds = sqtd; 2735 } 2736 } 2737 2738 sqtd = sc->sc_freeqtds; 2739 sc->sc_freeqtds = sqtd->nextqtd; 2740 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2741 sqtd->nextqtd = NULL; 2742 sqtd->xfer = NULL; 2743 2744 done: 2745 return sqtd; 2746 } 2747 2748 Static void 2749 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2750 { 2751 2752 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2753 2754 sqtd->nextqtd = sc->sc_freeqtds; 2755 sc->sc_freeqtds = sqtd; 2756 } 2757 2758 Static usbd_status 2759 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2760 int alen, int rd, usbd_xfer_handle xfer, 2761 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2762 { 2763 ehci_soft_qtd_t *next, *cur; 2764 ehci_physaddr_t nextphys; 2765 uint32_t qtdstatus; 2766 int len, curlen, mps; 2767 int i, tog; 2768 int pages, pageoffs; 2769 bus_size_t curoffs; 2770 vaddr_t va, va_offs; 2771 usb_dma_t *dma = &xfer->ux_dmabuf; 2772 uint16_t flags = xfer->ux_flags; 2773 paddr_t a; 2774 2775 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2776 2777 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2778 2779 len = alen; 2780 qtdstatus = EHCI_QTD_ACTIVE | 2781 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2782 EHCI_QTD_SET_CERR(3) 2783 /* IOC set below */ 2784 /* BYTES set below */ 2785 ; 2786 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 2787 tog = epipe->nexttoggle; 2788 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2789 2790 cur = ehci_alloc_sqtd(sc); 2791 *sp = cur; 2792 if (cur == NULL) 2793 goto nomem; 2794 2795 usb_syncmem(dma, 0, alen, 2796 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2797 curoffs = 0; 2798 for (;;) { 2799 /* The EHCI hardware can handle at most 5 pages. */ 2800 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2801 va_offs = EHCI_PAGE_OFFSET(va_offs); 2802 if (len-curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2803 /* we can handle it in this QTD */ 2804 curlen = len - curoffs; 2805 } else { 2806 /* must use multiple TDs, fill as much as possible. */ 2807 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2808 2809 /* the length must be a multiple of the max size */ 2810 curlen -= curlen % mps; 2811 USBHIST_LOG(ehcidebug, "multiple QTDs, " 2812 "curlen=%d", curlen, 0, 0, 0); 2813 KASSERT(curlen != 0); 2814 } 2815 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 2816 len, curlen, (size_t)curoffs, 0); 2817 2818 /* 2819 * Allocate another transfer if there's more data left, 2820 * or if force last short transfer flag is set and we're 2821 * allocating a multiple of the max packet size. 2822 */ 2823 2824 if (curoffs + curlen != len || 2825 ((curlen % mps) == 0 && !rd && curlen != 0 && 2826 (flags & USBD_FORCE_SHORT_XFER))) { 2827 next = ehci_alloc_sqtd(sc); 2828 if (next == NULL) 2829 goto nomem; 2830 nextphys = htole32(next->physaddr); 2831 } else { 2832 next = NULL; 2833 nextphys = EHCI_NULL; 2834 } 2835 2836 /* Find number of pages we'll be using, insert dma addresses */ 2837 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2838 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2839 pageoffs = EHCI_PAGE(curoffs); 2840 for (i = 0; i < pages; i++) { 2841 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2842 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2843 /* Cast up to avoid compiler warnings */ 2844 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2845 } 2846 2847 /* First buffer pointer requires a page offset to start at */ 2848 va = (vaddr_t)KERNADDR(dma, curoffs); 2849 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2850 2851 cur->nextqtd = next; 2852 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2853 cur->qtd.qtd_status = 2854 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2855 cur->xfer = xfer; 2856 cur->len = curlen; 2857 2858 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2859 (size_t)curoffs, (size_t)(curoffs + curlen), 0, 0); 2860 2861 /* 2862 * adjust the toggle based on the number of packets in this 2863 * qtd 2864 */ 2865 if (((curlen + mps - 1) / mps) & 1) { 2866 tog ^= 1; 2867 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2868 } 2869 if (next == NULL) 2870 break; 2871 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2872 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2873 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2874 if (len) 2875 curoffs += curlen; 2876 cur = next; 2877 } 2878 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2879 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2880 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2881 *ep = cur; 2882 epipe->nexttoggle = tog; 2883 2884 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 2885 *sp, *ep, 0, 0); 2886 2887 return USBD_NORMAL_COMPLETION; 2888 2889 nomem: 2890 /* XXX free chain */ 2891 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2892 return USBD_NOMEM; 2893 } 2894 2895 Static void 2896 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2897 ehci_soft_qtd_t *sqtdend) 2898 { 2899 ehci_soft_qtd_t *p; 2900 int i; 2901 2902 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2903 2904 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 2905 sqtd, sqtdend, 0, 0); 2906 2907 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2908 p = sqtd->nextqtd; 2909 ehci_free_sqtd(sc, sqtd); 2910 } 2911 } 2912 2913 Static ehci_soft_itd_t * 2914 ehci_alloc_itd(ehci_softc_t *sc) 2915 { 2916 struct ehci_soft_itd *itd, *freeitd; 2917 usbd_status err; 2918 int i, offs, frindex, previndex; 2919 usb_dma_t dma; 2920 2921 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2922 2923 mutex_enter(&sc->sc_lock); 2924 2925 /* 2926 * Find an itd that wasn't freed this frame or last frame. This can 2927 * discard itds that were freed before frindex wrapped around 2928 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2929 * interrupt and fiddling with list when that happens 2930 */ 2931 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2932 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2933 2934 freeitd = NULL; 2935 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2936 if (itd == NULL) 2937 break; 2938 if (itd->slot != frindex && itd->slot != previndex) { 2939 freeitd = itd; 2940 break; 2941 } 2942 } 2943 2944 if (freeitd == NULL) { 2945 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2946 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2947 EHCI_PAGE_SIZE, &dma); 2948 2949 if (err) { 2950 USBHIST_LOG(ehcidebug, 2951 "alloc returned %d", err, 0, 0, 0); 2952 mutex_exit(&sc->sc_lock); 2953 return NULL; 2954 } 2955 2956 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2957 offs = i * EHCI_ITD_SIZE; 2958 itd = KERNADDR(&dma, offs); 2959 itd->physaddr = DMAADDR(&dma, offs); 2960 itd->dma = dma; 2961 itd->offs = offs; 2962 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2963 } 2964 freeitd = LIST_FIRST(&sc->sc_freeitds); 2965 } 2966 2967 itd = freeitd; 2968 LIST_REMOVE(itd, u.free_list); 2969 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2970 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2971 sizeof(itd->itd.itd_next), 2972 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2973 2974 itd->u.frame_list.next = NULL; 2975 itd->u.frame_list.prev = NULL; 2976 itd->xfer_next = NULL; 2977 itd->slot = 0; 2978 2979 mutex_exit(&sc->sc_lock); 2980 2981 return itd; 2982 } 2983 2984 Static ehci_soft_sitd_t * 2985 ehci_alloc_sitd(ehci_softc_t *sc) 2986 { 2987 struct ehci_soft_sitd *sitd, *freesitd; 2988 usbd_status err; 2989 int i, offs, frindex, previndex; 2990 usb_dma_t dma; 2991 2992 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2993 2994 mutex_enter(&sc->sc_lock); 2995 2996 /* 2997 * Find an sitd that wasn't freed this frame or last frame. This can 2998 * discard sitds that were freed before frindex wrapped around 2999 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3000 * interrupt and fiddling with list when that happens 3001 */ 3002 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3003 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3004 3005 freesitd = NULL; 3006 LIST_FOREACH(sitd, &sc->sc_freesitds, u.free_list) { 3007 if (sitd == NULL) 3008 break; 3009 if (sitd->slot != frindex && sitd->slot != previndex) { 3010 freesitd = sitd; 3011 break; 3012 } 3013 } 3014 3015 if (freesitd == NULL) { 3016 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3017 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3018 EHCI_PAGE_SIZE, &dma); 3019 3020 if (err) { 3021 USBHIST_LOG(ehcidebug, 3022 "alloc returned %d", err, 0, 0, 0); 3023 mutex_exit(&sc->sc_lock); 3024 return NULL; 3025 } 3026 3027 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3028 offs = i * EHCI_SITD_SIZE; 3029 sitd = KERNADDR(&dma, offs); 3030 sitd->physaddr = DMAADDR(&dma, offs); 3031 sitd->dma = dma; 3032 sitd->offs = offs; 3033 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3034 } 3035 freesitd = LIST_FIRST(&sc->sc_freesitds); 3036 } 3037 3038 sitd = freesitd; 3039 LIST_REMOVE(sitd, u.free_list); 3040 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3041 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3042 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3043 BUS_DMASYNC_PREREAD); 3044 3045 sitd->u.frame_list.next = NULL; 3046 sitd->u.frame_list.prev = NULL; 3047 sitd->xfer_next = NULL; 3048 sitd->slot = 0; 3049 3050 mutex_exit(&sc->sc_lock); 3051 3052 return sitd; 3053 } 3054 3055 Static void 3056 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3057 { 3058 3059 KASSERT(mutex_owned(&sc->sc_lock)); 3060 3061 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3062 } 3063 3064 Static void 3065 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3066 { 3067 3068 KASSERT(mutex_owned(&sc->sc_lock)); 3069 3070 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3071 } 3072 3073 /****************/ 3074 3075 /* 3076 * Close a reqular pipe. 3077 * Assumes that there are no pending transactions. 3078 */ 3079 Static void 3080 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3081 { 3082 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3083 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3084 ehci_soft_qh_t *sqh = epipe->sqh; 3085 3086 KASSERT(mutex_owned(&sc->sc_lock)); 3087 3088 ehci_rem_qh(sc, sqh, head); 3089 ehci_free_sqh(sc, epipe->sqh); 3090 } 3091 3092 /* 3093 * Abort a device request. 3094 * If this routine is called at splusb() it guarantees that the request 3095 * will be removed from the hardware scheduling and that the callback 3096 * for it will be called with USBD_CANCELLED status. 3097 * It's impossible to guarantee that the requested transfer will not 3098 * have happened since the hardware runs concurrently. 3099 * If the transaction has already happened we rely on the ordinary 3100 * interrupt processing to process it. 3101 * XXX This is most probably wrong. 3102 * XXXMRG this doesn't make sense anymore. 3103 */ 3104 Static void 3105 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3106 { 3107 #define exfer EXFER(xfer) 3108 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3109 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3110 ehci_soft_qh_t *sqh = epipe->sqh; 3111 ehci_soft_qtd_t *sqtd; 3112 ehci_physaddr_t cur; 3113 uint32_t qhstatus; 3114 int hit; 3115 int wake; 3116 3117 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3118 3119 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3120 3121 KASSERT(mutex_owned(&sc->sc_lock)); 3122 ASSERT_SLEEPABLE(); 3123 3124 if (sc->sc_dying) { 3125 /* If we're dying, just do the software part. */ 3126 xfer->ux_status = status; /* make software ignore it */ 3127 callout_stop(&xfer->ux_callout); 3128 usb_transfer_complete(xfer); 3129 return; 3130 } 3131 3132 /* 3133 * If an abort is already in progress then just wait for it to 3134 * complete and return. 3135 */ 3136 if (xfer->ux_hcflags & UXFER_ABORTING) { 3137 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3138 #ifdef DIAGNOSTIC 3139 if (status == USBD_TIMEOUT) 3140 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3141 #endif 3142 /* Override the status which might be USBD_TIMEOUT. */ 3143 xfer->ux_status = status; 3144 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3145 0, 0, 0, 0); 3146 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3147 while (xfer->ux_hcflags & UXFER_ABORTING) 3148 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3149 return; 3150 } 3151 xfer->ux_hcflags |= UXFER_ABORTING; 3152 3153 /* 3154 * Step 1: Make interrupt routine and hardware ignore xfer. 3155 */ 3156 xfer->ux_status = status; /* make software ignore it */ 3157 callout_stop(&xfer->ux_callout); 3158 3159 usb_syncmem(&sqh->dma, 3160 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3161 sizeof(sqh->qh.qh_qtd.qtd_status), 3162 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3163 qhstatus = sqh->qh.qh_qtd.qtd_status; 3164 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3165 usb_syncmem(&sqh->dma, 3166 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3167 sizeof(sqh->qh.qh_qtd.qtd_status), 3168 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3169 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3170 usb_syncmem(&sqtd->dma, 3171 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3172 sizeof(sqtd->qtd.qtd_status), 3173 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3174 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3175 usb_syncmem(&sqtd->dma, 3176 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3177 sizeof(sqtd->qtd.qtd_status), 3178 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3179 if (sqtd == exfer->ex_sqtdend) 3180 break; 3181 } 3182 3183 /* 3184 * Step 2: Wait until we know hardware has finished any possible 3185 * use of the xfer. Also make sure the soft interrupt routine 3186 * has run. 3187 */ 3188 ehci_sync_hc(sc); 3189 sc->sc_softwake = 1; 3190 usb_schedsoftintr(&sc->sc_bus); 3191 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3192 3193 /* 3194 * Step 3: Remove any vestiges of the xfer from the hardware. 3195 * The complication here is that the hardware may have executed 3196 * beyond the xfer we're trying to abort. So as we're scanning 3197 * the TDs of this xfer we check if the hardware points to 3198 * any of them. 3199 */ 3200 3201 usb_syncmem(&sqh->dma, 3202 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3203 sizeof(sqh->qh.qh_curqtd), 3204 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3205 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3206 hit = 0; 3207 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3208 hit |= cur == sqtd->physaddr; 3209 if (sqtd == exfer->ex_sqtdend) 3210 break; 3211 } 3212 sqtd = sqtd->nextqtd; 3213 /* Zap curqtd register if hardware pointed inside the xfer. */ 3214 if (hit && sqtd != NULL) { 3215 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3216 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3217 usb_syncmem(&sqh->dma, 3218 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3219 sizeof(sqh->qh.qh_curqtd), 3220 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3221 sqh->qh.qh_qtd.qtd_status = qhstatus; 3222 usb_syncmem(&sqh->dma, 3223 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3224 sizeof(sqh->qh.qh_qtd.qtd_status), 3225 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3226 } else { 3227 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3228 } 3229 3230 /* 3231 * Step 4: Execute callback. 3232 */ 3233 #ifdef DIAGNOSTIC 3234 exfer->ex_isdone = 1; 3235 #endif 3236 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3237 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3238 usb_transfer_complete(xfer); 3239 if (wake) { 3240 cv_broadcast(&xfer->ux_hccv); 3241 } 3242 3243 KASSERT(mutex_owned(&sc->sc_lock)); 3244 #undef exfer 3245 } 3246 3247 Static void 3248 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3249 { 3250 ehci_isoc_trans_t trans_status; 3251 struct ehci_pipe *epipe; 3252 struct ehci_xfer *exfer; 3253 ehci_softc_t *sc; 3254 struct ehci_soft_itd *itd; 3255 struct ehci_soft_sitd *sitd; 3256 int i, wake; 3257 3258 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3259 3260 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3261 exfer = EXFER(xfer); 3262 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3263 3264 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3265 3266 KASSERT(mutex_owned(&sc->sc_lock)); 3267 3268 if (sc->sc_dying) { 3269 xfer->ux_status = status; 3270 callout_stop(&xfer->ux_callout); 3271 usb_transfer_complete(xfer); 3272 return; 3273 } 3274 3275 if (xfer->ux_hcflags & UXFER_ABORTING) { 3276 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3277 3278 #ifdef DIAGNOSTIC 3279 if (status == USBD_TIMEOUT) 3280 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3281 #endif 3282 3283 xfer->ux_status = status; 3284 USBHIST_LOG(ehcidebug, 3285 "waiting for abort to finish", 0, 0, 0, 0); 3286 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3287 while (xfer->ux_hcflags & UXFER_ABORTING) 3288 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3289 goto done; 3290 } 3291 xfer->ux_hcflags |= UXFER_ABORTING; 3292 3293 xfer->ux_status = status; 3294 callout_stop(&xfer->ux_callout); 3295 3296 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3297 for (itd = exfer->ex_itdstart; itd != NULL; 3298 itd = itd->xfer_next) { 3299 usb_syncmem(&itd->dma, 3300 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3301 sizeof(itd->itd.itd_ctl), 3302 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3303 3304 for (i = 0; i < 8; i++) { 3305 trans_status = le32toh(itd->itd.itd_ctl[i]); 3306 trans_status &= ~EHCI_ITD_ACTIVE; 3307 itd->itd.itd_ctl[i] = htole32(trans_status); 3308 } 3309 3310 usb_syncmem(&itd->dma, 3311 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3312 sizeof(itd->itd.itd_ctl), 3313 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3314 } 3315 } else { 3316 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3317 sitd = sitd->xfer_next) { 3318 usb_syncmem(&sitd->dma, 3319 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3320 sizeof(sitd->sitd.sitd_buffer), 3321 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3322 3323 trans_status = le32toh(sitd->sitd.sitd_trans); 3324 trans_status &= ~EHCI_SITD_ACTIVE; 3325 sitd->sitd.sitd_trans = htole32(trans_status); 3326 3327 usb_syncmem(&sitd->dma, 3328 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3329 sizeof(sitd->sitd.sitd_buffer), 3330 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3331 } 3332 } 3333 3334 sc->sc_softwake = 1; 3335 usb_schedsoftintr(&sc->sc_bus); 3336 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3337 3338 #ifdef DIAGNOSTIC 3339 exfer->ex_isdone = 1; 3340 #endif 3341 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3342 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3343 usb_transfer_complete(xfer); 3344 if (wake) { 3345 cv_broadcast(&xfer->ux_hccv); 3346 } 3347 3348 done: 3349 KASSERT(mutex_owned(&sc->sc_lock)); 3350 return; 3351 } 3352 3353 Static void 3354 ehci_timeout(void *addr) 3355 { 3356 struct ehci_xfer *exfer = addr; 3357 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->ex_xfer.ux_pipe; 3358 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3359 3360 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3361 3362 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3363 #ifdef EHCI_DEBUG 3364 if (ehcidebug > 1) 3365 usbd_dump_pipe(exfer->ex_xfer.ux_pipe); 3366 #endif 3367 3368 if (sc->sc_dying) { 3369 mutex_enter(&sc->sc_lock); 3370 ehci_abort_xfer(&exfer->ex_xfer, USBD_TIMEOUT); 3371 mutex_exit(&sc->sc_lock); 3372 return; 3373 } 3374 3375 /* Execute the abort in a process context. */ 3376 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, addr, 3377 USB_TASKQ_MPSAFE); 3378 usb_add_task(exfer->ex_xfer.ux_pipe->up_dev, &exfer->ex_aborttask, 3379 USB_TASKQ_HC); 3380 } 3381 3382 Static void 3383 ehci_timeout_task(void *addr) 3384 { 3385 usbd_xfer_handle xfer = addr; 3386 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3387 3388 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3389 3390 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3391 3392 mutex_enter(&sc->sc_lock); 3393 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3394 mutex_exit(&sc->sc_lock); 3395 } 3396 3397 /************************/ 3398 3399 Static usbd_status 3400 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3401 { 3402 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3403 usbd_status err; 3404 3405 /* Insert last in queue. */ 3406 mutex_enter(&sc->sc_lock); 3407 err = usb_insert_transfer(xfer); 3408 mutex_exit(&sc->sc_lock); 3409 if (err) 3410 return err; 3411 3412 /* Pipe isn't running, start first */ 3413 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3414 } 3415 3416 Static usbd_status 3417 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3418 { 3419 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3420 usbd_status err; 3421 3422 if (sc->sc_dying) 3423 return USBD_IOERROR; 3424 3425 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3426 3427 err = ehci_device_request(xfer); 3428 if (err) { 3429 return err; 3430 } 3431 3432 if (sc->sc_bus.ub_usepolling) 3433 ehci_waitintr(sc, xfer); 3434 3435 return USBD_IN_PROGRESS; 3436 } 3437 3438 Static void 3439 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3440 { 3441 struct ehci_xfer *ex = EXFER(xfer); 3442 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3443 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3444 usb_device_request_t *req = &xfer->ux_request; 3445 int len = UGETW(req->wLength); 3446 int rd = req->bmRequestType & UT_READ; 3447 3448 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3449 3450 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3451 3452 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3453 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3454 3455 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3456 ehci_del_intr_list(sc, ex); /* remove from active list */ 3457 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3458 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof(*req), 3459 BUS_DMASYNC_POSTWRITE); 3460 if (len) 3461 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3462 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3463 } 3464 3465 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3466 } 3467 3468 /* Abort a device control request. */ 3469 Static void 3470 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3471 { 3472 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3473 3474 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3475 ehci_abort_xfer(xfer, USBD_CANCELLED); 3476 } 3477 3478 /* Close a device control pipe. */ 3479 Static void 3480 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3481 { 3482 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3483 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3484 3485 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3486 3487 KASSERT(mutex_owned(&sc->sc_lock)); 3488 3489 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3490 3491 ehci_close_pipe(pipe, sc->sc_async_head); 3492 } 3493 3494 Static usbd_status 3495 ehci_device_request(usbd_xfer_handle xfer) 3496 { 3497 #define exfer EXFER(xfer) 3498 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3499 usb_device_request_t *req = &xfer->ux_request; 3500 usbd_device_handle dev = epipe->pipe.up_dev; 3501 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3502 ehci_soft_qtd_t *setup, *stat, *next; 3503 ehci_soft_qh_t *sqh; 3504 int isread; 3505 int len; 3506 usbd_status err; 3507 3508 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3509 3510 isread = req->bmRequestType & UT_READ; 3511 len = UGETW(req->wLength); 3512 3513 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3514 "wValue=0x%04x, wIndex=0x%04x", 3515 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3516 UGETW(req->wIndex)); 3517 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3518 len, dev->ud_addr, 3519 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3520 3521 setup = ehci_alloc_sqtd(sc); 3522 if (setup == NULL) { 3523 err = USBD_NOMEM; 3524 goto bad1; 3525 } 3526 stat = ehci_alloc_sqtd(sc); 3527 if (stat == NULL) { 3528 err = USBD_NOMEM; 3529 goto bad2; 3530 } 3531 3532 mutex_enter(&sc->sc_lock); 3533 3534 sqh = epipe->sqh; 3535 3536 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3537 "address QH %d pipe %d\n", 3538 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3539 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3540 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3541 "MPS QH %d pipe %d\n", 3542 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3543 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3544 3545 /* Set up data transaction */ 3546 if (len != 0) { 3547 ehci_soft_qtd_t *end; 3548 3549 /* Start toggle at 1. */ 3550 epipe->nexttoggle = 1; 3551 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3552 &next, &end); 3553 if (err) 3554 goto bad3; 3555 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3556 end->nextqtd = stat; 3557 end->qtd.qtd_next = end->qtd.qtd_altnext = 3558 htole32(stat->physaddr); 3559 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3560 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3561 } else { 3562 next = stat; 3563 } 3564 3565 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 3566 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3567 3568 /* Clear toggle */ 3569 setup->qtd.qtd_status = htole32( 3570 EHCI_QTD_ACTIVE | 3571 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3572 EHCI_QTD_SET_CERR(3) | 3573 EHCI_QTD_SET_TOGGLE(0) | 3574 EHCI_QTD_SET_BYTES(sizeof(*req)) 3575 ); 3576 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3577 setup->qtd.qtd_buffer_hi[0] = 0; 3578 setup->nextqtd = next; 3579 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3580 setup->xfer = xfer; 3581 setup->len = sizeof(*req); 3582 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3583 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3584 3585 stat->qtd.qtd_status = htole32( 3586 EHCI_QTD_ACTIVE | 3587 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3588 EHCI_QTD_SET_CERR(3) | 3589 EHCI_QTD_SET_TOGGLE(1) | 3590 EHCI_QTD_IOC 3591 ); 3592 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3593 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3594 stat->nextqtd = NULL; 3595 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3596 stat->xfer = xfer; 3597 stat->len = 0; 3598 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3599 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3600 3601 #ifdef EHCI_DEBUG 3602 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3603 ehci_dump_sqh(sqh); 3604 ehci_dump_sqtds(setup); 3605 #endif 3606 3607 exfer->ex_sqtdstart = setup; 3608 exfer->ex_sqtdend = stat; 3609 #ifdef DIAGNOSTIC 3610 if (!exfer->ex_isdone) { 3611 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3612 } 3613 exfer->ex_isdone = 0; 3614 #endif 3615 3616 /* Insert qTD in QH list. */ 3617 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3618 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3619 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3620 ehci_timeout, xfer); 3621 } 3622 ehci_add_intr_list(sc, exfer); 3623 xfer->ux_status = USBD_IN_PROGRESS; 3624 mutex_exit(&sc->sc_lock); 3625 3626 #ifdef EHCI_DEBUG 3627 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3628 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3629 // delay(10000); 3630 ehci_dump_regs(sc); 3631 ehci_dump_sqh(sc->sc_async_head); 3632 ehci_dump_sqh(sqh); 3633 ehci_dump_sqtds(setup); 3634 #endif 3635 3636 return USBD_NORMAL_COMPLETION; 3637 3638 bad3: 3639 mutex_exit(&sc->sc_lock); 3640 ehci_free_sqtd(sc, stat); 3641 bad2: 3642 ehci_free_sqtd(sc, setup); 3643 bad1: 3644 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3645 mutex_enter(&sc->sc_lock); 3646 xfer->ux_status = err; 3647 usb_transfer_complete(xfer); 3648 mutex_exit(&sc->sc_lock); 3649 return err; 3650 #undef exfer 3651 } 3652 3653 /* 3654 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3655 * qTD status, or miss signalling occasionally under heavy load. If the host 3656 * machine is too fast, we we can miss transaction completion - when we scan 3657 * the active list the transaction still seems to be active. This generally 3658 * exhibits itself as a umass stall that never recovers. 3659 * 3660 * We work around this behaviour by setting up this callback after any softintr 3661 * that completes with transactions still pending, giving us another chance to 3662 * check for completion after the writeback has taken place. 3663 */ 3664 Static void 3665 ehci_intrlist_timeout(void *arg) 3666 { 3667 ehci_softc_t *sc = arg; 3668 3669 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3670 3671 usb_schedsoftintr(&sc->sc_bus); 3672 } 3673 3674 /************************/ 3675 3676 Static usbd_status 3677 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3678 { 3679 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3680 usbd_status err; 3681 3682 /* Insert last in queue. */ 3683 mutex_enter(&sc->sc_lock); 3684 err = usb_insert_transfer(xfer); 3685 mutex_exit(&sc->sc_lock); 3686 if (err) 3687 return err; 3688 3689 /* Pipe isn't running, start first */ 3690 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3691 } 3692 3693 Static usbd_status 3694 ehci_device_bulk_start(usbd_xfer_handle xfer) 3695 { 3696 #define exfer EXFER(xfer) 3697 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3698 usbd_device_handle dev = epipe->pipe.up_dev; 3699 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3700 ehci_soft_qtd_t *data, *dataend; 3701 ehci_soft_qh_t *sqh; 3702 usbd_status err; 3703 int len, isread, endpt; 3704 3705 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3706 3707 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3708 xfer, xfer->ux_length, xfer->ux_flags, 0); 3709 3710 if (sc->sc_dying) 3711 return USBD_IOERROR; 3712 3713 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3714 3715 mutex_enter(&sc->sc_lock); 3716 3717 len = xfer->ux_length; 3718 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3719 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3720 sqh = epipe->sqh; 3721 3722 epipe->u.bulk.length = len; 3723 3724 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3725 &dataend); 3726 if (err) { 3727 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3728 xfer->ux_status = err; 3729 usb_transfer_complete(xfer); 3730 mutex_exit(&sc->sc_lock); 3731 return err; 3732 } 3733 3734 #ifdef EHCI_DEBUG 3735 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3736 ehci_dump_sqh(sqh); 3737 ehci_dump_sqtds(data); 3738 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3739 #endif 3740 3741 /* Set up interrupt info. */ 3742 exfer->ex_sqtdstart = data; 3743 exfer->ex_sqtdend = dataend; 3744 #ifdef DIAGNOSTIC 3745 if (!exfer->ex_isdone) { 3746 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3747 } 3748 exfer->ex_isdone = 0; 3749 #endif 3750 3751 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3752 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3753 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3754 ehci_timeout, xfer); 3755 } 3756 ehci_add_intr_list(sc, exfer); 3757 xfer->ux_status = USBD_IN_PROGRESS; 3758 mutex_exit(&sc->sc_lock); 3759 3760 #ifdef EHCI_DEBUG 3761 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3762 // delay(10000); 3763 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3764 ehci_dump_regs(sc); 3765 #if 0 3766 printf("async_head:\n"); 3767 ehci_dump_sqh(sc->sc_async_head); 3768 #endif 3769 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3770 ehci_dump_sqh(sqh); 3771 ehci_dump_sqtds(data); 3772 #endif 3773 3774 if (sc->sc_bus.ub_usepolling) 3775 ehci_waitintr(sc, xfer); 3776 3777 return USBD_IN_PROGRESS; 3778 #undef exfer 3779 } 3780 3781 Static void 3782 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3783 { 3784 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3785 3786 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3787 ehci_abort_xfer(xfer, USBD_CANCELLED); 3788 } 3789 3790 /* 3791 * Close a device bulk pipe. 3792 */ 3793 Static void 3794 ehci_device_bulk_close(usbd_pipe_handle pipe) 3795 { 3796 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3797 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3798 3799 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3800 3801 KASSERT(mutex_owned(&sc->sc_lock)); 3802 3803 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3804 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3805 ehci_close_pipe(pipe, sc->sc_async_head); 3806 } 3807 3808 Static void 3809 ehci_device_bulk_done(usbd_xfer_handle xfer) 3810 { 3811 struct ehci_xfer *ex = EXFER(xfer); 3812 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3813 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3814 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3815 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3816 3817 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3818 3819 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3820 xfer, xfer->ux_actlen, 0, 0); 3821 3822 KASSERT(mutex_owned(&sc->sc_lock)); 3823 3824 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3825 ehci_del_intr_list(sc, ex); /* remove from active list */ 3826 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3827 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3828 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3829 } 3830 3831 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3832 } 3833 3834 /************************/ 3835 3836 Static usbd_status 3837 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3838 { 3839 struct ehci_soft_islot *isp; 3840 int islot, lev; 3841 3842 /* Find a poll rate that is large enough. */ 3843 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3844 if (EHCI_ILEV_IVAL(lev) <= ival) 3845 break; 3846 3847 /* Pick an interrupt slot at the right level. */ 3848 /* XXX could do better than picking at random */ 3849 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3850 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3851 3852 sqh->islot = islot; 3853 isp = &sc->sc_islots[islot]; 3854 mutex_enter(&sc->sc_lock); 3855 ehci_add_qh(sc, sqh, isp->sqh); 3856 mutex_exit(&sc->sc_lock); 3857 3858 return USBD_NORMAL_COMPLETION; 3859 } 3860 3861 Static usbd_status 3862 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3863 { 3864 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3865 usbd_status err; 3866 3867 /* Insert last in queue. */ 3868 mutex_enter(&sc->sc_lock); 3869 err = usb_insert_transfer(xfer); 3870 mutex_exit(&sc->sc_lock); 3871 if (err) 3872 return err; 3873 3874 /* 3875 * Pipe isn't running (otherwise err would be USBD_INPROG), 3876 * so start it first. 3877 */ 3878 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3879 } 3880 3881 Static usbd_status 3882 ehci_device_intr_start(usbd_xfer_handle xfer) 3883 { 3884 #define exfer EXFER(xfer) 3885 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3886 usbd_device_handle dev = xfer->ux_pipe->up_dev; 3887 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3888 ehci_soft_qtd_t *data, *dataend; 3889 ehci_soft_qh_t *sqh; 3890 usbd_status err; 3891 int len, isread, endpt; 3892 3893 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3894 3895 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3896 xfer, xfer->ux_length, xfer->ux_flags, 0); 3897 3898 if (sc->sc_dying) 3899 return USBD_IOERROR; 3900 3901 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3902 3903 mutex_enter(&sc->sc_lock); 3904 3905 len = xfer->ux_length; 3906 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3907 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3908 sqh = epipe->sqh; 3909 3910 epipe->u.intr.length = len; 3911 3912 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3913 &dataend); 3914 if (err) { 3915 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3916 xfer->ux_status = err; 3917 usb_transfer_complete(xfer); 3918 mutex_exit(&sc->sc_lock); 3919 return err; 3920 } 3921 3922 #ifdef EHCI_DEBUG 3923 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3924 ehci_dump_sqh(sqh); 3925 ehci_dump_sqtds(data); 3926 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3927 #endif 3928 3929 /* Set up interrupt info. */ 3930 exfer->ex_sqtdstart = data; 3931 exfer->ex_sqtdend = dataend; 3932 #ifdef DIAGNOSTIC 3933 if (!exfer->ex_isdone) { 3934 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3935 } 3936 exfer->ex_isdone = 0; 3937 #endif 3938 3939 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3940 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3941 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3942 ehci_timeout, xfer); 3943 } 3944 ehci_add_intr_list(sc, exfer); 3945 xfer->ux_status = USBD_IN_PROGRESS; 3946 mutex_exit(&sc->sc_lock); 3947 3948 #ifdef EHCI_DEBUG 3949 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3950 // delay(10000); 3951 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3952 ehci_dump_regs(sc); 3953 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3954 ehci_dump_sqh(sqh); 3955 ehci_dump_sqtds(data); 3956 #endif 3957 3958 if (sc->sc_bus.ub_usepolling) 3959 ehci_waitintr(sc, xfer); 3960 3961 return USBD_IN_PROGRESS; 3962 #undef exfer 3963 } 3964 3965 Static void 3966 ehci_device_intr_abort(usbd_xfer_handle xfer) 3967 { 3968 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3969 3970 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3971 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3972 3973 /* 3974 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3975 * async doorbell. That's dependent on the async list, wheras 3976 * intr xfers are periodic, should not use this? 3977 */ 3978 ehci_abort_xfer(xfer, USBD_CANCELLED); 3979 } 3980 3981 Static void 3982 ehci_device_intr_close(usbd_pipe_handle pipe) 3983 { 3984 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3985 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3986 struct ehci_soft_islot *isp; 3987 3988 KASSERT(mutex_owned(&sc->sc_lock)); 3989 3990 isp = &sc->sc_islots[epipe->sqh->islot]; 3991 ehci_close_pipe(pipe, isp->sqh); 3992 } 3993 3994 Static void 3995 ehci_device_intr_done(usbd_xfer_handle xfer) 3996 { 3997 #define exfer EXFER(xfer) 3998 struct ehci_xfer *ex = EXFER(xfer); 3999 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4000 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 4001 ehci_soft_qtd_t *data, *dataend; 4002 ehci_soft_qh_t *sqh; 4003 usbd_status err; 4004 int len, isread, endpt; 4005 4006 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4007 4008 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4009 xfer, xfer->ux_actlen, 0, 0); 4010 4011 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4012 4013 if (xfer->ux_pipe->up_repeat) { 4014 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 4015 4016 len = epipe->u.intr.length; 4017 xfer->ux_length = len; 4018 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4019 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4020 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4021 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4022 sqh = epipe->sqh; 4023 4024 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4025 &data, &dataend); 4026 if (err) { 4027 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4028 xfer->ux_status = err; 4029 return; 4030 } 4031 4032 /* Set up interrupt info. */ 4033 exfer->ex_sqtdstart = data; 4034 exfer->ex_sqtdend = dataend; 4035 #ifdef DIAGNOSTIC 4036 if (!exfer->ex_isdone) { 4037 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", 4038 exfer, 0, 0, 0); 4039 printf("ehci_device_intr_done: not done, ex=%p\n", 4040 exfer); 4041 } 4042 exfer->ex_isdone = 0; 4043 #endif 4044 4045 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4046 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4047 callout_reset(&xfer->ux_callout, 4048 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4049 } 4050 4051 xfer->ux_status = USBD_IN_PROGRESS; 4052 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4053 ehci_del_intr_list(sc, ex); /* remove from active list */ 4054 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 4055 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4056 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4057 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4058 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4059 } 4060 #undef exfer 4061 } 4062 4063 /************************/ 4064 4065 Static usbd_status 4066 ehci_device_fs_isoc_transfer(usbd_xfer_handle xfer) 4067 { 4068 usbd_status err; 4069 4070 err = usb_insert_transfer(xfer); 4071 if (err && err != USBD_IN_PROGRESS) 4072 return err; 4073 4074 return ehci_device_fs_isoc_start(xfer); 4075 } 4076 4077 Static usbd_status 4078 ehci_device_fs_isoc_start(usbd_xfer_handle xfer) 4079 { 4080 struct ehci_pipe *epipe; 4081 usbd_device_handle dev; 4082 ehci_softc_t *sc; 4083 struct ehci_xfer *exfer; 4084 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4085 usb_dma_t *dma_buf; 4086 int i, j, k, frames; 4087 int offs, total_length; 4088 int frindex; 4089 u_int huba, dir; 4090 4091 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4092 4093 start = NULL; 4094 prev = NULL; 4095 sitd = NULL; 4096 total_length = 0; 4097 exfer = (struct ehci_xfer *) xfer; 4098 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4099 dev = xfer->ux_pipe->up_dev; 4100 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4101 4102 /* 4103 * To allow continuous transfers, above we start all transfers 4104 * immediately. However, we're still going to get usbd_start_next call 4105 * this when another xfer completes. So, check if this is already 4106 * in progress or not 4107 */ 4108 4109 if (exfer->ex_sitdstart != NULL) 4110 return USBD_IN_PROGRESS; 4111 4112 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4113 xfer, xfer->ux_length, xfer->ux_flags, 0); 4114 4115 if (sc->sc_dying) 4116 return USBD_IOERROR; 4117 4118 /* 4119 * To avoid complication, don't allow a request right now that'll span 4120 * the entire frame table. To within 4 frames, to allow some leeway 4121 * on either side of where the hc currently is. 4122 */ 4123 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4124 xfer->ux_nframes >= sc->sc_flsize - 4) { 4125 printf("ehci: isoc descriptor requested that spans the entire" 4126 "frametable, too many frames\n"); 4127 return USBD_INVAL; 4128 } 4129 4130 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4131 4132 #ifdef DIAGNOSTIC 4133 if (!exfer->ex_isdone) 4134 printf("ehci_device_fs_isoc_start: not done, ex = %p\n", exfer); 4135 exfer->ex_isdone = 0; 4136 #endif 4137 4138 /* 4139 * Step 1: Allocate and initialize sitds. 4140 */ 4141 4142 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4143 if (i > 16 || i == 0) { 4144 /* Spec page 271 says intervals > 16 are invalid */ 4145 USBHIST_LOG(ehcidebug, "bInterval %d invalid", 0, 0, 0, 0); 4146 4147 return USBD_INVAL; 4148 } 4149 4150 frames = xfer->ux_nframes; 4151 4152 if (frames == 0) { 4153 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4154 4155 return USBD_INVAL; 4156 } 4157 4158 dma_buf = &xfer->ux_dmabuf; 4159 offs = 0; 4160 4161 for (i = 0; i < frames; i++) { 4162 sitd = ehci_alloc_sitd(sc); 4163 4164 if (prev) 4165 prev->xfer_next = sitd; 4166 else 4167 start = sitd; 4168 4169 #ifdef DIAGNOSTIC 4170 if (xfer->ux_frlengths[i] > 0x3ff) { 4171 printf("ehci: invalid frame length\n"); 4172 xfer->ux_frlengths[i] = 0x3ff; 4173 } 4174 #endif 4175 4176 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4177 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4178 4179 /* Set page0 index and offset. */ 4180 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4181 4182 total_length += xfer->ux_frlengths[i]; 4183 offs += xfer->ux_frlengths[i]; 4184 4185 sitd->sitd.sitd_buffer[1] = 4186 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4187 4188 huba = dev->ud_myhsport->up_parent->ud_addr; 4189 4190 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4191 // Set hub address to 0 if embedded TT is used. 4192 if (huba == sc->sc_addr) 4193 huba = 0; 4194 } 4195 */ 4196 4197 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4198 dir = UE_GET_DIR(k) ? 1 : 0; 4199 sitd->sitd.sitd_endp = 4200 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4201 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4202 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4203 EHCI_SITD_SET_HUBA(huba) | 4204 EHCI_SITD_SET_DIR(dir)); 4205 4206 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4207 4208 /* XXX */ 4209 u_char sa, sb; 4210 u_int temp, tlen; 4211 sa = 0; 4212 4213 if (dir == 0) { /* OUT */ 4214 temp = 0; 4215 tlen = xfer->ux_frlengths[i]; 4216 if (tlen <= 188) { 4217 temp |= 1; /* T-count = 1, TP = ALL */ 4218 tlen = 1; 4219 } else { 4220 tlen += 187; 4221 tlen /= 188; 4222 temp |= tlen; /* T-count = [1..6] */ 4223 temp |= 8; /* TP = Begin */ 4224 } 4225 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4226 4227 tlen += sa; 4228 4229 if (tlen >= 8) { 4230 sb = 0; 4231 } else { 4232 sb = (1 << tlen); 4233 } 4234 4235 sa = (1 << sa); 4236 sa = (sb - sa) & 0x3F; 4237 sb = 0; 4238 } else { 4239 sb = (-(4 << sa)) & 0xFE; 4240 sa = (1 << sa) & 0x3F; 4241 sa = 0x01; 4242 sb = 0xfc; 4243 } 4244 4245 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4246 EHCI_SITD_SET_CMASK(sb)); 4247 4248 prev = sitd; 4249 } /* End of frame */ 4250 4251 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4252 4253 stop = sitd; 4254 stop->xfer_next = NULL; 4255 4256 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4257 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4258 4259 /* 4260 * Part 2: Transfer descriptors have now been set up, now they must 4261 * be scheduled into the periodic frame list. Erk. Not wanting to 4262 * complicate matters, transfer is denied if the transfer spans 4263 * more than the period frame list. 4264 */ 4265 4266 mutex_enter(&sc->sc_lock); 4267 4268 /* Start inserting frames */ 4269 if (epipe->u.isoc.cur_xfers > 0) { 4270 frindex = epipe->u.isoc.next_frame; 4271 } else { 4272 frindex = EOREAD4(sc, EHCI_FRINDEX); 4273 frindex = frindex >> 3; /* Erase microframe index */ 4274 frindex += 2; 4275 } 4276 4277 if (frindex >= sc->sc_flsize) 4278 frindex &= (sc->sc_flsize - 1); 4279 4280 /* Whats the frame interval? */ 4281 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4282 4283 sitd = start; 4284 for (j = 0; j < frames; j++) { 4285 if (sitd == NULL) 4286 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4287 4288 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4289 if (sitd->sitd.sitd_next == 0) 4290 /* FIXME: frindex table gets initialized to NULL 4291 * or EHCI_NULL? */ 4292 sitd->sitd.sitd_next = EHCI_NULL; 4293 4294 usb_syncmem(&sitd->dma, 4295 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4296 sizeof(ehci_sitd_t), 4297 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4298 4299 sc->sc_flist[frindex] = 4300 htole32(EHCI_LINK_SITD | sitd->physaddr); 4301 4302 usb_syncmem(&sc->sc_fldma, 4303 sizeof(ehci_link_t) * frindex, 4304 sizeof(ehci_link_t), 4305 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4306 4307 sitd->u.frame_list.next = sc->sc_softsitds[frindex]; 4308 sc->sc_softsitds[frindex] = sitd; 4309 if (sitd->u.frame_list.next != NULL) 4310 sitd->u.frame_list.next->u.frame_list.prev = sitd; 4311 sitd->slot = frindex; 4312 sitd->u.frame_list.prev = NULL; 4313 4314 frindex += i; 4315 if (frindex >= sc->sc_flsize) 4316 frindex -= sc->sc_flsize; 4317 4318 sitd = sitd->xfer_next; 4319 } 4320 4321 epipe->u.isoc.cur_xfers++; 4322 epipe->u.isoc.next_frame = frindex; 4323 4324 exfer->ex_sitdstart = start; 4325 exfer->ex_sitdend = stop; 4326 4327 ehci_add_intr_list(sc, exfer); 4328 xfer->ux_status = USBD_IN_PROGRESS; 4329 xfer->ux_done = 0; 4330 4331 mutex_exit(&sc->sc_lock); 4332 4333 if (sc->sc_bus.ub_usepolling) { 4334 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4335 ehci_waitintr(sc, xfer); 4336 } 4337 4338 return USBD_IN_PROGRESS; 4339 } 4340 4341 Static void 4342 ehci_device_fs_isoc_abort(usbd_xfer_handle xfer) 4343 { 4344 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4345 4346 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4347 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4348 } 4349 4350 Static void 4351 ehci_device_fs_isoc_close(usbd_pipe_handle pipe) 4352 { 4353 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4354 4355 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4356 } 4357 4358 Static void 4359 ehci_device_fs_isoc_done(usbd_xfer_handle xfer) 4360 { 4361 struct ehci_xfer *exfer; 4362 ehci_softc_t *sc; 4363 struct ehci_pipe *epipe; 4364 4365 exfer = EXFER(xfer); 4366 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4367 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4368 4369 KASSERT(mutex_owned(&sc->sc_lock)); 4370 4371 epipe->u.isoc.cur_xfers--; 4372 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4373 ehci_del_intr_list(sc, exfer); 4374 ehci_rem_free_sitd_chain(sc, exfer); 4375 } 4376 4377 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4378 BUS_DMASYNC_POSTREAD); 4379 } 4380 Static usbd_status 4381 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 4382 { 4383 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4384 usbd_status err; 4385 4386 mutex_enter(&sc->sc_lock); 4387 err = usb_insert_transfer(xfer); 4388 mutex_exit(&sc->sc_lock); 4389 if (err && err != USBD_IN_PROGRESS) 4390 return err; 4391 4392 return ehci_device_isoc_start(xfer); 4393 } 4394 4395 Static usbd_status 4396 ehci_device_isoc_start(usbd_xfer_handle xfer) 4397 { 4398 struct ehci_pipe *epipe; 4399 ehci_softc_t *sc; 4400 struct ehci_xfer *exfer; 4401 ehci_soft_itd_t *itd, *prev, *start, *stop; 4402 usb_dma_t *dma_buf; 4403 int i, j, k, frames, uframes, ufrperframe; 4404 int trans_count, offs, total_length; 4405 int frindex; 4406 4407 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4408 4409 start = NULL; 4410 prev = NULL; 4411 itd = NULL; 4412 trans_count = 0; 4413 total_length = 0; 4414 exfer = (struct ehci_xfer *) xfer; 4415 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4416 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4417 4418 /* 4419 * To allow continuous transfers, above we start all transfers 4420 * immediately. However, we're still going to get usbd_start_next call 4421 * this when another xfer completes. So, check if this is already 4422 * in progress or not 4423 */ 4424 4425 if (exfer->ex_itdstart != NULL) 4426 return USBD_IN_PROGRESS; 4427 4428 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4429 xfer, xfer->ux_length, xfer->ux_flags, 0); 4430 4431 if (sc->sc_dying) 4432 return USBD_IOERROR; 4433 4434 /* 4435 * To avoid complication, don't allow a request right now that'll span 4436 * the entire frame table. To within 4 frames, to allow some leeway 4437 * on either side of where the hc currently is. 4438 */ 4439 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4440 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4441 USBHIST_LOG(ehcidebug, 4442 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4443 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4444 return USBD_INVAL; 4445 } 4446 4447 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4448 4449 #ifdef DIAGNOSTIC 4450 if (!exfer->ex_isdone) { 4451 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", exfer, 4452 0, 0, 0); 4453 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 4454 } 4455 exfer->ex_isdone = 0; 4456 #endif 4457 4458 /* 4459 * Step 1: Allocate and initialize itds, how many do we need? 4460 * One per transfer if interval >= 8 microframes, fewer if we use 4461 * multiple microframes per frame. 4462 */ 4463 4464 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4465 if (i > 16 || i == 0) { 4466 /* Spec page 271 says intervals > 16 are invalid */ 4467 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4468 return USBD_INVAL; 4469 } 4470 4471 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4472 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4473 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4474 4475 if (frames == 0) { 4476 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4477 return USBD_INVAL; 4478 } 4479 4480 dma_buf = &xfer->ux_dmabuf; 4481 offs = 0; 4482 4483 for (i = 0; i < frames; i++) { 4484 int froffs = offs; 4485 itd = ehci_alloc_itd(sc); 4486 4487 if (prev != NULL) { 4488 prev->itd.itd_next = 4489 htole32(itd->physaddr | EHCI_LINK_ITD); 4490 usb_syncmem(&itd->dma, 4491 itd->offs + offsetof(ehci_itd_t, itd_next), 4492 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4493 4494 prev->xfer_next = itd; 4495 } else { 4496 start = itd; 4497 } 4498 4499 /* 4500 * Step 1.5, initialize uframes 4501 */ 4502 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4503 /* Calculate which page in the list this starts in */ 4504 int addr = DMAADDR(dma_buf, froffs); 4505 addr = EHCI_PAGE_OFFSET(addr); 4506 addr += (offs - froffs); 4507 addr = EHCI_PAGE(addr); 4508 addr /= EHCI_PAGE_SIZE; 4509 4510 /* 4511 * This gets the initial offset into the first page, 4512 * looks how far further along the current uframe 4513 * offset is. Works out how many pages that is. 4514 */ 4515 4516 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4517 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4518 EHCI_ITD_SET_PG(addr) | 4519 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4520 4521 total_length += xfer->ux_frlengths[trans_count]; 4522 offs += xfer->ux_frlengths[trans_count]; 4523 trans_count++; 4524 4525 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4526 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4527 break; 4528 } 4529 } 4530 4531 /* 4532 * Step 1.75, set buffer pointers. To simplify matters, all 4533 * pointers are filled out for the next 7 hardware pages in 4534 * the dma block, so no need to worry what pages to cover 4535 * and what to not. 4536 */ 4537 4538 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4539 /* 4540 * Don't try to lookup a page that's past the end 4541 * of buffer 4542 */ 4543 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4544 if (page_offs >= dma_buf->udma_block->size) 4545 break; 4546 4547 unsigned long long page = DMAADDR(dma_buf, page_offs); 4548 page = EHCI_PAGE(page); 4549 itd->itd.itd_bufr[j] = 4550 htole32(EHCI_ITD_SET_BPTR(page)); 4551 itd->itd.itd_bufr_hi[j] = 4552 htole32(page >> 32); 4553 } 4554 4555 /* 4556 * Other special values 4557 */ 4558 4559 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4560 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4561 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4562 4563 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4564 ? 1 : 0; 4565 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4566 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4567 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4568 4569 /* FIXME: handle invalid trans */ 4570 itd->itd.itd_bufr[2] |= 4571 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4572 4573 usb_syncmem(&itd->dma, 4574 itd->offs + offsetof(ehci_itd_t, itd_next), 4575 sizeof(ehci_itd_t), 4576 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4577 4578 prev = itd; 4579 } /* End of frame */ 4580 4581 stop = itd; 4582 stop->xfer_next = NULL; 4583 4584 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4585 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4586 4587 /* 4588 * Part 2: Transfer descriptors have now been set up, now they must 4589 * be scheduled into the period frame list. Erk. Not wanting to 4590 * complicate matters, transfer is denied if the transfer spans 4591 * more than the period frame list. 4592 */ 4593 4594 mutex_enter(&sc->sc_lock); 4595 4596 /* Start inserting frames */ 4597 if (epipe->u.isoc.cur_xfers > 0) { 4598 frindex = epipe->u.isoc.next_frame; 4599 } else { 4600 frindex = EOREAD4(sc, EHCI_FRINDEX); 4601 frindex = frindex >> 3; /* Erase microframe index */ 4602 frindex += 2; 4603 } 4604 4605 if (frindex >= sc->sc_flsize) 4606 frindex &= (sc->sc_flsize - 1); 4607 4608 /* What's the frame interval? */ 4609 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4610 if (i / USB_UFRAMES_PER_FRAME == 0) 4611 i = 1; 4612 else 4613 i /= USB_UFRAMES_PER_FRAME; 4614 4615 itd = start; 4616 for (j = 0; j < frames; j++) { 4617 if (itd == NULL) 4618 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4619 4620 itd->itd.itd_next = sc->sc_flist[frindex]; 4621 if (itd->itd.itd_next == 0) 4622 /* FIXME: frindex table gets initialized to NULL 4623 * or EHCI_NULL? */ 4624 itd->itd.itd_next = EHCI_NULL; 4625 4626 usb_syncmem(&itd->dma, 4627 itd->offs + offsetof(ehci_itd_t, itd_next), 4628 sizeof(itd->itd.itd_next), 4629 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4630 4631 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4632 4633 usb_syncmem(&sc->sc_fldma, 4634 sizeof(ehci_link_t) * frindex, 4635 sizeof(ehci_link_t), 4636 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4637 4638 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4639 sc->sc_softitds[frindex] = itd; 4640 if (itd->u.frame_list.next != NULL) 4641 itd->u.frame_list.next->u.frame_list.prev = itd; 4642 itd->slot = frindex; 4643 itd->u.frame_list.prev = NULL; 4644 4645 frindex += i; 4646 if (frindex >= sc->sc_flsize) 4647 frindex -= sc->sc_flsize; 4648 4649 itd = itd->xfer_next; 4650 } 4651 4652 epipe->u.isoc.cur_xfers++; 4653 epipe->u.isoc.next_frame = frindex; 4654 4655 exfer->ex_itdstart = start; 4656 exfer->ex_itdend = stop; 4657 4658 ehci_add_intr_list(sc, exfer); 4659 xfer->ux_status = USBD_IN_PROGRESS; 4660 xfer->ux_done = 0; 4661 mutex_exit(&sc->sc_lock); 4662 4663 if (sc->sc_bus.ub_usepolling) { 4664 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4665 ehci_waitintr(sc, xfer); 4666 } 4667 4668 return USBD_IN_PROGRESS; 4669 } 4670 4671 Static void 4672 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4673 { 4674 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4675 4676 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4677 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4678 } 4679 4680 Static void 4681 ehci_device_isoc_close(usbd_pipe_handle pipe) 4682 { 4683 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4684 4685 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4686 } 4687 4688 Static void 4689 ehci_device_isoc_done(usbd_xfer_handle xfer) 4690 { 4691 struct ehci_xfer *exfer; 4692 ehci_softc_t *sc; 4693 struct ehci_pipe *epipe; 4694 4695 exfer = EXFER(xfer); 4696 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4697 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4698 4699 KASSERT(mutex_owned(&sc->sc_lock)); 4700 4701 epipe->u.isoc.cur_xfers--; 4702 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4703 ehci_del_intr_list(sc, exfer); 4704 ehci_rem_free_itd_chain(sc, exfer); 4705 } 4706 4707 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4708 BUS_DMASYNC_POSTREAD); 4709 4710 } 4711
Indexes created Wed Oct 01 19:09:53 GMT 2025