ehci.c revision 1.234.2.33
1 /* $NetBSD: ehci.c,v 1.234.2.33 2015/03/01 08:18:16 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.33 2015/03/01 08:18:16 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 85 #include <dev/usb/ehcireg.h> 86 #include <dev/usb/ehcivar.h> 87 #include <dev/usb/usbroothub.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 /* ehci_soft_sitd_t *sitd; */ 135 } tail; 136 union { 137 /* Control pipe */ 138 struct { 139 usb_dma_t reqdma; 140 } ctl; 141 /* Interrupt pipe */ 142 struct { 143 u_int length; 144 } intr; 145 /* Bulk pipe */ 146 struct { 147 u_int length; 148 } bulk; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 } u; 155 }; 156 157 Static usbd_status ehci_open(usbd_pipe_handle); 158 Static void ehci_poll(struct usbd_bus *); 159 Static void ehci_softintr(void *); 160 Static int ehci_intr1(ehci_softc_t *); 161 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 162 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 166 Static void ehci_idone(struct ehci_xfer *); 167 Static void ehci_timeout(void *); 168 Static void ehci_timeout_task(void *); 169 Static void ehci_intrlist_timeout(void *); 170 Static void ehci_doorbell(void *); 171 Static void ehci_pcd(void *); 172 173 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 174 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 Static int ehci_roothub_ctrl(struct usbd_bus *, 177 usb_device_request_t *, void *, int); 178 179 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 180 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 181 Static void ehci_root_intr_abort(usbd_xfer_handle); 182 Static void ehci_root_intr_close(usbd_pipe_handle); 183 Static void ehci_root_intr_done(usbd_xfer_handle); 184 185 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 186 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 187 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 188 Static void ehci_device_ctrl_close(usbd_pipe_handle); 189 Static void ehci_device_ctrl_done(usbd_xfer_handle); 190 191 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 192 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 193 Static void ehci_device_bulk_abort(usbd_xfer_handle); 194 Static void ehci_device_bulk_close(usbd_pipe_handle); 195 Static void ehci_device_bulk_done(usbd_xfer_handle); 196 197 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 198 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 199 Static void ehci_device_intr_abort(usbd_xfer_handle); 200 Static void ehci_device_intr_close(usbd_pipe_handle); 201 Static void ehci_device_intr_done(usbd_xfer_handle); 202 203 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 204 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 205 Static void ehci_device_isoc_abort(usbd_xfer_handle); 206 Static void ehci_device_isoc_close(usbd_pipe_handle); 207 Static void ehci_device_isoc_done(usbd_xfer_handle); 208 209 Static usbd_status ehci_device_fs_isoc_transfer(usbd_xfer_handle); 210 Static usbd_status ehci_device_fs_isoc_start(usbd_xfer_handle); 211 Static void ehci_device_fs_isoc_abort(usbd_xfer_handle); 212 Static void ehci_device_fs_isoc_close(usbd_pipe_handle); 213 Static void ehci_device_fs_isoc_done(usbd_xfer_handle); 214 215 Static void ehci_device_clear_toggle(usbd_pipe_handle); 216 Static void ehci_noop(usbd_pipe_handle); 217 218 Static void ehci_disown(ehci_softc_t *, int, int); 219 220 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 221 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 222 223 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 224 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 225 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 226 ehci_softc_t *, int, int, usbd_xfer_handle, 227 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 228 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 229 ehci_soft_qtd_t *); 230 231 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 232 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *); 233 Static void ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *); 234 Static void ehci_free_sitd(ehci_softc_t *, ehci_soft_sitd_t *); 235 Static void ehci_rem_free_itd_chain(ehci_softc_t *, 236 struct ehci_xfer *); 237 Static void ehci_rem_free_sitd_chain(ehci_softc_t *, 238 struct ehci_xfer *); 239 Static void ehci_abort_isoc_xfer(usbd_xfer_handle, 240 usbd_status); 241 242 Static usbd_status ehci_device_request(usbd_xfer_handle); 243 244 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 245 int); 246 247 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 248 ehci_soft_qh_t *); 249 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 250 ehci_soft_qh_t *); 251 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 252 Static void ehci_sync_hc(ehci_softc_t *); 253 254 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 255 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 256 257 #ifdef EHCI_DEBUG 258 Static ehci_softc_t *theehci; 259 void ehci_dump(void); 260 #endif 261 262 #ifdef EHCI_DEBUG 263 Static void ehci_dump_regs(ehci_softc_t *); 264 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 265 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 266 Static void ehci_dump_qtd(ehci_qtd_t *); 267 Static void ehci_dump_sqh(ehci_soft_qh_t *); 268 Static void ehci_dump_sitd(struct ehci_soft_itd *); 269 Static void ehci_dump_itd(struct ehci_soft_itd *); 270 Static void ehci_dump_exfer(struct ehci_xfer *); 271 #endif 272 273 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 274 275 #define ehci_add_intr_list(sc, ex) \ 276 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 277 #define ehci_del_intr_list(sc, ex) \ 278 do { \ 279 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 280 (ex)->ex_next.tqe_prev = NULL; \ 281 } while (0) 282 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 283 284 Static const struct usbd_bus_methods ehci_bus_methods = { 285 .ubm_open = ehci_open, 286 .ubm_softint = ehci_softintr, 287 .ubm_dopoll = ehci_poll, 288 .ubm_allocx = ehci_allocx, 289 .ubm_freex = ehci_freex, 290 .ubm_getlock = ehci_get_lock, 291 .ubm_rhctrl = ehci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 295 .upm_transfer = ehci_root_intr_transfer, 296 .upm_start = ehci_root_intr_start, 297 .upm_abort = ehci_root_intr_abort, 298 .upm_close = ehci_root_intr_close, 299 .upm_cleartoggle = ehci_noop, 300 .upm_done = ehci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 304 .upm_transfer = ehci_device_ctrl_transfer, 305 .upm_start = ehci_device_ctrl_start, 306 .upm_abort = ehci_device_ctrl_abort, 307 .upm_close = ehci_device_ctrl_close, 308 .upm_cleartoggle = ehci_noop, 309 .upm_done = ehci_device_ctrl_done, 310 }; 311 312 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 313 .upm_transfer = ehci_device_intr_transfer, 314 .upm_start = ehci_device_intr_start, 315 .upm_abort = ehci_device_intr_abort, 316 .upm_close = ehci_device_intr_close, 317 .upm_cleartoggle = ehci_device_clear_toggle, 318 .upm_done = ehci_device_intr_done, 319 }; 320 321 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 322 .upm_transfer = ehci_device_bulk_transfer, 323 .upm_start = ehci_device_bulk_start, 324 .upm_abort = ehci_device_bulk_abort, 325 .upm_close = ehci_device_bulk_close, 326 .upm_cleartoggle = ehci_device_clear_toggle, 327 .upm_done = ehci_device_bulk_done, 328 }; 329 330 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 331 .upm_transfer = ehci_device_isoc_transfer, 332 .upm_start = ehci_device_isoc_start, 333 .upm_abort = ehci_device_isoc_abort, 334 .upm_close = ehci_device_isoc_close, 335 .upm_cleartoggle = ehci_noop, 336 .upm_done = ehci_device_isoc_done, 337 }; 338 339 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 340 .upm_transfer = ehci_device_fs_isoc_transfer, 341 .upm_start = ehci_device_fs_isoc_start, 342 .upm_abort = ehci_device_fs_isoc_abort, 343 .upm_close = ehci_device_fs_isoc_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_fs_isoc_done, 346 }; 347 348 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 349 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 350 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 351 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 352 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 353 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 354 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 355 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 356 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 357 }; 358 359 int 360 ehci_init(ehci_softc_t *sc) 361 { 362 uint32_t vers, sparams, cparams, hcr; 363 u_int i; 364 usbd_status err; 365 ehci_soft_qh_t *sqh; 366 u_int ncomp; 367 368 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 369 #ifdef EHCI_DEBUG 370 theehci = sc; 371 #endif 372 373 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 374 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 375 cv_init(&sc->sc_softwake_cv, "ehciab"); 376 cv_init(&sc->sc_doorbell, "ehcidi"); 377 378 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 379 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 380 381 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 382 ehci_doorbell, sc); 383 KASSERT(sc->sc_doorbell_si != NULL); 384 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 385 ehci_pcd, sc); 386 KASSERT(sc->sc_pcd_si != NULL); 387 388 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 389 390 vers = EREAD2(sc, EHCI_HCIVERSION); 391 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 392 vers >> 8, vers & 0xff); 393 394 sparams = EREAD4(sc, EHCI_HCSPARAMS); 395 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 396 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 397 ncomp = EHCI_HCS_N_CC(sparams); 398 if (ncomp != sc->sc_ncomp) { 399 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 400 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 401 #if NOHCI == 0 || NUHCI == 0 402 aprint_error("%s: ohci or uhci probably not configured\n", 403 device_xname(sc->sc_dev)); 404 #endif 405 if (ncomp < sc->sc_ncomp) 406 sc->sc_ncomp = ncomp; 407 } 408 if (sc->sc_ncomp > 0) { 409 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 410 aprint_normal("%s: companion controller%s, %d port%s each:", 411 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 412 EHCI_HCS_N_PCC(sparams), 413 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 414 for (i = 0; i < sc->sc_ncomp; i++) 415 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 416 aprint_normal("\n"); 417 } 418 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 419 cparams = EREAD4(sc, EHCI_HCCPARAMS); 420 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 421 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 422 423 if (EHCI_HCC_64BIT(cparams)) { 424 /* MUST clear segment register if 64 bit capable. */ 425 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 426 } 427 428 sc->sc_bus.ub_revision = USBREV_2_0; 429 sc->sc_bus.ub_usedma = true; 430 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 431 432 /* Reset the controller */ 433 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 434 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 435 usb_delay_ms(&sc->sc_bus, 1); 436 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 437 for (i = 0; i < 100; i++) { 438 usb_delay_ms(&sc->sc_bus, 1); 439 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 440 if (!hcr) 441 break; 442 } 443 if (hcr) { 444 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 445 return EIO; 446 } 447 if (sc->sc_vendor_init) 448 sc->sc_vendor_init(sc); 449 450 /* 451 * If we are doing embedded transaction translation function, force 452 * the controller to host mode. 453 */ 454 if (sc->sc_flags & EHCIF_ETTF) { 455 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 456 usbmode &= ~EHCI_USBMODE_CM; 457 usbmode |= EHCI_USBMODE_CM_HOST; 458 EWRITE4(sc, EHCI_USBMODE, usbmode); 459 } 460 461 /* XXX need proper intr scheduling */ 462 sc->sc_rand = 96; 463 464 /* frame list size at default, read back what we got and use that */ 465 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 466 case 0: sc->sc_flsize = 1024; break; 467 case 1: sc->sc_flsize = 512; break; 468 case 2: sc->sc_flsize = 256; break; 469 case 3: return EIO; 470 } 471 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 472 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 473 if (err) 474 return err; 475 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 476 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 477 478 for (i = 0; i < sc->sc_flsize; i++) { 479 sc->sc_flist[i] = EHCI_NULL; 480 } 481 482 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 483 484 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 485 KM_SLEEP); 486 if (sc->sc_softitds == NULL) 487 return ENOMEM; 488 LIST_INIT(&sc->sc_freeitds); 489 LIST_INIT(&sc->sc_freesitds); 490 TAILQ_INIT(&sc->sc_intrhead); 491 492 /* Set up the bus struct. */ 493 sc->sc_bus.ub_methods = &ehci_bus_methods; 494 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 495 496 sc->sc_eintrs = EHCI_NORMAL_INTRS; 497 498 /* 499 * Allocate the interrupt dummy QHs. These are arranged to give poll 500 * intervals that are powers of 2 times 1ms. 501 */ 502 for (i = 0; i < EHCI_INTRQHS; i++) { 503 sqh = ehci_alloc_sqh(sc); 504 if (sqh == NULL) { 505 err = ENOMEM; 506 goto bad1; 507 } 508 sc->sc_islots[i].sqh = sqh; 509 } 510 for (i = 0; i < EHCI_INTRQHS; i++) { 511 sqh = sc->sc_islots[i].sqh; 512 if (i == 0) { 513 /* The last (1ms) QH terminates. */ 514 sqh->qh.qh_link = EHCI_NULL; 515 sqh->next = NULL; 516 } else { 517 /* Otherwise the next QH has half the poll interval */ 518 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 519 sqh->qh.qh_link = htole32(sqh->next->physaddr | 520 EHCI_LINK_QH); 521 } 522 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 523 sqh->qh.qh_curqtd = EHCI_NULL; 524 sqh->next = NULL; 525 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 526 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 527 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 528 sqh->sqtd = NULL; 529 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 531 } 532 /* Point the frame list at the last level (128ms). */ 533 for (i = 0; i < sc->sc_flsize; i++) { 534 int j; 535 536 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 537 revbits[i & (EHCI_MAX_POLLRATE-1)]; 538 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 539 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 540 i)].sqh->physaddr); 541 } 542 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 543 BUS_DMASYNC_PREWRITE); 544 545 /* Allocate dummy QH that starts the async list. */ 546 sqh = ehci_alloc_sqh(sc); 547 if (sqh == NULL) { 548 err = ENOMEM; 549 goto bad1; 550 } 551 /* Fill the QH */ 552 sqh->qh.qh_endp = 553 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 554 sqh->qh.qh_link = 555 htole32(sqh->physaddr | EHCI_LINK_QH); 556 sqh->qh.qh_curqtd = EHCI_NULL; 557 sqh->next = NULL; 558 /* Fill the overlay qTD */ 559 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 560 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 561 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 562 sqh->sqtd = NULL; 563 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 564 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 565 #ifdef EHCI_DEBUG 566 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 567 ehci_dump_sqh(sqh); 568 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 569 #endif 570 571 /* Point to async list */ 572 sc->sc_async_head = sqh; 573 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 574 575 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 576 577 /* Turn on controller */ 578 EOWRITE4(sc, EHCI_USBCMD, 579 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 580 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 581 EHCI_CMD_ASE | 582 EHCI_CMD_PSE | 583 EHCI_CMD_RS); 584 585 /* Take over port ownership */ 586 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 587 588 for (i = 0; i < 100; i++) { 589 usb_delay_ms(&sc->sc_bus, 1); 590 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 591 if (!hcr) 592 break; 593 } 594 if (hcr) { 595 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 596 return EIO; 597 } 598 599 /* Enable interrupts */ 600 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 601 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 602 603 return 0; 604 605 #if 0 606 bad2: 607 ehci_free_sqh(sc, sc->sc_async_head); 608 #endif 609 bad1: 610 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 611 return err; 612 } 613 614 int 615 ehci_intr(void *v) 616 { 617 ehci_softc_t *sc = v; 618 int ret = 0; 619 620 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 621 622 if (sc == NULL) 623 return 0; 624 625 mutex_spin_enter(&sc->sc_intr_lock); 626 627 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 628 goto done; 629 630 /* If we get an interrupt while polling, then just ignore it. */ 631 if (sc->sc_bus.ub_usepolling) { 632 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 633 634 if (intrs) 635 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 636 USBHIST_LOGN(ehcidebug, 16, 637 "ignored interrupt while polling", 0, 0, 0, 0); 638 goto done; 639 } 640 641 ret = ehci_intr1(sc); 642 643 done: 644 mutex_spin_exit(&sc->sc_intr_lock); 645 return ret; 646 } 647 648 Static int 649 ehci_intr1(ehci_softc_t *sc) 650 { 651 uint32_t intrs, eintrs; 652 653 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 654 655 /* In case the interrupt occurs before initialization has completed. */ 656 if (sc == NULL) { 657 #ifdef DIAGNOSTIC 658 printf("ehci_intr1: sc == NULL\n"); 659 #endif 660 return 0; 661 } 662 663 KASSERT(mutex_owned(&sc->sc_intr_lock)); 664 665 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 666 if (!intrs) 667 return 0; 668 669 eintrs = intrs & sc->sc_eintrs; 670 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 671 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 672 if (!eintrs) 673 return 0; 674 675 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 676 if (eintrs & EHCI_STS_IAA) { 677 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 678 kpreempt_disable(); 679 KASSERT(sc->sc_doorbell_si != NULL); 680 softint_schedule(sc->sc_doorbell_si); 681 kpreempt_enable(); 682 eintrs &= ~EHCI_STS_IAA; 683 } 684 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 685 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 686 eintrs & EHCI_STS_INT ? 1 : 0, 687 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 688 usb_schedsoftintr(&sc->sc_bus); 689 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 690 } 691 if (eintrs & EHCI_STS_HSE) { 692 printf("%s: unrecoverable error, controller halted\n", 693 device_xname(sc->sc_dev)); 694 /* XXX what else */ 695 } 696 if (eintrs & EHCI_STS_PCD) { 697 kpreempt_disable(); 698 KASSERT(sc->sc_pcd_si != NULL); 699 softint_schedule(sc->sc_pcd_si); 700 kpreempt_enable(); 701 eintrs &= ~EHCI_STS_PCD; 702 } 703 704 if (eintrs != 0) { 705 /* Block unprocessed interrupts. */ 706 sc->sc_eintrs &= ~eintrs; 707 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 708 printf("%s: blocking intrs 0x%x\n", 709 device_xname(sc->sc_dev), eintrs); 710 } 711 712 return 1; 713 } 714 715 Static void 716 ehci_doorbell(void *addr) 717 { 718 ehci_softc_t *sc = addr; 719 720 mutex_enter(&sc->sc_lock); 721 cv_broadcast(&sc->sc_doorbell); 722 mutex_exit(&sc->sc_lock); 723 } 724 725 Static void 726 ehci_pcd(void *addr) 727 { 728 ehci_softc_t *sc = addr; 729 usbd_xfer_handle xfer; 730 u_char *p; 731 int i, m; 732 733 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 734 735 mutex_enter(&sc->sc_lock); 736 xfer = sc->sc_intrxfer; 737 738 if (xfer == NULL) { 739 /* Just ignore the change. */ 740 goto done; 741 } 742 743 p = xfer->ux_buf; 744 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 745 memset(p, 0, xfer->ux_length); 746 for (i = 1; i <= m; i++) { 747 /* Pick out CHANGE bits from the status reg. */ 748 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 749 p[i/8] |= 1 << (i%8); 750 if (i % 8 == 7) 751 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 752 p[i/8], 0, 0); 753 } 754 xfer->ux_actlen = xfer->ux_length; 755 xfer->ux_status = USBD_NORMAL_COMPLETION; 756 757 usb_transfer_complete(xfer); 758 759 done: 760 mutex_exit(&sc->sc_lock); 761 } 762 763 Static void 764 ehci_softintr(void *v) 765 { 766 struct usbd_bus *bus = v; 767 ehci_softc_t *sc = bus->ub_hcpriv; 768 struct ehci_xfer *ex, *nextex; 769 770 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 771 772 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 773 774 /* 775 * The only explanation I can think of for why EHCI is as brain dead 776 * as UHCI interrupt-wise is that Intel was involved in both. 777 * An interrupt just tells us that something is done, we have no 778 * clue what, so we need to scan through all active transfers. :-( 779 */ 780 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 781 nextex = TAILQ_NEXT(ex, ex_next); 782 ehci_check_intr(sc, ex); 783 } 784 785 /* Schedule a callout to catch any dropped transactions. */ 786 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 787 !TAILQ_EMPTY(&sc->sc_intrhead)) 788 callout_reset(&sc->sc_tmo_intrlist, 789 hz, ehci_intrlist_timeout, sc); 790 791 if (sc->sc_softwake) { 792 sc->sc_softwake = 0; 793 cv_broadcast(&sc->sc_softwake_cv); 794 } 795 } 796 797 /* Check for an interrupt. */ 798 Static void 799 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 800 { 801 usbd_device_handle dev = ex->ex_xfer.ux_pipe->up_dev; 802 int attr; 803 804 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 805 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 806 807 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 808 809 attr = ex->ex_xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 810 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 811 if (dev->ud_speed == USB_SPEED_HIGH) 812 ehci_check_itd_intr(sc, ex); 813 else 814 ehci_check_sitd_intr(sc, ex); 815 } else 816 ehci_check_qh_intr(sc, ex); 817 818 return; 819 } 820 821 Static void 822 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 823 { 824 ehci_soft_qtd_t *sqtd, *lsqtd; 825 uint32_t status; 826 827 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 828 829 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 830 831 if (ex->ex_sqtdstart == NULL) { 832 printf("ehci_check_qh_intr: not valid sqtd\n"); 833 return; 834 } 835 836 lsqtd = ex->ex_sqtdend; 837 #ifdef DIAGNOSTIC 838 if (lsqtd == NULL) { 839 printf("ehci_check_qh_intr: lsqtd==0\n"); 840 return; 841 } 842 #endif 843 /* 844 * If the last TD is still active we need to check whether there 845 * is an error somewhere in the middle, or whether there was a 846 * short packet (SPD and not ACTIVE). 847 */ 848 usb_syncmem(&lsqtd->dma, 849 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 850 sizeof(lsqtd->qtd.qtd_status), 851 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 852 status = le32toh(lsqtd->qtd.qtd_status); 853 usb_syncmem(&lsqtd->dma, 854 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 855 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 856 if (status & EHCI_QTD_ACTIVE) { 857 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 858 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd; 859 sqtd = sqtd->nextqtd) { 860 usb_syncmem(&sqtd->dma, 861 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 862 sizeof(sqtd->qtd.qtd_status), 863 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 864 status = le32toh(sqtd->qtd.qtd_status); 865 usb_syncmem(&sqtd->dma, 866 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 867 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 868 /* If there's an active QTD the xfer isn't done. */ 869 if (status & EHCI_QTD_ACTIVE) 870 break; 871 /* Any kind of error makes the xfer done. */ 872 if (status & EHCI_QTD_HALTED) 873 goto done; 874 /* Handle short packets */ 875 if (EHCI_QTD_GET_BYTES(status) != 0) { 876 usbd_pipe_handle pipe = ex->ex_xfer.ux_pipe; 877 usb_endpoint_descriptor_t *ed = 878 pipe->up_endpoint->ue_edesc; 879 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 880 881 /* 882 * If we get here for a control transfer then 883 * we need to let the hardware complete the 884 * status phase. That is, we're not done 885 * quite yet. 886 * 887 * Otherwise, we're done. 888 */ 889 if (xt == UE_CONTROL) { 890 break; 891 } 892 goto done; 893 } 894 } 895 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 896 ex, ex->ex_sqtdstart, 0, 0); 897 #ifdef EHCI_DEBUG 898 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 0, 0); 899 ehci_dump_sqtds(ex->ex_sqtdstart); 900 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 0); 901 #endif 902 return; 903 } 904 done: 905 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 906 callout_stop(&ex->ex_xfer.ux_callout); 907 ehci_idone(ex); 908 } 909 910 Static void 911 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 912 { 913 ehci_soft_itd_t *itd; 914 int i; 915 916 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 917 918 KASSERT(mutex_owned(&sc->sc_lock)); 919 920 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 921 return; 922 923 if (ex->ex_itdstart == NULL) { 924 printf("ehci_check_itd_intr: not valid itd\n"); 925 return; 926 } 927 928 itd = ex->ex_itdend; 929 #ifdef DIAGNOSTIC 930 if (itd == NULL) { 931 printf("ehci_check_itd_intr: itdend == 0\n"); 932 return; 933 } 934 #endif 935 936 /* 937 * check no active transfers in last itd, meaning we're finished 938 */ 939 940 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 941 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 942 BUS_DMASYNC_POSTREAD); 943 944 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 945 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 946 break; 947 } 948 949 if (i == EHCI_ITD_NUFRAMES) { 950 goto done; /* All 8 descriptors inactive, it's done */ 951 } 952 953 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 954 ex->ex_itdstart, 0, 0); 955 return; 956 done: 957 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 958 callout_stop(&ex->ex_xfer.ux_callout); 959 ehci_idone(ex); 960 } 961 962 void 963 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 964 { 965 ehci_soft_sitd_t *sitd; 966 967 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 968 969 KASSERT(mutex_owned(&sc->sc_lock)); 970 971 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 972 return; 973 974 if (ex->ex_sitdstart == NULL) { 975 printf("ehci_check_sitd_intr: not valid sitd\n"); 976 return; 977 } 978 979 sitd = ex->ex_sitdend; 980 #ifdef DIAGNOSTIC 981 if (sitd == NULL) { 982 printf("ehci_check_sitd_intr: sitdend == 0\n"); 983 return; 984 } 985 #endif 986 987 /* 988 * check no active transfers in last sitd, meaning we're finished 989 */ 990 991 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 992 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 993 BUS_DMASYNC_POSTREAD); 994 995 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 996 return; 997 998 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 999 callout_stop(&(ex->ex_xfer.ux_callout)); 1000 ehci_idone(ex); 1001 } 1002 1003 1004 Static void 1005 ehci_idone(struct ehci_xfer *ex) 1006 { 1007 usbd_xfer_handle xfer = &ex->ex_xfer; 1008 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1009 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1010 ehci_soft_qtd_t *sqtd, *lsqtd; 1011 uint32_t status = 0, nstatus = 0; 1012 int actlen; 1013 1014 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1015 1016 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1017 1018 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1019 1020 #ifdef DIAGNOSTIC 1021 if (ex->ex_isdone) { 1022 printf("ehci_idone: ex=%p is done!\n", ex); 1023 #ifdef EHCI_DEBUG 1024 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1025 ehci_dump_exfer(ex); 1026 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1027 #endif 1028 return; 1029 } 1030 ex->ex_isdone = 1; 1031 #endif 1032 1033 if (xfer->ux_status == USBD_CANCELLED || 1034 xfer->ux_status == USBD_TIMEOUT) { 1035 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1036 return; 1037 } 1038 1039 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1040 #ifdef EHCI_DEBUG 1041 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1042 ehci_dump_sqtds(ex->ex_sqtdstart); 1043 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1044 #endif 1045 1046 /* The transfer is done, compute actual length and status. */ 1047 1048 u_int xfertype, speed; 1049 1050 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1051 speed = xfer->ux_pipe->up_dev->ud_speed; 1052 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1053 /* HS isoc transfer */ 1054 1055 struct ehci_soft_itd *itd; 1056 int i, nframes, len, uframes; 1057 1058 nframes = 0; 1059 actlen = 0; 1060 1061 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1062 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1063 1064 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1065 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1066 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1067 BUS_DMASYNC_POSTREAD); 1068 1069 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1070 /* 1071 * XXX - driver didn't fill in the frame full 1072 * of uframes. This leads to scheduling 1073 * inefficiencies, but working around 1074 * this doubles complexity of tracking 1075 * an xfer. 1076 */ 1077 if (nframes >= xfer->ux_nframes) 1078 break; 1079 1080 status = le32toh(itd->itd.itd_ctl[i]); 1081 len = EHCI_ITD_GET_LEN(status); 1082 if (EHCI_ITD_GET_STATUS(status) != 0) 1083 len = 0; /*No valid data on error*/ 1084 1085 xfer->ux_frlengths[nframes++] = len; 1086 actlen += len; 1087 } 1088 1089 if (nframes >= xfer->ux_nframes) 1090 break; 1091 } 1092 1093 xfer->ux_actlen = actlen; 1094 xfer->ux_status = USBD_NORMAL_COMPLETION; 1095 goto end; 1096 } 1097 1098 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1099 /* FS isoc transfer */ 1100 struct ehci_soft_sitd *sitd; 1101 int nframes, len; 1102 1103 nframes = 0; 1104 actlen = 0; 1105 1106 for (sitd = ex->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1107 usb_syncmem(&sitd->dma,sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 1108 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 1109 BUS_DMASYNC_POSTREAD); 1110 1111 /* 1112 * XXX - driver didn't fill in the frame full 1113 * of uframes. This leads to scheduling 1114 * inefficiencies, but working around 1115 * this doubles complexity of tracking 1116 * an xfer. 1117 */ 1118 if (nframes >= xfer->ux_nframes) 1119 break; 1120 1121 status = le32toh(sitd->sitd.sitd_trans); 1122 len = EHCI_SITD_GET_LEN(status); 1123 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1124 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1125 /* No valid data on error */ 1126 len = xfer->ux_frlengths[nframes]; 1127 } 1128 1129 /* 1130 * frlengths[i]: # of bytes to send 1131 * len: # of bytes host didn't send 1132 */ 1133 xfer->ux_frlengths[nframes] -= len; 1134 /* frlengths[i]: # of bytes host sent */ 1135 actlen += xfer->ux_frlengths[nframes++]; 1136 1137 if (nframes >= xfer->ux_nframes) 1138 break; 1139 } 1140 1141 xfer->ux_actlen = actlen; 1142 xfer->ux_status = USBD_NORMAL_COMPLETION; 1143 goto end; 1144 } 1145 KASSERT(xfertype != UE_ISOCHRONOUS); 1146 1147 /* Continue processing xfers using queue heads */ 1148 1149 lsqtd = ex->ex_sqtdend; 1150 actlen = 0; 1151 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd->nextqtd; 1152 sqtd = sqtd->nextqtd) { 1153 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1154 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1155 nstatus = le32toh(sqtd->qtd.qtd_status); 1156 if (nstatus & EHCI_QTD_ACTIVE) 1157 break; 1158 1159 status = nstatus; 1160 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1161 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1162 } 1163 1164 1165 /* 1166 * If there are left over TDs we need to update the toggle. 1167 * The default pipe doesn't need it since control transfers 1168 * start the toggle at 0 every time. 1169 * For a short transfer we need to update the toggle for the missing 1170 * packets within the qTD. 1171 */ 1172 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1173 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1174 USBHIST_LOG(ehcidebug, 1175 "toggle update status=0x%08x nstatus=0x%08x", 1176 status, nstatus, 0, 0); 1177 #if 0 1178 ehci_dump_sqh(epipe->sqh); 1179 ehci_dump_sqtds(ex->ex_sqtdstart); 1180 #endif 1181 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1182 } 1183 1184 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1185 actlen, status, 0); 1186 xfer->ux_actlen = actlen; 1187 if (status & EHCI_QTD_HALTED) { 1188 #ifdef EHCI_DEBUG 1189 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1190 xfer->ux_pipe->up_dev->ud_addr, 1191 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1192 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1193 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1194 0, 0); 1195 USBHIST_LOG(ehcidebug, 1196 "active =%d halted=%d buferr=%d babble=%d", 1197 status & EHCI_QTD_ACTIVE ? 1 : 0, 1198 status & EHCI_QTD_HALTED ? 1 : 0, 1199 status & EHCI_QTD_BUFERR ? 1 : 0, 1200 status & EHCI_QTD_BABBLE ? 1 : 0); 1201 1202 USBHIST_LOG(ehcidebug, 1203 "xacterr=%d missed=%d split =%d ping =%d", 1204 status & EHCI_QTD_XACTERR ? 1 : 0, 1205 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1206 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1207 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1208 1209 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1210 ehci_dump_sqh(epipe->sqh); 1211 ehci_dump_sqtds(ex->ex_sqtdstart); 1212 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1213 #endif 1214 /* low&full speed has an extra error flag */ 1215 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1216 EHCI_QH_SPEED_HIGH) 1217 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1218 else 1219 status &= EHCI_QTD_STATERRS; 1220 if (status == 0) /* no other errors means a stall */ { 1221 xfer->ux_status = USBD_STALLED; 1222 } else { 1223 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1224 } 1225 /* XXX need to reset TT on missed microframe */ 1226 if (status & EHCI_QTD_MISSEDMICRO) { 1227 printf("%s: missed microframe, TT reset not " 1228 "implemented, hub might be inoperational\n", 1229 device_xname(sc->sc_dev)); 1230 } 1231 } else { 1232 xfer->ux_status = USBD_NORMAL_COMPLETION; 1233 } 1234 1235 end: 1236 /* 1237 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1238 * during this call, before methods->done is called: dma sync required 1239 * beforehand? 1240 */ 1241 usb_transfer_complete(xfer); 1242 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1243 } 1244 1245 /* 1246 * Wait here until controller claims to have an interrupt. 1247 * Then call ehci_intr and return. Use timeout to avoid waiting 1248 * too long. 1249 */ 1250 Static void 1251 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1252 { 1253 int timo; 1254 uint32_t intrs; 1255 1256 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1257 1258 xfer->ux_status = USBD_IN_PROGRESS; 1259 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1260 usb_delay_ms(&sc->sc_bus, 1); 1261 if (sc->sc_dying) 1262 break; 1263 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1264 sc->sc_eintrs; 1265 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1266 #ifdef EHCI_DEBUG 1267 if (ehcidebug > 15) 1268 ehci_dump_regs(sc); 1269 #endif 1270 if (intrs) { 1271 mutex_spin_enter(&sc->sc_intr_lock); 1272 ehci_intr1(sc); 1273 mutex_spin_exit(&sc->sc_intr_lock); 1274 if (xfer->ux_status != USBD_IN_PROGRESS) 1275 return; 1276 } 1277 } 1278 1279 /* Timeout */ 1280 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1281 xfer->ux_status = USBD_TIMEOUT; 1282 mutex_enter(&sc->sc_lock); 1283 usb_transfer_complete(xfer); 1284 mutex_exit(&sc->sc_lock); 1285 /* XXX should free TD */ 1286 } 1287 1288 Static void 1289 ehci_poll(struct usbd_bus *bus) 1290 { 1291 ehci_softc_t *sc = bus->ub_hcpriv; 1292 1293 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1294 1295 #ifdef EHCI_DEBUG 1296 static int last; 1297 int new; 1298 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1299 if (new != last) { 1300 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1301 last = new; 1302 } 1303 #endif 1304 1305 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1306 mutex_spin_enter(&sc->sc_intr_lock); 1307 ehci_intr1(sc); 1308 mutex_spin_exit(&sc->sc_intr_lock); 1309 } 1310 } 1311 1312 void 1313 ehci_childdet(device_t self, device_t child) 1314 { 1315 struct ehci_softc *sc = device_private(self); 1316 1317 KASSERT(sc->sc_child == child); 1318 sc->sc_child = NULL; 1319 } 1320 1321 int 1322 ehci_detach(struct ehci_softc *sc, int flags) 1323 { 1324 int rv = 0; 1325 1326 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1327 1328 if (sc->sc_child != NULL) 1329 rv = config_detach(sc->sc_child, flags); 1330 1331 if (rv != 0) 1332 return rv; 1333 1334 callout_halt(&sc->sc_tmo_intrlist, NULL); 1335 callout_destroy(&sc->sc_tmo_intrlist); 1336 1337 /* XXX free other data structures XXX */ 1338 if (sc->sc_softitds) 1339 kmem_free(sc->sc_softitds, 1340 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1341 cv_destroy(&sc->sc_doorbell); 1342 cv_destroy(&sc->sc_softwake_cv); 1343 1344 #if 0 1345 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1346 1347 softint_disestablish(sc->sc_doorbell_si); 1348 softint_disestablish(sc->sc_pcd_si); 1349 1350 mutex_destroy(&sc->sc_lock); 1351 mutex_destroy(&sc->sc_intr_lock); 1352 #endif 1353 1354 pool_cache_destroy(sc->sc_xferpool); 1355 1356 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1357 1358 return rv; 1359 } 1360 1361 1362 int 1363 ehci_activate(device_t self, enum devact act) 1364 { 1365 struct ehci_softc *sc = device_private(self); 1366 1367 switch (act) { 1368 case DVACT_DEACTIVATE: 1369 sc->sc_dying = 1; 1370 return 0; 1371 default: 1372 return EOPNOTSUPP; 1373 } 1374 } 1375 1376 /* 1377 * Handle suspend/resume. 1378 * 1379 * We need to switch to polling mode here, because this routine is 1380 * called from an interrupt context. This is all right since we 1381 * are almost suspended anyway. 1382 * 1383 * Note that this power handler isn't to be registered directly; the 1384 * bus glue needs to call out to it. 1385 */ 1386 bool 1387 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1388 { 1389 ehci_softc_t *sc = device_private(dv); 1390 int i; 1391 uint32_t cmd, hcr; 1392 1393 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1394 1395 mutex_spin_enter(&sc->sc_intr_lock); 1396 sc->sc_bus.ub_usepolling++; 1397 mutex_spin_exit(&sc->sc_intr_lock); 1398 1399 for (i = 1; i <= sc->sc_noport; i++) { 1400 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1401 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1402 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1403 } 1404 1405 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1406 1407 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1408 EOWRITE4(sc, EHCI_USBCMD, cmd); 1409 1410 for (i = 0; i < 100; i++) { 1411 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1412 if (hcr == 0) 1413 break; 1414 1415 usb_delay_ms(&sc->sc_bus, 1); 1416 } 1417 if (hcr != 0) 1418 printf("%s: reset timeout\n", device_xname(dv)); 1419 1420 cmd &= ~EHCI_CMD_RS; 1421 EOWRITE4(sc, EHCI_USBCMD, cmd); 1422 1423 for (i = 0; i < 100; i++) { 1424 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1425 if (hcr == EHCI_STS_HCH) 1426 break; 1427 1428 usb_delay_ms(&sc->sc_bus, 1); 1429 } 1430 if (hcr != EHCI_STS_HCH) 1431 printf("%s: config timeout\n", device_xname(dv)); 1432 1433 mutex_spin_enter(&sc->sc_intr_lock); 1434 sc->sc_bus.ub_usepolling--; 1435 mutex_spin_exit(&sc->sc_intr_lock); 1436 1437 return true; 1438 } 1439 1440 bool 1441 ehci_resume(device_t dv, const pmf_qual_t *qual) 1442 { 1443 ehci_softc_t *sc = device_private(dv); 1444 int i; 1445 uint32_t cmd, hcr; 1446 1447 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1448 1449 /* restore things in case the bios sucks */ 1450 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1451 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1452 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1453 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1454 1455 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1456 1457 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1458 1459 hcr = 0; 1460 for (i = 1; i <= sc->sc_noport; i++) { 1461 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1462 if ((cmd & EHCI_PS_PO) == 0 && 1463 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1464 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1465 hcr = 1; 1466 } 1467 } 1468 1469 if (hcr) { 1470 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1471 1472 for (i = 1; i <= sc->sc_noport; i++) { 1473 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1474 if ((cmd & EHCI_PS_PO) == 0 && 1475 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1476 EOWRITE4(sc, EHCI_PORTSC(i), 1477 cmd & ~EHCI_PS_FPR); 1478 } 1479 } 1480 1481 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1482 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1483 1484 for (i = 0; i < 100; i++) { 1485 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1486 if (hcr != EHCI_STS_HCH) 1487 break; 1488 1489 usb_delay_ms(&sc->sc_bus, 1); 1490 } 1491 if (hcr == EHCI_STS_HCH) 1492 printf("%s: config timeout\n", device_xname(dv)); 1493 1494 return true; 1495 } 1496 1497 /* 1498 * Shut down the controller when the system is going down. 1499 */ 1500 bool 1501 ehci_shutdown(device_t self, int flags) 1502 { 1503 ehci_softc_t *sc = device_private(self); 1504 1505 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1506 1507 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1508 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1509 return true; 1510 } 1511 1512 Static usbd_xfer_handle 1513 ehci_allocx(struct usbd_bus *bus) 1514 { 1515 struct ehci_softc *sc = bus->ub_hcpriv; 1516 usbd_xfer_handle xfer; 1517 1518 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1519 if (xfer != NULL) { 1520 memset(xfer, 0, sizeof(struct ehci_xfer)); 1521 #ifdef DIAGNOSTIC 1522 EXFER(xfer)->ex_isdone = 1; 1523 xfer->ux_state = XFER_BUSY; 1524 #endif 1525 } 1526 return xfer; 1527 } 1528 1529 Static void 1530 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1531 { 1532 struct ehci_softc *sc = bus->ub_hcpriv; 1533 1534 #ifdef DIAGNOSTIC 1535 if (xfer->ux_state != XFER_BUSY) { 1536 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer, 1537 xfer->ux_state); 1538 } 1539 xfer->ux_state = XFER_FREE; 1540 if (!EXFER(xfer)->ex_isdone) { 1541 printf("ehci_freex: !isdone\n"); 1542 } 1543 #endif 1544 pool_cache_put(sc->sc_xferpool, xfer); 1545 } 1546 1547 Static void 1548 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1549 { 1550 struct ehci_softc *sc = bus->ub_hcpriv; 1551 1552 *lock = &sc->sc_lock; 1553 } 1554 1555 Static void 1556 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1557 { 1558 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1559 1560 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1561 1562 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1563 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1564 #ifdef EHCI_DEBUG 1565 if (ehcidebug) 1566 usbd_dump_pipe(pipe); 1567 #endif 1568 epipe->nexttoggle = 0; 1569 } 1570 1571 Static void 1572 ehci_noop(usbd_pipe_handle pipe) 1573 { 1574 } 1575 1576 #ifdef EHCI_DEBUG 1577 /* 1578 * Unused function - this is meant to be called from a kernel 1579 * debugger. 1580 */ 1581 void 1582 ehci_dump(void) 1583 { 1584 ehci_softc_t *sc = theehci; 1585 int i; 1586 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1587 EOREAD4(sc, EHCI_USBCMD), 1588 EOREAD4(sc, EHCI_USBSTS), 1589 EOREAD4(sc, EHCI_USBINTR)); 1590 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1591 EOREAD4(sc, EHCI_FRINDEX), 1592 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1593 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1594 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1595 for (i = 1; i <= sc->sc_noport; i++) 1596 printf("port %d status=0x%08x\n", i, 1597 EOREAD4(sc, EHCI_PORTSC(i))); 1598 } 1599 1600 Static void 1601 ehci_dump_regs(ehci_softc_t *sc) 1602 { 1603 int i; 1604 1605 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1606 1607 USBHIST_LOG(ehcidebug, 1608 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1609 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1610 EOREAD4(sc, EHCI_USBINTR), 0); 1611 USBHIST_LOG(ehcidebug, 1612 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1613 "async = 0x%08x", 1614 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1615 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1616 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1617 for (i = 1; i <= sc->sc_noport; i += 2) { 1618 if (i == sc->sc_noport) { 1619 USBHIST_LOG(ehcidebug, 1620 "port %d status = 0x%08x", i, 1621 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1622 } else { 1623 USBHIST_LOG(ehcidebug, 1624 "port %d status = 0x%08x port %d status = 0x%08x", 1625 i, EOREAD4(sc, EHCI_PORTSC(i)), 1626 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1627 } 1628 } 1629 } 1630 1631 #ifdef EHCI_DEBUG 1632 #define ehci_dump_link(link, type) do { \ 1633 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1634 link, \ 1635 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1636 if (type) { \ 1637 USBHIST_LOG(ehcidebug, \ 1638 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1639 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1640 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1641 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1642 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1643 } \ 1644 } while(0) 1645 #else 1646 #define ehci_dump_link(link, type) 1647 #endif 1648 1649 Static void 1650 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1651 { 1652 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1653 int i; 1654 uint32_t stop = 0; 1655 1656 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1657 ehci_dump_sqtd(sqtd); 1658 usb_syncmem(&sqtd->dma, 1659 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1660 sizeof(sqtd->qtd), 1661 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1662 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1663 usb_syncmem(&sqtd->dma, 1664 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1665 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1666 } 1667 if (!stop) 1668 USBHIST_LOG(ehcidebug, 1669 "dump aborted, too many TDs", 0, 0, 0, 0); 1670 } 1671 1672 Static void 1673 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1674 { 1675 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1676 1677 usb_syncmem(&sqtd->dma, sqtd->offs, 1678 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1679 1680 USBHIST_LOGN(ehcidebug, 10, 1681 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1682 ehci_dump_qtd(&sqtd->qtd); 1683 1684 usb_syncmem(&sqtd->dma, sqtd->offs, 1685 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1686 } 1687 1688 Static void 1689 ehci_dump_qtd(ehci_qtd_t *qtd) 1690 { 1691 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1692 1693 #ifdef USBHIST 1694 uint32_t s = le32toh(qtd->qtd_status); 1695 #endif 1696 1697 USBHIST_LOGN(ehcidebug, 10, 1698 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1699 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1700 USBHIST_LOGN(ehcidebug, 10, 1701 " toggle = %d ioc = %d bytes = %#x " 1702 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1703 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1704 USBHIST_LOGN(ehcidebug, 10, 1705 " cerr = %d pid = %d stat = %x", 1706 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1707 0); 1708 USBHIST_LOGN(ehcidebug, 10, 1709 "active =%d halted=%d buferr=%d babble=%d", 1710 s & EHCI_QTD_ACTIVE ? 1 : 0, 1711 s & EHCI_QTD_HALTED ? 1 : 0, 1712 s & EHCI_QTD_BUFERR ? 1 : 0, 1713 s & EHCI_QTD_BABBLE ? 1 : 0); 1714 USBHIST_LOGN(ehcidebug, 10, 1715 "xacterr=%d missed=%d split =%d ping =%d", 1716 s & EHCI_QTD_XACTERR ? 1 : 0, 1717 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1718 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1719 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1720 USBHIST_LOGN(ehcidebug, 10, 1721 "buffer[0] = %#x buffer[1] = %#x " 1722 "buffer[2] = %#x buffer[3] = %#x", 1723 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1724 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1725 USBHIST_LOGN(ehcidebug, 10, 1726 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1727 } 1728 1729 Static void 1730 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1731 { 1732 #ifdef USBHIST 1733 ehci_qh_t *qh = &sqh->qh; 1734 ehci_link_t link; 1735 #endif 1736 uint32_t endp, endphub; 1737 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1738 1739 usb_syncmem(&sqh->dma, sqh->offs, 1740 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1741 1742 USBHIST_LOGN(ehcidebug, 10, 1743 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1744 link = le32toh(qh->qh_link); 1745 ehci_dump_link(link, true); 1746 1747 endp = le32toh(qh->qh_endp); 1748 USBHIST_LOGN(ehcidebug, 10, 1749 " endp = %#x", endp, 0, 0, 0); 1750 USBHIST_LOGN(ehcidebug, 10, 1751 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1752 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1753 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1754 USBHIST_LOGN(ehcidebug, 10, 1755 " dtc = %d hrecl = %d", 1756 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1757 USBHIST_LOGN(ehcidebug, 10, 1758 " ctl = %d nrl = %d mpl = %#x(%d)", 1759 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1760 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1761 1762 endphub = le32toh(qh->qh_endphub); 1763 USBHIST_LOGN(ehcidebug, 10, 1764 " endphub = %#x", endphub, 0, 0, 0); 1765 USBHIST_LOGN(ehcidebug, 10, 1766 " smask = 0x%02x cmask = 0x%02x", 1767 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1768 USBHIST_LOGN(ehcidebug, 10, 1769 " huba = 0x%02x port = %d mult = %d", 1770 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1771 EHCI_QH_GET_MULT(endphub), 0); 1772 1773 link = le32toh(qh->qh_curqtd); 1774 ehci_dump_link(link, false); 1775 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1776 ehci_dump_qtd(&qh->qh_qtd); 1777 1778 usb_syncmem(&sqh->dma, sqh->offs, 1779 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1780 } 1781 1782 Static void 1783 ehci_dump_itd(struct ehci_soft_itd *itd) 1784 { 1785 ehci_isoc_trans_t t; 1786 ehci_isoc_bufr_ptr_t b, b2, b3; 1787 int i; 1788 1789 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1790 1791 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1792 0, 0); 1793 1794 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1795 t = le32toh(itd->itd.itd_ctl[i]); 1796 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1797 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1798 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1799 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1800 EHCI_ITD_GET_OFFS(t), 0); 1801 } 1802 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1803 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1804 USBHIST_LOG(ehcidebug, " %x", 1805 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1806 1807 b = le32toh(itd->itd.itd_bufr[0]); 1808 b2 = le32toh(itd->itd.itd_bufr[1]); 1809 b3 = le32toh(itd->itd.itd_bufr[2]); 1810 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1811 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1812 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1813 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1814 } 1815 1816 Static void 1817 ehci_dump_sitd(struct ehci_soft_itd *itd) 1818 { 1819 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1820 1821 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1822 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1823 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1824 itd->xfer_next, itd->physaddr, itd->slot, 0); 1825 } 1826 1827 Static void 1828 ehci_dump_exfer(struct ehci_xfer *ex) 1829 { 1830 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1831 1832 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1833 ex, ex->ex_sqtdstart, ex->ex_sqtdend, 0); 1834 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1835 ex->ex_itdstart, ex->ex_itdend, ex->ex_isdone, 0); 1836 } 1837 #endif 1838 1839 Static usbd_status 1840 ehci_open(usbd_pipe_handle pipe) 1841 { 1842 usbd_device_handle dev = pipe->up_dev; 1843 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1844 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1845 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1846 uint8_t addr = dev->ud_addr; 1847 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1848 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1849 ehci_soft_qh_t *sqh; 1850 usbd_status err; 1851 int ival, speed, naks; 1852 int hshubaddr, hshubport; 1853 1854 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1855 1856 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1857 pipe, addr, ed->bEndpointAddress, rhaddr); 1858 1859 if (dev->ud_myhsport) { 1860 /* 1861 * When directly attached FS/LS device while doing embedded 1862 * transaction translations and we are the hub, set the hub 1863 * address to 0 (us). 1864 */ 1865 if (!(sc->sc_flags & EHCIF_ETTF) 1866 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1867 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1868 } else { 1869 hshubaddr = 0; 1870 } 1871 hshubport = dev->ud_myhsport->up_portno; 1872 } else { 1873 hshubaddr = 0; 1874 hshubport = 0; 1875 } 1876 1877 if (sc->sc_dying) 1878 return USBD_IOERROR; 1879 1880 /* toggle state needed for bulk endpoints */ 1881 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1882 1883 if (addr == rhaddr) { 1884 switch (ed->bEndpointAddress) { 1885 case USB_CONTROL_ENDPOINT: 1886 pipe->up_methods = &roothub_ctrl_methods; 1887 break; 1888 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1889 pipe->up_methods = &ehci_root_intr_methods; 1890 break; 1891 default: 1892 USBHIST_LOG(ehcidebug, 1893 "bad bEndpointAddress 0x%02x", 1894 ed->bEndpointAddress, 0, 0, 0); 1895 return USBD_INVAL; 1896 } 1897 return USBD_NORMAL_COMPLETION; 1898 } 1899 1900 /* XXX All this stuff is only valid for async. */ 1901 switch (dev->ud_speed) { 1902 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1903 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1904 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1905 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1906 } 1907 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1908 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1909 hshubaddr, hshubport, 0, 0); 1910 return USBD_INVAL; 1911 } 1912 1913 /* 1914 * For interrupt transfer, nak throttling must be disabled, but for 1915 * the other transfer type, nak throttling should be enabled from the 1916 * viewpoint that avoids the memory thrashing. 1917 */ 1918 naks = (xfertype == UE_INTERRUPT) ? 0 1919 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1920 1921 /* Allocate sqh for everything, save isoc xfers */ 1922 if (xfertype != UE_ISOCHRONOUS) { 1923 sqh = ehci_alloc_sqh(sc); 1924 if (sqh == NULL) 1925 return USBD_NOMEM; 1926 /* qh_link filled when the QH is added */ 1927 sqh->qh.qh_endp = htole32( 1928 EHCI_QH_SET_ADDR(addr) | 1929 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1930 EHCI_QH_SET_EPS(speed) | 1931 EHCI_QH_DTC | 1932 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1933 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1934 EHCI_QH_CTL : 0) | 1935 EHCI_QH_SET_NRL(naks) 1936 ); 1937 sqh->qh.qh_endphub = htole32( 1938 EHCI_QH_SET_MULT(1) | 1939 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1940 ); 1941 if (speed != EHCI_QH_SPEED_HIGH) 1942 sqh->qh.qh_endphub |= htole32( 1943 EHCI_QH_SET_PORT(hshubport) | 1944 EHCI_QH_SET_HUBA(hshubaddr) | 1945 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1946 ); 1947 sqh->qh.qh_curqtd = EHCI_NULL; 1948 /* Fill the overlay qTD */ 1949 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1950 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1951 sqh->qh.qh_qtd.qtd_status = htole32(0); 1952 1953 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1954 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1955 epipe->sqh = sqh; 1956 } else { 1957 sqh = NULL; 1958 } /*xfertype == UE_ISOC*/ 1959 1960 switch (xfertype) { 1961 case UE_CONTROL: 1962 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1963 0, &epipe->u.ctl.reqdma); 1964 #ifdef EHCI_DEBUG 1965 if (err) 1966 printf("ehci_open: usb_allocmem()=%d\n", err); 1967 #endif 1968 if (err) 1969 goto bad; 1970 pipe->up_methods = &ehci_device_ctrl_methods; 1971 mutex_enter(&sc->sc_lock); 1972 ehci_add_qh(sc, sqh, sc->sc_async_head); 1973 mutex_exit(&sc->sc_lock); 1974 break; 1975 case UE_BULK: 1976 pipe->up_methods = &ehci_device_bulk_methods; 1977 mutex_enter(&sc->sc_lock); 1978 ehci_add_qh(sc, sqh, sc->sc_async_head); 1979 mutex_exit(&sc->sc_lock); 1980 break; 1981 case UE_INTERRUPT: 1982 pipe->up_methods = &ehci_device_intr_methods; 1983 ival = pipe->up_interval; 1984 if (ival == USBD_DEFAULT_INTERVAL) { 1985 if (speed == EHCI_QH_SPEED_HIGH) { 1986 if (ed->bInterval > 16) { 1987 /* 1988 * illegal with high-speed, but there 1989 * were documentation bugs in the spec, 1990 * so be generous 1991 */ 1992 ival = 256; 1993 } else 1994 ival = (1 << (ed->bInterval - 1)) / 8; 1995 } else 1996 ival = ed->bInterval; 1997 } 1998 err = ehci_device_setintr(sc, sqh, ival); 1999 if (err) 2000 goto bad; 2001 break; 2002 case UE_ISOCHRONOUS: 2003 if (speed == EHCI_QH_SPEED_HIGH) 2004 pipe->up_methods = &ehci_device_isoc_methods; 2005 else 2006 pipe->up_methods = &ehci_device_fs_isoc_methods; 2007 if (ed->bInterval == 0 || ed->bInterval > 16) { 2008 printf("ehci: opening pipe with invalid bInterval\n"); 2009 err = USBD_INVAL; 2010 goto bad; 2011 } 2012 if (UGETW(ed->wMaxPacketSize) == 0) { 2013 printf("ehci: zero length endpoint open request\n"); 2014 err = USBD_INVAL; 2015 goto bad; 2016 } 2017 epipe->u.isoc.next_frame = 0; 2018 epipe->u.isoc.cur_xfers = 0; 2019 break; 2020 default: 2021 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2022 err = USBD_INVAL; 2023 goto bad; 2024 } 2025 return USBD_NORMAL_COMPLETION; 2026 2027 bad: 2028 if (sqh != NULL) 2029 ehci_free_sqh(sc, sqh); 2030 return err; 2031 } 2032 2033 /* 2034 * Add an ED to the schedule. Called with USB lock held. 2035 */ 2036 Static void 2037 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2038 { 2039 2040 KASSERT(mutex_owned(&sc->sc_lock)); 2041 2042 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2043 2044 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2045 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2046 2047 sqh->next = head->next; 2048 sqh->qh.qh_link = head->qh.qh_link; 2049 2050 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2051 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2052 2053 head->next = sqh; 2054 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2055 2056 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2057 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2058 2059 #ifdef EHCI_DEBUG 2060 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2061 ehci_dump_sqh(sqh); 2062 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2063 #endif 2064 } 2065 2066 /* 2067 * Remove an ED from the schedule. Called with USB lock held. 2068 */ 2069 Static void 2070 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2071 { 2072 ehci_soft_qh_t *p; 2073 2074 KASSERT(mutex_owned(&sc->sc_lock)); 2075 2076 /* XXX */ 2077 for (p = head; p != NULL && p->next != sqh; p = p->next) 2078 ; 2079 if (p == NULL) 2080 panic("ehci_rem_qh: ED not found"); 2081 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2082 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2083 p->next = sqh->next; 2084 p->qh.qh_link = sqh->qh.qh_link; 2085 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2086 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2087 2088 ehci_sync_hc(sc); 2089 } 2090 2091 Static void 2092 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2093 { 2094 int i; 2095 uint32_t status; 2096 2097 /* Save toggle bit and ping status. */ 2098 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2099 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2100 status = sqh->qh.qh_qtd.qtd_status & 2101 htole32(EHCI_QTD_TOGGLE_MASK | 2102 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2103 /* Set HALTED to make hw leave it alone. */ 2104 sqh->qh.qh_qtd.qtd_status = 2105 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2106 usb_syncmem(&sqh->dma, 2107 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2108 sizeof(sqh->qh.qh_qtd.qtd_status), 2109 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2110 sqh->qh.qh_curqtd = 0; 2111 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2112 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2113 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2114 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2115 sqh->sqtd = sqtd; 2116 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2117 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2118 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2119 sqh->qh.qh_qtd.qtd_status = status; 2120 usb_syncmem(&sqh->dma, 2121 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2122 sizeof(sqh->qh.qh_qtd.qtd_status), 2123 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2124 } 2125 2126 /* 2127 * Ensure that the HC has released all references to the QH. We do this 2128 * by asking for a Async Advance Doorbell interrupt and then we wait for 2129 * the interrupt. 2130 * To make this easier we first obtain exclusive use of the doorbell. 2131 */ 2132 Static void 2133 ehci_sync_hc(ehci_softc_t *sc) 2134 { 2135 int error __diagused; 2136 2137 KASSERT(mutex_owned(&sc->sc_lock)); 2138 2139 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2140 2141 if (sc->sc_dying) { 2142 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2143 return; 2144 } 2145 /* ask for doorbell */ 2146 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2147 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2148 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2149 2150 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2151 2152 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2153 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2154 #ifdef DIAGNOSTIC 2155 if (error) 2156 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2157 #endif 2158 } 2159 2160 Static void 2161 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2162 { 2163 struct ehci_soft_itd *itd, *prev; 2164 2165 prev = NULL; 2166 2167 if (exfer->ex_itdstart == NULL || exfer->ex_itdend == NULL) 2168 panic("ehci isoc xfer being freed, but with no itd chain\n"); 2169 2170 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2171 prev = itd->u.frame_list.prev; 2172 /* Unlink itd from hardware chain, or frame array */ 2173 if (prev == NULL) { /* We're at the table head */ 2174 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2175 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2176 usb_syncmem(&sc->sc_fldma, 2177 sizeof(ehci_link_t) * itd->slot, 2178 sizeof(ehci_link_t), 2179 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2180 2181 if (itd->u.frame_list.next != NULL) 2182 itd->u.frame_list.next->u.frame_list.prev = NULL; 2183 } else { 2184 /* XXX this part is untested... */ 2185 prev->itd.itd_next = itd->itd.itd_next; 2186 usb_syncmem(&itd->dma, 2187 itd->offs + offsetof(ehci_itd_t, itd_next), 2188 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2189 2190 prev->u.frame_list.next = itd->u.frame_list.next; 2191 if (itd->u.frame_list.next != NULL) 2192 itd->u.frame_list.next->u.frame_list.prev = prev; 2193 } 2194 } 2195 2196 prev = NULL; 2197 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2198 if (prev != NULL) 2199 ehci_free_itd(sc, prev); 2200 prev = itd; 2201 } 2202 if (prev) 2203 ehci_free_itd(sc, prev); 2204 exfer->ex_itdstart = NULL; 2205 exfer->ex_itdend = NULL; 2206 } 2207 2208 Static void 2209 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2210 { 2211 struct ehci_soft_sitd *sitd, *prev; 2212 2213 prev = NULL; 2214 2215 if (exfer->ex_sitdstart == NULL || exfer->ex_sitdend == NULL) 2216 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2217 2218 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2219 prev = sitd->u.frame_list.prev; 2220 /* Unlink sitd from hardware chain, or frame array */ 2221 if (prev == NULL) { /* We're at the table head */ 2222 sc->sc_softsitds[sitd->slot] = sitd->u.frame_list.next; 2223 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2224 usb_syncmem(&sc->sc_fldma, 2225 sizeof(ehci_link_t) * sitd->slot, 2226 sizeof(ehci_link_t), 2227 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2228 2229 if (sitd->u.frame_list.next != NULL) 2230 sitd->u.frame_list.next->u.frame_list.prev = NULL; 2231 } else { 2232 /* XXX this part is untested... */ 2233 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2234 usb_syncmem(&sitd->dma, 2235 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2236 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2237 2238 prev->u.frame_list.next = sitd->u.frame_list.next; 2239 if (sitd->u.frame_list.next != NULL) 2240 sitd->u.frame_list.next->u.frame_list.prev = prev; 2241 } 2242 } 2243 2244 prev = NULL; 2245 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2246 if (prev != NULL) 2247 ehci_free_sitd(sc, prev); 2248 prev = sitd; 2249 } 2250 if (prev) 2251 ehci_free_sitd(sc, prev); 2252 exfer->ex_sitdstart = NULL; 2253 exfer->ex_sitdend = NULL; 2254 } 2255 2256 /***********/ 2257 2258 Static int 2259 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2260 void *buf, int buflen) 2261 { 2262 ehci_softc_t *sc = bus->ub_hcpriv; 2263 usb_hub_descriptor_t hubd; 2264 usb_port_status_t ps; 2265 uint16_t len, value, index; 2266 int l, totlen = 0; 2267 int port, i; 2268 uint32_t v; 2269 2270 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2271 2272 if (sc->sc_dying) 2273 return -1; 2274 2275 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2276 req->bmRequestType, req->bRequest, 0, 0); 2277 2278 len = UGETW(req->wLength); 2279 value = UGETW(req->wValue); 2280 index = UGETW(req->wIndex); 2281 2282 #define C(x,y) ((x) | ((y) << 8)) 2283 switch (C(req->bRequest, req->bmRequestType)) { 2284 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2285 if (len == 0) 2286 break; 2287 switch (value) { 2288 case C(0, UDESC_DEVICE): { 2289 usb_device_descriptor_t devd; 2290 totlen = min(buflen, sizeof(devd)); 2291 memcpy(&devd, buf, totlen); 2292 USETW(devd.idVendor, sc->sc_id_vendor); 2293 memcpy(buf, &devd, totlen); 2294 break; 2295 2296 } 2297 #define sd ((usb_string_descriptor_t *)buf) 2298 case C(1, UDESC_STRING): 2299 /* Vendor */ 2300 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2301 break; 2302 case C(2, UDESC_STRING): 2303 /* Product */ 2304 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2305 break; 2306 #undef sd 2307 default: 2308 /* default from usbroothub */ 2309 return buflen; 2310 } 2311 break; 2312 2313 /* Hub requests */ 2314 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2315 break; 2316 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2317 USBHIST_LOG(ehcidebug, 2318 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2319 0, 0); 2320 if (index < 1 || index > sc->sc_noport) { 2321 return -1; 2322 } 2323 port = EHCI_PORTSC(index); 2324 v = EOREAD4(sc, port); 2325 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2326 v &= ~EHCI_PS_CLEAR; 2327 switch (value) { 2328 case UHF_PORT_ENABLE: 2329 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2330 break; 2331 case UHF_PORT_SUSPEND: 2332 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2333 break; 2334 v &= ~EHCI_PS_SUSP; 2335 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2336 /* see USB2 spec ch. 7.1.7.7 */ 2337 usb_delay_ms(&sc->sc_bus, 20); 2338 EOWRITE4(sc, port, v); 2339 usb_delay_ms(&sc->sc_bus, 2); 2340 #ifdef DEBUG 2341 v = EOREAD4(sc, port); 2342 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2343 printf("ehci: resume failed: %x\n", v); 2344 #endif 2345 break; 2346 case UHF_PORT_POWER: 2347 if (sc->sc_hasppc) 2348 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2349 break; 2350 case UHF_PORT_TEST: 2351 USBHIST_LOG(ehcidebug, "clear port test " 2352 "%d", index, 0, 0, 0); 2353 break; 2354 case UHF_PORT_INDICATOR: 2355 USBHIST_LOG(ehcidebug, "clear port ind " 2356 "%d", index, 0, 0, 0); 2357 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2358 break; 2359 case UHF_C_PORT_CONNECTION: 2360 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2361 break; 2362 case UHF_C_PORT_ENABLE: 2363 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2364 break; 2365 case UHF_C_PORT_SUSPEND: 2366 /* how? */ 2367 break; 2368 case UHF_C_PORT_OVER_CURRENT: 2369 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2370 break; 2371 case UHF_C_PORT_RESET: 2372 sc->sc_isreset[index] = 0; 2373 break; 2374 default: 2375 return -1; 2376 } 2377 #if 0 2378 switch(value) { 2379 case UHF_C_PORT_CONNECTION: 2380 case UHF_C_PORT_ENABLE: 2381 case UHF_C_PORT_SUSPEND: 2382 case UHF_C_PORT_OVER_CURRENT: 2383 case UHF_C_PORT_RESET: 2384 default: 2385 break; 2386 } 2387 #endif 2388 break; 2389 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2390 if (len == 0) 2391 break; 2392 if ((value & 0xff) != 0) { 2393 return -1; 2394 } 2395 totlen = min(buflen, sizeof(hubd)); 2396 memcpy(&hubd, buf, totlen); 2397 hubd.bNbrPorts = sc->sc_noport; 2398 v = EOREAD4(sc, EHCI_HCSPARAMS); 2399 USETW(hubd.wHubCharacteristics, 2400 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2401 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2402 ? UHD_PORT_IND : 0); 2403 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2404 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2405 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2406 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2407 totlen = min(totlen, hubd.bDescLength); 2408 memcpy(buf, &hubd, totlen); 2409 break; 2410 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2411 if (len != 4) { 2412 return -1; 2413 } 2414 memset(buf, 0, len); /* ? XXX */ 2415 totlen = len; 2416 break; 2417 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2418 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2419 if (index < 1 || index > sc->sc_noport) { 2420 return -1; 2421 } 2422 if (len != 4) { 2423 return -1; 2424 } 2425 v = EOREAD4(sc, EHCI_PORTSC(index)); 2426 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2427 2428 i = UPS_HIGH_SPEED; 2429 if (sc->sc_flags & EHCIF_ETTF) { 2430 /* 2431 * If we are doing embedded transaction translation, 2432 * then directly attached LS/FS devices are reset by 2433 * the EHCI controller itself. PSPD is encoded 2434 * the same way as in USBSTATUS. 2435 */ 2436 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2437 } 2438 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2439 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2440 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2441 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2442 if (v & EHCI_PS_PR) i |= UPS_RESET; 2443 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2444 if (sc->sc_vendor_port_status) 2445 i = sc->sc_vendor_port_status(sc, v, i); 2446 USETW(ps.wPortStatus, i); 2447 i = 0; 2448 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2449 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2450 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2451 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2452 USETW(ps.wPortChange, i); 2453 totlen = min(len, sizeof(ps)); 2454 memcpy(buf, &ps, totlen); 2455 break; 2456 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2457 return -1; 2458 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2459 break; 2460 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2461 if (index < 1 || index > sc->sc_noport) { 2462 return -1; 2463 } 2464 port = EHCI_PORTSC(index); 2465 v = EOREAD4(sc, port); 2466 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2467 v &= ~EHCI_PS_CLEAR; 2468 switch(value) { 2469 case UHF_PORT_ENABLE: 2470 EOWRITE4(sc, port, v | EHCI_PS_PE); 2471 break; 2472 case UHF_PORT_SUSPEND: 2473 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2474 break; 2475 case UHF_PORT_RESET: 2476 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2477 if (EHCI_PS_IS_LOWSPEED(v) 2478 && sc->sc_ncomp > 0 2479 && !(sc->sc_flags & EHCIF_ETTF)) { 2480 /* 2481 * Low speed device on non-ETTF controller or 2482 * unaccompanied controller, give up ownership. 2483 */ 2484 ehci_disown(sc, index, 1); 2485 break; 2486 } 2487 /* Start reset sequence. */ 2488 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2489 EOWRITE4(sc, port, v | EHCI_PS_PR); 2490 /* Wait for reset to complete. */ 2491 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2492 if (sc->sc_dying) { 2493 return -1; 2494 } 2495 /* 2496 * An embedded transaction translator will automatically 2497 * terminate the reset sequence so there's no need to 2498 * it. 2499 */ 2500 v = EOREAD4(sc, port); 2501 if (v & EHCI_PS_PR) { 2502 /* Terminate reset sequence. */ 2503 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2504 /* Wait for HC to complete reset. */ 2505 usb_delay_ms(&sc->sc_bus, 2506 EHCI_PORT_RESET_COMPLETE); 2507 if (sc->sc_dying) { 2508 return -1; 2509 } 2510 } 2511 2512 v = EOREAD4(sc, port); 2513 USBHIST_LOG(ehcidebug, 2514 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2515 if (v & EHCI_PS_PR) { 2516 printf("%s: port reset timeout\n", 2517 device_xname(sc->sc_dev)); 2518 return USBD_TIMEOUT; 2519 } 2520 if (!(v & EHCI_PS_PE)) { 2521 /* Not a high speed device, give up ownership.*/ 2522 ehci_disown(sc, index, 0); 2523 break; 2524 } 2525 sc->sc_isreset[index] = 1; 2526 USBHIST_LOG(ehcidebug, 2527 "ehci port %d reset, status = 0x%08x", index, v, 0, 2528 0); 2529 break; 2530 case UHF_PORT_POWER: 2531 USBHIST_LOG(ehcidebug, 2532 "set port power %d (has PPC = %d)", index, 2533 sc->sc_hasppc, 0, 0); 2534 if (sc->sc_hasppc) 2535 EOWRITE4(sc, port, v | EHCI_PS_PP); 2536 break; 2537 case UHF_PORT_TEST: 2538 USBHIST_LOG(ehcidebug, "set port test %d", 2539 index, 0, 0, 0); 2540 break; 2541 case UHF_PORT_INDICATOR: 2542 USBHIST_LOG(ehcidebug, "set port ind %d", 2543 index, 0, 0, 0); 2544 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2545 break; 2546 default: 2547 return -1; 2548 } 2549 break; 2550 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2551 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2552 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2553 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2554 break; 2555 default: 2556 /* default from usbroothub */ 2557 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2558 buflen, 0, 0, 0); 2559 2560 return buflen; 2561 } 2562 2563 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2564 2565 return totlen; 2566 } 2567 2568 Static void 2569 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2570 { 2571 int port; 2572 uint32_t v; 2573 2574 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2575 2576 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2577 #ifdef DIAGNOSTIC 2578 if (sc->sc_npcomp != 0) { 2579 int i = (index-1) / sc->sc_npcomp; 2580 if (i >= sc->sc_ncomp) 2581 printf("%s: strange port\n", 2582 device_xname(sc->sc_dev)); 2583 else 2584 printf("%s: handing over %s speed device on " 2585 "port %d to %s\n", 2586 device_xname(sc->sc_dev), 2587 lowspeed ? "low" : "full", 2588 index, device_xname(sc->sc_comps[i])); 2589 } else { 2590 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2591 } 2592 #endif 2593 port = EHCI_PORTSC(index); 2594 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2595 EOWRITE4(sc, port, v | EHCI_PS_PO); 2596 } 2597 2598 Static usbd_status 2599 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2600 { 2601 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2602 usbd_status err; 2603 2604 /* Insert last in queue. */ 2605 mutex_enter(&sc->sc_lock); 2606 err = usb_insert_transfer(xfer); 2607 mutex_exit(&sc->sc_lock); 2608 if (err) 2609 return err; 2610 2611 /* Pipe isn't running, start first */ 2612 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2613 } 2614 2615 Static usbd_status 2616 ehci_root_intr_start(usbd_xfer_handle xfer) 2617 { 2618 usbd_pipe_handle pipe = xfer->ux_pipe; 2619 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2620 2621 if (sc->sc_dying) 2622 return USBD_IOERROR; 2623 2624 mutex_enter(&sc->sc_lock); 2625 sc->sc_intrxfer = xfer; 2626 mutex_exit(&sc->sc_lock); 2627 2628 return USBD_IN_PROGRESS; 2629 } 2630 2631 /* Abort a root interrupt request. */ 2632 Static void 2633 ehci_root_intr_abort(usbd_xfer_handle xfer) 2634 { 2635 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2636 2637 KASSERT(mutex_owned(&sc->sc_lock)); 2638 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2639 2640 sc->sc_intrxfer = NULL; 2641 2642 xfer->ux_status = USBD_CANCELLED; 2643 usb_transfer_complete(xfer); 2644 } 2645 2646 /* Close the root pipe. */ 2647 Static void 2648 ehci_root_intr_close(usbd_pipe_handle pipe) 2649 { 2650 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2651 2652 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2653 2654 KASSERT(mutex_owned(&sc->sc_lock)); 2655 2656 sc->sc_intrxfer = NULL; 2657 } 2658 2659 Static void 2660 ehci_root_intr_done(usbd_xfer_handle xfer) 2661 { 2662 xfer->ux_hcpriv = NULL; 2663 } 2664 2665 /************************/ 2666 2667 Static ehci_soft_qh_t * 2668 ehci_alloc_sqh(ehci_softc_t *sc) 2669 { 2670 ehci_soft_qh_t *sqh; 2671 usbd_status err; 2672 int i, offs; 2673 usb_dma_t dma; 2674 2675 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2676 2677 if (sc->sc_freeqhs == NULL) { 2678 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2679 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2680 EHCI_PAGE_SIZE, &dma); 2681 #ifdef EHCI_DEBUG 2682 if (err) 2683 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2684 #endif 2685 if (err) 2686 return NULL; 2687 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2688 offs = i * EHCI_SQH_SIZE; 2689 sqh = KERNADDR(&dma, offs); 2690 sqh->physaddr = DMAADDR(&dma, offs); 2691 sqh->dma = dma; 2692 sqh->offs = offs; 2693 sqh->next = sc->sc_freeqhs; 2694 sc->sc_freeqhs = sqh; 2695 } 2696 } 2697 sqh = sc->sc_freeqhs; 2698 sc->sc_freeqhs = sqh->next; 2699 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2700 sqh->next = NULL; 2701 return sqh; 2702 } 2703 2704 Static void 2705 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2706 { 2707 sqh->next = sc->sc_freeqhs; 2708 sc->sc_freeqhs = sqh; 2709 } 2710 2711 Static ehci_soft_qtd_t * 2712 ehci_alloc_sqtd(ehci_softc_t *sc) 2713 { 2714 ehci_soft_qtd_t *sqtd = NULL; 2715 usbd_status err; 2716 int i, offs; 2717 usb_dma_t dma; 2718 2719 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2720 2721 if (sc->sc_freeqtds == NULL) { 2722 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2723 2724 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2725 EHCI_PAGE_SIZE, &dma); 2726 #ifdef EHCI_DEBUG 2727 if (err) 2728 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2729 #endif 2730 if (err) 2731 goto done; 2732 2733 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2734 offs = i * EHCI_SQTD_SIZE; 2735 sqtd = KERNADDR(&dma, offs); 2736 sqtd->physaddr = DMAADDR(&dma, offs); 2737 sqtd->dma = dma; 2738 sqtd->offs = offs; 2739 2740 sqtd->nextqtd = sc->sc_freeqtds; 2741 sc->sc_freeqtds = sqtd; 2742 } 2743 } 2744 2745 sqtd = sc->sc_freeqtds; 2746 sc->sc_freeqtds = sqtd->nextqtd; 2747 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2748 sqtd->nextqtd = NULL; 2749 sqtd->xfer = NULL; 2750 2751 done: 2752 return sqtd; 2753 } 2754 2755 Static void 2756 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2757 { 2758 2759 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2760 2761 sqtd->nextqtd = sc->sc_freeqtds; 2762 sc->sc_freeqtds = sqtd; 2763 } 2764 2765 Static usbd_status 2766 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2767 int alen, int rd, usbd_xfer_handle xfer, 2768 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2769 { 2770 ehci_soft_qtd_t *next, *cur; 2771 ehci_physaddr_t nextphys; 2772 uint32_t qtdstatus; 2773 int len, curlen, mps; 2774 int i, tog; 2775 int pages, pageoffs; 2776 bus_size_t curoffs; 2777 vaddr_t va, va_offs; 2778 usb_dma_t *dma = &xfer->ux_dmabuf; 2779 uint16_t flags = xfer->ux_flags; 2780 paddr_t a; 2781 2782 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2783 2784 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2785 2786 len = alen; 2787 qtdstatus = EHCI_QTD_ACTIVE | 2788 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2789 EHCI_QTD_SET_CERR(3) 2790 /* IOC set below */ 2791 /* BYTES set below */ 2792 ; 2793 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 2794 tog = epipe->nexttoggle; 2795 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2796 2797 cur = ehci_alloc_sqtd(sc); 2798 *sp = cur; 2799 if (cur == NULL) 2800 goto nomem; 2801 2802 usb_syncmem(dma, 0, alen, 2803 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2804 curoffs = 0; 2805 for (;;) { 2806 /* The EHCI hardware can handle at most 5 pages. */ 2807 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2808 va_offs = EHCI_PAGE_OFFSET(va_offs); 2809 if (len-curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2810 /* we can handle it in this QTD */ 2811 curlen = len - curoffs; 2812 } else { 2813 /* must use multiple TDs, fill as much as possible. */ 2814 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2815 2816 /* the length must be a multiple of the max size */ 2817 curlen -= curlen % mps; 2818 USBHIST_LOG(ehcidebug, "multiple QTDs, " 2819 "curlen=%d", curlen, 0, 0, 0); 2820 KASSERT(curlen != 0); 2821 } 2822 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 2823 len, curlen, (size_t)curoffs, 0); 2824 2825 /* 2826 * Allocate another transfer if there's more data left, 2827 * or if force last short transfer flag is set and we're 2828 * allocating a multiple of the max packet size. 2829 */ 2830 2831 if (curoffs + curlen != len || 2832 ((curlen % mps) == 0 && !rd && curlen != 0 && 2833 (flags & USBD_FORCE_SHORT_XFER))) { 2834 next = ehci_alloc_sqtd(sc); 2835 if (next == NULL) 2836 goto nomem; 2837 nextphys = htole32(next->physaddr); 2838 } else { 2839 next = NULL; 2840 nextphys = EHCI_NULL; 2841 } 2842 2843 /* Find number of pages we'll be using, insert dma addresses */ 2844 pages = EHCI_PAGE(curlen + EHCI_PAGE_SIZE -1) >> 12; 2845 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2846 pageoffs = EHCI_PAGE(curoffs); 2847 for (i = 0; i < pages; i++) { 2848 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2849 cur->qtd.qtd_buffer[i] = htole32(a & 0xFFFFF000); 2850 /* Cast up to avoid compiler warnings */ 2851 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2852 } 2853 2854 /* First buffer pointer requires a page offset to start at */ 2855 va = (vaddr_t)KERNADDR(dma, curoffs); 2856 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2857 2858 cur->nextqtd = next; 2859 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2860 cur->qtd.qtd_status = 2861 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2862 cur->xfer = xfer; 2863 cur->len = curlen; 2864 2865 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2866 (size_t)curoffs, (size_t)(curoffs + curlen), 0, 0); 2867 2868 /* 2869 * adjust the toggle based on the number of packets in this 2870 * qtd 2871 */ 2872 if (((curlen + mps - 1) / mps) & 1) { 2873 tog ^= 1; 2874 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2875 } 2876 if (next == NULL) 2877 break; 2878 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2879 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2880 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2881 if (len) 2882 curoffs += curlen; 2883 cur = next; 2884 } 2885 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2886 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2887 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2888 *ep = cur; 2889 epipe->nexttoggle = tog; 2890 2891 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 2892 *sp, *ep, 0, 0); 2893 2894 return USBD_NORMAL_COMPLETION; 2895 2896 nomem: 2897 /* XXX free chain */ 2898 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2899 return USBD_NOMEM; 2900 } 2901 2902 Static void 2903 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2904 ehci_soft_qtd_t *sqtdend) 2905 { 2906 ehci_soft_qtd_t *p; 2907 int i; 2908 2909 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2910 2911 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 2912 sqtd, sqtdend, 0, 0); 2913 2914 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2915 p = sqtd->nextqtd; 2916 ehci_free_sqtd(sc, sqtd); 2917 } 2918 } 2919 2920 Static ehci_soft_itd_t * 2921 ehci_alloc_itd(ehci_softc_t *sc) 2922 { 2923 struct ehci_soft_itd *itd, *freeitd; 2924 usbd_status err; 2925 int i, offs, frindex, previndex; 2926 usb_dma_t dma; 2927 2928 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2929 2930 mutex_enter(&sc->sc_lock); 2931 2932 /* 2933 * Find an itd that wasn't freed this frame or last frame. This can 2934 * discard itds that were freed before frindex wrapped around 2935 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2936 * interrupt and fiddling with list when that happens 2937 */ 2938 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2939 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2940 2941 freeitd = NULL; 2942 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2943 if (itd == NULL) 2944 break; 2945 if (itd->slot != frindex && itd->slot != previndex) { 2946 freeitd = itd; 2947 break; 2948 } 2949 } 2950 2951 if (freeitd == NULL) { 2952 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2953 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2954 EHCI_PAGE_SIZE, &dma); 2955 2956 if (err) { 2957 USBHIST_LOG(ehcidebug, 2958 "alloc returned %d", err, 0, 0, 0); 2959 mutex_exit(&sc->sc_lock); 2960 return NULL; 2961 } 2962 2963 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2964 offs = i * EHCI_ITD_SIZE; 2965 itd = KERNADDR(&dma, offs); 2966 itd->physaddr = DMAADDR(&dma, offs); 2967 itd->dma = dma; 2968 itd->offs = offs; 2969 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2970 } 2971 freeitd = LIST_FIRST(&sc->sc_freeitds); 2972 } 2973 2974 itd = freeitd; 2975 LIST_REMOVE(itd, u.free_list); 2976 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2977 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2978 sizeof(itd->itd.itd_next), 2979 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2980 2981 itd->u.frame_list.next = NULL; 2982 itd->u.frame_list.prev = NULL; 2983 itd->xfer_next = NULL; 2984 itd->slot = 0; 2985 2986 mutex_exit(&sc->sc_lock); 2987 2988 return itd; 2989 } 2990 2991 Static ehci_soft_sitd_t * 2992 ehci_alloc_sitd(ehci_softc_t *sc) 2993 { 2994 struct ehci_soft_sitd *sitd, *freesitd; 2995 usbd_status err; 2996 int i, offs, frindex, previndex; 2997 usb_dma_t dma; 2998 2999 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3000 3001 mutex_enter(&sc->sc_lock); 3002 3003 /* 3004 * Find an sitd that wasn't freed this frame or last frame. This can 3005 * discard sitds that were freed before frindex wrapped around 3006 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3007 * interrupt and fiddling with list when that happens 3008 */ 3009 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3010 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3011 3012 freesitd = NULL; 3013 LIST_FOREACH(sitd, &sc->sc_freesitds, u.free_list) { 3014 if (sitd == NULL) 3015 break; 3016 if (sitd->slot != frindex && sitd->slot != previndex) { 3017 freesitd = sitd; 3018 break; 3019 } 3020 } 3021 3022 if (freesitd == NULL) { 3023 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3024 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3025 EHCI_PAGE_SIZE, &dma); 3026 3027 if (err) { 3028 USBHIST_LOG(ehcidebug, 3029 "alloc returned %d", err, 0, 0, 0); 3030 mutex_exit(&sc->sc_lock); 3031 return NULL; 3032 } 3033 3034 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3035 offs = i * EHCI_SITD_SIZE; 3036 sitd = KERNADDR(&dma, offs); 3037 sitd->physaddr = DMAADDR(&dma, offs); 3038 sitd->dma = dma; 3039 sitd->offs = offs; 3040 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3041 } 3042 freesitd = LIST_FIRST(&sc->sc_freesitds); 3043 } 3044 3045 sitd = freesitd; 3046 LIST_REMOVE(sitd, u.free_list); 3047 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3048 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3049 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3050 BUS_DMASYNC_PREREAD); 3051 3052 sitd->u.frame_list.next = NULL; 3053 sitd->u.frame_list.prev = NULL; 3054 sitd->xfer_next = NULL; 3055 sitd->slot = 0; 3056 3057 mutex_exit(&sc->sc_lock); 3058 3059 return sitd; 3060 } 3061 3062 Static void 3063 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3064 { 3065 3066 KASSERT(mutex_owned(&sc->sc_lock)); 3067 3068 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3069 } 3070 3071 Static void 3072 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3073 { 3074 3075 KASSERT(mutex_owned(&sc->sc_lock)); 3076 3077 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3078 } 3079 3080 /****************/ 3081 3082 /* 3083 * Close a reqular pipe. 3084 * Assumes that there are no pending transactions. 3085 */ 3086 Static void 3087 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3088 { 3089 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3090 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3091 ehci_soft_qh_t *sqh = epipe->sqh; 3092 3093 KASSERT(mutex_owned(&sc->sc_lock)); 3094 3095 ehci_rem_qh(sc, sqh, head); 3096 ehci_free_sqh(sc, epipe->sqh); 3097 } 3098 3099 /* 3100 * Abort a device request. 3101 * If this routine is called at splusb() it guarantees that the request 3102 * will be removed from the hardware scheduling and that the callback 3103 * for it will be called with USBD_CANCELLED status. 3104 * It's impossible to guarantee that the requested transfer will not 3105 * have happened since the hardware runs concurrently. 3106 * If the transaction has already happened we rely on the ordinary 3107 * interrupt processing to process it. 3108 * XXX This is most probably wrong. 3109 * XXXMRG this doesn't make sense anymore. 3110 */ 3111 Static void 3112 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3113 { 3114 #define exfer EXFER(xfer) 3115 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3116 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3117 ehci_soft_qh_t *sqh = epipe->sqh; 3118 ehci_soft_qtd_t *sqtd; 3119 ehci_physaddr_t cur; 3120 uint32_t qhstatus; 3121 int hit; 3122 int wake; 3123 3124 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3125 3126 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3127 3128 KASSERT(mutex_owned(&sc->sc_lock)); 3129 ASSERT_SLEEPABLE(); 3130 3131 if (sc->sc_dying) { 3132 /* If we're dying, just do the software part. */ 3133 xfer->ux_status = status; /* make software ignore it */ 3134 callout_stop(&xfer->ux_callout); 3135 usb_transfer_complete(xfer); 3136 return; 3137 } 3138 3139 /* 3140 * If an abort is already in progress then just wait for it to 3141 * complete and return. 3142 */ 3143 if (xfer->ux_hcflags & UXFER_ABORTING) { 3144 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3145 #ifdef DIAGNOSTIC 3146 if (status == USBD_TIMEOUT) 3147 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3148 #endif 3149 /* Override the status which might be USBD_TIMEOUT. */ 3150 xfer->ux_status = status; 3151 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3152 0, 0, 0, 0); 3153 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3154 while (xfer->ux_hcflags & UXFER_ABORTING) 3155 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3156 return; 3157 } 3158 xfer->ux_hcflags |= UXFER_ABORTING; 3159 3160 /* 3161 * Step 1: Make interrupt routine and hardware ignore xfer. 3162 */ 3163 xfer->ux_status = status; /* make software ignore it */ 3164 callout_stop(&xfer->ux_callout); 3165 3166 usb_syncmem(&sqh->dma, 3167 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3168 sizeof(sqh->qh.qh_qtd.qtd_status), 3169 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3170 qhstatus = sqh->qh.qh_qtd.qtd_status; 3171 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3172 usb_syncmem(&sqh->dma, 3173 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3174 sizeof(sqh->qh.qh_qtd.qtd_status), 3175 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3176 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3177 usb_syncmem(&sqtd->dma, 3178 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3179 sizeof(sqtd->qtd.qtd_status), 3180 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3181 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3182 usb_syncmem(&sqtd->dma, 3183 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3184 sizeof(sqtd->qtd.qtd_status), 3185 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3186 if (sqtd == exfer->ex_sqtdend) 3187 break; 3188 } 3189 3190 /* 3191 * Step 2: Wait until we know hardware has finished any possible 3192 * use of the xfer. Also make sure the soft interrupt routine 3193 * has run. 3194 */ 3195 ehci_sync_hc(sc); 3196 sc->sc_softwake = 1; 3197 usb_schedsoftintr(&sc->sc_bus); 3198 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3199 3200 /* 3201 * Step 3: Remove any vestiges of the xfer from the hardware. 3202 * The complication here is that the hardware may have executed 3203 * beyond the xfer we're trying to abort. So as we're scanning 3204 * the TDs of this xfer we check if the hardware points to 3205 * any of them. 3206 */ 3207 3208 usb_syncmem(&sqh->dma, 3209 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3210 sizeof(sqh->qh.qh_curqtd), 3211 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3212 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3213 hit = 0; 3214 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3215 hit |= cur == sqtd->physaddr; 3216 if (sqtd == exfer->ex_sqtdend) 3217 break; 3218 } 3219 sqtd = sqtd->nextqtd; 3220 /* Zap curqtd register if hardware pointed inside the xfer. */ 3221 if (hit && sqtd != NULL) { 3222 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3223 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3224 usb_syncmem(&sqh->dma, 3225 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3226 sizeof(sqh->qh.qh_curqtd), 3227 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3228 sqh->qh.qh_qtd.qtd_status = qhstatus; 3229 usb_syncmem(&sqh->dma, 3230 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3231 sizeof(sqh->qh.qh_qtd.qtd_status), 3232 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3233 } else { 3234 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3235 } 3236 3237 /* 3238 * Step 4: Execute callback. 3239 */ 3240 #ifdef DIAGNOSTIC 3241 exfer->ex_isdone = 1; 3242 #endif 3243 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3244 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3245 usb_transfer_complete(xfer); 3246 if (wake) { 3247 cv_broadcast(&xfer->ux_hccv); 3248 } 3249 3250 KASSERT(mutex_owned(&sc->sc_lock)); 3251 #undef exfer 3252 } 3253 3254 Static void 3255 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3256 { 3257 ehci_isoc_trans_t trans_status; 3258 struct ehci_pipe *epipe; 3259 struct ehci_xfer *exfer; 3260 ehci_softc_t *sc; 3261 struct ehci_soft_itd *itd; 3262 struct ehci_soft_sitd *sitd; 3263 int i, wake; 3264 3265 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3266 3267 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3268 exfer = EXFER(xfer); 3269 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3270 3271 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3272 3273 KASSERT(mutex_owned(&sc->sc_lock)); 3274 3275 if (sc->sc_dying) { 3276 xfer->ux_status = status; 3277 callout_stop(&xfer->ux_callout); 3278 usb_transfer_complete(xfer); 3279 return; 3280 } 3281 3282 if (xfer->ux_hcflags & UXFER_ABORTING) { 3283 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3284 3285 #ifdef DIAGNOSTIC 3286 if (status == USBD_TIMEOUT) 3287 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3288 #endif 3289 3290 xfer->ux_status = status; 3291 USBHIST_LOG(ehcidebug, 3292 "waiting for abort to finish", 0, 0, 0, 0); 3293 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3294 while (xfer->ux_hcflags & UXFER_ABORTING) 3295 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3296 goto done; 3297 } 3298 xfer->ux_hcflags |= UXFER_ABORTING; 3299 3300 xfer->ux_status = status; 3301 callout_stop(&xfer->ux_callout); 3302 3303 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3304 for (itd = exfer->ex_itdstart; itd != NULL; 3305 itd = itd->xfer_next) { 3306 usb_syncmem(&itd->dma, 3307 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3308 sizeof(itd->itd.itd_ctl), 3309 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3310 3311 for (i = 0; i < 8; i++) { 3312 trans_status = le32toh(itd->itd.itd_ctl[i]); 3313 trans_status &= ~EHCI_ITD_ACTIVE; 3314 itd->itd.itd_ctl[i] = htole32(trans_status); 3315 } 3316 3317 usb_syncmem(&itd->dma, 3318 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3319 sizeof(itd->itd.itd_ctl), 3320 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3321 } 3322 } else { 3323 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3324 sitd = sitd->xfer_next) { 3325 usb_syncmem(&sitd->dma, 3326 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3327 sizeof(sitd->sitd.sitd_buffer), 3328 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3329 3330 trans_status = le32toh(sitd->sitd.sitd_trans); 3331 trans_status &= ~EHCI_SITD_ACTIVE; 3332 sitd->sitd.sitd_trans = htole32(trans_status); 3333 3334 usb_syncmem(&sitd->dma, 3335 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3336 sizeof(sitd->sitd.sitd_buffer), 3337 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3338 } 3339 } 3340 3341 sc->sc_softwake = 1; 3342 usb_schedsoftintr(&sc->sc_bus); 3343 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3344 3345 #ifdef DIAGNOSTIC 3346 exfer->ex_isdone = 1; 3347 #endif 3348 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3349 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3350 usb_transfer_complete(xfer); 3351 if (wake) { 3352 cv_broadcast(&xfer->ux_hccv); 3353 } 3354 3355 done: 3356 KASSERT(mutex_owned(&sc->sc_lock)); 3357 return; 3358 } 3359 3360 Static void 3361 ehci_timeout(void *addr) 3362 { 3363 struct ehci_xfer *exfer = addr; 3364 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->ex_xfer.ux_pipe; 3365 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3366 3367 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3368 3369 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3370 #ifdef EHCI_DEBUG 3371 if (ehcidebug > 1) 3372 usbd_dump_pipe(exfer->ex_xfer.ux_pipe); 3373 #endif 3374 3375 if (sc->sc_dying) { 3376 mutex_enter(&sc->sc_lock); 3377 ehci_abort_xfer(&exfer->ex_xfer, USBD_TIMEOUT); 3378 mutex_exit(&sc->sc_lock); 3379 return; 3380 } 3381 3382 /* Execute the abort in a process context. */ 3383 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, addr, 3384 USB_TASKQ_MPSAFE); 3385 usb_add_task(exfer->ex_xfer.ux_pipe->up_dev, &exfer->ex_aborttask, 3386 USB_TASKQ_HC); 3387 } 3388 3389 Static void 3390 ehci_timeout_task(void *addr) 3391 { 3392 usbd_xfer_handle xfer = addr; 3393 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3394 3395 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3396 3397 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3398 3399 mutex_enter(&sc->sc_lock); 3400 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3401 mutex_exit(&sc->sc_lock); 3402 } 3403 3404 /************************/ 3405 3406 Static usbd_status 3407 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3408 { 3409 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3410 usbd_status err; 3411 3412 /* Insert last in queue. */ 3413 mutex_enter(&sc->sc_lock); 3414 err = usb_insert_transfer(xfer); 3415 mutex_exit(&sc->sc_lock); 3416 if (err) 3417 return err; 3418 3419 /* Pipe isn't running, start first */ 3420 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3421 } 3422 3423 Static usbd_status 3424 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3425 { 3426 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3427 usbd_status err; 3428 3429 if (sc->sc_dying) 3430 return USBD_IOERROR; 3431 3432 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3433 3434 err = ehci_device_request(xfer); 3435 if (err) { 3436 return err; 3437 } 3438 3439 if (sc->sc_bus.ub_usepolling) 3440 ehci_waitintr(sc, xfer); 3441 3442 return USBD_IN_PROGRESS; 3443 } 3444 3445 Static void 3446 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3447 { 3448 struct ehci_xfer *ex = EXFER(xfer); 3449 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3450 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3451 usb_device_request_t *req = &xfer->ux_request; 3452 int len = UGETW(req->wLength); 3453 int rd = req->bmRequestType & UT_READ; 3454 3455 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3456 3457 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3458 3459 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3460 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3461 3462 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3463 ehci_del_intr_list(sc, ex); /* remove from active list */ 3464 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3465 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof(*req), 3466 BUS_DMASYNC_POSTWRITE); 3467 if (len) 3468 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3469 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3470 } 3471 3472 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3473 } 3474 3475 /* Abort a device control request. */ 3476 Static void 3477 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3478 { 3479 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3480 3481 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3482 ehci_abort_xfer(xfer, USBD_CANCELLED); 3483 } 3484 3485 /* Close a device control pipe. */ 3486 Static void 3487 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3488 { 3489 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3490 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3491 3492 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3493 3494 KASSERT(mutex_owned(&sc->sc_lock)); 3495 3496 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3497 3498 ehci_close_pipe(pipe, sc->sc_async_head); 3499 } 3500 3501 Static usbd_status 3502 ehci_device_request(usbd_xfer_handle xfer) 3503 { 3504 #define exfer EXFER(xfer) 3505 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3506 usb_device_request_t *req = &xfer->ux_request; 3507 usbd_device_handle dev = epipe->pipe.up_dev; 3508 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3509 ehci_soft_qtd_t *setup, *stat, *next; 3510 ehci_soft_qh_t *sqh; 3511 int isread; 3512 int len; 3513 usbd_status err; 3514 3515 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3516 3517 isread = req->bmRequestType & UT_READ; 3518 len = UGETW(req->wLength); 3519 3520 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3521 "wValue=0x%04x, wIndex=0x%04x", 3522 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3523 UGETW(req->wIndex)); 3524 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3525 len, dev->ud_addr, 3526 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3527 3528 setup = ehci_alloc_sqtd(sc); 3529 if (setup == NULL) { 3530 err = USBD_NOMEM; 3531 goto bad1; 3532 } 3533 stat = ehci_alloc_sqtd(sc); 3534 if (stat == NULL) { 3535 err = USBD_NOMEM; 3536 goto bad2; 3537 } 3538 3539 mutex_enter(&sc->sc_lock); 3540 3541 sqh = epipe->sqh; 3542 3543 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3544 "address QH %d pipe %d\n", 3545 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3546 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3547 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3548 "MPS QH %d pipe %d\n", 3549 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3550 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3551 3552 /* Set up data transaction */ 3553 if (len != 0) { 3554 ehci_soft_qtd_t *end; 3555 3556 /* Start toggle at 1. */ 3557 epipe->nexttoggle = 1; 3558 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3559 &next, &end); 3560 if (err) 3561 goto bad3; 3562 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3563 end->nextqtd = stat; 3564 end->qtd.qtd_next = end->qtd.qtd_altnext = 3565 htole32(stat->physaddr); 3566 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3567 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3568 } else { 3569 next = stat; 3570 } 3571 3572 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 3573 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3574 3575 /* Clear toggle */ 3576 setup->qtd.qtd_status = htole32( 3577 EHCI_QTD_ACTIVE | 3578 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3579 EHCI_QTD_SET_CERR(3) | 3580 EHCI_QTD_SET_TOGGLE(0) | 3581 EHCI_QTD_SET_BYTES(sizeof(*req)) 3582 ); 3583 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3584 setup->qtd.qtd_buffer_hi[0] = 0; 3585 setup->nextqtd = next; 3586 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3587 setup->xfer = xfer; 3588 setup->len = sizeof(*req); 3589 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3590 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3591 3592 stat->qtd.qtd_status = htole32( 3593 EHCI_QTD_ACTIVE | 3594 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3595 EHCI_QTD_SET_CERR(3) | 3596 EHCI_QTD_SET_TOGGLE(1) | 3597 EHCI_QTD_IOC 3598 ); 3599 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3600 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3601 stat->nextqtd = NULL; 3602 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3603 stat->xfer = xfer; 3604 stat->len = 0; 3605 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3606 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3607 3608 #ifdef EHCI_DEBUG 3609 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3610 ehci_dump_sqh(sqh); 3611 ehci_dump_sqtds(setup); 3612 #endif 3613 3614 exfer->ex_sqtdstart = setup; 3615 exfer->ex_sqtdend = stat; 3616 #ifdef DIAGNOSTIC 3617 if (!exfer->ex_isdone) { 3618 printf("ehci_device_request: not done, exfer=%p\n", exfer); 3619 } 3620 exfer->ex_isdone = 0; 3621 #endif 3622 3623 /* Insert qTD in QH list. */ 3624 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3625 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3626 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3627 ehci_timeout, xfer); 3628 } 3629 ehci_add_intr_list(sc, exfer); 3630 xfer->ux_status = USBD_IN_PROGRESS; 3631 mutex_exit(&sc->sc_lock); 3632 3633 #ifdef EHCI_DEBUG 3634 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3635 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3636 // delay(10000); 3637 ehci_dump_regs(sc); 3638 ehci_dump_sqh(sc->sc_async_head); 3639 ehci_dump_sqh(sqh); 3640 ehci_dump_sqtds(setup); 3641 #endif 3642 3643 return USBD_NORMAL_COMPLETION; 3644 3645 bad3: 3646 mutex_exit(&sc->sc_lock); 3647 ehci_free_sqtd(sc, stat); 3648 bad2: 3649 ehci_free_sqtd(sc, setup); 3650 bad1: 3651 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3652 mutex_enter(&sc->sc_lock); 3653 xfer->ux_status = err; 3654 usb_transfer_complete(xfer); 3655 mutex_exit(&sc->sc_lock); 3656 return err; 3657 #undef exfer 3658 } 3659 3660 /* 3661 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3662 * qTD status, or miss signalling occasionally under heavy load. If the host 3663 * machine is too fast, we we can miss transaction completion - when we scan 3664 * the active list the transaction still seems to be active. This generally 3665 * exhibits itself as a umass stall that never recovers. 3666 * 3667 * We work around this behaviour by setting up this callback after any softintr 3668 * that completes with transactions still pending, giving us another chance to 3669 * check for completion after the writeback has taken place. 3670 */ 3671 Static void 3672 ehci_intrlist_timeout(void *arg) 3673 { 3674 ehci_softc_t *sc = arg; 3675 3676 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3677 3678 usb_schedsoftintr(&sc->sc_bus); 3679 } 3680 3681 /************************/ 3682 3683 Static usbd_status 3684 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3685 { 3686 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3687 usbd_status err; 3688 3689 /* Insert last in queue. */ 3690 mutex_enter(&sc->sc_lock); 3691 err = usb_insert_transfer(xfer); 3692 mutex_exit(&sc->sc_lock); 3693 if (err) 3694 return err; 3695 3696 /* Pipe isn't running, start first */ 3697 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3698 } 3699 3700 Static usbd_status 3701 ehci_device_bulk_start(usbd_xfer_handle xfer) 3702 { 3703 #define exfer EXFER(xfer) 3704 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3705 usbd_device_handle dev = epipe->pipe.up_dev; 3706 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3707 ehci_soft_qtd_t *data, *dataend; 3708 ehci_soft_qh_t *sqh; 3709 usbd_status err; 3710 int len, isread, endpt; 3711 3712 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3713 3714 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3715 xfer, xfer->ux_length, xfer->ux_flags, 0); 3716 3717 if (sc->sc_dying) 3718 return USBD_IOERROR; 3719 3720 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3721 3722 mutex_enter(&sc->sc_lock); 3723 3724 len = xfer->ux_length; 3725 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3726 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3727 sqh = epipe->sqh; 3728 3729 epipe->u.bulk.length = len; 3730 3731 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3732 &dataend); 3733 if (err) { 3734 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3735 xfer->ux_status = err; 3736 usb_transfer_complete(xfer); 3737 mutex_exit(&sc->sc_lock); 3738 return err; 3739 } 3740 3741 #ifdef EHCI_DEBUG 3742 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3743 ehci_dump_sqh(sqh); 3744 ehci_dump_sqtds(data); 3745 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3746 #endif 3747 3748 /* Set up interrupt info. */ 3749 exfer->ex_sqtdstart = data; 3750 exfer->ex_sqtdend = dataend; 3751 #ifdef DIAGNOSTIC 3752 if (!exfer->ex_isdone) { 3753 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer); 3754 } 3755 exfer->ex_isdone = 0; 3756 #endif 3757 3758 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3759 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3760 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3761 ehci_timeout, xfer); 3762 } 3763 ehci_add_intr_list(sc, exfer); 3764 xfer->ux_status = USBD_IN_PROGRESS; 3765 mutex_exit(&sc->sc_lock); 3766 3767 #ifdef EHCI_DEBUG 3768 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3769 // delay(10000); 3770 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3771 ehci_dump_regs(sc); 3772 #if 0 3773 printf("async_head:\n"); 3774 ehci_dump_sqh(sc->sc_async_head); 3775 #endif 3776 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3777 ehci_dump_sqh(sqh); 3778 ehci_dump_sqtds(data); 3779 #endif 3780 3781 if (sc->sc_bus.ub_usepolling) 3782 ehci_waitintr(sc, xfer); 3783 3784 return USBD_IN_PROGRESS; 3785 #undef exfer 3786 } 3787 3788 Static void 3789 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3790 { 3791 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3792 3793 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3794 ehci_abort_xfer(xfer, USBD_CANCELLED); 3795 } 3796 3797 /* 3798 * Close a device bulk pipe. 3799 */ 3800 Static void 3801 ehci_device_bulk_close(usbd_pipe_handle pipe) 3802 { 3803 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3804 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3805 3806 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3807 3808 KASSERT(mutex_owned(&sc->sc_lock)); 3809 3810 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3811 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3812 ehci_close_pipe(pipe, sc->sc_async_head); 3813 } 3814 3815 Static void 3816 ehci_device_bulk_done(usbd_xfer_handle xfer) 3817 { 3818 struct ehci_xfer *ex = EXFER(xfer); 3819 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3820 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3821 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3822 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3823 3824 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3825 3826 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3827 xfer, xfer->ux_actlen, 0, 0); 3828 3829 KASSERT(mutex_owned(&sc->sc_lock)); 3830 3831 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3832 ehci_del_intr_list(sc, ex); /* remove from active list */ 3833 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3834 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3835 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3836 } 3837 3838 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3839 } 3840 3841 /************************/ 3842 3843 Static usbd_status 3844 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3845 { 3846 struct ehci_soft_islot *isp; 3847 int islot, lev; 3848 3849 /* Find a poll rate that is large enough. */ 3850 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3851 if (EHCI_ILEV_IVAL(lev) <= ival) 3852 break; 3853 3854 /* Pick an interrupt slot at the right level. */ 3855 /* XXX could do better than picking at random */ 3856 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3857 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3858 3859 sqh->islot = islot; 3860 isp = &sc->sc_islots[islot]; 3861 mutex_enter(&sc->sc_lock); 3862 ehci_add_qh(sc, sqh, isp->sqh); 3863 mutex_exit(&sc->sc_lock); 3864 3865 return USBD_NORMAL_COMPLETION; 3866 } 3867 3868 Static usbd_status 3869 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3870 { 3871 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3872 usbd_status err; 3873 3874 /* Insert last in queue. */ 3875 mutex_enter(&sc->sc_lock); 3876 err = usb_insert_transfer(xfer); 3877 mutex_exit(&sc->sc_lock); 3878 if (err) 3879 return err; 3880 3881 /* 3882 * Pipe isn't running (otherwise err would be USBD_INPROG), 3883 * so start it first. 3884 */ 3885 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3886 } 3887 3888 Static usbd_status 3889 ehci_device_intr_start(usbd_xfer_handle xfer) 3890 { 3891 #define exfer EXFER(xfer) 3892 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3893 usbd_device_handle dev = xfer->ux_pipe->up_dev; 3894 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3895 ehci_soft_qtd_t *data, *dataend; 3896 ehci_soft_qh_t *sqh; 3897 usbd_status err; 3898 int len, isread, endpt; 3899 3900 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3901 3902 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3903 xfer, xfer->ux_length, xfer->ux_flags, 0); 3904 3905 if (sc->sc_dying) 3906 return USBD_IOERROR; 3907 3908 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3909 3910 mutex_enter(&sc->sc_lock); 3911 3912 len = xfer->ux_length; 3913 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3914 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3915 sqh = epipe->sqh; 3916 3917 epipe->u.intr.length = len; 3918 3919 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3920 &dataend); 3921 if (err) { 3922 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3923 xfer->ux_status = err; 3924 usb_transfer_complete(xfer); 3925 mutex_exit(&sc->sc_lock); 3926 return err; 3927 } 3928 3929 #ifdef EHCI_DEBUG 3930 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3931 ehci_dump_sqh(sqh); 3932 ehci_dump_sqtds(data); 3933 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3934 #endif 3935 3936 /* Set up interrupt info. */ 3937 exfer->ex_sqtdstart = data; 3938 exfer->ex_sqtdend = dataend; 3939 #ifdef DIAGNOSTIC 3940 if (!exfer->ex_isdone) { 3941 printf("ehci_device_intr_start: not done, ex=%p\n", exfer); 3942 } 3943 exfer->ex_isdone = 0; 3944 #endif 3945 3946 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3947 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3948 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3949 ehci_timeout, xfer); 3950 } 3951 ehci_add_intr_list(sc, exfer); 3952 xfer->ux_status = USBD_IN_PROGRESS; 3953 mutex_exit(&sc->sc_lock); 3954 3955 #ifdef EHCI_DEBUG 3956 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3957 // delay(10000); 3958 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3959 ehci_dump_regs(sc); 3960 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3961 ehci_dump_sqh(sqh); 3962 ehci_dump_sqtds(data); 3963 #endif 3964 3965 if (sc->sc_bus.ub_usepolling) 3966 ehci_waitintr(sc, xfer); 3967 3968 return USBD_IN_PROGRESS; 3969 #undef exfer 3970 } 3971 3972 Static void 3973 ehci_device_intr_abort(usbd_xfer_handle xfer) 3974 { 3975 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3976 3977 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3978 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3979 3980 /* 3981 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3982 * async doorbell. That's dependent on the async list, wheras 3983 * intr xfers are periodic, should not use this? 3984 */ 3985 ehci_abort_xfer(xfer, USBD_CANCELLED); 3986 } 3987 3988 Static void 3989 ehci_device_intr_close(usbd_pipe_handle pipe) 3990 { 3991 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3992 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3993 struct ehci_soft_islot *isp; 3994 3995 KASSERT(mutex_owned(&sc->sc_lock)); 3996 3997 isp = &sc->sc_islots[epipe->sqh->islot]; 3998 ehci_close_pipe(pipe, isp->sqh); 3999 } 4000 4001 Static void 4002 ehci_device_intr_done(usbd_xfer_handle xfer) 4003 { 4004 #define exfer EXFER(xfer) 4005 struct ehci_xfer *ex = EXFER(xfer); 4006 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4007 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 4008 ehci_soft_qtd_t *data, *dataend; 4009 ehci_soft_qh_t *sqh; 4010 usbd_status err; 4011 int len, isread, endpt; 4012 4013 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4014 4015 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4016 xfer, xfer->ux_actlen, 0, 0); 4017 4018 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4019 4020 if (xfer->ux_pipe->up_repeat) { 4021 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 4022 4023 len = epipe->u.intr.length; 4024 xfer->ux_length = len; 4025 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4026 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4027 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4028 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4029 sqh = epipe->sqh; 4030 4031 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4032 &data, &dataend); 4033 if (err) { 4034 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4035 xfer->ux_status = err; 4036 return; 4037 } 4038 4039 /* Set up interrupt info. */ 4040 exfer->ex_sqtdstart = data; 4041 exfer->ex_sqtdend = dataend; 4042 #ifdef DIAGNOSTIC 4043 if (!exfer->ex_isdone) { 4044 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", 4045 exfer, 0, 0, 0); 4046 printf("ehci_device_intr_done: not done, ex=%p\n", 4047 exfer); 4048 } 4049 exfer->ex_isdone = 0; 4050 #endif 4051 4052 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4053 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4054 callout_reset(&xfer->ux_callout, 4055 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4056 } 4057 4058 xfer->ux_status = USBD_IN_PROGRESS; 4059 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4060 ehci_del_intr_list(sc, ex); /* remove from active list */ 4061 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 4062 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4063 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4064 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4065 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4066 } 4067 #undef exfer 4068 } 4069 4070 /************************/ 4071 4072 Static usbd_status 4073 ehci_device_fs_isoc_transfer(usbd_xfer_handle xfer) 4074 { 4075 usbd_status err; 4076 4077 err = usb_insert_transfer(xfer); 4078 if (err && err != USBD_IN_PROGRESS) 4079 return err; 4080 4081 return ehci_device_fs_isoc_start(xfer); 4082 } 4083 4084 Static usbd_status 4085 ehci_device_fs_isoc_start(usbd_xfer_handle xfer) 4086 { 4087 struct ehci_pipe *epipe; 4088 usbd_device_handle dev; 4089 ehci_softc_t *sc; 4090 struct ehci_xfer *exfer; 4091 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4092 usb_dma_t *dma_buf; 4093 int i, j, k, frames; 4094 int offs, total_length; 4095 int frindex; 4096 u_int huba, dir; 4097 4098 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4099 4100 start = NULL; 4101 prev = NULL; 4102 sitd = NULL; 4103 total_length = 0; 4104 exfer = (struct ehci_xfer *) xfer; 4105 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4106 dev = xfer->ux_pipe->up_dev; 4107 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4108 4109 /* 4110 * To allow continuous transfers, above we start all transfers 4111 * immediately. However, we're still going to get usbd_start_next call 4112 * this when another xfer completes. So, check if this is already 4113 * in progress or not 4114 */ 4115 4116 if (exfer->ex_sitdstart != NULL) 4117 return USBD_IN_PROGRESS; 4118 4119 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4120 xfer, xfer->ux_length, xfer->ux_flags, 0); 4121 4122 if (sc->sc_dying) 4123 return USBD_IOERROR; 4124 4125 /* 4126 * To avoid complication, don't allow a request right now that'll span 4127 * the entire frame table. To within 4 frames, to allow some leeway 4128 * on either side of where the hc currently is. 4129 */ 4130 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4131 xfer->ux_nframes >= sc->sc_flsize - 4) { 4132 printf("ehci: isoc descriptor requested that spans the entire" 4133 "frametable, too many frames\n"); 4134 return USBD_INVAL; 4135 } 4136 4137 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4138 4139 #ifdef DIAGNOSTIC 4140 if (!exfer->ex_isdone) 4141 printf("ehci_device_fs_isoc_start: not done, ex = %p\n", exfer); 4142 exfer->ex_isdone = 0; 4143 #endif 4144 4145 /* 4146 * Step 1: Allocate and initialize sitds. 4147 */ 4148 4149 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4150 if (i > 16 || i == 0) { 4151 /* Spec page 271 says intervals > 16 are invalid */ 4152 USBHIST_LOG(ehcidebug, "bInterval %d invalid", 0, 0, 0, 0); 4153 4154 return USBD_INVAL; 4155 } 4156 4157 frames = xfer->ux_nframes; 4158 4159 if (frames == 0) { 4160 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4161 4162 return USBD_INVAL; 4163 } 4164 4165 dma_buf = &xfer->ux_dmabuf; 4166 offs = 0; 4167 4168 for (i = 0; i < frames; i++) { 4169 sitd = ehci_alloc_sitd(sc); 4170 4171 if (prev) 4172 prev->xfer_next = sitd; 4173 else 4174 start = sitd; 4175 4176 #ifdef DIAGNOSTIC 4177 if (xfer->ux_frlengths[i] > 0x3ff) { 4178 printf("ehci: invalid frame length\n"); 4179 xfer->ux_frlengths[i] = 0x3ff; 4180 } 4181 #endif 4182 4183 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4184 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4185 4186 /* Set page0 index and offset. */ 4187 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4188 4189 total_length += xfer->ux_frlengths[i]; 4190 offs += xfer->ux_frlengths[i]; 4191 4192 sitd->sitd.sitd_buffer[1] = 4193 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4194 4195 huba = dev->ud_myhsport->up_parent->ud_addr; 4196 4197 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4198 // Set hub address to 0 if embedded TT is used. 4199 if (huba == sc->sc_addr) 4200 huba = 0; 4201 } 4202 */ 4203 4204 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4205 dir = UE_GET_DIR(k) ? 1 : 0; 4206 sitd->sitd.sitd_endp = 4207 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4208 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4209 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4210 EHCI_SITD_SET_HUBA(huba) | 4211 EHCI_SITD_SET_DIR(dir)); 4212 4213 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4214 4215 /* XXX */ 4216 u_char sa, sb; 4217 u_int temp, tlen; 4218 sa = 0; 4219 4220 if (dir == 0) { /* OUT */ 4221 temp = 0; 4222 tlen = xfer->ux_frlengths[i]; 4223 if (tlen <= 188) { 4224 temp |= 1; /* T-count = 1, TP = ALL */ 4225 tlen = 1; 4226 } else { 4227 tlen += 187; 4228 tlen /= 188; 4229 temp |= tlen; /* T-count = [1..6] */ 4230 temp |= 8; /* TP = Begin */ 4231 } 4232 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4233 4234 tlen += sa; 4235 4236 if (tlen >= 8) { 4237 sb = 0; 4238 } else { 4239 sb = (1 << tlen); 4240 } 4241 4242 sa = (1 << sa); 4243 sa = (sb - sa) & 0x3F; 4244 sb = 0; 4245 } else { 4246 sb = (-(4 << sa)) & 0xFE; 4247 sa = (1 << sa) & 0x3F; 4248 sa = 0x01; 4249 sb = 0xfc; 4250 } 4251 4252 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4253 EHCI_SITD_SET_CMASK(sb)); 4254 4255 prev = sitd; 4256 } /* End of frame */ 4257 4258 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4259 4260 stop = sitd; 4261 stop->xfer_next = NULL; 4262 4263 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4264 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4265 4266 /* 4267 * Part 2: Transfer descriptors have now been set up, now they must 4268 * be scheduled into the periodic frame list. Erk. Not wanting to 4269 * complicate matters, transfer is denied if the transfer spans 4270 * more than the period frame list. 4271 */ 4272 4273 mutex_enter(&sc->sc_lock); 4274 4275 /* Start inserting frames */ 4276 if (epipe->u.isoc.cur_xfers > 0) { 4277 frindex = epipe->u.isoc.next_frame; 4278 } else { 4279 frindex = EOREAD4(sc, EHCI_FRINDEX); 4280 frindex = frindex >> 3; /* Erase microframe index */ 4281 frindex += 2; 4282 } 4283 4284 if (frindex >= sc->sc_flsize) 4285 frindex &= (sc->sc_flsize - 1); 4286 4287 /* Whats the frame interval? */ 4288 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4289 4290 sitd = start; 4291 for (j = 0; j < frames; j++) { 4292 if (sitd == NULL) 4293 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4294 4295 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4296 if (sitd->sitd.sitd_next == 0) 4297 /* FIXME: frindex table gets initialized to NULL 4298 * or EHCI_NULL? */ 4299 sitd->sitd.sitd_next = EHCI_NULL; 4300 4301 usb_syncmem(&sitd->dma, 4302 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4303 sizeof(ehci_sitd_t), 4304 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4305 4306 sc->sc_flist[frindex] = 4307 htole32(EHCI_LINK_SITD | sitd->physaddr); 4308 4309 usb_syncmem(&sc->sc_fldma, 4310 sizeof(ehci_link_t) * frindex, 4311 sizeof(ehci_link_t), 4312 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4313 4314 sitd->u.frame_list.next = sc->sc_softsitds[frindex]; 4315 sc->sc_softsitds[frindex] = sitd; 4316 if (sitd->u.frame_list.next != NULL) 4317 sitd->u.frame_list.next->u.frame_list.prev = sitd; 4318 sitd->slot = frindex; 4319 sitd->u.frame_list.prev = NULL; 4320 4321 frindex += i; 4322 if (frindex >= sc->sc_flsize) 4323 frindex -= sc->sc_flsize; 4324 4325 sitd = sitd->xfer_next; 4326 } 4327 4328 epipe->u.isoc.cur_xfers++; 4329 epipe->u.isoc.next_frame = frindex; 4330 4331 exfer->ex_sitdstart = start; 4332 exfer->ex_sitdend = stop; 4333 4334 ehci_add_intr_list(sc, exfer); 4335 xfer->ux_status = USBD_IN_PROGRESS; 4336 xfer->ux_done = 0; 4337 4338 mutex_exit(&sc->sc_lock); 4339 4340 if (sc->sc_bus.ub_usepolling) { 4341 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4342 ehci_waitintr(sc, xfer); 4343 } 4344 4345 return USBD_IN_PROGRESS; 4346 } 4347 4348 Static void 4349 ehci_device_fs_isoc_abort(usbd_xfer_handle xfer) 4350 { 4351 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4352 4353 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4354 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4355 } 4356 4357 Static void 4358 ehci_device_fs_isoc_close(usbd_pipe_handle pipe) 4359 { 4360 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4361 4362 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4363 } 4364 4365 Static void 4366 ehci_device_fs_isoc_done(usbd_xfer_handle xfer) 4367 { 4368 struct ehci_xfer *exfer; 4369 ehci_softc_t *sc; 4370 struct ehci_pipe *epipe; 4371 4372 exfer = EXFER(xfer); 4373 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4374 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4375 4376 KASSERT(mutex_owned(&sc->sc_lock)); 4377 4378 epipe->u.isoc.cur_xfers--; 4379 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4380 ehci_del_intr_list(sc, exfer); 4381 ehci_rem_free_sitd_chain(sc, exfer); 4382 } 4383 4384 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4385 BUS_DMASYNC_POSTREAD); 4386 } 4387 Static usbd_status 4388 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 4389 { 4390 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4391 usbd_status err; 4392 4393 mutex_enter(&sc->sc_lock); 4394 err = usb_insert_transfer(xfer); 4395 mutex_exit(&sc->sc_lock); 4396 if (err && err != USBD_IN_PROGRESS) 4397 return err; 4398 4399 return ehci_device_isoc_start(xfer); 4400 } 4401 4402 Static usbd_status 4403 ehci_device_isoc_start(usbd_xfer_handle xfer) 4404 { 4405 struct ehci_pipe *epipe; 4406 ehci_softc_t *sc; 4407 struct ehci_xfer *exfer; 4408 ehci_soft_itd_t *itd, *prev, *start, *stop; 4409 usb_dma_t *dma_buf; 4410 int i, j, k, frames, uframes, ufrperframe; 4411 int trans_count, offs, total_length; 4412 int frindex; 4413 4414 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4415 4416 start = NULL; 4417 prev = NULL; 4418 itd = NULL; 4419 trans_count = 0; 4420 total_length = 0; 4421 exfer = (struct ehci_xfer *) xfer; 4422 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4423 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4424 4425 /* 4426 * To allow continuous transfers, above we start all transfers 4427 * immediately. However, we're still going to get usbd_start_next call 4428 * this when another xfer completes. So, check if this is already 4429 * in progress or not 4430 */ 4431 4432 if (exfer->ex_itdstart != NULL) 4433 return USBD_IN_PROGRESS; 4434 4435 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4436 xfer, xfer->ux_length, xfer->ux_flags, 0); 4437 4438 if (sc->sc_dying) 4439 return USBD_IOERROR; 4440 4441 /* 4442 * To avoid complication, don't allow a request right now that'll span 4443 * the entire frame table. To within 4 frames, to allow some leeway 4444 * on either side of where the hc currently is. 4445 */ 4446 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4447 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4448 USBHIST_LOG(ehcidebug, 4449 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4450 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4451 return USBD_INVAL; 4452 } 4453 4454 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4455 4456 #ifdef DIAGNOSTIC 4457 if (!exfer->ex_isdone) { 4458 USBHIST_LOG(ehcidebug, "marked not done, ex = %p", exfer, 4459 0, 0, 0); 4460 printf("ehci_device_isoc_start: not done, ex = %p\n", exfer); 4461 } 4462 exfer->ex_isdone = 0; 4463 #endif 4464 4465 /* 4466 * Step 1: Allocate and initialize itds, how many do we need? 4467 * One per transfer if interval >= 8 microframes, fewer if we use 4468 * multiple microframes per frame. 4469 */ 4470 4471 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4472 if (i > 16 || i == 0) { 4473 /* Spec page 271 says intervals > 16 are invalid */ 4474 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4475 return USBD_INVAL; 4476 } 4477 4478 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4479 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4480 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4481 4482 if (frames == 0) { 4483 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4484 return USBD_INVAL; 4485 } 4486 4487 dma_buf = &xfer->ux_dmabuf; 4488 offs = 0; 4489 4490 for (i = 0; i < frames; i++) { 4491 int froffs = offs; 4492 itd = ehci_alloc_itd(sc); 4493 4494 if (prev != NULL) { 4495 prev->itd.itd_next = 4496 htole32(itd->physaddr | EHCI_LINK_ITD); 4497 usb_syncmem(&itd->dma, 4498 itd->offs + offsetof(ehci_itd_t, itd_next), 4499 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4500 4501 prev->xfer_next = itd; 4502 } else { 4503 start = itd; 4504 } 4505 4506 /* 4507 * Step 1.5, initialize uframes 4508 */ 4509 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4510 /* Calculate which page in the list this starts in */ 4511 int addr = DMAADDR(dma_buf, froffs); 4512 addr = EHCI_PAGE_OFFSET(addr); 4513 addr += (offs - froffs); 4514 addr = EHCI_PAGE(addr); 4515 addr /= EHCI_PAGE_SIZE; 4516 4517 /* 4518 * This gets the initial offset into the first page, 4519 * looks how far further along the current uframe 4520 * offset is. Works out how many pages that is. 4521 */ 4522 4523 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4524 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4525 EHCI_ITD_SET_PG(addr) | 4526 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4527 4528 total_length += xfer->ux_frlengths[trans_count]; 4529 offs += xfer->ux_frlengths[trans_count]; 4530 trans_count++; 4531 4532 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4533 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4534 break; 4535 } 4536 } 4537 4538 /* 4539 * Step 1.75, set buffer pointers. To simplify matters, all 4540 * pointers are filled out for the next 7 hardware pages in 4541 * the dma block, so no need to worry what pages to cover 4542 * and what to not. 4543 */ 4544 4545 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4546 /* 4547 * Don't try to lookup a page that's past the end 4548 * of buffer 4549 */ 4550 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4551 if (page_offs >= dma_buf->udma_block->size) 4552 break; 4553 4554 unsigned long long page = DMAADDR(dma_buf, page_offs); 4555 page = EHCI_PAGE(page); 4556 itd->itd.itd_bufr[j] = 4557 htole32(EHCI_ITD_SET_BPTR(page)); 4558 itd->itd.itd_bufr_hi[j] = 4559 htole32(page >> 32); 4560 } 4561 4562 /* 4563 * Other special values 4564 */ 4565 4566 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4567 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4568 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4569 4570 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4571 ? 1 : 0; 4572 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4573 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4574 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4575 4576 /* FIXME: handle invalid trans */ 4577 itd->itd.itd_bufr[2] |= 4578 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4579 4580 usb_syncmem(&itd->dma, 4581 itd->offs + offsetof(ehci_itd_t, itd_next), 4582 sizeof(ehci_itd_t), 4583 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4584 4585 prev = itd; 4586 } /* End of frame */ 4587 4588 stop = itd; 4589 stop->xfer_next = NULL; 4590 4591 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4592 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4593 4594 /* 4595 * Part 2: Transfer descriptors have now been set up, now they must 4596 * be scheduled into the period frame list. Erk. Not wanting to 4597 * complicate matters, transfer is denied if the transfer spans 4598 * more than the period frame list. 4599 */ 4600 4601 mutex_enter(&sc->sc_lock); 4602 4603 /* Start inserting frames */ 4604 if (epipe->u.isoc.cur_xfers > 0) { 4605 frindex = epipe->u.isoc.next_frame; 4606 } else { 4607 frindex = EOREAD4(sc, EHCI_FRINDEX); 4608 frindex = frindex >> 3; /* Erase microframe index */ 4609 frindex += 2; 4610 } 4611 4612 if (frindex >= sc->sc_flsize) 4613 frindex &= (sc->sc_flsize - 1); 4614 4615 /* What's the frame interval? */ 4616 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4617 if (i / USB_UFRAMES_PER_FRAME == 0) 4618 i = 1; 4619 else 4620 i /= USB_UFRAMES_PER_FRAME; 4621 4622 itd = start; 4623 for (j = 0; j < frames; j++) { 4624 if (itd == NULL) 4625 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4626 4627 itd->itd.itd_next = sc->sc_flist[frindex]; 4628 if (itd->itd.itd_next == 0) 4629 /* FIXME: frindex table gets initialized to NULL 4630 * or EHCI_NULL? */ 4631 itd->itd.itd_next = EHCI_NULL; 4632 4633 usb_syncmem(&itd->dma, 4634 itd->offs + offsetof(ehci_itd_t, itd_next), 4635 sizeof(itd->itd.itd_next), 4636 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4637 4638 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4639 4640 usb_syncmem(&sc->sc_fldma, 4641 sizeof(ehci_link_t) * frindex, 4642 sizeof(ehci_link_t), 4643 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4644 4645 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4646 sc->sc_softitds[frindex] = itd; 4647 if (itd->u.frame_list.next != NULL) 4648 itd->u.frame_list.next->u.frame_list.prev = itd; 4649 itd->slot = frindex; 4650 itd->u.frame_list.prev = NULL; 4651 4652 frindex += i; 4653 if (frindex >= sc->sc_flsize) 4654 frindex -= sc->sc_flsize; 4655 4656 itd = itd->xfer_next; 4657 } 4658 4659 epipe->u.isoc.cur_xfers++; 4660 epipe->u.isoc.next_frame = frindex; 4661 4662 exfer->ex_itdstart = start; 4663 exfer->ex_itdend = stop; 4664 4665 ehci_add_intr_list(sc, exfer); 4666 xfer->ux_status = USBD_IN_PROGRESS; 4667 xfer->ux_done = 0; 4668 mutex_exit(&sc->sc_lock); 4669 4670 if (sc->sc_bus.ub_usepolling) { 4671 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4672 ehci_waitintr(sc, xfer); 4673 } 4674 4675 return USBD_IN_PROGRESS; 4676 } 4677 4678 Static void 4679 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4680 { 4681 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4682 4683 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4684 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4685 } 4686 4687 Static void 4688 ehci_device_isoc_close(usbd_pipe_handle pipe) 4689 { 4690 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4691 4692 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4693 } 4694 4695 Static void 4696 ehci_device_isoc_done(usbd_xfer_handle xfer) 4697 { 4698 struct ehci_xfer *exfer; 4699 ehci_softc_t *sc; 4700 struct ehci_pipe *epipe; 4701 4702 exfer = EXFER(xfer); 4703 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4704 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4705 4706 KASSERT(mutex_owned(&sc->sc_lock)); 4707 4708 epipe->u.isoc.cur_xfers--; 4709 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4710 ehci_del_intr_list(sc, exfer); 4711 ehci_rem_free_itd_chain(sc, exfer); 4712 } 4713 4714 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4715 BUS_DMASYNC_POSTREAD); 4716 4717 } 4718
Indexes created Thu Oct 02 01:09:59 GMT 2025