ehci.c revision 1.234.2.37
1 /* $NetBSD: ehci.c,v 1.234.2.37 2015/03/03 06:36:53 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.37 2015/03/03 06:36:53 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 85 #include <dev/usb/ehcireg.h> 86 #include <dev/usb/ehcivar.h> 87 #include <dev/usb/usbroothub.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 /* ehci_soft_sitd_t *sitd; */ 135 } tail; 136 union { 137 /* Control pipe */ 138 struct { 139 usb_dma_t reqdma; 140 } ctl; 141 /* Interrupt pipe */ 142 struct { 143 u_int length; 144 } intr; 145 /* Bulk pipe */ 146 struct { 147 u_int length; 148 } bulk; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 } u; 155 }; 156 157 Static usbd_status ehci_open(usbd_pipe_handle); 158 Static void ehci_poll(struct usbd_bus *); 159 Static void ehci_softintr(void *); 160 Static int ehci_intr1(ehci_softc_t *); 161 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 162 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 166 Static void ehci_idone(struct ehci_xfer *); 167 Static void ehci_timeout(void *); 168 Static void ehci_timeout_task(void *); 169 Static void ehci_intrlist_timeout(void *); 170 Static void ehci_doorbell(void *); 171 Static void ehci_pcd(void *); 172 173 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 174 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 Static int ehci_roothub_ctrl(struct usbd_bus *, 177 usb_device_request_t *, void *, int); 178 179 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 180 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 181 Static void ehci_root_intr_abort(usbd_xfer_handle); 182 Static void ehci_root_intr_close(usbd_pipe_handle); 183 Static void ehci_root_intr_done(usbd_xfer_handle); 184 185 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 186 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 187 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 188 Static void ehci_device_ctrl_close(usbd_pipe_handle); 189 Static void ehci_device_ctrl_done(usbd_xfer_handle); 190 191 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 192 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 193 Static void ehci_device_bulk_abort(usbd_xfer_handle); 194 Static void ehci_device_bulk_close(usbd_pipe_handle); 195 Static void ehci_device_bulk_done(usbd_xfer_handle); 196 197 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 198 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 199 Static void ehci_device_intr_abort(usbd_xfer_handle); 200 Static void ehci_device_intr_close(usbd_pipe_handle); 201 Static void ehci_device_intr_done(usbd_xfer_handle); 202 203 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 204 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 205 Static void ehci_device_isoc_abort(usbd_xfer_handle); 206 Static void ehci_device_isoc_close(usbd_pipe_handle); 207 Static void ehci_device_isoc_done(usbd_xfer_handle); 208 209 Static usbd_status ehci_device_fs_isoc_transfer(usbd_xfer_handle); 210 Static usbd_status ehci_device_fs_isoc_start(usbd_xfer_handle); 211 Static void ehci_device_fs_isoc_abort(usbd_xfer_handle); 212 Static void ehci_device_fs_isoc_close(usbd_pipe_handle); 213 Static void ehci_device_fs_isoc_done(usbd_xfer_handle); 214 215 Static void ehci_device_clear_toggle(usbd_pipe_handle); 216 Static void ehci_noop(usbd_pipe_handle); 217 218 Static void ehci_disown(ehci_softc_t *, int, int); 219 220 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 221 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 222 223 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 224 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 225 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 226 ehci_softc_t *, int, int, usbd_xfer_handle, 227 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 228 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 229 ehci_soft_qtd_t *); 230 231 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 232 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *); 233 Static void ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *); 234 Static void ehci_free_sitd(ehci_softc_t *, ehci_soft_sitd_t *); 235 Static void ehci_rem_free_itd_chain(ehci_softc_t *, 236 struct ehci_xfer *); 237 Static void ehci_rem_free_sitd_chain(ehci_softc_t *, 238 struct ehci_xfer *); 239 Static void ehci_abort_isoc_xfer(usbd_xfer_handle, 240 usbd_status); 241 242 Static usbd_status ehci_device_request(usbd_xfer_handle); 243 244 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 245 int); 246 247 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 248 ehci_soft_qh_t *); 249 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 250 ehci_soft_qh_t *); 251 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 252 Static void ehci_sync_hc(ehci_softc_t *); 253 254 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 255 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 256 257 #ifdef EHCI_DEBUG 258 Static ehci_softc_t *theehci; 259 void ehci_dump(void); 260 #endif 261 262 #ifdef EHCI_DEBUG 263 Static void ehci_dump_regs(ehci_softc_t *); 264 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 265 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 266 Static void ehci_dump_qtd(ehci_qtd_t *); 267 Static void ehci_dump_sqh(ehci_soft_qh_t *); 268 Static void ehci_dump_sitd(struct ehci_soft_itd *); 269 Static void ehci_dump_itd(struct ehci_soft_itd *); 270 Static void ehci_dump_exfer(struct ehci_xfer *); 271 #endif 272 273 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 274 275 #define ehci_add_intr_list(sc, ex) \ 276 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 277 #define ehci_del_intr_list(sc, ex) \ 278 do { \ 279 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 280 (ex)->ex_next.tqe_prev = NULL; \ 281 } while (0) 282 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 283 284 Static const struct usbd_bus_methods ehci_bus_methods = { 285 .ubm_open = ehci_open, 286 .ubm_softint = ehci_softintr, 287 .ubm_dopoll = ehci_poll, 288 .ubm_allocx = ehci_allocx, 289 .ubm_freex = ehci_freex, 290 .ubm_getlock = ehci_get_lock, 291 .ubm_rhctrl = ehci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 295 .upm_transfer = ehci_root_intr_transfer, 296 .upm_start = ehci_root_intr_start, 297 .upm_abort = ehci_root_intr_abort, 298 .upm_close = ehci_root_intr_close, 299 .upm_cleartoggle = ehci_noop, 300 .upm_done = ehci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 304 .upm_transfer = ehci_device_ctrl_transfer, 305 .upm_start = ehci_device_ctrl_start, 306 .upm_abort = ehci_device_ctrl_abort, 307 .upm_close = ehci_device_ctrl_close, 308 .upm_cleartoggle = ehci_noop, 309 .upm_done = ehci_device_ctrl_done, 310 }; 311 312 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 313 .upm_transfer = ehci_device_intr_transfer, 314 .upm_start = ehci_device_intr_start, 315 .upm_abort = ehci_device_intr_abort, 316 .upm_close = ehci_device_intr_close, 317 .upm_cleartoggle = ehci_device_clear_toggle, 318 .upm_done = ehci_device_intr_done, 319 }; 320 321 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 322 .upm_transfer = ehci_device_bulk_transfer, 323 .upm_start = ehci_device_bulk_start, 324 .upm_abort = ehci_device_bulk_abort, 325 .upm_close = ehci_device_bulk_close, 326 .upm_cleartoggle = ehci_device_clear_toggle, 327 .upm_done = ehci_device_bulk_done, 328 }; 329 330 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 331 .upm_transfer = ehci_device_isoc_transfer, 332 .upm_start = ehci_device_isoc_start, 333 .upm_abort = ehci_device_isoc_abort, 334 .upm_close = ehci_device_isoc_close, 335 .upm_cleartoggle = ehci_noop, 336 .upm_done = ehci_device_isoc_done, 337 }; 338 339 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 340 .upm_transfer = ehci_device_fs_isoc_transfer, 341 .upm_start = ehci_device_fs_isoc_start, 342 .upm_abort = ehci_device_fs_isoc_abort, 343 .upm_close = ehci_device_fs_isoc_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_fs_isoc_done, 346 }; 347 348 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 349 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 350 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 351 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 352 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 353 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 354 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 355 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 356 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 357 }; 358 359 int 360 ehci_init(ehci_softc_t *sc) 361 { 362 uint32_t vers, sparams, cparams, hcr; 363 u_int i; 364 usbd_status err; 365 ehci_soft_qh_t *sqh; 366 u_int ncomp; 367 368 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 369 #ifdef EHCI_DEBUG 370 theehci = sc; 371 #endif 372 373 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 374 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 375 cv_init(&sc->sc_softwake_cv, "ehciab"); 376 cv_init(&sc->sc_doorbell, "ehcidi"); 377 378 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 379 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 380 381 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 382 ehci_doorbell, sc); 383 KASSERT(sc->sc_doorbell_si != NULL); 384 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 385 ehci_pcd, sc); 386 KASSERT(sc->sc_pcd_si != NULL); 387 388 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 389 390 vers = EREAD2(sc, EHCI_HCIVERSION); 391 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 392 vers >> 8, vers & 0xff); 393 394 sparams = EREAD4(sc, EHCI_HCSPARAMS); 395 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 396 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 397 ncomp = EHCI_HCS_N_CC(sparams); 398 if (ncomp != sc->sc_ncomp) { 399 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 400 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 401 #if NOHCI == 0 || NUHCI == 0 402 aprint_error("%s: ohci or uhci probably not configured\n", 403 device_xname(sc->sc_dev)); 404 #endif 405 if (ncomp < sc->sc_ncomp) 406 sc->sc_ncomp = ncomp; 407 } 408 if (sc->sc_ncomp > 0) { 409 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 410 aprint_normal("%s: companion controller%s, %d port%s each:", 411 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 412 EHCI_HCS_N_PCC(sparams), 413 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 414 for (i = 0; i < sc->sc_ncomp; i++) 415 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 416 aprint_normal("\n"); 417 } 418 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 419 cparams = EREAD4(sc, EHCI_HCCPARAMS); 420 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 421 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 422 423 if (EHCI_HCC_64BIT(cparams)) { 424 /* MUST clear segment register if 64 bit capable. */ 425 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 426 } 427 428 sc->sc_bus.ub_revision = USBREV_2_0; 429 sc->sc_bus.ub_usedma = true; 430 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 431 432 /* Reset the controller */ 433 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 434 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 435 usb_delay_ms(&sc->sc_bus, 1); 436 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 437 for (i = 0; i < 100; i++) { 438 usb_delay_ms(&sc->sc_bus, 1); 439 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 440 if (!hcr) 441 break; 442 } 443 if (hcr) { 444 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 445 return EIO; 446 } 447 if (sc->sc_vendor_init) 448 sc->sc_vendor_init(sc); 449 450 /* 451 * If we are doing embedded transaction translation function, force 452 * the controller to host mode. 453 */ 454 if (sc->sc_flags & EHCIF_ETTF) { 455 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 456 usbmode &= ~EHCI_USBMODE_CM; 457 usbmode |= EHCI_USBMODE_CM_HOST; 458 EWRITE4(sc, EHCI_USBMODE, usbmode); 459 } 460 461 /* XXX need proper intr scheduling */ 462 sc->sc_rand = 96; 463 464 /* frame list size at default, read back what we got and use that */ 465 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 466 case 0: sc->sc_flsize = 1024; break; 467 case 1: sc->sc_flsize = 512; break; 468 case 2: sc->sc_flsize = 256; break; 469 case 3: return EIO; 470 } 471 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 472 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 473 if (err) 474 return err; 475 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 476 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 477 478 for (i = 0; i < sc->sc_flsize; i++) { 479 sc->sc_flist[i] = EHCI_NULL; 480 } 481 482 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 483 484 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 485 KM_SLEEP); 486 if (sc->sc_softitds == NULL) 487 return ENOMEM; 488 LIST_INIT(&sc->sc_freeitds); 489 LIST_INIT(&sc->sc_freesitds); 490 TAILQ_INIT(&sc->sc_intrhead); 491 492 /* Set up the bus struct. */ 493 sc->sc_bus.ub_methods = &ehci_bus_methods; 494 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 495 496 sc->sc_eintrs = EHCI_NORMAL_INTRS; 497 498 /* 499 * Allocate the interrupt dummy QHs. These are arranged to give poll 500 * intervals that are powers of 2 times 1ms. 501 */ 502 for (i = 0; i < EHCI_INTRQHS; i++) { 503 sqh = ehci_alloc_sqh(sc); 504 if (sqh == NULL) { 505 err = ENOMEM; 506 goto bad1; 507 } 508 sc->sc_islots[i].sqh = sqh; 509 } 510 for (i = 0; i < EHCI_INTRQHS; i++) { 511 sqh = sc->sc_islots[i].sqh; 512 if (i == 0) { 513 /* The last (1ms) QH terminates. */ 514 sqh->qh.qh_link = EHCI_NULL; 515 sqh->next = NULL; 516 } else { 517 /* Otherwise the next QH has half the poll interval */ 518 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 519 sqh->qh.qh_link = htole32(sqh->next->physaddr | 520 EHCI_LINK_QH); 521 } 522 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 523 sqh->qh.qh_curqtd = EHCI_NULL; 524 sqh->next = NULL; 525 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 526 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 527 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 528 sqh->sqtd = NULL; 529 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 531 } 532 /* Point the frame list at the last level (128ms). */ 533 for (i = 0; i < sc->sc_flsize; i++) { 534 int j; 535 536 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 537 revbits[i & (EHCI_MAX_POLLRATE-1)]; 538 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 539 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 540 i)].sqh->physaddr); 541 } 542 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 543 BUS_DMASYNC_PREWRITE); 544 545 /* Allocate dummy QH that starts the async list. */ 546 sqh = ehci_alloc_sqh(sc); 547 if (sqh == NULL) { 548 err = ENOMEM; 549 goto bad1; 550 } 551 /* Fill the QH */ 552 sqh->qh.qh_endp = 553 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 554 sqh->qh.qh_link = 555 htole32(sqh->physaddr | EHCI_LINK_QH); 556 sqh->qh.qh_curqtd = EHCI_NULL; 557 sqh->next = NULL; 558 /* Fill the overlay qTD */ 559 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 560 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 561 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 562 sqh->sqtd = NULL; 563 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 564 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 565 #ifdef EHCI_DEBUG 566 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 567 ehci_dump_sqh(sqh); 568 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 569 #endif 570 571 /* Point to async list */ 572 sc->sc_async_head = sqh; 573 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 574 575 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 576 577 /* Turn on controller */ 578 EOWRITE4(sc, EHCI_USBCMD, 579 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 580 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 581 EHCI_CMD_ASE | 582 EHCI_CMD_PSE | 583 EHCI_CMD_RS); 584 585 /* Take over port ownership */ 586 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 587 588 for (i = 0; i < 100; i++) { 589 usb_delay_ms(&sc->sc_bus, 1); 590 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 591 if (!hcr) 592 break; 593 } 594 if (hcr) { 595 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 596 return EIO; 597 } 598 599 /* Enable interrupts */ 600 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 601 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 602 603 return 0; 604 605 #if 0 606 bad2: 607 ehci_free_sqh(sc, sc->sc_async_head); 608 #endif 609 bad1: 610 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 611 return err; 612 } 613 614 int 615 ehci_intr(void *v) 616 { 617 ehci_softc_t *sc = v; 618 int ret = 0; 619 620 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 621 622 if (sc == NULL) 623 return 0; 624 625 mutex_spin_enter(&sc->sc_intr_lock); 626 627 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 628 goto done; 629 630 /* If we get an interrupt while polling, then just ignore it. */ 631 if (sc->sc_bus.ub_usepolling) { 632 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 633 634 if (intrs) 635 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 636 USBHIST_LOGN(ehcidebug, 16, 637 "ignored interrupt while polling", 0, 0, 0, 0); 638 goto done; 639 } 640 641 ret = ehci_intr1(sc); 642 643 done: 644 mutex_spin_exit(&sc->sc_intr_lock); 645 return ret; 646 } 647 648 Static int 649 ehci_intr1(ehci_softc_t *sc) 650 { 651 uint32_t intrs, eintrs; 652 653 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 654 655 /* In case the interrupt occurs before initialization has completed. */ 656 if (sc == NULL) { 657 #ifdef DIAGNOSTIC 658 printf("ehci_intr1: sc == NULL\n"); 659 #endif 660 return 0; 661 } 662 663 KASSERT(mutex_owned(&sc->sc_intr_lock)); 664 665 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 666 if (!intrs) 667 return 0; 668 669 eintrs = intrs & sc->sc_eintrs; 670 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 671 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 672 if (!eintrs) 673 return 0; 674 675 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 676 if (eintrs & EHCI_STS_IAA) { 677 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 678 kpreempt_disable(); 679 KASSERT(sc->sc_doorbell_si != NULL); 680 softint_schedule(sc->sc_doorbell_si); 681 kpreempt_enable(); 682 eintrs &= ~EHCI_STS_IAA; 683 } 684 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 685 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 686 eintrs & EHCI_STS_INT ? 1 : 0, 687 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 688 usb_schedsoftintr(&sc->sc_bus); 689 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 690 } 691 if (eintrs & EHCI_STS_HSE) { 692 printf("%s: unrecoverable error, controller halted\n", 693 device_xname(sc->sc_dev)); 694 /* XXX what else */ 695 } 696 if (eintrs & EHCI_STS_PCD) { 697 kpreempt_disable(); 698 KASSERT(sc->sc_pcd_si != NULL); 699 softint_schedule(sc->sc_pcd_si); 700 kpreempt_enable(); 701 eintrs &= ~EHCI_STS_PCD; 702 } 703 704 if (eintrs != 0) { 705 /* Block unprocessed interrupts. */ 706 sc->sc_eintrs &= ~eintrs; 707 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 708 printf("%s: blocking intrs 0x%x\n", 709 device_xname(sc->sc_dev), eintrs); 710 } 711 712 return 1; 713 } 714 715 Static void 716 ehci_doorbell(void *addr) 717 { 718 ehci_softc_t *sc = addr; 719 720 mutex_enter(&sc->sc_lock); 721 cv_broadcast(&sc->sc_doorbell); 722 mutex_exit(&sc->sc_lock); 723 } 724 725 Static void 726 ehci_pcd(void *addr) 727 { 728 ehci_softc_t *sc = addr; 729 usbd_xfer_handle xfer; 730 u_char *p; 731 int i, m; 732 733 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 734 735 mutex_enter(&sc->sc_lock); 736 xfer = sc->sc_intrxfer; 737 738 if (xfer == NULL) { 739 /* Just ignore the change. */ 740 goto done; 741 } 742 743 p = xfer->ux_buf; 744 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 745 memset(p, 0, xfer->ux_length); 746 for (i = 1; i <= m; i++) { 747 /* Pick out CHANGE bits from the status reg. */ 748 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 749 p[i/8] |= 1 << (i%8); 750 if (i % 8 == 7) 751 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 752 p[i/8], 0, 0); 753 } 754 xfer->ux_actlen = xfer->ux_length; 755 xfer->ux_status = USBD_NORMAL_COMPLETION; 756 757 usb_transfer_complete(xfer); 758 759 done: 760 mutex_exit(&sc->sc_lock); 761 } 762 763 Static void 764 ehci_softintr(void *v) 765 { 766 struct usbd_bus *bus = v; 767 ehci_softc_t *sc = bus->ub_hcpriv; 768 struct ehci_xfer *ex, *nextex; 769 770 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 771 772 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 773 774 /* 775 * The only explanation I can think of for why EHCI is as brain dead 776 * as UHCI interrupt-wise is that Intel was involved in both. 777 * An interrupt just tells us that something is done, we have no 778 * clue what, so we need to scan through all active transfers. :-( 779 */ 780 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 781 nextex = TAILQ_NEXT(ex, ex_next); 782 ehci_check_intr(sc, ex); 783 } 784 785 /* Schedule a callout to catch any dropped transactions. */ 786 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 787 !TAILQ_EMPTY(&sc->sc_intrhead)) 788 callout_reset(&sc->sc_tmo_intrlist, 789 hz, ehci_intrlist_timeout, sc); 790 791 if (sc->sc_softwake) { 792 sc->sc_softwake = 0; 793 cv_broadcast(&sc->sc_softwake_cv); 794 } 795 } 796 797 /* Check for an interrupt. */ 798 Static void 799 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 800 { 801 usbd_device_handle dev = ex->ex_xfer.ux_pipe->up_dev; 802 int attr; 803 804 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 805 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 806 807 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 808 809 attr = ex->ex_xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 810 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 811 if (dev->ud_speed == USB_SPEED_HIGH) 812 ehci_check_itd_intr(sc, ex); 813 else 814 ehci_check_sitd_intr(sc, ex); 815 } else 816 ehci_check_qh_intr(sc, ex); 817 818 return; 819 } 820 821 Static void 822 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 823 { 824 ehci_soft_qtd_t *sqtd, *lsqtd; 825 uint32_t status; 826 827 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 828 829 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 830 831 if (ex->ex_sqtdstart == NULL) { 832 printf("ehci_check_qh_intr: not valid sqtd\n"); 833 return; 834 } 835 836 lsqtd = ex->ex_sqtdend; 837 #ifdef DIAGNOSTIC 838 if (lsqtd == NULL) { 839 printf("ehci_check_qh_intr: lsqtd==0\n"); 840 return; 841 } 842 #endif 843 /* 844 * If the last TD is still active we need to check whether there 845 * is an error somewhere in the middle, or whether there was a 846 * short packet (SPD and not ACTIVE). 847 */ 848 usb_syncmem(&lsqtd->dma, 849 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 850 sizeof(lsqtd->qtd.qtd_status), 851 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 852 status = le32toh(lsqtd->qtd.qtd_status); 853 usb_syncmem(&lsqtd->dma, 854 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 855 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 856 if (status & EHCI_QTD_ACTIVE) { 857 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 858 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd; 859 sqtd = sqtd->nextqtd) { 860 usb_syncmem(&sqtd->dma, 861 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 862 sizeof(sqtd->qtd.qtd_status), 863 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 864 status = le32toh(sqtd->qtd.qtd_status); 865 usb_syncmem(&sqtd->dma, 866 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 867 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 868 /* If there's an active QTD the xfer isn't done. */ 869 if (status & EHCI_QTD_ACTIVE) 870 break; 871 /* Any kind of error makes the xfer done. */ 872 if (status & EHCI_QTD_HALTED) 873 goto done; 874 /* Handle short packets */ 875 if (EHCI_QTD_GET_BYTES(status) != 0) { 876 usbd_pipe_handle pipe = ex->ex_xfer.ux_pipe; 877 usb_endpoint_descriptor_t *ed = 878 pipe->up_endpoint->ue_edesc; 879 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 880 881 /* 882 * If we get here for a control transfer then 883 * we need to let the hardware complete the 884 * status phase. That is, we're not done 885 * quite yet. 886 * 887 * Otherwise, we're done. 888 */ 889 if (xt == UE_CONTROL) { 890 break; 891 } 892 goto done; 893 } 894 } 895 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 896 ex, ex->ex_sqtdstart, 0, 0); 897 #ifdef EHCI_DEBUG 898 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 0, 0); 899 ehci_dump_sqtds(ex->ex_sqtdstart); 900 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 0); 901 #endif 902 return; 903 } 904 done: 905 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 906 callout_stop(&ex->ex_xfer.ux_callout); 907 ehci_idone(ex); 908 } 909 910 Static void 911 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 912 { 913 ehci_soft_itd_t *itd; 914 int i; 915 916 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 917 918 KASSERT(mutex_owned(&sc->sc_lock)); 919 920 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 921 return; 922 923 if (ex->ex_itdstart == NULL) { 924 printf("ehci_check_itd_intr: not valid itd\n"); 925 return; 926 } 927 928 itd = ex->ex_itdend; 929 #ifdef DIAGNOSTIC 930 if (itd == NULL) { 931 printf("ehci_check_itd_intr: itdend == 0\n"); 932 return; 933 } 934 #endif 935 936 /* 937 * check no active transfers in last itd, meaning we're finished 938 */ 939 940 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 941 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 942 BUS_DMASYNC_POSTREAD); 943 944 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 945 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 946 break; 947 } 948 949 if (i == EHCI_ITD_NUFRAMES) { 950 goto done; /* All 8 descriptors inactive, it's done */ 951 } 952 953 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 954 ex->ex_itdstart, 0, 0); 955 return; 956 done: 957 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 958 callout_stop(&ex->ex_xfer.ux_callout); 959 ehci_idone(ex); 960 } 961 962 void 963 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 964 { 965 ehci_soft_sitd_t *sitd; 966 967 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 968 969 KASSERT(mutex_owned(&sc->sc_lock)); 970 971 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 972 return; 973 974 if (ex->ex_sitdstart == NULL) { 975 printf("ehci_check_sitd_intr: not valid sitd\n"); 976 return; 977 } 978 979 sitd = ex->ex_sitdend; 980 #ifdef DIAGNOSTIC 981 if (sitd == NULL) { 982 printf("ehci_check_sitd_intr: sitdend == 0\n"); 983 return; 984 } 985 #endif 986 987 /* 988 * check no active transfers in last sitd, meaning we're finished 989 */ 990 991 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 992 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 993 BUS_DMASYNC_POSTREAD); 994 995 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 996 return; 997 998 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 999 callout_stop(&(ex->ex_xfer.ux_callout)); 1000 ehci_idone(ex); 1001 } 1002 1003 1004 Static void 1005 ehci_idone(struct ehci_xfer *ex) 1006 { 1007 usbd_xfer_handle xfer = &ex->ex_xfer; 1008 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1009 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1010 ehci_soft_qtd_t *sqtd, *lsqtd; 1011 uint32_t status = 0, nstatus = 0; 1012 int actlen; 1013 1014 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1015 1016 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1017 1018 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1019 1020 #ifdef DIAGNOSTIC 1021 #ifdef EHCI_DEBUG 1022 if (ex->ex_isdone) { 1023 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1024 ehci_dump_exfer(ex); 1025 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1026 } 1027 #endif 1028 KASSERT(!ex->ex_isdone); 1029 ex->ex_isdone = true; 1030 #endif 1031 1032 if (xfer->ux_status == USBD_CANCELLED || 1033 xfer->ux_status == USBD_TIMEOUT) { 1034 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1035 return; 1036 } 1037 1038 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1039 #ifdef EHCI_DEBUG 1040 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1041 ehci_dump_sqtds(ex->ex_sqtdstart); 1042 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1043 #endif 1044 1045 /* The transfer is done, compute actual length and status. */ 1046 1047 u_int xfertype, speed; 1048 1049 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1050 speed = xfer->ux_pipe->up_dev->ud_speed; 1051 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1052 /* HS isoc transfer */ 1053 1054 struct ehci_soft_itd *itd; 1055 int i, nframes, len, uframes; 1056 1057 nframes = 0; 1058 actlen = 0; 1059 1060 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1061 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1062 1063 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1064 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1065 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1066 BUS_DMASYNC_POSTREAD); 1067 1068 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1069 /* 1070 * XXX - driver didn't fill in the frame full 1071 * of uframes. This leads to scheduling 1072 * inefficiencies, but working around 1073 * this doubles complexity of tracking 1074 * an xfer. 1075 */ 1076 if (nframes >= xfer->ux_nframes) 1077 break; 1078 1079 status = le32toh(itd->itd.itd_ctl[i]); 1080 len = EHCI_ITD_GET_LEN(status); 1081 if (EHCI_ITD_GET_STATUS(status) != 0) 1082 len = 0; /*No valid data on error*/ 1083 1084 xfer->ux_frlengths[nframes++] = len; 1085 actlen += len; 1086 } 1087 1088 if (nframes >= xfer->ux_nframes) 1089 break; 1090 } 1091 1092 xfer->ux_actlen = actlen; 1093 xfer->ux_status = USBD_NORMAL_COMPLETION; 1094 goto end; 1095 } 1096 1097 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1098 /* FS isoc transfer */ 1099 struct ehci_soft_sitd *sitd; 1100 int nframes, len; 1101 1102 nframes = 0; 1103 actlen = 0; 1104 1105 for (sitd = ex->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1106 usb_syncmem(&sitd->dma,sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 1107 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 1108 BUS_DMASYNC_POSTREAD); 1109 1110 /* 1111 * XXX - driver didn't fill in the frame full 1112 * of uframes. This leads to scheduling 1113 * inefficiencies, but working around 1114 * this doubles complexity of tracking 1115 * an xfer. 1116 */ 1117 if (nframes >= xfer->ux_nframes) 1118 break; 1119 1120 status = le32toh(sitd->sitd.sitd_trans); 1121 len = EHCI_SITD_GET_LEN(status); 1122 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1123 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1124 /* No valid data on error */ 1125 len = xfer->ux_frlengths[nframes]; 1126 } 1127 1128 /* 1129 * frlengths[i]: # of bytes to send 1130 * len: # of bytes host didn't send 1131 */ 1132 xfer->ux_frlengths[nframes] -= len; 1133 /* frlengths[i]: # of bytes host sent */ 1134 actlen += xfer->ux_frlengths[nframes++]; 1135 1136 if (nframes >= xfer->ux_nframes) 1137 break; 1138 } 1139 1140 xfer->ux_actlen = actlen; 1141 xfer->ux_status = USBD_NORMAL_COMPLETION; 1142 goto end; 1143 } 1144 KASSERT(xfertype != UE_ISOCHRONOUS); 1145 1146 /* Continue processing xfers using queue heads */ 1147 1148 lsqtd = ex->ex_sqtdend; 1149 actlen = 0; 1150 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd->nextqtd; 1151 sqtd = sqtd->nextqtd) { 1152 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1153 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1154 nstatus = le32toh(sqtd->qtd.qtd_status); 1155 if (nstatus & EHCI_QTD_ACTIVE) 1156 break; 1157 1158 status = nstatus; 1159 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1160 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1161 } 1162 1163 1164 /* 1165 * If there are left over TDs we need to update the toggle. 1166 * The default pipe doesn't need it since control transfers 1167 * start the toggle at 0 every time. 1168 * For a short transfer we need to update the toggle for the missing 1169 * packets within the qTD. 1170 */ 1171 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1172 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1173 USBHIST_LOG(ehcidebug, 1174 "toggle update status=0x%08x nstatus=0x%08x", 1175 status, nstatus, 0, 0); 1176 #if 0 1177 ehci_dump_sqh(epipe->sqh); 1178 ehci_dump_sqtds(ex->ex_sqtdstart); 1179 #endif 1180 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1181 } 1182 1183 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1184 actlen, status, 0); 1185 xfer->ux_actlen = actlen; 1186 if (status & EHCI_QTD_HALTED) { 1187 #ifdef EHCI_DEBUG 1188 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1189 xfer->ux_pipe->up_dev->ud_addr, 1190 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1191 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1192 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1193 0, 0); 1194 USBHIST_LOG(ehcidebug, 1195 "active =%d halted=%d buferr=%d babble=%d", 1196 status & EHCI_QTD_ACTIVE ? 1 : 0, 1197 status & EHCI_QTD_HALTED ? 1 : 0, 1198 status & EHCI_QTD_BUFERR ? 1 : 0, 1199 status & EHCI_QTD_BABBLE ? 1 : 0); 1200 1201 USBHIST_LOG(ehcidebug, 1202 "xacterr=%d missed=%d split =%d ping =%d", 1203 status & EHCI_QTD_XACTERR ? 1 : 0, 1204 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1205 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1206 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1207 1208 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1209 ehci_dump_sqh(epipe->sqh); 1210 ehci_dump_sqtds(ex->ex_sqtdstart); 1211 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1212 #endif 1213 /* low&full speed has an extra error flag */ 1214 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1215 EHCI_QH_SPEED_HIGH) 1216 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1217 else 1218 status &= EHCI_QTD_STATERRS; 1219 if (status == 0) /* no other errors means a stall */ { 1220 xfer->ux_status = USBD_STALLED; 1221 } else { 1222 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1223 } 1224 /* XXX need to reset TT on missed microframe */ 1225 if (status & EHCI_QTD_MISSEDMICRO) { 1226 printf("%s: missed microframe, TT reset not " 1227 "implemented, hub might be inoperational\n", 1228 device_xname(sc->sc_dev)); 1229 } 1230 } else { 1231 xfer->ux_status = USBD_NORMAL_COMPLETION; 1232 } 1233 1234 end: 1235 /* 1236 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1237 * during this call, before methods->done is called: dma sync required 1238 * beforehand? 1239 */ 1240 usb_transfer_complete(xfer); 1241 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1242 } 1243 1244 /* 1245 * Wait here until controller claims to have an interrupt. 1246 * Then call ehci_intr and return. Use timeout to avoid waiting 1247 * too long. 1248 */ 1249 Static void 1250 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1251 { 1252 int timo; 1253 uint32_t intrs; 1254 1255 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1256 1257 xfer->ux_status = USBD_IN_PROGRESS; 1258 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1259 usb_delay_ms(&sc->sc_bus, 1); 1260 if (sc->sc_dying) 1261 break; 1262 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1263 sc->sc_eintrs; 1264 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1265 #ifdef EHCI_DEBUG 1266 if (ehcidebug > 15) 1267 ehci_dump_regs(sc); 1268 #endif 1269 if (intrs) { 1270 mutex_spin_enter(&sc->sc_intr_lock); 1271 ehci_intr1(sc); 1272 mutex_spin_exit(&sc->sc_intr_lock); 1273 if (xfer->ux_status != USBD_IN_PROGRESS) 1274 return; 1275 } 1276 } 1277 1278 /* Timeout */ 1279 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1280 xfer->ux_status = USBD_TIMEOUT; 1281 mutex_enter(&sc->sc_lock); 1282 usb_transfer_complete(xfer); 1283 mutex_exit(&sc->sc_lock); 1284 /* XXX should free TD */ 1285 } 1286 1287 Static void 1288 ehci_poll(struct usbd_bus *bus) 1289 { 1290 ehci_softc_t *sc = bus->ub_hcpriv; 1291 1292 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1293 1294 #ifdef EHCI_DEBUG 1295 static int last; 1296 int new; 1297 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1298 if (new != last) { 1299 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1300 last = new; 1301 } 1302 #endif 1303 1304 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1305 mutex_spin_enter(&sc->sc_intr_lock); 1306 ehci_intr1(sc); 1307 mutex_spin_exit(&sc->sc_intr_lock); 1308 } 1309 } 1310 1311 void 1312 ehci_childdet(device_t self, device_t child) 1313 { 1314 struct ehci_softc *sc = device_private(self); 1315 1316 KASSERT(sc->sc_child == child); 1317 sc->sc_child = NULL; 1318 } 1319 1320 int 1321 ehci_detach(struct ehci_softc *sc, int flags) 1322 { 1323 int rv = 0; 1324 1325 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1326 1327 if (sc->sc_child != NULL) 1328 rv = config_detach(sc->sc_child, flags); 1329 1330 if (rv != 0) 1331 return rv; 1332 1333 callout_halt(&sc->sc_tmo_intrlist, NULL); 1334 callout_destroy(&sc->sc_tmo_intrlist); 1335 1336 /* XXX free other data structures XXX */ 1337 if (sc->sc_softitds) 1338 kmem_free(sc->sc_softitds, 1339 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1340 cv_destroy(&sc->sc_doorbell); 1341 cv_destroy(&sc->sc_softwake_cv); 1342 1343 #if 0 1344 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1345 1346 softint_disestablish(sc->sc_doorbell_si); 1347 softint_disestablish(sc->sc_pcd_si); 1348 1349 mutex_destroy(&sc->sc_lock); 1350 mutex_destroy(&sc->sc_intr_lock); 1351 #endif 1352 1353 pool_cache_destroy(sc->sc_xferpool); 1354 1355 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1356 1357 return rv; 1358 } 1359 1360 1361 int 1362 ehci_activate(device_t self, enum devact act) 1363 { 1364 struct ehci_softc *sc = device_private(self); 1365 1366 switch (act) { 1367 case DVACT_DEACTIVATE: 1368 sc->sc_dying = 1; 1369 return 0; 1370 default: 1371 return EOPNOTSUPP; 1372 } 1373 } 1374 1375 /* 1376 * Handle suspend/resume. 1377 * 1378 * We need to switch to polling mode here, because this routine is 1379 * called from an interrupt context. This is all right since we 1380 * are almost suspended anyway. 1381 * 1382 * Note that this power handler isn't to be registered directly; the 1383 * bus glue needs to call out to it. 1384 */ 1385 bool 1386 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1387 { 1388 ehci_softc_t *sc = device_private(dv); 1389 int i; 1390 uint32_t cmd, hcr; 1391 1392 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1393 1394 mutex_spin_enter(&sc->sc_intr_lock); 1395 sc->sc_bus.ub_usepolling++; 1396 mutex_spin_exit(&sc->sc_intr_lock); 1397 1398 for (i = 1; i <= sc->sc_noport; i++) { 1399 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1400 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1401 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1402 } 1403 1404 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1405 1406 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1407 EOWRITE4(sc, EHCI_USBCMD, cmd); 1408 1409 for (i = 0; i < 100; i++) { 1410 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1411 if (hcr == 0) 1412 break; 1413 1414 usb_delay_ms(&sc->sc_bus, 1); 1415 } 1416 if (hcr != 0) 1417 printf("%s: reset timeout\n", device_xname(dv)); 1418 1419 cmd &= ~EHCI_CMD_RS; 1420 EOWRITE4(sc, EHCI_USBCMD, cmd); 1421 1422 for (i = 0; i < 100; i++) { 1423 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1424 if (hcr == EHCI_STS_HCH) 1425 break; 1426 1427 usb_delay_ms(&sc->sc_bus, 1); 1428 } 1429 if (hcr != EHCI_STS_HCH) 1430 printf("%s: config timeout\n", device_xname(dv)); 1431 1432 mutex_spin_enter(&sc->sc_intr_lock); 1433 sc->sc_bus.ub_usepolling--; 1434 mutex_spin_exit(&sc->sc_intr_lock); 1435 1436 return true; 1437 } 1438 1439 bool 1440 ehci_resume(device_t dv, const pmf_qual_t *qual) 1441 { 1442 ehci_softc_t *sc = device_private(dv); 1443 int i; 1444 uint32_t cmd, hcr; 1445 1446 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1447 1448 /* restore things in case the bios sucks */ 1449 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1450 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1451 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1452 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1453 1454 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1455 1456 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1457 1458 hcr = 0; 1459 for (i = 1; i <= sc->sc_noport; i++) { 1460 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1461 if ((cmd & EHCI_PS_PO) == 0 && 1462 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1463 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1464 hcr = 1; 1465 } 1466 } 1467 1468 if (hcr) { 1469 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1470 1471 for (i = 1; i <= sc->sc_noport; i++) { 1472 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1473 if ((cmd & EHCI_PS_PO) == 0 && 1474 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1475 EOWRITE4(sc, EHCI_PORTSC(i), 1476 cmd & ~EHCI_PS_FPR); 1477 } 1478 } 1479 1480 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1481 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1482 1483 for (i = 0; i < 100; i++) { 1484 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1485 if (hcr != EHCI_STS_HCH) 1486 break; 1487 1488 usb_delay_ms(&sc->sc_bus, 1); 1489 } 1490 if (hcr == EHCI_STS_HCH) 1491 printf("%s: config timeout\n", device_xname(dv)); 1492 1493 return true; 1494 } 1495 1496 /* 1497 * Shut down the controller when the system is going down. 1498 */ 1499 bool 1500 ehci_shutdown(device_t self, int flags) 1501 { 1502 ehci_softc_t *sc = device_private(self); 1503 1504 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1505 1506 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1507 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1508 return true; 1509 } 1510 1511 Static usbd_xfer_handle 1512 ehci_allocx(struct usbd_bus *bus) 1513 { 1514 struct ehci_softc *sc = bus->ub_hcpriv; 1515 usbd_xfer_handle xfer; 1516 1517 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1518 if (xfer != NULL) { 1519 memset(xfer, 0, sizeof(struct ehci_xfer)); 1520 #ifdef DIAGNOSTIC 1521 EXFER(xfer)->ex_isdone = true; 1522 xfer->ux_state = XFER_BUSY; 1523 #endif 1524 } 1525 return xfer; 1526 } 1527 1528 Static void 1529 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1530 { 1531 struct ehci_softc *sc = bus->ub_hcpriv; 1532 1533 KASSERT(xfer->ux_state == XFER_BUSY); 1534 KASSERT(EXFER(xfer)->ex_isdone); 1535 #ifdef DIAGNOSTIC 1536 xfer->ux_state = XFER_FREE; 1537 #endif 1538 pool_cache_put(sc->sc_xferpool, xfer); 1539 } 1540 1541 Static void 1542 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1543 { 1544 struct ehci_softc *sc = bus->ub_hcpriv; 1545 1546 *lock = &sc->sc_lock; 1547 } 1548 1549 Static void 1550 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1551 { 1552 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1553 1554 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1555 1556 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1557 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1558 #ifdef EHCI_DEBUG 1559 if (ehcidebug) 1560 usbd_dump_pipe(pipe); 1561 #endif 1562 epipe->nexttoggle = 0; 1563 } 1564 1565 Static void 1566 ehci_noop(usbd_pipe_handle pipe) 1567 { 1568 } 1569 1570 #ifdef EHCI_DEBUG 1571 /* 1572 * Unused function - this is meant to be called from a kernel 1573 * debugger. 1574 */ 1575 void 1576 ehci_dump(void) 1577 { 1578 ehci_softc_t *sc = theehci; 1579 int i; 1580 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1581 EOREAD4(sc, EHCI_USBCMD), 1582 EOREAD4(sc, EHCI_USBSTS), 1583 EOREAD4(sc, EHCI_USBINTR)); 1584 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1585 EOREAD4(sc, EHCI_FRINDEX), 1586 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1587 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1588 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1589 for (i = 1; i <= sc->sc_noport; i++) 1590 printf("port %d status=0x%08x\n", i, 1591 EOREAD4(sc, EHCI_PORTSC(i))); 1592 } 1593 1594 Static void 1595 ehci_dump_regs(ehci_softc_t *sc) 1596 { 1597 int i; 1598 1599 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1600 1601 USBHIST_LOG(ehcidebug, 1602 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1603 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1604 EOREAD4(sc, EHCI_USBINTR), 0); 1605 USBHIST_LOG(ehcidebug, 1606 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1607 "async = 0x%08x", 1608 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1609 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1610 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1611 for (i = 1; i <= sc->sc_noport; i += 2) { 1612 if (i == sc->sc_noport) { 1613 USBHIST_LOG(ehcidebug, 1614 "port %d status = 0x%08x", i, 1615 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1616 } else { 1617 USBHIST_LOG(ehcidebug, 1618 "port %d status = 0x%08x port %d status = 0x%08x", 1619 i, EOREAD4(sc, EHCI_PORTSC(i)), 1620 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1621 } 1622 } 1623 } 1624 1625 #ifdef EHCI_DEBUG 1626 #define ehci_dump_link(link, type) do { \ 1627 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1628 link, \ 1629 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1630 if (type) { \ 1631 USBHIST_LOG(ehcidebug, \ 1632 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1633 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1634 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1635 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1636 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1637 } \ 1638 } while(0) 1639 #else 1640 #define ehci_dump_link(link, type) 1641 #endif 1642 1643 Static void 1644 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1645 { 1646 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1647 int i; 1648 uint32_t stop = 0; 1649 1650 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1651 ehci_dump_sqtd(sqtd); 1652 usb_syncmem(&sqtd->dma, 1653 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1654 sizeof(sqtd->qtd), 1655 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1656 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1657 usb_syncmem(&sqtd->dma, 1658 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1659 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1660 } 1661 if (!stop) 1662 USBHIST_LOG(ehcidebug, 1663 "dump aborted, too many TDs", 0, 0, 0, 0); 1664 } 1665 1666 Static void 1667 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1668 { 1669 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1670 1671 usb_syncmem(&sqtd->dma, sqtd->offs, 1672 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1673 1674 USBHIST_LOGN(ehcidebug, 10, 1675 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1676 ehci_dump_qtd(&sqtd->qtd); 1677 1678 usb_syncmem(&sqtd->dma, sqtd->offs, 1679 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1680 } 1681 1682 Static void 1683 ehci_dump_qtd(ehci_qtd_t *qtd) 1684 { 1685 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1686 1687 #ifdef USBHIST 1688 uint32_t s = le32toh(qtd->qtd_status); 1689 #endif 1690 1691 USBHIST_LOGN(ehcidebug, 10, 1692 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1693 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1694 USBHIST_LOGN(ehcidebug, 10, 1695 " toggle = %d ioc = %d bytes = %#x " 1696 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1697 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1698 USBHIST_LOGN(ehcidebug, 10, 1699 " cerr = %d pid = %d stat = %x", 1700 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1701 0); 1702 USBHIST_LOGN(ehcidebug, 10, 1703 "active =%d halted=%d buferr=%d babble=%d", 1704 s & EHCI_QTD_ACTIVE ? 1 : 0, 1705 s & EHCI_QTD_HALTED ? 1 : 0, 1706 s & EHCI_QTD_BUFERR ? 1 : 0, 1707 s & EHCI_QTD_BABBLE ? 1 : 0); 1708 USBHIST_LOGN(ehcidebug, 10, 1709 "xacterr=%d missed=%d split =%d ping =%d", 1710 s & EHCI_QTD_XACTERR ? 1 : 0, 1711 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1712 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1713 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1714 USBHIST_LOGN(ehcidebug, 10, 1715 "buffer[0] = %#x buffer[1] = %#x " 1716 "buffer[2] = %#x buffer[3] = %#x", 1717 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1718 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1719 USBHIST_LOGN(ehcidebug, 10, 1720 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1721 } 1722 1723 Static void 1724 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1725 { 1726 #ifdef USBHIST 1727 ehci_qh_t *qh = &sqh->qh; 1728 ehci_link_t link; 1729 #endif 1730 uint32_t endp, endphub; 1731 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1732 1733 usb_syncmem(&sqh->dma, sqh->offs, 1734 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1735 1736 USBHIST_LOGN(ehcidebug, 10, 1737 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1738 link = le32toh(qh->qh_link); 1739 ehci_dump_link(link, true); 1740 1741 endp = le32toh(qh->qh_endp); 1742 USBHIST_LOGN(ehcidebug, 10, 1743 " endp = %#x", endp, 0, 0, 0); 1744 USBHIST_LOGN(ehcidebug, 10, 1745 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1746 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1747 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1748 USBHIST_LOGN(ehcidebug, 10, 1749 " dtc = %d hrecl = %d", 1750 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1751 USBHIST_LOGN(ehcidebug, 10, 1752 " ctl = %d nrl = %d mpl = %#x(%d)", 1753 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1754 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1755 1756 endphub = le32toh(qh->qh_endphub); 1757 USBHIST_LOGN(ehcidebug, 10, 1758 " endphub = %#x", endphub, 0, 0, 0); 1759 USBHIST_LOGN(ehcidebug, 10, 1760 " smask = 0x%02x cmask = 0x%02x", 1761 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1762 USBHIST_LOGN(ehcidebug, 10, 1763 " huba = 0x%02x port = %d mult = %d", 1764 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1765 EHCI_QH_GET_MULT(endphub), 0); 1766 1767 link = le32toh(qh->qh_curqtd); 1768 ehci_dump_link(link, false); 1769 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1770 ehci_dump_qtd(&qh->qh_qtd); 1771 1772 usb_syncmem(&sqh->dma, sqh->offs, 1773 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1774 } 1775 1776 Static void 1777 ehci_dump_itd(struct ehci_soft_itd *itd) 1778 { 1779 ehci_isoc_trans_t t; 1780 ehci_isoc_bufr_ptr_t b, b2, b3; 1781 int i; 1782 1783 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1784 1785 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1786 0, 0); 1787 1788 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1789 t = le32toh(itd->itd.itd_ctl[i]); 1790 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1791 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1792 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1793 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1794 EHCI_ITD_GET_OFFS(t), 0); 1795 } 1796 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1797 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1798 USBHIST_LOG(ehcidebug, " %x", 1799 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1800 1801 b = le32toh(itd->itd.itd_bufr[0]); 1802 b2 = le32toh(itd->itd.itd_bufr[1]); 1803 b3 = le32toh(itd->itd.itd_bufr[2]); 1804 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1805 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1806 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1807 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1808 } 1809 1810 Static void 1811 ehci_dump_sitd(struct ehci_soft_itd *itd) 1812 { 1813 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1814 1815 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1816 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1817 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1818 itd->xfer_next, itd->physaddr, itd->slot, 0); 1819 } 1820 1821 Static void 1822 ehci_dump_exfer(struct ehci_xfer *ex) 1823 { 1824 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1825 1826 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1827 ex, ex->ex_sqtdstart, ex->ex_sqtdend, 0); 1828 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1829 ex->ex_itdstart, ex->ex_itdend, ex->ex_isdone, 0); 1830 } 1831 #endif 1832 1833 Static usbd_status 1834 ehci_open(usbd_pipe_handle pipe) 1835 { 1836 usbd_device_handle dev = pipe->up_dev; 1837 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1838 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1839 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1840 uint8_t addr = dev->ud_addr; 1841 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1842 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1843 ehci_soft_qh_t *sqh; 1844 usbd_status err; 1845 int ival, speed, naks; 1846 int hshubaddr, hshubport; 1847 1848 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1849 1850 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1851 pipe, addr, ed->bEndpointAddress, rhaddr); 1852 1853 if (dev->ud_myhsport) { 1854 /* 1855 * When directly attached FS/LS device while doing embedded 1856 * transaction translations and we are the hub, set the hub 1857 * address to 0 (us). 1858 */ 1859 if (!(sc->sc_flags & EHCIF_ETTF) 1860 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1861 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1862 } else { 1863 hshubaddr = 0; 1864 } 1865 hshubport = dev->ud_myhsport->up_portno; 1866 } else { 1867 hshubaddr = 0; 1868 hshubport = 0; 1869 } 1870 1871 if (sc->sc_dying) 1872 return USBD_IOERROR; 1873 1874 /* toggle state needed for bulk endpoints */ 1875 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1876 1877 if (addr == rhaddr) { 1878 switch (ed->bEndpointAddress) { 1879 case USB_CONTROL_ENDPOINT: 1880 pipe->up_methods = &roothub_ctrl_methods; 1881 break; 1882 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1883 pipe->up_methods = &ehci_root_intr_methods; 1884 break; 1885 default: 1886 USBHIST_LOG(ehcidebug, 1887 "bad bEndpointAddress 0x%02x", 1888 ed->bEndpointAddress, 0, 0, 0); 1889 return USBD_INVAL; 1890 } 1891 return USBD_NORMAL_COMPLETION; 1892 } 1893 1894 /* XXX All this stuff is only valid for async. */ 1895 switch (dev->ud_speed) { 1896 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1897 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1898 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1899 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1900 } 1901 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1902 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1903 hshubaddr, hshubport, 0, 0); 1904 return USBD_INVAL; 1905 } 1906 1907 /* 1908 * For interrupt transfer, nak throttling must be disabled, but for 1909 * the other transfer type, nak throttling should be enabled from the 1910 * viewpoint that avoids the memory thrashing. 1911 */ 1912 naks = (xfertype == UE_INTERRUPT) ? 0 1913 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1914 1915 /* Allocate sqh for everything, save isoc xfers */ 1916 if (xfertype != UE_ISOCHRONOUS) { 1917 sqh = ehci_alloc_sqh(sc); 1918 if (sqh == NULL) 1919 return USBD_NOMEM; 1920 /* qh_link filled when the QH is added */ 1921 sqh->qh.qh_endp = htole32( 1922 EHCI_QH_SET_ADDR(addr) | 1923 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1924 EHCI_QH_SET_EPS(speed) | 1925 EHCI_QH_DTC | 1926 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1927 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1928 EHCI_QH_CTL : 0) | 1929 EHCI_QH_SET_NRL(naks) 1930 ); 1931 sqh->qh.qh_endphub = htole32( 1932 EHCI_QH_SET_MULT(1) | 1933 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1934 ); 1935 if (speed != EHCI_QH_SPEED_HIGH) 1936 sqh->qh.qh_endphub |= htole32( 1937 EHCI_QH_SET_PORT(hshubport) | 1938 EHCI_QH_SET_HUBA(hshubaddr) | 1939 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1940 ); 1941 sqh->qh.qh_curqtd = EHCI_NULL; 1942 /* Fill the overlay qTD */ 1943 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1944 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1945 sqh->qh.qh_qtd.qtd_status = htole32(0); 1946 1947 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1948 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1949 epipe->sqh = sqh; 1950 } else { 1951 sqh = NULL; 1952 } /*xfertype == UE_ISOC*/ 1953 1954 switch (xfertype) { 1955 case UE_CONTROL: 1956 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1957 0, &epipe->u.ctl.reqdma); 1958 #ifdef EHCI_DEBUG 1959 if (err) 1960 printf("ehci_open: usb_allocmem()=%d\n", err); 1961 #endif 1962 if (err) 1963 goto bad; 1964 pipe->up_methods = &ehci_device_ctrl_methods; 1965 mutex_enter(&sc->sc_lock); 1966 ehci_add_qh(sc, sqh, sc->sc_async_head); 1967 mutex_exit(&sc->sc_lock); 1968 break; 1969 case UE_BULK: 1970 pipe->up_methods = &ehci_device_bulk_methods; 1971 mutex_enter(&sc->sc_lock); 1972 ehci_add_qh(sc, sqh, sc->sc_async_head); 1973 mutex_exit(&sc->sc_lock); 1974 break; 1975 case UE_INTERRUPT: 1976 pipe->up_methods = &ehci_device_intr_methods; 1977 ival = pipe->up_interval; 1978 if (ival == USBD_DEFAULT_INTERVAL) { 1979 if (speed == EHCI_QH_SPEED_HIGH) { 1980 if (ed->bInterval > 16) { 1981 /* 1982 * illegal with high-speed, but there 1983 * were documentation bugs in the spec, 1984 * so be generous 1985 */ 1986 ival = 256; 1987 } else 1988 ival = (1 << (ed->bInterval - 1)) / 8; 1989 } else 1990 ival = ed->bInterval; 1991 } 1992 err = ehci_device_setintr(sc, sqh, ival); 1993 if (err) 1994 goto bad; 1995 break; 1996 case UE_ISOCHRONOUS: 1997 if (speed == EHCI_QH_SPEED_HIGH) 1998 pipe->up_methods = &ehci_device_isoc_methods; 1999 else 2000 pipe->up_methods = &ehci_device_fs_isoc_methods; 2001 if (ed->bInterval == 0 || ed->bInterval > 16) { 2002 printf("ehci: opening pipe with invalid bInterval\n"); 2003 err = USBD_INVAL; 2004 goto bad; 2005 } 2006 if (UGETW(ed->wMaxPacketSize) == 0) { 2007 printf("ehci: zero length endpoint open request\n"); 2008 err = USBD_INVAL; 2009 goto bad; 2010 } 2011 epipe->u.isoc.next_frame = 0; 2012 epipe->u.isoc.cur_xfers = 0; 2013 break; 2014 default: 2015 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2016 err = USBD_INVAL; 2017 goto bad; 2018 } 2019 return USBD_NORMAL_COMPLETION; 2020 2021 bad: 2022 if (sqh != NULL) 2023 ehci_free_sqh(sc, sqh); 2024 return err; 2025 } 2026 2027 /* 2028 * Add an ED to the schedule. Called with USB lock held. 2029 */ 2030 Static void 2031 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2032 { 2033 2034 KASSERT(mutex_owned(&sc->sc_lock)); 2035 2036 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2037 2038 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2039 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2040 2041 sqh->next = head->next; 2042 sqh->qh.qh_link = head->qh.qh_link; 2043 2044 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2045 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2046 2047 head->next = sqh; 2048 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2049 2050 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2051 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2052 2053 #ifdef EHCI_DEBUG 2054 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2055 ehci_dump_sqh(sqh); 2056 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2057 #endif 2058 } 2059 2060 /* 2061 * Remove an ED from the schedule. Called with USB lock held. 2062 */ 2063 Static void 2064 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2065 { 2066 ehci_soft_qh_t *p; 2067 2068 KASSERT(mutex_owned(&sc->sc_lock)); 2069 2070 /* XXX */ 2071 for (p = head; p != NULL && p->next != sqh; p = p->next) 2072 ; 2073 if (p == NULL) 2074 panic("ehci_rem_qh: ED not found"); 2075 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2076 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2077 p->next = sqh->next; 2078 p->qh.qh_link = sqh->qh.qh_link; 2079 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2080 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2081 2082 ehci_sync_hc(sc); 2083 } 2084 2085 Static void 2086 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2087 { 2088 int i; 2089 uint32_t status; 2090 2091 /* Save toggle bit and ping status. */ 2092 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2093 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2094 status = sqh->qh.qh_qtd.qtd_status & 2095 htole32(EHCI_QTD_TOGGLE_MASK | 2096 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2097 /* Set HALTED to make hw leave it alone. */ 2098 sqh->qh.qh_qtd.qtd_status = 2099 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2100 usb_syncmem(&sqh->dma, 2101 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2102 sizeof(sqh->qh.qh_qtd.qtd_status), 2103 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2104 sqh->qh.qh_curqtd = 0; 2105 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2106 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2107 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2108 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2109 sqh->sqtd = sqtd; 2110 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2111 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2112 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2113 sqh->qh.qh_qtd.qtd_status = status; 2114 usb_syncmem(&sqh->dma, 2115 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2116 sizeof(sqh->qh.qh_qtd.qtd_status), 2117 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2118 } 2119 2120 /* 2121 * Ensure that the HC has released all references to the QH. We do this 2122 * by asking for a Async Advance Doorbell interrupt and then we wait for 2123 * the interrupt. 2124 * To make this easier we first obtain exclusive use of the doorbell. 2125 */ 2126 Static void 2127 ehci_sync_hc(ehci_softc_t *sc) 2128 { 2129 int error __diagused; 2130 2131 KASSERT(mutex_owned(&sc->sc_lock)); 2132 2133 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2134 2135 if (sc->sc_dying) { 2136 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2137 return; 2138 } 2139 /* ask for doorbell */ 2140 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2141 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2142 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2143 2144 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2145 2146 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2147 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2148 #ifdef DIAGNOSTIC 2149 if (error) 2150 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2151 #endif 2152 } 2153 2154 Static void 2155 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2156 { 2157 struct ehci_soft_itd *itd, *prev; 2158 2159 prev = NULL; 2160 2161 if (exfer->ex_itdstart == NULL || exfer->ex_itdend == NULL) 2162 panic("ehci isoc xfer being freed, but with no itd chain\n"); 2163 2164 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2165 prev = itd->u.frame_list.prev; 2166 /* Unlink itd from hardware chain, or frame array */ 2167 if (prev == NULL) { /* We're at the table head */ 2168 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2169 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2170 usb_syncmem(&sc->sc_fldma, 2171 sizeof(ehci_link_t) * itd->slot, 2172 sizeof(ehci_link_t), 2173 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2174 2175 if (itd->u.frame_list.next != NULL) 2176 itd->u.frame_list.next->u.frame_list.prev = NULL; 2177 } else { 2178 /* XXX this part is untested... */ 2179 prev->itd.itd_next = itd->itd.itd_next; 2180 usb_syncmem(&itd->dma, 2181 itd->offs + offsetof(ehci_itd_t, itd_next), 2182 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2183 2184 prev->u.frame_list.next = itd->u.frame_list.next; 2185 if (itd->u.frame_list.next != NULL) 2186 itd->u.frame_list.next->u.frame_list.prev = prev; 2187 } 2188 } 2189 2190 prev = NULL; 2191 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2192 if (prev != NULL) 2193 ehci_free_itd(sc, prev); 2194 prev = itd; 2195 } 2196 if (prev) 2197 ehci_free_itd(sc, prev); 2198 exfer->ex_itdstart = NULL; 2199 exfer->ex_itdend = NULL; 2200 } 2201 2202 Static void 2203 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2204 { 2205 struct ehci_soft_sitd *sitd, *prev; 2206 2207 prev = NULL; 2208 2209 if (exfer->ex_sitdstart == NULL || exfer->ex_sitdend == NULL) 2210 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2211 2212 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2213 prev = sitd->u.frame_list.prev; 2214 /* Unlink sitd from hardware chain, or frame array */ 2215 if (prev == NULL) { /* We're at the table head */ 2216 sc->sc_softsitds[sitd->slot] = sitd->u.frame_list.next; 2217 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2218 usb_syncmem(&sc->sc_fldma, 2219 sizeof(ehci_link_t) * sitd->slot, 2220 sizeof(ehci_link_t), 2221 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2222 2223 if (sitd->u.frame_list.next != NULL) 2224 sitd->u.frame_list.next->u.frame_list.prev = NULL; 2225 } else { 2226 /* XXX this part is untested... */ 2227 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2228 usb_syncmem(&sitd->dma, 2229 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2230 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2231 2232 prev->u.frame_list.next = sitd->u.frame_list.next; 2233 if (sitd->u.frame_list.next != NULL) 2234 sitd->u.frame_list.next->u.frame_list.prev = prev; 2235 } 2236 } 2237 2238 prev = NULL; 2239 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2240 if (prev != NULL) 2241 ehci_free_sitd(sc, prev); 2242 prev = sitd; 2243 } 2244 if (prev) 2245 ehci_free_sitd(sc, prev); 2246 exfer->ex_sitdstart = NULL; 2247 exfer->ex_sitdend = NULL; 2248 } 2249 2250 /***********/ 2251 2252 Static int 2253 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2254 void *buf, int buflen) 2255 { 2256 ehci_softc_t *sc = bus->ub_hcpriv; 2257 usb_hub_descriptor_t hubd; 2258 usb_port_status_t ps; 2259 uint16_t len, value, index; 2260 int l, totlen = 0; 2261 int port, i; 2262 uint32_t v; 2263 2264 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2265 2266 if (sc->sc_dying) 2267 return -1; 2268 2269 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2270 req->bmRequestType, req->bRequest, 0, 0); 2271 2272 len = UGETW(req->wLength); 2273 value = UGETW(req->wValue); 2274 index = UGETW(req->wIndex); 2275 2276 #define C(x,y) ((x) | ((y) << 8)) 2277 switch (C(req->bRequest, req->bmRequestType)) { 2278 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2279 if (len == 0) 2280 break; 2281 switch (value) { 2282 case C(0, UDESC_DEVICE): { 2283 usb_device_descriptor_t devd; 2284 totlen = min(buflen, sizeof(devd)); 2285 memcpy(&devd, buf, totlen); 2286 USETW(devd.idVendor, sc->sc_id_vendor); 2287 memcpy(buf, &devd, totlen); 2288 break; 2289 2290 } 2291 #define sd ((usb_string_descriptor_t *)buf) 2292 case C(1, UDESC_STRING): 2293 /* Vendor */ 2294 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2295 break; 2296 case C(2, UDESC_STRING): 2297 /* Product */ 2298 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2299 break; 2300 #undef sd 2301 default: 2302 /* default from usbroothub */ 2303 return buflen; 2304 } 2305 break; 2306 2307 /* Hub requests */ 2308 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2309 break; 2310 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2311 USBHIST_LOG(ehcidebug, 2312 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2313 0, 0); 2314 if (index < 1 || index > sc->sc_noport) { 2315 return -1; 2316 } 2317 port = EHCI_PORTSC(index); 2318 v = EOREAD4(sc, port); 2319 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2320 v &= ~EHCI_PS_CLEAR; 2321 switch (value) { 2322 case UHF_PORT_ENABLE: 2323 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2324 break; 2325 case UHF_PORT_SUSPEND: 2326 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2327 break; 2328 v &= ~EHCI_PS_SUSP; 2329 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2330 /* see USB2 spec ch. 7.1.7.7 */ 2331 usb_delay_ms(&sc->sc_bus, 20); 2332 EOWRITE4(sc, port, v); 2333 usb_delay_ms(&sc->sc_bus, 2); 2334 #ifdef DEBUG 2335 v = EOREAD4(sc, port); 2336 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2337 printf("ehci: resume failed: %x\n", v); 2338 #endif 2339 break; 2340 case UHF_PORT_POWER: 2341 if (sc->sc_hasppc) 2342 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2343 break; 2344 case UHF_PORT_TEST: 2345 USBHIST_LOG(ehcidebug, "clear port test " 2346 "%d", index, 0, 0, 0); 2347 break; 2348 case UHF_PORT_INDICATOR: 2349 USBHIST_LOG(ehcidebug, "clear port ind " 2350 "%d", index, 0, 0, 0); 2351 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2352 break; 2353 case UHF_C_PORT_CONNECTION: 2354 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2355 break; 2356 case UHF_C_PORT_ENABLE: 2357 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2358 break; 2359 case UHF_C_PORT_SUSPEND: 2360 /* how? */ 2361 break; 2362 case UHF_C_PORT_OVER_CURRENT: 2363 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2364 break; 2365 case UHF_C_PORT_RESET: 2366 sc->sc_isreset[index] = 0; 2367 break; 2368 default: 2369 return -1; 2370 } 2371 #if 0 2372 switch(value) { 2373 case UHF_C_PORT_CONNECTION: 2374 case UHF_C_PORT_ENABLE: 2375 case UHF_C_PORT_SUSPEND: 2376 case UHF_C_PORT_OVER_CURRENT: 2377 case UHF_C_PORT_RESET: 2378 default: 2379 break; 2380 } 2381 #endif 2382 break; 2383 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2384 if (len == 0) 2385 break; 2386 if ((value & 0xff) != 0) { 2387 return -1; 2388 } 2389 totlen = min(buflen, sizeof(hubd)); 2390 memcpy(&hubd, buf, totlen); 2391 hubd.bNbrPorts = sc->sc_noport; 2392 v = EOREAD4(sc, EHCI_HCSPARAMS); 2393 USETW(hubd.wHubCharacteristics, 2394 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2395 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2396 ? UHD_PORT_IND : 0); 2397 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2398 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2399 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2400 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2401 totlen = min(totlen, hubd.bDescLength); 2402 memcpy(buf, &hubd, totlen); 2403 break; 2404 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2405 if (len != 4) { 2406 return -1; 2407 } 2408 memset(buf, 0, len); /* ? XXX */ 2409 totlen = len; 2410 break; 2411 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2412 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2413 if (index < 1 || index > sc->sc_noport) { 2414 return -1; 2415 } 2416 if (len != 4) { 2417 return -1; 2418 } 2419 v = EOREAD4(sc, EHCI_PORTSC(index)); 2420 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2421 2422 i = UPS_HIGH_SPEED; 2423 if (sc->sc_flags & EHCIF_ETTF) { 2424 /* 2425 * If we are doing embedded transaction translation, 2426 * then directly attached LS/FS devices are reset by 2427 * the EHCI controller itself. PSPD is encoded 2428 * the same way as in USBSTATUS. 2429 */ 2430 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2431 } 2432 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2433 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2434 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2435 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2436 if (v & EHCI_PS_PR) i |= UPS_RESET; 2437 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2438 if (sc->sc_vendor_port_status) 2439 i = sc->sc_vendor_port_status(sc, v, i); 2440 USETW(ps.wPortStatus, i); 2441 i = 0; 2442 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2443 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2444 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2445 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2446 USETW(ps.wPortChange, i); 2447 totlen = min(len, sizeof(ps)); 2448 memcpy(buf, &ps, totlen); 2449 break; 2450 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2451 return -1; 2452 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2453 break; 2454 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2455 if (index < 1 || index > sc->sc_noport) { 2456 return -1; 2457 } 2458 port = EHCI_PORTSC(index); 2459 v = EOREAD4(sc, port); 2460 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2461 v &= ~EHCI_PS_CLEAR; 2462 switch(value) { 2463 case UHF_PORT_ENABLE: 2464 EOWRITE4(sc, port, v | EHCI_PS_PE); 2465 break; 2466 case UHF_PORT_SUSPEND: 2467 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2468 break; 2469 case UHF_PORT_RESET: 2470 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2471 if (EHCI_PS_IS_LOWSPEED(v) 2472 && sc->sc_ncomp > 0 2473 && !(sc->sc_flags & EHCIF_ETTF)) { 2474 /* 2475 * Low speed device on non-ETTF controller or 2476 * unaccompanied controller, give up ownership. 2477 */ 2478 ehci_disown(sc, index, 1); 2479 break; 2480 } 2481 /* Start reset sequence. */ 2482 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2483 EOWRITE4(sc, port, v | EHCI_PS_PR); 2484 /* Wait for reset to complete. */ 2485 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2486 if (sc->sc_dying) { 2487 return -1; 2488 } 2489 /* 2490 * An embedded transaction translator will automatically 2491 * terminate the reset sequence so there's no need to 2492 * it. 2493 */ 2494 v = EOREAD4(sc, port); 2495 if (v & EHCI_PS_PR) { 2496 /* Terminate reset sequence. */ 2497 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2498 /* Wait for HC to complete reset. */ 2499 usb_delay_ms(&sc->sc_bus, 2500 EHCI_PORT_RESET_COMPLETE); 2501 if (sc->sc_dying) { 2502 return -1; 2503 } 2504 } 2505 2506 v = EOREAD4(sc, port); 2507 USBHIST_LOG(ehcidebug, 2508 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2509 if (v & EHCI_PS_PR) { 2510 printf("%s: port reset timeout\n", 2511 device_xname(sc->sc_dev)); 2512 return USBD_TIMEOUT; 2513 } 2514 if (!(v & EHCI_PS_PE)) { 2515 /* Not a high speed device, give up ownership.*/ 2516 ehci_disown(sc, index, 0); 2517 break; 2518 } 2519 sc->sc_isreset[index] = 1; 2520 USBHIST_LOG(ehcidebug, 2521 "ehci port %d reset, status = 0x%08x", index, v, 0, 2522 0); 2523 break; 2524 case UHF_PORT_POWER: 2525 USBHIST_LOG(ehcidebug, 2526 "set port power %d (has PPC = %d)", index, 2527 sc->sc_hasppc, 0, 0); 2528 if (sc->sc_hasppc) 2529 EOWRITE4(sc, port, v | EHCI_PS_PP); 2530 break; 2531 case UHF_PORT_TEST: 2532 USBHIST_LOG(ehcidebug, "set port test %d", 2533 index, 0, 0, 0); 2534 break; 2535 case UHF_PORT_INDICATOR: 2536 USBHIST_LOG(ehcidebug, "set port ind %d", 2537 index, 0, 0, 0); 2538 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2539 break; 2540 default: 2541 return -1; 2542 } 2543 break; 2544 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2545 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2546 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2547 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2548 break; 2549 default: 2550 /* default from usbroothub */ 2551 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2552 buflen, 0, 0, 0); 2553 2554 return buflen; 2555 } 2556 2557 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2558 2559 return totlen; 2560 } 2561 2562 Static void 2563 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2564 { 2565 int port; 2566 uint32_t v; 2567 2568 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2569 2570 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2571 #ifdef DIAGNOSTIC 2572 if (sc->sc_npcomp != 0) { 2573 int i = (index-1) / sc->sc_npcomp; 2574 if (i >= sc->sc_ncomp) 2575 printf("%s: strange port\n", 2576 device_xname(sc->sc_dev)); 2577 else 2578 printf("%s: handing over %s speed device on " 2579 "port %d to %s\n", 2580 device_xname(sc->sc_dev), 2581 lowspeed ? "low" : "full", 2582 index, device_xname(sc->sc_comps[i])); 2583 } else { 2584 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2585 } 2586 #endif 2587 port = EHCI_PORTSC(index); 2588 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2589 EOWRITE4(sc, port, v | EHCI_PS_PO); 2590 } 2591 2592 Static usbd_status 2593 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2594 { 2595 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2596 usbd_status err; 2597 2598 /* Insert last in queue. */ 2599 mutex_enter(&sc->sc_lock); 2600 err = usb_insert_transfer(xfer); 2601 mutex_exit(&sc->sc_lock); 2602 if (err) 2603 return err; 2604 2605 /* Pipe isn't running, start first */ 2606 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2607 } 2608 2609 Static usbd_status 2610 ehci_root_intr_start(usbd_xfer_handle xfer) 2611 { 2612 usbd_pipe_handle pipe = xfer->ux_pipe; 2613 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2614 2615 if (sc->sc_dying) 2616 return USBD_IOERROR; 2617 2618 mutex_enter(&sc->sc_lock); 2619 sc->sc_intrxfer = xfer; 2620 mutex_exit(&sc->sc_lock); 2621 2622 return USBD_IN_PROGRESS; 2623 } 2624 2625 /* Abort a root interrupt request. */ 2626 Static void 2627 ehci_root_intr_abort(usbd_xfer_handle xfer) 2628 { 2629 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2630 2631 KASSERT(mutex_owned(&sc->sc_lock)); 2632 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2633 2634 sc->sc_intrxfer = NULL; 2635 2636 xfer->ux_status = USBD_CANCELLED; 2637 usb_transfer_complete(xfer); 2638 } 2639 2640 /* Close the root pipe. */ 2641 Static void 2642 ehci_root_intr_close(usbd_pipe_handle pipe) 2643 { 2644 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2645 2646 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2647 2648 KASSERT(mutex_owned(&sc->sc_lock)); 2649 2650 sc->sc_intrxfer = NULL; 2651 } 2652 2653 Static void 2654 ehci_root_intr_done(usbd_xfer_handle xfer) 2655 { 2656 xfer->ux_hcpriv = NULL; 2657 } 2658 2659 /************************/ 2660 2661 Static ehci_soft_qh_t * 2662 ehci_alloc_sqh(ehci_softc_t *sc) 2663 { 2664 ehci_soft_qh_t *sqh; 2665 usbd_status err; 2666 int i, offs; 2667 usb_dma_t dma; 2668 2669 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2670 2671 if (sc->sc_freeqhs == NULL) { 2672 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2673 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2674 EHCI_PAGE_SIZE, &dma); 2675 #ifdef EHCI_DEBUG 2676 if (err) 2677 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2678 #endif 2679 if (err) 2680 return NULL; 2681 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2682 offs = i * EHCI_SQH_SIZE; 2683 sqh = KERNADDR(&dma, offs); 2684 sqh->physaddr = DMAADDR(&dma, offs); 2685 sqh->dma = dma; 2686 sqh->offs = offs; 2687 sqh->next = sc->sc_freeqhs; 2688 sc->sc_freeqhs = sqh; 2689 } 2690 } 2691 sqh = sc->sc_freeqhs; 2692 sc->sc_freeqhs = sqh->next; 2693 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2694 sqh->next = NULL; 2695 return sqh; 2696 } 2697 2698 Static void 2699 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2700 { 2701 sqh->next = sc->sc_freeqhs; 2702 sc->sc_freeqhs = sqh; 2703 } 2704 2705 Static ehci_soft_qtd_t * 2706 ehci_alloc_sqtd(ehci_softc_t *sc) 2707 { 2708 ehci_soft_qtd_t *sqtd = NULL; 2709 usbd_status err; 2710 int i, offs; 2711 usb_dma_t dma; 2712 2713 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2714 2715 if (sc->sc_freeqtds == NULL) { 2716 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2717 2718 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2719 EHCI_PAGE_SIZE, &dma); 2720 #ifdef EHCI_DEBUG 2721 if (err) 2722 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2723 #endif 2724 if (err) 2725 goto done; 2726 2727 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2728 offs = i * EHCI_SQTD_SIZE; 2729 sqtd = KERNADDR(&dma, offs); 2730 sqtd->physaddr = DMAADDR(&dma, offs); 2731 sqtd->dma = dma; 2732 sqtd->offs = offs; 2733 2734 sqtd->nextqtd = sc->sc_freeqtds; 2735 sc->sc_freeqtds = sqtd; 2736 } 2737 } 2738 2739 sqtd = sc->sc_freeqtds; 2740 sc->sc_freeqtds = sqtd->nextqtd; 2741 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2742 sqtd->nextqtd = NULL; 2743 sqtd->xfer = NULL; 2744 2745 done: 2746 return sqtd; 2747 } 2748 2749 Static void 2750 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2751 { 2752 2753 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2754 2755 sqtd->nextqtd = sc->sc_freeqtds; 2756 sc->sc_freeqtds = sqtd; 2757 } 2758 2759 Static usbd_status 2760 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2761 int alen, int rd, usbd_xfer_handle xfer, 2762 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2763 { 2764 ehci_soft_qtd_t *next, *cur; 2765 ehci_physaddr_t nextphys; 2766 uint32_t qtdstatus; 2767 int len, curlen, mps; 2768 int i, tog; 2769 int pages, pageoffs; 2770 size_t curoffs; 2771 vaddr_t va, va_offs; 2772 usb_dma_t *dma = &xfer->ux_dmabuf; 2773 uint16_t flags = xfer->ux_flags; 2774 paddr_t a; 2775 2776 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2777 2778 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2779 2780 len = alen; 2781 qtdstatus = EHCI_QTD_ACTIVE | 2782 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2783 EHCI_QTD_SET_CERR(3) 2784 /* IOC set below */ 2785 /* BYTES set below */ 2786 ; 2787 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 2788 tog = epipe->nexttoggle; 2789 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2790 2791 cur = ehci_alloc_sqtd(sc); 2792 *sp = cur; 2793 if (cur == NULL) 2794 goto nomem; 2795 2796 usb_syncmem(dma, 0, alen, 2797 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2798 curoffs = 0; 2799 for (;;) { 2800 /* The EHCI hardware can handle at most 5 pages. */ 2801 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2802 va_offs = EHCI_PAGE_OFFSET(va_offs); 2803 if (len-curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2804 /* we can handle it in this QTD */ 2805 curlen = len - curoffs; 2806 } else { 2807 /* must use multiple TDs, fill as much as possible. */ 2808 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2809 2810 /* the length must be a multiple of the max size */ 2811 curlen -= curlen % mps; 2812 USBHIST_LOG(ehcidebug, "multiple QTDs, " 2813 "curlen=%d", curlen, 0, 0, 0); 2814 KASSERT(curlen != 0); 2815 } 2816 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 2817 len, curlen, curoffs, 0); 2818 2819 /* 2820 * Allocate another transfer if there's more data left, 2821 * or if force last short transfer flag is set and we're 2822 * allocating a multiple of the max packet size. 2823 */ 2824 2825 if (curoffs + curlen != len || 2826 ((curlen % mps) == 0 && !rd && curlen != 0 && 2827 (flags & USBD_FORCE_SHORT_XFER))) { 2828 next = ehci_alloc_sqtd(sc); 2829 if (next == NULL) 2830 goto nomem; 2831 nextphys = htole32(next->physaddr); 2832 } else { 2833 next = NULL; 2834 nextphys = EHCI_NULL; 2835 } 2836 2837 /* Find number of pages we'll be using, insert dma addresses */ 2838 pages = EHCI_NPAGES(curlen); 2839 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2840 pageoffs = EHCI_PAGE(curoffs); 2841 for (i = 0; i < pages; i++) { 2842 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2843 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2844 /* Cast up to avoid compiler warnings */ 2845 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2846 } 2847 2848 /* First buffer pointer requires a page offset to start at */ 2849 va = (vaddr_t)KERNADDR(dma, curoffs); 2850 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2851 2852 cur->nextqtd = next; 2853 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2854 cur->qtd.qtd_status = 2855 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2856 cur->xfer = xfer; 2857 cur->len = curlen; 2858 2859 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2860 curoffs, curoffs + curlen, 0, 0); 2861 2862 /* 2863 * adjust the toggle based on the number of packets in this 2864 * qtd 2865 */ 2866 if (((curlen + mps - 1) / mps) & 1) { 2867 tog ^= 1; 2868 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2869 } 2870 if (next == NULL) 2871 break; 2872 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2873 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2874 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2875 if (len) 2876 curoffs += curlen; 2877 cur = next; 2878 } 2879 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2880 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2881 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2882 *ep = cur; 2883 epipe->nexttoggle = tog; 2884 2885 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 2886 *sp, *ep, 0, 0); 2887 2888 return USBD_NORMAL_COMPLETION; 2889 2890 nomem: 2891 /* XXX free chain */ 2892 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2893 return USBD_NOMEM; 2894 } 2895 2896 Static void 2897 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2898 ehci_soft_qtd_t *sqtdend) 2899 { 2900 ehci_soft_qtd_t *p; 2901 int i; 2902 2903 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2904 2905 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 2906 sqtd, sqtdend, 0, 0); 2907 2908 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2909 p = sqtd->nextqtd; 2910 ehci_free_sqtd(sc, sqtd); 2911 } 2912 } 2913 2914 Static ehci_soft_itd_t * 2915 ehci_alloc_itd(ehci_softc_t *sc) 2916 { 2917 struct ehci_soft_itd *itd, *freeitd; 2918 usbd_status err; 2919 int i, offs, frindex, previndex; 2920 usb_dma_t dma; 2921 2922 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2923 2924 mutex_enter(&sc->sc_lock); 2925 2926 /* 2927 * Find an itd that wasn't freed this frame or last frame. This can 2928 * discard itds that were freed before frindex wrapped around 2929 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2930 * interrupt and fiddling with list when that happens 2931 */ 2932 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2933 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2934 2935 freeitd = NULL; 2936 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2937 if (itd == NULL) 2938 break; 2939 if (itd->slot != frindex && itd->slot != previndex) { 2940 freeitd = itd; 2941 break; 2942 } 2943 } 2944 2945 if (freeitd == NULL) { 2946 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2947 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2948 EHCI_PAGE_SIZE, &dma); 2949 2950 if (err) { 2951 USBHIST_LOG(ehcidebug, 2952 "alloc returned %d", err, 0, 0, 0); 2953 mutex_exit(&sc->sc_lock); 2954 return NULL; 2955 } 2956 2957 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2958 offs = i * EHCI_ITD_SIZE; 2959 itd = KERNADDR(&dma, offs); 2960 itd->physaddr = DMAADDR(&dma, offs); 2961 itd->dma = dma; 2962 itd->offs = offs; 2963 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2964 } 2965 freeitd = LIST_FIRST(&sc->sc_freeitds); 2966 } 2967 2968 itd = freeitd; 2969 LIST_REMOVE(itd, u.free_list); 2970 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2971 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2972 sizeof(itd->itd.itd_next), 2973 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2974 2975 itd->u.frame_list.next = NULL; 2976 itd->u.frame_list.prev = NULL; 2977 itd->xfer_next = NULL; 2978 itd->slot = 0; 2979 2980 mutex_exit(&sc->sc_lock); 2981 2982 return itd; 2983 } 2984 2985 Static ehci_soft_sitd_t * 2986 ehci_alloc_sitd(ehci_softc_t *sc) 2987 { 2988 struct ehci_soft_sitd *sitd, *freesitd; 2989 usbd_status err; 2990 int i, offs, frindex, previndex; 2991 usb_dma_t dma; 2992 2993 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2994 2995 mutex_enter(&sc->sc_lock); 2996 2997 /* 2998 * Find an sitd that wasn't freed this frame or last frame. This can 2999 * discard sitds that were freed before frindex wrapped around 3000 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3001 * interrupt and fiddling with list when that happens 3002 */ 3003 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3004 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3005 3006 freesitd = NULL; 3007 LIST_FOREACH(sitd, &sc->sc_freesitds, u.free_list) { 3008 if (sitd == NULL) 3009 break; 3010 if (sitd->slot != frindex && sitd->slot != previndex) { 3011 freesitd = sitd; 3012 break; 3013 } 3014 } 3015 3016 if (freesitd == NULL) { 3017 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3018 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3019 EHCI_PAGE_SIZE, &dma); 3020 3021 if (err) { 3022 USBHIST_LOG(ehcidebug, 3023 "alloc returned %d", err, 0, 0, 0); 3024 mutex_exit(&sc->sc_lock); 3025 return NULL; 3026 } 3027 3028 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3029 offs = i * EHCI_SITD_SIZE; 3030 sitd = KERNADDR(&dma, offs); 3031 sitd->physaddr = DMAADDR(&dma, offs); 3032 sitd->dma = dma; 3033 sitd->offs = offs; 3034 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3035 } 3036 freesitd = LIST_FIRST(&sc->sc_freesitds); 3037 } 3038 3039 sitd = freesitd; 3040 LIST_REMOVE(sitd, u.free_list); 3041 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3042 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3043 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3044 BUS_DMASYNC_PREREAD); 3045 3046 sitd->u.frame_list.next = NULL; 3047 sitd->u.frame_list.prev = NULL; 3048 sitd->xfer_next = NULL; 3049 sitd->slot = 0; 3050 3051 mutex_exit(&sc->sc_lock); 3052 3053 return sitd; 3054 } 3055 3056 Static void 3057 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3058 { 3059 3060 KASSERT(mutex_owned(&sc->sc_lock)); 3061 3062 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3063 } 3064 3065 Static void 3066 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3067 { 3068 3069 KASSERT(mutex_owned(&sc->sc_lock)); 3070 3071 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3072 } 3073 3074 /****************/ 3075 3076 /* 3077 * Close a reqular pipe. 3078 * Assumes that there are no pending transactions. 3079 */ 3080 Static void 3081 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3082 { 3083 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3084 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3085 ehci_soft_qh_t *sqh = epipe->sqh; 3086 3087 KASSERT(mutex_owned(&sc->sc_lock)); 3088 3089 ehci_rem_qh(sc, sqh, head); 3090 ehci_free_sqh(sc, epipe->sqh); 3091 } 3092 3093 /* 3094 * Abort a device request. 3095 * If this routine is called at splusb() it guarantees that the request 3096 * will be removed from the hardware scheduling and that the callback 3097 * for it will be called with USBD_CANCELLED status. 3098 * It's impossible to guarantee that the requested transfer will not 3099 * have happened since the hardware runs concurrently. 3100 * If the transaction has already happened we rely on the ordinary 3101 * interrupt processing to process it. 3102 * XXX This is most probably wrong. 3103 * XXXMRG this doesn't make sense anymore. 3104 */ 3105 Static void 3106 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3107 { 3108 #define exfer EXFER(xfer) 3109 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3110 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3111 ehci_soft_qh_t *sqh = epipe->sqh; 3112 ehci_soft_qtd_t *sqtd; 3113 ehci_physaddr_t cur; 3114 uint32_t qhstatus; 3115 int hit; 3116 int wake; 3117 3118 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3119 3120 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3121 3122 KASSERT(mutex_owned(&sc->sc_lock)); 3123 ASSERT_SLEEPABLE(); 3124 3125 if (sc->sc_dying) { 3126 /* If we're dying, just do the software part. */ 3127 xfer->ux_status = status; /* make software ignore it */ 3128 callout_stop(&xfer->ux_callout); 3129 usb_transfer_complete(xfer); 3130 return; 3131 } 3132 3133 /* 3134 * If an abort is already in progress then just wait for it to 3135 * complete and return. 3136 */ 3137 if (xfer->ux_hcflags & UXFER_ABORTING) { 3138 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3139 #ifdef DIAGNOSTIC 3140 if (status == USBD_TIMEOUT) 3141 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3142 #endif 3143 /* Override the status which might be USBD_TIMEOUT. */ 3144 xfer->ux_status = status; 3145 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3146 0, 0, 0, 0); 3147 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3148 while (xfer->ux_hcflags & UXFER_ABORTING) 3149 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3150 return; 3151 } 3152 xfer->ux_hcflags |= UXFER_ABORTING; 3153 3154 /* 3155 * Step 1: Make interrupt routine and hardware ignore xfer. 3156 */ 3157 xfer->ux_status = status; /* make software ignore it */ 3158 callout_stop(&xfer->ux_callout); 3159 3160 usb_syncmem(&sqh->dma, 3161 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3162 sizeof(sqh->qh.qh_qtd.qtd_status), 3163 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3164 qhstatus = sqh->qh.qh_qtd.qtd_status; 3165 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3166 usb_syncmem(&sqh->dma, 3167 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3168 sizeof(sqh->qh.qh_qtd.qtd_status), 3169 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3170 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3171 usb_syncmem(&sqtd->dma, 3172 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3173 sizeof(sqtd->qtd.qtd_status), 3174 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3175 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3176 usb_syncmem(&sqtd->dma, 3177 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3178 sizeof(sqtd->qtd.qtd_status), 3179 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3180 if (sqtd == exfer->ex_sqtdend) 3181 break; 3182 } 3183 3184 /* 3185 * Step 2: Wait until we know hardware has finished any possible 3186 * use of the xfer. Also make sure the soft interrupt routine 3187 * has run. 3188 */ 3189 ehci_sync_hc(sc); 3190 sc->sc_softwake = 1; 3191 usb_schedsoftintr(&sc->sc_bus); 3192 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3193 3194 /* 3195 * Step 3: Remove any vestiges of the xfer from the hardware. 3196 * The complication here is that the hardware may have executed 3197 * beyond the xfer we're trying to abort. So as we're scanning 3198 * the TDs of this xfer we check if the hardware points to 3199 * any of them. 3200 */ 3201 3202 usb_syncmem(&sqh->dma, 3203 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3204 sizeof(sqh->qh.qh_curqtd), 3205 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3206 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3207 hit = 0; 3208 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3209 hit |= cur == sqtd->physaddr; 3210 if (sqtd == exfer->ex_sqtdend) 3211 break; 3212 } 3213 sqtd = sqtd->nextqtd; 3214 /* Zap curqtd register if hardware pointed inside the xfer. */ 3215 if (hit && sqtd != NULL) { 3216 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3217 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3218 usb_syncmem(&sqh->dma, 3219 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3220 sizeof(sqh->qh.qh_curqtd), 3221 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3222 sqh->qh.qh_qtd.qtd_status = qhstatus; 3223 usb_syncmem(&sqh->dma, 3224 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3225 sizeof(sqh->qh.qh_qtd.qtd_status), 3226 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3227 } else { 3228 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3229 } 3230 3231 /* 3232 * Step 4: Execute callback. 3233 */ 3234 #ifdef DIAGNOSTIC 3235 exfer->ex_isdone = true; 3236 #endif 3237 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3238 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3239 usb_transfer_complete(xfer); 3240 if (wake) { 3241 cv_broadcast(&xfer->ux_hccv); 3242 } 3243 3244 KASSERT(mutex_owned(&sc->sc_lock)); 3245 #undef exfer 3246 } 3247 3248 Static void 3249 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3250 { 3251 ehci_isoc_trans_t trans_status; 3252 struct ehci_pipe *epipe; 3253 struct ehci_xfer *exfer; 3254 ehci_softc_t *sc; 3255 struct ehci_soft_itd *itd; 3256 struct ehci_soft_sitd *sitd; 3257 int i, wake; 3258 3259 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3260 3261 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3262 exfer = EXFER(xfer); 3263 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3264 3265 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3266 3267 KASSERT(mutex_owned(&sc->sc_lock)); 3268 3269 if (sc->sc_dying) { 3270 xfer->ux_status = status; 3271 callout_stop(&xfer->ux_callout); 3272 usb_transfer_complete(xfer); 3273 return; 3274 } 3275 3276 if (xfer->ux_hcflags & UXFER_ABORTING) { 3277 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3278 3279 #ifdef DIAGNOSTIC 3280 if (status == USBD_TIMEOUT) 3281 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3282 #endif 3283 3284 xfer->ux_status = status; 3285 USBHIST_LOG(ehcidebug, 3286 "waiting for abort to finish", 0, 0, 0, 0); 3287 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3288 while (xfer->ux_hcflags & UXFER_ABORTING) 3289 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3290 goto done; 3291 } 3292 xfer->ux_hcflags |= UXFER_ABORTING; 3293 3294 xfer->ux_status = status; 3295 callout_stop(&xfer->ux_callout); 3296 3297 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3298 for (itd = exfer->ex_itdstart; itd != NULL; 3299 itd = itd->xfer_next) { 3300 usb_syncmem(&itd->dma, 3301 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3302 sizeof(itd->itd.itd_ctl), 3303 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3304 3305 for (i = 0; i < 8; i++) { 3306 trans_status = le32toh(itd->itd.itd_ctl[i]); 3307 trans_status &= ~EHCI_ITD_ACTIVE; 3308 itd->itd.itd_ctl[i] = htole32(trans_status); 3309 } 3310 3311 usb_syncmem(&itd->dma, 3312 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3313 sizeof(itd->itd.itd_ctl), 3314 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3315 } 3316 } else { 3317 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3318 sitd = sitd->xfer_next) { 3319 usb_syncmem(&sitd->dma, 3320 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3321 sizeof(sitd->sitd.sitd_buffer), 3322 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3323 3324 trans_status = le32toh(sitd->sitd.sitd_trans); 3325 trans_status &= ~EHCI_SITD_ACTIVE; 3326 sitd->sitd.sitd_trans = htole32(trans_status); 3327 3328 usb_syncmem(&sitd->dma, 3329 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3330 sizeof(sitd->sitd.sitd_buffer), 3331 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3332 } 3333 } 3334 3335 sc->sc_softwake = 1; 3336 usb_schedsoftintr(&sc->sc_bus); 3337 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3338 3339 #ifdef DIAGNOSTIC 3340 exfer->ex_isdone = true; 3341 #endif 3342 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3343 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3344 usb_transfer_complete(xfer); 3345 if (wake) { 3346 cv_broadcast(&xfer->ux_hccv); 3347 } 3348 3349 done: 3350 KASSERT(mutex_owned(&sc->sc_lock)); 3351 return; 3352 } 3353 3354 Static void 3355 ehci_timeout(void *addr) 3356 { 3357 struct ehci_xfer *exfer = addr; 3358 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->ex_xfer.ux_pipe; 3359 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3360 3361 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3362 3363 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3364 #ifdef EHCI_DEBUG 3365 if (ehcidebug > 1) 3366 usbd_dump_pipe(exfer->ex_xfer.ux_pipe); 3367 #endif 3368 3369 if (sc->sc_dying) { 3370 mutex_enter(&sc->sc_lock); 3371 ehci_abort_xfer(&exfer->ex_xfer, USBD_TIMEOUT); 3372 mutex_exit(&sc->sc_lock); 3373 return; 3374 } 3375 3376 /* Execute the abort in a process context. */ 3377 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, addr, 3378 USB_TASKQ_MPSAFE); 3379 usb_add_task(exfer->ex_xfer.ux_pipe->up_dev, &exfer->ex_aborttask, 3380 USB_TASKQ_HC); 3381 } 3382 3383 Static void 3384 ehci_timeout_task(void *addr) 3385 { 3386 usbd_xfer_handle xfer = addr; 3387 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3388 3389 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3390 3391 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3392 3393 mutex_enter(&sc->sc_lock); 3394 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3395 mutex_exit(&sc->sc_lock); 3396 } 3397 3398 /************************/ 3399 3400 Static usbd_status 3401 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3402 { 3403 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3404 usbd_status err; 3405 3406 /* Insert last in queue. */ 3407 mutex_enter(&sc->sc_lock); 3408 err = usb_insert_transfer(xfer); 3409 mutex_exit(&sc->sc_lock); 3410 if (err) 3411 return err; 3412 3413 /* Pipe isn't running, start first */ 3414 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3415 } 3416 3417 Static usbd_status 3418 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3419 { 3420 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3421 usbd_status err; 3422 3423 if (sc->sc_dying) 3424 return USBD_IOERROR; 3425 3426 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3427 3428 err = ehci_device_request(xfer); 3429 if (err) { 3430 return err; 3431 } 3432 3433 if (sc->sc_bus.ub_usepolling) 3434 ehci_waitintr(sc, xfer); 3435 3436 return USBD_IN_PROGRESS; 3437 } 3438 3439 Static void 3440 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3441 { 3442 struct ehci_xfer *ex = EXFER(xfer); 3443 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3444 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3445 usb_device_request_t *req = &xfer->ux_request; 3446 int len = UGETW(req->wLength); 3447 int rd = req->bmRequestType & UT_READ; 3448 3449 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3450 3451 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3452 3453 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3454 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3455 3456 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3457 ehci_del_intr_list(sc, ex); /* remove from active list */ 3458 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3459 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof(*req), 3460 BUS_DMASYNC_POSTWRITE); 3461 if (len) 3462 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3463 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3464 } 3465 3466 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3467 } 3468 3469 /* Abort a device control request. */ 3470 Static void 3471 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3472 { 3473 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3474 3475 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3476 ehci_abort_xfer(xfer, USBD_CANCELLED); 3477 } 3478 3479 /* Close a device control pipe. */ 3480 Static void 3481 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3482 { 3483 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3484 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3485 3486 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3487 3488 KASSERT(mutex_owned(&sc->sc_lock)); 3489 3490 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3491 3492 ehci_close_pipe(pipe, sc->sc_async_head); 3493 } 3494 3495 Static usbd_status 3496 ehci_device_request(usbd_xfer_handle xfer) 3497 { 3498 #define exfer EXFER(xfer) 3499 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3500 usb_device_request_t *req = &xfer->ux_request; 3501 usbd_device_handle dev = epipe->pipe.up_dev; 3502 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3503 ehci_soft_qtd_t *setup, *stat, *next; 3504 ehci_soft_qh_t *sqh; 3505 int isread; 3506 int len; 3507 usbd_status err; 3508 3509 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3510 3511 isread = req->bmRequestType & UT_READ; 3512 len = UGETW(req->wLength); 3513 3514 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3515 "wValue=0x%04x, wIndex=0x%04x", 3516 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3517 UGETW(req->wIndex)); 3518 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3519 len, dev->ud_addr, 3520 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3521 3522 setup = ehci_alloc_sqtd(sc); 3523 if (setup == NULL) { 3524 err = USBD_NOMEM; 3525 goto bad1; 3526 } 3527 stat = ehci_alloc_sqtd(sc); 3528 if (stat == NULL) { 3529 err = USBD_NOMEM; 3530 goto bad2; 3531 } 3532 3533 mutex_enter(&sc->sc_lock); 3534 3535 sqh = epipe->sqh; 3536 3537 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3538 "address QH %d pipe %d\n", 3539 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3540 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3541 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3542 "MPS QH %d pipe %d\n", 3543 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3544 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3545 3546 /* Set up data transaction */ 3547 if (len != 0) { 3548 ehci_soft_qtd_t *end; 3549 3550 /* Start toggle at 1. */ 3551 epipe->nexttoggle = 1; 3552 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3553 &next, &end); 3554 if (err) 3555 goto bad3; 3556 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3557 end->nextqtd = stat; 3558 end->qtd.qtd_next = end->qtd.qtd_altnext = 3559 htole32(stat->physaddr); 3560 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3561 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3562 } else { 3563 next = stat; 3564 } 3565 3566 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 3567 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3568 3569 /* Clear toggle */ 3570 setup->qtd.qtd_status = htole32( 3571 EHCI_QTD_ACTIVE | 3572 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3573 EHCI_QTD_SET_CERR(3) | 3574 EHCI_QTD_SET_TOGGLE(0) | 3575 EHCI_QTD_SET_BYTES(sizeof(*req)) 3576 ); 3577 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3578 setup->qtd.qtd_buffer_hi[0] = 0; 3579 setup->nextqtd = next; 3580 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3581 setup->xfer = xfer; 3582 setup->len = sizeof(*req); 3583 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3584 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3585 3586 stat->qtd.qtd_status = htole32( 3587 EHCI_QTD_ACTIVE | 3588 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3589 EHCI_QTD_SET_CERR(3) | 3590 EHCI_QTD_SET_TOGGLE(1) | 3591 EHCI_QTD_IOC 3592 ); 3593 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3594 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3595 stat->nextqtd = NULL; 3596 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3597 stat->xfer = xfer; 3598 stat->len = 0; 3599 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3600 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3601 3602 #ifdef EHCI_DEBUG 3603 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3604 ehci_dump_sqh(sqh); 3605 ehci_dump_sqtds(setup); 3606 #endif 3607 3608 exfer->ex_sqtdstart = setup; 3609 exfer->ex_sqtdend = stat; 3610 KASSERT(exfer->ex_isdone); 3611 #ifdef DIAGNOSTIC 3612 exfer->ex_isdone = false; 3613 #endif 3614 3615 /* Insert qTD in QH list. */ 3616 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3617 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3618 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3619 ehci_timeout, xfer); 3620 } 3621 ehci_add_intr_list(sc, exfer); 3622 xfer->ux_status = USBD_IN_PROGRESS; 3623 mutex_exit(&sc->sc_lock); 3624 3625 #ifdef EHCI_DEBUG 3626 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3627 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3628 // delay(10000); 3629 ehci_dump_regs(sc); 3630 ehci_dump_sqh(sc->sc_async_head); 3631 ehci_dump_sqh(sqh); 3632 ehci_dump_sqtds(setup); 3633 #endif 3634 3635 return USBD_NORMAL_COMPLETION; 3636 3637 bad3: 3638 mutex_exit(&sc->sc_lock); 3639 ehci_free_sqtd(sc, stat); 3640 bad2: 3641 ehci_free_sqtd(sc, setup); 3642 bad1: 3643 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3644 mutex_enter(&sc->sc_lock); 3645 xfer->ux_status = err; 3646 usb_transfer_complete(xfer); 3647 mutex_exit(&sc->sc_lock); 3648 return err; 3649 #undef exfer 3650 } 3651 3652 /* 3653 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3654 * qTD status, or miss signalling occasionally under heavy load. If the host 3655 * machine is too fast, we we can miss transaction completion - when we scan 3656 * the active list the transaction still seems to be active. This generally 3657 * exhibits itself as a umass stall that never recovers. 3658 * 3659 * We work around this behaviour by setting up this callback after any softintr 3660 * that completes with transactions still pending, giving us another chance to 3661 * check for completion after the writeback has taken place. 3662 */ 3663 Static void 3664 ehci_intrlist_timeout(void *arg) 3665 { 3666 ehci_softc_t *sc = arg; 3667 3668 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3669 3670 usb_schedsoftintr(&sc->sc_bus); 3671 } 3672 3673 /************************/ 3674 3675 Static usbd_status 3676 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3677 { 3678 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3679 usbd_status err; 3680 3681 /* Insert last in queue. */ 3682 mutex_enter(&sc->sc_lock); 3683 err = usb_insert_transfer(xfer); 3684 mutex_exit(&sc->sc_lock); 3685 if (err) 3686 return err; 3687 3688 /* Pipe isn't running, start first */ 3689 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3690 } 3691 3692 Static usbd_status 3693 ehci_device_bulk_start(usbd_xfer_handle xfer) 3694 { 3695 #define exfer EXFER(xfer) 3696 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3697 usbd_device_handle dev = epipe->pipe.up_dev; 3698 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3699 ehci_soft_qtd_t *data, *dataend; 3700 ehci_soft_qh_t *sqh; 3701 usbd_status err; 3702 int len, isread, endpt; 3703 3704 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3705 3706 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3707 xfer, xfer->ux_length, xfer->ux_flags, 0); 3708 3709 if (sc->sc_dying) 3710 return USBD_IOERROR; 3711 3712 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3713 3714 mutex_enter(&sc->sc_lock); 3715 3716 len = xfer->ux_length; 3717 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3718 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3719 sqh = epipe->sqh; 3720 3721 epipe->u.bulk.length = len; 3722 3723 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3724 &dataend); 3725 if (err) { 3726 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3727 xfer->ux_status = err; 3728 usb_transfer_complete(xfer); 3729 mutex_exit(&sc->sc_lock); 3730 return err; 3731 } 3732 3733 #ifdef EHCI_DEBUG 3734 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3735 ehci_dump_sqh(sqh); 3736 ehci_dump_sqtds(data); 3737 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3738 #endif 3739 3740 /* Set up interrupt info. */ 3741 exfer->ex_sqtdstart = data; 3742 exfer->ex_sqtdend = dataend; 3743 KASSERT(exfer->ex_isdone); 3744 #ifdef DIAGNOSTIC 3745 exfer->ex_isdone = false; 3746 #endif 3747 3748 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3749 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3750 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3751 ehci_timeout, xfer); 3752 } 3753 ehci_add_intr_list(sc, exfer); 3754 xfer->ux_status = USBD_IN_PROGRESS; 3755 mutex_exit(&sc->sc_lock); 3756 3757 #ifdef EHCI_DEBUG 3758 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3759 // delay(10000); 3760 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3761 ehci_dump_regs(sc); 3762 #if 0 3763 printf("async_head:\n"); 3764 ehci_dump_sqh(sc->sc_async_head); 3765 #endif 3766 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3767 ehci_dump_sqh(sqh); 3768 ehci_dump_sqtds(data); 3769 #endif 3770 3771 if (sc->sc_bus.ub_usepolling) 3772 ehci_waitintr(sc, xfer); 3773 3774 return USBD_IN_PROGRESS; 3775 #undef exfer 3776 } 3777 3778 Static void 3779 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3780 { 3781 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3782 3783 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3784 ehci_abort_xfer(xfer, USBD_CANCELLED); 3785 } 3786 3787 /* 3788 * Close a device bulk pipe. 3789 */ 3790 Static void 3791 ehci_device_bulk_close(usbd_pipe_handle pipe) 3792 { 3793 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3794 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3795 3796 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3797 3798 KASSERT(mutex_owned(&sc->sc_lock)); 3799 3800 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3801 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3802 ehci_close_pipe(pipe, sc->sc_async_head); 3803 } 3804 3805 Static void 3806 ehci_device_bulk_done(usbd_xfer_handle xfer) 3807 { 3808 struct ehci_xfer *ex = EXFER(xfer); 3809 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3810 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3811 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3812 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3813 3814 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3815 3816 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3817 xfer, xfer->ux_actlen, 0, 0); 3818 3819 KASSERT(mutex_owned(&sc->sc_lock)); 3820 3821 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3822 ehci_del_intr_list(sc, ex); /* remove from active list */ 3823 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3824 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3825 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3826 } 3827 3828 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3829 } 3830 3831 /************************/ 3832 3833 Static usbd_status 3834 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3835 { 3836 struct ehci_soft_islot *isp; 3837 int islot, lev; 3838 3839 /* Find a poll rate that is large enough. */ 3840 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3841 if (EHCI_ILEV_IVAL(lev) <= ival) 3842 break; 3843 3844 /* Pick an interrupt slot at the right level. */ 3845 /* XXX could do better than picking at random */ 3846 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3847 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3848 3849 sqh->islot = islot; 3850 isp = &sc->sc_islots[islot]; 3851 mutex_enter(&sc->sc_lock); 3852 ehci_add_qh(sc, sqh, isp->sqh); 3853 mutex_exit(&sc->sc_lock); 3854 3855 return USBD_NORMAL_COMPLETION; 3856 } 3857 3858 Static usbd_status 3859 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3860 { 3861 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3862 usbd_status err; 3863 3864 /* Insert last in queue. */ 3865 mutex_enter(&sc->sc_lock); 3866 err = usb_insert_transfer(xfer); 3867 mutex_exit(&sc->sc_lock); 3868 if (err) 3869 return err; 3870 3871 /* 3872 * Pipe isn't running (otherwise err would be USBD_INPROG), 3873 * so start it first. 3874 */ 3875 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3876 } 3877 3878 Static usbd_status 3879 ehci_device_intr_start(usbd_xfer_handle xfer) 3880 { 3881 #define exfer EXFER(xfer) 3882 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3883 usbd_device_handle dev = xfer->ux_pipe->up_dev; 3884 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3885 ehci_soft_qtd_t *data, *dataend; 3886 ehci_soft_qh_t *sqh; 3887 usbd_status err; 3888 int len, isread, endpt; 3889 3890 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3891 3892 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3893 xfer, xfer->ux_length, xfer->ux_flags, 0); 3894 3895 if (sc->sc_dying) 3896 return USBD_IOERROR; 3897 3898 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3899 3900 mutex_enter(&sc->sc_lock); 3901 3902 len = xfer->ux_length; 3903 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3904 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3905 sqh = epipe->sqh; 3906 3907 epipe->u.intr.length = len; 3908 3909 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3910 &dataend); 3911 if (err) { 3912 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3913 xfer->ux_status = err; 3914 usb_transfer_complete(xfer); 3915 mutex_exit(&sc->sc_lock); 3916 return err; 3917 } 3918 3919 #ifdef EHCI_DEBUG 3920 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3921 ehci_dump_sqh(sqh); 3922 ehci_dump_sqtds(data); 3923 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3924 #endif 3925 3926 /* Set up interrupt info. */ 3927 exfer->ex_sqtdstart = data; 3928 exfer->ex_sqtdend = dataend; 3929 KASSERT(exfer->ex_isdone); 3930 #ifdef DIAGNOSTIC 3931 exfer->ex_isdone = false; 3932 #endif 3933 3934 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3935 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3936 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3937 ehci_timeout, xfer); 3938 } 3939 ehci_add_intr_list(sc, exfer); 3940 xfer->ux_status = USBD_IN_PROGRESS; 3941 mutex_exit(&sc->sc_lock); 3942 3943 #ifdef EHCI_DEBUG 3944 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3945 // delay(10000); 3946 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3947 ehci_dump_regs(sc); 3948 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3949 ehci_dump_sqh(sqh); 3950 ehci_dump_sqtds(data); 3951 #endif 3952 3953 if (sc->sc_bus.ub_usepolling) 3954 ehci_waitintr(sc, xfer); 3955 3956 return USBD_IN_PROGRESS; 3957 #undef exfer 3958 } 3959 3960 Static void 3961 ehci_device_intr_abort(usbd_xfer_handle xfer) 3962 { 3963 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3964 3965 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3966 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3967 3968 /* 3969 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3970 * async doorbell. That's dependent on the async list, wheras 3971 * intr xfers are periodic, should not use this? 3972 */ 3973 ehci_abort_xfer(xfer, USBD_CANCELLED); 3974 } 3975 3976 Static void 3977 ehci_device_intr_close(usbd_pipe_handle pipe) 3978 { 3979 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3980 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3981 struct ehci_soft_islot *isp; 3982 3983 KASSERT(mutex_owned(&sc->sc_lock)); 3984 3985 isp = &sc->sc_islots[epipe->sqh->islot]; 3986 ehci_close_pipe(pipe, isp->sqh); 3987 } 3988 3989 Static void 3990 ehci_device_intr_done(usbd_xfer_handle xfer) 3991 { 3992 #define exfer EXFER(xfer) 3993 struct ehci_xfer *ex = EXFER(xfer); 3994 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3995 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3996 ehci_soft_qtd_t *data, *dataend; 3997 ehci_soft_qh_t *sqh; 3998 usbd_status err; 3999 int len, isread, endpt; 4000 4001 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4002 4003 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4004 xfer, xfer->ux_actlen, 0, 0); 4005 4006 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4007 4008 if (xfer->ux_pipe->up_repeat) { 4009 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 4010 4011 len = epipe->u.intr.length; 4012 xfer->ux_length = len; 4013 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4014 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4015 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4016 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4017 sqh = epipe->sqh; 4018 4019 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4020 &data, &dataend); 4021 if (err) { 4022 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4023 xfer->ux_status = err; 4024 return; 4025 } 4026 4027 /* Set up interrupt info. */ 4028 exfer->ex_sqtdstart = data; 4029 exfer->ex_sqtdend = dataend; 4030 KASSERT(exfer->ex_isdone); 4031 #ifdef DIAGNOSTIC 4032 exfer->ex_isdone = false; 4033 #endif 4034 4035 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4036 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4037 callout_reset(&xfer->ux_callout, 4038 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4039 } 4040 4041 xfer->ux_status = USBD_IN_PROGRESS; 4042 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 4043 ehci_del_intr_list(sc, ex); /* remove from active list */ 4044 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 4045 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4046 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4047 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4048 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4049 } 4050 #undef exfer 4051 } 4052 4053 /************************/ 4054 4055 Static usbd_status 4056 ehci_device_fs_isoc_transfer(usbd_xfer_handle xfer) 4057 { 4058 usbd_status err; 4059 4060 err = usb_insert_transfer(xfer); 4061 if (err && err != USBD_IN_PROGRESS) 4062 return err; 4063 4064 return ehci_device_fs_isoc_start(xfer); 4065 } 4066 4067 Static usbd_status 4068 ehci_device_fs_isoc_start(usbd_xfer_handle xfer) 4069 { 4070 struct ehci_pipe *epipe; 4071 usbd_device_handle dev; 4072 ehci_softc_t *sc; 4073 struct ehci_xfer *exfer; 4074 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4075 usb_dma_t *dma_buf; 4076 int i, j, k, frames; 4077 int offs, total_length; 4078 int frindex; 4079 u_int huba, dir; 4080 4081 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4082 4083 start = NULL; 4084 prev = NULL; 4085 sitd = NULL; 4086 total_length = 0; 4087 exfer = (struct ehci_xfer *) xfer; 4088 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4089 dev = xfer->ux_pipe->up_dev; 4090 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4091 4092 /* 4093 * To allow continuous transfers, above we start all transfers 4094 * immediately. However, we're still going to get usbd_start_next call 4095 * this when another xfer completes. So, check if this is already 4096 * in progress or not 4097 */ 4098 4099 if (exfer->ex_sitdstart != NULL) 4100 return USBD_IN_PROGRESS; 4101 4102 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4103 xfer, xfer->ux_length, xfer->ux_flags, 0); 4104 4105 if (sc->sc_dying) 4106 return USBD_IOERROR; 4107 4108 /* 4109 * To avoid complication, don't allow a request right now that'll span 4110 * the entire frame table. To within 4 frames, to allow some leeway 4111 * on either side of where the hc currently is. 4112 */ 4113 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4114 xfer->ux_nframes >= sc->sc_flsize - 4) { 4115 printf("ehci: isoc descriptor requested that spans the entire" 4116 "frametable, too many frames\n"); 4117 return USBD_INVAL; 4118 } 4119 4120 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4121 KASSERT(exfer->ex_isdone); 4122 4123 #ifdef DIAGNOSTIC 4124 exfer->ex_isdone = false; 4125 #endif 4126 4127 /* 4128 * Step 1: Allocate and initialize sitds. 4129 */ 4130 4131 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4132 if (i > 16 || i == 0) { 4133 /* Spec page 271 says intervals > 16 are invalid */ 4134 USBHIST_LOG(ehcidebug, "bInterval %d invalid", 0, 0, 0, 0); 4135 4136 return USBD_INVAL; 4137 } 4138 4139 frames = xfer->ux_nframes; 4140 4141 if (frames == 0) { 4142 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4143 4144 return USBD_INVAL; 4145 } 4146 4147 dma_buf = &xfer->ux_dmabuf; 4148 offs = 0; 4149 4150 for (i = 0; i < frames; i++) { 4151 sitd = ehci_alloc_sitd(sc); 4152 4153 if (prev) 4154 prev->xfer_next = sitd; 4155 else 4156 start = sitd; 4157 4158 #ifdef DIAGNOSTIC 4159 if (xfer->ux_frlengths[i] > 0x3ff) { 4160 printf("ehci: invalid frame length\n"); 4161 xfer->ux_frlengths[i] = 0x3ff; 4162 } 4163 #endif 4164 4165 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4166 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4167 4168 /* Set page0 index and offset. */ 4169 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4170 4171 total_length += xfer->ux_frlengths[i]; 4172 offs += xfer->ux_frlengths[i]; 4173 4174 sitd->sitd.sitd_buffer[1] = 4175 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4176 4177 huba = dev->ud_myhsport->up_parent->ud_addr; 4178 4179 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4180 // Set hub address to 0 if embedded TT is used. 4181 if (huba == sc->sc_addr) 4182 huba = 0; 4183 } 4184 */ 4185 4186 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4187 dir = UE_GET_DIR(k) ? 1 : 0; 4188 sitd->sitd.sitd_endp = 4189 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4190 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4191 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4192 EHCI_SITD_SET_HUBA(huba) | 4193 EHCI_SITD_SET_DIR(dir)); 4194 4195 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4196 4197 /* XXX */ 4198 u_char sa, sb; 4199 u_int temp, tlen; 4200 sa = 0; 4201 4202 if (dir == 0) { /* OUT */ 4203 temp = 0; 4204 tlen = xfer->ux_frlengths[i]; 4205 if (tlen <= 188) { 4206 temp |= 1; /* T-count = 1, TP = ALL */ 4207 tlen = 1; 4208 } else { 4209 tlen += 187; 4210 tlen /= 188; 4211 temp |= tlen; /* T-count = [1..6] */ 4212 temp |= 8; /* TP = Begin */ 4213 } 4214 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4215 4216 tlen += sa; 4217 4218 if (tlen >= 8) { 4219 sb = 0; 4220 } else { 4221 sb = (1 << tlen); 4222 } 4223 4224 sa = (1 << sa); 4225 sa = (sb - sa) & 0x3F; 4226 sb = 0; 4227 } else { 4228 sb = (-(4 << sa)) & 0xFE; 4229 sa = (1 << sa) & 0x3F; 4230 sa = 0x01; 4231 sb = 0xfc; 4232 } 4233 4234 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4235 EHCI_SITD_SET_CMASK(sb)); 4236 4237 prev = sitd; 4238 } /* End of frame */ 4239 4240 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4241 4242 stop = sitd; 4243 stop->xfer_next = NULL; 4244 4245 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4246 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4247 4248 /* 4249 * Part 2: Transfer descriptors have now been set up, now they must 4250 * be scheduled into the periodic frame list. Erk. Not wanting to 4251 * complicate matters, transfer is denied if the transfer spans 4252 * more than the period frame list. 4253 */ 4254 4255 mutex_enter(&sc->sc_lock); 4256 4257 /* Start inserting frames */ 4258 if (epipe->u.isoc.cur_xfers > 0) { 4259 frindex = epipe->u.isoc.next_frame; 4260 } else { 4261 frindex = EOREAD4(sc, EHCI_FRINDEX); 4262 frindex = frindex >> 3; /* Erase microframe index */ 4263 frindex += 2; 4264 } 4265 4266 if (frindex >= sc->sc_flsize) 4267 frindex &= (sc->sc_flsize - 1); 4268 4269 /* Whats the frame interval? */ 4270 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4271 4272 sitd = start; 4273 for (j = 0; j < frames; j++) { 4274 if (sitd == NULL) 4275 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4276 4277 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4278 if (sitd->sitd.sitd_next == 0) 4279 /* FIXME: frindex table gets initialized to NULL 4280 * or EHCI_NULL? */ 4281 sitd->sitd.sitd_next = EHCI_NULL; 4282 4283 usb_syncmem(&sitd->dma, 4284 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4285 sizeof(ehci_sitd_t), 4286 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4287 4288 sc->sc_flist[frindex] = 4289 htole32(EHCI_LINK_SITD | sitd->physaddr); 4290 4291 usb_syncmem(&sc->sc_fldma, 4292 sizeof(ehci_link_t) * frindex, 4293 sizeof(ehci_link_t), 4294 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4295 4296 sitd->u.frame_list.next = sc->sc_softsitds[frindex]; 4297 sc->sc_softsitds[frindex] = sitd; 4298 if (sitd->u.frame_list.next != NULL) 4299 sitd->u.frame_list.next->u.frame_list.prev = sitd; 4300 sitd->slot = frindex; 4301 sitd->u.frame_list.prev = NULL; 4302 4303 frindex += i; 4304 if (frindex >= sc->sc_flsize) 4305 frindex -= sc->sc_flsize; 4306 4307 sitd = sitd->xfer_next; 4308 } 4309 4310 epipe->u.isoc.cur_xfers++; 4311 epipe->u.isoc.next_frame = frindex; 4312 4313 exfer->ex_sitdstart = start; 4314 exfer->ex_sitdend = stop; 4315 4316 ehci_add_intr_list(sc, exfer); 4317 xfer->ux_status = USBD_IN_PROGRESS; 4318 xfer->ux_done = 0; 4319 4320 mutex_exit(&sc->sc_lock); 4321 4322 if (sc->sc_bus.ub_usepolling) { 4323 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4324 ehci_waitintr(sc, xfer); 4325 } 4326 4327 return USBD_IN_PROGRESS; 4328 } 4329 4330 Static void 4331 ehci_device_fs_isoc_abort(usbd_xfer_handle xfer) 4332 { 4333 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4334 4335 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4336 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4337 } 4338 4339 Static void 4340 ehci_device_fs_isoc_close(usbd_pipe_handle pipe) 4341 { 4342 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4343 4344 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4345 } 4346 4347 Static void 4348 ehci_device_fs_isoc_done(usbd_xfer_handle xfer) 4349 { 4350 struct ehci_xfer *exfer; 4351 ehci_softc_t *sc; 4352 struct ehci_pipe *epipe; 4353 4354 exfer = EXFER(xfer); 4355 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4356 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4357 4358 KASSERT(mutex_owned(&sc->sc_lock)); 4359 4360 epipe->u.isoc.cur_xfers--; 4361 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4362 ehci_del_intr_list(sc, exfer); 4363 ehci_rem_free_sitd_chain(sc, exfer); 4364 } 4365 4366 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4367 BUS_DMASYNC_POSTREAD); 4368 } 4369 Static usbd_status 4370 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 4371 { 4372 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4373 usbd_status err; 4374 4375 mutex_enter(&sc->sc_lock); 4376 err = usb_insert_transfer(xfer); 4377 mutex_exit(&sc->sc_lock); 4378 if (err && err != USBD_IN_PROGRESS) 4379 return err; 4380 4381 return ehci_device_isoc_start(xfer); 4382 } 4383 4384 Static usbd_status 4385 ehci_device_isoc_start(usbd_xfer_handle xfer) 4386 { 4387 struct ehci_pipe *epipe; 4388 ehci_softc_t *sc; 4389 struct ehci_xfer *exfer; 4390 ehci_soft_itd_t *itd, *prev, *start, *stop; 4391 usb_dma_t *dma_buf; 4392 int i, j, k, frames, uframes, ufrperframe; 4393 int trans_count, offs, total_length; 4394 int frindex; 4395 4396 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4397 4398 start = NULL; 4399 prev = NULL; 4400 itd = NULL; 4401 trans_count = 0; 4402 total_length = 0; 4403 exfer = (struct ehci_xfer *) xfer; 4404 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4405 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4406 4407 /* 4408 * To allow continuous transfers, above we start all transfers 4409 * immediately. However, we're still going to get usbd_start_next call 4410 * this when another xfer completes. So, check if this is already 4411 * in progress or not 4412 */ 4413 4414 if (exfer->ex_itdstart != NULL) 4415 return USBD_IN_PROGRESS; 4416 4417 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4418 xfer, xfer->ux_length, xfer->ux_flags, 0); 4419 4420 if (sc->sc_dying) 4421 return USBD_IOERROR; 4422 4423 /* 4424 * To avoid complication, don't allow a request right now that'll span 4425 * the entire frame table. To within 4 frames, to allow some leeway 4426 * on either side of where the hc currently is. 4427 */ 4428 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4429 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4430 USBHIST_LOG(ehcidebug, 4431 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4432 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4433 return USBD_INVAL; 4434 } 4435 4436 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4437 KASSERT(exfer->ex_isdone); 4438 #ifdef DIAGNOSTIC 4439 exfer->ex_isdone = false; 4440 #endif 4441 4442 /* 4443 * Step 1: Allocate and initialize itds, how many do we need? 4444 * One per transfer if interval >= 8 microframes, fewer if we use 4445 * multiple microframes per frame. 4446 */ 4447 4448 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4449 if (i > 16 || i == 0) { 4450 /* Spec page 271 says intervals > 16 are invalid */ 4451 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4452 return USBD_INVAL; 4453 } 4454 4455 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4456 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4457 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4458 4459 if (frames == 0) { 4460 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4461 return USBD_INVAL; 4462 } 4463 4464 dma_buf = &xfer->ux_dmabuf; 4465 offs = 0; 4466 4467 for (i = 0; i < frames; i++) { 4468 int froffs = offs; 4469 itd = ehci_alloc_itd(sc); 4470 4471 if (prev != NULL) { 4472 prev->itd.itd_next = 4473 htole32(itd->physaddr | EHCI_LINK_ITD); 4474 usb_syncmem(&itd->dma, 4475 itd->offs + offsetof(ehci_itd_t, itd_next), 4476 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4477 4478 prev->xfer_next = itd; 4479 } else { 4480 start = itd; 4481 } 4482 4483 /* 4484 * Step 1.5, initialize uframes 4485 */ 4486 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4487 /* Calculate which page in the list this starts in */ 4488 int addr = DMAADDR(dma_buf, froffs); 4489 addr = EHCI_PAGE_OFFSET(addr); 4490 addr += (offs - froffs); 4491 addr = EHCI_PAGE(addr); 4492 addr /= EHCI_PAGE_SIZE; 4493 4494 /* 4495 * This gets the initial offset into the first page, 4496 * looks how far further along the current uframe 4497 * offset is. Works out how many pages that is. 4498 */ 4499 4500 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4501 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4502 EHCI_ITD_SET_PG(addr) | 4503 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4504 4505 total_length += xfer->ux_frlengths[trans_count]; 4506 offs += xfer->ux_frlengths[trans_count]; 4507 trans_count++; 4508 4509 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4510 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4511 break; 4512 } 4513 } 4514 4515 /* 4516 * Step 1.75, set buffer pointers. To simplify matters, all 4517 * pointers are filled out for the next 7 hardware pages in 4518 * the dma block, so no need to worry what pages to cover 4519 * and what to not. 4520 */ 4521 4522 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4523 /* 4524 * Don't try to lookup a page that's past the end 4525 * of buffer 4526 */ 4527 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4528 if (page_offs >= dma_buf->udma_block->size) 4529 break; 4530 4531 unsigned long long page = DMAADDR(dma_buf, page_offs); 4532 page = EHCI_PAGE(page); 4533 itd->itd.itd_bufr[j] = 4534 htole32(EHCI_ITD_SET_BPTR(page)); 4535 itd->itd.itd_bufr_hi[j] = 4536 htole32(page >> 32); 4537 } 4538 4539 /* 4540 * Other special values 4541 */ 4542 4543 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4544 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4545 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4546 4547 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4548 ? 1 : 0; 4549 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4550 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4551 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4552 4553 /* FIXME: handle invalid trans */ 4554 itd->itd.itd_bufr[2] |= 4555 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4556 4557 usb_syncmem(&itd->dma, 4558 itd->offs + offsetof(ehci_itd_t, itd_next), 4559 sizeof(ehci_itd_t), 4560 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4561 4562 prev = itd; 4563 } /* End of frame */ 4564 4565 stop = itd; 4566 stop->xfer_next = NULL; 4567 4568 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4569 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4570 4571 /* 4572 * Part 2: Transfer descriptors have now been set up, now they must 4573 * be scheduled into the period frame list. Erk. Not wanting to 4574 * complicate matters, transfer is denied if the transfer spans 4575 * more than the period frame list. 4576 */ 4577 4578 mutex_enter(&sc->sc_lock); 4579 4580 /* Start inserting frames */ 4581 if (epipe->u.isoc.cur_xfers > 0) { 4582 frindex = epipe->u.isoc.next_frame; 4583 } else { 4584 frindex = EOREAD4(sc, EHCI_FRINDEX); 4585 frindex = frindex >> 3; /* Erase microframe index */ 4586 frindex += 2; 4587 } 4588 4589 if (frindex >= sc->sc_flsize) 4590 frindex &= (sc->sc_flsize - 1); 4591 4592 /* What's the frame interval? */ 4593 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4594 if (i / USB_UFRAMES_PER_FRAME == 0) 4595 i = 1; 4596 else 4597 i /= USB_UFRAMES_PER_FRAME; 4598 4599 itd = start; 4600 for (j = 0; j < frames; j++) { 4601 if (itd == NULL) 4602 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4603 4604 itd->itd.itd_next = sc->sc_flist[frindex]; 4605 if (itd->itd.itd_next == 0) 4606 /* FIXME: frindex table gets initialized to NULL 4607 * or EHCI_NULL? */ 4608 itd->itd.itd_next = EHCI_NULL; 4609 4610 usb_syncmem(&itd->dma, 4611 itd->offs + offsetof(ehci_itd_t, itd_next), 4612 sizeof(itd->itd.itd_next), 4613 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4614 4615 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4616 4617 usb_syncmem(&sc->sc_fldma, 4618 sizeof(ehci_link_t) * frindex, 4619 sizeof(ehci_link_t), 4620 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4621 4622 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4623 sc->sc_softitds[frindex] = itd; 4624 if (itd->u.frame_list.next != NULL) 4625 itd->u.frame_list.next->u.frame_list.prev = itd; 4626 itd->slot = frindex; 4627 itd->u.frame_list.prev = NULL; 4628 4629 frindex += i; 4630 if (frindex >= sc->sc_flsize) 4631 frindex -= sc->sc_flsize; 4632 4633 itd = itd->xfer_next; 4634 } 4635 4636 epipe->u.isoc.cur_xfers++; 4637 epipe->u.isoc.next_frame = frindex; 4638 4639 exfer->ex_itdstart = start; 4640 exfer->ex_itdend = stop; 4641 4642 ehci_add_intr_list(sc, exfer); 4643 xfer->ux_status = USBD_IN_PROGRESS; 4644 xfer->ux_done = 0; 4645 mutex_exit(&sc->sc_lock); 4646 4647 if (sc->sc_bus.ub_usepolling) { 4648 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4649 ehci_waitintr(sc, xfer); 4650 } 4651 4652 return USBD_IN_PROGRESS; 4653 } 4654 4655 Static void 4656 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4657 { 4658 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4659 4660 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4661 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4662 } 4663 4664 Static void 4665 ehci_device_isoc_close(usbd_pipe_handle pipe) 4666 { 4667 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4668 4669 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4670 } 4671 4672 Static void 4673 ehci_device_isoc_done(usbd_xfer_handle xfer) 4674 { 4675 struct ehci_xfer *exfer; 4676 ehci_softc_t *sc; 4677 struct ehci_pipe *epipe; 4678 4679 exfer = EXFER(xfer); 4680 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4681 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4682 4683 KASSERT(mutex_owned(&sc->sc_lock)); 4684 4685 epipe->u.isoc.cur_xfers--; 4686 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4687 ehci_del_intr_list(sc, exfer); 4688 ehci_rem_free_itd_chain(sc, exfer); 4689 } 4690 4691 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4692 BUS_DMASYNC_POSTREAD); 4693 4694 } 4695
Indexes created Wed Oct 01 19:09:53 GMT 2025