ehci.c revision 1.234.2.41
1 /* $NetBSD: ehci.c,v 1.234.2.41 2015/03/15 11:52:47 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.41 2015/03/15 11:52:47 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 85 #include <dev/usb/ehcireg.h> 86 #include <dev/usb/ehcivar.h> 87 #include <dev/usb/usbroothub.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 /* ehci_soft_sitd_t *sitd; */ 135 } tail; 136 union { 137 /* Control pipe */ 138 struct { 139 usb_dma_t reqdma; 140 } ctl; 141 /* Interrupt pipe */ 142 struct { 143 u_int length; 144 } intr; 145 /* Bulk pipe */ 146 struct { 147 u_int length; 148 } bulk; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 } u; 155 }; 156 157 Static usbd_status ehci_open(usbd_pipe_handle); 158 Static void ehci_poll(struct usbd_bus *); 159 Static void ehci_softintr(void *); 160 Static int ehci_intr1(ehci_softc_t *); 161 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 162 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 166 Static void ehci_idone(struct ehci_xfer *); 167 Static void ehci_timeout(void *); 168 Static void ehci_timeout_task(void *); 169 Static void ehci_intrlist_timeout(void *); 170 Static void ehci_doorbell(void *); 171 Static void ehci_pcd(void *); 172 173 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 174 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 Static int ehci_roothub_ctrl(struct usbd_bus *, 177 usb_device_request_t *, void *, int); 178 179 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 180 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 181 Static void ehci_root_intr_abort(usbd_xfer_handle); 182 Static void ehci_root_intr_close(usbd_pipe_handle); 183 Static void ehci_root_intr_done(usbd_xfer_handle); 184 185 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 186 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 187 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 188 Static void ehci_device_ctrl_close(usbd_pipe_handle); 189 Static void ehci_device_ctrl_done(usbd_xfer_handle); 190 191 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 192 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 193 Static void ehci_device_bulk_abort(usbd_xfer_handle); 194 Static void ehci_device_bulk_close(usbd_pipe_handle); 195 Static void ehci_device_bulk_done(usbd_xfer_handle); 196 197 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 198 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 199 Static void ehci_device_intr_abort(usbd_xfer_handle); 200 Static void ehci_device_intr_close(usbd_pipe_handle); 201 Static void ehci_device_intr_done(usbd_xfer_handle); 202 203 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 204 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 205 Static void ehci_device_isoc_abort(usbd_xfer_handle); 206 Static void ehci_device_isoc_close(usbd_pipe_handle); 207 Static void ehci_device_isoc_done(usbd_xfer_handle); 208 209 Static usbd_status ehci_device_fs_isoc_transfer(usbd_xfer_handle); 210 Static usbd_status ehci_device_fs_isoc_start(usbd_xfer_handle); 211 Static void ehci_device_fs_isoc_abort(usbd_xfer_handle); 212 Static void ehci_device_fs_isoc_close(usbd_pipe_handle); 213 Static void ehci_device_fs_isoc_done(usbd_xfer_handle); 214 215 Static void ehci_device_clear_toggle(usbd_pipe_handle); 216 Static void ehci_noop(usbd_pipe_handle); 217 218 Static void ehci_disown(ehci_softc_t *, int, int); 219 220 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 221 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 222 223 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 224 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 225 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 226 ehci_softc_t *, int, int, usbd_xfer_handle, 227 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 228 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 229 ehci_soft_qtd_t *); 230 231 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 232 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *); 233 Static void ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *); 234 Static void ehci_free_sitd(ehci_softc_t *, ehci_soft_sitd_t *); 235 Static void ehci_rem_free_itd_chain(ehci_softc_t *, 236 struct ehci_xfer *); 237 Static void ehci_rem_free_sitd_chain(ehci_softc_t *, 238 struct ehci_xfer *); 239 Static void ehci_abort_isoc_xfer(usbd_xfer_handle, 240 usbd_status); 241 242 Static usbd_status ehci_device_request(usbd_xfer_handle); 243 244 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 245 int); 246 247 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 248 ehci_soft_qh_t *); 249 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 250 ehci_soft_qh_t *); 251 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 252 Static void ehci_sync_hc(ehci_softc_t *); 253 254 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 255 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 256 257 #ifdef EHCI_DEBUG 258 Static ehci_softc_t *theehci; 259 void ehci_dump(void); 260 #endif 261 262 #ifdef EHCI_DEBUG 263 Static void ehci_dump_regs(ehci_softc_t *); 264 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 265 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 266 Static void ehci_dump_qtd(ehci_qtd_t *); 267 Static void ehci_dump_sqh(ehci_soft_qh_t *); 268 Static void ehci_dump_sitd(struct ehci_soft_itd *); 269 Static void ehci_dump_itd(struct ehci_soft_itd *); 270 Static void ehci_dump_exfer(struct ehci_xfer *); 271 #endif 272 273 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 274 275 #define ehci_add_intr_list(sc, ex) \ 276 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 277 #define ehci_del_intr_list(sc, ex) \ 278 do { \ 279 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 280 (ex)->ex_next.tqe_prev = NULL; \ 281 } while (0) 282 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 283 284 Static const struct usbd_bus_methods ehci_bus_methods = { 285 .ubm_open = ehci_open, 286 .ubm_softint = ehci_softintr, 287 .ubm_dopoll = ehci_poll, 288 .ubm_allocx = ehci_allocx, 289 .ubm_freex = ehci_freex, 290 .ubm_getlock = ehci_get_lock, 291 .ubm_rhctrl = ehci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 295 .upm_transfer = ehci_root_intr_transfer, 296 .upm_start = ehci_root_intr_start, 297 .upm_abort = ehci_root_intr_abort, 298 .upm_close = ehci_root_intr_close, 299 .upm_cleartoggle = ehci_noop, 300 .upm_done = ehci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 304 .upm_transfer = ehci_device_ctrl_transfer, 305 .upm_start = ehci_device_ctrl_start, 306 .upm_abort = ehci_device_ctrl_abort, 307 .upm_close = ehci_device_ctrl_close, 308 .upm_cleartoggle = ehci_noop, 309 .upm_done = ehci_device_ctrl_done, 310 }; 311 312 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 313 .upm_transfer = ehci_device_intr_transfer, 314 .upm_start = ehci_device_intr_start, 315 .upm_abort = ehci_device_intr_abort, 316 .upm_close = ehci_device_intr_close, 317 .upm_cleartoggle = ehci_device_clear_toggle, 318 .upm_done = ehci_device_intr_done, 319 }; 320 321 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 322 .upm_transfer = ehci_device_bulk_transfer, 323 .upm_start = ehci_device_bulk_start, 324 .upm_abort = ehci_device_bulk_abort, 325 .upm_close = ehci_device_bulk_close, 326 .upm_cleartoggle = ehci_device_clear_toggle, 327 .upm_done = ehci_device_bulk_done, 328 }; 329 330 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 331 .upm_transfer = ehci_device_isoc_transfer, 332 .upm_start = ehci_device_isoc_start, 333 .upm_abort = ehci_device_isoc_abort, 334 .upm_close = ehci_device_isoc_close, 335 .upm_cleartoggle = ehci_noop, 336 .upm_done = ehci_device_isoc_done, 337 }; 338 339 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 340 .upm_transfer = ehci_device_fs_isoc_transfer, 341 .upm_start = ehci_device_fs_isoc_start, 342 .upm_abort = ehci_device_fs_isoc_abort, 343 .upm_close = ehci_device_fs_isoc_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_fs_isoc_done, 346 }; 347 348 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 349 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 350 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 351 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 352 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 353 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 354 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 355 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 356 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 357 }; 358 359 int 360 ehci_init(ehci_softc_t *sc) 361 { 362 uint32_t vers, sparams, cparams, hcr; 363 u_int i; 364 usbd_status err; 365 ehci_soft_qh_t *sqh; 366 u_int ncomp; 367 368 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 369 #ifdef EHCI_DEBUG 370 theehci = sc; 371 #endif 372 373 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 374 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 375 cv_init(&sc->sc_softwake_cv, "ehciab"); 376 cv_init(&sc->sc_doorbell, "ehcidi"); 377 378 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 379 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 380 381 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 382 ehci_doorbell, sc); 383 KASSERT(sc->sc_doorbell_si != NULL); 384 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 385 ehci_pcd, sc); 386 KASSERT(sc->sc_pcd_si != NULL); 387 388 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 389 390 vers = EREAD2(sc, EHCI_HCIVERSION); 391 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 392 vers >> 8, vers & 0xff); 393 394 sparams = EREAD4(sc, EHCI_HCSPARAMS); 395 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 396 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 397 ncomp = EHCI_HCS_N_CC(sparams); 398 if (ncomp != sc->sc_ncomp) { 399 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 400 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 401 #if NOHCI == 0 || NUHCI == 0 402 aprint_error("%s: ohci or uhci probably not configured\n", 403 device_xname(sc->sc_dev)); 404 #endif 405 if (ncomp < sc->sc_ncomp) 406 sc->sc_ncomp = ncomp; 407 } 408 if (sc->sc_ncomp > 0) { 409 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 410 aprint_normal("%s: companion controller%s, %d port%s each:", 411 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 412 EHCI_HCS_N_PCC(sparams), 413 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 414 for (i = 0; i < sc->sc_ncomp; i++) 415 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 416 aprint_normal("\n"); 417 } 418 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 419 cparams = EREAD4(sc, EHCI_HCCPARAMS); 420 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 421 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 422 423 if (EHCI_HCC_64BIT(cparams)) { 424 /* MUST clear segment register if 64 bit capable. */ 425 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 426 } 427 428 sc->sc_bus.ub_revision = USBREV_2_0; 429 sc->sc_bus.ub_usedma = true; 430 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 431 432 /* Reset the controller */ 433 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 434 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 435 usb_delay_ms(&sc->sc_bus, 1); 436 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 437 for (i = 0; i < 100; i++) { 438 usb_delay_ms(&sc->sc_bus, 1); 439 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 440 if (!hcr) 441 break; 442 } 443 if (hcr) { 444 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 445 return EIO; 446 } 447 if (sc->sc_vendor_init) 448 sc->sc_vendor_init(sc); 449 450 /* 451 * If we are doing embedded transaction translation function, force 452 * the controller to host mode. 453 */ 454 if (sc->sc_flags & EHCIF_ETTF) { 455 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 456 usbmode &= ~EHCI_USBMODE_CM; 457 usbmode |= EHCI_USBMODE_CM_HOST; 458 EWRITE4(sc, EHCI_USBMODE, usbmode); 459 } 460 461 /* XXX need proper intr scheduling */ 462 sc->sc_rand = 96; 463 464 /* frame list size at default, read back what we got and use that */ 465 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 466 case 0: sc->sc_flsize = 1024; break; 467 case 1: sc->sc_flsize = 512; break; 468 case 2: sc->sc_flsize = 256; break; 469 case 3: return EIO; 470 } 471 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 472 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 473 if (err) 474 return err; 475 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 476 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 477 478 for (i = 0; i < sc->sc_flsize; i++) { 479 sc->sc_flist[i] = EHCI_NULL; 480 } 481 482 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 483 484 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 485 KM_SLEEP); 486 if (sc->sc_softitds == NULL) 487 return ENOMEM; 488 LIST_INIT(&sc->sc_freeitds); 489 LIST_INIT(&sc->sc_freesitds); 490 TAILQ_INIT(&sc->sc_intrhead); 491 492 /* Set up the bus struct. */ 493 sc->sc_bus.ub_methods = &ehci_bus_methods; 494 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 495 496 sc->sc_eintrs = EHCI_NORMAL_INTRS; 497 498 /* 499 * Allocate the interrupt dummy QHs. These are arranged to give poll 500 * intervals that are powers of 2 times 1ms. 501 */ 502 for (i = 0; i < EHCI_INTRQHS; i++) { 503 sqh = ehci_alloc_sqh(sc); 504 if (sqh == NULL) { 505 err = ENOMEM; 506 goto bad1; 507 } 508 sc->sc_islots[i].sqh = sqh; 509 } 510 for (i = 0; i < EHCI_INTRQHS; i++) { 511 sqh = sc->sc_islots[i].sqh; 512 if (i == 0) { 513 /* The last (1ms) QH terminates. */ 514 sqh->qh.qh_link = EHCI_NULL; 515 sqh->next = NULL; 516 } else { 517 /* Otherwise the next QH has half the poll interval */ 518 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 519 sqh->qh.qh_link = htole32(sqh->next->physaddr | 520 EHCI_LINK_QH); 521 } 522 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 523 sqh->qh.qh_curqtd = EHCI_NULL; 524 sqh->next = NULL; 525 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 526 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 527 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 528 sqh->sqtd = NULL; 529 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 531 } 532 /* Point the frame list at the last level (128ms). */ 533 for (i = 0; i < sc->sc_flsize; i++) { 534 int j; 535 536 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 537 revbits[i & (EHCI_MAX_POLLRATE-1)]; 538 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 539 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 540 i)].sqh->physaddr); 541 } 542 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 543 BUS_DMASYNC_PREWRITE); 544 545 /* Allocate dummy QH that starts the async list. */ 546 sqh = ehci_alloc_sqh(sc); 547 if (sqh == NULL) { 548 err = ENOMEM; 549 goto bad1; 550 } 551 /* Fill the QH */ 552 sqh->qh.qh_endp = 553 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 554 sqh->qh.qh_link = 555 htole32(sqh->physaddr | EHCI_LINK_QH); 556 sqh->qh.qh_curqtd = EHCI_NULL; 557 sqh->next = NULL; 558 /* Fill the overlay qTD */ 559 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 560 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 561 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 562 sqh->sqtd = NULL; 563 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 564 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 565 #ifdef EHCI_DEBUG 566 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 567 ehci_dump_sqh(sqh); 568 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 569 #endif 570 571 /* Point to async list */ 572 sc->sc_async_head = sqh; 573 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 574 575 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 576 577 /* Turn on controller */ 578 EOWRITE4(sc, EHCI_USBCMD, 579 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 580 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 581 EHCI_CMD_ASE | 582 EHCI_CMD_PSE | 583 EHCI_CMD_RS); 584 585 /* Take over port ownership */ 586 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 587 588 for (i = 0; i < 100; i++) { 589 usb_delay_ms(&sc->sc_bus, 1); 590 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 591 if (!hcr) 592 break; 593 } 594 if (hcr) { 595 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 596 return EIO; 597 } 598 599 /* Enable interrupts */ 600 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 601 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 602 603 return 0; 604 605 #if 0 606 bad2: 607 ehci_free_sqh(sc, sc->sc_async_head); 608 #endif 609 bad1: 610 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 611 return err; 612 } 613 614 int 615 ehci_intr(void *v) 616 { 617 ehci_softc_t *sc = v; 618 int ret = 0; 619 620 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 621 622 if (sc == NULL) 623 return 0; 624 625 mutex_spin_enter(&sc->sc_intr_lock); 626 627 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 628 goto done; 629 630 /* If we get an interrupt while polling, then just ignore it. */ 631 if (sc->sc_bus.ub_usepolling) { 632 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 633 634 if (intrs) 635 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 636 USBHIST_LOGN(ehcidebug, 16, 637 "ignored interrupt while polling", 0, 0, 0, 0); 638 goto done; 639 } 640 641 ret = ehci_intr1(sc); 642 643 done: 644 mutex_spin_exit(&sc->sc_intr_lock); 645 return ret; 646 } 647 648 Static int 649 ehci_intr1(ehci_softc_t *sc) 650 { 651 uint32_t intrs, eintrs; 652 653 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 654 655 /* In case the interrupt occurs before initialization has completed. */ 656 if (sc == NULL) { 657 #ifdef DIAGNOSTIC 658 printf("ehci_intr1: sc == NULL\n"); 659 #endif 660 return 0; 661 } 662 663 KASSERT(mutex_owned(&sc->sc_intr_lock)); 664 665 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 666 if (!intrs) 667 return 0; 668 669 eintrs = intrs & sc->sc_eintrs; 670 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 671 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 672 if (!eintrs) 673 return 0; 674 675 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 676 if (eintrs & EHCI_STS_IAA) { 677 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 678 kpreempt_disable(); 679 KASSERT(sc->sc_doorbell_si != NULL); 680 softint_schedule(sc->sc_doorbell_si); 681 kpreempt_enable(); 682 eintrs &= ~EHCI_STS_IAA; 683 } 684 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 685 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 686 eintrs & EHCI_STS_INT ? 1 : 0, 687 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 688 usb_schedsoftintr(&sc->sc_bus); 689 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 690 } 691 if (eintrs & EHCI_STS_HSE) { 692 printf("%s: unrecoverable error, controller halted\n", 693 device_xname(sc->sc_dev)); 694 /* XXX what else */ 695 } 696 if (eintrs & EHCI_STS_PCD) { 697 kpreempt_disable(); 698 KASSERT(sc->sc_pcd_si != NULL); 699 softint_schedule(sc->sc_pcd_si); 700 kpreempt_enable(); 701 eintrs &= ~EHCI_STS_PCD; 702 } 703 704 if (eintrs != 0) { 705 /* Block unprocessed interrupts. */ 706 sc->sc_eintrs &= ~eintrs; 707 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 708 printf("%s: blocking intrs 0x%x\n", 709 device_xname(sc->sc_dev), eintrs); 710 } 711 712 return 1; 713 } 714 715 Static void 716 ehci_doorbell(void *addr) 717 { 718 ehci_softc_t *sc = addr; 719 720 mutex_enter(&sc->sc_lock); 721 cv_broadcast(&sc->sc_doorbell); 722 mutex_exit(&sc->sc_lock); 723 } 724 725 Static void 726 ehci_pcd(void *addr) 727 { 728 ehci_softc_t *sc = addr; 729 usbd_xfer_handle xfer; 730 u_char *p; 731 int i, m; 732 733 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 734 735 mutex_enter(&sc->sc_lock); 736 xfer = sc->sc_intrxfer; 737 738 if (xfer == NULL) { 739 /* Just ignore the change. */ 740 goto done; 741 } 742 743 p = xfer->ux_buf; 744 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 745 memset(p, 0, xfer->ux_length); 746 for (i = 1; i <= m; i++) { 747 /* Pick out CHANGE bits from the status reg. */ 748 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 749 p[i/8] |= 1 << (i%8); 750 if (i % 8 == 7) 751 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 752 p[i/8], 0, 0); 753 } 754 xfer->ux_actlen = xfer->ux_length; 755 xfer->ux_status = USBD_NORMAL_COMPLETION; 756 757 usb_transfer_complete(xfer); 758 759 done: 760 mutex_exit(&sc->sc_lock); 761 } 762 763 Static void 764 ehci_softintr(void *v) 765 { 766 struct usbd_bus *bus = v; 767 ehci_softc_t *sc = bus->ub_hcpriv; 768 struct ehci_xfer *ex, *nextex; 769 770 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 771 772 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 773 774 /* 775 * The only explanation I can think of for why EHCI is as brain dead 776 * as UHCI interrupt-wise is that Intel was involved in both. 777 * An interrupt just tells us that something is done, we have no 778 * clue what, so we need to scan through all active transfers. :-( 779 */ 780 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 781 nextex = TAILQ_NEXT(ex, ex_next); 782 ehci_check_intr(sc, ex); 783 } 784 785 /* Schedule a callout to catch any dropped transactions. */ 786 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 787 !TAILQ_EMPTY(&sc->sc_intrhead)) 788 callout_reset(&sc->sc_tmo_intrlist, 789 hz, ehci_intrlist_timeout, sc); 790 791 if (sc->sc_softwake) { 792 sc->sc_softwake = 0; 793 cv_broadcast(&sc->sc_softwake_cv); 794 } 795 } 796 797 /* Check for an interrupt. */ 798 Static void 799 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 800 { 801 usbd_device_handle dev = ex->ex_xfer.ux_pipe->up_dev; 802 int attr; 803 804 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 805 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 806 807 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 808 809 attr = ex->ex_xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 810 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 811 if (dev->ud_speed == USB_SPEED_HIGH) 812 ehci_check_itd_intr(sc, ex); 813 else 814 ehci_check_sitd_intr(sc, ex); 815 } else 816 ehci_check_qh_intr(sc, ex); 817 818 return; 819 } 820 821 Static void 822 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 823 { 824 ehci_soft_qtd_t *sqtd, *lsqtd; 825 uint32_t status; 826 827 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 828 829 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 830 831 if (ex->ex_sqtdstart == NULL) { 832 printf("ehci_check_qh_intr: not valid sqtd\n"); 833 return; 834 } 835 836 lsqtd = ex->ex_sqtdend; 837 #ifdef DIAGNOSTIC 838 if (lsqtd == NULL) { 839 printf("ehci_check_qh_intr: lsqtd==0\n"); 840 return; 841 } 842 #endif 843 /* 844 * If the last TD is still active we need to check whether there 845 * is an error somewhere in the middle, or whether there was a 846 * short packet (SPD and not ACTIVE). 847 */ 848 usb_syncmem(&lsqtd->dma, 849 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 850 sizeof(lsqtd->qtd.qtd_status), 851 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 852 status = le32toh(lsqtd->qtd.qtd_status); 853 usb_syncmem(&lsqtd->dma, 854 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 855 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 856 if (status & EHCI_QTD_ACTIVE) { 857 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 858 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd; 859 sqtd = sqtd->nextqtd) { 860 usb_syncmem(&sqtd->dma, 861 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 862 sizeof(sqtd->qtd.qtd_status), 863 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 864 status = le32toh(sqtd->qtd.qtd_status); 865 usb_syncmem(&sqtd->dma, 866 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 867 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 868 /* If there's an active QTD the xfer isn't done. */ 869 if (status & EHCI_QTD_ACTIVE) 870 break; 871 /* Any kind of error makes the xfer done. */ 872 if (status & EHCI_QTD_HALTED) 873 goto done; 874 /* Handle short packets */ 875 if (EHCI_QTD_GET_BYTES(status) != 0) { 876 usbd_pipe_handle pipe = ex->ex_xfer.ux_pipe; 877 usb_endpoint_descriptor_t *ed = 878 pipe->up_endpoint->ue_edesc; 879 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 880 881 /* 882 * If we get here for a control transfer then 883 * we need to let the hardware complete the 884 * status phase. That is, we're not done 885 * quite yet. 886 * 887 * Otherwise, we're done. 888 */ 889 if (xt == UE_CONTROL) { 890 break; 891 } 892 goto done; 893 } 894 } 895 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 896 ex, ex->ex_sqtdstart, 0, 0); 897 #ifdef EHCI_DEBUG 898 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 0, 0); 899 ehci_dump_sqtds(ex->ex_sqtdstart); 900 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 0); 901 #endif 902 return; 903 } 904 done: 905 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 906 callout_stop(&ex->ex_xfer.ux_callout); 907 ehci_idone(ex); 908 } 909 910 Static void 911 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 912 { 913 ehci_soft_itd_t *itd; 914 int i; 915 916 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 917 918 KASSERT(mutex_owned(&sc->sc_lock)); 919 920 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 921 return; 922 923 if (ex->ex_itdstart == NULL) { 924 printf("ehci_check_itd_intr: not valid itd\n"); 925 return; 926 } 927 928 itd = ex->ex_itdend; 929 #ifdef DIAGNOSTIC 930 if (itd == NULL) { 931 printf("ehci_check_itd_intr: itdend == 0\n"); 932 return; 933 } 934 #endif 935 936 /* 937 * check no active transfers in last itd, meaning we're finished 938 */ 939 940 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 941 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 942 BUS_DMASYNC_POSTREAD); 943 944 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 945 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 946 break; 947 } 948 949 if (i == EHCI_ITD_NUFRAMES) { 950 goto done; /* All 8 descriptors inactive, it's done */ 951 } 952 953 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 954 ex->ex_itdstart, 0, 0); 955 return; 956 done: 957 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 958 callout_stop(&ex->ex_xfer.ux_callout); 959 ehci_idone(ex); 960 } 961 962 void 963 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 964 { 965 ehci_soft_sitd_t *sitd; 966 967 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 968 969 KASSERT(mutex_owned(&sc->sc_lock)); 970 971 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 972 return; 973 974 if (ex->ex_sitdstart == NULL) { 975 printf("ehci_check_sitd_intr: not valid sitd\n"); 976 return; 977 } 978 979 sitd = ex->ex_sitdend; 980 #ifdef DIAGNOSTIC 981 if (sitd == NULL) { 982 printf("ehci_check_sitd_intr: sitdend == 0\n"); 983 return; 984 } 985 #endif 986 987 /* 988 * check no active transfers in last sitd, meaning we're finished 989 */ 990 991 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 992 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 993 BUS_DMASYNC_POSTREAD); 994 995 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 996 return; 997 998 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 999 callout_stop(&(ex->ex_xfer.ux_callout)); 1000 ehci_idone(ex); 1001 } 1002 1003 1004 Static void 1005 ehci_idone(struct ehci_xfer *ex) 1006 { 1007 usbd_xfer_handle xfer = &ex->ex_xfer; 1008 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1009 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1010 ehci_soft_qtd_t *sqtd, *lsqtd; 1011 uint32_t status = 0, nstatus = 0; 1012 int actlen; 1013 1014 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1015 1016 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1017 1018 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1019 1020 #ifdef DIAGNOSTIC 1021 #ifdef EHCI_DEBUG 1022 if (ex->ex_isdone) { 1023 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1024 ehci_dump_exfer(ex); 1025 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1026 } 1027 #endif 1028 KASSERT(!ex->ex_isdone); 1029 ex->ex_isdone = true; 1030 #endif 1031 1032 if (xfer->ux_status == USBD_CANCELLED || 1033 xfer->ux_status == USBD_TIMEOUT) { 1034 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1035 return; 1036 } 1037 1038 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1039 1040 /* The transfer is done, compute actual length and status. */ 1041 1042 u_int xfertype, speed; 1043 1044 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1045 speed = xfer->ux_pipe->up_dev->ud_speed; 1046 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1047 /* HS isoc transfer */ 1048 1049 struct ehci_soft_itd *itd; 1050 int i, nframes, len, uframes; 1051 1052 nframes = 0; 1053 actlen = 0; 1054 1055 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1056 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1057 1058 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1059 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1060 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1061 BUS_DMASYNC_POSTREAD); 1062 1063 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1064 /* 1065 * XXX - driver didn't fill in the frame full 1066 * of uframes. This leads to scheduling 1067 * inefficiencies, but working around 1068 * this doubles complexity of tracking 1069 * an xfer. 1070 */ 1071 if (nframes >= xfer->ux_nframes) 1072 break; 1073 1074 status = le32toh(itd->itd.itd_ctl[i]); 1075 len = EHCI_ITD_GET_LEN(status); 1076 if (EHCI_ITD_GET_STATUS(status) != 0) 1077 len = 0; /*No valid data on error*/ 1078 1079 xfer->ux_frlengths[nframes++] = len; 1080 actlen += len; 1081 } 1082 1083 if (nframes >= xfer->ux_nframes) 1084 break; 1085 } 1086 1087 xfer->ux_actlen = actlen; 1088 xfer->ux_status = USBD_NORMAL_COMPLETION; 1089 goto end; 1090 } 1091 1092 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1093 /* FS isoc transfer */ 1094 struct ehci_soft_sitd *sitd; 1095 int nframes, len; 1096 1097 nframes = 0; 1098 actlen = 0; 1099 1100 for (sitd = ex->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1101 usb_syncmem(&sitd->dma,sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 1102 sizeof(sitd->sitd.sitd_buffer), BUS_DMASYNC_POSTWRITE | 1103 BUS_DMASYNC_POSTREAD); 1104 1105 /* 1106 * XXX - driver didn't fill in the frame full 1107 * of uframes. This leads to scheduling 1108 * inefficiencies, but working around 1109 * this doubles complexity of tracking 1110 * an xfer. 1111 */ 1112 if (nframes >= xfer->ux_nframes) 1113 break; 1114 1115 status = le32toh(sitd->sitd.sitd_trans); 1116 len = EHCI_SITD_GET_LEN(status); 1117 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1118 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1119 /* No valid data on error */ 1120 len = xfer->ux_frlengths[nframes]; 1121 } 1122 1123 /* 1124 * frlengths[i]: # of bytes to send 1125 * len: # of bytes host didn't send 1126 */ 1127 xfer->ux_frlengths[nframes] -= len; 1128 /* frlengths[i]: # of bytes host sent */ 1129 actlen += xfer->ux_frlengths[nframes++]; 1130 1131 if (nframes >= xfer->ux_nframes) 1132 break; 1133 } 1134 1135 xfer->ux_actlen = actlen; 1136 xfer->ux_status = USBD_NORMAL_COMPLETION; 1137 goto end; 1138 } 1139 KASSERT(xfertype != UE_ISOCHRONOUS); 1140 1141 /* Continue processing xfers using queue heads */ 1142 1143 #ifdef EHCI_DEBUG 1144 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1145 ehci_dump_sqtds(ex->ex_sqtdstart); 1146 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1147 #endif 1148 1149 lsqtd = ex->ex_sqtdend; 1150 actlen = 0; 1151 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd->nextqtd; 1152 sqtd = sqtd->nextqtd) { 1153 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1154 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1155 nstatus = le32toh(sqtd->qtd.qtd_status); 1156 if (nstatus & EHCI_QTD_ACTIVE) 1157 break; 1158 1159 status = nstatus; 1160 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1161 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1162 } 1163 1164 1165 /* 1166 * If there are left over TDs we need to update the toggle. 1167 * The default pipe doesn't need it since control transfers 1168 * start the toggle at 0 every time. 1169 * For a short transfer we need to update the toggle for the missing 1170 * packets within the qTD. 1171 */ 1172 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1173 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1174 USBHIST_LOG(ehcidebug, 1175 "toggle update status=0x%08x nstatus=0x%08x", 1176 status, nstatus, 0, 0); 1177 #if 0 1178 ehci_dump_sqh(epipe->sqh); 1179 ehci_dump_sqtds(ex->ex_sqtdstart); 1180 #endif 1181 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1182 } 1183 1184 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1185 actlen, status, 0); 1186 xfer->ux_actlen = actlen; 1187 if (status & EHCI_QTD_HALTED) { 1188 #ifdef EHCI_DEBUG 1189 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1190 xfer->ux_pipe->up_dev->ud_addr, 1191 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1192 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1193 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1194 0, 0); 1195 USBHIST_LOG(ehcidebug, 1196 "active =%d halted=%d buferr=%d babble=%d", 1197 status & EHCI_QTD_ACTIVE ? 1 : 0, 1198 status & EHCI_QTD_HALTED ? 1 : 0, 1199 status & EHCI_QTD_BUFERR ? 1 : 0, 1200 status & EHCI_QTD_BABBLE ? 1 : 0); 1201 1202 USBHIST_LOG(ehcidebug, 1203 "xacterr=%d missed=%d split =%d ping =%d", 1204 status & EHCI_QTD_XACTERR ? 1 : 0, 1205 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1206 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1207 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1208 1209 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1210 ehci_dump_sqh(epipe->sqh); 1211 ehci_dump_sqtds(ex->ex_sqtdstart); 1212 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1213 #endif 1214 /* low&full speed has an extra error flag */ 1215 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1216 EHCI_QH_SPEED_HIGH) 1217 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1218 else 1219 status &= EHCI_QTD_STATERRS; 1220 if (status == 0) /* no other errors means a stall */ { 1221 xfer->ux_status = USBD_STALLED; 1222 } else { 1223 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1224 } 1225 /* XXX need to reset TT on missed microframe */ 1226 if (status & EHCI_QTD_MISSEDMICRO) { 1227 printf("%s: missed microframe, TT reset not " 1228 "implemented, hub might be inoperational\n", 1229 device_xname(sc->sc_dev)); 1230 } 1231 } else { 1232 xfer->ux_status = USBD_NORMAL_COMPLETION; 1233 } 1234 1235 end: 1236 /* 1237 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1238 * during this call, before methods->done is called: dma sync required 1239 * beforehand? 1240 */ 1241 usb_transfer_complete(xfer); 1242 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1243 } 1244 1245 /* 1246 * Wait here until controller claims to have an interrupt. 1247 * Then call ehci_intr and return. Use timeout to avoid waiting 1248 * too long. 1249 */ 1250 Static void 1251 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1252 { 1253 int timo; 1254 uint32_t intrs; 1255 1256 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1257 1258 xfer->ux_status = USBD_IN_PROGRESS; 1259 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1260 usb_delay_ms(&sc->sc_bus, 1); 1261 if (sc->sc_dying) 1262 break; 1263 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1264 sc->sc_eintrs; 1265 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1266 #ifdef EHCI_DEBUG 1267 if (ehcidebug > 15) 1268 ehci_dump_regs(sc); 1269 #endif 1270 if (intrs) { 1271 mutex_spin_enter(&sc->sc_intr_lock); 1272 ehci_intr1(sc); 1273 mutex_spin_exit(&sc->sc_intr_lock); 1274 if (xfer->ux_status != USBD_IN_PROGRESS) 1275 return; 1276 } 1277 } 1278 1279 /* Timeout */ 1280 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1281 xfer->ux_status = USBD_TIMEOUT; 1282 mutex_enter(&sc->sc_lock); 1283 usb_transfer_complete(xfer); 1284 mutex_exit(&sc->sc_lock); 1285 /* XXX should free TD */ 1286 } 1287 1288 Static void 1289 ehci_poll(struct usbd_bus *bus) 1290 { 1291 ehci_softc_t *sc = bus->ub_hcpriv; 1292 1293 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1294 1295 #ifdef EHCI_DEBUG 1296 static int last; 1297 int new; 1298 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1299 if (new != last) { 1300 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1301 last = new; 1302 } 1303 #endif 1304 1305 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1306 mutex_spin_enter(&sc->sc_intr_lock); 1307 ehci_intr1(sc); 1308 mutex_spin_exit(&sc->sc_intr_lock); 1309 } 1310 } 1311 1312 void 1313 ehci_childdet(device_t self, device_t child) 1314 { 1315 struct ehci_softc *sc = device_private(self); 1316 1317 KASSERT(sc->sc_child == child); 1318 sc->sc_child = NULL; 1319 } 1320 1321 int 1322 ehci_detach(struct ehci_softc *sc, int flags) 1323 { 1324 int rv = 0; 1325 1326 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1327 1328 if (sc->sc_child != NULL) 1329 rv = config_detach(sc->sc_child, flags); 1330 1331 if (rv != 0) 1332 return rv; 1333 1334 callout_halt(&sc->sc_tmo_intrlist, NULL); 1335 callout_destroy(&sc->sc_tmo_intrlist); 1336 1337 /* XXX free other data structures XXX */ 1338 if (sc->sc_softitds) 1339 kmem_free(sc->sc_softitds, 1340 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1341 cv_destroy(&sc->sc_doorbell); 1342 cv_destroy(&sc->sc_softwake_cv); 1343 1344 #if 0 1345 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1346 1347 softint_disestablish(sc->sc_doorbell_si); 1348 softint_disestablish(sc->sc_pcd_si); 1349 1350 mutex_destroy(&sc->sc_lock); 1351 mutex_destroy(&sc->sc_intr_lock); 1352 #endif 1353 1354 pool_cache_destroy(sc->sc_xferpool); 1355 1356 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1357 1358 return rv; 1359 } 1360 1361 1362 int 1363 ehci_activate(device_t self, enum devact act) 1364 { 1365 struct ehci_softc *sc = device_private(self); 1366 1367 switch (act) { 1368 case DVACT_DEACTIVATE: 1369 sc->sc_dying = 1; 1370 return 0; 1371 default: 1372 return EOPNOTSUPP; 1373 } 1374 } 1375 1376 /* 1377 * Handle suspend/resume. 1378 * 1379 * We need to switch to polling mode here, because this routine is 1380 * called from an interrupt context. This is all right since we 1381 * are almost suspended anyway. 1382 * 1383 * Note that this power handler isn't to be registered directly; the 1384 * bus glue needs to call out to it. 1385 */ 1386 bool 1387 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1388 { 1389 ehci_softc_t *sc = device_private(dv); 1390 int i; 1391 uint32_t cmd, hcr; 1392 1393 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1394 1395 mutex_spin_enter(&sc->sc_intr_lock); 1396 sc->sc_bus.ub_usepolling++; 1397 mutex_spin_exit(&sc->sc_intr_lock); 1398 1399 for (i = 1; i <= sc->sc_noport; i++) { 1400 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1401 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1402 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1403 } 1404 1405 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1406 1407 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1408 EOWRITE4(sc, EHCI_USBCMD, cmd); 1409 1410 for (i = 0; i < 100; i++) { 1411 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1412 if (hcr == 0) 1413 break; 1414 1415 usb_delay_ms(&sc->sc_bus, 1); 1416 } 1417 if (hcr != 0) 1418 printf("%s: reset timeout\n", device_xname(dv)); 1419 1420 cmd &= ~EHCI_CMD_RS; 1421 EOWRITE4(sc, EHCI_USBCMD, cmd); 1422 1423 for (i = 0; i < 100; i++) { 1424 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1425 if (hcr == EHCI_STS_HCH) 1426 break; 1427 1428 usb_delay_ms(&sc->sc_bus, 1); 1429 } 1430 if (hcr != EHCI_STS_HCH) 1431 printf("%s: config timeout\n", device_xname(dv)); 1432 1433 mutex_spin_enter(&sc->sc_intr_lock); 1434 sc->sc_bus.ub_usepolling--; 1435 mutex_spin_exit(&sc->sc_intr_lock); 1436 1437 return true; 1438 } 1439 1440 bool 1441 ehci_resume(device_t dv, const pmf_qual_t *qual) 1442 { 1443 ehci_softc_t *sc = device_private(dv); 1444 int i; 1445 uint32_t cmd, hcr; 1446 1447 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1448 1449 /* restore things in case the bios sucks */ 1450 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1451 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1452 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1453 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1454 1455 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1456 1457 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1458 1459 hcr = 0; 1460 for (i = 1; i <= sc->sc_noport; i++) { 1461 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1462 if ((cmd & EHCI_PS_PO) == 0 && 1463 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1464 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1465 hcr = 1; 1466 } 1467 } 1468 1469 if (hcr) { 1470 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1471 1472 for (i = 1; i <= sc->sc_noport; i++) { 1473 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1474 if ((cmd & EHCI_PS_PO) == 0 && 1475 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1476 EOWRITE4(sc, EHCI_PORTSC(i), 1477 cmd & ~EHCI_PS_FPR); 1478 } 1479 } 1480 1481 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1482 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1483 1484 for (i = 0; i < 100; i++) { 1485 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1486 if (hcr != EHCI_STS_HCH) 1487 break; 1488 1489 usb_delay_ms(&sc->sc_bus, 1); 1490 } 1491 if (hcr == EHCI_STS_HCH) 1492 printf("%s: config timeout\n", device_xname(dv)); 1493 1494 return true; 1495 } 1496 1497 /* 1498 * Shut down the controller when the system is going down. 1499 */ 1500 bool 1501 ehci_shutdown(device_t self, int flags) 1502 { 1503 ehci_softc_t *sc = device_private(self); 1504 1505 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1506 1507 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1508 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1509 return true; 1510 } 1511 1512 Static usbd_xfer_handle 1513 ehci_allocx(struct usbd_bus *bus) 1514 { 1515 struct ehci_softc *sc = bus->ub_hcpriv; 1516 usbd_xfer_handle xfer; 1517 1518 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1519 if (xfer != NULL) { 1520 memset(xfer, 0, sizeof(struct ehci_xfer)); 1521 #ifdef DIAGNOSTIC 1522 EXFER(xfer)->ex_isdone = true; 1523 xfer->ux_state = XFER_BUSY; 1524 #endif 1525 } 1526 return xfer; 1527 } 1528 1529 Static void 1530 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1531 { 1532 struct ehci_softc *sc = bus->ub_hcpriv; 1533 1534 KASSERT(xfer->ux_state == XFER_BUSY); 1535 KASSERT(EXFER(xfer)->ex_isdone); 1536 #ifdef DIAGNOSTIC 1537 xfer->ux_state = XFER_FREE; 1538 #endif 1539 pool_cache_put(sc->sc_xferpool, xfer); 1540 } 1541 1542 Static void 1543 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1544 { 1545 struct ehci_softc *sc = bus->ub_hcpriv; 1546 1547 *lock = &sc->sc_lock; 1548 } 1549 1550 Static void 1551 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1552 { 1553 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1554 1555 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1556 1557 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1558 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1559 #ifdef EHCI_DEBUG 1560 if (ehcidebug) 1561 usbd_dump_pipe(pipe); 1562 #endif 1563 epipe->nexttoggle = 0; 1564 } 1565 1566 Static void 1567 ehci_noop(usbd_pipe_handle pipe) 1568 { 1569 } 1570 1571 #ifdef EHCI_DEBUG 1572 /* 1573 * Unused function - this is meant to be called from a kernel 1574 * debugger. 1575 */ 1576 void 1577 ehci_dump(void) 1578 { 1579 ehci_softc_t *sc = theehci; 1580 int i; 1581 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1582 EOREAD4(sc, EHCI_USBCMD), 1583 EOREAD4(sc, EHCI_USBSTS), 1584 EOREAD4(sc, EHCI_USBINTR)); 1585 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1586 EOREAD4(sc, EHCI_FRINDEX), 1587 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1588 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1589 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1590 for (i = 1; i <= sc->sc_noport; i++) 1591 printf("port %d status=0x%08x\n", i, 1592 EOREAD4(sc, EHCI_PORTSC(i))); 1593 } 1594 1595 Static void 1596 ehci_dump_regs(ehci_softc_t *sc) 1597 { 1598 int i; 1599 1600 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1601 1602 USBHIST_LOG(ehcidebug, 1603 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1604 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1605 EOREAD4(sc, EHCI_USBINTR), 0); 1606 USBHIST_LOG(ehcidebug, 1607 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1608 "async = 0x%08x", 1609 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1610 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1611 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1612 for (i = 1; i <= sc->sc_noport; i += 2) { 1613 if (i == sc->sc_noport) { 1614 USBHIST_LOG(ehcidebug, 1615 "port %d status = 0x%08x", i, 1616 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1617 } else { 1618 USBHIST_LOG(ehcidebug, 1619 "port %d status = 0x%08x port %d status = 0x%08x", 1620 i, EOREAD4(sc, EHCI_PORTSC(i)), 1621 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1622 } 1623 } 1624 } 1625 1626 #ifdef EHCI_DEBUG 1627 #define ehci_dump_link(link, type) do { \ 1628 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1629 link, \ 1630 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1631 if (type) { \ 1632 USBHIST_LOG(ehcidebug, \ 1633 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1634 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1635 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1636 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1637 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1638 } \ 1639 } while(0) 1640 #else 1641 #define ehci_dump_link(link, type) 1642 #endif 1643 1644 Static void 1645 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1646 { 1647 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1648 int i; 1649 uint32_t stop = 0; 1650 1651 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1652 ehci_dump_sqtd(sqtd); 1653 usb_syncmem(&sqtd->dma, 1654 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1655 sizeof(sqtd->qtd), 1656 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1657 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1658 usb_syncmem(&sqtd->dma, 1659 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1660 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1661 } 1662 if (!stop) 1663 USBHIST_LOG(ehcidebug, 1664 "dump aborted, too many TDs", 0, 0, 0, 0); 1665 } 1666 1667 Static void 1668 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1669 { 1670 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1671 1672 usb_syncmem(&sqtd->dma, sqtd->offs, 1673 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1674 1675 USBHIST_LOGN(ehcidebug, 10, 1676 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1677 ehci_dump_qtd(&sqtd->qtd); 1678 1679 usb_syncmem(&sqtd->dma, sqtd->offs, 1680 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1681 } 1682 1683 Static void 1684 ehci_dump_qtd(ehci_qtd_t *qtd) 1685 { 1686 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1687 1688 #ifdef USBHIST 1689 uint32_t s = le32toh(qtd->qtd_status); 1690 #endif 1691 1692 USBHIST_LOGN(ehcidebug, 10, 1693 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1694 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1695 USBHIST_LOGN(ehcidebug, 10, 1696 " toggle = %d ioc = %d bytes = %#x " 1697 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1698 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1699 USBHIST_LOGN(ehcidebug, 10, 1700 " cerr = %d pid = %d stat = %x", 1701 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1702 0); 1703 USBHIST_LOGN(ehcidebug, 10, 1704 "active =%d halted=%d buferr=%d babble=%d", 1705 s & EHCI_QTD_ACTIVE ? 1 : 0, 1706 s & EHCI_QTD_HALTED ? 1 : 0, 1707 s & EHCI_QTD_BUFERR ? 1 : 0, 1708 s & EHCI_QTD_BABBLE ? 1 : 0); 1709 USBHIST_LOGN(ehcidebug, 10, 1710 "xacterr=%d missed=%d split =%d ping =%d", 1711 s & EHCI_QTD_XACTERR ? 1 : 0, 1712 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1713 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1714 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1715 USBHIST_LOGN(ehcidebug, 10, 1716 "buffer[0] = %#x buffer[1] = %#x " 1717 "buffer[2] = %#x buffer[3] = %#x", 1718 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1719 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1720 USBHIST_LOGN(ehcidebug, 10, 1721 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1722 } 1723 1724 Static void 1725 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1726 { 1727 #ifdef USBHIST 1728 ehci_qh_t *qh = &sqh->qh; 1729 ehci_link_t link; 1730 #endif 1731 uint32_t endp, endphub; 1732 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1733 1734 usb_syncmem(&sqh->dma, sqh->offs, 1735 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1736 1737 USBHIST_LOGN(ehcidebug, 10, 1738 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1739 link = le32toh(qh->qh_link); 1740 ehci_dump_link(link, true); 1741 1742 endp = le32toh(qh->qh_endp); 1743 USBHIST_LOGN(ehcidebug, 10, 1744 " endp = %#x", endp, 0, 0, 0); 1745 USBHIST_LOGN(ehcidebug, 10, 1746 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1747 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1748 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1749 USBHIST_LOGN(ehcidebug, 10, 1750 " dtc = %d hrecl = %d", 1751 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1752 USBHIST_LOGN(ehcidebug, 10, 1753 " ctl = %d nrl = %d mpl = %#x(%d)", 1754 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1755 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1756 1757 endphub = le32toh(qh->qh_endphub); 1758 USBHIST_LOGN(ehcidebug, 10, 1759 " endphub = %#x", endphub, 0, 0, 0); 1760 USBHIST_LOGN(ehcidebug, 10, 1761 " smask = 0x%02x cmask = 0x%02x", 1762 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1763 USBHIST_LOGN(ehcidebug, 10, 1764 " huba = 0x%02x port = %d mult = %d", 1765 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1766 EHCI_QH_GET_MULT(endphub), 0); 1767 1768 link = le32toh(qh->qh_curqtd); 1769 ehci_dump_link(link, false); 1770 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1771 ehci_dump_qtd(&qh->qh_qtd); 1772 1773 usb_syncmem(&sqh->dma, sqh->offs, 1774 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1775 } 1776 1777 Static void 1778 ehci_dump_itd(struct ehci_soft_itd *itd) 1779 { 1780 ehci_isoc_trans_t t; 1781 ehci_isoc_bufr_ptr_t b, b2, b3; 1782 int i; 1783 1784 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1785 1786 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1787 0, 0); 1788 1789 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1790 t = le32toh(itd->itd.itd_ctl[i]); 1791 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1792 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1793 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1794 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1795 EHCI_ITD_GET_OFFS(t), 0); 1796 } 1797 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1798 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1799 USBHIST_LOG(ehcidebug, " %x", 1800 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1801 1802 b = le32toh(itd->itd.itd_bufr[0]); 1803 b2 = le32toh(itd->itd.itd_bufr[1]); 1804 b3 = le32toh(itd->itd.itd_bufr[2]); 1805 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1806 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1807 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1808 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1809 } 1810 1811 Static void 1812 ehci_dump_sitd(struct ehci_soft_itd *itd) 1813 { 1814 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1815 1816 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1817 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1818 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1819 itd->xfer_next, itd->physaddr, itd->slot, 0); 1820 } 1821 1822 Static void 1823 ehci_dump_exfer(struct ehci_xfer *ex) 1824 { 1825 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1826 1827 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1828 ex, ex->ex_sqtdstart, ex->ex_sqtdend, 0); 1829 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1830 ex->ex_itdstart, ex->ex_itdend, ex->ex_isdone, 0); 1831 } 1832 #endif 1833 1834 Static usbd_status 1835 ehci_open(usbd_pipe_handle pipe) 1836 { 1837 usbd_device_handle dev = pipe->up_dev; 1838 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1839 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1840 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1841 uint8_t addr = dev->ud_addr; 1842 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1843 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1844 ehci_soft_qh_t *sqh; 1845 usbd_status err; 1846 int ival, speed, naks; 1847 int hshubaddr, hshubport; 1848 1849 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1850 1851 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1852 pipe, addr, ed->bEndpointAddress, rhaddr); 1853 1854 if (dev->ud_myhsport) { 1855 /* 1856 * When directly attached FS/LS device while doing embedded 1857 * transaction translations and we are the hub, set the hub 1858 * address to 0 (us). 1859 */ 1860 if (!(sc->sc_flags & EHCIF_ETTF) 1861 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1862 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1863 } else { 1864 hshubaddr = 0; 1865 } 1866 hshubport = dev->ud_myhsport->up_portno; 1867 } else { 1868 hshubaddr = 0; 1869 hshubport = 0; 1870 } 1871 1872 if (sc->sc_dying) 1873 return USBD_IOERROR; 1874 1875 /* toggle state needed for bulk endpoints */ 1876 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1877 1878 if (addr == rhaddr) { 1879 switch (ed->bEndpointAddress) { 1880 case USB_CONTROL_ENDPOINT: 1881 pipe->up_methods = &roothub_ctrl_methods; 1882 break; 1883 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1884 pipe->up_methods = &ehci_root_intr_methods; 1885 break; 1886 default: 1887 USBHIST_LOG(ehcidebug, 1888 "bad bEndpointAddress 0x%02x", 1889 ed->bEndpointAddress, 0, 0, 0); 1890 return USBD_INVAL; 1891 } 1892 return USBD_NORMAL_COMPLETION; 1893 } 1894 1895 /* XXX All this stuff is only valid for async. */ 1896 switch (dev->ud_speed) { 1897 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1898 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1899 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1900 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1901 } 1902 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1903 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1904 hshubaddr, hshubport, 0, 0); 1905 return USBD_INVAL; 1906 } 1907 1908 /* 1909 * For interrupt transfer, nak throttling must be disabled, but for 1910 * the other transfer type, nak throttling should be enabled from the 1911 * viewpoint that avoids the memory thrashing. 1912 */ 1913 naks = (xfertype == UE_INTERRUPT) ? 0 1914 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1915 1916 /* Allocate sqh for everything, save isoc xfers */ 1917 if (xfertype != UE_ISOCHRONOUS) { 1918 sqh = ehci_alloc_sqh(sc); 1919 if (sqh == NULL) 1920 return USBD_NOMEM; 1921 /* qh_link filled when the QH is added */ 1922 sqh->qh.qh_endp = htole32( 1923 EHCI_QH_SET_ADDR(addr) | 1924 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1925 EHCI_QH_SET_EPS(speed) | 1926 EHCI_QH_DTC | 1927 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1928 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1929 EHCI_QH_CTL : 0) | 1930 EHCI_QH_SET_NRL(naks) 1931 ); 1932 sqh->qh.qh_endphub = htole32( 1933 EHCI_QH_SET_MULT(1) | 1934 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1935 ); 1936 if (speed != EHCI_QH_SPEED_HIGH) 1937 sqh->qh.qh_endphub |= htole32( 1938 EHCI_QH_SET_PORT(hshubport) | 1939 EHCI_QH_SET_HUBA(hshubaddr) | 1940 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1941 ); 1942 sqh->qh.qh_curqtd = EHCI_NULL; 1943 /* Fill the overlay qTD */ 1944 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1945 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1946 sqh->qh.qh_qtd.qtd_status = htole32(0); 1947 1948 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1949 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1950 epipe->sqh = sqh; 1951 } else { 1952 sqh = NULL; 1953 } /*xfertype == UE_ISOC*/ 1954 1955 switch (xfertype) { 1956 case UE_CONTROL: 1957 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1958 0, &epipe->u.ctl.reqdma); 1959 #ifdef EHCI_DEBUG 1960 if (err) 1961 printf("ehci_open: usb_allocmem()=%d\n", err); 1962 #endif 1963 if (err) 1964 goto bad; 1965 pipe->up_methods = &ehci_device_ctrl_methods; 1966 mutex_enter(&sc->sc_lock); 1967 ehci_add_qh(sc, sqh, sc->sc_async_head); 1968 mutex_exit(&sc->sc_lock); 1969 break; 1970 case UE_BULK: 1971 pipe->up_methods = &ehci_device_bulk_methods; 1972 mutex_enter(&sc->sc_lock); 1973 ehci_add_qh(sc, sqh, sc->sc_async_head); 1974 mutex_exit(&sc->sc_lock); 1975 break; 1976 case UE_INTERRUPT: 1977 pipe->up_methods = &ehci_device_intr_methods; 1978 ival = pipe->up_interval; 1979 if (ival == USBD_DEFAULT_INTERVAL) { 1980 if (speed == EHCI_QH_SPEED_HIGH) { 1981 if (ed->bInterval > 16) { 1982 /* 1983 * illegal with high-speed, but there 1984 * were documentation bugs in the spec, 1985 * so be generous 1986 */ 1987 ival = 256; 1988 } else 1989 ival = (1 << (ed->bInterval - 1)) / 8; 1990 } else 1991 ival = ed->bInterval; 1992 } 1993 err = ehci_device_setintr(sc, sqh, ival); 1994 if (err) 1995 goto bad; 1996 break; 1997 case UE_ISOCHRONOUS: 1998 if (speed == EHCI_QH_SPEED_HIGH) 1999 pipe->up_methods = &ehci_device_isoc_methods; 2000 else 2001 pipe->up_methods = &ehci_device_fs_isoc_methods; 2002 if (ed->bInterval == 0 || ed->bInterval > 16) { 2003 printf("ehci: opening pipe with invalid bInterval\n"); 2004 err = USBD_INVAL; 2005 goto bad; 2006 } 2007 if (UGETW(ed->wMaxPacketSize) == 0) { 2008 printf("ehci: zero length endpoint open request\n"); 2009 err = USBD_INVAL; 2010 goto bad; 2011 } 2012 epipe->u.isoc.next_frame = 0; 2013 epipe->u.isoc.cur_xfers = 0; 2014 break; 2015 default: 2016 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2017 err = USBD_INVAL; 2018 goto bad; 2019 } 2020 return USBD_NORMAL_COMPLETION; 2021 2022 bad: 2023 if (sqh != NULL) 2024 ehci_free_sqh(sc, sqh); 2025 return err; 2026 } 2027 2028 /* 2029 * Add an ED to the schedule. Called with USB lock held. 2030 */ 2031 Static void 2032 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2033 { 2034 2035 KASSERT(mutex_owned(&sc->sc_lock)); 2036 2037 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2038 2039 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2040 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2041 2042 sqh->next = head->next; 2043 sqh->qh.qh_link = head->qh.qh_link; 2044 2045 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2046 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2047 2048 head->next = sqh; 2049 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2050 2051 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2052 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2053 2054 #ifdef EHCI_DEBUG 2055 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2056 ehci_dump_sqh(sqh); 2057 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2058 #endif 2059 } 2060 2061 /* 2062 * Remove an ED from the schedule. Called with USB lock held. 2063 */ 2064 Static void 2065 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2066 { 2067 ehci_soft_qh_t *p; 2068 2069 KASSERT(mutex_owned(&sc->sc_lock)); 2070 2071 /* XXX */ 2072 for (p = head; p != NULL && p->next != sqh; p = p->next) 2073 ; 2074 if (p == NULL) 2075 panic("ehci_rem_qh: ED not found"); 2076 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2077 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2078 p->next = sqh->next; 2079 p->qh.qh_link = sqh->qh.qh_link; 2080 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2081 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2082 2083 ehci_sync_hc(sc); 2084 } 2085 2086 Static void 2087 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2088 { 2089 int i; 2090 uint32_t status; 2091 2092 /* Save toggle bit and ping status. */ 2093 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2094 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2095 status = sqh->qh.qh_qtd.qtd_status & 2096 htole32(EHCI_QTD_TOGGLE_MASK | 2097 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2098 /* Set HALTED to make hw leave it alone. */ 2099 sqh->qh.qh_qtd.qtd_status = 2100 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2101 usb_syncmem(&sqh->dma, 2102 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2103 sizeof(sqh->qh.qh_qtd.qtd_status), 2104 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2105 sqh->qh.qh_curqtd = 0; 2106 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2107 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2108 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2109 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2110 sqh->sqtd = sqtd; 2111 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2112 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2113 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2114 sqh->qh.qh_qtd.qtd_status = status; 2115 usb_syncmem(&sqh->dma, 2116 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2117 sizeof(sqh->qh.qh_qtd.qtd_status), 2118 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2119 } 2120 2121 /* 2122 * Ensure that the HC has released all references to the QH. We do this 2123 * by asking for a Async Advance Doorbell interrupt and then we wait for 2124 * the interrupt. 2125 * To make this easier we first obtain exclusive use of the doorbell. 2126 */ 2127 Static void 2128 ehci_sync_hc(ehci_softc_t *sc) 2129 { 2130 int error __diagused; 2131 2132 KASSERT(mutex_owned(&sc->sc_lock)); 2133 2134 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2135 2136 if (sc->sc_dying) { 2137 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2138 return; 2139 } 2140 /* ask for doorbell */ 2141 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2142 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2143 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2144 2145 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2146 2147 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2148 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2149 #ifdef DIAGNOSTIC 2150 if (error) 2151 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2152 #endif 2153 } 2154 2155 Static void 2156 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2157 { 2158 struct ehci_soft_itd *itd, *prev; 2159 2160 prev = NULL; 2161 2162 if (exfer->ex_itdstart == NULL || exfer->ex_itdend == NULL) 2163 panic("ehci isoc xfer being freed, but with no itd chain\n"); 2164 2165 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2166 prev = itd->u.frame_list.prev; 2167 /* Unlink itd from hardware chain, or frame array */ 2168 if (prev == NULL) { /* We're at the table head */ 2169 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2170 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2171 usb_syncmem(&sc->sc_fldma, 2172 sizeof(ehci_link_t) * itd->slot, 2173 sizeof(ehci_link_t), 2174 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2175 2176 if (itd->u.frame_list.next != NULL) 2177 itd->u.frame_list.next->u.frame_list.prev = NULL; 2178 } else { 2179 /* XXX this part is untested... */ 2180 prev->itd.itd_next = itd->itd.itd_next; 2181 usb_syncmem(&itd->dma, 2182 itd->offs + offsetof(ehci_itd_t, itd_next), 2183 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2184 2185 prev->u.frame_list.next = itd->u.frame_list.next; 2186 if (itd->u.frame_list.next != NULL) 2187 itd->u.frame_list.next->u.frame_list.prev = prev; 2188 } 2189 } 2190 2191 prev = NULL; 2192 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2193 if (prev != NULL) 2194 ehci_free_itd(sc, prev); 2195 prev = itd; 2196 } 2197 if (prev) 2198 ehci_free_itd(sc, prev); 2199 exfer->ex_itdstart = NULL; 2200 exfer->ex_itdend = NULL; 2201 } 2202 2203 Static void 2204 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2205 { 2206 struct ehci_soft_sitd *sitd, *prev; 2207 2208 prev = NULL; 2209 2210 if (exfer->ex_sitdstart == NULL || exfer->ex_sitdend == NULL) 2211 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2212 2213 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2214 prev = sitd->u.frame_list.prev; 2215 /* Unlink sitd from hardware chain, or frame array */ 2216 if (prev == NULL) { /* We're at the table head */ 2217 sc->sc_softsitds[sitd->slot] = sitd->u.frame_list.next; 2218 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2219 usb_syncmem(&sc->sc_fldma, 2220 sizeof(ehci_link_t) * sitd->slot, 2221 sizeof(ehci_link_t), 2222 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2223 2224 if (sitd->u.frame_list.next != NULL) 2225 sitd->u.frame_list.next->u.frame_list.prev = NULL; 2226 } else { 2227 /* XXX this part is untested... */ 2228 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2229 usb_syncmem(&sitd->dma, 2230 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2231 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2232 2233 prev->u.frame_list.next = sitd->u.frame_list.next; 2234 if (sitd->u.frame_list.next != NULL) 2235 sitd->u.frame_list.next->u.frame_list.prev = prev; 2236 } 2237 } 2238 2239 prev = NULL; 2240 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2241 if (prev != NULL) 2242 ehci_free_sitd(sc, prev); 2243 prev = sitd; 2244 } 2245 if (prev) 2246 ehci_free_sitd(sc, prev); 2247 exfer->ex_sitdstart = NULL; 2248 exfer->ex_sitdend = NULL; 2249 } 2250 2251 /***********/ 2252 2253 Static int 2254 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2255 void *buf, int buflen) 2256 { 2257 ehci_softc_t *sc = bus->ub_hcpriv; 2258 usb_hub_descriptor_t hubd; 2259 usb_port_status_t ps; 2260 uint16_t len, value, index; 2261 int l, totlen = 0; 2262 int port, i; 2263 uint32_t v; 2264 2265 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2266 2267 if (sc->sc_dying) 2268 return -1; 2269 2270 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2271 req->bmRequestType, req->bRequest, 0, 0); 2272 2273 len = UGETW(req->wLength); 2274 value = UGETW(req->wValue); 2275 index = UGETW(req->wIndex); 2276 2277 #define C(x,y) ((x) | ((y) << 8)) 2278 switch (C(req->bRequest, req->bmRequestType)) { 2279 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2280 if (len == 0) 2281 break; 2282 switch (value) { 2283 case C(0, UDESC_DEVICE): { 2284 usb_device_descriptor_t devd; 2285 totlen = min(buflen, sizeof(devd)); 2286 memcpy(&devd, buf, totlen); 2287 USETW(devd.idVendor, sc->sc_id_vendor); 2288 memcpy(buf, &devd, totlen); 2289 break; 2290 2291 } 2292 #define sd ((usb_string_descriptor_t *)buf) 2293 case C(1, UDESC_STRING): 2294 /* Vendor */ 2295 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2296 break; 2297 case C(2, UDESC_STRING): 2298 /* Product */ 2299 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2300 break; 2301 #undef sd 2302 default: 2303 /* default from usbroothub */ 2304 return buflen; 2305 } 2306 break; 2307 2308 /* Hub requests */ 2309 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2310 break; 2311 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2312 USBHIST_LOG(ehcidebug, 2313 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2314 0, 0); 2315 if (index < 1 || index > sc->sc_noport) { 2316 return -1; 2317 } 2318 port = EHCI_PORTSC(index); 2319 v = EOREAD4(sc, port); 2320 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2321 v &= ~EHCI_PS_CLEAR; 2322 switch (value) { 2323 case UHF_PORT_ENABLE: 2324 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2325 break; 2326 case UHF_PORT_SUSPEND: 2327 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2328 break; 2329 v &= ~EHCI_PS_SUSP; 2330 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2331 /* see USB2 spec ch. 7.1.7.7 */ 2332 usb_delay_ms(&sc->sc_bus, 20); 2333 EOWRITE4(sc, port, v); 2334 usb_delay_ms(&sc->sc_bus, 2); 2335 #ifdef DEBUG 2336 v = EOREAD4(sc, port); 2337 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2338 printf("ehci: resume failed: %x\n", v); 2339 #endif 2340 break; 2341 case UHF_PORT_POWER: 2342 if (sc->sc_hasppc) 2343 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2344 break; 2345 case UHF_PORT_TEST: 2346 USBHIST_LOG(ehcidebug, "clear port test " 2347 "%d", index, 0, 0, 0); 2348 break; 2349 case UHF_PORT_INDICATOR: 2350 USBHIST_LOG(ehcidebug, "clear port ind " 2351 "%d", index, 0, 0, 0); 2352 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2353 break; 2354 case UHF_C_PORT_CONNECTION: 2355 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2356 break; 2357 case UHF_C_PORT_ENABLE: 2358 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2359 break; 2360 case UHF_C_PORT_SUSPEND: 2361 /* how? */ 2362 break; 2363 case UHF_C_PORT_OVER_CURRENT: 2364 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2365 break; 2366 case UHF_C_PORT_RESET: 2367 sc->sc_isreset[index] = 0; 2368 break; 2369 default: 2370 return -1; 2371 } 2372 #if 0 2373 switch(value) { 2374 case UHF_C_PORT_CONNECTION: 2375 case UHF_C_PORT_ENABLE: 2376 case UHF_C_PORT_SUSPEND: 2377 case UHF_C_PORT_OVER_CURRENT: 2378 case UHF_C_PORT_RESET: 2379 default: 2380 break; 2381 } 2382 #endif 2383 break; 2384 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2385 if (len == 0) 2386 break; 2387 if ((value & 0xff) != 0) { 2388 return -1; 2389 } 2390 totlen = min(buflen, sizeof(hubd)); 2391 memcpy(&hubd, buf, totlen); 2392 hubd.bNbrPorts = sc->sc_noport; 2393 v = EOREAD4(sc, EHCI_HCSPARAMS); 2394 USETW(hubd.wHubCharacteristics, 2395 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2396 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2397 ? UHD_PORT_IND : 0); 2398 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2399 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2400 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2401 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2402 totlen = min(totlen, hubd.bDescLength); 2403 memcpy(buf, &hubd, totlen); 2404 break; 2405 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2406 if (len != 4) { 2407 return -1; 2408 } 2409 memset(buf, 0, len); /* ? XXX */ 2410 totlen = len; 2411 break; 2412 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2413 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2414 if (index < 1 || index > sc->sc_noport) { 2415 return -1; 2416 } 2417 if (len != 4) { 2418 return -1; 2419 } 2420 v = EOREAD4(sc, EHCI_PORTSC(index)); 2421 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2422 2423 i = UPS_HIGH_SPEED; 2424 if (sc->sc_flags & EHCIF_ETTF) { 2425 /* 2426 * If we are doing embedded transaction translation, 2427 * then directly attached LS/FS devices are reset by 2428 * the EHCI controller itself. PSPD is encoded 2429 * the same way as in USBSTATUS. 2430 */ 2431 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2432 } 2433 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2434 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2435 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2436 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2437 if (v & EHCI_PS_PR) i |= UPS_RESET; 2438 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2439 if (sc->sc_vendor_port_status) 2440 i = sc->sc_vendor_port_status(sc, v, i); 2441 USETW(ps.wPortStatus, i); 2442 i = 0; 2443 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2444 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2445 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2446 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2447 USETW(ps.wPortChange, i); 2448 totlen = min(len, sizeof(ps)); 2449 memcpy(buf, &ps, totlen); 2450 break; 2451 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2452 return -1; 2453 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2454 break; 2455 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2456 if (index < 1 || index > sc->sc_noport) { 2457 return -1; 2458 } 2459 port = EHCI_PORTSC(index); 2460 v = EOREAD4(sc, port); 2461 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2462 v &= ~EHCI_PS_CLEAR; 2463 switch(value) { 2464 case UHF_PORT_ENABLE: 2465 EOWRITE4(sc, port, v | EHCI_PS_PE); 2466 break; 2467 case UHF_PORT_SUSPEND: 2468 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2469 break; 2470 case UHF_PORT_RESET: 2471 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2472 if (EHCI_PS_IS_LOWSPEED(v) 2473 && sc->sc_ncomp > 0 2474 && !(sc->sc_flags & EHCIF_ETTF)) { 2475 /* 2476 * Low speed device on non-ETTF controller or 2477 * unaccompanied controller, give up ownership. 2478 */ 2479 ehci_disown(sc, index, 1); 2480 break; 2481 } 2482 /* Start reset sequence. */ 2483 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2484 EOWRITE4(sc, port, v | EHCI_PS_PR); 2485 /* Wait for reset to complete. */ 2486 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2487 if (sc->sc_dying) { 2488 return -1; 2489 } 2490 /* 2491 * An embedded transaction translator will automatically 2492 * terminate the reset sequence so there's no need to 2493 * it. 2494 */ 2495 v = EOREAD4(sc, port); 2496 if (v & EHCI_PS_PR) { 2497 /* Terminate reset sequence. */ 2498 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2499 /* Wait for HC to complete reset. */ 2500 usb_delay_ms(&sc->sc_bus, 2501 EHCI_PORT_RESET_COMPLETE); 2502 if (sc->sc_dying) { 2503 return -1; 2504 } 2505 } 2506 2507 v = EOREAD4(sc, port); 2508 USBHIST_LOG(ehcidebug, 2509 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2510 if (v & EHCI_PS_PR) { 2511 printf("%s: port reset timeout\n", 2512 device_xname(sc->sc_dev)); 2513 return USBD_TIMEOUT; 2514 } 2515 if (!(v & EHCI_PS_PE)) { 2516 /* Not a high speed device, give up ownership.*/ 2517 ehci_disown(sc, index, 0); 2518 break; 2519 } 2520 sc->sc_isreset[index] = 1; 2521 USBHIST_LOG(ehcidebug, 2522 "ehci port %d reset, status = 0x%08x", index, v, 0, 2523 0); 2524 break; 2525 case UHF_PORT_POWER: 2526 USBHIST_LOG(ehcidebug, 2527 "set port power %d (has PPC = %d)", index, 2528 sc->sc_hasppc, 0, 0); 2529 if (sc->sc_hasppc) 2530 EOWRITE4(sc, port, v | EHCI_PS_PP); 2531 break; 2532 case UHF_PORT_TEST: 2533 USBHIST_LOG(ehcidebug, "set port test %d", 2534 index, 0, 0, 0); 2535 break; 2536 case UHF_PORT_INDICATOR: 2537 USBHIST_LOG(ehcidebug, "set port ind %d", 2538 index, 0, 0, 0); 2539 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2540 break; 2541 default: 2542 return -1; 2543 } 2544 break; 2545 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2546 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2547 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2548 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2549 break; 2550 default: 2551 /* default from usbroothub */ 2552 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2553 buflen, 0, 0, 0); 2554 2555 return buflen; 2556 } 2557 2558 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2559 2560 return totlen; 2561 } 2562 2563 Static void 2564 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2565 { 2566 int port; 2567 uint32_t v; 2568 2569 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2570 2571 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2572 #ifdef DIAGNOSTIC 2573 if (sc->sc_npcomp != 0) { 2574 int i = (index-1) / sc->sc_npcomp; 2575 if (i >= sc->sc_ncomp) 2576 printf("%s: strange port\n", 2577 device_xname(sc->sc_dev)); 2578 else 2579 printf("%s: handing over %s speed device on " 2580 "port %d to %s\n", 2581 device_xname(sc->sc_dev), 2582 lowspeed ? "low" : "full", 2583 index, device_xname(sc->sc_comps[i])); 2584 } else { 2585 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2586 } 2587 #endif 2588 port = EHCI_PORTSC(index); 2589 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2590 EOWRITE4(sc, port, v | EHCI_PS_PO); 2591 } 2592 2593 Static usbd_status 2594 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2595 { 2596 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2597 usbd_status err; 2598 2599 /* Insert last in queue. */ 2600 mutex_enter(&sc->sc_lock); 2601 err = usb_insert_transfer(xfer); 2602 mutex_exit(&sc->sc_lock); 2603 if (err) 2604 return err; 2605 2606 /* Pipe isn't running, start first */ 2607 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2608 } 2609 2610 Static usbd_status 2611 ehci_root_intr_start(usbd_xfer_handle xfer) 2612 { 2613 usbd_pipe_handle pipe = xfer->ux_pipe; 2614 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2615 2616 if (sc->sc_dying) 2617 return USBD_IOERROR; 2618 2619 mutex_enter(&sc->sc_lock); 2620 sc->sc_intrxfer = xfer; 2621 mutex_exit(&sc->sc_lock); 2622 2623 return USBD_IN_PROGRESS; 2624 } 2625 2626 /* Abort a root interrupt request. */ 2627 Static void 2628 ehci_root_intr_abort(usbd_xfer_handle xfer) 2629 { 2630 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2631 2632 KASSERT(mutex_owned(&sc->sc_lock)); 2633 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2634 2635 sc->sc_intrxfer = NULL; 2636 2637 xfer->ux_status = USBD_CANCELLED; 2638 usb_transfer_complete(xfer); 2639 } 2640 2641 /* Close the root pipe. */ 2642 Static void 2643 ehci_root_intr_close(usbd_pipe_handle pipe) 2644 { 2645 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2646 2647 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2648 2649 KASSERT(mutex_owned(&sc->sc_lock)); 2650 2651 sc->sc_intrxfer = NULL; 2652 } 2653 2654 Static void 2655 ehci_root_intr_done(usbd_xfer_handle xfer) 2656 { 2657 xfer->ux_hcpriv = NULL; 2658 } 2659 2660 /************************/ 2661 2662 Static ehci_soft_qh_t * 2663 ehci_alloc_sqh(ehci_softc_t *sc) 2664 { 2665 ehci_soft_qh_t *sqh; 2666 usbd_status err; 2667 int i, offs; 2668 usb_dma_t dma; 2669 2670 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2671 2672 if (sc->sc_freeqhs == NULL) { 2673 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2674 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2675 EHCI_PAGE_SIZE, &dma); 2676 #ifdef EHCI_DEBUG 2677 if (err) 2678 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2679 #endif 2680 if (err) 2681 return NULL; 2682 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2683 offs = i * EHCI_SQH_SIZE; 2684 sqh = KERNADDR(&dma, offs); 2685 sqh->physaddr = DMAADDR(&dma, offs); 2686 sqh->dma = dma; 2687 sqh->offs = offs; 2688 sqh->next = sc->sc_freeqhs; 2689 sc->sc_freeqhs = sqh; 2690 } 2691 } 2692 sqh = sc->sc_freeqhs; 2693 sc->sc_freeqhs = sqh->next; 2694 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2695 sqh->next = NULL; 2696 return sqh; 2697 } 2698 2699 Static void 2700 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2701 { 2702 sqh->next = sc->sc_freeqhs; 2703 sc->sc_freeqhs = sqh; 2704 } 2705 2706 Static ehci_soft_qtd_t * 2707 ehci_alloc_sqtd(ehci_softc_t *sc) 2708 { 2709 ehci_soft_qtd_t *sqtd = NULL; 2710 usbd_status err; 2711 int i, offs; 2712 usb_dma_t dma; 2713 2714 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2715 2716 if (sc->sc_freeqtds == NULL) { 2717 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2718 2719 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2720 EHCI_PAGE_SIZE, &dma); 2721 #ifdef EHCI_DEBUG 2722 if (err) 2723 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2724 #endif 2725 if (err) 2726 goto done; 2727 2728 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2729 offs = i * EHCI_SQTD_SIZE; 2730 sqtd = KERNADDR(&dma, offs); 2731 sqtd->physaddr = DMAADDR(&dma, offs); 2732 sqtd->dma = dma; 2733 sqtd->offs = offs; 2734 2735 sqtd->nextqtd = sc->sc_freeqtds; 2736 sc->sc_freeqtds = sqtd; 2737 } 2738 } 2739 2740 sqtd = sc->sc_freeqtds; 2741 sc->sc_freeqtds = sqtd->nextqtd; 2742 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2743 sqtd->nextqtd = NULL; 2744 sqtd->xfer = NULL; 2745 2746 done: 2747 return sqtd; 2748 } 2749 2750 Static void 2751 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2752 { 2753 2754 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2755 2756 sqtd->nextqtd = sc->sc_freeqtds; 2757 sc->sc_freeqtds = sqtd; 2758 } 2759 2760 Static usbd_status 2761 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2762 int alen, int rd, usbd_xfer_handle xfer, 2763 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2764 { 2765 ehci_soft_qtd_t *next, *cur; 2766 ehci_physaddr_t nextphys; 2767 uint32_t qtdstatus; 2768 int len, curlen, mps; 2769 int i, tog; 2770 int pages, pageoffs; 2771 size_t curoffs; 2772 vaddr_t va, va_offs; 2773 usb_dma_t *dma = &xfer->ux_dmabuf; 2774 uint16_t flags = xfer->ux_flags; 2775 paddr_t a; 2776 2777 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2778 2779 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2780 2781 len = alen; 2782 qtdstatus = EHCI_QTD_ACTIVE | 2783 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2784 EHCI_QTD_SET_CERR(3) 2785 /* IOC set below */ 2786 /* BYTES set below */ 2787 ; 2788 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 2789 tog = epipe->nexttoggle; 2790 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2791 2792 cur = ehci_alloc_sqtd(sc); 2793 *sp = cur; 2794 if (cur == NULL) 2795 goto nomem; 2796 2797 usb_syncmem(dma, 0, alen, 2798 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2799 curoffs = 0; 2800 for (;;) { 2801 /* The EHCI hardware can handle at most 5 pages. */ 2802 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2803 va_offs = EHCI_PAGE_OFFSET(va_offs); 2804 if (len-curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2805 /* we can handle it in this QTD */ 2806 curlen = len - curoffs; 2807 } else { 2808 /* must use multiple TDs, fill as much as possible. */ 2809 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2810 2811 /* the length must be a multiple of the max size */ 2812 curlen -= curlen % mps; 2813 USBHIST_LOG(ehcidebug, "multiple QTDs, " 2814 "curlen=%d", curlen, 0, 0, 0); 2815 KASSERT(curlen != 0); 2816 } 2817 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 2818 len, curlen, curoffs, 0); 2819 2820 /* 2821 * Allocate another transfer if there's more data left, 2822 * or if force last short transfer flag is set and we're 2823 * allocating a multiple of the max packet size. 2824 */ 2825 2826 if (curoffs + curlen != len || 2827 ((curlen % mps) == 0 && !rd && curlen != 0 && 2828 (flags & USBD_FORCE_SHORT_XFER))) { 2829 next = ehci_alloc_sqtd(sc); 2830 if (next == NULL) 2831 goto nomem; 2832 nextphys = htole32(next->physaddr); 2833 } else { 2834 next = NULL; 2835 nextphys = EHCI_NULL; 2836 } 2837 2838 /* Find number of pages we'll be using, insert dma addresses */ 2839 pages = EHCI_NPAGES(curlen); 2840 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2841 pageoffs = EHCI_PAGE(curoffs); 2842 for (i = 0; i < pages; i++) { 2843 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2844 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2845 /* Cast up to avoid compiler warnings */ 2846 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2847 } 2848 2849 /* First buffer pointer requires a page offset to start at */ 2850 va = (vaddr_t)KERNADDR(dma, curoffs); 2851 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2852 2853 cur->nextqtd = next; 2854 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2855 cur->qtd.qtd_status = 2856 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2857 cur->xfer = xfer; 2858 cur->len = curlen; 2859 2860 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2861 curoffs, curoffs + curlen, 0, 0); 2862 2863 /* 2864 * adjust the toggle based on the number of packets in this 2865 * qtd 2866 */ 2867 if (((curlen + mps - 1) / mps) & 1) { 2868 tog ^= 1; 2869 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2870 } 2871 if (next == NULL) 2872 break; 2873 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2874 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2875 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2876 if (len) 2877 curoffs += curlen; 2878 cur = next; 2879 } 2880 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2881 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2882 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2883 *ep = cur; 2884 epipe->nexttoggle = tog; 2885 2886 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 2887 *sp, *ep, 0, 0); 2888 2889 return USBD_NORMAL_COMPLETION; 2890 2891 nomem: 2892 /* XXX free chain */ 2893 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2894 return USBD_NOMEM; 2895 } 2896 2897 Static void 2898 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2899 ehci_soft_qtd_t *sqtdend) 2900 { 2901 ehci_soft_qtd_t *p; 2902 int i; 2903 2904 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2905 2906 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 2907 sqtd, sqtdend, 0, 0); 2908 2909 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2910 p = sqtd->nextqtd; 2911 ehci_free_sqtd(sc, sqtd); 2912 } 2913 } 2914 2915 Static ehci_soft_itd_t * 2916 ehci_alloc_itd(ehci_softc_t *sc) 2917 { 2918 struct ehci_soft_itd *itd, *freeitd; 2919 usbd_status err; 2920 int i, offs, frindex, previndex; 2921 usb_dma_t dma; 2922 2923 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2924 2925 mutex_enter(&sc->sc_lock); 2926 2927 /* 2928 * Find an itd that wasn't freed this frame or last frame. This can 2929 * discard itds that were freed before frindex wrapped around 2930 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2931 * interrupt and fiddling with list when that happens 2932 */ 2933 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2934 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2935 2936 freeitd = NULL; 2937 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2938 if (itd == NULL) 2939 break; 2940 if (itd->slot != frindex && itd->slot != previndex) { 2941 freeitd = itd; 2942 break; 2943 } 2944 } 2945 2946 if (freeitd == NULL) { 2947 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2948 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2949 EHCI_PAGE_SIZE, &dma); 2950 2951 if (err) { 2952 USBHIST_LOG(ehcidebug, 2953 "alloc returned %d", err, 0, 0, 0); 2954 mutex_exit(&sc->sc_lock); 2955 return NULL; 2956 } 2957 2958 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2959 offs = i * EHCI_ITD_SIZE; 2960 itd = KERNADDR(&dma, offs); 2961 itd->physaddr = DMAADDR(&dma, offs); 2962 itd->dma = dma; 2963 itd->offs = offs; 2964 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2965 } 2966 freeitd = LIST_FIRST(&sc->sc_freeitds); 2967 } 2968 2969 itd = freeitd; 2970 LIST_REMOVE(itd, u.free_list); 2971 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2972 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2973 sizeof(itd->itd.itd_next), 2974 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2975 2976 itd->u.frame_list.next = NULL; 2977 itd->u.frame_list.prev = NULL; 2978 itd->xfer_next = NULL; 2979 itd->slot = 0; 2980 2981 mutex_exit(&sc->sc_lock); 2982 2983 return itd; 2984 } 2985 2986 Static ehci_soft_sitd_t * 2987 ehci_alloc_sitd(ehci_softc_t *sc) 2988 { 2989 struct ehci_soft_sitd *sitd, *freesitd; 2990 usbd_status err; 2991 int i, offs, frindex, previndex; 2992 usb_dma_t dma; 2993 2994 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2995 2996 mutex_enter(&sc->sc_lock); 2997 2998 /* 2999 * Find an sitd that wasn't freed this frame or last frame. This can 3000 * discard sitds that were freed before frindex wrapped around 3001 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3002 * interrupt and fiddling with list when that happens 3003 */ 3004 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3005 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3006 3007 freesitd = NULL; 3008 LIST_FOREACH(sitd, &sc->sc_freesitds, u.free_list) { 3009 if (sitd == NULL) 3010 break; 3011 if (sitd->slot != frindex && sitd->slot != previndex) { 3012 freesitd = sitd; 3013 break; 3014 } 3015 } 3016 3017 if (freesitd == NULL) { 3018 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3019 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3020 EHCI_PAGE_SIZE, &dma); 3021 3022 if (err) { 3023 USBHIST_LOG(ehcidebug, 3024 "alloc returned %d", err, 0, 0, 0); 3025 mutex_exit(&sc->sc_lock); 3026 return NULL; 3027 } 3028 3029 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3030 offs = i * EHCI_SITD_SIZE; 3031 sitd = KERNADDR(&dma, offs); 3032 sitd->physaddr = DMAADDR(&dma, offs); 3033 sitd->dma = dma; 3034 sitd->offs = offs; 3035 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3036 } 3037 freesitd = LIST_FIRST(&sc->sc_freesitds); 3038 } 3039 3040 sitd = freesitd; 3041 LIST_REMOVE(sitd, u.free_list); 3042 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3043 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3044 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3045 BUS_DMASYNC_PREREAD); 3046 3047 sitd->u.frame_list.next = NULL; 3048 sitd->u.frame_list.prev = NULL; 3049 sitd->xfer_next = NULL; 3050 sitd->slot = 0; 3051 3052 mutex_exit(&sc->sc_lock); 3053 3054 return sitd; 3055 } 3056 3057 Static void 3058 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3059 { 3060 3061 KASSERT(mutex_owned(&sc->sc_lock)); 3062 3063 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3064 } 3065 3066 Static void 3067 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3068 { 3069 3070 KASSERT(mutex_owned(&sc->sc_lock)); 3071 3072 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3073 } 3074 3075 /****************/ 3076 3077 /* 3078 * Close a reqular pipe. 3079 * Assumes that there are no pending transactions. 3080 */ 3081 Static void 3082 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3083 { 3084 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3085 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3086 ehci_soft_qh_t *sqh = epipe->sqh; 3087 3088 KASSERT(mutex_owned(&sc->sc_lock)); 3089 3090 ehci_rem_qh(sc, sqh, head); 3091 ehci_free_sqh(sc, epipe->sqh); 3092 } 3093 3094 /* 3095 * Abort a device request. 3096 * If this routine is called at splusb() it guarantees that the request 3097 * will be removed from the hardware scheduling and that the callback 3098 * for it will be called with USBD_CANCELLED status. 3099 * It's impossible to guarantee that the requested transfer will not 3100 * have happened since the hardware runs concurrently. 3101 * If the transaction has already happened we rely on the ordinary 3102 * interrupt processing to process it. 3103 * XXX This is most probably wrong. 3104 * XXXMRG this doesn't make sense anymore. 3105 */ 3106 Static void 3107 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3108 { 3109 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3110 struct ehci_xfer *exfer = EXFER(xfer); 3111 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3112 ehci_soft_qh_t *sqh = epipe->sqh; 3113 ehci_soft_qtd_t *sqtd; 3114 ehci_physaddr_t cur; 3115 uint32_t qhstatus; 3116 int hit; 3117 int wake; 3118 3119 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3120 3121 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3122 3123 KASSERT(mutex_owned(&sc->sc_lock)); 3124 ASSERT_SLEEPABLE(); 3125 3126 if (sc->sc_dying) { 3127 /* If we're dying, just do the software part. */ 3128 xfer->ux_status = status; /* make software ignore it */ 3129 callout_stop(&xfer->ux_callout); 3130 usb_transfer_complete(xfer); 3131 return; 3132 } 3133 3134 /* 3135 * If an abort is already in progress then just wait for it to 3136 * complete and return. 3137 */ 3138 if (xfer->ux_hcflags & UXFER_ABORTING) { 3139 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3140 #ifdef DIAGNOSTIC 3141 if (status == USBD_TIMEOUT) 3142 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3143 #endif 3144 /* Override the status which might be USBD_TIMEOUT. */ 3145 xfer->ux_status = status; 3146 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3147 0, 0, 0, 0); 3148 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3149 while (xfer->ux_hcflags & UXFER_ABORTING) 3150 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3151 return; 3152 } 3153 xfer->ux_hcflags |= UXFER_ABORTING; 3154 3155 /* 3156 * Step 1: Make interrupt routine and hardware ignore xfer. 3157 */ 3158 xfer->ux_status = status; /* make software ignore it */ 3159 callout_stop(&xfer->ux_callout); 3160 3161 usb_syncmem(&sqh->dma, 3162 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3163 sizeof(sqh->qh.qh_qtd.qtd_status), 3164 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3165 qhstatus = sqh->qh.qh_qtd.qtd_status; 3166 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3167 usb_syncmem(&sqh->dma, 3168 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3169 sizeof(sqh->qh.qh_qtd.qtd_status), 3170 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3171 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3172 usb_syncmem(&sqtd->dma, 3173 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3174 sizeof(sqtd->qtd.qtd_status), 3175 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3176 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3177 usb_syncmem(&sqtd->dma, 3178 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3179 sizeof(sqtd->qtd.qtd_status), 3180 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3181 if (sqtd == exfer->ex_sqtdend) 3182 break; 3183 } 3184 3185 /* 3186 * Step 2: Wait until we know hardware has finished any possible 3187 * use of the xfer. Also make sure the soft interrupt routine 3188 * has run. 3189 */ 3190 ehci_sync_hc(sc); 3191 sc->sc_softwake = 1; 3192 usb_schedsoftintr(&sc->sc_bus); 3193 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3194 3195 /* 3196 * Step 3: Remove any vestiges of the xfer from the hardware. 3197 * The complication here is that the hardware may have executed 3198 * beyond the xfer we're trying to abort. So as we're scanning 3199 * the TDs of this xfer we check if the hardware points to 3200 * any of them. 3201 */ 3202 3203 usb_syncmem(&sqh->dma, 3204 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3205 sizeof(sqh->qh.qh_curqtd), 3206 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3207 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3208 hit = 0; 3209 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3210 hit |= cur == sqtd->physaddr; 3211 if (sqtd == exfer->ex_sqtdend) 3212 break; 3213 } 3214 sqtd = sqtd->nextqtd; 3215 /* Zap curqtd register if hardware pointed inside the xfer. */ 3216 if (hit && sqtd != NULL) { 3217 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3218 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3219 usb_syncmem(&sqh->dma, 3220 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3221 sizeof(sqh->qh.qh_curqtd), 3222 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3223 sqh->qh.qh_qtd.qtd_status = qhstatus; 3224 usb_syncmem(&sqh->dma, 3225 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3226 sizeof(sqh->qh.qh_qtd.qtd_status), 3227 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3228 } else { 3229 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3230 } 3231 3232 /* 3233 * Step 4: Execute callback. 3234 */ 3235 #ifdef DIAGNOSTIC 3236 exfer->ex_isdone = true; 3237 #endif 3238 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3239 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3240 usb_transfer_complete(xfer); 3241 if (wake) { 3242 cv_broadcast(&xfer->ux_hccv); 3243 } 3244 3245 KASSERT(mutex_owned(&sc->sc_lock)); 3246 } 3247 3248 Static void 3249 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3250 { 3251 ehci_isoc_trans_t trans_status; 3252 struct ehci_pipe *epipe; 3253 struct ehci_xfer *exfer; 3254 ehci_softc_t *sc; 3255 struct ehci_soft_itd *itd; 3256 struct ehci_soft_sitd *sitd; 3257 int i, wake; 3258 3259 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3260 3261 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3262 exfer = EXFER(xfer); 3263 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3264 3265 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3266 3267 KASSERT(mutex_owned(&sc->sc_lock)); 3268 3269 if (sc->sc_dying) { 3270 xfer->ux_status = status; 3271 callout_stop(&xfer->ux_callout); 3272 usb_transfer_complete(xfer); 3273 return; 3274 } 3275 3276 if (xfer->ux_hcflags & UXFER_ABORTING) { 3277 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3278 3279 #ifdef DIAGNOSTIC 3280 if (status == USBD_TIMEOUT) 3281 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3282 #endif 3283 3284 xfer->ux_status = status; 3285 USBHIST_LOG(ehcidebug, 3286 "waiting for abort to finish", 0, 0, 0, 0); 3287 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3288 while (xfer->ux_hcflags & UXFER_ABORTING) 3289 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3290 goto done; 3291 } 3292 xfer->ux_hcflags |= UXFER_ABORTING; 3293 3294 xfer->ux_status = status; 3295 callout_stop(&xfer->ux_callout); 3296 3297 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3298 for (itd = exfer->ex_itdstart; itd != NULL; 3299 itd = itd->xfer_next) { 3300 usb_syncmem(&itd->dma, 3301 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3302 sizeof(itd->itd.itd_ctl), 3303 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3304 3305 for (i = 0; i < 8; i++) { 3306 trans_status = le32toh(itd->itd.itd_ctl[i]); 3307 trans_status &= ~EHCI_ITD_ACTIVE; 3308 itd->itd.itd_ctl[i] = htole32(trans_status); 3309 } 3310 3311 usb_syncmem(&itd->dma, 3312 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3313 sizeof(itd->itd.itd_ctl), 3314 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3315 } 3316 } else { 3317 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3318 sitd = sitd->xfer_next) { 3319 usb_syncmem(&sitd->dma, 3320 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3321 sizeof(sitd->sitd.sitd_buffer), 3322 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3323 3324 trans_status = le32toh(sitd->sitd.sitd_trans); 3325 trans_status &= ~EHCI_SITD_ACTIVE; 3326 sitd->sitd.sitd_trans = htole32(trans_status); 3327 3328 usb_syncmem(&sitd->dma, 3329 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3330 sizeof(sitd->sitd.sitd_buffer), 3331 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3332 } 3333 } 3334 3335 sc->sc_softwake = 1; 3336 usb_schedsoftintr(&sc->sc_bus); 3337 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3338 3339 #ifdef DIAGNOSTIC 3340 exfer->ex_isdone = true; 3341 #endif 3342 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3343 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3344 usb_transfer_complete(xfer); 3345 if (wake) { 3346 cv_broadcast(&xfer->ux_hccv); 3347 } 3348 3349 done: 3350 KASSERT(mutex_owned(&sc->sc_lock)); 3351 return; 3352 } 3353 3354 Static void 3355 ehci_timeout(void *addr) 3356 { 3357 struct ehci_xfer *exfer = addr; 3358 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->ex_xfer.ux_pipe; 3359 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3360 3361 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3362 3363 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3364 #ifdef EHCI_DEBUG 3365 if (ehcidebug > 1) 3366 usbd_dump_pipe(exfer->ex_xfer.ux_pipe); 3367 #endif 3368 3369 if (sc->sc_dying) { 3370 mutex_enter(&sc->sc_lock); 3371 ehci_abort_xfer(&exfer->ex_xfer, USBD_TIMEOUT); 3372 mutex_exit(&sc->sc_lock); 3373 return; 3374 } 3375 3376 /* Execute the abort in a process context. */ 3377 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, addr, 3378 USB_TASKQ_MPSAFE); 3379 usb_add_task(exfer->ex_xfer.ux_pipe->up_dev, &exfer->ex_aborttask, 3380 USB_TASKQ_HC); 3381 } 3382 3383 Static void 3384 ehci_timeout_task(void *addr) 3385 { 3386 usbd_xfer_handle xfer = addr; 3387 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3388 3389 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3390 3391 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3392 3393 mutex_enter(&sc->sc_lock); 3394 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3395 mutex_exit(&sc->sc_lock); 3396 } 3397 3398 /************************/ 3399 3400 Static usbd_status 3401 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3402 { 3403 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3404 usbd_status err; 3405 3406 /* Insert last in queue. */ 3407 mutex_enter(&sc->sc_lock); 3408 err = usb_insert_transfer(xfer); 3409 mutex_exit(&sc->sc_lock); 3410 if (err) 3411 return err; 3412 3413 /* Pipe isn't running, start first */ 3414 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3415 } 3416 3417 Static usbd_status 3418 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3419 { 3420 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3421 usbd_status err; 3422 3423 if (sc->sc_dying) 3424 return USBD_IOERROR; 3425 3426 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3427 3428 err = ehci_device_request(xfer); 3429 if (err) { 3430 return err; 3431 } 3432 3433 if (sc->sc_bus.ub_usepolling) 3434 ehci_waitintr(sc, xfer); 3435 3436 return USBD_IN_PROGRESS; 3437 } 3438 3439 Static void 3440 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3441 { 3442 struct ehci_xfer *ex = EXFER(xfer); 3443 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3444 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3445 usb_device_request_t *req = &xfer->ux_request; 3446 int len = UGETW(req->wLength); 3447 int rd = req->bmRequestType & UT_READ; 3448 3449 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3450 3451 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3452 3453 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3454 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3455 3456 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3457 ehci_del_intr_list(sc, ex); /* remove from active list */ 3458 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3459 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof(*req), 3460 BUS_DMASYNC_POSTWRITE); 3461 if (len) 3462 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3463 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3464 } 3465 3466 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3467 } 3468 3469 /* Abort a device control request. */ 3470 Static void 3471 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3472 { 3473 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3474 3475 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3476 ehci_abort_xfer(xfer, USBD_CANCELLED); 3477 } 3478 3479 /* Close a device control pipe. */ 3480 Static void 3481 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3482 { 3483 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3484 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3485 3486 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3487 3488 KASSERT(mutex_owned(&sc->sc_lock)); 3489 3490 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3491 3492 ehci_close_pipe(pipe, sc->sc_async_head); 3493 } 3494 3495 Static usbd_status 3496 ehci_device_request(usbd_xfer_handle xfer) 3497 { 3498 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3499 struct ehci_xfer *exfer = EXFER(xfer); 3500 usb_device_request_t *req = &xfer->ux_request; 3501 usbd_device_handle dev = epipe->pipe.up_dev; 3502 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3503 ehci_soft_qtd_t *setup, *stat, *next; 3504 ehci_soft_qh_t *sqh; 3505 int isread; 3506 int len; 3507 usbd_status err; 3508 3509 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3510 3511 isread = req->bmRequestType & UT_READ; 3512 len = UGETW(req->wLength); 3513 3514 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3515 "wValue=0x%04x, wIndex=0x%04x", 3516 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3517 UGETW(req->wIndex)); 3518 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3519 len, dev->ud_addr, 3520 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3521 3522 setup = ehci_alloc_sqtd(sc); 3523 if (setup == NULL) { 3524 err = USBD_NOMEM; 3525 goto bad1; 3526 } 3527 stat = ehci_alloc_sqtd(sc); 3528 if (stat == NULL) { 3529 err = USBD_NOMEM; 3530 goto bad2; 3531 } 3532 3533 mutex_enter(&sc->sc_lock); 3534 3535 sqh = epipe->sqh; 3536 3537 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3538 "address QH %" __PRIuBIT " pipe %d\n", 3539 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3540 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3541 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3542 "MPS QH %" __PRIuBIT " pipe %d\n", 3543 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3544 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3545 3546 /* Set up data transaction */ 3547 if (len != 0) { 3548 ehci_soft_qtd_t *end; 3549 3550 /* Start toggle at 1. */ 3551 epipe->nexttoggle = 1; 3552 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3553 &next, &end); 3554 if (err) 3555 goto bad3; 3556 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3557 end->nextqtd = stat; 3558 end->qtd.qtd_next = end->qtd.qtd_altnext = 3559 htole32(stat->physaddr); 3560 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3561 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3562 } else { 3563 next = stat; 3564 } 3565 3566 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 3567 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3568 3569 /* Clear toggle */ 3570 setup->qtd.qtd_status = htole32( 3571 EHCI_QTD_ACTIVE | 3572 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3573 EHCI_QTD_SET_CERR(3) | 3574 EHCI_QTD_SET_TOGGLE(0) | 3575 EHCI_QTD_SET_BYTES(sizeof(*req)) 3576 ); 3577 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3578 setup->qtd.qtd_buffer_hi[0] = 0; 3579 setup->nextqtd = next; 3580 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3581 setup->xfer = xfer; 3582 setup->len = sizeof(*req); 3583 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3584 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3585 3586 stat->qtd.qtd_status = htole32( 3587 EHCI_QTD_ACTIVE | 3588 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3589 EHCI_QTD_SET_CERR(3) | 3590 EHCI_QTD_SET_TOGGLE(1) | 3591 EHCI_QTD_IOC 3592 ); 3593 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3594 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3595 stat->nextqtd = NULL; 3596 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3597 stat->xfer = xfer; 3598 stat->len = 0; 3599 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3600 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3601 3602 #ifdef EHCI_DEBUG 3603 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3604 ehci_dump_sqh(sqh); 3605 ehci_dump_sqtds(setup); 3606 #endif 3607 3608 exfer->ex_sqtdstart = setup; 3609 exfer->ex_sqtdend = stat; 3610 KASSERT(exfer->ex_isdone); 3611 #ifdef DIAGNOSTIC 3612 exfer->ex_isdone = false; 3613 #endif 3614 3615 /* Insert qTD in QH list. */ 3616 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3617 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3618 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3619 ehci_timeout, xfer); 3620 } 3621 ehci_add_intr_list(sc, exfer); 3622 xfer->ux_status = USBD_IN_PROGRESS; 3623 mutex_exit(&sc->sc_lock); 3624 3625 #ifdef EHCI_DEBUG 3626 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3627 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3628 // delay(10000); 3629 ehci_dump_regs(sc); 3630 ehci_dump_sqh(sc->sc_async_head); 3631 ehci_dump_sqh(sqh); 3632 ehci_dump_sqtds(setup); 3633 #endif 3634 3635 return USBD_NORMAL_COMPLETION; 3636 3637 bad3: 3638 mutex_exit(&sc->sc_lock); 3639 ehci_free_sqtd(sc, stat); 3640 bad2: 3641 ehci_free_sqtd(sc, setup); 3642 bad1: 3643 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3644 mutex_enter(&sc->sc_lock); 3645 xfer->ux_status = err; 3646 usb_transfer_complete(xfer); 3647 mutex_exit(&sc->sc_lock); 3648 return err; 3649 } 3650 3651 /* 3652 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3653 * qTD status, or miss signalling occasionally under heavy load. If the host 3654 * machine is too fast, we we can miss transaction completion - when we scan 3655 * the active list the transaction still seems to be active. This generally 3656 * exhibits itself as a umass stall that never recovers. 3657 * 3658 * We work around this behaviour by setting up this callback after any softintr 3659 * that completes with transactions still pending, giving us another chance to 3660 * check for completion after the writeback has taken place. 3661 */ 3662 Static void 3663 ehci_intrlist_timeout(void *arg) 3664 { 3665 ehci_softc_t *sc = arg; 3666 3667 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3668 3669 usb_schedsoftintr(&sc->sc_bus); 3670 } 3671 3672 /************************/ 3673 3674 Static usbd_status 3675 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3676 { 3677 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3678 usbd_status err; 3679 3680 /* Insert last in queue. */ 3681 mutex_enter(&sc->sc_lock); 3682 err = usb_insert_transfer(xfer); 3683 mutex_exit(&sc->sc_lock); 3684 if (err) 3685 return err; 3686 3687 /* Pipe isn't running, start first */ 3688 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3689 } 3690 3691 Static usbd_status 3692 ehci_device_bulk_start(usbd_xfer_handle xfer) 3693 { 3694 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3695 struct ehci_xfer *exfer = EXFER(xfer); 3696 usbd_device_handle dev = epipe->pipe.up_dev; 3697 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3698 ehci_soft_qtd_t *data, *dataend; 3699 ehci_soft_qh_t *sqh; 3700 usbd_status err; 3701 int len, isread, endpt; 3702 3703 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3704 3705 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3706 xfer, xfer->ux_length, xfer->ux_flags, 0); 3707 3708 if (sc->sc_dying) 3709 return USBD_IOERROR; 3710 3711 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3712 3713 mutex_enter(&sc->sc_lock); 3714 3715 len = xfer->ux_length; 3716 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3717 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3718 sqh = epipe->sqh; 3719 3720 epipe->u.bulk.length = len; 3721 3722 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3723 &dataend); 3724 if (err) { 3725 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3726 xfer->ux_status = err; 3727 usb_transfer_complete(xfer); 3728 mutex_exit(&sc->sc_lock); 3729 return err; 3730 } 3731 3732 #ifdef EHCI_DEBUG 3733 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3734 ehci_dump_sqh(sqh); 3735 ehci_dump_sqtds(data); 3736 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3737 #endif 3738 3739 /* Set up interrupt info. */ 3740 exfer->ex_sqtdstart = data; 3741 exfer->ex_sqtdend = dataend; 3742 KASSERT(exfer->ex_isdone); 3743 #ifdef DIAGNOSTIC 3744 exfer->ex_isdone = false; 3745 #endif 3746 3747 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3748 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3749 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3750 ehci_timeout, xfer); 3751 } 3752 ehci_add_intr_list(sc, exfer); 3753 xfer->ux_status = USBD_IN_PROGRESS; 3754 mutex_exit(&sc->sc_lock); 3755 3756 #ifdef EHCI_DEBUG 3757 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3758 // delay(10000); 3759 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3760 ehci_dump_regs(sc); 3761 #if 0 3762 printf("async_head:\n"); 3763 ehci_dump_sqh(sc->sc_async_head); 3764 #endif 3765 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3766 ehci_dump_sqh(sqh); 3767 ehci_dump_sqtds(data); 3768 #endif 3769 3770 if (sc->sc_bus.ub_usepolling) 3771 ehci_waitintr(sc, xfer); 3772 3773 return USBD_IN_PROGRESS; 3774 } 3775 3776 Static void 3777 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3778 { 3779 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3780 3781 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3782 ehci_abort_xfer(xfer, USBD_CANCELLED); 3783 } 3784 3785 /* 3786 * Close a device bulk pipe. 3787 */ 3788 Static void 3789 ehci_device_bulk_close(usbd_pipe_handle pipe) 3790 { 3791 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3792 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3793 3794 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3795 3796 KASSERT(mutex_owned(&sc->sc_lock)); 3797 3798 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3799 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3800 ehci_close_pipe(pipe, sc->sc_async_head); 3801 } 3802 3803 Static void 3804 ehci_device_bulk_done(usbd_xfer_handle xfer) 3805 { 3806 struct ehci_xfer *ex = EXFER(xfer); 3807 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3808 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3809 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3810 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3811 3812 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3813 3814 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3815 xfer, xfer->ux_actlen, 0, 0); 3816 3817 KASSERT(mutex_owned(&sc->sc_lock)); 3818 3819 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3820 ehci_del_intr_list(sc, ex); /* remove from active list */ 3821 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3822 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3823 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3824 } 3825 3826 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3827 } 3828 3829 /************************/ 3830 3831 Static usbd_status 3832 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3833 { 3834 struct ehci_soft_islot *isp; 3835 int islot, lev; 3836 3837 /* Find a poll rate that is large enough. */ 3838 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3839 if (EHCI_ILEV_IVAL(lev) <= ival) 3840 break; 3841 3842 /* Pick an interrupt slot at the right level. */ 3843 /* XXX could do better than picking at random */ 3844 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3845 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3846 3847 sqh->islot = islot; 3848 isp = &sc->sc_islots[islot]; 3849 mutex_enter(&sc->sc_lock); 3850 ehci_add_qh(sc, sqh, isp->sqh); 3851 mutex_exit(&sc->sc_lock); 3852 3853 return USBD_NORMAL_COMPLETION; 3854 } 3855 3856 Static usbd_status 3857 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3858 { 3859 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3860 usbd_status err; 3861 3862 /* Insert last in queue. */ 3863 mutex_enter(&sc->sc_lock); 3864 err = usb_insert_transfer(xfer); 3865 mutex_exit(&sc->sc_lock); 3866 if (err) 3867 return err; 3868 3869 /* 3870 * Pipe isn't running (otherwise err would be USBD_INPROG), 3871 * so start it first. 3872 */ 3873 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3874 } 3875 3876 Static usbd_status 3877 ehci_device_intr_start(usbd_xfer_handle xfer) 3878 { 3879 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3880 struct ehci_xfer *exfer = EXFER(xfer); 3881 usbd_device_handle dev = xfer->ux_pipe->up_dev; 3882 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3883 ehci_soft_qtd_t *data, *dataend; 3884 ehci_soft_qh_t *sqh; 3885 usbd_status err; 3886 int len, isread, endpt; 3887 3888 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3889 3890 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3891 xfer, xfer->ux_length, xfer->ux_flags, 0); 3892 3893 if (sc->sc_dying) 3894 return USBD_IOERROR; 3895 3896 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3897 3898 mutex_enter(&sc->sc_lock); 3899 3900 len = xfer->ux_length; 3901 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3902 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3903 sqh = epipe->sqh; 3904 3905 epipe->u.intr.length = len; 3906 3907 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3908 &dataend); 3909 if (err) { 3910 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3911 xfer->ux_status = err; 3912 usb_transfer_complete(xfer); 3913 mutex_exit(&sc->sc_lock); 3914 return err; 3915 } 3916 3917 #ifdef EHCI_DEBUG 3918 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3919 ehci_dump_sqh(sqh); 3920 ehci_dump_sqtds(data); 3921 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3922 #endif 3923 3924 /* Set up interrupt info. */ 3925 exfer->ex_sqtdstart = data; 3926 exfer->ex_sqtdend = dataend; 3927 KASSERT(exfer->ex_isdone); 3928 #ifdef DIAGNOSTIC 3929 exfer->ex_isdone = false; 3930 #endif 3931 3932 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3933 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3934 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3935 ehci_timeout, xfer); 3936 } 3937 ehci_add_intr_list(sc, exfer); 3938 xfer->ux_status = USBD_IN_PROGRESS; 3939 mutex_exit(&sc->sc_lock); 3940 3941 #ifdef EHCI_DEBUG 3942 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3943 // delay(10000); 3944 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3945 ehci_dump_regs(sc); 3946 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3947 ehci_dump_sqh(sqh); 3948 ehci_dump_sqtds(data); 3949 #endif 3950 3951 if (sc->sc_bus.ub_usepolling) 3952 ehci_waitintr(sc, xfer); 3953 3954 return USBD_IN_PROGRESS; 3955 } 3956 3957 Static void 3958 ehci_device_intr_abort(usbd_xfer_handle xfer) 3959 { 3960 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3961 3962 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3963 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3964 3965 /* 3966 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3967 * async doorbell. That's dependent on the async list, wheras 3968 * intr xfers are periodic, should not use this? 3969 */ 3970 ehci_abort_xfer(xfer, USBD_CANCELLED); 3971 } 3972 3973 Static void 3974 ehci_device_intr_close(usbd_pipe_handle pipe) 3975 { 3976 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3977 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3978 struct ehci_soft_islot *isp; 3979 3980 KASSERT(mutex_owned(&sc->sc_lock)); 3981 3982 isp = &sc->sc_islots[epipe->sqh->islot]; 3983 ehci_close_pipe(pipe, isp->sqh); 3984 } 3985 3986 Static void 3987 ehci_device_intr_done(usbd_xfer_handle xfer) 3988 { 3989 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3990 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3991 struct ehci_xfer *exfer = EXFER(xfer); 3992 ehci_soft_qtd_t *data, *dataend; 3993 ehci_soft_qh_t *sqh; 3994 usbd_status err; 3995 int len, isread, endpt; 3996 3997 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3998 3999 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4000 xfer, xfer->ux_actlen, 0, 0); 4001 4002 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4003 4004 if (xfer->ux_pipe->up_repeat) { 4005 ehci_free_sqtd_chain(sc, exfer->ex_sqtdstart, NULL); 4006 4007 len = epipe->u.intr.length; 4008 xfer->ux_length = len; 4009 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4010 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4011 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4012 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4013 sqh = epipe->sqh; 4014 4015 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4016 &data, &dataend); 4017 if (err) { 4018 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4019 xfer->ux_status = err; 4020 return; 4021 } 4022 4023 /* Set up interrupt info. */ 4024 exfer->ex_sqtdstart = data; 4025 exfer->ex_sqtdend = dataend; 4026 KASSERT(exfer->ex_isdone); 4027 #ifdef DIAGNOSTIC 4028 exfer->ex_isdone = false; 4029 #endif 4030 4031 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4032 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4033 callout_reset(&xfer->ux_callout, 4034 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4035 } 4036 4037 xfer->ux_status = USBD_IN_PROGRESS; 4038 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4039 ehci_del_intr_list(sc, exfer); /* remove from active list */ 4040 ehci_free_sqtd_chain(sc, exfer->ex_sqtdstart, NULL); 4041 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4042 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4043 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4044 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4045 } 4046 } 4047 4048 /************************/ 4049 4050 Static usbd_status 4051 ehci_device_fs_isoc_transfer(usbd_xfer_handle xfer) 4052 { 4053 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4054 usbd_status err; 4055 4056 mutex_enter(&sc->sc_lock); 4057 err = usb_insert_transfer(xfer); 4058 mutex_exit(&sc->sc_lock); 4059 4060 if (err && err != USBD_IN_PROGRESS) 4061 return err; 4062 4063 return ehci_device_fs_isoc_start(xfer); 4064 } 4065 4066 Static usbd_status 4067 ehci_device_fs_isoc_start(usbd_xfer_handle xfer) 4068 { 4069 struct ehci_pipe *epipe; 4070 usbd_device_handle dev; 4071 ehci_softc_t *sc; 4072 struct ehci_xfer *exfer; 4073 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4074 usb_dma_t *dma_buf; 4075 int i, j, k, frames; 4076 int offs, total_length; 4077 int frindex; 4078 u_int huba, dir; 4079 4080 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4081 4082 start = NULL; 4083 prev = NULL; 4084 sitd = NULL; 4085 total_length = 0; 4086 exfer = (struct ehci_xfer *) xfer; 4087 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4088 dev = xfer->ux_pipe->up_dev; 4089 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4090 4091 /* 4092 * To allow continuous transfers, above we start all transfers 4093 * immediately. However, we're still going to get usbd_start_next call 4094 * this when another xfer completes. So, check if this is already 4095 * in progress or not 4096 */ 4097 4098 if (exfer->ex_sitdstart != NULL) 4099 return USBD_IN_PROGRESS; 4100 4101 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4102 xfer, xfer->ux_length, xfer->ux_flags, 0); 4103 4104 if (sc->sc_dying) 4105 return USBD_IOERROR; 4106 4107 /* 4108 * To avoid complication, don't allow a request right now that'll span 4109 * the entire frame table. To within 4 frames, to allow some leeway 4110 * on either side of where the hc currently is. 4111 */ 4112 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4113 xfer->ux_nframes >= sc->sc_flsize - 4) { 4114 printf("ehci: isoc descriptor requested that spans the entire" 4115 "frametable, too many frames\n"); 4116 return USBD_INVAL; 4117 } 4118 4119 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4120 KASSERT(exfer->ex_isdone); 4121 4122 #ifdef DIAGNOSTIC 4123 exfer->ex_isdone = false; 4124 #endif 4125 4126 /* 4127 * Step 1: Allocate and initialize sitds. 4128 */ 4129 4130 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4131 if (i > 16 || i == 0) { 4132 /* Spec page 271 says intervals > 16 are invalid */ 4133 USBHIST_LOG(ehcidebug, "bInterval %d invalid", 0, 0, 0, 0); 4134 4135 return USBD_INVAL; 4136 } 4137 4138 frames = xfer->ux_nframes; 4139 4140 if (frames == 0) { 4141 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4142 4143 return USBD_INVAL; 4144 } 4145 4146 dma_buf = &xfer->ux_dmabuf; 4147 offs = 0; 4148 4149 for (i = 0; i < frames; i++) { 4150 sitd = ehci_alloc_sitd(sc); 4151 4152 if (prev) 4153 prev->xfer_next = sitd; 4154 else 4155 start = sitd; 4156 4157 #ifdef DIAGNOSTIC 4158 if (xfer->ux_frlengths[i] > 0x3ff) { 4159 printf("ehci: invalid frame length\n"); 4160 xfer->ux_frlengths[i] = 0x3ff; 4161 } 4162 #endif 4163 4164 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4165 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4166 4167 /* Set page0 index and offset. */ 4168 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4169 4170 total_length += xfer->ux_frlengths[i]; 4171 offs += xfer->ux_frlengths[i]; 4172 4173 sitd->sitd.sitd_buffer[1] = 4174 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4175 4176 huba = dev->ud_myhsport->up_parent->ud_addr; 4177 4178 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4179 // Set hub address to 0 if embedded TT is used. 4180 if (huba == sc->sc_addr) 4181 huba = 0; 4182 } 4183 */ 4184 4185 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4186 dir = UE_GET_DIR(k) ? 1 : 0; 4187 sitd->sitd.sitd_endp = 4188 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4189 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4190 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4191 EHCI_SITD_SET_HUBA(huba) | 4192 EHCI_SITD_SET_DIR(dir)); 4193 4194 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4195 4196 /* XXX */ 4197 u_char sa, sb; 4198 u_int temp, tlen; 4199 sa = 0; 4200 4201 if (dir == 0) { /* OUT */ 4202 temp = 0; 4203 tlen = xfer->ux_frlengths[i]; 4204 if (tlen <= 188) { 4205 temp |= 1; /* T-count = 1, TP = ALL */ 4206 tlen = 1; 4207 } else { 4208 tlen += 187; 4209 tlen /= 188; 4210 temp |= tlen; /* T-count = [1..6] */ 4211 temp |= 8; /* TP = Begin */ 4212 } 4213 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4214 4215 tlen += sa; 4216 4217 if (tlen >= 8) { 4218 sb = 0; 4219 } else { 4220 sb = (1 << tlen); 4221 } 4222 4223 sa = (1 << sa); 4224 sa = (sb - sa) & 0x3F; 4225 sb = 0; 4226 } else { 4227 sb = (-(4 << sa)) & 0xFE; 4228 sa = (1 << sa) & 0x3F; 4229 sa = 0x01; 4230 sb = 0xfc; 4231 } 4232 4233 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4234 EHCI_SITD_SET_CMASK(sb)); 4235 4236 prev = sitd; 4237 } /* End of frame */ 4238 4239 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4240 4241 stop = sitd; 4242 stop->xfer_next = NULL; 4243 4244 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4245 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4246 4247 /* 4248 * Part 2: Transfer descriptors have now been set up, now they must 4249 * be scheduled into the periodic frame list. Erk. Not wanting to 4250 * complicate matters, transfer is denied if the transfer spans 4251 * more than the period frame list. 4252 */ 4253 4254 mutex_enter(&sc->sc_lock); 4255 4256 /* Start inserting frames */ 4257 if (epipe->u.isoc.cur_xfers > 0) { 4258 frindex = epipe->u.isoc.next_frame; 4259 } else { 4260 frindex = EOREAD4(sc, EHCI_FRINDEX); 4261 frindex = frindex >> 3; /* Erase microframe index */ 4262 frindex += 2; 4263 } 4264 4265 if (frindex >= sc->sc_flsize) 4266 frindex &= (sc->sc_flsize - 1); 4267 4268 /* Whats the frame interval? */ 4269 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4270 4271 sitd = start; 4272 for (j = 0; j < frames; j++) { 4273 if (sitd == NULL) 4274 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4275 4276 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4277 if (sitd->sitd.sitd_next == 0) 4278 /* FIXME: frindex table gets initialized to NULL 4279 * or EHCI_NULL? */ 4280 sitd->sitd.sitd_next = EHCI_NULL; 4281 4282 usb_syncmem(&sitd->dma, 4283 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4284 sizeof(ehci_sitd_t), 4285 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4286 4287 sc->sc_flist[frindex] = 4288 htole32(EHCI_LINK_SITD | sitd->physaddr); 4289 4290 usb_syncmem(&sc->sc_fldma, 4291 sizeof(ehci_link_t) * frindex, 4292 sizeof(ehci_link_t), 4293 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4294 4295 sitd->u.frame_list.next = sc->sc_softsitds[frindex]; 4296 sc->sc_softsitds[frindex] = sitd; 4297 if (sitd->u.frame_list.next != NULL) 4298 sitd->u.frame_list.next->u.frame_list.prev = sitd; 4299 sitd->slot = frindex; 4300 sitd->u.frame_list.prev = NULL; 4301 4302 frindex += i; 4303 if (frindex >= sc->sc_flsize) 4304 frindex -= sc->sc_flsize; 4305 4306 sitd = sitd->xfer_next; 4307 } 4308 4309 epipe->u.isoc.cur_xfers++; 4310 epipe->u.isoc.next_frame = frindex; 4311 4312 exfer->ex_sitdstart = start; 4313 exfer->ex_sitdend = stop; 4314 4315 ehci_add_intr_list(sc, exfer); 4316 xfer->ux_status = USBD_IN_PROGRESS; 4317 xfer->ux_done = 0; 4318 4319 mutex_exit(&sc->sc_lock); 4320 4321 if (sc->sc_bus.ub_usepolling) { 4322 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4323 ehci_waitintr(sc, xfer); 4324 } 4325 4326 return USBD_IN_PROGRESS; 4327 } 4328 4329 Static void 4330 ehci_device_fs_isoc_abort(usbd_xfer_handle xfer) 4331 { 4332 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4333 4334 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4335 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4336 } 4337 4338 Static void 4339 ehci_device_fs_isoc_close(usbd_pipe_handle pipe) 4340 { 4341 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4342 4343 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4344 } 4345 4346 Static void 4347 ehci_device_fs_isoc_done(usbd_xfer_handle xfer) 4348 { 4349 struct ehci_xfer *exfer; 4350 ehci_softc_t *sc; 4351 struct ehci_pipe *epipe; 4352 4353 exfer = EXFER(xfer); 4354 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4355 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4356 4357 KASSERT(mutex_owned(&sc->sc_lock)); 4358 4359 epipe->u.isoc.cur_xfers--; 4360 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4361 ehci_del_intr_list(sc, exfer); 4362 ehci_rem_free_sitd_chain(sc, exfer); 4363 } 4364 4365 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4366 BUS_DMASYNC_POSTREAD); 4367 } 4368 Static usbd_status 4369 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 4370 { 4371 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4372 usbd_status err; 4373 4374 mutex_enter(&sc->sc_lock); 4375 err = usb_insert_transfer(xfer); 4376 mutex_exit(&sc->sc_lock); 4377 if (err && err != USBD_IN_PROGRESS) 4378 return err; 4379 4380 return ehci_device_isoc_start(xfer); 4381 } 4382 4383 Static usbd_status 4384 ehci_device_isoc_start(usbd_xfer_handle xfer) 4385 { 4386 struct ehci_pipe *epipe; 4387 ehci_softc_t *sc; 4388 struct ehci_xfer *exfer; 4389 ehci_soft_itd_t *itd, *prev, *start, *stop; 4390 usb_dma_t *dma_buf; 4391 int i, j, k, frames, uframes, ufrperframe; 4392 int trans_count, offs, total_length; 4393 int frindex; 4394 4395 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4396 4397 start = NULL; 4398 prev = NULL; 4399 itd = NULL; 4400 trans_count = 0; 4401 total_length = 0; 4402 exfer = (struct ehci_xfer *) xfer; 4403 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4404 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4405 4406 /* 4407 * To allow continuous transfers, above we start all transfers 4408 * immediately. However, we're still going to get usbd_start_next call 4409 * this when another xfer completes. So, check if this is already 4410 * in progress or not 4411 */ 4412 4413 if (exfer->ex_itdstart != NULL) 4414 return USBD_IN_PROGRESS; 4415 4416 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4417 xfer, xfer->ux_length, xfer->ux_flags, 0); 4418 4419 if (sc->sc_dying) 4420 return USBD_IOERROR; 4421 4422 /* 4423 * To avoid complication, don't allow a request right now that'll span 4424 * the entire frame table. To within 4 frames, to allow some leeway 4425 * on either side of where the hc currently is. 4426 */ 4427 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4428 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4429 USBHIST_LOG(ehcidebug, 4430 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4431 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4432 return USBD_INVAL; 4433 } 4434 4435 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4436 KASSERT(exfer->ex_isdone); 4437 #ifdef DIAGNOSTIC 4438 exfer->ex_isdone = false; 4439 #endif 4440 4441 /* 4442 * Step 1: Allocate and initialize itds, how many do we need? 4443 * One per transfer if interval >= 8 microframes, fewer if we use 4444 * multiple microframes per frame. 4445 */ 4446 4447 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4448 if (i > 16 || i == 0) { 4449 /* Spec page 271 says intervals > 16 are invalid */ 4450 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4451 return USBD_INVAL; 4452 } 4453 4454 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4455 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4456 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4457 4458 if (frames == 0) { 4459 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4460 return USBD_INVAL; 4461 } 4462 4463 dma_buf = &xfer->ux_dmabuf; 4464 offs = 0; 4465 4466 for (i = 0; i < frames; i++) { 4467 int froffs = offs; 4468 itd = ehci_alloc_itd(sc); 4469 4470 if (prev != NULL) { 4471 prev->itd.itd_next = 4472 htole32(itd->physaddr | EHCI_LINK_ITD); 4473 usb_syncmem(&itd->dma, 4474 itd->offs + offsetof(ehci_itd_t, itd_next), 4475 sizeof(itd->itd.itd_next), BUS_DMASYNC_POSTWRITE); 4476 4477 prev->xfer_next = itd; 4478 } else { 4479 start = itd; 4480 } 4481 4482 /* 4483 * Step 1.5, initialize uframes 4484 */ 4485 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4486 /* Calculate which page in the list this starts in */ 4487 int addr = DMAADDR(dma_buf, froffs); 4488 addr = EHCI_PAGE_OFFSET(addr); 4489 addr += (offs - froffs); 4490 addr = EHCI_PAGE(addr); 4491 addr /= EHCI_PAGE_SIZE; 4492 4493 /* 4494 * This gets the initial offset into the first page, 4495 * looks how far further along the current uframe 4496 * offset is. Works out how many pages that is. 4497 */ 4498 4499 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4500 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4501 EHCI_ITD_SET_PG(addr) | 4502 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4503 4504 total_length += xfer->ux_frlengths[trans_count]; 4505 offs += xfer->ux_frlengths[trans_count]; 4506 trans_count++; 4507 4508 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4509 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4510 break; 4511 } 4512 } 4513 4514 /* 4515 * Step 1.75, set buffer pointers. To simplify matters, all 4516 * pointers are filled out for the next 7 hardware pages in 4517 * the dma block, so no need to worry what pages to cover 4518 * and what to not. 4519 */ 4520 4521 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4522 /* 4523 * Don't try to lookup a page that's past the end 4524 * of buffer 4525 */ 4526 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4527 if (page_offs >= dma_buf->udma_block->size) 4528 break; 4529 4530 unsigned long long page = DMAADDR(dma_buf, page_offs); 4531 page = EHCI_PAGE(page); 4532 itd->itd.itd_bufr[j] = 4533 htole32(EHCI_ITD_SET_BPTR(page)); 4534 itd->itd.itd_bufr_hi[j] = 4535 htole32(page >> 32); 4536 } 4537 4538 /* 4539 * Other special values 4540 */ 4541 4542 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4543 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4544 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4545 4546 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4547 ? 1 : 0; 4548 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4549 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4550 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4551 4552 /* FIXME: handle invalid trans */ 4553 itd->itd.itd_bufr[2] |= 4554 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4555 4556 usb_syncmem(&itd->dma, 4557 itd->offs + offsetof(ehci_itd_t, itd_next), 4558 sizeof(ehci_itd_t), 4559 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4560 4561 prev = itd; 4562 } /* End of frame */ 4563 4564 stop = itd; 4565 stop->xfer_next = NULL; 4566 4567 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4568 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4569 4570 /* 4571 * Part 2: Transfer descriptors have now been set up, now they must 4572 * be scheduled into the period frame list. Erk. Not wanting to 4573 * complicate matters, transfer is denied if the transfer spans 4574 * more than the period frame list. 4575 */ 4576 4577 mutex_enter(&sc->sc_lock); 4578 4579 /* Start inserting frames */ 4580 if (epipe->u.isoc.cur_xfers > 0) { 4581 frindex = epipe->u.isoc.next_frame; 4582 } else { 4583 frindex = EOREAD4(sc, EHCI_FRINDEX); 4584 frindex = frindex >> 3; /* Erase microframe index */ 4585 frindex += 2; 4586 } 4587 4588 if (frindex >= sc->sc_flsize) 4589 frindex &= (sc->sc_flsize - 1); 4590 4591 /* What's the frame interval? */ 4592 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4593 if (i / USB_UFRAMES_PER_FRAME == 0) 4594 i = 1; 4595 else 4596 i /= USB_UFRAMES_PER_FRAME; 4597 4598 itd = start; 4599 for (j = 0; j < frames; j++) { 4600 if (itd == NULL) 4601 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4602 4603 itd->itd.itd_next = sc->sc_flist[frindex]; 4604 if (itd->itd.itd_next == 0) 4605 /* FIXME: frindex table gets initialized to NULL 4606 * or EHCI_NULL? */ 4607 itd->itd.itd_next = EHCI_NULL; 4608 4609 usb_syncmem(&itd->dma, 4610 itd->offs + offsetof(ehci_itd_t, itd_next), 4611 sizeof(itd->itd.itd_next), 4612 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4613 4614 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4615 4616 usb_syncmem(&sc->sc_fldma, 4617 sizeof(ehci_link_t) * frindex, 4618 sizeof(ehci_link_t), 4619 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4620 4621 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4622 sc->sc_softitds[frindex] = itd; 4623 if (itd->u.frame_list.next != NULL) 4624 itd->u.frame_list.next->u.frame_list.prev = itd; 4625 itd->slot = frindex; 4626 itd->u.frame_list.prev = NULL; 4627 4628 frindex += i; 4629 if (frindex >= sc->sc_flsize) 4630 frindex -= sc->sc_flsize; 4631 4632 itd = itd->xfer_next; 4633 } 4634 4635 epipe->u.isoc.cur_xfers++; 4636 epipe->u.isoc.next_frame = frindex; 4637 4638 exfer->ex_itdstart = start; 4639 exfer->ex_itdend = stop; 4640 4641 ehci_add_intr_list(sc, exfer); 4642 xfer->ux_status = USBD_IN_PROGRESS; 4643 xfer->ux_done = 0; 4644 mutex_exit(&sc->sc_lock); 4645 4646 if (sc->sc_bus.ub_usepolling) { 4647 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4648 ehci_waitintr(sc, xfer); 4649 } 4650 4651 return USBD_IN_PROGRESS; 4652 } 4653 4654 Static void 4655 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4656 { 4657 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4658 4659 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4660 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4661 } 4662 4663 Static void 4664 ehci_device_isoc_close(usbd_pipe_handle pipe) 4665 { 4666 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4667 4668 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4669 } 4670 4671 Static void 4672 ehci_device_isoc_done(usbd_xfer_handle xfer) 4673 { 4674 struct ehci_xfer *exfer; 4675 ehci_softc_t *sc; 4676 struct ehci_pipe *epipe; 4677 4678 exfer = EXFER(xfer); 4679 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4680 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4681 4682 KASSERT(mutex_owned(&sc->sc_lock)); 4683 4684 epipe->u.isoc.cur_xfers--; 4685 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4686 ehci_del_intr_list(sc, exfer); 4687 ehci_rem_free_itd_chain(sc, exfer); 4688 } 4689 4690 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4691 BUS_DMASYNC_POSTREAD); 4692 4693 } 4694
Indexes created Wed Oct 01 19:09:53 GMT 2025