ehci.c revision 1.234.2.42
1 /* $NetBSD: ehci.c,v 1.234.2.42 2015/03/16 21:21:46 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.42 2015/03/16 21:21:46 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 85 #include <dev/usb/ehcireg.h> 86 #include <dev/usb/ehcivar.h> 87 #include <dev/usb/usbroothub.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 /* ehci_soft_sitd_t *sitd; */ 135 } tail; 136 union { 137 /* Control pipe */ 138 struct { 139 usb_dma_t reqdma; 140 } ctl; 141 /* Interrupt pipe */ 142 struct { 143 u_int length; 144 } intr; 145 /* Bulk pipe */ 146 struct { 147 u_int length; 148 } bulk; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 } u; 155 }; 156 157 Static usbd_status ehci_open(usbd_pipe_handle); 158 Static void ehci_poll(struct usbd_bus *); 159 Static void ehci_softintr(void *); 160 Static int ehci_intr1(ehci_softc_t *); 161 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle); 162 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 166 Static void ehci_idone(struct ehci_xfer *); 167 Static void ehci_timeout(void *); 168 Static void ehci_timeout_task(void *); 169 Static void ehci_intrlist_timeout(void *); 170 Static void ehci_doorbell(void *); 171 Static void ehci_pcd(void *); 172 173 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *); 174 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle); 175 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 176 Static int ehci_roothub_ctrl(struct usbd_bus *, 177 usb_device_request_t *, void *, int); 178 179 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle); 180 Static usbd_status ehci_root_intr_start(usbd_xfer_handle); 181 Static void ehci_root_intr_abort(usbd_xfer_handle); 182 Static void ehci_root_intr_close(usbd_pipe_handle); 183 Static void ehci_root_intr_done(usbd_xfer_handle); 184 185 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle); 186 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle); 187 Static void ehci_device_ctrl_abort(usbd_xfer_handle); 188 Static void ehci_device_ctrl_close(usbd_pipe_handle); 189 Static void ehci_device_ctrl_done(usbd_xfer_handle); 190 191 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle); 192 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle); 193 Static void ehci_device_bulk_abort(usbd_xfer_handle); 194 Static void ehci_device_bulk_close(usbd_pipe_handle); 195 Static void ehci_device_bulk_done(usbd_xfer_handle); 196 197 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle); 198 Static usbd_status ehci_device_intr_start(usbd_xfer_handle); 199 Static void ehci_device_intr_abort(usbd_xfer_handle); 200 Static void ehci_device_intr_close(usbd_pipe_handle); 201 Static void ehci_device_intr_done(usbd_xfer_handle); 202 203 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle); 204 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle); 205 Static void ehci_device_isoc_abort(usbd_xfer_handle); 206 Static void ehci_device_isoc_close(usbd_pipe_handle); 207 Static void ehci_device_isoc_done(usbd_xfer_handle); 208 209 Static usbd_status ehci_device_fs_isoc_transfer(usbd_xfer_handle); 210 Static usbd_status ehci_device_fs_isoc_start(usbd_xfer_handle); 211 Static void ehci_device_fs_isoc_abort(usbd_xfer_handle); 212 Static void ehci_device_fs_isoc_close(usbd_pipe_handle); 213 Static void ehci_device_fs_isoc_done(usbd_xfer_handle); 214 215 Static void ehci_device_clear_toggle(usbd_pipe_handle); 216 Static void ehci_noop(usbd_pipe_handle); 217 218 Static void ehci_disown(ehci_softc_t *, int, int); 219 220 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 221 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 222 223 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 224 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 225 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 226 ehci_softc_t *, int, int, usbd_xfer_handle, 227 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 228 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 229 ehci_soft_qtd_t *); 230 231 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 232 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *); 233 Static void ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *); 234 Static void ehci_free_sitd(ehci_softc_t *, ehci_soft_sitd_t *); 235 Static void ehci_rem_free_itd_chain(ehci_softc_t *, 236 struct ehci_xfer *); 237 Static void ehci_rem_free_sitd_chain(ehci_softc_t *, 238 struct ehci_xfer *); 239 Static void ehci_abort_isoc_xfer(usbd_xfer_handle, 240 usbd_status); 241 242 Static usbd_status ehci_device_request(usbd_xfer_handle); 243 244 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 245 int); 246 247 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 248 ehci_soft_qh_t *); 249 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 250 ehci_soft_qh_t *); 251 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 252 Static void ehci_sync_hc(ehci_softc_t *); 253 254 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *); 255 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status); 256 257 #ifdef EHCI_DEBUG 258 Static ehci_softc_t *theehci; 259 void ehci_dump(void); 260 #endif 261 262 #ifdef EHCI_DEBUG 263 Static void ehci_dump_regs(ehci_softc_t *); 264 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 265 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 266 Static void ehci_dump_qtd(ehci_qtd_t *); 267 Static void ehci_dump_sqh(ehci_soft_qh_t *); 268 Static void ehci_dump_sitd(struct ehci_soft_itd *); 269 Static void ehci_dump_itd(struct ehci_soft_itd *); 270 Static void ehci_dump_exfer(struct ehci_xfer *); 271 #endif 272 273 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 274 275 #define ehci_add_intr_list(sc, ex) \ 276 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 277 #define ehci_del_intr_list(sc, ex) \ 278 do { \ 279 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 280 (ex)->ex_next.tqe_prev = NULL; \ 281 } while (0) 282 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 283 284 Static const struct usbd_bus_methods ehci_bus_methods = { 285 .ubm_open = ehci_open, 286 .ubm_softint = ehci_softintr, 287 .ubm_dopoll = ehci_poll, 288 .ubm_allocx = ehci_allocx, 289 .ubm_freex = ehci_freex, 290 .ubm_getlock = ehci_get_lock, 291 .ubm_rhctrl = ehci_roothub_ctrl, 292 }; 293 294 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 295 .upm_transfer = ehci_root_intr_transfer, 296 .upm_start = ehci_root_intr_start, 297 .upm_abort = ehci_root_intr_abort, 298 .upm_close = ehci_root_intr_close, 299 .upm_cleartoggle = ehci_noop, 300 .upm_done = ehci_root_intr_done, 301 }; 302 303 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 304 .upm_transfer = ehci_device_ctrl_transfer, 305 .upm_start = ehci_device_ctrl_start, 306 .upm_abort = ehci_device_ctrl_abort, 307 .upm_close = ehci_device_ctrl_close, 308 .upm_cleartoggle = ehci_noop, 309 .upm_done = ehci_device_ctrl_done, 310 }; 311 312 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 313 .upm_transfer = ehci_device_intr_transfer, 314 .upm_start = ehci_device_intr_start, 315 .upm_abort = ehci_device_intr_abort, 316 .upm_close = ehci_device_intr_close, 317 .upm_cleartoggle = ehci_device_clear_toggle, 318 .upm_done = ehci_device_intr_done, 319 }; 320 321 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 322 .upm_transfer = ehci_device_bulk_transfer, 323 .upm_start = ehci_device_bulk_start, 324 .upm_abort = ehci_device_bulk_abort, 325 .upm_close = ehci_device_bulk_close, 326 .upm_cleartoggle = ehci_device_clear_toggle, 327 .upm_done = ehci_device_bulk_done, 328 }; 329 330 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 331 .upm_transfer = ehci_device_isoc_transfer, 332 .upm_start = ehci_device_isoc_start, 333 .upm_abort = ehci_device_isoc_abort, 334 .upm_close = ehci_device_isoc_close, 335 .upm_cleartoggle = ehci_noop, 336 .upm_done = ehci_device_isoc_done, 337 }; 338 339 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 340 .upm_transfer = ehci_device_fs_isoc_transfer, 341 .upm_start = ehci_device_fs_isoc_start, 342 .upm_abort = ehci_device_fs_isoc_abort, 343 .upm_close = ehci_device_fs_isoc_close, 344 .upm_cleartoggle = ehci_noop, 345 .upm_done = ehci_device_fs_isoc_done, 346 }; 347 348 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 349 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 350 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 351 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 352 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 353 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 354 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 355 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 356 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 357 }; 358 359 int 360 ehci_init(ehci_softc_t *sc) 361 { 362 uint32_t vers, sparams, cparams, hcr; 363 u_int i; 364 usbd_status err; 365 ehci_soft_qh_t *sqh; 366 u_int ncomp; 367 368 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 369 #ifdef EHCI_DEBUG 370 theehci = sc; 371 #endif 372 373 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 374 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 375 cv_init(&sc->sc_softwake_cv, "ehciab"); 376 cv_init(&sc->sc_doorbell, "ehcidi"); 377 378 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 379 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 380 381 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 382 ehci_doorbell, sc); 383 KASSERT(sc->sc_doorbell_si != NULL); 384 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 385 ehci_pcd, sc); 386 KASSERT(sc->sc_pcd_si != NULL); 387 388 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 389 390 vers = EREAD2(sc, EHCI_HCIVERSION); 391 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 392 vers >> 8, vers & 0xff); 393 394 sparams = EREAD4(sc, EHCI_HCSPARAMS); 395 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 396 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 397 ncomp = EHCI_HCS_N_CC(sparams); 398 if (ncomp != sc->sc_ncomp) { 399 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 400 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 401 #if NOHCI == 0 || NUHCI == 0 402 aprint_error("%s: ohci or uhci probably not configured\n", 403 device_xname(sc->sc_dev)); 404 #endif 405 if (ncomp < sc->sc_ncomp) 406 sc->sc_ncomp = ncomp; 407 } 408 if (sc->sc_ncomp > 0) { 409 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 410 aprint_normal("%s: companion controller%s, %d port%s each:", 411 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 412 EHCI_HCS_N_PCC(sparams), 413 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 414 for (i = 0; i < sc->sc_ncomp; i++) 415 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 416 aprint_normal("\n"); 417 } 418 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 419 cparams = EREAD4(sc, EHCI_HCCPARAMS); 420 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 421 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 422 423 if (EHCI_HCC_64BIT(cparams)) { 424 /* MUST clear segment register if 64 bit capable. */ 425 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 426 } 427 428 sc->sc_bus.ub_revision = USBREV_2_0; 429 sc->sc_bus.ub_usedma = true; 430 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 431 432 /* Reset the controller */ 433 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 434 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 435 usb_delay_ms(&sc->sc_bus, 1); 436 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 437 for (i = 0; i < 100; i++) { 438 usb_delay_ms(&sc->sc_bus, 1); 439 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 440 if (!hcr) 441 break; 442 } 443 if (hcr) { 444 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 445 return EIO; 446 } 447 if (sc->sc_vendor_init) 448 sc->sc_vendor_init(sc); 449 450 /* 451 * If we are doing embedded transaction translation function, force 452 * the controller to host mode. 453 */ 454 if (sc->sc_flags & EHCIF_ETTF) { 455 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 456 usbmode &= ~EHCI_USBMODE_CM; 457 usbmode |= EHCI_USBMODE_CM_HOST; 458 EWRITE4(sc, EHCI_USBMODE, usbmode); 459 } 460 461 /* XXX need proper intr scheduling */ 462 sc->sc_rand = 96; 463 464 /* frame list size at default, read back what we got and use that */ 465 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 466 case 0: sc->sc_flsize = 1024; break; 467 case 1: sc->sc_flsize = 512; break; 468 case 2: sc->sc_flsize = 256; break; 469 case 3: return EIO; 470 } 471 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 472 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 473 if (err) 474 return err; 475 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 476 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 477 478 for (i = 0; i < sc->sc_flsize; i++) { 479 sc->sc_flist[i] = EHCI_NULL; 480 } 481 482 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 483 484 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 485 KM_SLEEP); 486 if (sc->sc_softitds == NULL) 487 return ENOMEM; 488 LIST_INIT(&sc->sc_freeitds); 489 LIST_INIT(&sc->sc_freesitds); 490 TAILQ_INIT(&sc->sc_intrhead); 491 492 /* Set up the bus struct. */ 493 sc->sc_bus.ub_methods = &ehci_bus_methods; 494 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 495 496 sc->sc_eintrs = EHCI_NORMAL_INTRS; 497 498 /* 499 * Allocate the interrupt dummy QHs. These are arranged to give poll 500 * intervals that are powers of 2 times 1ms. 501 */ 502 for (i = 0; i < EHCI_INTRQHS; i++) { 503 sqh = ehci_alloc_sqh(sc); 504 if (sqh == NULL) { 505 err = ENOMEM; 506 goto bad1; 507 } 508 sc->sc_islots[i].sqh = sqh; 509 } 510 for (i = 0; i < EHCI_INTRQHS; i++) { 511 sqh = sc->sc_islots[i].sqh; 512 if (i == 0) { 513 /* The last (1ms) QH terminates. */ 514 sqh->qh.qh_link = EHCI_NULL; 515 sqh->next = NULL; 516 } else { 517 /* Otherwise the next QH has half the poll interval */ 518 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 519 sqh->qh.qh_link = htole32(sqh->next->physaddr | 520 EHCI_LINK_QH); 521 } 522 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 523 sqh->qh.qh_curqtd = EHCI_NULL; 524 sqh->next = NULL; 525 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 526 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 527 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 528 sqh->sqtd = NULL; 529 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 530 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 531 } 532 /* Point the frame list at the last level (128ms). */ 533 for (i = 0; i < sc->sc_flsize; i++) { 534 int j; 535 536 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 537 revbits[i & (EHCI_MAX_POLLRATE-1)]; 538 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 539 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 540 i)].sqh->physaddr); 541 } 542 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 543 BUS_DMASYNC_PREWRITE); 544 545 /* Allocate dummy QH that starts the async list. */ 546 sqh = ehci_alloc_sqh(sc); 547 if (sqh == NULL) { 548 err = ENOMEM; 549 goto bad1; 550 } 551 /* Fill the QH */ 552 sqh->qh.qh_endp = 553 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 554 sqh->qh.qh_link = 555 htole32(sqh->physaddr | EHCI_LINK_QH); 556 sqh->qh.qh_curqtd = EHCI_NULL; 557 sqh->next = NULL; 558 /* Fill the overlay qTD */ 559 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 560 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 561 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 562 sqh->sqtd = NULL; 563 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 564 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 565 #ifdef EHCI_DEBUG 566 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 567 ehci_dump_sqh(sqh); 568 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 569 #endif 570 571 /* Point to async list */ 572 sc->sc_async_head = sqh; 573 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 574 575 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 576 577 /* Turn on controller */ 578 EOWRITE4(sc, EHCI_USBCMD, 579 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 580 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 581 EHCI_CMD_ASE | 582 EHCI_CMD_PSE | 583 EHCI_CMD_RS); 584 585 /* Take over port ownership */ 586 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 587 588 for (i = 0; i < 100; i++) { 589 usb_delay_ms(&sc->sc_bus, 1); 590 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 591 if (!hcr) 592 break; 593 } 594 if (hcr) { 595 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 596 return EIO; 597 } 598 599 /* Enable interrupts */ 600 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 601 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 602 603 return 0; 604 605 #if 0 606 bad2: 607 ehci_free_sqh(sc, sc->sc_async_head); 608 #endif 609 bad1: 610 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 611 return err; 612 } 613 614 int 615 ehci_intr(void *v) 616 { 617 ehci_softc_t *sc = v; 618 int ret = 0; 619 620 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 621 622 if (sc == NULL) 623 return 0; 624 625 mutex_spin_enter(&sc->sc_intr_lock); 626 627 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 628 goto done; 629 630 /* If we get an interrupt while polling, then just ignore it. */ 631 if (sc->sc_bus.ub_usepolling) { 632 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 633 634 if (intrs) 635 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 636 USBHIST_LOGN(ehcidebug, 16, 637 "ignored interrupt while polling", 0, 0, 0, 0); 638 goto done; 639 } 640 641 ret = ehci_intr1(sc); 642 643 done: 644 mutex_spin_exit(&sc->sc_intr_lock); 645 return ret; 646 } 647 648 Static int 649 ehci_intr1(ehci_softc_t *sc) 650 { 651 uint32_t intrs, eintrs; 652 653 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 654 655 /* In case the interrupt occurs before initialization has completed. */ 656 if (sc == NULL) { 657 #ifdef DIAGNOSTIC 658 printf("ehci_intr1: sc == NULL\n"); 659 #endif 660 return 0; 661 } 662 663 KASSERT(mutex_owned(&sc->sc_intr_lock)); 664 665 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 666 if (!intrs) 667 return 0; 668 669 eintrs = intrs & sc->sc_eintrs; 670 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 671 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 672 if (!eintrs) 673 return 0; 674 675 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 676 if (eintrs & EHCI_STS_IAA) { 677 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 678 kpreempt_disable(); 679 KASSERT(sc->sc_doorbell_si != NULL); 680 softint_schedule(sc->sc_doorbell_si); 681 kpreempt_enable(); 682 eintrs &= ~EHCI_STS_IAA; 683 } 684 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 685 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 686 eintrs & EHCI_STS_INT ? 1 : 0, 687 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 688 usb_schedsoftintr(&sc->sc_bus); 689 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 690 } 691 if (eintrs & EHCI_STS_HSE) { 692 printf("%s: unrecoverable error, controller halted\n", 693 device_xname(sc->sc_dev)); 694 /* XXX what else */ 695 } 696 if (eintrs & EHCI_STS_PCD) { 697 kpreempt_disable(); 698 KASSERT(sc->sc_pcd_si != NULL); 699 softint_schedule(sc->sc_pcd_si); 700 kpreempt_enable(); 701 eintrs &= ~EHCI_STS_PCD; 702 } 703 704 if (eintrs != 0) { 705 /* Block unprocessed interrupts. */ 706 sc->sc_eintrs &= ~eintrs; 707 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 708 printf("%s: blocking intrs 0x%x\n", 709 device_xname(sc->sc_dev), eintrs); 710 } 711 712 return 1; 713 } 714 715 Static void 716 ehci_doorbell(void *addr) 717 { 718 ehci_softc_t *sc = addr; 719 720 mutex_enter(&sc->sc_lock); 721 cv_broadcast(&sc->sc_doorbell); 722 mutex_exit(&sc->sc_lock); 723 } 724 725 Static void 726 ehci_pcd(void *addr) 727 { 728 ehci_softc_t *sc = addr; 729 usbd_xfer_handle xfer; 730 u_char *p; 731 int i, m; 732 733 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 734 735 mutex_enter(&sc->sc_lock); 736 xfer = sc->sc_intrxfer; 737 738 if (xfer == NULL) { 739 /* Just ignore the change. */ 740 goto done; 741 } 742 743 p = xfer->ux_buf; 744 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 745 memset(p, 0, xfer->ux_length); 746 for (i = 1; i <= m; i++) { 747 /* Pick out CHANGE bits from the status reg. */ 748 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 749 p[i/8] |= 1 << (i%8); 750 if (i % 8 == 7) 751 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 752 p[i/8], 0, 0); 753 } 754 xfer->ux_actlen = xfer->ux_length; 755 xfer->ux_status = USBD_NORMAL_COMPLETION; 756 757 usb_transfer_complete(xfer); 758 759 done: 760 mutex_exit(&sc->sc_lock); 761 } 762 763 Static void 764 ehci_softintr(void *v) 765 { 766 struct usbd_bus *bus = v; 767 ehci_softc_t *sc = bus->ub_hcpriv; 768 struct ehci_xfer *ex, *nextex; 769 770 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 771 772 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 773 774 /* 775 * The only explanation I can think of for why EHCI is as brain dead 776 * as UHCI interrupt-wise is that Intel was involved in both. 777 * An interrupt just tells us that something is done, we have no 778 * clue what, so we need to scan through all active transfers. :-( 779 */ 780 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 781 nextex = TAILQ_NEXT(ex, ex_next); 782 ehci_check_intr(sc, ex); 783 } 784 785 /* Schedule a callout to catch any dropped transactions. */ 786 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 787 !TAILQ_EMPTY(&sc->sc_intrhead)) 788 callout_reset(&sc->sc_tmo_intrlist, 789 hz, ehci_intrlist_timeout, sc); 790 791 if (sc->sc_softwake) { 792 sc->sc_softwake = 0; 793 cv_broadcast(&sc->sc_softwake_cv); 794 } 795 } 796 797 /* Check for an interrupt. */ 798 Static void 799 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 800 { 801 usbd_device_handle dev = ex->ex_xfer.ux_pipe->up_dev; 802 int attr; 803 804 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 805 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 806 807 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 808 809 attr = ex->ex_xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 810 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 811 if (dev->ud_speed == USB_SPEED_HIGH) 812 ehci_check_itd_intr(sc, ex); 813 else 814 ehci_check_sitd_intr(sc, ex); 815 } else 816 ehci_check_qh_intr(sc, ex); 817 818 return; 819 } 820 821 Static void 822 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 823 { 824 ehci_soft_qtd_t *sqtd, *lsqtd; 825 uint32_t status; 826 827 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 828 829 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 830 831 if (ex->ex_sqtdstart == NULL) { 832 printf("ehci_check_qh_intr: not valid sqtd\n"); 833 return; 834 } 835 836 lsqtd = ex->ex_sqtdend; 837 #ifdef DIAGNOSTIC 838 if (lsqtd == NULL) { 839 printf("ehci_check_qh_intr: lsqtd==0\n"); 840 return; 841 } 842 #endif 843 /* 844 * If the last TD is still active we need to check whether there 845 * is an error somewhere in the middle, or whether there was a 846 * short packet (SPD and not ACTIVE). 847 */ 848 usb_syncmem(&lsqtd->dma, 849 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 850 sizeof(lsqtd->qtd.qtd_status), 851 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 852 status = le32toh(lsqtd->qtd.qtd_status); 853 usb_syncmem(&lsqtd->dma, 854 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 855 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 856 if (status & EHCI_QTD_ACTIVE) { 857 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 858 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd; 859 sqtd = sqtd->nextqtd) { 860 usb_syncmem(&sqtd->dma, 861 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 862 sizeof(sqtd->qtd.qtd_status), 863 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 864 status = le32toh(sqtd->qtd.qtd_status); 865 usb_syncmem(&sqtd->dma, 866 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 867 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 868 /* If there's an active QTD the xfer isn't done. */ 869 if (status & EHCI_QTD_ACTIVE) 870 break; 871 /* Any kind of error makes the xfer done. */ 872 if (status & EHCI_QTD_HALTED) 873 goto done; 874 /* Handle short packets */ 875 if (EHCI_QTD_GET_BYTES(status) != 0) { 876 usbd_pipe_handle pipe = ex->ex_xfer.ux_pipe; 877 usb_endpoint_descriptor_t *ed = 878 pipe->up_endpoint->ue_edesc; 879 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 880 881 /* 882 * If we get here for a control transfer then 883 * we need to let the hardware complete the 884 * status phase. That is, we're not done 885 * quite yet. 886 * 887 * Otherwise, we're done. 888 */ 889 if (xt == UE_CONTROL) { 890 break; 891 } 892 goto done; 893 } 894 } 895 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 896 ex, ex->ex_sqtdstart, 0, 0); 897 #ifdef EHCI_DEBUG 898 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 0, 0); 899 ehci_dump_sqtds(ex->ex_sqtdstart); 900 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 0); 901 #endif 902 return; 903 } 904 done: 905 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 906 callout_stop(&ex->ex_xfer.ux_callout); 907 ehci_idone(ex); 908 } 909 910 Static void 911 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 912 { 913 ehci_soft_itd_t *itd; 914 int i; 915 916 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 917 918 KASSERT(mutex_owned(&sc->sc_lock)); 919 920 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 921 return; 922 923 if (ex->ex_itdstart == NULL) { 924 printf("ehci_check_itd_intr: not valid itd\n"); 925 return; 926 } 927 928 itd = ex->ex_itdend; 929 #ifdef DIAGNOSTIC 930 if (itd == NULL) { 931 printf("ehci_check_itd_intr: itdend == 0\n"); 932 return; 933 } 934 #endif 935 936 /* 937 * check no active transfers in last itd, meaning we're finished 938 */ 939 940 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 941 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 942 BUS_DMASYNC_POSTREAD); 943 944 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 945 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 946 break; 947 } 948 949 if (i == EHCI_ITD_NUFRAMES) { 950 goto done; /* All 8 descriptors inactive, it's done */ 951 } 952 953 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 954 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 955 956 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 957 ex->ex_itdstart, 0, 0); 958 return; 959 done: 960 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 961 callout_stop(&ex->ex_xfer.ux_callout); 962 ehci_idone(ex); 963 } 964 965 void 966 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 967 { 968 ehci_soft_sitd_t *sitd; 969 970 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 971 972 KASSERT(mutex_owned(&sc->sc_lock)); 973 974 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 975 return; 976 977 if (ex->ex_sitdstart == NULL) { 978 printf("ehci_check_sitd_intr: not valid sitd\n"); 979 return; 980 } 981 982 sitd = ex->ex_sitdend; 983 #ifdef DIAGNOSTIC 984 if (sitd == NULL) { 985 printf("ehci_check_sitd_intr: sitdend == 0\n"); 986 return; 987 } 988 #endif 989 990 /* 991 * check no active transfers in last sitd, meaning we're finished 992 */ 993 994 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 995 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_POSTWRITE | 996 BUS_DMASYNC_POSTREAD); 997 998 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 999 return; 1000 1001 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1002 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1003 1004 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 1005 callout_stop(&(ex->ex_xfer.ux_callout)); 1006 ehci_idone(ex); 1007 } 1008 1009 1010 Static void 1011 ehci_idone(struct ehci_xfer *ex) 1012 { 1013 usbd_xfer_handle xfer = &ex->ex_xfer; 1014 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1015 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1016 ehci_soft_qtd_t *sqtd, *lsqtd; 1017 uint32_t status = 0, nstatus = 0; 1018 int actlen; 1019 1020 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1021 1022 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1023 1024 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1025 1026 #ifdef DIAGNOSTIC 1027 #ifdef EHCI_DEBUG 1028 if (ex->ex_isdone) { 1029 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1030 ehci_dump_exfer(ex); 1031 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1032 } 1033 #endif 1034 KASSERT(!ex->ex_isdone); 1035 ex->ex_isdone = true; 1036 #endif 1037 1038 if (xfer->ux_status == USBD_CANCELLED || 1039 xfer->ux_status == USBD_TIMEOUT) { 1040 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1041 return; 1042 } 1043 1044 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1045 1046 /* The transfer is done, compute actual length and status. */ 1047 1048 u_int xfertype, speed; 1049 1050 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1051 speed = xfer->ux_pipe->up_dev->ud_speed; 1052 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1053 /* HS isoc transfer */ 1054 1055 struct ehci_soft_itd *itd; 1056 int i, nframes, len, uframes; 1057 1058 nframes = 0; 1059 actlen = 0; 1060 1061 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1062 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1063 1064 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1065 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1066 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1067 BUS_DMASYNC_POSTREAD); 1068 1069 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1070 /* 1071 * XXX - driver didn't fill in the frame full 1072 * of uframes. This leads to scheduling 1073 * inefficiencies, but working around 1074 * this doubles complexity of tracking 1075 * an xfer. 1076 */ 1077 if (nframes >= xfer->ux_nframes) 1078 break; 1079 1080 status = le32toh(itd->itd.itd_ctl[i]); 1081 len = EHCI_ITD_GET_LEN(status); 1082 if (EHCI_ITD_GET_STATUS(status) != 0) 1083 len = 0; /*No valid data on error*/ 1084 1085 xfer->ux_frlengths[nframes++] = len; 1086 actlen += len; 1087 } 1088 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1089 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1090 1091 if (nframes >= xfer->ux_nframes) 1092 break; 1093 } 1094 1095 xfer->ux_actlen = actlen; 1096 xfer->ux_status = USBD_NORMAL_COMPLETION; 1097 goto end; 1098 } 1099 1100 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1101 /* FS isoc transfer */ 1102 struct ehci_soft_sitd *sitd; 1103 int nframes, len; 1104 1105 nframes = 0; 1106 actlen = 0; 1107 1108 for (sitd = ex->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1109 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1110 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_POSTWRITE | 1111 BUS_DMASYNC_POSTREAD); 1112 1113 /* 1114 * XXX - driver didn't fill in the frame full 1115 * of uframes. This leads to scheduling 1116 * inefficiencies, but working around 1117 * this doubles complexity of tracking 1118 * an xfer. 1119 */ 1120 if (nframes >= xfer->ux_nframes) 1121 break; 1122 1123 status = le32toh(sitd->sitd.sitd_trans); 1124 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1125 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1126 1127 len = EHCI_SITD_GET_LEN(status); 1128 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1129 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1130 /* No valid data on error */ 1131 len = xfer->ux_frlengths[nframes]; 1132 } 1133 1134 /* 1135 * frlengths[i]: # of bytes to send 1136 * len: # of bytes host didn't send 1137 */ 1138 xfer->ux_frlengths[nframes] -= len; 1139 /* frlengths[i]: # of bytes host sent */ 1140 actlen += xfer->ux_frlengths[nframes++]; 1141 1142 if (nframes >= xfer->ux_nframes) 1143 break; 1144 } 1145 1146 xfer->ux_actlen = actlen; 1147 xfer->ux_status = USBD_NORMAL_COMPLETION; 1148 goto end; 1149 } 1150 KASSERT(xfertype != UE_ISOCHRONOUS); 1151 1152 /* Continue processing xfers using queue heads */ 1153 1154 #ifdef EHCI_DEBUG 1155 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1156 ehci_dump_sqtds(ex->ex_sqtdstart); 1157 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1158 #endif 1159 1160 lsqtd = ex->ex_sqtdend; 1161 actlen = 0; 1162 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd->nextqtd; 1163 sqtd = sqtd->nextqtd) { 1164 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1165 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1166 nstatus = le32toh(sqtd->qtd.qtd_status); 1167 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1168 BUS_DMASYNC_PREREAD); 1169 if (nstatus & EHCI_QTD_ACTIVE) 1170 break; 1171 1172 status = nstatus; 1173 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1174 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1175 } 1176 1177 1178 /* 1179 * If there are left over TDs we need to update the toggle. 1180 * The default pipe doesn't need it since control transfers 1181 * start the toggle at 0 every time. 1182 * For a short transfer we need to update the toggle for the missing 1183 * packets within the qTD. 1184 */ 1185 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1186 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1187 USBHIST_LOG(ehcidebug, 1188 "toggle update status=0x%08x nstatus=0x%08x", 1189 status, nstatus, 0, 0); 1190 #if 0 1191 ehci_dump_sqh(epipe->sqh); 1192 ehci_dump_sqtds(ex->ex_sqtdstart); 1193 #endif 1194 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1195 } 1196 1197 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1198 actlen, status, 0); 1199 xfer->ux_actlen = actlen; 1200 if (status & EHCI_QTD_HALTED) { 1201 #ifdef EHCI_DEBUG 1202 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1203 xfer->ux_pipe->up_dev->ud_addr, 1204 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1205 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1206 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1207 0, 0); 1208 USBHIST_LOG(ehcidebug, 1209 "active =%d halted=%d buferr=%d babble=%d", 1210 status & EHCI_QTD_ACTIVE ? 1 : 0, 1211 status & EHCI_QTD_HALTED ? 1 : 0, 1212 status & EHCI_QTD_BUFERR ? 1 : 0, 1213 status & EHCI_QTD_BABBLE ? 1 : 0); 1214 1215 USBHIST_LOG(ehcidebug, 1216 "xacterr=%d missed=%d split =%d ping =%d", 1217 status & EHCI_QTD_XACTERR ? 1 : 0, 1218 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1219 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1220 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1221 1222 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1223 ehci_dump_sqh(epipe->sqh); 1224 ehci_dump_sqtds(ex->ex_sqtdstart); 1225 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1226 #endif 1227 /* low&full speed has an extra error flag */ 1228 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1229 EHCI_QH_SPEED_HIGH) 1230 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1231 else 1232 status &= EHCI_QTD_STATERRS; 1233 if (status == 0) /* no other errors means a stall */ { 1234 xfer->ux_status = USBD_STALLED; 1235 } else { 1236 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1237 } 1238 /* XXX need to reset TT on missed microframe */ 1239 if (status & EHCI_QTD_MISSEDMICRO) { 1240 printf("%s: missed microframe, TT reset not " 1241 "implemented, hub might be inoperational\n", 1242 device_xname(sc->sc_dev)); 1243 } 1244 } else { 1245 xfer->ux_status = USBD_NORMAL_COMPLETION; 1246 } 1247 1248 end: 1249 /* 1250 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1251 * during this call, before methods->done is called: dma sync required 1252 * beforehand? 1253 */ 1254 usb_transfer_complete(xfer); 1255 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1256 } 1257 1258 /* 1259 * Wait here until controller claims to have an interrupt. 1260 * Then call ehci_intr and return. Use timeout to avoid waiting 1261 * too long. 1262 */ 1263 Static void 1264 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer) 1265 { 1266 int timo; 1267 uint32_t intrs; 1268 1269 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1270 1271 xfer->ux_status = USBD_IN_PROGRESS; 1272 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1273 usb_delay_ms(&sc->sc_bus, 1); 1274 if (sc->sc_dying) 1275 break; 1276 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1277 sc->sc_eintrs; 1278 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1279 #ifdef EHCI_DEBUG 1280 if (ehcidebug > 15) 1281 ehci_dump_regs(sc); 1282 #endif 1283 if (intrs) { 1284 mutex_spin_enter(&sc->sc_intr_lock); 1285 ehci_intr1(sc); 1286 mutex_spin_exit(&sc->sc_intr_lock); 1287 if (xfer->ux_status != USBD_IN_PROGRESS) 1288 return; 1289 } 1290 } 1291 1292 /* Timeout */ 1293 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1294 xfer->ux_status = USBD_TIMEOUT; 1295 mutex_enter(&sc->sc_lock); 1296 usb_transfer_complete(xfer); 1297 mutex_exit(&sc->sc_lock); 1298 /* XXX should free TD */ 1299 } 1300 1301 Static void 1302 ehci_poll(struct usbd_bus *bus) 1303 { 1304 ehci_softc_t *sc = bus->ub_hcpriv; 1305 1306 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1307 1308 #ifdef EHCI_DEBUG 1309 static int last; 1310 int new; 1311 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1312 if (new != last) { 1313 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1314 last = new; 1315 } 1316 #endif 1317 1318 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1319 mutex_spin_enter(&sc->sc_intr_lock); 1320 ehci_intr1(sc); 1321 mutex_spin_exit(&sc->sc_intr_lock); 1322 } 1323 } 1324 1325 void 1326 ehci_childdet(device_t self, device_t child) 1327 { 1328 struct ehci_softc *sc = device_private(self); 1329 1330 KASSERT(sc->sc_child == child); 1331 sc->sc_child = NULL; 1332 } 1333 1334 int 1335 ehci_detach(struct ehci_softc *sc, int flags) 1336 { 1337 int rv = 0; 1338 1339 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1340 1341 if (sc->sc_child != NULL) 1342 rv = config_detach(sc->sc_child, flags); 1343 1344 if (rv != 0) 1345 return rv; 1346 1347 callout_halt(&sc->sc_tmo_intrlist, NULL); 1348 callout_destroy(&sc->sc_tmo_intrlist); 1349 1350 /* XXX free other data structures XXX */ 1351 if (sc->sc_softitds) 1352 kmem_free(sc->sc_softitds, 1353 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1354 cv_destroy(&sc->sc_doorbell); 1355 cv_destroy(&sc->sc_softwake_cv); 1356 1357 #if 0 1358 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1359 1360 softint_disestablish(sc->sc_doorbell_si); 1361 softint_disestablish(sc->sc_pcd_si); 1362 1363 mutex_destroy(&sc->sc_lock); 1364 mutex_destroy(&sc->sc_intr_lock); 1365 #endif 1366 1367 pool_cache_destroy(sc->sc_xferpool); 1368 1369 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1370 1371 return rv; 1372 } 1373 1374 1375 int 1376 ehci_activate(device_t self, enum devact act) 1377 { 1378 struct ehci_softc *sc = device_private(self); 1379 1380 switch (act) { 1381 case DVACT_DEACTIVATE: 1382 sc->sc_dying = 1; 1383 return 0; 1384 default: 1385 return EOPNOTSUPP; 1386 } 1387 } 1388 1389 /* 1390 * Handle suspend/resume. 1391 * 1392 * We need to switch to polling mode here, because this routine is 1393 * called from an interrupt context. This is all right since we 1394 * are almost suspended anyway. 1395 * 1396 * Note that this power handler isn't to be registered directly; the 1397 * bus glue needs to call out to it. 1398 */ 1399 bool 1400 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1401 { 1402 ehci_softc_t *sc = device_private(dv); 1403 int i; 1404 uint32_t cmd, hcr; 1405 1406 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1407 1408 mutex_spin_enter(&sc->sc_intr_lock); 1409 sc->sc_bus.ub_usepolling++; 1410 mutex_spin_exit(&sc->sc_intr_lock); 1411 1412 for (i = 1; i <= sc->sc_noport; i++) { 1413 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1414 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1415 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1416 } 1417 1418 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1419 1420 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1421 EOWRITE4(sc, EHCI_USBCMD, cmd); 1422 1423 for (i = 0; i < 100; i++) { 1424 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1425 if (hcr == 0) 1426 break; 1427 1428 usb_delay_ms(&sc->sc_bus, 1); 1429 } 1430 if (hcr != 0) 1431 printf("%s: reset timeout\n", device_xname(dv)); 1432 1433 cmd &= ~EHCI_CMD_RS; 1434 EOWRITE4(sc, EHCI_USBCMD, cmd); 1435 1436 for (i = 0; i < 100; i++) { 1437 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1438 if (hcr == EHCI_STS_HCH) 1439 break; 1440 1441 usb_delay_ms(&sc->sc_bus, 1); 1442 } 1443 if (hcr != EHCI_STS_HCH) 1444 printf("%s: config timeout\n", device_xname(dv)); 1445 1446 mutex_spin_enter(&sc->sc_intr_lock); 1447 sc->sc_bus.ub_usepolling--; 1448 mutex_spin_exit(&sc->sc_intr_lock); 1449 1450 return true; 1451 } 1452 1453 bool 1454 ehci_resume(device_t dv, const pmf_qual_t *qual) 1455 { 1456 ehci_softc_t *sc = device_private(dv); 1457 int i; 1458 uint32_t cmd, hcr; 1459 1460 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1461 1462 /* restore things in case the bios sucks */ 1463 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1464 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1465 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1466 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1467 1468 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1469 1470 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1471 1472 hcr = 0; 1473 for (i = 1; i <= sc->sc_noport; i++) { 1474 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1475 if ((cmd & EHCI_PS_PO) == 0 && 1476 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1477 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1478 hcr = 1; 1479 } 1480 } 1481 1482 if (hcr) { 1483 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1484 1485 for (i = 1; i <= sc->sc_noport; i++) { 1486 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1487 if ((cmd & EHCI_PS_PO) == 0 && 1488 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1489 EOWRITE4(sc, EHCI_PORTSC(i), 1490 cmd & ~EHCI_PS_FPR); 1491 } 1492 } 1493 1494 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1495 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1496 1497 for (i = 0; i < 100; i++) { 1498 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1499 if (hcr != EHCI_STS_HCH) 1500 break; 1501 1502 usb_delay_ms(&sc->sc_bus, 1); 1503 } 1504 if (hcr == EHCI_STS_HCH) 1505 printf("%s: config timeout\n", device_xname(dv)); 1506 1507 return true; 1508 } 1509 1510 /* 1511 * Shut down the controller when the system is going down. 1512 */ 1513 bool 1514 ehci_shutdown(device_t self, int flags) 1515 { 1516 ehci_softc_t *sc = device_private(self); 1517 1518 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1519 1520 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1521 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1522 return true; 1523 } 1524 1525 Static usbd_xfer_handle 1526 ehci_allocx(struct usbd_bus *bus) 1527 { 1528 struct ehci_softc *sc = bus->ub_hcpriv; 1529 usbd_xfer_handle xfer; 1530 1531 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1532 if (xfer != NULL) { 1533 memset(xfer, 0, sizeof(struct ehci_xfer)); 1534 #ifdef DIAGNOSTIC 1535 EXFER(xfer)->ex_isdone = true; 1536 xfer->ux_state = XFER_BUSY; 1537 #endif 1538 } 1539 return xfer; 1540 } 1541 1542 Static void 1543 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer) 1544 { 1545 struct ehci_softc *sc = bus->ub_hcpriv; 1546 1547 KASSERT(xfer->ux_state == XFER_BUSY); 1548 KASSERT(EXFER(xfer)->ex_isdone); 1549 #ifdef DIAGNOSTIC 1550 xfer->ux_state = XFER_FREE; 1551 #endif 1552 pool_cache_put(sc->sc_xferpool, xfer); 1553 } 1554 1555 Static void 1556 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1557 { 1558 struct ehci_softc *sc = bus->ub_hcpriv; 1559 1560 *lock = &sc->sc_lock; 1561 } 1562 1563 Static void 1564 ehci_device_clear_toggle(usbd_pipe_handle pipe) 1565 { 1566 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1567 1568 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1569 1570 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1571 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1572 #ifdef EHCI_DEBUG 1573 if (ehcidebug) 1574 usbd_dump_pipe(pipe); 1575 #endif 1576 epipe->nexttoggle = 0; 1577 } 1578 1579 Static void 1580 ehci_noop(usbd_pipe_handle pipe) 1581 { 1582 } 1583 1584 #ifdef EHCI_DEBUG 1585 /* 1586 * Unused function - this is meant to be called from a kernel 1587 * debugger. 1588 */ 1589 void 1590 ehci_dump(void) 1591 { 1592 ehci_softc_t *sc = theehci; 1593 int i; 1594 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1595 EOREAD4(sc, EHCI_USBCMD), 1596 EOREAD4(sc, EHCI_USBSTS), 1597 EOREAD4(sc, EHCI_USBINTR)); 1598 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1599 EOREAD4(sc, EHCI_FRINDEX), 1600 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1601 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1602 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1603 for (i = 1; i <= sc->sc_noport; i++) 1604 printf("port %d status=0x%08x\n", i, 1605 EOREAD4(sc, EHCI_PORTSC(i))); 1606 } 1607 1608 Static void 1609 ehci_dump_regs(ehci_softc_t *sc) 1610 { 1611 int i; 1612 1613 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1614 1615 USBHIST_LOG(ehcidebug, 1616 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1617 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1618 EOREAD4(sc, EHCI_USBINTR), 0); 1619 USBHIST_LOG(ehcidebug, 1620 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1621 "async = 0x%08x", 1622 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1623 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1624 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1625 for (i = 1; i <= sc->sc_noport; i += 2) { 1626 if (i == sc->sc_noport) { 1627 USBHIST_LOG(ehcidebug, 1628 "port %d status = 0x%08x", i, 1629 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1630 } else { 1631 USBHIST_LOG(ehcidebug, 1632 "port %d status = 0x%08x port %d status = 0x%08x", 1633 i, EOREAD4(sc, EHCI_PORTSC(i)), 1634 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1635 } 1636 } 1637 } 1638 1639 #ifdef EHCI_DEBUG 1640 #define ehci_dump_link(link, type) do { \ 1641 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1642 link, \ 1643 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1644 if (type) { \ 1645 USBHIST_LOG(ehcidebug, \ 1646 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1647 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1648 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1649 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1650 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1651 } \ 1652 } while(0) 1653 #else 1654 #define ehci_dump_link(link, type) 1655 #endif 1656 1657 Static void 1658 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1659 { 1660 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1661 int i; 1662 uint32_t stop = 0; 1663 1664 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1665 ehci_dump_sqtd(sqtd); 1666 usb_syncmem(&sqtd->dma, 1667 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1668 sizeof(sqtd->qtd), 1669 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1670 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1671 usb_syncmem(&sqtd->dma, 1672 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1673 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1674 } 1675 if (!stop) 1676 USBHIST_LOG(ehcidebug, 1677 "dump aborted, too many TDs", 0, 0, 0, 0); 1678 } 1679 1680 Static void 1681 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1682 { 1683 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1684 1685 usb_syncmem(&sqtd->dma, sqtd->offs, 1686 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1687 1688 USBHIST_LOGN(ehcidebug, 10, 1689 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1690 ehci_dump_qtd(&sqtd->qtd); 1691 1692 usb_syncmem(&sqtd->dma, sqtd->offs, 1693 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1694 } 1695 1696 Static void 1697 ehci_dump_qtd(ehci_qtd_t *qtd) 1698 { 1699 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1700 1701 #ifdef USBHIST 1702 uint32_t s = le32toh(qtd->qtd_status); 1703 #endif 1704 1705 USBHIST_LOGN(ehcidebug, 10, 1706 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1707 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1708 USBHIST_LOGN(ehcidebug, 10, 1709 " toggle = %d ioc = %d bytes = %#x " 1710 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1711 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1712 USBHIST_LOGN(ehcidebug, 10, 1713 " cerr = %d pid = %d stat = %x", 1714 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1715 0); 1716 USBHIST_LOGN(ehcidebug, 10, 1717 "active =%d halted=%d buferr=%d babble=%d", 1718 s & EHCI_QTD_ACTIVE ? 1 : 0, 1719 s & EHCI_QTD_HALTED ? 1 : 0, 1720 s & EHCI_QTD_BUFERR ? 1 : 0, 1721 s & EHCI_QTD_BABBLE ? 1 : 0); 1722 USBHIST_LOGN(ehcidebug, 10, 1723 "xacterr=%d missed=%d split =%d ping =%d", 1724 s & EHCI_QTD_XACTERR ? 1 : 0, 1725 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1726 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1727 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1728 USBHIST_LOGN(ehcidebug, 10, 1729 "buffer[0] = %#x buffer[1] = %#x " 1730 "buffer[2] = %#x buffer[3] = %#x", 1731 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1732 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1733 USBHIST_LOGN(ehcidebug, 10, 1734 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1735 } 1736 1737 Static void 1738 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1739 { 1740 #ifdef USBHIST 1741 ehci_qh_t *qh = &sqh->qh; 1742 ehci_link_t link; 1743 #endif 1744 uint32_t endp, endphub; 1745 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1746 1747 usb_syncmem(&sqh->dma, sqh->offs, 1748 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1749 1750 USBHIST_LOGN(ehcidebug, 10, 1751 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1752 link = le32toh(qh->qh_link); 1753 ehci_dump_link(link, true); 1754 1755 endp = le32toh(qh->qh_endp); 1756 USBHIST_LOGN(ehcidebug, 10, 1757 " endp = %#x", endp, 0, 0, 0); 1758 USBHIST_LOGN(ehcidebug, 10, 1759 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1760 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1761 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1762 USBHIST_LOGN(ehcidebug, 10, 1763 " dtc = %d hrecl = %d", 1764 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1765 USBHIST_LOGN(ehcidebug, 10, 1766 " ctl = %d nrl = %d mpl = %#x(%d)", 1767 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1768 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1769 1770 endphub = le32toh(qh->qh_endphub); 1771 USBHIST_LOGN(ehcidebug, 10, 1772 " endphub = %#x", endphub, 0, 0, 0); 1773 USBHIST_LOGN(ehcidebug, 10, 1774 " smask = 0x%02x cmask = 0x%02x", 1775 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1776 USBHIST_LOGN(ehcidebug, 10, 1777 " huba = 0x%02x port = %d mult = %d", 1778 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1779 EHCI_QH_GET_MULT(endphub), 0); 1780 1781 link = le32toh(qh->qh_curqtd); 1782 ehci_dump_link(link, false); 1783 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1784 ehci_dump_qtd(&qh->qh_qtd); 1785 1786 usb_syncmem(&sqh->dma, sqh->offs, 1787 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1788 } 1789 1790 Static void 1791 ehci_dump_itd(struct ehci_soft_itd *itd) 1792 { 1793 ehci_isoc_trans_t t; 1794 ehci_isoc_bufr_ptr_t b, b2, b3; 1795 int i; 1796 1797 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1798 1799 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1800 0, 0); 1801 1802 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1803 t = le32toh(itd->itd.itd_ctl[i]); 1804 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1805 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1806 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1807 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1808 EHCI_ITD_GET_OFFS(t), 0); 1809 } 1810 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1811 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1812 USBHIST_LOG(ehcidebug, " %x", 1813 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1814 1815 b = le32toh(itd->itd.itd_bufr[0]); 1816 b2 = le32toh(itd->itd.itd_bufr[1]); 1817 b3 = le32toh(itd->itd.itd_bufr[2]); 1818 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1819 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1820 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1821 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1822 } 1823 1824 Static void 1825 ehci_dump_sitd(struct ehci_soft_itd *itd) 1826 { 1827 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1828 1829 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1830 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1831 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1832 itd->xfer_next, itd->physaddr, itd->slot, 0); 1833 } 1834 1835 Static void 1836 ehci_dump_exfer(struct ehci_xfer *ex) 1837 { 1838 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1839 1840 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1841 ex, ex->ex_sqtdstart, ex->ex_sqtdend, 0); 1842 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1843 ex->ex_itdstart, ex->ex_itdend, ex->ex_isdone, 0); 1844 } 1845 #endif 1846 1847 Static usbd_status 1848 ehci_open(usbd_pipe_handle pipe) 1849 { 1850 usbd_device_handle dev = pipe->up_dev; 1851 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1852 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1853 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1854 uint8_t addr = dev->ud_addr; 1855 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1856 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1857 ehci_soft_qh_t *sqh; 1858 usbd_status err; 1859 int ival, speed, naks; 1860 int hshubaddr, hshubport; 1861 1862 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1863 1864 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1865 pipe, addr, ed->bEndpointAddress, rhaddr); 1866 1867 if (dev->ud_myhsport) { 1868 /* 1869 * When directly attached FS/LS device while doing embedded 1870 * transaction translations and we are the hub, set the hub 1871 * address to 0 (us). 1872 */ 1873 if (!(sc->sc_flags & EHCIF_ETTF) 1874 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1875 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1876 } else { 1877 hshubaddr = 0; 1878 } 1879 hshubport = dev->ud_myhsport->up_portno; 1880 } else { 1881 hshubaddr = 0; 1882 hshubport = 0; 1883 } 1884 1885 if (sc->sc_dying) 1886 return USBD_IOERROR; 1887 1888 /* toggle state needed for bulk endpoints */ 1889 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1890 1891 if (addr == rhaddr) { 1892 switch (ed->bEndpointAddress) { 1893 case USB_CONTROL_ENDPOINT: 1894 pipe->up_methods = &roothub_ctrl_methods; 1895 break; 1896 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1897 pipe->up_methods = &ehci_root_intr_methods; 1898 break; 1899 default: 1900 USBHIST_LOG(ehcidebug, 1901 "bad bEndpointAddress 0x%02x", 1902 ed->bEndpointAddress, 0, 0, 0); 1903 return USBD_INVAL; 1904 } 1905 return USBD_NORMAL_COMPLETION; 1906 } 1907 1908 /* XXX All this stuff is only valid for async. */ 1909 switch (dev->ud_speed) { 1910 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1911 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1912 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1913 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1914 } 1915 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1916 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1917 hshubaddr, hshubport, 0, 0); 1918 return USBD_INVAL; 1919 } 1920 1921 /* 1922 * For interrupt transfer, nak throttling must be disabled, but for 1923 * the other transfer type, nak throttling should be enabled from the 1924 * viewpoint that avoids the memory thrashing. 1925 */ 1926 naks = (xfertype == UE_INTERRUPT) ? 0 1927 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1928 1929 /* Allocate sqh for everything, save isoc xfers */ 1930 if (xfertype != UE_ISOCHRONOUS) { 1931 sqh = ehci_alloc_sqh(sc); 1932 if (sqh == NULL) 1933 return USBD_NOMEM; 1934 /* qh_link filled when the QH is added */ 1935 sqh->qh.qh_endp = htole32( 1936 EHCI_QH_SET_ADDR(addr) | 1937 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1938 EHCI_QH_SET_EPS(speed) | 1939 EHCI_QH_DTC | 1940 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1941 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1942 EHCI_QH_CTL : 0) | 1943 EHCI_QH_SET_NRL(naks) 1944 ); 1945 sqh->qh.qh_endphub = htole32( 1946 EHCI_QH_SET_MULT(1) | 1947 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1948 ); 1949 if (speed != EHCI_QH_SPEED_HIGH) 1950 sqh->qh.qh_endphub |= htole32( 1951 EHCI_QH_SET_PORT(hshubport) | 1952 EHCI_QH_SET_HUBA(hshubaddr) | 1953 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1954 ); 1955 sqh->qh.qh_curqtd = EHCI_NULL; 1956 /* Fill the overlay qTD */ 1957 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1958 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1959 sqh->qh.qh_qtd.qtd_status = htole32(0); 1960 1961 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1962 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1963 epipe->sqh = sqh; 1964 } else { 1965 sqh = NULL; 1966 } /*xfertype == UE_ISOC*/ 1967 1968 switch (xfertype) { 1969 case UE_CONTROL: 1970 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1971 0, &epipe->u.ctl.reqdma); 1972 #ifdef EHCI_DEBUG 1973 if (err) 1974 printf("ehci_open: usb_allocmem()=%d\n", err); 1975 #endif 1976 if (err) 1977 goto bad; 1978 pipe->up_methods = &ehci_device_ctrl_methods; 1979 mutex_enter(&sc->sc_lock); 1980 ehci_add_qh(sc, sqh, sc->sc_async_head); 1981 mutex_exit(&sc->sc_lock); 1982 break; 1983 case UE_BULK: 1984 pipe->up_methods = &ehci_device_bulk_methods; 1985 mutex_enter(&sc->sc_lock); 1986 ehci_add_qh(sc, sqh, sc->sc_async_head); 1987 mutex_exit(&sc->sc_lock); 1988 break; 1989 case UE_INTERRUPT: 1990 pipe->up_methods = &ehci_device_intr_methods; 1991 ival = pipe->up_interval; 1992 if (ival == USBD_DEFAULT_INTERVAL) { 1993 if (speed == EHCI_QH_SPEED_HIGH) { 1994 if (ed->bInterval > 16) { 1995 /* 1996 * illegal with high-speed, but there 1997 * were documentation bugs in the spec, 1998 * so be generous 1999 */ 2000 ival = 256; 2001 } else 2002 ival = (1 << (ed->bInterval - 1)) / 8; 2003 } else 2004 ival = ed->bInterval; 2005 } 2006 err = ehci_device_setintr(sc, sqh, ival); 2007 if (err) 2008 goto bad; 2009 break; 2010 case UE_ISOCHRONOUS: 2011 if (speed == EHCI_QH_SPEED_HIGH) 2012 pipe->up_methods = &ehci_device_isoc_methods; 2013 else 2014 pipe->up_methods = &ehci_device_fs_isoc_methods; 2015 if (ed->bInterval == 0 || ed->bInterval > 16) { 2016 printf("ehci: opening pipe with invalid bInterval\n"); 2017 err = USBD_INVAL; 2018 goto bad; 2019 } 2020 if (UGETW(ed->wMaxPacketSize) == 0) { 2021 printf("ehci: zero length endpoint open request\n"); 2022 err = USBD_INVAL; 2023 goto bad; 2024 } 2025 epipe->u.isoc.next_frame = 0; 2026 epipe->u.isoc.cur_xfers = 0; 2027 break; 2028 default: 2029 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2030 err = USBD_INVAL; 2031 goto bad; 2032 } 2033 return USBD_NORMAL_COMPLETION; 2034 2035 bad: 2036 if (sqh != NULL) 2037 ehci_free_sqh(sc, sqh); 2038 return err; 2039 } 2040 2041 /* 2042 * Add an ED to the schedule. Called with USB lock held. 2043 */ 2044 Static void 2045 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2046 { 2047 2048 KASSERT(mutex_owned(&sc->sc_lock)); 2049 2050 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2051 2052 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2053 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2054 2055 sqh->next = head->next; 2056 sqh->qh.qh_link = head->qh.qh_link; 2057 2058 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2059 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2060 2061 head->next = sqh; 2062 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2063 2064 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2065 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2066 2067 #ifdef EHCI_DEBUG 2068 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2069 ehci_dump_sqh(sqh); 2070 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2071 #endif 2072 } 2073 2074 /* 2075 * Remove an ED from the schedule. Called with USB lock held. 2076 */ 2077 Static void 2078 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2079 { 2080 ehci_soft_qh_t *p; 2081 2082 KASSERT(mutex_owned(&sc->sc_lock)); 2083 2084 /* XXX */ 2085 for (p = head; p != NULL && p->next != sqh; p = p->next) 2086 ; 2087 if (p == NULL) 2088 panic("ehci_rem_qh: ED not found"); 2089 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2090 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2091 p->next = sqh->next; 2092 p->qh.qh_link = sqh->qh.qh_link; 2093 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2094 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2095 2096 ehci_sync_hc(sc); 2097 } 2098 2099 Static void 2100 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2101 { 2102 int i; 2103 uint32_t status; 2104 2105 /* Save toggle bit and ping status. */ 2106 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2107 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2108 status = sqh->qh.qh_qtd.qtd_status & 2109 htole32(EHCI_QTD_TOGGLE_MASK | 2110 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2111 /* Set HALTED to make hw leave it alone. */ 2112 sqh->qh.qh_qtd.qtd_status = 2113 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2114 usb_syncmem(&sqh->dma, 2115 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2116 sizeof(sqh->qh.qh_qtd.qtd_status), 2117 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2118 sqh->qh.qh_curqtd = 0; 2119 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2120 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2121 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2122 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2123 sqh->sqtd = sqtd; 2124 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2125 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2126 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2127 sqh->qh.qh_qtd.qtd_status = status; 2128 usb_syncmem(&sqh->dma, 2129 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2130 sizeof(sqh->qh.qh_qtd.qtd_status), 2131 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2132 } 2133 2134 /* 2135 * Ensure that the HC has released all references to the QH. We do this 2136 * by asking for a Async Advance Doorbell interrupt and then we wait for 2137 * the interrupt. 2138 * To make this easier we first obtain exclusive use of the doorbell. 2139 */ 2140 Static void 2141 ehci_sync_hc(ehci_softc_t *sc) 2142 { 2143 int error __diagused; 2144 2145 KASSERT(mutex_owned(&sc->sc_lock)); 2146 2147 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2148 2149 if (sc->sc_dying) { 2150 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2151 return; 2152 } 2153 /* ask for doorbell */ 2154 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2155 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2156 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2157 2158 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2159 2160 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2161 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2162 #ifdef DIAGNOSTIC 2163 if (error) 2164 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2165 #endif 2166 } 2167 2168 Static void 2169 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2170 { 2171 struct ehci_soft_itd *itd, *prev; 2172 2173 prev = NULL; 2174 2175 if (exfer->ex_itdstart == NULL || exfer->ex_itdend == NULL) 2176 panic("ehci isoc xfer being freed, but with no itd chain\n"); 2177 2178 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2179 prev = itd->u.frame_list.prev; 2180 /* Unlink itd from hardware chain, or frame array */ 2181 if (prev == NULL) { /* We're at the table head */ 2182 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2183 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2184 usb_syncmem(&sc->sc_fldma, 2185 sizeof(ehci_link_t) * itd->slot, 2186 sizeof(ehci_link_t), 2187 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2188 2189 if (itd->u.frame_list.next != NULL) 2190 itd->u.frame_list.next->u.frame_list.prev = NULL; 2191 } else { 2192 /* XXX this part is untested... */ 2193 prev->itd.itd_next = itd->itd.itd_next; 2194 usb_syncmem(&itd->dma, 2195 itd->offs + offsetof(ehci_itd_t, itd_next), 2196 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2197 2198 prev->u.frame_list.next = itd->u.frame_list.next; 2199 if (itd->u.frame_list.next != NULL) 2200 itd->u.frame_list.next->u.frame_list.prev = prev; 2201 } 2202 } 2203 2204 prev = NULL; 2205 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2206 if (prev != NULL) 2207 ehci_free_itd(sc, prev); 2208 prev = itd; 2209 } 2210 if (prev) 2211 ehci_free_itd(sc, prev); 2212 exfer->ex_itdstart = NULL; 2213 exfer->ex_itdend = NULL; 2214 } 2215 2216 Static void 2217 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2218 { 2219 struct ehci_soft_sitd *sitd, *prev; 2220 2221 prev = NULL; 2222 2223 if (exfer->ex_sitdstart == NULL || exfer->ex_sitdend == NULL) 2224 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2225 2226 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2227 prev = sitd->u.frame_list.prev; 2228 /* Unlink sitd from hardware chain, or frame array */ 2229 if (prev == NULL) { /* We're at the table head */ 2230 sc->sc_softsitds[sitd->slot] = sitd->u.frame_list.next; 2231 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2232 usb_syncmem(&sc->sc_fldma, 2233 sizeof(ehci_link_t) * sitd->slot, 2234 sizeof(ehci_link_t), 2235 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2236 2237 if (sitd->u.frame_list.next != NULL) 2238 sitd->u.frame_list.next->u.frame_list.prev = NULL; 2239 } else { 2240 /* XXX this part is untested... */ 2241 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2242 usb_syncmem(&sitd->dma, 2243 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2244 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2245 2246 prev->u.frame_list.next = sitd->u.frame_list.next; 2247 if (sitd->u.frame_list.next != NULL) 2248 sitd->u.frame_list.next->u.frame_list.prev = prev; 2249 } 2250 } 2251 2252 prev = NULL; 2253 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2254 if (prev != NULL) 2255 ehci_free_sitd(sc, prev); 2256 prev = sitd; 2257 } 2258 if (prev) 2259 ehci_free_sitd(sc, prev); 2260 exfer->ex_sitdstart = NULL; 2261 exfer->ex_sitdend = NULL; 2262 } 2263 2264 /***********/ 2265 2266 Static int 2267 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2268 void *buf, int buflen) 2269 { 2270 ehci_softc_t *sc = bus->ub_hcpriv; 2271 usb_hub_descriptor_t hubd; 2272 usb_port_status_t ps; 2273 uint16_t len, value, index; 2274 int l, totlen = 0; 2275 int port, i; 2276 uint32_t v; 2277 2278 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2279 2280 if (sc->sc_dying) 2281 return -1; 2282 2283 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2284 req->bmRequestType, req->bRequest, 0, 0); 2285 2286 len = UGETW(req->wLength); 2287 value = UGETW(req->wValue); 2288 index = UGETW(req->wIndex); 2289 2290 #define C(x,y) ((x) | ((y) << 8)) 2291 switch (C(req->bRequest, req->bmRequestType)) { 2292 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2293 if (len == 0) 2294 break; 2295 switch (value) { 2296 case C(0, UDESC_DEVICE): { 2297 usb_device_descriptor_t devd; 2298 totlen = min(buflen, sizeof(devd)); 2299 memcpy(&devd, buf, totlen); 2300 USETW(devd.idVendor, sc->sc_id_vendor); 2301 memcpy(buf, &devd, totlen); 2302 break; 2303 2304 } 2305 #define sd ((usb_string_descriptor_t *)buf) 2306 case C(1, UDESC_STRING): 2307 /* Vendor */ 2308 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2309 break; 2310 case C(2, UDESC_STRING): 2311 /* Product */ 2312 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2313 break; 2314 #undef sd 2315 default: 2316 /* default from usbroothub */ 2317 return buflen; 2318 } 2319 break; 2320 2321 /* Hub requests */ 2322 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2323 break; 2324 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2325 USBHIST_LOG(ehcidebug, 2326 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2327 0, 0); 2328 if (index < 1 || index > sc->sc_noport) { 2329 return -1; 2330 } 2331 port = EHCI_PORTSC(index); 2332 v = EOREAD4(sc, port); 2333 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2334 v &= ~EHCI_PS_CLEAR; 2335 switch (value) { 2336 case UHF_PORT_ENABLE: 2337 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2338 break; 2339 case UHF_PORT_SUSPEND: 2340 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2341 break; 2342 v &= ~EHCI_PS_SUSP; 2343 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2344 /* see USB2 spec ch. 7.1.7.7 */ 2345 usb_delay_ms(&sc->sc_bus, 20); 2346 EOWRITE4(sc, port, v); 2347 usb_delay_ms(&sc->sc_bus, 2); 2348 #ifdef DEBUG 2349 v = EOREAD4(sc, port); 2350 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2351 printf("ehci: resume failed: %x\n", v); 2352 #endif 2353 break; 2354 case UHF_PORT_POWER: 2355 if (sc->sc_hasppc) 2356 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2357 break; 2358 case UHF_PORT_TEST: 2359 USBHIST_LOG(ehcidebug, "clear port test " 2360 "%d", index, 0, 0, 0); 2361 break; 2362 case UHF_PORT_INDICATOR: 2363 USBHIST_LOG(ehcidebug, "clear port ind " 2364 "%d", index, 0, 0, 0); 2365 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2366 break; 2367 case UHF_C_PORT_CONNECTION: 2368 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2369 break; 2370 case UHF_C_PORT_ENABLE: 2371 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2372 break; 2373 case UHF_C_PORT_SUSPEND: 2374 /* how? */ 2375 break; 2376 case UHF_C_PORT_OVER_CURRENT: 2377 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2378 break; 2379 case UHF_C_PORT_RESET: 2380 sc->sc_isreset[index] = 0; 2381 break; 2382 default: 2383 return -1; 2384 } 2385 #if 0 2386 switch(value) { 2387 case UHF_C_PORT_CONNECTION: 2388 case UHF_C_PORT_ENABLE: 2389 case UHF_C_PORT_SUSPEND: 2390 case UHF_C_PORT_OVER_CURRENT: 2391 case UHF_C_PORT_RESET: 2392 default: 2393 break; 2394 } 2395 #endif 2396 break; 2397 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2398 if (len == 0) 2399 break; 2400 if ((value & 0xff) != 0) { 2401 return -1; 2402 } 2403 totlen = min(buflen, sizeof(hubd)); 2404 memcpy(&hubd, buf, totlen); 2405 hubd.bNbrPorts = sc->sc_noport; 2406 v = EOREAD4(sc, EHCI_HCSPARAMS); 2407 USETW(hubd.wHubCharacteristics, 2408 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2409 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2410 ? UHD_PORT_IND : 0); 2411 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2412 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2413 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2414 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2415 totlen = min(totlen, hubd.bDescLength); 2416 memcpy(buf, &hubd, totlen); 2417 break; 2418 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2419 if (len != 4) { 2420 return -1; 2421 } 2422 memset(buf, 0, len); /* ? XXX */ 2423 totlen = len; 2424 break; 2425 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2426 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2427 if (index < 1 || index > sc->sc_noport) { 2428 return -1; 2429 } 2430 if (len != 4) { 2431 return -1; 2432 } 2433 v = EOREAD4(sc, EHCI_PORTSC(index)); 2434 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2435 2436 i = UPS_HIGH_SPEED; 2437 if (sc->sc_flags & EHCIF_ETTF) { 2438 /* 2439 * If we are doing embedded transaction translation, 2440 * then directly attached LS/FS devices are reset by 2441 * the EHCI controller itself. PSPD is encoded 2442 * the same way as in USBSTATUS. 2443 */ 2444 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2445 } 2446 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2447 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2448 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2449 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2450 if (v & EHCI_PS_PR) i |= UPS_RESET; 2451 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2452 if (sc->sc_vendor_port_status) 2453 i = sc->sc_vendor_port_status(sc, v, i); 2454 USETW(ps.wPortStatus, i); 2455 i = 0; 2456 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2457 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2458 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2459 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2460 USETW(ps.wPortChange, i); 2461 totlen = min(len, sizeof(ps)); 2462 memcpy(buf, &ps, totlen); 2463 break; 2464 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2465 return -1; 2466 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2467 break; 2468 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2469 if (index < 1 || index > sc->sc_noport) { 2470 return -1; 2471 } 2472 port = EHCI_PORTSC(index); 2473 v = EOREAD4(sc, port); 2474 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2475 v &= ~EHCI_PS_CLEAR; 2476 switch(value) { 2477 case UHF_PORT_ENABLE: 2478 EOWRITE4(sc, port, v | EHCI_PS_PE); 2479 break; 2480 case UHF_PORT_SUSPEND: 2481 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2482 break; 2483 case UHF_PORT_RESET: 2484 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2485 if (EHCI_PS_IS_LOWSPEED(v) 2486 && sc->sc_ncomp > 0 2487 && !(sc->sc_flags & EHCIF_ETTF)) { 2488 /* 2489 * Low speed device on non-ETTF controller or 2490 * unaccompanied controller, give up ownership. 2491 */ 2492 ehci_disown(sc, index, 1); 2493 break; 2494 } 2495 /* Start reset sequence. */ 2496 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2497 EOWRITE4(sc, port, v | EHCI_PS_PR); 2498 /* Wait for reset to complete. */ 2499 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2500 if (sc->sc_dying) { 2501 return -1; 2502 } 2503 /* 2504 * An embedded transaction translator will automatically 2505 * terminate the reset sequence so there's no need to 2506 * it. 2507 */ 2508 v = EOREAD4(sc, port); 2509 if (v & EHCI_PS_PR) { 2510 /* Terminate reset sequence. */ 2511 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2512 /* Wait for HC to complete reset. */ 2513 usb_delay_ms(&sc->sc_bus, 2514 EHCI_PORT_RESET_COMPLETE); 2515 if (sc->sc_dying) { 2516 return -1; 2517 } 2518 } 2519 2520 v = EOREAD4(sc, port); 2521 USBHIST_LOG(ehcidebug, 2522 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2523 if (v & EHCI_PS_PR) { 2524 printf("%s: port reset timeout\n", 2525 device_xname(sc->sc_dev)); 2526 return USBD_TIMEOUT; 2527 } 2528 if (!(v & EHCI_PS_PE)) { 2529 /* Not a high speed device, give up ownership.*/ 2530 ehci_disown(sc, index, 0); 2531 break; 2532 } 2533 sc->sc_isreset[index] = 1; 2534 USBHIST_LOG(ehcidebug, 2535 "ehci port %d reset, status = 0x%08x", index, v, 0, 2536 0); 2537 break; 2538 case UHF_PORT_POWER: 2539 USBHIST_LOG(ehcidebug, 2540 "set port power %d (has PPC = %d)", index, 2541 sc->sc_hasppc, 0, 0); 2542 if (sc->sc_hasppc) 2543 EOWRITE4(sc, port, v | EHCI_PS_PP); 2544 break; 2545 case UHF_PORT_TEST: 2546 USBHIST_LOG(ehcidebug, "set port test %d", 2547 index, 0, 0, 0); 2548 break; 2549 case UHF_PORT_INDICATOR: 2550 USBHIST_LOG(ehcidebug, "set port ind %d", 2551 index, 0, 0, 0); 2552 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2553 break; 2554 default: 2555 return -1; 2556 } 2557 break; 2558 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2559 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2560 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2561 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2562 break; 2563 default: 2564 /* default from usbroothub */ 2565 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2566 buflen, 0, 0, 0); 2567 2568 return buflen; 2569 } 2570 2571 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2572 2573 return totlen; 2574 } 2575 2576 Static void 2577 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2578 { 2579 int port; 2580 uint32_t v; 2581 2582 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2583 2584 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2585 #ifdef DIAGNOSTIC 2586 if (sc->sc_npcomp != 0) { 2587 int i = (index-1) / sc->sc_npcomp; 2588 if (i >= sc->sc_ncomp) 2589 printf("%s: strange port\n", 2590 device_xname(sc->sc_dev)); 2591 else 2592 printf("%s: handing over %s speed device on " 2593 "port %d to %s\n", 2594 device_xname(sc->sc_dev), 2595 lowspeed ? "low" : "full", 2596 index, device_xname(sc->sc_comps[i])); 2597 } else { 2598 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2599 } 2600 #endif 2601 port = EHCI_PORTSC(index); 2602 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2603 EOWRITE4(sc, port, v | EHCI_PS_PO); 2604 } 2605 2606 Static usbd_status 2607 ehci_root_intr_transfer(usbd_xfer_handle xfer) 2608 { 2609 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2610 usbd_status err; 2611 2612 /* Insert last in queue. */ 2613 mutex_enter(&sc->sc_lock); 2614 err = usb_insert_transfer(xfer); 2615 mutex_exit(&sc->sc_lock); 2616 if (err) 2617 return err; 2618 2619 /* Pipe isn't running, start first */ 2620 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2621 } 2622 2623 Static usbd_status 2624 ehci_root_intr_start(usbd_xfer_handle xfer) 2625 { 2626 usbd_pipe_handle pipe = xfer->ux_pipe; 2627 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2628 2629 if (sc->sc_dying) 2630 return USBD_IOERROR; 2631 2632 mutex_enter(&sc->sc_lock); 2633 sc->sc_intrxfer = xfer; 2634 mutex_exit(&sc->sc_lock); 2635 2636 return USBD_IN_PROGRESS; 2637 } 2638 2639 /* Abort a root interrupt request. */ 2640 Static void 2641 ehci_root_intr_abort(usbd_xfer_handle xfer) 2642 { 2643 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2644 2645 KASSERT(mutex_owned(&sc->sc_lock)); 2646 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2647 2648 sc->sc_intrxfer = NULL; 2649 2650 xfer->ux_status = USBD_CANCELLED; 2651 usb_transfer_complete(xfer); 2652 } 2653 2654 /* Close the root pipe. */ 2655 Static void 2656 ehci_root_intr_close(usbd_pipe_handle pipe) 2657 { 2658 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2659 2660 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2661 2662 KASSERT(mutex_owned(&sc->sc_lock)); 2663 2664 sc->sc_intrxfer = NULL; 2665 } 2666 2667 Static void 2668 ehci_root_intr_done(usbd_xfer_handle xfer) 2669 { 2670 xfer->ux_hcpriv = NULL; 2671 } 2672 2673 /************************/ 2674 2675 Static ehci_soft_qh_t * 2676 ehci_alloc_sqh(ehci_softc_t *sc) 2677 { 2678 ehci_soft_qh_t *sqh; 2679 usbd_status err; 2680 int i, offs; 2681 usb_dma_t dma; 2682 2683 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2684 2685 if (sc->sc_freeqhs == NULL) { 2686 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2687 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2688 EHCI_PAGE_SIZE, &dma); 2689 #ifdef EHCI_DEBUG 2690 if (err) 2691 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2692 #endif 2693 if (err) 2694 return NULL; 2695 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2696 offs = i * EHCI_SQH_SIZE; 2697 sqh = KERNADDR(&dma, offs); 2698 sqh->physaddr = DMAADDR(&dma, offs); 2699 sqh->dma = dma; 2700 sqh->offs = offs; 2701 sqh->next = sc->sc_freeqhs; 2702 sc->sc_freeqhs = sqh; 2703 } 2704 } 2705 sqh = sc->sc_freeqhs; 2706 sc->sc_freeqhs = sqh->next; 2707 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2708 sqh->next = NULL; 2709 return sqh; 2710 } 2711 2712 Static void 2713 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2714 { 2715 sqh->next = sc->sc_freeqhs; 2716 sc->sc_freeqhs = sqh; 2717 } 2718 2719 Static ehci_soft_qtd_t * 2720 ehci_alloc_sqtd(ehci_softc_t *sc) 2721 { 2722 ehci_soft_qtd_t *sqtd = NULL; 2723 usbd_status err; 2724 int i, offs; 2725 usb_dma_t dma; 2726 2727 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2728 2729 if (sc->sc_freeqtds == NULL) { 2730 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2731 2732 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2733 EHCI_PAGE_SIZE, &dma); 2734 #ifdef EHCI_DEBUG 2735 if (err) 2736 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2737 #endif 2738 if (err) 2739 goto done; 2740 2741 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2742 offs = i * EHCI_SQTD_SIZE; 2743 sqtd = KERNADDR(&dma, offs); 2744 sqtd->physaddr = DMAADDR(&dma, offs); 2745 sqtd->dma = dma; 2746 sqtd->offs = offs; 2747 2748 sqtd->nextqtd = sc->sc_freeqtds; 2749 sc->sc_freeqtds = sqtd; 2750 } 2751 } 2752 2753 sqtd = sc->sc_freeqtds; 2754 sc->sc_freeqtds = sqtd->nextqtd; 2755 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2756 sqtd->nextqtd = NULL; 2757 sqtd->xfer = NULL; 2758 2759 done: 2760 return sqtd; 2761 } 2762 2763 Static void 2764 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2765 { 2766 2767 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2768 2769 sqtd->nextqtd = sc->sc_freeqtds; 2770 sc->sc_freeqtds = sqtd; 2771 } 2772 2773 Static usbd_status 2774 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2775 int alen, int rd, usbd_xfer_handle xfer, 2776 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2777 { 2778 ehci_soft_qtd_t *next, *cur; 2779 ehci_physaddr_t nextphys; 2780 uint32_t qtdstatus; 2781 int len, curlen, mps; 2782 int i, tog; 2783 int pages, pageoffs; 2784 size_t curoffs; 2785 vaddr_t va, va_offs; 2786 usb_dma_t *dma = &xfer->ux_dmabuf; 2787 uint16_t flags = xfer->ux_flags; 2788 paddr_t a; 2789 2790 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2791 2792 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2793 2794 len = alen; 2795 qtdstatus = EHCI_QTD_ACTIVE | 2796 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2797 EHCI_QTD_SET_CERR(3) 2798 /* IOC set below */ 2799 /* BYTES set below */ 2800 ; 2801 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 2802 tog = epipe->nexttoggle; 2803 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2804 2805 cur = ehci_alloc_sqtd(sc); 2806 *sp = cur; 2807 if (cur == NULL) 2808 goto nomem; 2809 2810 usb_syncmem(dma, 0, alen, 2811 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2812 curoffs = 0; 2813 for (;;) { 2814 /* The EHCI hardware can handle at most 5 pages. */ 2815 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2816 va_offs = EHCI_PAGE_OFFSET(va_offs); 2817 if (len-curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2818 /* we can handle it in this QTD */ 2819 curlen = len - curoffs; 2820 } else { 2821 /* must use multiple TDs, fill as much as possible. */ 2822 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2823 2824 /* the length must be a multiple of the max size */ 2825 curlen -= curlen % mps; 2826 USBHIST_LOG(ehcidebug, "multiple QTDs, " 2827 "curlen=%d", curlen, 0, 0, 0); 2828 KASSERT(curlen != 0); 2829 } 2830 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 2831 len, curlen, curoffs, 0); 2832 2833 /* 2834 * Allocate another transfer if there's more data left, 2835 * or if force last short transfer flag is set and we're 2836 * allocating a multiple of the max packet size. 2837 */ 2838 2839 if (curoffs + curlen != len || 2840 ((curlen % mps) == 0 && !rd && curlen != 0 && 2841 (flags & USBD_FORCE_SHORT_XFER))) { 2842 next = ehci_alloc_sqtd(sc); 2843 if (next == NULL) 2844 goto nomem; 2845 nextphys = htole32(next->physaddr); 2846 } else { 2847 next = NULL; 2848 nextphys = EHCI_NULL; 2849 } 2850 2851 /* Find number of pages we'll be using, insert dma addresses */ 2852 pages = EHCI_NPAGES(curlen); 2853 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2854 pageoffs = EHCI_PAGE(curoffs); 2855 for (i = 0; i < pages; i++) { 2856 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2857 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2858 /* Cast up to avoid compiler warnings */ 2859 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2860 } 2861 2862 /* First buffer pointer requires a page offset to start at */ 2863 va = (vaddr_t)KERNADDR(dma, curoffs); 2864 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2865 2866 cur->nextqtd = next; 2867 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2868 cur->qtd.qtd_status = 2869 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2870 cur->xfer = xfer; 2871 cur->len = curlen; 2872 2873 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2874 curoffs, curoffs + curlen, 0, 0); 2875 2876 /* 2877 * adjust the toggle based on the number of packets in this 2878 * qtd 2879 */ 2880 if (((curlen + mps - 1) / mps) & 1) { 2881 tog ^= 1; 2882 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2883 } 2884 if (next == NULL) 2885 break; 2886 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2887 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2888 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2889 if (len) 2890 curoffs += curlen; 2891 cur = next; 2892 } 2893 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2894 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2895 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2896 *ep = cur; 2897 epipe->nexttoggle = tog; 2898 2899 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 2900 *sp, *ep, 0, 0); 2901 2902 return USBD_NORMAL_COMPLETION; 2903 2904 nomem: 2905 /* XXX free chain */ 2906 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2907 return USBD_NOMEM; 2908 } 2909 2910 Static void 2911 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2912 ehci_soft_qtd_t *sqtdend) 2913 { 2914 ehci_soft_qtd_t *p; 2915 int i; 2916 2917 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2918 2919 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 2920 sqtd, sqtdend, 0, 0); 2921 2922 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2923 p = sqtd->nextqtd; 2924 ehci_free_sqtd(sc, sqtd); 2925 } 2926 } 2927 2928 Static ehci_soft_itd_t * 2929 ehci_alloc_itd(ehci_softc_t *sc) 2930 { 2931 struct ehci_soft_itd *itd, *freeitd; 2932 usbd_status err; 2933 int i, offs, frindex, previndex; 2934 usb_dma_t dma; 2935 2936 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2937 2938 mutex_enter(&sc->sc_lock); 2939 2940 /* 2941 * Find an itd that wasn't freed this frame or last frame. This can 2942 * discard itds that were freed before frindex wrapped around 2943 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2944 * interrupt and fiddling with list when that happens 2945 */ 2946 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2947 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2948 2949 freeitd = NULL; 2950 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2951 if (itd == NULL) 2952 break; 2953 if (itd->slot != frindex && itd->slot != previndex) { 2954 freeitd = itd; 2955 break; 2956 } 2957 } 2958 2959 if (freeitd == NULL) { 2960 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2961 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2962 EHCI_PAGE_SIZE, &dma); 2963 2964 if (err) { 2965 USBHIST_LOG(ehcidebug, 2966 "alloc returned %d", err, 0, 0, 0); 2967 mutex_exit(&sc->sc_lock); 2968 return NULL; 2969 } 2970 2971 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2972 offs = i * EHCI_ITD_SIZE; 2973 itd = KERNADDR(&dma, offs); 2974 itd->physaddr = DMAADDR(&dma, offs); 2975 itd->dma = dma; 2976 itd->offs = offs; 2977 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2978 } 2979 freeitd = LIST_FIRST(&sc->sc_freeitds); 2980 } 2981 2982 itd = freeitd; 2983 LIST_REMOVE(itd, u.free_list); 2984 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2985 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2986 sizeof(itd->itd.itd_next), 2987 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2988 2989 itd->u.frame_list.next = NULL; 2990 itd->u.frame_list.prev = NULL; 2991 itd->xfer_next = NULL; 2992 itd->slot = 0; 2993 2994 mutex_exit(&sc->sc_lock); 2995 2996 return itd; 2997 } 2998 2999 Static ehci_soft_sitd_t * 3000 ehci_alloc_sitd(ehci_softc_t *sc) 3001 { 3002 struct ehci_soft_sitd *sitd, *freesitd; 3003 usbd_status err; 3004 int i, offs, frindex, previndex; 3005 usb_dma_t dma; 3006 3007 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3008 3009 mutex_enter(&sc->sc_lock); 3010 3011 /* 3012 * Find an sitd that wasn't freed this frame or last frame. This can 3013 * discard sitds that were freed before frindex wrapped around 3014 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3015 * interrupt and fiddling with list when that happens 3016 */ 3017 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3018 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3019 3020 freesitd = NULL; 3021 LIST_FOREACH(sitd, &sc->sc_freesitds, u.free_list) { 3022 if (sitd == NULL) 3023 break; 3024 if (sitd->slot != frindex && sitd->slot != previndex) { 3025 freesitd = sitd; 3026 break; 3027 } 3028 } 3029 3030 if (freesitd == NULL) { 3031 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3032 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3033 EHCI_PAGE_SIZE, &dma); 3034 3035 if (err) { 3036 USBHIST_LOG(ehcidebug, 3037 "alloc returned %d", err, 0, 0, 0); 3038 mutex_exit(&sc->sc_lock); 3039 return NULL; 3040 } 3041 3042 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3043 offs = i * EHCI_SITD_SIZE; 3044 sitd = KERNADDR(&dma, offs); 3045 sitd->physaddr = DMAADDR(&dma, offs); 3046 sitd->dma = dma; 3047 sitd->offs = offs; 3048 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3049 } 3050 freesitd = LIST_FIRST(&sc->sc_freesitds); 3051 } 3052 3053 sitd = freesitd; 3054 LIST_REMOVE(sitd, u.free_list); 3055 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3056 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3057 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3058 BUS_DMASYNC_PREREAD); 3059 3060 sitd->u.frame_list.next = NULL; 3061 sitd->u.frame_list.prev = NULL; 3062 sitd->xfer_next = NULL; 3063 sitd->slot = 0; 3064 3065 mutex_exit(&sc->sc_lock); 3066 3067 return sitd; 3068 } 3069 3070 Static void 3071 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3072 { 3073 3074 KASSERT(mutex_owned(&sc->sc_lock)); 3075 3076 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3077 } 3078 3079 Static void 3080 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3081 { 3082 3083 KASSERT(mutex_owned(&sc->sc_lock)); 3084 3085 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3086 } 3087 3088 /****************/ 3089 3090 /* 3091 * Close a reqular pipe. 3092 * Assumes that there are no pending transactions. 3093 */ 3094 Static void 3095 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head) 3096 { 3097 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3098 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3099 ehci_soft_qh_t *sqh = epipe->sqh; 3100 3101 KASSERT(mutex_owned(&sc->sc_lock)); 3102 3103 ehci_rem_qh(sc, sqh, head); 3104 ehci_free_sqh(sc, epipe->sqh); 3105 } 3106 3107 /* 3108 * Abort a device request. 3109 * If this routine is called at splusb() it guarantees that the request 3110 * will be removed from the hardware scheduling and that the callback 3111 * for it will be called with USBD_CANCELLED status. 3112 * It's impossible to guarantee that the requested transfer will not 3113 * have happened since the hardware runs concurrently. 3114 * If the transaction has already happened we rely on the ordinary 3115 * interrupt processing to process it. 3116 * XXX This is most probably wrong. 3117 * XXXMRG this doesn't make sense anymore. 3118 */ 3119 Static void 3120 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status) 3121 { 3122 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3123 struct ehci_xfer *exfer = EXFER(xfer); 3124 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3125 ehci_soft_qh_t *sqh = epipe->sqh; 3126 ehci_soft_qtd_t *sqtd; 3127 ehci_physaddr_t cur; 3128 uint32_t qhstatus; 3129 int hit; 3130 int wake; 3131 3132 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3133 3134 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3135 3136 KASSERT(mutex_owned(&sc->sc_lock)); 3137 ASSERT_SLEEPABLE(); 3138 3139 if (sc->sc_dying) { 3140 /* If we're dying, just do the software part. */ 3141 xfer->ux_status = status; /* make software ignore it */ 3142 callout_stop(&xfer->ux_callout); 3143 usb_transfer_complete(xfer); 3144 return; 3145 } 3146 3147 /* 3148 * If an abort is already in progress then just wait for it to 3149 * complete and return. 3150 */ 3151 if (xfer->ux_hcflags & UXFER_ABORTING) { 3152 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3153 #ifdef DIAGNOSTIC 3154 if (status == USBD_TIMEOUT) 3155 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3156 #endif 3157 /* Override the status which might be USBD_TIMEOUT. */ 3158 xfer->ux_status = status; 3159 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3160 0, 0, 0, 0); 3161 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3162 while (xfer->ux_hcflags & UXFER_ABORTING) 3163 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3164 return; 3165 } 3166 xfer->ux_hcflags |= UXFER_ABORTING; 3167 3168 /* 3169 * Step 1: Make interrupt routine and hardware ignore xfer. 3170 */ 3171 xfer->ux_status = status; /* make software ignore it */ 3172 callout_stop(&xfer->ux_callout); 3173 3174 usb_syncmem(&sqh->dma, 3175 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3176 sizeof(sqh->qh.qh_qtd.qtd_status), 3177 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3178 qhstatus = sqh->qh.qh_qtd.qtd_status; 3179 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3180 usb_syncmem(&sqh->dma, 3181 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3182 sizeof(sqh->qh.qh_qtd.qtd_status), 3183 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3184 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3185 usb_syncmem(&sqtd->dma, 3186 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3187 sizeof(sqtd->qtd.qtd_status), 3188 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3189 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3190 usb_syncmem(&sqtd->dma, 3191 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3192 sizeof(sqtd->qtd.qtd_status), 3193 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3194 if (sqtd == exfer->ex_sqtdend) 3195 break; 3196 } 3197 3198 /* 3199 * Step 2: Wait until we know hardware has finished any possible 3200 * use of the xfer. Also make sure the soft interrupt routine 3201 * has run. 3202 */ 3203 ehci_sync_hc(sc); 3204 sc->sc_softwake = 1; 3205 usb_schedsoftintr(&sc->sc_bus); 3206 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3207 3208 /* 3209 * Step 3: Remove any vestiges of the xfer from the hardware. 3210 * The complication here is that the hardware may have executed 3211 * beyond the xfer we're trying to abort. So as we're scanning 3212 * the TDs of this xfer we check if the hardware points to 3213 * any of them. 3214 */ 3215 3216 usb_syncmem(&sqh->dma, 3217 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3218 sizeof(sqh->qh.qh_curqtd), 3219 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3220 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3221 hit = 0; 3222 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3223 hit |= cur == sqtd->physaddr; 3224 if (sqtd == exfer->ex_sqtdend) 3225 break; 3226 } 3227 sqtd = sqtd->nextqtd; 3228 /* Zap curqtd register if hardware pointed inside the xfer. */ 3229 if (hit && sqtd != NULL) { 3230 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3231 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3232 usb_syncmem(&sqh->dma, 3233 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3234 sizeof(sqh->qh.qh_curqtd), 3235 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3236 sqh->qh.qh_qtd.qtd_status = qhstatus; 3237 usb_syncmem(&sqh->dma, 3238 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3239 sizeof(sqh->qh.qh_qtd.qtd_status), 3240 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3241 } else { 3242 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3243 usb_syncmem(&sqh->dma, 3244 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3245 sizeof(sqh->qh.qh_curqtd), 3246 BUS_DMASYNC_PREREAD); 3247 } 3248 3249 /* 3250 * Step 4: Execute callback. 3251 */ 3252 #ifdef DIAGNOSTIC 3253 exfer->ex_isdone = true; 3254 #endif 3255 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3256 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3257 usb_transfer_complete(xfer); 3258 if (wake) { 3259 cv_broadcast(&xfer->ux_hccv); 3260 } 3261 3262 KASSERT(mutex_owned(&sc->sc_lock)); 3263 } 3264 3265 Static void 3266 ehci_abort_isoc_xfer(usbd_xfer_handle xfer, usbd_status status) 3267 { 3268 ehci_isoc_trans_t trans_status; 3269 struct ehci_pipe *epipe; 3270 struct ehci_xfer *exfer; 3271 ehci_softc_t *sc; 3272 struct ehci_soft_itd *itd; 3273 struct ehci_soft_sitd *sitd; 3274 int i, wake; 3275 3276 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3277 3278 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3279 exfer = EXFER(xfer); 3280 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3281 3282 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3283 3284 KASSERT(mutex_owned(&sc->sc_lock)); 3285 3286 if (sc->sc_dying) { 3287 xfer->ux_status = status; 3288 callout_stop(&xfer->ux_callout); 3289 usb_transfer_complete(xfer); 3290 return; 3291 } 3292 3293 if (xfer->ux_hcflags & UXFER_ABORTING) { 3294 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3295 3296 #ifdef DIAGNOSTIC 3297 if (status == USBD_TIMEOUT) 3298 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3299 #endif 3300 3301 xfer->ux_status = status; 3302 USBHIST_LOG(ehcidebug, 3303 "waiting for abort to finish", 0, 0, 0, 0); 3304 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3305 while (xfer->ux_hcflags & UXFER_ABORTING) 3306 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3307 goto done; 3308 } 3309 xfer->ux_hcflags |= UXFER_ABORTING; 3310 3311 xfer->ux_status = status; 3312 callout_stop(&xfer->ux_callout); 3313 3314 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3315 for (itd = exfer->ex_itdstart; itd != NULL; 3316 itd = itd->xfer_next) { 3317 usb_syncmem(&itd->dma, 3318 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3319 sizeof(itd->itd.itd_ctl), 3320 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3321 3322 for (i = 0; i < 8; i++) { 3323 trans_status = le32toh(itd->itd.itd_ctl[i]); 3324 trans_status &= ~EHCI_ITD_ACTIVE; 3325 itd->itd.itd_ctl[i] = htole32(trans_status); 3326 } 3327 3328 usb_syncmem(&itd->dma, 3329 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3330 sizeof(itd->itd.itd_ctl), 3331 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3332 } 3333 } else { 3334 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3335 sitd = sitd->xfer_next) { 3336 usb_syncmem(&sitd->dma, 3337 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3338 sizeof(sitd->sitd.sitd_buffer), 3339 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3340 3341 trans_status = le32toh(sitd->sitd.sitd_trans); 3342 trans_status &= ~EHCI_SITD_ACTIVE; 3343 sitd->sitd.sitd_trans = htole32(trans_status); 3344 3345 usb_syncmem(&sitd->dma, 3346 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3347 sizeof(sitd->sitd.sitd_buffer), 3348 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3349 } 3350 } 3351 3352 sc->sc_softwake = 1; 3353 usb_schedsoftintr(&sc->sc_bus); 3354 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3355 3356 #ifdef DIAGNOSTIC 3357 exfer->ex_isdone = true; 3358 #endif 3359 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3360 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3361 usb_transfer_complete(xfer); 3362 if (wake) { 3363 cv_broadcast(&xfer->ux_hccv); 3364 } 3365 3366 done: 3367 KASSERT(mutex_owned(&sc->sc_lock)); 3368 return; 3369 } 3370 3371 Static void 3372 ehci_timeout(void *addr) 3373 { 3374 struct ehci_xfer *exfer = addr; 3375 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->ex_xfer.ux_pipe; 3376 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3377 3378 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3379 3380 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3381 #ifdef EHCI_DEBUG 3382 if (ehcidebug > 1) 3383 usbd_dump_pipe(exfer->ex_xfer.ux_pipe); 3384 #endif 3385 3386 if (sc->sc_dying) { 3387 mutex_enter(&sc->sc_lock); 3388 ehci_abort_xfer(&exfer->ex_xfer, USBD_TIMEOUT); 3389 mutex_exit(&sc->sc_lock); 3390 return; 3391 } 3392 3393 /* Execute the abort in a process context. */ 3394 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, addr, 3395 USB_TASKQ_MPSAFE); 3396 usb_add_task(exfer->ex_xfer.ux_pipe->up_dev, &exfer->ex_aborttask, 3397 USB_TASKQ_HC); 3398 } 3399 3400 Static void 3401 ehci_timeout_task(void *addr) 3402 { 3403 usbd_xfer_handle xfer = addr; 3404 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3405 3406 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3407 3408 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3409 3410 mutex_enter(&sc->sc_lock); 3411 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3412 mutex_exit(&sc->sc_lock); 3413 } 3414 3415 /************************/ 3416 3417 Static usbd_status 3418 ehci_device_ctrl_transfer(usbd_xfer_handle xfer) 3419 { 3420 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3421 usbd_status err; 3422 3423 /* Insert last in queue. */ 3424 mutex_enter(&sc->sc_lock); 3425 err = usb_insert_transfer(xfer); 3426 mutex_exit(&sc->sc_lock); 3427 if (err) 3428 return err; 3429 3430 /* Pipe isn't running, start first */ 3431 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3432 } 3433 3434 Static usbd_status 3435 ehci_device_ctrl_start(usbd_xfer_handle xfer) 3436 { 3437 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3438 usbd_status err; 3439 3440 if (sc->sc_dying) 3441 return USBD_IOERROR; 3442 3443 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3444 3445 err = ehci_device_request(xfer); 3446 if (err) { 3447 return err; 3448 } 3449 3450 if (sc->sc_bus.ub_usepolling) 3451 ehci_waitintr(sc, xfer); 3452 3453 return USBD_IN_PROGRESS; 3454 } 3455 3456 Static void 3457 ehci_device_ctrl_done(usbd_xfer_handle xfer) 3458 { 3459 struct ehci_xfer *ex = EXFER(xfer); 3460 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3461 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3462 usb_device_request_t *req = &xfer->ux_request; 3463 int len = UGETW(req->wLength); 3464 int rd = req->bmRequestType & UT_READ; 3465 3466 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3467 3468 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3469 3470 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3471 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3472 3473 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3474 ehci_del_intr_list(sc, ex); /* remove from active list */ 3475 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3476 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof(*req), 3477 BUS_DMASYNC_POSTWRITE); 3478 if (len) 3479 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3480 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3481 } 3482 3483 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3484 } 3485 3486 /* Abort a device control request. */ 3487 Static void 3488 ehci_device_ctrl_abort(usbd_xfer_handle xfer) 3489 { 3490 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3491 3492 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3493 ehci_abort_xfer(xfer, USBD_CANCELLED); 3494 } 3495 3496 /* Close a device control pipe. */ 3497 Static void 3498 ehci_device_ctrl_close(usbd_pipe_handle pipe) 3499 { 3500 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3501 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3502 3503 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3504 3505 KASSERT(mutex_owned(&sc->sc_lock)); 3506 3507 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3508 3509 ehci_close_pipe(pipe, sc->sc_async_head); 3510 } 3511 3512 Static usbd_status 3513 ehci_device_request(usbd_xfer_handle xfer) 3514 { 3515 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3516 struct ehci_xfer *exfer = EXFER(xfer); 3517 usb_device_request_t *req = &xfer->ux_request; 3518 usbd_device_handle dev = epipe->pipe.up_dev; 3519 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3520 ehci_soft_qtd_t *setup, *stat, *next; 3521 ehci_soft_qh_t *sqh; 3522 int isread; 3523 int len; 3524 usbd_status err; 3525 3526 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3527 3528 isread = req->bmRequestType & UT_READ; 3529 len = UGETW(req->wLength); 3530 3531 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3532 "wValue=0x%04x, wIndex=0x%04x", 3533 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3534 UGETW(req->wIndex)); 3535 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3536 len, dev->ud_addr, 3537 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3538 3539 setup = ehci_alloc_sqtd(sc); 3540 if (setup == NULL) { 3541 err = USBD_NOMEM; 3542 goto bad1; 3543 } 3544 stat = ehci_alloc_sqtd(sc); 3545 if (stat == NULL) { 3546 err = USBD_NOMEM; 3547 goto bad2; 3548 } 3549 3550 mutex_enter(&sc->sc_lock); 3551 3552 sqh = epipe->sqh; 3553 3554 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3555 "address QH %" __PRIuBIT " pipe %d\n", 3556 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3557 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3558 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3559 "MPS QH %" __PRIuBIT " pipe %d\n", 3560 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3561 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3562 3563 /* Set up data transaction */ 3564 if (len != 0) { 3565 ehci_soft_qtd_t *end; 3566 3567 /* Start toggle at 1. */ 3568 epipe->nexttoggle = 1; 3569 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3570 &next, &end); 3571 if (err) 3572 goto bad3; 3573 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3574 end->nextqtd = stat; 3575 end->qtd.qtd_next = end->qtd.qtd_altnext = 3576 htole32(stat->physaddr); 3577 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3578 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3579 } else { 3580 next = stat; 3581 } 3582 3583 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 3584 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3585 3586 /* Clear toggle */ 3587 setup->qtd.qtd_status = htole32( 3588 EHCI_QTD_ACTIVE | 3589 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3590 EHCI_QTD_SET_CERR(3) | 3591 EHCI_QTD_SET_TOGGLE(0) | 3592 EHCI_QTD_SET_BYTES(sizeof(*req)) 3593 ); 3594 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3595 setup->qtd.qtd_buffer_hi[0] = 0; 3596 setup->nextqtd = next; 3597 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3598 setup->xfer = xfer; 3599 setup->len = sizeof(*req); 3600 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3601 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3602 3603 stat->qtd.qtd_status = htole32( 3604 EHCI_QTD_ACTIVE | 3605 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3606 EHCI_QTD_SET_CERR(3) | 3607 EHCI_QTD_SET_TOGGLE(1) | 3608 EHCI_QTD_IOC 3609 ); 3610 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3611 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3612 stat->nextqtd = NULL; 3613 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3614 stat->xfer = xfer; 3615 stat->len = 0; 3616 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3617 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3618 3619 #ifdef EHCI_DEBUG 3620 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3621 ehci_dump_sqh(sqh); 3622 ehci_dump_sqtds(setup); 3623 #endif 3624 3625 exfer->ex_sqtdstart = setup; 3626 exfer->ex_sqtdend = stat; 3627 KASSERT(exfer->ex_isdone); 3628 #ifdef DIAGNOSTIC 3629 exfer->ex_isdone = false; 3630 #endif 3631 3632 /* Insert qTD in QH list. */ 3633 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3634 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3635 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3636 ehci_timeout, xfer); 3637 } 3638 ehci_add_intr_list(sc, exfer); 3639 xfer->ux_status = USBD_IN_PROGRESS; 3640 mutex_exit(&sc->sc_lock); 3641 3642 #ifdef EHCI_DEBUG 3643 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3644 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3645 // delay(10000); 3646 ehci_dump_regs(sc); 3647 ehci_dump_sqh(sc->sc_async_head); 3648 ehci_dump_sqh(sqh); 3649 ehci_dump_sqtds(setup); 3650 #endif 3651 3652 return USBD_NORMAL_COMPLETION; 3653 3654 bad3: 3655 mutex_exit(&sc->sc_lock); 3656 ehci_free_sqtd(sc, stat); 3657 bad2: 3658 ehci_free_sqtd(sc, setup); 3659 bad1: 3660 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3661 mutex_enter(&sc->sc_lock); 3662 xfer->ux_status = err; 3663 usb_transfer_complete(xfer); 3664 mutex_exit(&sc->sc_lock); 3665 return err; 3666 } 3667 3668 /* 3669 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3670 * qTD status, or miss signalling occasionally under heavy load. If the host 3671 * machine is too fast, we we can miss transaction completion - when we scan 3672 * the active list the transaction still seems to be active. This generally 3673 * exhibits itself as a umass stall that never recovers. 3674 * 3675 * We work around this behaviour by setting up this callback after any softintr 3676 * that completes with transactions still pending, giving us another chance to 3677 * check for completion after the writeback has taken place. 3678 */ 3679 Static void 3680 ehci_intrlist_timeout(void *arg) 3681 { 3682 ehci_softc_t *sc = arg; 3683 3684 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3685 3686 usb_schedsoftintr(&sc->sc_bus); 3687 } 3688 3689 /************************/ 3690 3691 Static usbd_status 3692 ehci_device_bulk_transfer(usbd_xfer_handle xfer) 3693 { 3694 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3695 usbd_status err; 3696 3697 /* Insert last in queue. */ 3698 mutex_enter(&sc->sc_lock); 3699 err = usb_insert_transfer(xfer); 3700 mutex_exit(&sc->sc_lock); 3701 if (err) 3702 return err; 3703 3704 /* Pipe isn't running, start first */ 3705 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3706 } 3707 3708 Static usbd_status 3709 ehci_device_bulk_start(usbd_xfer_handle xfer) 3710 { 3711 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3712 struct ehci_xfer *exfer = EXFER(xfer); 3713 usbd_device_handle dev = epipe->pipe.up_dev; 3714 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3715 ehci_soft_qtd_t *data, *dataend; 3716 ehci_soft_qh_t *sqh; 3717 usbd_status err; 3718 int len, isread, endpt; 3719 3720 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3721 3722 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3723 xfer, xfer->ux_length, xfer->ux_flags, 0); 3724 3725 if (sc->sc_dying) 3726 return USBD_IOERROR; 3727 3728 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3729 3730 mutex_enter(&sc->sc_lock); 3731 3732 len = xfer->ux_length; 3733 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3734 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3735 sqh = epipe->sqh; 3736 3737 epipe->u.bulk.length = len; 3738 3739 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3740 &dataend); 3741 if (err) { 3742 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3743 xfer->ux_status = err; 3744 usb_transfer_complete(xfer); 3745 mutex_exit(&sc->sc_lock); 3746 return err; 3747 } 3748 3749 #ifdef EHCI_DEBUG 3750 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3751 ehci_dump_sqh(sqh); 3752 ehci_dump_sqtds(data); 3753 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3754 #endif 3755 3756 /* Set up interrupt info. */ 3757 exfer->ex_sqtdstart = data; 3758 exfer->ex_sqtdend = dataend; 3759 KASSERT(exfer->ex_isdone); 3760 #ifdef DIAGNOSTIC 3761 exfer->ex_isdone = false; 3762 #endif 3763 3764 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3765 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3766 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3767 ehci_timeout, xfer); 3768 } 3769 ehci_add_intr_list(sc, exfer); 3770 xfer->ux_status = USBD_IN_PROGRESS; 3771 mutex_exit(&sc->sc_lock); 3772 3773 #ifdef EHCI_DEBUG 3774 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3775 // delay(10000); 3776 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3777 ehci_dump_regs(sc); 3778 #if 0 3779 printf("async_head:\n"); 3780 ehci_dump_sqh(sc->sc_async_head); 3781 #endif 3782 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3783 ehci_dump_sqh(sqh); 3784 ehci_dump_sqtds(data); 3785 #endif 3786 3787 if (sc->sc_bus.ub_usepolling) 3788 ehci_waitintr(sc, xfer); 3789 3790 return USBD_IN_PROGRESS; 3791 } 3792 3793 Static void 3794 ehci_device_bulk_abort(usbd_xfer_handle xfer) 3795 { 3796 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3797 3798 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3799 ehci_abort_xfer(xfer, USBD_CANCELLED); 3800 } 3801 3802 /* 3803 * Close a device bulk pipe. 3804 */ 3805 Static void 3806 ehci_device_bulk_close(usbd_pipe_handle pipe) 3807 { 3808 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3809 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3810 3811 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3812 3813 KASSERT(mutex_owned(&sc->sc_lock)); 3814 3815 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3816 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3817 ehci_close_pipe(pipe, sc->sc_async_head); 3818 } 3819 3820 Static void 3821 ehci_device_bulk_done(usbd_xfer_handle xfer) 3822 { 3823 struct ehci_xfer *ex = EXFER(xfer); 3824 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3825 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3826 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3827 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3828 3829 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3830 3831 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3832 xfer, xfer->ux_actlen, 0, 0); 3833 3834 KASSERT(mutex_owned(&sc->sc_lock)); 3835 3836 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3837 ehci_del_intr_list(sc, ex); /* remove from active list */ 3838 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3839 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3840 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3841 } 3842 3843 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3844 } 3845 3846 /************************/ 3847 3848 Static usbd_status 3849 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3850 { 3851 struct ehci_soft_islot *isp; 3852 int islot, lev; 3853 3854 /* Find a poll rate that is large enough. */ 3855 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3856 if (EHCI_ILEV_IVAL(lev) <= ival) 3857 break; 3858 3859 /* Pick an interrupt slot at the right level. */ 3860 /* XXX could do better than picking at random */ 3861 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3862 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3863 3864 sqh->islot = islot; 3865 isp = &sc->sc_islots[islot]; 3866 mutex_enter(&sc->sc_lock); 3867 ehci_add_qh(sc, sqh, isp->sqh); 3868 mutex_exit(&sc->sc_lock); 3869 3870 return USBD_NORMAL_COMPLETION; 3871 } 3872 3873 Static usbd_status 3874 ehci_device_intr_transfer(usbd_xfer_handle xfer) 3875 { 3876 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3877 usbd_status err; 3878 3879 /* Insert last in queue. */ 3880 mutex_enter(&sc->sc_lock); 3881 err = usb_insert_transfer(xfer); 3882 mutex_exit(&sc->sc_lock); 3883 if (err) 3884 return err; 3885 3886 /* 3887 * Pipe isn't running (otherwise err would be USBD_INPROG), 3888 * so start it first. 3889 */ 3890 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3891 } 3892 3893 Static usbd_status 3894 ehci_device_intr_start(usbd_xfer_handle xfer) 3895 { 3896 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3897 struct ehci_xfer *exfer = EXFER(xfer); 3898 usbd_device_handle dev = xfer->ux_pipe->up_dev; 3899 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3900 ehci_soft_qtd_t *data, *dataend; 3901 ehci_soft_qh_t *sqh; 3902 usbd_status err; 3903 int len, isread, endpt; 3904 3905 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3906 3907 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3908 xfer, xfer->ux_length, xfer->ux_flags, 0); 3909 3910 if (sc->sc_dying) 3911 return USBD_IOERROR; 3912 3913 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3914 3915 mutex_enter(&sc->sc_lock); 3916 3917 len = xfer->ux_length; 3918 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3919 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3920 sqh = epipe->sqh; 3921 3922 epipe->u.intr.length = len; 3923 3924 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3925 &dataend); 3926 if (err) { 3927 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3928 xfer->ux_status = err; 3929 usb_transfer_complete(xfer); 3930 mutex_exit(&sc->sc_lock); 3931 return err; 3932 } 3933 3934 #ifdef EHCI_DEBUG 3935 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3936 ehci_dump_sqh(sqh); 3937 ehci_dump_sqtds(data); 3938 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3939 #endif 3940 3941 /* Set up interrupt info. */ 3942 exfer->ex_sqtdstart = data; 3943 exfer->ex_sqtdend = dataend; 3944 KASSERT(exfer->ex_isdone); 3945 #ifdef DIAGNOSTIC 3946 exfer->ex_isdone = false; 3947 #endif 3948 3949 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3950 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3951 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3952 ehci_timeout, xfer); 3953 } 3954 ehci_add_intr_list(sc, exfer); 3955 xfer->ux_status = USBD_IN_PROGRESS; 3956 mutex_exit(&sc->sc_lock); 3957 3958 #ifdef EHCI_DEBUG 3959 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3960 // delay(10000); 3961 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3962 ehci_dump_regs(sc); 3963 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3964 ehci_dump_sqh(sqh); 3965 ehci_dump_sqtds(data); 3966 #endif 3967 3968 if (sc->sc_bus.ub_usepolling) 3969 ehci_waitintr(sc, xfer); 3970 3971 return USBD_IN_PROGRESS; 3972 } 3973 3974 Static void 3975 ehci_device_intr_abort(usbd_xfer_handle xfer) 3976 { 3977 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3978 3979 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3980 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3981 3982 /* 3983 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3984 * async doorbell. That's dependent on the async list, wheras 3985 * intr xfers are periodic, should not use this? 3986 */ 3987 ehci_abort_xfer(xfer, USBD_CANCELLED); 3988 } 3989 3990 Static void 3991 ehci_device_intr_close(usbd_pipe_handle pipe) 3992 { 3993 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3994 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3995 struct ehci_soft_islot *isp; 3996 3997 KASSERT(mutex_owned(&sc->sc_lock)); 3998 3999 isp = &sc->sc_islots[epipe->sqh->islot]; 4000 ehci_close_pipe(pipe, isp->sqh); 4001 } 4002 4003 Static void 4004 ehci_device_intr_done(usbd_xfer_handle xfer) 4005 { 4006 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4007 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 4008 struct ehci_xfer *exfer = EXFER(xfer); 4009 ehci_soft_qtd_t *data, *dataend; 4010 ehci_soft_qh_t *sqh; 4011 usbd_status err; 4012 int len, isread, endpt; 4013 4014 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4015 4016 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4017 xfer, xfer->ux_actlen, 0, 0); 4018 4019 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4020 4021 if (xfer->ux_pipe->up_repeat) { 4022 ehci_free_sqtd_chain(sc, exfer->ex_sqtdstart, NULL); 4023 4024 len = epipe->u.intr.length; 4025 xfer->ux_length = len; 4026 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4027 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4028 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4029 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4030 sqh = epipe->sqh; 4031 4032 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4033 &data, &dataend); 4034 if (err) { 4035 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4036 xfer->ux_status = err; 4037 return; 4038 } 4039 4040 /* Set up interrupt info. */ 4041 exfer->ex_sqtdstart = data; 4042 exfer->ex_sqtdend = dataend; 4043 KASSERT(exfer->ex_isdone); 4044 #ifdef DIAGNOSTIC 4045 exfer->ex_isdone = false; 4046 #endif 4047 4048 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4049 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4050 callout_reset(&xfer->ux_callout, 4051 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4052 } 4053 4054 xfer->ux_status = USBD_IN_PROGRESS; 4055 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4056 ehci_del_intr_list(sc, exfer); /* remove from active list */ 4057 ehci_free_sqtd_chain(sc, exfer->ex_sqtdstart, NULL); 4058 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4059 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4060 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4061 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4062 } 4063 } 4064 4065 /************************/ 4066 4067 Static usbd_status 4068 ehci_device_fs_isoc_transfer(usbd_xfer_handle xfer) 4069 { 4070 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4071 usbd_status err; 4072 4073 mutex_enter(&sc->sc_lock); 4074 err = usb_insert_transfer(xfer); 4075 mutex_exit(&sc->sc_lock); 4076 4077 if (err && err != USBD_IN_PROGRESS) 4078 return err; 4079 4080 return ehci_device_fs_isoc_start(xfer); 4081 } 4082 4083 Static usbd_status 4084 ehci_device_fs_isoc_start(usbd_xfer_handle xfer) 4085 { 4086 struct ehci_pipe *epipe; 4087 usbd_device_handle dev; 4088 ehci_softc_t *sc; 4089 struct ehci_xfer *exfer; 4090 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4091 usb_dma_t *dma_buf; 4092 int i, j, k, frames; 4093 int offs, total_length; 4094 int frindex; 4095 u_int huba, dir; 4096 4097 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4098 4099 start = NULL; 4100 prev = NULL; 4101 sitd = NULL; 4102 total_length = 0; 4103 exfer = (struct ehci_xfer *) xfer; 4104 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4105 dev = xfer->ux_pipe->up_dev; 4106 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4107 4108 /* 4109 * To allow continuous transfers, above we start all transfers 4110 * immediately. However, we're still going to get usbd_start_next call 4111 * this when another xfer completes. So, check if this is already 4112 * in progress or not 4113 */ 4114 4115 if (exfer->ex_sitdstart != NULL) 4116 return USBD_IN_PROGRESS; 4117 4118 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4119 xfer, xfer->ux_length, xfer->ux_flags, 0); 4120 4121 if (sc->sc_dying) 4122 return USBD_IOERROR; 4123 4124 /* 4125 * To avoid complication, don't allow a request right now that'll span 4126 * the entire frame table. To within 4 frames, to allow some leeway 4127 * on either side of where the hc currently is. 4128 */ 4129 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4130 xfer->ux_nframes >= sc->sc_flsize - 4) { 4131 printf("ehci: isoc descriptor requested that spans the entire" 4132 "frametable, too many frames\n"); 4133 return USBD_INVAL; 4134 } 4135 4136 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4137 KASSERT(exfer->ex_isdone); 4138 4139 #ifdef DIAGNOSTIC 4140 exfer->ex_isdone = false; 4141 #endif 4142 4143 /* 4144 * Step 1: Allocate and initialize sitds. 4145 */ 4146 4147 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4148 if (i > 16 || i == 0) { 4149 /* Spec page 271 says intervals > 16 are invalid */ 4150 USBHIST_LOG(ehcidebug, "bInterval %d invalid", 0, 0, 0, 0); 4151 4152 return USBD_INVAL; 4153 } 4154 4155 frames = xfer->ux_nframes; 4156 4157 if (frames == 0) { 4158 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4159 4160 return USBD_INVAL; 4161 } 4162 4163 dma_buf = &xfer->ux_dmabuf; 4164 offs = 0; 4165 4166 for (i = 0; i < frames; i++) { 4167 sitd = ehci_alloc_sitd(sc); 4168 4169 if (prev) 4170 prev->xfer_next = sitd; 4171 else 4172 start = sitd; 4173 4174 #ifdef DIAGNOSTIC 4175 if (xfer->ux_frlengths[i] > 0x3ff) { 4176 printf("ehci: invalid frame length\n"); 4177 xfer->ux_frlengths[i] = 0x3ff; 4178 } 4179 #endif 4180 4181 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4182 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4183 4184 /* Set page0 index and offset. */ 4185 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4186 4187 total_length += xfer->ux_frlengths[i]; 4188 offs += xfer->ux_frlengths[i]; 4189 4190 sitd->sitd.sitd_buffer[1] = 4191 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4192 4193 huba = dev->ud_myhsport->up_parent->ud_addr; 4194 4195 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4196 // Set hub address to 0 if embedded TT is used. 4197 if (huba == sc->sc_addr) 4198 huba = 0; 4199 } 4200 */ 4201 4202 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4203 dir = UE_GET_DIR(k) ? 1 : 0; 4204 sitd->sitd.sitd_endp = 4205 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4206 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4207 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4208 EHCI_SITD_SET_HUBA(huba) | 4209 EHCI_SITD_SET_DIR(dir)); 4210 4211 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4212 4213 /* XXX */ 4214 u_char sa, sb; 4215 u_int temp, tlen; 4216 sa = 0; 4217 4218 if (dir == 0) { /* OUT */ 4219 temp = 0; 4220 tlen = xfer->ux_frlengths[i]; 4221 if (tlen <= 188) { 4222 temp |= 1; /* T-count = 1, TP = ALL */ 4223 tlen = 1; 4224 } else { 4225 tlen += 187; 4226 tlen /= 188; 4227 temp |= tlen; /* T-count = [1..6] */ 4228 temp |= 8; /* TP = Begin */ 4229 } 4230 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4231 4232 tlen += sa; 4233 4234 if (tlen >= 8) { 4235 sb = 0; 4236 } else { 4237 sb = (1 << tlen); 4238 } 4239 4240 sa = (1 << sa); 4241 sa = (sb - sa) & 0x3F; 4242 sb = 0; 4243 } else { 4244 sb = (-(4 << sa)) & 0xFE; 4245 sa = (1 << sa) & 0x3F; 4246 sa = 0x01; 4247 sb = 0xfc; 4248 } 4249 4250 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4251 EHCI_SITD_SET_CMASK(sb)); 4252 4253 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4254 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4255 4256 prev = sitd; 4257 } /* End of frame */ 4258 4259 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4260 4261 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4262 sizeof(sitd->sitd.sitd_trans), 4263 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4264 4265 stop = sitd; 4266 stop->xfer_next = NULL; 4267 4268 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4269 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4270 4271 /* 4272 * Part 2: Transfer descriptors have now been set up, now they must 4273 * be scheduled into the periodic frame list. Erk. Not wanting to 4274 * complicate matters, transfer is denied if the transfer spans 4275 * more than the period frame list. 4276 */ 4277 4278 mutex_enter(&sc->sc_lock); 4279 4280 /* Start inserting frames */ 4281 if (epipe->u.isoc.cur_xfers > 0) { 4282 frindex = epipe->u.isoc.next_frame; 4283 } else { 4284 frindex = EOREAD4(sc, EHCI_FRINDEX); 4285 frindex = frindex >> 3; /* Erase microframe index */ 4286 frindex += 2; 4287 } 4288 4289 if (frindex >= sc->sc_flsize) 4290 frindex &= (sc->sc_flsize - 1); 4291 4292 /* Whats the frame interval? */ 4293 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4294 4295 sitd = start; 4296 for (j = 0; j < frames; j++) { 4297 if (sitd == NULL) 4298 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4299 4300 usb_syncmem(&sc->sc_fldma, 4301 sizeof(ehci_link_t) * frindex, 4302 sizeof(ehci_link_t), 4303 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4304 4305 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4306 if (sitd->sitd.sitd_next == 0) 4307 /* FIXME: frindex table gets initialized to NULL 4308 * or EHCI_NULL? */ 4309 sitd->sitd.sitd_next = EHCI_NULL; 4310 4311 usb_syncmem(&sitd->dma, 4312 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4313 sizeof(ehci_sitd_t), 4314 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4315 4316 sc->sc_flist[frindex] = 4317 htole32(EHCI_LINK_SITD | sitd->physaddr); 4318 4319 usb_syncmem(&sc->sc_fldma, 4320 sizeof(ehci_link_t) * frindex, 4321 sizeof(ehci_link_t), 4322 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4323 4324 sitd->u.frame_list.next = sc->sc_softsitds[frindex]; 4325 sc->sc_softsitds[frindex] = sitd; 4326 if (sitd->u.frame_list.next != NULL) 4327 sitd->u.frame_list.next->u.frame_list.prev = sitd; 4328 sitd->slot = frindex; 4329 sitd->u.frame_list.prev = NULL; 4330 4331 frindex += i; 4332 if (frindex >= sc->sc_flsize) 4333 frindex -= sc->sc_flsize; 4334 4335 sitd = sitd->xfer_next; 4336 } 4337 4338 epipe->u.isoc.cur_xfers++; 4339 epipe->u.isoc.next_frame = frindex; 4340 4341 exfer->ex_sitdstart = start; 4342 exfer->ex_sitdend = stop; 4343 4344 ehci_add_intr_list(sc, exfer); 4345 xfer->ux_status = USBD_IN_PROGRESS; 4346 xfer->ux_done = 0; 4347 4348 mutex_exit(&sc->sc_lock); 4349 4350 if (sc->sc_bus.ub_usepolling) { 4351 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4352 ehci_waitintr(sc, xfer); 4353 } 4354 4355 return USBD_IN_PROGRESS; 4356 } 4357 4358 Static void 4359 ehci_device_fs_isoc_abort(usbd_xfer_handle xfer) 4360 { 4361 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4362 4363 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4364 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4365 } 4366 4367 Static void 4368 ehci_device_fs_isoc_close(usbd_pipe_handle pipe) 4369 { 4370 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4371 4372 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4373 } 4374 4375 Static void 4376 ehci_device_fs_isoc_done(usbd_xfer_handle xfer) 4377 { 4378 struct ehci_xfer *exfer; 4379 ehci_softc_t *sc; 4380 struct ehci_pipe *epipe; 4381 4382 exfer = EXFER(xfer); 4383 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4384 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4385 4386 KASSERT(mutex_owned(&sc->sc_lock)); 4387 4388 epipe->u.isoc.cur_xfers--; 4389 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4390 ehci_del_intr_list(sc, exfer); 4391 ehci_rem_free_sitd_chain(sc, exfer); 4392 } 4393 4394 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4395 BUS_DMASYNC_POSTREAD); 4396 } 4397 Static usbd_status 4398 ehci_device_isoc_transfer(usbd_xfer_handle xfer) 4399 { 4400 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4401 usbd_status err; 4402 4403 mutex_enter(&sc->sc_lock); 4404 err = usb_insert_transfer(xfer); 4405 mutex_exit(&sc->sc_lock); 4406 if (err && err != USBD_IN_PROGRESS) 4407 return err; 4408 4409 return ehci_device_isoc_start(xfer); 4410 } 4411 4412 Static usbd_status 4413 ehci_device_isoc_start(usbd_xfer_handle xfer) 4414 { 4415 struct ehci_pipe *epipe; 4416 ehci_softc_t *sc; 4417 struct ehci_xfer *exfer; 4418 ehci_soft_itd_t *itd, *prev, *start, *stop; 4419 usb_dma_t *dma_buf; 4420 int i, j, k, frames, uframes, ufrperframe; 4421 int trans_count, offs, total_length; 4422 int frindex; 4423 4424 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4425 4426 start = NULL; 4427 prev = NULL; 4428 itd = NULL; 4429 trans_count = 0; 4430 total_length = 0; 4431 exfer = (struct ehci_xfer *) xfer; 4432 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4433 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4434 4435 /* 4436 * To allow continuous transfers, above we start all transfers 4437 * immediately. However, we're still going to get usbd_start_next call 4438 * this when another xfer completes. So, check if this is already 4439 * in progress or not 4440 */ 4441 4442 if (exfer->ex_itdstart != NULL) 4443 return USBD_IN_PROGRESS; 4444 4445 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4446 xfer, xfer->ux_length, xfer->ux_flags, 0); 4447 4448 if (sc->sc_dying) 4449 return USBD_IOERROR; 4450 4451 /* 4452 * To avoid complication, don't allow a request right now that'll span 4453 * the entire frame table. To within 4 frames, to allow some leeway 4454 * on either side of where the hc currently is. 4455 */ 4456 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4457 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4458 USBHIST_LOG(ehcidebug, 4459 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4460 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4461 return USBD_INVAL; 4462 } 4463 4464 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4465 KASSERT(exfer->ex_isdone); 4466 #ifdef DIAGNOSTIC 4467 exfer->ex_isdone = false; 4468 #endif 4469 4470 /* 4471 * Step 1: Allocate and initialize itds, how many do we need? 4472 * One per transfer if interval >= 8 microframes, fewer if we use 4473 * multiple microframes per frame. 4474 */ 4475 4476 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4477 if (i > 16 || i == 0) { 4478 /* Spec page 271 says intervals > 16 are invalid */ 4479 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4480 return USBD_INVAL; 4481 } 4482 4483 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4484 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4485 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4486 4487 if (frames == 0) { 4488 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4489 return USBD_INVAL; 4490 } 4491 4492 dma_buf = &xfer->ux_dmabuf; 4493 offs = 0; 4494 4495 for (i = 0; i < frames; i++) { 4496 int froffs = offs; 4497 itd = ehci_alloc_itd(sc); 4498 4499 if (prev != NULL) { 4500 prev->itd.itd_next = 4501 htole32(itd->physaddr | EHCI_LINK_ITD); 4502 usb_syncmem(&prev->dma, 4503 prev->offs + offsetof(ehci_itd_t, itd_next), 4504 sizeof(prev->itd.itd_next), 4505 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4506 4507 prev->xfer_next = itd; 4508 } else { 4509 start = itd; 4510 } 4511 4512 /* 4513 * Step 1.5, initialize uframes 4514 */ 4515 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4516 /* Calculate which page in the list this starts in */ 4517 int addr = DMAADDR(dma_buf, froffs); 4518 addr = EHCI_PAGE_OFFSET(addr); 4519 addr += (offs - froffs); 4520 addr = EHCI_PAGE(addr); 4521 addr /= EHCI_PAGE_SIZE; 4522 4523 /* 4524 * This gets the initial offset into the first page, 4525 * looks how far further along the current uframe 4526 * offset is. Works out how many pages that is. 4527 */ 4528 4529 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4530 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4531 EHCI_ITD_SET_PG(addr) | 4532 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4533 4534 total_length += xfer->ux_frlengths[trans_count]; 4535 offs += xfer->ux_frlengths[trans_count]; 4536 trans_count++; 4537 4538 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4539 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4540 break; 4541 } 4542 } 4543 4544 /* 4545 * Step 1.75, set buffer pointers. To simplify matters, all 4546 * pointers are filled out for the next 7 hardware pages in 4547 * the dma block, so no need to worry what pages to cover 4548 * and what to not. 4549 */ 4550 4551 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4552 /* 4553 * Don't try to lookup a page that's past the end 4554 * of buffer 4555 */ 4556 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4557 if (page_offs >= dma_buf->udma_block->size) 4558 break; 4559 4560 unsigned long long page = DMAADDR(dma_buf, page_offs); 4561 page = EHCI_PAGE(page); 4562 itd->itd.itd_bufr[j] = 4563 htole32(EHCI_ITD_SET_BPTR(page)); 4564 itd->itd.itd_bufr_hi[j] = 4565 htole32(page >> 32); 4566 } 4567 4568 /* 4569 * Other special values 4570 */ 4571 4572 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4573 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4574 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4575 4576 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4577 ? 1 : 0; 4578 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4579 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4580 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4581 4582 /* FIXME: handle invalid trans */ 4583 itd->itd.itd_bufr[2] |= 4584 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4585 4586 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4587 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4588 4589 prev = itd; 4590 } /* End of frame */ 4591 4592 stop = itd; 4593 stop->xfer_next = NULL; 4594 4595 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4596 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4597 4598 /* 4599 * Part 2: Transfer descriptors have now been set up, now they must 4600 * be scheduled into the period frame list. Erk. Not wanting to 4601 * complicate matters, transfer is denied if the transfer spans 4602 * more than the period frame list. 4603 */ 4604 4605 mutex_enter(&sc->sc_lock); 4606 4607 /* Start inserting frames */ 4608 if (epipe->u.isoc.cur_xfers > 0) { 4609 frindex = epipe->u.isoc.next_frame; 4610 } else { 4611 frindex = EOREAD4(sc, EHCI_FRINDEX); 4612 frindex = frindex >> 3; /* Erase microframe index */ 4613 frindex += 2; 4614 } 4615 4616 if (frindex >= sc->sc_flsize) 4617 frindex &= (sc->sc_flsize - 1); 4618 4619 /* What's the frame interval? */ 4620 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4621 if (i / USB_UFRAMES_PER_FRAME == 0) 4622 i = 1; 4623 else 4624 i /= USB_UFRAMES_PER_FRAME; 4625 4626 itd = start; 4627 for (j = 0; j < frames; j++) { 4628 if (itd == NULL) 4629 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4630 4631 usb_syncmem(&sc->sc_fldma, 4632 sizeof(ehci_link_t) * frindex, 4633 sizeof(ehci_link_t), 4634 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4635 4636 itd->itd.itd_next = sc->sc_flist[frindex]; 4637 if (itd->itd.itd_next == 0) 4638 /* FIXME: frindex table gets initialized to NULL 4639 * or EHCI_NULL? */ 4640 itd->itd.itd_next = EHCI_NULL; 4641 4642 usb_syncmem(&itd->dma, 4643 itd->offs + offsetof(ehci_itd_t, itd_next), 4644 sizeof(itd->itd.itd_next), 4645 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4646 4647 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4648 4649 usb_syncmem(&sc->sc_fldma, 4650 sizeof(ehci_link_t) * frindex, 4651 sizeof(ehci_link_t), 4652 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4653 4654 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4655 sc->sc_softitds[frindex] = itd; 4656 if (itd->u.frame_list.next != NULL) 4657 itd->u.frame_list.next->u.frame_list.prev = itd; 4658 itd->slot = frindex; 4659 itd->u.frame_list.prev = NULL; 4660 4661 frindex += i; 4662 if (frindex >= sc->sc_flsize) 4663 frindex -= sc->sc_flsize; 4664 4665 itd = itd->xfer_next; 4666 } 4667 4668 epipe->u.isoc.cur_xfers++; 4669 epipe->u.isoc.next_frame = frindex; 4670 4671 exfer->ex_itdstart = start; 4672 exfer->ex_itdend = stop; 4673 4674 ehci_add_intr_list(sc, exfer); 4675 xfer->ux_status = USBD_IN_PROGRESS; 4676 xfer->ux_done = 0; 4677 mutex_exit(&sc->sc_lock); 4678 4679 if (sc->sc_bus.ub_usepolling) { 4680 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4681 ehci_waitintr(sc, xfer); 4682 } 4683 4684 return USBD_IN_PROGRESS; 4685 } 4686 4687 Static void 4688 ehci_device_isoc_abort(usbd_xfer_handle xfer) 4689 { 4690 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4691 4692 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4693 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4694 } 4695 4696 Static void 4697 ehci_device_isoc_close(usbd_pipe_handle pipe) 4698 { 4699 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4700 4701 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4702 } 4703 4704 Static void 4705 ehci_device_isoc_done(usbd_xfer_handle xfer) 4706 { 4707 struct ehci_xfer *exfer; 4708 ehci_softc_t *sc; 4709 struct ehci_pipe *epipe; 4710 4711 exfer = EXFER(xfer); 4712 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4713 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4714 4715 KASSERT(mutex_owned(&sc->sc_lock)); 4716 4717 epipe->u.isoc.cur_xfers--; 4718 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4719 ehci_del_intr_list(sc, exfer); 4720 ehci_rem_free_itd_chain(sc, exfer); 4721 } 4722 4723 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4724 BUS_DMASYNC_POSTREAD); 4725 4726 } 4727
Indexes created Thu Oct 02 01:09:59 GMT 2025