ehci.c revision 1.234.2.45
1 /* $NetBSD: ehci.c,v 1.234.2.45 2015/03/19 17:26:42 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004-2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Lennart Augustsson (lennart (at) augustsson.net), Charles M. Hannum, 9 * Jeremy Morse (jeremy.morse (at) gmail.com), Jared D. McNeill 10 * (jmcneill (at) invisible.ca) and Matthew R. Green (mrg (at) eterna.com.au). 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller. 36 * 37 * The EHCI 1.0 spec can be found at 38 * http://www.intel.com/technology/usb/spec.htm 39 * and the USB 2.0 spec at 40 * http://www.usb.org/developers/docs/ 41 * 42 */ 43 44 /* 45 * TODO: 46 * 1) hold off explorations by companion controllers until ehci has started. 47 * 48 * 2) The hub driver needs to handle and schedule the transaction translator, 49 * to assign place in frame where different devices get to go. See chapter 50 * on hubs in USB 2.0 for details. 51 * 52 * 3) Command failures are not recovered correctly. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: ehci.c,v 1.234.2.45 2015/03/19 17:26:42 skrll Exp $"); 57 58 #include "ohci.h" 59 #include "uhci.h" 60 #include "opt_usb.h" 61 62 #include <sys/param.h> 63 64 #include <sys/bus.h> 65 #include <sys/cpu.h> 66 #include <sys/device.h> 67 #include <sys/kernel.h> 68 #include <sys/kmem.h> 69 #include <sys/mutex.h> 70 #include <sys/proc.h> 71 #include <sys/queue.h> 72 #include <sys/select.h> 73 #include <sys/sysctl.h> 74 #include <sys/systm.h> 75 76 #include <machine/endian.h> 77 78 #include <dev/usb/usb.h> 79 #include <dev/usb/usbdi.h> 80 #include <dev/usb/usbdivar.h> 81 #include <dev/usb/usbhist.h> 82 #include <dev/usb/usb_mem.h> 83 #include <dev/usb/usb_quirks.h> 84 85 #include <dev/usb/ehcireg.h> 86 #include <dev/usb/ehcivar.h> 87 #include <dev/usb/usbroothub.h> 88 89 90 #ifdef USB_DEBUG 91 #ifndef EHCI_DEBUG 92 #define ehcidebug 0 93 #else 94 static int ehcidebug = 0; 95 96 SYSCTL_SETUP(sysctl_hw_ehci_setup, "sysctl hw.ehci setup") 97 { 98 int err; 99 const struct sysctlnode *rnode; 100 const struct sysctlnode *cnode; 101 102 err = sysctl_createv(clog, 0, NULL, &rnode, 103 CTLFLAG_PERMANENT, CTLTYPE_NODE, "ehci", 104 SYSCTL_DESCR("ehci global controls"), 105 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL); 106 107 if (err) 108 goto fail; 109 110 /* control debugging printfs */ 111 err = sysctl_createv(clog, 0, &rnode, &cnode, 112 CTLFLAG_PERMANENT|CTLFLAG_READWRITE, CTLTYPE_INT, 113 "debug", SYSCTL_DESCR("Enable debugging output"), 114 NULL, 0, &ehcidebug, sizeof(ehcidebug), CTL_CREATE, CTL_EOL); 115 if (err) 116 goto fail; 117 118 return; 119 fail: 120 aprint_error("%s: sysctl_createv failed (err = %d)\n", __func__, err); 121 } 122 123 #endif /* EHCI_DEBUG */ 124 #endif /* USB_DEBUG */ 125 126 struct ehci_pipe { 127 struct usbd_pipe pipe; 128 int nexttoggle; 129 130 ehci_soft_qh_t *sqh; 131 union { 132 ehci_soft_qtd_t *qtd; 133 /* ehci_soft_itd_t *itd; */ 134 /* ehci_soft_sitd_t *sitd; */ 135 } tail; 136 union { 137 /* Control pipe */ 138 struct { 139 usb_dma_t reqdma; 140 } ctl; 141 /* Interrupt pipe */ 142 struct { 143 u_int length; 144 } intr; 145 /* Bulk pipe */ 146 struct { 147 u_int length; 148 } bulk; 149 /* Iso pipe */ 150 struct { 151 u_int next_frame; 152 u_int cur_xfers; 153 } isoc; 154 } u; 155 }; 156 157 Static usbd_status ehci_open(struct usbd_pipe *); 158 Static void ehci_poll(struct usbd_bus *); 159 Static void ehci_softintr(void *); 160 Static int ehci_intr1(ehci_softc_t *); 161 Static void ehci_waitintr(ehci_softc_t *, struct usbd_xfer *); 162 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *); 163 Static void ehci_check_qh_intr(ehci_softc_t *, struct ehci_xfer *); 164 Static void ehci_check_itd_intr(ehci_softc_t *, struct ehci_xfer *); 165 Static void ehci_check_sitd_intr(ehci_softc_t *, struct ehci_xfer *); 166 Static void ehci_idone(struct ehci_xfer *); 167 Static void ehci_timeout(void *); 168 Static void ehci_timeout_task(void *); 169 Static void ehci_intrlist_timeout(void *); 170 Static void ehci_doorbell(void *); 171 Static void ehci_pcd(void *); 172 173 Static struct usbd_xfer * 174 ehci_allocx(struct usbd_bus *); 175 Static void ehci_freex(struct usbd_bus *, struct usbd_xfer *); 176 Static void ehci_get_lock(struct usbd_bus *, kmutex_t **); 177 Static int ehci_roothub_ctrl(struct usbd_bus *, 178 usb_device_request_t *, void *, int); 179 180 Static usbd_status ehci_root_intr_transfer(struct usbd_xfer *); 181 Static usbd_status ehci_root_intr_start(struct usbd_xfer *); 182 Static void ehci_root_intr_abort(struct usbd_xfer *); 183 Static void ehci_root_intr_close(struct usbd_pipe *); 184 Static void ehci_root_intr_done(struct usbd_xfer *); 185 186 Static usbd_status ehci_device_ctrl_transfer(struct usbd_xfer *); 187 Static usbd_status ehci_device_ctrl_start(struct usbd_xfer *); 188 Static void ehci_device_ctrl_abort(struct usbd_xfer *); 189 Static void ehci_device_ctrl_close(struct usbd_pipe *); 190 Static void ehci_device_ctrl_done(struct usbd_xfer *); 191 192 Static usbd_status ehci_device_bulk_transfer(struct usbd_xfer *); 193 Static usbd_status ehci_device_bulk_start(struct usbd_xfer *); 194 Static void ehci_device_bulk_abort(struct usbd_xfer *); 195 Static void ehci_device_bulk_close(struct usbd_pipe *); 196 Static void ehci_device_bulk_done(struct usbd_xfer *); 197 198 Static usbd_status ehci_device_intr_transfer(struct usbd_xfer *); 199 Static usbd_status ehci_device_intr_start(struct usbd_xfer *); 200 Static void ehci_device_intr_abort(struct usbd_xfer *); 201 Static void ehci_device_intr_close(struct usbd_pipe *); 202 Static void ehci_device_intr_done(struct usbd_xfer *); 203 204 Static usbd_status ehci_device_isoc_transfer(struct usbd_xfer *); 205 Static usbd_status ehci_device_isoc_start(struct usbd_xfer *); 206 Static void ehci_device_isoc_abort(struct usbd_xfer *); 207 Static void ehci_device_isoc_close(struct usbd_pipe *); 208 Static void ehci_device_isoc_done(struct usbd_xfer *); 209 210 Static usbd_status ehci_device_fs_isoc_transfer(struct usbd_xfer *); 211 Static usbd_status ehci_device_fs_isoc_start(struct usbd_xfer *); 212 Static void ehci_device_fs_isoc_abort(struct usbd_xfer *); 213 Static void ehci_device_fs_isoc_close(struct usbd_pipe *); 214 Static void ehci_device_fs_isoc_done(struct usbd_xfer *); 215 216 Static void ehci_device_clear_toggle(struct usbd_pipe *); 217 Static void ehci_noop(struct usbd_pipe *); 218 219 Static void ehci_disown(ehci_softc_t *, int, int); 220 221 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *); 222 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *); 223 224 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *); 225 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *); 226 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *, 227 ehci_softc_t *, int, int, struct usbd_xfer *, 228 ehci_soft_qtd_t **, ehci_soft_qtd_t **); 229 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *, 230 ehci_soft_qtd_t *); 231 232 Static ehci_soft_itd_t *ehci_alloc_itd(ehci_softc_t *); 233 Static ehci_soft_sitd_t *ehci_alloc_sitd(ehci_softc_t *); 234 Static void ehci_free_itd(ehci_softc_t *, ehci_soft_itd_t *); 235 Static void ehci_free_sitd(ehci_softc_t *, ehci_soft_sitd_t *); 236 Static void ehci_rem_free_itd_chain(ehci_softc_t *, 237 struct ehci_xfer *); 238 Static void ehci_rem_free_sitd_chain(ehci_softc_t *, 239 struct ehci_xfer *); 240 Static void ehci_abort_isoc_xfer(struct usbd_xfer *, 241 usbd_status); 242 243 Static usbd_status ehci_device_request(struct usbd_xfer *); 244 245 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *, 246 int); 247 248 Static void ehci_add_qh(ehci_softc_t *, ehci_soft_qh_t *, 249 ehci_soft_qh_t *); 250 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *, 251 ehci_soft_qh_t *); 252 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *); 253 Static void ehci_sync_hc(ehci_softc_t *); 254 255 Static void ehci_close_pipe(struct usbd_pipe *, ehci_soft_qh_t *); 256 Static void ehci_abort_xfer(struct usbd_xfer *, usbd_status); 257 258 #ifdef EHCI_DEBUG 259 Static ehci_softc_t *theehci; 260 void ehci_dump(void); 261 #endif 262 263 #ifdef EHCI_DEBUG 264 Static void ehci_dump_regs(ehci_softc_t *); 265 Static void ehci_dump_sqtds(ehci_soft_qtd_t *); 266 Static void ehci_dump_sqtd(ehci_soft_qtd_t *); 267 Static void ehci_dump_qtd(ehci_qtd_t *); 268 Static void ehci_dump_sqh(ehci_soft_qh_t *); 269 Static void ehci_dump_sitd(struct ehci_soft_itd *); 270 Static void ehci_dump_itd(struct ehci_soft_itd *); 271 Static void ehci_dump_exfer(struct ehci_xfer *); 272 #endif 273 274 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE) 275 276 #define ehci_add_intr_list(sc, ex) \ 277 TAILQ_INSERT_TAIL(&(sc)->sc_intrhead, (ex), ex_next); 278 #define ehci_del_intr_list(sc, ex) \ 279 do { \ 280 TAILQ_REMOVE(&sc->sc_intrhead, (ex), ex_next); \ 281 (ex)->ex_next.tqe_prev = NULL; \ 282 } while (0) 283 #define ehci_active_intr_list(ex) ((ex)->ex_next.tqe_prev != NULL) 284 285 Static const struct usbd_bus_methods ehci_bus_methods = { 286 .ubm_open = ehci_open, 287 .ubm_softint = ehci_softintr, 288 .ubm_dopoll = ehci_poll, 289 .ubm_allocx = ehci_allocx, 290 .ubm_freex = ehci_freex, 291 .ubm_getlock = ehci_get_lock, 292 .ubm_rhctrl = ehci_roothub_ctrl, 293 }; 294 295 Static const struct usbd_pipe_methods ehci_root_intr_methods = { 296 .upm_transfer = ehci_root_intr_transfer, 297 .upm_start = ehci_root_intr_start, 298 .upm_abort = ehci_root_intr_abort, 299 .upm_close = ehci_root_intr_close, 300 .upm_cleartoggle = ehci_noop, 301 .upm_done = ehci_root_intr_done, 302 }; 303 304 Static const struct usbd_pipe_methods ehci_device_ctrl_methods = { 305 .upm_transfer = ehci_device_ctrl_transfer, 306 .upm_start = ehci_device_ctrl_start, 307 .upm_abort = ehci_device_ctrl_abort, 308 .upm_close = ehci_device_ctrl_close, 309 .upm_cleartoggle = ehci_noop, 310 .upm_done = ehci_device_ctrl_done, 311 }; 312 313 Static const struct usbd_pipe_methods ehci_device_intr_methods = { 314 .upm_transfer = ehci_device_intr_transfer, 315 .upm_start = ehci_device_intr_start, 316 .upm_abort = ehci_device_intr_abort, 317 .upm_close = ehci_device_intr_close, 318 .upm_cleartoggle = ehci_device_clear_toggle, 319 .upm_done = ehci_device_intr_done, 320 }; 321 322 Static const struct usbd_pipe_methods ehci_device_bulk_methods = { 323 .upm_transfer = ehci_device_bulk_transfer, 324 .upm_start = ehci_device_bulk_start, 325 .upm_abort = ehci_device_bulk_abort, 326 .upm_close = ehci_device_bulk_close, 327 .upm_cleartoggle = ehci_device_clear_toggle, 328 .upm_done = ehci_device_bulk_done, 329 }; 330 331 Static const struct usbd_pipe_methods ehci_device_isoc_methods = { 332 .upm_transfer = ehci_device_isoc_transfer, 333 .upm_start = ehci_device_isoc_start, 334 .upm_abort = ehci_device_isoc_abort, 335 .upm_close = ehci_device_isoc_close, 336 .upm_cleartoggle = ehci_noop, 337 .upm_done = ehci_device_isoc_done, 338 }; 339 340 Static const struct usbd_pipe_methods ehci_device_fs_isoc_methods = { 341 .upm_transfer = ehci_device_fs_isoc_transfer, 342 .upm_start = ehci_device_fs_isoc_start, 343 .upm_abort = ehci_device_fs_isoc_abort, 344 .upm_close = ehci_device_fs_isoc_close, 345 .upm_cleartoggle = ehci_noop, 346 .upm_done = ehci_device_fs_isoc_done, 347 }; 348 349 static const uint8_t revbits[EHCI_MAX_POLLRATE] = { 350 0x00,0x40,0x20,0x60,0x10,0x50,0x30,0x70,0x08,0x48,0x28,0x68,0x18,0x58,0x38,0x78, 351 0x04,0x44,0x24,0x64,0x14,0x54,0x34,0x74,0x0c,0x4c,0x2c,0x6c,0x1c,0x5c,0x3c,0x7c, 352 0x02,0x42,0x22,0x62,0x12,0x52,0x32,0x72,0x0a,0x4a,0x2a,0x6a,0x1a,0x5a,0x3a,0x7a, 353 0x06,0x46,0x26,0x66,0x16,0x56,0x36,0x76,0x0e,0x4e,0x2e,0x6e,0x1e,0x5e,0x3e,0x7e, 354 0x01,0x41,0x21,0x61,0x11,0x51,0x31,0x71,0x09,0x49,0x29,0x69,0x19,0x59,0x39,0x79, 355 0x05,0x45,0x25,0x65,0x15,0x55,0x35,0x75,0x0d,0x4d,0x2d,0x6d,0x1d,0x5d,0x3d,0x7d, 356 0x03,0x43,0x23,0x63,0x13,0x53,0x33,0x73,0x0b,0x4b,0x2b,0x6b,0x1b,0x5b,0x3b,0x7b, 357 0x07,0x47,0x27,0x67,0x17,0x57,0x37,0x77,0x0f,0x4f,0x2f,0x6f,0x1f,0x5f,0x3f,0x7f, 358 }; 359 360 int 361 ehci_init(ehci_softc_t *sc) 362 { 363 uint32_t vers, sparams, cparams, hcr; 364 u_int i; 365 usbd_status err; 366 ehci_soft_qh_t *sqh; 367 u_int ncomp; 368 369 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 370 #ifdef EHCI_DEBUG 371 theehci = sc; 372 #endif 373 374 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_SOFTUSB); 375 mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_SCHED); 376 cv_init(&sc->sc_softwake_cv, "ehciab"); 377 cv_init(&sc->sc_doorbell, "ehcidi"); 378 379 sc->sc_xferpool = pool_cache_init(sizeof(struct ehci_xfer), 0, 0, 0, 380 "ehcixfer", NULL, IPL_USB, NULL, NULL, NULL); 381 382 sc->sc_doorbell_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 383 ehci_doorbell, sc); 384 KASSERT(sc->sc_doorbell_si != NULL); 385 sc->sc_pcd_si = softint_establish(SOFTINT_NET | SOFTINT_MPSAFE, 386 ehci_pcd, sc); 387 KASSERT(sc->sc_pcd_si != NULL); 388 389 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH); 390 391 vers = EREAD2(sc, EHCI_HCIVERSION); 392 aprint_verbose("%s: EHCI version %x.%x\n", device_xname(sc->sc_dev), 393 vers >> 8, vers & 0xff); 394 395 sparams = EREAD4(sc, EHCI_HCSPARAMS); 396 USBHIST_LOG(ehcidebug, "sparams=%#x", sparams, 0, 0, 0); 397 sc->sc_npcomp = EHCI_HCS_N_PCC(sparams); 398 ncomp = EHCI_HCS_N_CC(sparams); 399 if (ncomp != sc->sc_ncomp) { 400 aprint_verbose("%s: wrong number of companions (%d != %d)\n", 401 device_xname(sc->sc_dev), ncomp, sc->sc_ncomp); 402 #if NOHCI == 0 || NUHCI == 0 403 aprint_error("%s: ohci or uhci probably not configured\n", 404 device_xname(sc->sc_dev)); 405 #endif 406 if (ncomp < sc->sc_ncomp) 407 sc->sc_ncomp = ncomp; 408 } 409 if (sc->sc_ncomp > 0) { 410 KASSERT(!(sc->sc_flags & EHCIF_ETTF)); 411 aprint_normal("%s: companion controller%s, %d port%s each:", 412 device_xname(sc->sc_dev), sc->sc_ncomp!=1 ? "s" : "", 413 EHCI_HCS_N_PCC(sparams), 414 EHCI_HCS_N_PCC(sparams)!=1 ? "s" : ""); 415 for (i = 0; i < sc->sc_ncomp; i++) 416 aprint_normal(" %s", device_xname(sc->sc_comps[i])); 417 aprint_normal("\n"); 418 } 419 sc->sc_noport = EHCI_HCS_N_PORTS(sparams); 420 cparams = EREAD4(sc, EHCI_HCCPARAMS); 421 USBHIST_LOG(ehcidebug, "cparams=%#x", cparams, 0, 0, 0); 422 sc->sc_hasppc = EHCI_HCS_PPC(sparams); 423 424 if (EHCI_HCC_64BIT(cparams)) { 425 /* MUST clear segment register if 64 bit capable. */ 426 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 427 } 428 429 sc->sc_bus.ub_revision = USBREV_2_0; 430 sc->sc_bus.ub_usedma = true; 431 sc->sc_bus.ub_dmaflags = USBMALLOC_MULTISEG; 432 433 /* Reset the controller */ 434 USBHIST_LOG(ehcidebug, "resetting", 0, 0, 0, 0); 435 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 436 usb_delay_ms(&sc->sc_bus, 1); 437 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 438 for (i = 0; i < 100; i++) { 439 usb_delay_ms(&sc->sc_bus, 1); 440 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET; 441 if (!hcr) 442 break; 443 } 444 if (hcr) { 445 aprint_error("%s: reset timeout\n", device_xname(sc->sc_dev)); 446 return EIO; 447 } 448 if (sc->sc_vendor_init) 449 sc->sc_vendor_init(sc); 450 451 /* 452 * If we are doing embedded transaction translation function, force 453 * the controller to host mode. 454 */ 455 if (sc->sc_flags & EHCIF_ETTF) { 456 uint32_t usbmode = EREAD4(sc, EHCI_USBMODE); 457 usbmode &= ~EHCI_USBMODE_CM; 458 usbmode |= EHCI_USBMODE_CM_HOST; 459 EWRITE4(sc, EHCI_USBMODE, usbmode); 460 } 461 462 /* XXX need proper intr scheduling */ 463 sc->sc_rand = 96; 464 465 /* frame list size at default, read back what we got and use that */ 466 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) { 467 case 0: sc->sc_flsize = 1024; break; 468 case 1: sc->sc_flsize = 512; break; 469 case 2: sc->sc_flsize = 256; break; 470 case 3: return EIO; 471 } 472 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t), 473 EHCI_FLALIGN_ALIGN, &sc->sc_fldma); 474 if (err) 475 return err; 476 USBHIST_LOG(ehcidebug, "flsize=%d", sc->sc_flsize, 0, 0, 0); 477 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0); 478 479 for (i = 0; i < sc->sc_flsize; i++) { 480 sc->sc_flist[i] = EHCI_NULL; 481 } 482 483 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 484 485 sc->sc_softitds = kmem_zalloc(sc->sc_flsize * sizeof(ehci_soft_itd_t *), 486 KM_SLEEP); 487 if (sc->sc_softitds == NULL) 488 return ENOMEM; 489 LIST_INIT(&sc->sc_freeitds); 490 LIST_INIT(&sc->sc_freesitds); 491 TAILQ_INIT(&sc->sc_intrhead); 492 493 /* Set up the bus struct. */ 494 sc->sc_bus.ub_methods = &ehci_bus_methods; 495 sc->sc_bus.ub_pipesize= sizeof(struct ehci_pipe); 496 497 sc->sc_eintrs = EHCI_NORMAL_INTRS; 498 499 /* 500 * Allocate the interrupt dummy QHs. These are arranged to give poll 501 * intervals that are powers of 2 times 1ms. 502 */ 503 for (i = 0; i < EHCI_INTRQHS; i++) { 504 sqh = ehci_alloc_sqh(sc); 505 if (sqh == NULL) { 506 err = ENOMEM; 507 goto bad1; 508 } 509 sc->sc_islots[i].sqh = sqh; 510 } 511 for (i = 0; i < EHCI_INTRQHS; i++) { 512 sqh = sc->sc_islots[i].sqh; 513 if (i == 0) { 514 /* The last (1ms) QH terminates. */ 515 sqh->qh.qh_link = EHCI_NULL; 516 sqh->next = NULL; 517 } else { 518 /* Otherwise the next QH has half the poll interval */ 519 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh; 520 sqh->qh.qh_link = htole32(sqh->next->physaddr | 521 EHCI_LINK_QH); 522 } 523 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH)); 524 sqh->qh.qh_curqtd = EHCI_NULL; 525 sqh->next = NULL; 526 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 527 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 528 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 529 sqh->sqtd = NULL; 530 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 531 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 532 } 533 /* Point the frame list at the last level (128ms). */ 534 for (i = 0; i < sc->sc_flsize; i++) { 535 int j; 536 537 j = (i & ~(EHCI_MAX_POLLRATE-1)) | 538 revbits[i & (EHCI_MAX_POLLRATE-1)]; 539 sc->sc_flist[j] = htole32(EHCI_LINK_QH | 540 sc->sc_islots[EHCI_IQHIDX(EHCI_IPOLLRATES - 1, 541 i)].sqh->physaddr); 542 } 543 usb_syncmem(&sc->sc_fldma, 0, sc->sc_flsize * sizeof(ehci_link_t), 544 BUS_DMASYNC_PREWRITE); 545 546 /* Allocate dummy QH that starts the async list. */ 547 sqh = ehci_alloc_sqh(sc); 548 if (sqh == NULL) { 549 err = ENOMEM; 550 goto bad1; 551 } 552 /* Fill the QH */ 553 sqh->qh.qh_endp = 554 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL); 555 sqh->qh.qh_link = 556 htole32(sqh->physaddr | EHCI_LINK_QH); 557 sqh->qh.qh_curqtd = EHCI_NULL; 558 sqh->next = NULL; 559 /* Fill the overlay qTD */ 560 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 561 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 562 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED); 563 sqh->sqtd = NULL; 564 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 565 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 566 #ifdef EHCI_DEBUG 567 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 568 ehci_dump_sqh(sqh); 569 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 570 #endif 571 572 /* Point to async list */ 573 sc->sc_async_head = sqh; 574 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH); 575 576 callout_init(&sc->sc_tmo_intrlist, CALLOUT_MPSAFE); 577 578 /* Turn on controller */ 579 EOWRITE4(sc, EHCI_USBCMD, 580 EHCI_CMD_ITC_2 | /* 2 microframes interrupt delay */ 581 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) | 582 EHCI_CMD_ASE | 583 EHCI_CMD_PSE | 584 EHCI_CMD_RS); 585 586 /* Take over port ownership */ 587 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF); 588 589 for (i = 0; i < 100; i++) { 590 usb_delay_ms(&sc->sc_bus, 1); 591 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 592 if (!hcr) 593 break; 594 } 595 if (hcr) { 596 aprint_error("%s: run timeout\n", device_xname(sc->sc_dev)); 597 return EIO; 598 } 599 600 /* Enable interrupts */ 601 USBHIST_LOG(ehcidebug, "enabling interupts", 0, 0, 0, 0); 602 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 603 604 return 0; 605 606 #if 0 607 bad2: 608 ehci_free_sqh(sc, sc->sc_async_head); 609 #endif 610 bad1: 611 usb_freemem(&sc->sc_bus, &sc->sc_fldma); 612 return err; 613 } 614 615 int 616 ehci_intr(void *v) 617 { 618 ehci_softc_t *sc = v; 619 int ret = 0; 620 621 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 622 623 if (sc == NULL) 624 return 0; 625 626 mutex_spin_enter(&sc->sc_intr_lock); 627 628 if (sc->sc_dying || !device_has_power(sc->sc_dev)) 629 goto done; 630 631 /* If we get an interrupt while polling, then just ignore it. */ 632 if (sc->sc_bus.ub_usepolling) { 633 uint32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 634 635 if (intrs) 636 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 637 USBHIST_LOGN(ehcidebug, 16, 638 "ignored interrupt while polling", 0, 0, 0, 0); 639 goto done; 640 } 641 642 ret = ehci_intr1(sc); 643 644 done: 645 mutex_spin_exit(&sc->sc_intr_lock); 646 return ret; 647 } 648 649 Static int 650 ehci_intr1(ehci_softc_t *sc) 651 { 652 uint32_t intrs, eintrs; 653 654 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 655 656 /* In case the interrupt occurs before initialization has completed. */ 657 if (sc == NULL) { 658 #ifdef DIAGNOSTIC 659 printf("ehci_intr1: sc == NULL\n"); 660 #endif 661 return 0; 662 } 663 664 KASSERT(mutex_owned(&sc->sc_intr_lock)); 665 666 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 667 if (!intrs) 668 return 0; 669 670 eintrs = intrs & sc->sc_eintrs; 671 USBHIST_LOG(ehcidebug, "sc=%p intrs=%#x(%#x) eintrs=%#x", 672 sc, intrs, EOREAD4(sc, EHCI_USBSTS), eintrs); 673 if (!eintrs) 674 return 0; 675 676 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */ 677 if (eintrs & EHCI_STS_IAA) { 678 USBHIST_LOG(ehcidebug, "door bell", 0, 0, 0, 0); 679 kpreempt_disable(); 680 KASSERT(sc->sc_doorbell_si != NULL); 681 softint_schedule(sc->sc_doorbell_si); 682 kpreempt_enable(); 683 eintrs &= ~EHCI_STS_IAA; 684 } 685 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) { 686 USBHIST_LOG(ehcidebug, "INT=%d ERRINT=%d", 687 eintrs & EHCI_STS_INT ? 1 : 0, 688 eintrs & EHCI_STS_ERRINT ? 1 : 0, 0, 0); 689 usb_schedsoftintr(&sc->sc_bus); 690 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT); 691 } 692 if (eintrs & EHCI_STS_HSE) { 693 printf("%s: unrecoverable error, controller halted\n", 694 device_xname(sc->sc_dev)); 695 /* XXX what else */ 696 } 697 if (eintrs & EHCI_STS_PCD) { 698 kpreempt_disable(); 699 KASSERT(sc->sc_pcd_si != NULL); 700 softint_schedule(sc->sc_pcd_si); 701 kpreempt_enable(); 702 eintrs &= ~EHCI_STS_PCD; 703 } 704 705 if (eintrs != 0) { 706 /* Block unprocessed interrupts. */ 707 sc->sc_eintrs &= ~eintrs; 708 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 709 printf("%s: blocking intrs 0x%x\n", 710 device_xname(sc->sc_dev), eintrs); 711 } 712 713 return 1; 714 } 715 716 Static void 717 ehci_doorbell(void *addr) 718 { 719 ehci_softc_t *sc = addr; 720 721 mutex_enter(&sc->sc_lock); 722 cv_broadcast(&sc->sc_doorbell); 723 mutex_exit(&sc->sc_lock); 724 } 725 726 Static void 727 ehci_pcd(void *addr) 728 { 729 ehci_softc_t *sc = addr; 730 struct usbd_xfer *xfer; 731 u_char *p; 732 int i, m; 733 734 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 735 736 mutex_enter(&sc->sc_lock); 737 xfer = sc->sc_intrxfer; 738 739 if (xfer == NULL) { 740 /* Just ignore the change. */ 741 goto done; 742 } 743 744 p = xfer->ux_buf; 745 m = min(sc->sc_noport, xfer->ux_length * 8 - 1); 746 memset(p, 0, xfer->ux_length); 747 for (i = 1; i <= m; i++) { 748 /* Pick out CHANGE bits from the status reg. */ 749 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) 750 p[i/8] |= 1 << (i%8); 751 if (i % 8 == 7) 752 USBHIST_LOG(ehcidebug, "change(%d)=0x%02x", i / 8, 753 p[i/8], 0, 0); 754 } 755 xfer->ux_actlen = xfer->ux_length; 756 xfer->ux_status = USBD_NORMAL_COMPLETION; 757 758 usb_transfer_complete(xfer); 759 760 done: 761 mutex_exit(&sc->sc_lock); 762 } 763 764 Static void 765 ehci_softintr(void *v) 766 { 767 struct usbd_bus *bus = v; 768 ehci_softc_t *sc = bus->ub_hcpriv; 769 struct ehci_xfer *ex, *nextex; 770 771 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 772 773 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 774 775 /* 776 * The only explanation I can think of for why EHCI is as brain dead 777 * as UHCI interrupt-wise is that Intel was involved in both. 778 * An interrupt just tells us that something is done, we have no 779 * clue what, so we need to scan through all active transfers. :-( 780 */ 781 for (ex = TAILQ_FIRST(&sc->sc_intrhead); ex; ex = nextex) { 782 nextex = TAILQ_NEXT(ex, ex_next); 783 ehci_check_intr(sc, ex); 784 } 785 786 /* Schedule a callout to catch any dropped transactions. */ 787 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) && 788 !TAILQ_EMPTY(&sc->sc_intrhead)) 789 callout_reset(&sc->sc_tmo_intrlist, 790 hz, ehci_intrlist_timeout, sc); 791 792 if (sc->sc_softwake) { 793 sc->sc_softwake = 0; 794 cv_broadcast(&sc->sc_softwake_cv); 795 } 796 } 797 798 /* Check for an interrupt. */ 799 Static void 800 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 801 { 802 struct usbd_device *dev = ex->ex_xfer.ux_pipe->up_dev; 803 int attr; 804 805 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 806 USBHIST_LOG(ehcidebug, "ex = %p", ex, 0, 0, 0); 807 808 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 809 810 attr = ex->ex_xfer.ux_pipe->up_endpoint->ue_edesc->bmAttributes; 811 if (UE_GET_XFERTYPE(attr) == UE_ISOCHRONOUS) { 812 if (dev->ud_speed == USB_SPEED_HIGH) 813 ehci_check_itd_intr(sc, ex); 814 else 815 ehci_check_sitd_intr(sc, ex); 816 } else 817 ehci_check_qh_intr(sc, ex); 818 819 return; 820 } 821 822 Static void 823 ehci_check_qh_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 824 { 825 ehci_soft_qtd_t *sqtd, *lsqtd; 826 uint32_t status; 827 828 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 829 830 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 831 832 if (ex->ex_sqtdstart == NULL) { 833 printf("ehci_check_qh_intr: not valid sqtd\n"); 834 return; 835 } 836 837 lsqtd = ex->ex_sqtdend; 838 #ifdef DIAGNOSTIC 839 if (lsqtd == NULL) { 840 printf("ehci_check_qh_intr: lsqtd==0\n"); 841 return; 842 } 843 #endif 844 /* 845 * If the last TD is still active we need to check whether there 846 * is an error somewhere in the middle, or whether there was a 847 * short packet (SPD and not ACTIVE). 848 */ 849 usb_syncmem(&lsqtd->dma, 850 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 851 sizeof(lsqtd->qtd.qtd_status), 852 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 853 status = le32toh(lsqtd->qtd.qtd_status); 854 usb_syncmem(&lsqtd->dma, 855 lsqtd->offs + offsetof(ehci_qtd_t, qtd_status), 856 sizeof(lsqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 857 if (status & EHCI_QTD_ACTIVE) { 858 USBHIST_LOGN(ehcidebug, 10, "active ex=%p", ex, 0, 0, 0); 859 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd; 860 sqtd = sqtd->nextqtd) { 861 usb_syncmem(&sqtd->dma, 862 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 863 sizeof(sqtd->qtd.qtd_status), 864 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 865 status = le32toh(sqtd->qtd.qtd_status); 866 usb_syncmem(&sqtd->dma, 867 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 868 sizeof(sqtd->qtd.qtd_status), BUS_DMASYNC_PREREAD); 869 /* If there's an active QTD the xfer isn't done. */ 870 if (status & EHCI_QTD_ACTIVE) 871 break; 872 /* Any kind of error makes the xfer done. */ 873 if (status & EHCI_QTD_HALTED) 874 goto done; 875 /* Handle short packets */ 876 if (EHCI_QTD_GET_BYTES(status) != 0) { 877 struct usbd_pipe *pipe = ex->ex_xfer.ux_pipe; 878 usb_endpoint_descriptor_t *ed = 879 pipe->up_endpoint->ue_edesc; 880 uint8_t xt = UE_GET_XFERTYPE(ed->bmAttributes); 881 882 /* 883 * If we get here for a control transfer then 884 * we need to let the hardware complete the 885 * status phase. That is, we're not done 886 * quite yet. 887 * 888 * Otherwise, we're done. 889 */ 890 if (xt == UE_CONTROL) { 891 break; 892 } 893 goto done; 894 } 895 } 896 USBHIST_LOGN(ehcidebug, 10, "ex=%p std=%p still active", 897 ex, ex->ex_sqtdstart, 0, 0); 898 #ifdef EHCI_DEBUG 899 USBHIST_LOGN(ehcidebug, 5, "--- still active start ---", 0, 0, 0, 0); 900 ehci_dump_sqtds(ex->ex_sqtdstart); 901 USBHIST_LOGN(ehcidebug, 5, "--- still active end ---", 0, 0, 0, 0); 902 #endif 903 return; 904 } 905 done: 906 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 907 callout_stop(&ex->ex_xfer.ux_callout); 908 ehci_idone(ex); 909 } 910 911 Static void 912 ehci_check_itd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 913 { 914 ehci_soft_itd_t *itd; 915 int i; 916 917 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 918 919 KASSERT(mutex_owned(&sc->sc_lock)); 920 921 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 922 return; 923 924 if (ex->ex_itdstart == NULL) { 925 printf("ehci_check_itd_intr: not valid itd\n"); 926 return; 927 } 928 929 itd = ex->ex_itdend; 930 #ifdef DIAGNOSTIC 931 if (itd == NULL) { 932 printf("ehci_check_itd_intr: itdend == 0\n"); 933 return; 934 } 935 #endif 936 937 /* 938 * check no active transfers in last itd, meaning we're finished 939 */ 940 941 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 942 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 943 BUS_DMASYNC_POSTREAD); 944 945 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 946 if (le32toh(itd->itd.itd_ctl[i]) & EHCI_ITD_ACTIVE) 947 break; 948 } 949 950 if (i == EHCI_ITD_NUFRAMES) { 951 goto done; /* All 8 descriptors inactive, it's done */ 952 } 953 954 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_ctl), 955 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 956 957 USBHIST_LOGN(ehcidebug, 10, "ex %p itd %p still active", ex, 958 ex->ex_itdstart, 0, 0); 959 return; 960 done: 961 USBHIST_LOG(ehcidebug, "ex %p done", ex, 0, 0, 0); 962 callout_stop(&ex->ex_xfer.ux_callout); 963 ehci_idone(ex); 964 } 965 966 void 967 ehci_check_sitd_intr(ehci_softc_t *sc, struct ehci_xfer *ex) 968 { 969 ehci_soft_sitd_t *sitd; 970 971 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 972 973 KASSERT(mutex_owned(&sc->sc_lock)); 974 975 if (&ex->ex_xfer != SIMPLEQ_FIRST(&ex->ex_xfer.ux_pipe->up_queue)) 976 return; 977 978 if (ex->ex_sitdstart == NULL) { 979 printf("ehci_check_sitd_intr: not valid sitd\n"); 980 return; 981 } 982 983 sitd = ex->ex_sitdend; 984 #ifdef DIAGNOSTIC 985 if (sitd == NULL) { 986 printf("ehci_check_sitd_intr: sitdend == 0\n"); 987 return; 988 } 989 #endif 990 991 /* 992 * check no active transfers in last sitd, meaning we're finished 993 */ 994 995 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 996 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_POSTWRITE | 997 BUS_DMASYNC_POSTREAD); 998 999 if (le32toh(sitd->sitd.sitd_trans) & EHCI_SITD_ACTIVE) 1000 return; 1001 1002 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1003 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1004 1005 USBHIST_LOGN(ehcidebug, 10, "ex=%p done", ex, 0, 0, 0); 1006 callout_stop(&(ex->ex_xfer.ux_callout)); 1007 ehci_idone(ex); 1008 } 1009 1010 1011 Static void 1012 ehci_idone(struct ehci_xfer *ex) 1013 { 1014 struct usbd_xfer *xfer = &ex->ex_xfer; 1015 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 1016 struct ehci_softc *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 1017 ehci_soft_qtd_t *sqtd, *lsqtd; 1018 uint32_t status = 0, nstatus = 0; 1019 int actlen; 1020 1021 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1022 1023 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 1024 1025 USBHIST_LOG(ehcidebug, "ex=%p", ex, 0, 0, 0); 1026 1027 #ifdef DIAGNOSTIC 1028 #ifdef EHCI_DEBUG 1029 if (ex->ex_isdone) { 1030 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1031 ehci_dump_exfer(ex); 1032 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1033 } 1034 #endif 1035 KASSERT(!ex->ex_isdone); 1036 ex->ex_isdone = true; 1037 #endif 1038 1039 if (xfer->ux_status == USBD_CANCELLED || 1040 xfer->ux_status == USBD_TIMEOUT) { 1041 USBHIST_LOG(ehcidebug, "aborted xfer=%p", xfer, 0, 0, 0); 1042 return; 1043 } 1044 1045 USBHIST_LOG(ehcidebug, "xfer=%p, pipe=%p ready", xfer, epipe, 0, 0); 1046 1047 /* The transfer is done, compute actual length and status. */ 1048 1049 u_int xfertype, speed; 1050 1051 xfertype = UE_GET_XFERTYPE(xfer->ux_pipe->up_endpoint->ue_edesc->bmAttributes); 1052 speed = xfer->ux_pipe->up_dev->ud_speed; 1053 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_HIGH) { 1054 /* HS isoc transfer */ 1055 1056 struct ehci_soft_itd *itd; 1057 int i, nframes, len, uframes; 1058 1059 nframes = 0; 1060 actlen = 0; 1061 1062 i = xfer->ux_pipe->up_endpoint->ue_edesc->bInterval; 1063 uframes = min(1 << (i - 1), USB_UFRAMES_PER_FRAME); 1064 1065 for (itd = ex->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 1066 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1067 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_POSTWRITE | 1068 BUS_DMASYNC_POSTREAD); 1069 1070 for (i = 0; i < EHCI_ITD_NUFRAMES; i += uframes) { 1071 /* 1072 * XXX - driver didn't fill in the frame full 1073 * of uframes. This leads to scheduling 1074 * inefficiencies, but working around 1075 * this doubles complexity of tracking 1076 * an xfer. 1077 */ 1078 if (nframes >= xfer->ux_nframes) 1079 break; 1080 1081 status = le32toh(itd->itd.itd_ctl[i]); 1082 len = EHCI_ITD_GET_LEN(status); 1083 if (EHCI_ITD_GET_STATUS(status) != 0) 1084 len = 0; /*No valid data on error*/ 1085 1086 xfer->ux_frlengths[nframes++] = len; 1087 actlen += len; 1088 } 1089 usb_syncmem(&itd->dma,itd->offs + offsetof(ehci_itd_t,itd_ctl), 1090 sizeof(itd->itd.itd_ctl), BUS_DMASYNC_PREREAD); 1091 1092 if (nframes >= xfer->ux_nframes) 1093 break; 1094 } 1095 1096 xfer->ux_actlen = actlen; 1097 xfer->ux_status = USBD_NORMAL_COMPLETION; 1098 goto end; 1099 } 1100 1101 if (xfertype == UE_ISOCHRONOUS && speed == USB_SPEED_FULL) { 1102 /* FS isoc transfer */ 1103 struct ehci_soft_sitd *sitd; 1104 int nframes, len; 1105 1106 nframes = 0; 1107 actlen = 0; 1108 1109 for (sitd = ex->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 1110 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1111 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_POSTWRITE | 1112 BUS_DMASYNC_POSTREAD); 1113 1114 /* 1115 * XXX - driver didn't fill in the frame full 1116 * of uframes. This leads to scheduling 1117 * inefficiencies, but working around 1118 * this doubles complexity of tracking 1119 * an xfer. 1120 */ 1121 if (nframes >= xfer->ux_nframes) 1122 break; 1123 1124 status = le32toh(sitd->sitd.sitd_trans); 1125 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 1126 sizeof(sitd->sitd.sitd_trans), BUS_DMASYNC_PREREAD); 1127 1128 len = EHCI_SITD_GET_LEN(status); 1129 if (status & (EHCI_SITD_ERR|EHCI_SITD_BUFERR| 1130 EHCI_SITD_BABBLE|EHCI_SITD_XACTERR|EHCI_SITD_MISS)) { 1131 /* No valid data on error */ 1132 len = xfer->ux_frlengths[nframes]; 1133 } 1134 1135 /* 1136 * frlengths[i]: # of bytes to send 1137 * len: # of bytes host didn't send 1138 */ 1139 xfer->ux_frlengths[nframes] -= len; 1140 /* frlengths[i]: # of bytes host sent */ 1141 actlen += xfer->ux_frlengths[nframes++]; 1142 1143 if (nframes >= xfer->ux_nframes) 1144 break; 1145 } 1146 1147 xfer->ux_actlen = actlen; 1148 xfer->ux_status = USBD_NORMAL_COMPLETION; 1149 goto end; 1150 } 1151 KASSERT(xfertype != UE_ISOCHRONOUS); 1152 1153 /* Continue processing xfers using queue heads */ 1154 1155 #ifdef EHCI_DEBUG 1156 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1157 ehci_dump_sqtds(ex->ex_sqtdstart); 1158 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1159 #endif 1160 1161 lsqtd = ex->ex_sqtdend; 1162 actlen = 0; 1163 for (sqtd = ex->ex_sqtdstart; sqtd != lsqtd->nextqtd; 1164 sqtd = sqtd->nextqtd) { 1165 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1166 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1167 nstatus = le32toh(sqtd->qtd.qtd_status); 1168 usb_syncmem(&sqtd->dma, sqtd->offs, sizeof(sqtd->qtd), 1169 BUS_DMASYNC_PREREAD); 1170 if (nstatus & EHCI_QTD_ACTIVE) 1171 break; 1172 1173 status = nstatus; 1174 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP) 1175 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status); 1176 } 1177 1178 1179 /* 1180 * If there are left over TDs we need to update the toggle. 1181 * The default pipe doesn't need it since control transfers 1182 * start the toggle at 0 every time. 1183 * For a short transfer we need to update the toggle for the missing 1184 * packets within the qTD. 1185 */ 1186 if ((sqtd != lsqtd->nextqtd || EHCI_QTD_GET_BYTES(status)) && 1187 xfer->ux_pipe->up_dev->ud_pipe0 != xfer->ux_pipe) { 1188 USBHIST_LOG(ehcidebug, 1189 "toggle update status=0x%08x nstatus=0x%08x", 1190 status, nstatus, 0, 0); 1191 #if 0 1192 ehci_dump_sqh(epipe->sqh); 1193 ehci_dump_sqtds(ex->ex_sqtdstart); 1194 #endif 1195 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus); 1196 } 1197 1198 USBHIST_LOG(ehcidebug, "len=%d actlen=%d status=0x%08x", xfer->ux_length, 1199 actlen, status, 0); 1200 xfer->ux_actlen = actlen; 1201 if (status & EHCI_QTD_HALTED) { 1202 #ifdef EHCI_DEBUG 1203 USBHIST_LOG(ehcidebug, "halted addr=%d endpt=0x%02x", 1204 xfer->ux_pipe->up_dev->ud_addr, 1205 xfer->ux_pipe->up_endpoint->ue_edesc->bEndpointAddress, 0, 0); 1206 USBHIST_LOG(ehcidebug, "cerr=%d pid=%d", 1207 EHCI_QTD_GET_CERR(status), EHCI_QTD_GET_PID(status), 1208 0, 0); 1209 USBHIST_LOG(ehcidebug, 1210 "active =%d halted=%d buferr=%d babble=%d", 1211 status & EHCI_QTD_ACTIVE ? 1 : 0, 1212 status & EHCI_QTD_HALTED ? 1 : 0, 1213 status & EHCI_QTD_BUFERR ? 1 : 0, 1214 status & EHCI_QTD_BABBLE ? 1 : 0); 1215 1216 USBHIST_LOG(ehcidebug, 1217 "xacterr=%d missed=%d split =%d ping =%d", 1218 status & EHCI_QTD_XACTERR ? 1 : 0, 1219 status & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1220 status & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1221 status & EHCI_QTD_PINGSTATE ? 1 : 0); 1222 1223 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 1224 ehci_dump_sqh(epipe->sqh); 1225 ehci_dump_sqtds(ex->ex_sqtdstart); 1226 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 1227 #endif 1228 /* low&full speed has an extra error flag */ 1229 if (EHCI_QH_GET_EPS(epipe->sqh->qh.qh_endp) != 1230 EHCI_QH_SPEED_HIGH) 1231 status &= EHCI_QTD_STATERRS | EHCI_QTD_PINGSTATE; 1232 else 1233 status &= EHCI_QTD_STATERRS; 1234 if (status == 0) /* no other errors means a stall */ { 1235 xfer->ux_status = USBD_STALLED; 1236 } else { 1237 xfer->ux_status = USBD_IOERROR; /* more info XXX */ 1238 } 1239 /* XXX need to reset TT on missed microframe */ 1240 if (status & EHCI_QTD_MISSEDMICRO) { 1241 printf("%s: missed microframe, TT reset not " 1242 "implemented, hub might be inoperational\n", 1243 device_xname(sc->sc_dev)); 1244 } 1245 } else { 1246 xfer->ux_status = USBD_NORMAL_COMPLETION; 1247 } 1248 1249 end: 1250 /* 1251 * XXX transfer_complete memcpys out transfer data (for in endpoints) 1252 * during this call, before methods->done is called: dma sync required 1253 * beforehand? 1254 */ 1255 usb_transfer_complete(xfer); 1256 USBHIST_LOG(ehcidebug, "ex=%p done", ex, 0, 0, 0); 1257 } 1258 1259 /* 1260 * Wait here until controller claims to have an interrupt. 1261 * Then call ehci_intr and return. Use timeout to avoid waiting 1262 * too long. 1263 */ 1264 Static void 1265 ehci_waitintr(ehci_softc_t *sc, struct usbd_xfer *xfer) 1266 { 1267 int timo; 1268 uint32_t intrs; 1269 1270 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1271 1272 xfer->ux_status = USBD_IN_PROGRESS; 1273 for (timo = xfer->ux_timeout; timo >= 0; timo--) { 1274 usb_delay_ms(&sc->sc_bus, 1); 1275 if (sc->sc_dying) 1276 break; 1277 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) & 1278 sc->sc_eintrs; 1279 USBHIST_LOG(ehcidebug, "0x%04x", intrs, 0, 0, 0); 1280 #ifdef EHCI_DEBUG 1281 if (ehcidebug > 15) 1282 ehci_dump_regs(sc); 1283 #endif 1284 if (intrs) { 1285 mutex_spin_enter(&sc->sc_intr_lock); 1286 ehci_intr1(sc); 1287 mutex_spin_exit(&sc->sc_intr_lock); 1288 if (xfer->ux_status != USBD_IN_PROGRESS) 1289 return; 1290 } 1291 } 1292 1293 /* Timeout */ 1294 USBHIST_LOG(ehcidebug, "timeout", 0, 0, 0, 0); 1295 xfer->ux_status = USBD_TIMEOUT; 1296 mutex_enter(&sc->sc_lock); 1297 usb_transfer_complete(xfer); 1298 mutex_exit(&sc->sc_lock); 1299 /* XXX should free TD */ 1300 } 1301 1302 Static void 1303 ehci_poll(struct usbd_bus *bus) 1304 { 1305 ehci_softc_t *sc = bus->ub_hcpriv; 1306 1307 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1308 1309 #ifdef EHCI_DEBUG 1310 static int last; 1311 int new; 1312 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)); 1313 if (new != last) { 1314 USBHIST_LOG(ehcidebug, "intrs=0x%04x", new, 0, 0, 0); 1315 last = new; 1316 } 1317 #endif 1318 1319 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs) { 1320 mutex_spin_enter(&sc->sc_intr_lock); 1321 ehci_intr1(sc); 1322 mutex_spin_exit(&sc->sc_intr_lock); 1323 } 1324 } 1325 1326 void 1327 ehci_childdet(device_t self, device_t child) 1328 { 1329 struct ehci_softc *sc = device_private(self); 1330 1331 KASSERT(sc->sc_child == child); 1332 sc->sc_child = NULL; 1333 } 1334 1335 int 1336 ehci_detach(struct ehci_softc *sc, int flags) 1337 { 1338 int rv = 0; 1339 1340 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1341 1342 if (sc->sc_child != NULL) 1343 rv = config_detach(sc->sc_child, flags); 1344 1345 if (rv != 0) 1346 return rv; 1347 1348 callout_halt(&sc->sc_tmo_intrlist, NULL); 1349 callout_destroy(&sc->sc_tmo_intrlist); 1350 1351 /* XXX free other data structures XXX */ 1352 if (sc->sc_softitds) 1353 kmem_free(sc->sc_softitds, 1354 sc->sc_flsize * sizeof(ehci_soft_itd_t *)); 1355 cv_destroy(&sc->sc_doorbell); 1356 cv_destroy(&sc->sc_softwake_cv); 1357 1358 #if 0 1359 /* XXX destroyed in ehci_pci.c as it controls ehci_intr access */ 1360 1361 softint_disestablish(sc->sc_doorbell_si); 1362 softint_disestablish(sc->sc_pcd_si); 1363 1364 mutex_destroy(&sc->sc_lock); 1365 mutex_destroy(&sc->sc_intr_lock); 1366 #endif 1367 1368 pool_cache_destroy(sc->sc_xferpool); 1369 1370 EOWRITE4(sc, EHCI_CONFIGFLAG, 0); 1371 1372 return rv; 1373 } 1374 1375 1376 int 1377 ehci_activate(device_t self, enum devact act) 1378 { 1379 struct ehci_softc *sc = device_private(self); 1380 1381 switch (act) { 1382 case DVACT_DEACTIVATE: 1383 sc->sc_dying = 1; 1384 return 0; 1385 default: 1386 return EOPNOTSUPP; 1387 } 1388 } 1389 1390 /* 1391 * Handle suspend/resume. 1392 * 1393 * We need to switch to polling mode here, because this routine is 1394 * called from an interrupt context. This is all right since we 1395 * are almost suspended anyway. 1396 * 1397 * Note that this power handler isn't to be registered directly; the 1398 * bus glue needs to call out to it. 1399 */ 1400 bool 1401 ehci_suspend(device_t dv, const pmf_qual_t *qual) 1402 { 1403 ehci_softc_t *sc = device_private(dv); 1404 int i; 1405 uint32_t cmd, hcr; 1406 1407 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1408 1409 mutex_spin_enter(&sc->sc_intr_lock); 1410 sc->sc_bus.ub_usepolling++; 1411 mutex_spin_exit(&sc->sc_intr_lock); 1412 1413 for (i = 1; i <= sc->sc_noport; i++) { 1414 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1415 if ((cmd & EHCI_PS_PO) == 0 && (cmd & EHCI_PS_PE) == EHCI_PS_PE) 1416 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_SUSP); 1417 } 1418 1419 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD); 1420 1421 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE); 1422 EOWRITE4(sc, EHCI_USBCMD, cmd); 1423 1424 for (i = 0; i < 100; i++) { 1425 hcr = EOREAD4(sc, EHCI_USBSTS) & (EHCI_STS_ASS | EHCI_STS_PSS); 1426 if (hcr == 0) 1427 break; 1428 1429 usb_delay_ms(&sc->sc_bus, 1); 1430 } 1431 if (hcr != 0) 1432 printf("%s: reset timeout\n", device_xname(dv)); 1433 1434 cmd &= ~EHCI_CMD_RS; 1435 EOWRITE4(sc, EHCI_USBCMD, cmd); 1436 1437 for (i = 0; i < 100; i++) { 1438 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1439 if (hcr == EHCI_STS_HCH) 1440 break; 1441 1442 usb_delay_ms(&sc->sc_bus, 1); 1443 } 1444 if (hcr != EHCI_STS_HCH) 1445 printf("%s: config timeout\n", device_xname(dv)); 1446 1447 mutex_spin_enter(&sc->sc_intr_lock); 1448 sc->sc_bus.ub_usepolling--; 1449 mutex_spin_exit(&sc->sc_intr_lock); 1450 1451 return true; 1452 } 1453 1454 bool 1455 ehci_resume(device_t dv, const pmf_qual_t *qual) 1456 { 1457 ehci_softc_t *sc = device_private(dv); 1458 int i; 1459 uint32_t cmd, hcr; 1460 1461 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1462 1463 /* restore things in case the bios sucks */ 1464 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0); 1465 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0)); 1466 EOWRITE4(sc, EHCI_ASYNCLISTADDR, 1467 sc->sc_async_head->physaddr | EHCI_LINK_QH); 1468 1469 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs & ~EHCI_INTR_PCIE); 1470 1471 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1472 1473 hcr = 0; 1474 for (i = 1; i <= sc->sc_noport; i++) { 1475 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1476 if ((cmd & EHCI_PS_PO) == 0 && 1477 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) { 1478 EOWRITE4(sc, EHCI_PORTSC(i), cmd | EHCI_PS_FPR); 1479 hcr = 1; 1480 } 1481 } 1482 1483 if (hcr) { 1484 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT); 1485 1486 for (i = 1; i <= sc->sc_noport; i++) { 1487 cmd = EOREAD4(sc, EHCI_PORTSC(i)) & ~EHCI_PS_CLEAR; 1488 if ((cmd & EHCI_PS_PO) == 0 && 1489 (cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP) 1490 EOWRITE4(sc, EHCI_PORTSC(i), 1491 cmd & ~EHCI_PS_FPR); 1492 } 1493 } 1494 1495 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd); 1496 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs); 1497 1498 for (i = 0; i < 100; i++) { 1499 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH; 1500 if (hcr != EHCI_STS_HCH) 1501 break; 1502 1503 usb_delay_ms(&sc->sc_bus, 1); 1504 } 1505 if (hcr == EHCI_STS_HCH) 1506 printf("%s: config timeout\n", device_xname(dv)); 1507 1508 return true; 1509 } 1510 1511 /* 1512 * Shut down the controller when the system is going down. 1513 */ 1514 bool 1515 ehci_shutdown(device_t self, int flags) 1516 { 1517 ehci_softc_t *sc = device_private(self); 1518 1519 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1520 1521 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */ 1522 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET); 1523 return true; 1524 } 1525 1526 Static struct usbd_xfer * 1527 ehci_allocx(struct usbd_bus *bus) 1528 { 1529 struct ehci_softc *sc = bus->ub_hcpriv; 1530 struct usbd_xfer *xfer; 1531 1532 xfer = pool_cache_get(sc->sc_xferpool, PR_NOWAIT); 1533 if (xfer != NULL) { 1534 memset(xfer, 0, sizeof(struct ehci_xfer)); 1535 #ifdef DIAGNOSTIC 1536 EXFER(xfer)->ex_isdone = true; 1537 xfer->ux_state = XFER_BUSY; 1538 #endif 1539 } 1540 return xfer; 1541 } 1542 1543 Static void 1544 ehci_freex(struct usbd_bus *bus, struct usbd_xfer *xfer) 1545 { 1546 struct ehci_softc *sc = bus->ub_hcpriv; 1547 1548 KASSERT(xfer->ux_state == XFER_BUSY); 1549 KASSERT(EXFER(xfer)->ex_isdone); 1550 #ifdef DIAGNOSTIC 1551 xfer->ux_state = XFER_FREE; 1552 #endif 1553 pool_cache_put(sc->sc_xferpool, xfer); 1554 } 1555 1556 Static void 1557 ehci_get_lock(struct usbd_bus *bus, kmutex_t **lock) 1558 { 1559 struct ehci_softc *sc = bus->ub_hcpriv; 1560 1561 *lock = &sc->sc_lock; 1562 } 1563 1564 Static void 1565 ehci_device_clear_toggle(struct usbd_pipe *pipe) 1566 { 1567 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1568 1569 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1570 1571 USBHIST_LOG(ehcidebug, "epipe=%p status=0x%08x", 1572 epipe, epipe->sqh->qh.qh_qtd.qtd_status, 0, 0); 1573 #ifdef EHCI_DEBUG 1574 if (ehcidebug) 1575 usbd_dump_pipe(pipe); 1576 #endif 1577 epipe->nexttoggle = 0; 1578 } 1579 1580 Static void 1581 ehci_noop(struct usbd_pipe *pipe) 1582 { 1583 } 1584 1585 #ifdef EHCI_DEBUG 1586 /* 1587 * Unused function - this is meant to be called from a kernel 1588 * debugger. 1589 */ 1590 void 1591 ehci_dump(void) 1592 { 1593 ehci_softc_t *sc = theehci; 1594 int i; 1595 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n", 1596 EOREAD4(sc, EHCI_USBCMD), 1597 EOREAD4(sc, EHCI_USBSTS), 1598 EOREAD4(sc, EHCI_USBINTR)); 1599 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n", 1600 EOREAD4(sc, EHCI_FRINDEX), 1601 EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1602 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1603 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1604 for (i = 1; i <= sc->sc_noport; i++) 1605 printf("port %d status=0x%08x\n", i, 1606 EOREAD4(sc, EHCI_PORTSC(i))); 1607 } 1608 1609 Static void 1610 ehci_dump_regs(ehci_softc_t *sc) 1611 { 1612 int i; 1613 1614 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1615 1616 USBHIST_LOG(ehcidebug, 1617 "cmd = 0x%08x sts = 0x%08x ien = 0x%08x", 1618 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 1619 EOREAD4(sc, EHCI_USBINTR), 0); 1620 USBHIST_LOG(ehcidebug, 1621 "frindex = 0x%08x ctrdsegm = 0x%08x periodic = 0x%08x " 1622 "async = 0x%08x", 1623 EOREAD4(sc, EHCI_FRINDEX), EOREAD4(sc, EHCI_CTRLDSSEGMENT), 1624 EOREAD4(sc, EHCI_PERIODICLISTBASE), 1625 EOREAD4(sc, EHCI_ASYNCLISTADDR)); 1626 for (i = 1; i <= sc->sc_noport; i += 2) { 1627 if (i == sc->sc_noport) { 1628 USBHIST_LOG(ehcidebug, 1629 "port %d status = 0x%08x", i, 1630 EOREAD4(sc, EHCI_PORTSC(i)), 0, 0); 1631 } else { 1632 USBHIST_LOG(ehcidebug, 1633 "port %d status = 0x%08x port %d status = 0x%08x", 1634 i, EOREAD4(sc, EHCI_PORTSC(i)), 1635 i+1, EOREAD4(sc, EHCI_PORTSC(i+1))); 1636 } 1637 } 1638 } 1639 1640 #ifdef EHCI_DEBUG 1641 #define ehci_dump_link(link, type) do { \ 1642 USBHIST_LOG(ehcidebug, " link 0x%08x (T = %d):", \ 1643 link, \ 1644 link & EHCI_LINK_TERMINATE ? 1 : 0, 0, 0); \ 1645 if (type) { \ 1646 USBHIST_LOG(ehcidebug, \ 1647 " ITD = %d QH = %d SITD = %d FSTN = %d",\ 1648 EHCI_LINK_TYPE(link) == EHCI_LINK_ITD ? 1 : 0, \ 1649 EHCI_LINK_TYPE(link) == EHCI_LINK_QH ? 1 : 0, \ 1650 EHCI_LINK_TYPE(link) == EHCI_LINK_SITD ? 1 : 0, \ 1651 EHCI_LINK_TYPE(link) == EHCI_LINK_FSTN ? 1 : 0); \ 1652 } \ 1653 } while(0) 1654 #else 1655 #define ehci_dump_link(link, type) 1656 #endif 1657 1658 Static void 1659 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd) 1660 { 1661 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1662 int i; 1663 uint32_t stop = 0; 1664 1665 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) { 1666 ehci_dump_sqtd(sqtd); 1667 usb_syncmem(&sqtd->dma, 1668 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1669 sizeof(sqtd->qtd), 1670 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1671 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE); 1672 usb_syncmem(&sqtd->dma, 1673 sqtd->offs + offsetof(ehci_qtd_t, qtd_next), 1674 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1675 } 1676 if (!stop) 1677 USBHIST_LOG(ehcidebug, 1678 "dump aborted, too many TDs", 0, 0, 0, 0); 1679 } 1680 1681 Static void 1682 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd) 1683 { 1684 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1685 1686 usb_syncmem(&sqtd->dma, sqtd->offs, 1687 sizeof(sqtd->qtd), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1688 1689 USBHIST_LOGN(ehcidebug, 10, 1690 "QTD(%p) at 0x%08x:", sqtd, sqtd->physaddr, 0, 0); 1691 ehci_dump_qtd(&sqtd->qtd); 1692 1693 usb_syncmem(&sqtd->dma, sqtd->offs, 1694 sizeof(sqtd->qtd), BUS_DMASYNC_PREREAD); 1695 } 1696 1697 Static void 1698 ehci_dump_qtd(ehci_qtd_t *qtd) 1699 { 1700 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1701 1702 #ifdef USBHIST 1703 uint32_t s = le32toh(qtd->qtd_status); 1704 #endif 1705 1706 USBHIST_LOGN(ehcidebug, 10, 1707 " next = 0x%08x altnext = 0x%08x status = 0x%08x", 1708 qtd->qtd_next, qtd->qtd_altnext, s, 0); 1709 USBHIST_LOGN(ehcidebug, 10, 1710 " toggle = %d ioc = %d bytes = %#x " 1711 "c_page = %#x", EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_IOC(s), 1712 EHCI_QTD_GET_BYTES(s), EHCI_QTD_GET_C_PAGE(s)); 1713 USBHIST_LOGN(ehcidebug, 10, 1714 " cerr = %d pid = %d stat = %x", 1715 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s), EHCI_QTD_GET_STATUS(s), 1716 0); 1717 USBHIST_LOGN(ehcidebug, 10, 1718 "active =%d halted=%d buferr=%d babble=%d", 1719 s & EHCI_QTD_ACTIVE ? 1 : 0, 1720 s & EHCI_QTD_HALTED ? 1 : 0, 1721 s & EHCI_QTD_BUFERR ? 1 : 0, 1722 s & EHCI_QTD_BABBLE ? 1 : 0); 1723 USBHIST_LOGN(ehcidebug, 10, 1724 "xacterr=%d missed=%d split =%d ping =%d", 1725 s & EHCI_QTD_XACTERR ? 1 : 0, 1726 s & EHCI_QTD_MISSEDMICRO ? 1 : 0, 1727 s & EHCI_QTD_SPLITXSTATE ? 1 : 0, 1728 s & EHCI_QTD_PINGSTATE ? 1 : 0); 1729 USBHIST_LOGN(ehcidebug, 10, 1730 "buffer[0] = %#x buffer[1] = %#x " 1731 "buffer[2] = %#x buffer[3] = %#x", 1732 le32toh(qtd->qtd_buffer[0]), le32toh(qtd->qtd_buffer[1]), 1733 le32toh(qtd->qtd_buffer[2]), le32toh(qtd->qtd_buffer[3])); 1734 USBHIST_LOGN(ehcidebug, 10, 1735 "buffer[4] = %#x", le32toh(qtd->qtd_buffer[4]), 0, 0, 0); 1736 } 1737 1738 Static void 1739 ehci_dump_sqh(ehci_soft_qh_t *sqh) 1740 { 1741 #ifdef USBHIST 1742 ehci_qh_t *qh = &sqh->qh; 1743 ehci_link_t link; 1744 #endif 1745 uint32_t endp, endphub; 1746 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1747 1748 usb_syncmem(&sqh->dma, sqh->offs, 1749 sizeof(sqh->qh), BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 1750 1751 USBHIST_LOGN(ehcidebug, 10, 1752 "QH(%p) at %#x:", sqh, sqh->physaddr, 0, 0); 1753 link = le32toh(qh->qh_link); 1754 ehci_dump_link(link, true); 1755 1756 endp = le32toh(qh->qh_endp); 1757 USBHIST_LOGN(ehcidebug, 10, 1758 " endp = %#x", endp, 0, 0, 0); 1759 USBHIST_LOGN(ehcidebug, 10, 1760 " addr = 0x%02x inact = %d endpt = %d eps = %d", 1761 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp), 1762 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp)); 1763 USBHIST_LOGN(ehcidebug, 10, 1764 " dtc = %d hrecl = %d", 1765 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp), 0, 0); 1766 USBHIST_LOGN(ehcidebug, 10, 1767 " ctl = %d nrl = %d mpl = %#x(%d)", 1768 EHCI_QH_GET_CTL(endp),EHCI_QH_GET_NRL(endp), 1769 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_MPL(endp)); 1770 1771 endphub = le32toh(qh->qh_endphub); 1772 USBHIST_LOGN(ehcidebug, 10, 1773 " endphub = %#x", endphub, 0, 0, 0); 1774 USBHIST_LOGN(ehcidebug, 10, 1775 " smask = 0x%02x cmask = 0x%02x", 1776 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub), 1, 0); 1777 USBHIST_LOGN(ehcidebug, 10, 1778 " huba = 0x%02x port = %d mult = %d", 1779 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub), 1780 EHCI_QH_GET_MULT(endphub), 0); 1781 1782 link = le32toh(qh->qh_curqtd); 1783 ehci_dump_link(link, false); 1784 USBHIST_LOGN(ehcidebug, 10, "Overlay qTD:", 0, 0, 0, 0); 1785 ehci_dump_qtd(&qh->qh_qtd); 1786 1787 usb_syncmem(&sqh->dma, sqh->offs, 1788 sizeof(sqh->qh), BUS_DMASYNC_PREREAD); 1789 } 1790 1791 Static void 1792 ehci_dump_itd(struct ehci_soft_itd *itd) 1793 { 1794 ehci_isoc_trans_t t; 1795 ehci_isoc_bufr_ptr_t b, b2, b3; 1796 int i; 1797 1798 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1799 1800 USBHIST_LOG(ehcidebug, "ITD: next phys = %#x", itd->itd.itd_next, 0, 1801 0, 0); 1802 1803 for (i = 0; i < EHCI_ITD_NUFRAMES; i++) { 1804 t = le32toh(itd->itd.itd_ctl[i]); 1805 USBHIST_LOG(ehcidebug, "ITDctl %d: stat = %x len = %x", 1806 i, EHCI_ITD_GET_STATUS(t), EHCI_ITD_GET_LEN(t), 0); 1807 USBHIST_LOG(ehcidebug, " ioc = %x pg = %x offs = %x", 1808 EHCI_ITD_GET_IOC(t), EHCI_ITD_GET_PG(t), 1809 EHCI_ITD_GET_OFFS(t), 0); 1810 } 1811 USBHIST_LOG(ehcidebug, "ITDbufr: ", 0, 0, 0, 0); 1812 for (i = 0; i < EHCI_ITD_NBUFFERS; i++) 1813 USBHIST_LOG(ehcidebug, " %x", 1814 EHCI_ITD_GET_BPTR(le32toh(itd->itd.itd_bufr[i])), 0, 0, 0); 1815 1816 b = le32toh(itd->itd.itd_bufr[0]); 1817 b2 = le32toh(itd->itd.itd_bufr[1]); 1818 b3 = le32toh(itd->itd.itd_bufr[2]); 1819 USBHIST_LOG(ehcidebug, " ep = %x daddr = %x dir = %d", 1820 EHCI_ITD_GET_EP(b), EHCI_ITD_GET_DADDR(b), EHCI_ITD_GET_DIR(b2), 0); 1821 USBHIST_LOG(ehcidebug, " maxpkt = %x multi = %x", 1822 EHCI_ITD_GET_MAXPKT(b2), EHCI_ITD_GET_MULTI(b3), 0, 0); 1823 } 1824 1825 Static void 1826 ehci_dump_sitd(struct ehci_soft_itd *itd) 1827 { 1828 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1829 1830 USBHIST_LOG(ehcidebug, "SITD %p next = %p prev = %p", 1831 itd, itd->u.frame_list.next, itd->u.frame_list.prev, 0); 1832 USBHIST_LOG(ehcidebug, " xfernext=%p physaddr=%X slot=%d", 1833 itd->xfer_next, itd->physaddr, itd->slot, 0); 1834 } 1835 1836 Static void 1837 ehci_dump_exfer(struct ehci_xfer *ex) 1838 { 1839 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1840 1841 USBHIST_LOG(ehcidebug, "ex = %p sqtdstart = %p end = %p", 1842 ex, ex->ex_sqtdstart, ex->ex_sqtdend, 0); 1843 USBHIST_LOG(ehcidebug, " itdstart = %p end = %p isdone = %d", 1844 ex->ex_itdstart, ex->ex_itdend, ex->ex_isdone, 0); 1845 } 1846 #endif 1847 1848 Static usbd_status 1849 ehci_open(struct usbd_pipe *pipe) 1850 { 1851 struct usbd_device *dev = pipe->up_dev; 1852 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 1853 usb_endpoint_descriptor_t *ed = pipe->up_endpoint->ue_edesc; 1854 uint8_t rhaddr = dev->ud_bus->ub_rhaddr; 1855 uint8_t addr = dev->ud_addr; 1856 uint8_t xfertype = UE_GET_XFERTYPE(ed->bmAttributes); 1857 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 1858 ehci_soft_qh_t *sqh; 1859 usbd_status err; 1860 int ival, speed, naks; 1861 int hshubaddr, hshubport; 1862 1863 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 1864 1865 USBHIST_LOG(ehcidebug, "pipe=%p, addr=%d, endpt=%d (%d)", 1866 pipe, addr, ed->bEndpointAddress, rhaddr); 1867 1868 if (dev->ud_myhsport) { 1869 /* 1870 * When directly attached FS/LS device while doing embedded 1871 * transaction translations and we are the hub, set the hub 1872 * address to 0 (us). 1873 */ 1874 if (!(sc->sc_flags & EHCIF_ETTF) 1875 || (dev->ud_myhsport->up_parent->ud_addr != rhaddr)) { 1876 hshubaddr = dev->ud_myhsport->up_parent->ud_addr; 1877 } else { 1878 hshubaddr = 0; 1879 } 1880 hshubport = dev->ud_myhsport->up_portno; 1881 } else { 1882 hshubaddr = 0; 1883 hshubport = 0; 1884 } 1885 1886 if (sc->sc_dying) 1887 return USBD_IOERROR; 1888 1889 /* toggle state needed for bulk endpoints */ 1890 epipe->nexttoggle = pipe->up_endpoint->ue_toggle; 1891 1892 if (addr == rhaddr) { 1893 switch (ed->bEndpointAddress) { 1894 case USB_CONTROL_ENDPOINT: 1895 pipe->up_methods = &roothub_ctrl_methods; 1896 break; 1897 case UE_DIR_IN | USBROOTHUB_INTR_ENDPT: 1898 pipe->up_methods = &ehci_root_intr_methods; 1899 break; 1900 default: 1901 USBHIST_LOG(ehcidebug, 1902 "bad bEndpointAddress 0x%02x", 1903 ed->bEndpointAddress, 0, 0, 0); 1904 return USBD_INVAL; 1905 } 1906 return USBD_NORMAL_COMPLETION; 1907 } 1908 1909 /* XXX All this stuff is only valid for async. */ 1910 switch (dev->ud_speed) { 1911 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break; 1912 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break; 1913 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break; 1914 default: panic("ehci_open: bad device speed %d", dev->ud_speed); 1915 } 1916 if (speed == EHCI_QH_SPEED_LOW && xfertype == UE_ISOCHRONOUS) { 1917 USBHIST_LOG(ehcidebug, "hshubaddr=%d hshubport=%d", 1918 hshubaddr, hshubport, 0, 0); 1919 return USBD_INVAL; 1920 } 1921 1922 /* 1923 * For interrupt transfer, nak throttling must be disabled, but for 1924 * the other transfer type, nak throttling should be enabled from the 1925 * viewpoint that avoids the memory thrashing. 1926 */ 1927 naks = (xfertype == UE_INTERRUPT) ? 0 1928 : ((speed == EHCI_QH_SPEED_HIGH) ? 4 : 0); 1929 1930 /* Allocate sqh for everything, save isoc xfers */ 1931 if (xfertype != UE_ISOCHRONOUS) { 1932 sqh = ehci_alloc_sqh(sc); 1933 if (sqh == NULL) 1934 return USBD_NOMEM; 1935 /* qh_link filled when the QH is added */ 1936 sqh->qh.qh_endp = htole32( 1937 EHCI_QH_SET_ADDR(addr) | 1938 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) | 1939 EHCI_QH_SET_EPS(speed) | 1940 EHCI_QH_DTC | 1941 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) | 1942 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ? 1943 EHCI_QH_CTL : 0) | 1944 EHCI_QH_SET_NRL(naks) 1945 ); 1946 sqh->qh.qh_endphub = htole32( 1947 EHCI_QH_SET_MULT(1) | 1948 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x02 : 0) 1949 ); 1950 if (speed != EHCI_QH_SPEED_HIGH) 1951 sqh->qh.qh_endphub |= htole32( 1952 EHCI_QH_SET_PORT(hshubport) | 1953 EHCI_QH_SET_HUBA(hshubaddr) | 1954 EHCI_QH_SET_CMASK(0x08) /* XXX */ 1955 ); 1956 sqh->qh.qh_curqtd = EHCI_NULL; 1957 /* Fill the overlay qTD */ 1958 sqh->qh.qh_qtd.qtd_next = EHCI_NULL; 1959 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 1960 sqh->qh.qh_qtd.qtd_status = htole32(0); 1961 1962 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 1963 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1964 epipe->sqh = sqh; 1965 } else { 1966 sqh = NULL; 1967 } /*xfertype == UE_ISOC*/ 1968 1969 switch (xfertype) { 1970 case UE_CONTROL: 1971 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t), 1972 0, &epipe->u.ctl.reqdma); 1973 #ifdef EHCI_DEBUG 1974 if (err) 1975 printf("ehci_open: usb_allocmem()=%d\n", err); 1976 #endif 1977 if (err) 1978 goto bad; 1979 pipe->up_methods = &ehci_device_ctrl_methods; 1980 mutex_enter(&sc->sc_lock); 1981 ehci_add_qh(sc, sqh, sc->sc_async_head); 1982 mutex_exit(&sc->sc_lock); 1983 break; 1984 case UE_BULK: 1985 pipe->up_methods = &ehci_device_bulk_methods; 1986 mutex_enter(&sc->sc_lock); 1987 ehci_add_qh(sc, sqh, sc->sc_async_head); 1988 mutex_exit(&sc->sc_lock); 1989 break; 1990 case UE_INTERRUPT: 1991 pipe->up_methods = &ehci_device_intr_methods; 1992 ival = pipe->up_interval; 1993 if (ival == USBD_DEFAULT_INTERVAL) { 1994 if (speed == EHCI_QH_SPEED_HIGH) { 1995 if (ed->bInterval > 16) { 1996 /* 1997 * illegal with high-speed, but there 1998 * were documentation bugs in the spec, 1999 * so be generous 2000 */ 2001 ival = 256; 2002 } else 2003 ival = (1 << (ed->bInterval - 1)) / 8; 2004 } else 2005 ival = ed->bInterval; 2006 } 2007 err = ehci_device_setintr(sc, sqh, ival); 2008 if (err) 2009 goto bad; 2010 break; 2011 case UE_ISOCHRONOUS: 2012 if (speed == EHCI_QH_SPEED_HIGH) 2013 pipe->up_methods = &ehci_device_isoc_methods; 2014 else 2015 pipe->up_methods = &ehci_device_fs_isoc_methods; 2016 if (ed->bInterval == 0 || ed->bInterval > 16) { 2017 printf("ehci: opening pipe with invalid bInterval\n"); 2018 err = USBD_INVAL; 2019 goto bad; 2020 } 2021 if (UGETW(ed->wMaxPacketSize) == 0) { 2022 printf("ehci: zero length endpoint open request\n"); 2023 err = USBD_INVAL; 2024 goto bad; 2025 } 2026 epipe->u.isoc.next_frame = 0; 2027 epipe->u.isoc.cur_xfers = 0; 2028 break; 2029 default: 2030 USBHIST_LOG(ehcidebug, "bad xfer type %d", xfertype, 0, 0, 0); 2031 err = USBD_INVAL; 2032 goto bad; 2033 } 2034 return USBD_NORMAL_COMPLETION; 2035 2036 bad: 2037 if (sqh != NULL) 2038 ehci_free_sqh(sc, sqh); 2039 return err; 2040 } 2041 2042 /* 2043 * Add an ED to the schedule. Called with USB lock held. 2044 */ 2045 Static void 2046 ehci_add_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2047 { 2048 2049 KASSERT(mutex_owned(&sc->sc_lock)); 2050 2051 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2052 2053 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2054 sizeof(head->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2055 2056 sqh->next = head->next; 2057 sqh->qh.qh_link = head->qh.qh_link; 2058 2059 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2060 sizeof(sqh->qh.qh_link), BUS_DMASYNC_PREWRITE); 2061 2062 head->next = sqh; 2063 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH); 2064 2065 usb_syncmem(&head->dma, head->offs + offsetof(ehci_qh_t, qh_link), 2066 sizeof(head->qh.qh_link), BUS_DMASYNC_PREWRITE); 2067 2068 #ifdef EHCI_DEBUG 2069 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 2070 ehci_dump_sqh(sqh); 2071 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 2072 #endif 2073 } 2074 2075 /* 2076 * Remove an ED from the schedule. Called with USB lock held. 2077 */ 2078 Static void 2079 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head) 2080 { 2081 ehci_soft_qh_t *p; 2082 2083 KASSERT(mutex_owned(&sc->sc_lock)); 2084 2085 /* XXX */ 2086 for (p = head; p != NULL && p->next != sqh; p = p->next) 2087 ; 2088 if (p == NULL) 2089 panic("ehci_rem_qh: ED not found"); 2090 usb_syncmem(&sqh->dma, sqh->offs + offsetof(ehci_qh_t, qh_link), 2091 sizeof(sqh->qh.qh_link), BUS_DMASYNC_POSTWRITE); 2092 p->next = sqh->next; 2093 p->qh.qh_link = sqh->qh.qh_link; 2094 usb_syncmem(&p->dma, p->offs + offsetof(ehci_qh_t, qh_link), 2095 sizeof(p->qh.qh_link), BUS_DMASYNC_PREWRITE); 2096 2097 ehci_sync_hc(sc); 2098 } 2099 2100 Static void 2101 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd) 2102 { 2103 int i; 2104 uint32_t status; 2105 2106 /* Save toggle bit and ping status. */ 2107 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2108 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 2109 status = sqh->qh.qh_qtd.qtd_status & 2110 htole32(EHCI_QTD_TOGGLE_MASK | 2111 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE)); 2112 /* Set HALTED to make hw leave it alone. */ 2113 sqh->qh.qh_qtd.qtd_status = 2114 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED)); 2115 usb_syncmem(&sqh->dma, 2116 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2117 sizeof(sqh->qh.qh_qtd.qtd_status), 2118 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2119 sqh->qh.qh_curqtd = 0; 2120 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr); 2121 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL; 2122 for (i = 0; i < EHCI_QTD_NBUFFERS; i++) 2123 sqh->qh.qh_qtd.qtd_buffer[i] = 0; 2124 sqh->sqtd = sqtd; 2125 usb_syncmem(&sqh->dma, sqh->offs, sizeof(sqh->qh), 2126 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2127 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */ 2128 sqh->qh.qh_qtd.qtd_status = status; 2129 usb_syncmem(&sqh->dma, 2130 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 2131 sizeof(sqh->qh.qh_qtd.qtd_status), 2132 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2133 } 2134 2135 /* 2136 * Ensure that the HC has released all references to the QH. We do this 2137 * by asking for a Async Advance Doorbell interrupt and then we wait for 2138 * the interrupt. 2139 * To make this easier we first obtain exclusive use of the doorbell. 2140 */ 2141 Static void 2142 ehci_sync_hc(ehci_softc_t *sc) 2143 { 2144 int error __diagused; 2145 2146 KASSERT(mutex_owned(&sc->sc_lock)); 2147 2148 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2149 2150 if (sc->sc_dying) { 2151 USBHIST_LOG(ehcidebug, "dying", 0, 0, 0, 0); 2152 return; 2153 } 2154 /* ask for doorbell */ 2155 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD); 2156 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2157 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2158 2159 error = cv_timedwait(&sc->sc_doorbell, &sc->sc_lock, hz); /* bell wait */ 2160 2161 USBHIST_LOG(ehcidebug, "cmd = 0x%08x sts = 0x%08x", 2162 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS), 0, 0); 2163 #ifdef DIAGNOSTIC 2164 if (error) 2165 printf("ehci_sync_hc: cv_timedwait() = %d\n", error); 2166 #endif 2167 } 2168 2169 Static void 2170 ehci_rem_free_itd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2171 { 2172 struct ehci_soft_itd *itd, *prev; 2173 2174 prev = NULL; 2175 2176 if (exfer->ex_itdstart == NULL || exfer->ex_itdend == NULL) 2177 panic("ehci isoc xfer being freed, but with no itd chain\n"); 2178 2179 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2180 prev = itd->u.frame_list.prev; 2181 /* Unlink itd from hardware chain, or frame array */ 2182 if (prev == NULL) { /* We're at the table head */ 2183 sc->sc_softitds[itd->slot] = itd->u.frame_list.next; 2184 sc->sc_flist[itd->slot] = itd->itd.itd_next; 2185 usb_syncmem(&sc->sc_fldma, 2186 sizeof(ehci_link_t) * itd->slot, 2187 sizeof(ehci_link_t), 2188 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2189 2190 if (itd->u.frame_list.next != NULL) 2191 itd->u.frame_list.next->u.frame_list.prev = NULL; 2192 } else { 2193 /* XXX this part is untested... */ 2194 prev->itd.itd_next = itd->itd.itd_next; 2195 usb_syncmem(&itd->dma, 2196 itd->offs + offsetof(ehci_itd_t, itd_next), 2197 sizeof(itd->itd.itd_next), BUS_DMASYNC_PREWRITE); 2198 2199 prev->u.frame_list.next = itd->u.frame_list.next; 2200 if (itd->u.frame_list.next != NULL) 2201 itd->u.frame_list.next->u.frame_list.prev = prev; 2202 } 2203 } 2204 2205 prev = NULL; 2206 for (itd = exfer->ex_itdstart; itd != NULL; itd = itd->xfer_next) { 2207 if (prev != NULL) 2208 ehci_free_itd(sc, prev); 2209 prev = itd; 2210 } 2211 if (prev) 2212 ehci_free_itd(sc, prev); 2213 exfer->ex_itdstart = NULL; 2214 exfer->ex_itdend = NULL; 2215 } 2216 2217 Static void 2218 ehci_rem_free_sitd_chain(ehci_softc_t *sc, struct ehci_xfer *exfer) 2219 { 2220 struct ehci_soft_sitd *sitd, *prev; 2221 2222 prev = NULL; 2223 2224 if (exfer->ex_sitdstart == NULL || exfer->ex_sitdend == NULL) 2225 panic("ehci isoc xfer being freed, but with no sitd chain\n"); 2226 2227 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2228 prev = sitd->u.frame_list.prev; 2229 /* Unlink sitd from hardware chain, or frame array */ 2230 if (prev == NULL) { /* We're at the table head */ 2231 sc->sc_softsitds[sitd->slot] = sitd->u.frame_list.next; 2232 sc->sc_flist[sitd->slot] = sitd->sitd.sitd_next; 2233 usb_syncmem(&sc->sc_fldma, 2234 sizeof(ehci_link_t) * sitd->slot, 2235 sizeof(ehci_link_t), 2236 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2237 2238 if (sitd->u.frame_list.next != NULL) 2239 sitd->u.frame_list.next->u.frame_list.prev = NULL; 2240 } else { 2241 /* XXX this part is untested... */ 2242 prev->sitd.sitd_next = sitd->sitd.sitd_next; 2243 usb_syncmem(&sitd->dma, 2244 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 2245 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE); 2246 2247 prev->u.frame_list.next = sitd->u.frame_list.next; 2248 if (sitd->u.frame_list.next != NULL) 2249 sitd->u.frame_list.next->u.frame_list.prev = prev; 2250 } 2251 } 2252 2253 prev = NULL; 2254 for (sitd = exfer->ex_sitdstart; sitd != NULL; sitd = sitd->xfer_next) { 2255 if (prev != NULL) 2256 ehci_free_sitd(sc, prev); 2257 prev = sitd; 2258 } 2259 if (prev) 2260 ehci_free_sitd(sc, prev); 2261 exfer->ex_sitdstart = NULL; 2262 exfer->ex_sitdend = NULL; 2263 } 2264 2265 /***********/ 2266 2267 Static int 2268 ehci_roothub_ctrl(struct usbd_bus *bus, usb_device_request_t *req, 2269 void *buf, int buflen) 2270 { 2271 ehci_softc_t *sc = bus->ub_hcpriv; 2272 usb_hub_descriptor_t hubd; 2273 usb_port_status_t ps; 2274 uint16_t len, value, index; 2275 int l, totlen = 0; 2276 int port, i; 2277 uint32_t v; 2278 2279 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2280 2281 if (sc->sc_dying) 2282 return -1; 2283 2284 USBHIST_LOG(ehcidebug, "type=0x%02x request=%02x", 2285 req->bmRequestType, req->bRequest, 0, 0); 2286 2287 len = UGETW(req->wLength); 2288 value = UGETW(req->wValue); 2289 index = UGETW(req->wIndex); 2290 2291 #define C(x,y) ((x) | ((y) << 8)) 2292 switch (C(req->bRequest, req->bmRequestType)) { 2293 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2294 if (len == 0) 2295 break; 2296 switch (value) { 2297 case C(0, UDESC_DEVICE): { 2298 usb_device_descriptor_t devd; 2299 totlen = min(buflen, sizeof(devd)); 2300 memcpy(&devd, buf, totlen); 2301 USETW(devd.idVendor, sc->sc_id_vendor); 2302 memcpy(buf, &devd, totlen); 2303 break; 2304 2305 } 2306 #define sd ((usb_string_descriptor_t *)buf) 2307 case C(1, UDESC_STRING): 2308 /* Vendor */ 2309 totlen = usb_makestrdesc(sd, len, sc->sc_vendor); 2310 break; 2311 case C(2, UDESC_STRING): 2312 /* Product */ 2313 totlen = usb_makestrdesc(sd, len, "EHCI root hub"); 2314 break; 2315 #undef sd 2316 default: 2317 /* default from usbroothub */ 2318 return buflen; 2319 } 2320 break; 2321 2322 /* Hub requests */ 2323 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 2324 break; 2325 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 2326 USBHIST_LOG(ehcidebug, 2327 "UR_CLEAR_PORT_FEATURE port=%d feature=%d", index, value, 2328 0, 0); 2329 if (index < 1 || index > sc->sc_noport) { 2330 return -1; 2331 } 2332 port = EHCI_PORTSC(index); 2333 v = EOREAD4(sc, port); 2334 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2335 v &= ~EHCI_PS_CLEAR; 2336 switch (value) { 2337 case UHF_PORT_ENABLE: 2338 EOWRITE4(sc, port, v &~ EHCI_PS_PE); 2339 break; 2340 case UHF_PORT_SUSPEND: 2341 if (!(v & EHCI_PS_SUSP)) /* not suspended */ 2342 break; 2343 v &= ~EHCI_PS_SUSP; 2344 EOWRITE4(sc, port, v | EHCI_PS_FPR); 2345 /* see USB2 spec ch. 7.1.7.7 */ 2346 usb_delay_ms(&sc->sc_bus, 20); 2347 EOWRITE4(sc, port, v); 2348 usb_delay_ms(&sc->sc_bus, 2); 2349 #ifdef DEBUG 2350 v = EOREAD4(sc, port); 2351 if (v & (EHCI_PS_FPR | EHCI_PS_SUSP)) 2352 printf("ehci: resume failed: %x\n", v); 2353 #endif 2354 break; 2355 case UHF_PORT_POWER: 2356 if (sc->sc_hasppc) 2357 EOWRITE4(sc, port, v &~ EHCI_PS_PP); 2358 break; 2359 case UHF_PORT_TEST: 2360 USBHIST_LOG(ehcidebug, "clear port test " 2361 "%d", index, 0, 0, 0); 2362 break; 2363 case UHF_PORT_INDICATOR: 2364 USBHIST_LOG(ehcidebug, "clear port ind " 2365 "%d", index, 0, 0, 0); 2366 EOWRITE4(sc, port, v &~ EHCI_PS_PIC); 2367 break; 2368 case UHF_C_PORT_CONNECTION: 2369 EOWRITE4(sc, port, v | EHCI_PS_CSC); 2370 break; 2371 case UHF_C_PORT_ENABLE: 2372 EOWRITE4(sc, port, v | EHCI_PS_PEC); 2373 break; 2374 case UHF_C_PORT_SUSPEND: 2375 /* how? */ 2376 break; 2377 case UHF_C_PORT_OVER_CURRENT: 2378 EOWRITE4(sc, port, v | EHCI_PS_OCC); 2379 break; 2380 case UHF_C_PORT_RESET: 2381 sc->sc_isreset[index] = 0; 2382 break; 2383 default: 2384 return -1; 2385 } 2386 #if 0 2387 switch(value) { 2388 case UHF_C_PORT_CONNECTION: 2389 case UHF_C_PORT_ENABLE: 2390 case UHF_C_PORT_SUSPEND: 2391 case UHF_C_PORT_OVER_CURRENT: 2392 case UHF_C_PORT_RESET: 2393 default: 2394 break; 2395 } 2396 #endif 2397 break; 2398 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 2399 if (len == 0) 2400 break; 2401 if ((value & 0xff) != 0) { 2402 return -1; 2403 } 2404 totlen = min(buflen, sizeof(hubd)); 2405 memcpy(&hubd, buf, totlen); 2406 hubd.bNbrPorts = sc->sc_noport; 2407 v = EOREAD4(sc, EHCI_HCSPARAMS); 2408 USETW(hubd.wHubCharacteristics, 2409 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH | 2410 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) 2411 ? UHD_PORT_IND : 0); 2412 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */ 2413 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8) 2414 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */ 2415 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i; 2416 totlen = min(totlen, hubd.bDescLength); 2417 memcpy(buf, &hubd, totlen); 2418 break; 2419 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 2420 if (len != 4) { 2421 return -1; 2422 } 2423 memset(buf, 0, len); /* ? XXX */ 2424 totlen = len; 2425 break; 2426 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 2427 USBHIST_LOG(ehcidebug, "get port status i=%d", index, 0, 0, 0); 2428 if (index < 1 || index > sc->sc_noport) { 2429 return -1; 2430 } 2431 if (len != 4) { 2432 return -1; 2433 } 2434 v = EOREAD4(sc, EHCI_PORTSC(index)); 2435 USBHIST_LOG(ehcidebug, "port status=0x%04x", v, 0, 0, 0); 2436 2437 i = UPS_HIGH_SPEED; 2438 if (sc->sc_flags & EHCIF_ETTF) { 2439 /* 2440 * If we are doing embedded transaction translation, 2441 * then directly attached LS/FS devices are reset by 2442 * the EHCI controller itself. PSPD is encoded 2443 * the same way as in USBSTATUS. 2444 */ 2445 i = __SHIFTOUT(v, EHCI_PS_PSPD) * UPS_LOW_SPEED; 2446 } 2447 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS; 2448 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED; 2449 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND; 2450 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR; 2451 if (v & EHCI_PS_PR) i |= UPS_RESET; 2452 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER; 2453 if (sc->sc_vendor_port_status) 2454 i = sc->sc_vendor_port_status(sc, v, i); 2455 USETW(ps.wPortStatus, i); 2456 i = 0; 2457 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS; 2458 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED; 2459 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR; 2460 if (sc->sc_isreset[index]) i |= UPS_C_PORT_RESET; 2461 USETW(ps.wPortChange, i); 2462 totlen = min(len, sizeof(ps)); 2463 memcpy(buf, &ps, totlen); 2464 break; 2465 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 2466 return -1; 2467 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 2468 break; 2469 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 2470 if (index < 1 || index > sc->sc_noport) { 2471 return -1; 2472 } 2473 port = EHCI_PORTSC(index); 2474 v = EOREAD4(sc, port); 2475 USBHIST_LOG(ehcidebug, "portsc=0x%08x", v, 0, 0, 0); 2476 v &= ~EHCI_PS_CLEAR; 2477 switch(value) { 2478 case UHF_PORT_ENABLE: 2479 EOWRITE4(sc, port, v | EHCI_PS_PE); 2480 break; 2481 case UHF_PORT_SUSPEND: 2482 EOWRITE4(sc, port, v | EHCI_PS_SUSP); 2483 break; 2484 case UHF_PORT_RESET: 2485 USBHIST_LOG(ehcidebug, "reset port %d", index, 0, 0, 0); 2486 if (EHCI_PS_IS_LOWSPEED(v) 2487 && sc->sc_ncomp > 0 2488 && !(sc->sc_flags & EHCIF_ETTF)) { 2489 /* 2490 * Low speed device on non-ETTF controller or 2491 * unaccompanied controller, give up ownership. 2492 */ 2493 ehci_disown(sc, index, 1); 2494 break; 2495 } 2496 /* Start reset sequence. */ 2497 v &= ~ (EHCI_PS_PE | EHCI_PS_PR); 2498 EOWRITE4(sc, port, v | EHCI_PS_PR); 2499 /* Wait for reset to complete. */ 2500 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY); 2501 if (sc->sc_dying) { 2502 return -1; 2503 } 2504 /* 2505 * An embedded transaction translator will automatically 2506 * terminate the reset sequence so there's no need to 2507 * it. 2508 */ 2509 v = EOREAD4(sc, port); 2510 if (v & EHCI_PS_PR) { 2511 /* Terminate reset sequence. */ 2512 EOWRITE4(sc, port, v & ~EHCI_PS_PR); 2513 /* Wait for HC to complete reset. */ 2514 usb_delay_ms(&sc->sc_bus, 2515 EHCI_PORT_RESET_COMPLETE); 2516 if (sc->sc_dying) { 2517 return -1; 2518 } 2519 } 2520 2521 v = EOREAD4(sc, port); 2522 USBHIST_LOG(ehcidebug, 2523 "ehci after reset, status=0x%08x", v, 0, 0, 0); 2524 if (v & EHCI_PS_PR) { 2525 printf("%s: port reset timeout\n", 2526 device_xname(sc->sc_dev)); 2527 return USBD_TIMEOUT; 2528 } 2529 if (!(v & EHCI_PS_PE)) { 2530 /* Not a high speed device, give up ownership.*/ 2531 ehci_disown(sc, index, 0); 2532 break; 2533 } 2534 sc->sc_isreset[index] = 1; 2535 USBHIST_LOG(ehcidebug, 2536 "ehci port %d reset, status = 0x%08x", index, v, 0, 2537 0); 2538 break; 2539 case UHF_PORT_POWER: 2540 USBHIST_LOG(ehcidebug, 2541 "set port power %d (has PPC = %d)", index, 2542 sc->sc_hasppc, 0, 0); 2543 if (sc->sc_hasppc) 2544 EOWRITE4(sc, port, v | EHCI_PS_PP); 2545 break; 2546 case UHF_PORT_TEST: 2547 USBHIST_LOG(ehcidebug, "set port test %d", 2548 index, 0, 0, 0); 2549 break; 2550 case UHF_PORT_INDICATOR: 2551 USBHIST_LOG(ehcidebug, "set port ind %d", 2552 index, 0, 0, 0); 2553 EOWRITE4(sc, port, v | EHCI_PS_PIC); 2554 break; 2555 default: 2556 return -1; 2557 } 2558 break; 2559 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 2560 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 2561 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 2562 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 2563 break; 2564 default: 2565 /* default from usbroothub */ 2566 USBHIST_LOG(ehcidebug, "returning %d (usbroothub default)", 2567 buflen, 0, 0, 0); 2568 2569 return buflen; 2570 } 2571 2572 USBHIST_LOG(ehcidebug, "returning %d", totlen, 0, 0, 0); 2573 2574 return totlen; 2575 } 2576 2577 Static void 2578 ehci_disown(ehci_softc_t *sc, int index, int lowspeed) 2579 { 2580 int port; 2581 uint32_t v; 2582 2583 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2584 2585 USBHIST_LOG(ehcidebug, "index=%d lowspeed=%d", index, lowspeed, 0, 0); 2586 #ifdef DIAGNOSTIC 2587 if (sc->sc_npcomp != 0) { 2588 int i = (index-1) / sc->sc_npcomp; 2589 if (i >= sc->sc_ncomp) 2590 printf("%s: strange port\n", 2591 device_xname(sc->sc_dev)); 2592 else 2593 printf("%s: handing over %s speed device on " 2594 "port %d to %s\n", 2595 device_xname(sc->sc_dev), 2596 lowspeed ? "low" : "full", 2597 index, device_xname(sc->sc_comps[i])); 2598 } else { 2599 printf("%s: npcomp == 0\n", device_xname(sc->sc_dev)); 2600 } 2601 #endif 2602 port = EHCI_PORTSC(index); 2603 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR; 2604 EOWRITE4(sc, port, v | EHCI_PS_PO); 2605 } 2606 2607 Static usbd_status 2608 ehci_root_intr_transfer(struct usbd_xfer *xfer) 2609 { 2610 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2611 usbd_status err; 2612 2613 /* Insert last in queue. */ 2614 mutex_enter(&sc->sc_lock); 2615 err = usb_insert_transfer(xfer); 2616 mutex_exit(&sc->sc_lock); 2617 if (err) 2618 return err; 2619 2620 /* Pipe isn't running, start first */ 2621 return ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 2622 } 2623 2624 Static usbd_status 2625 ehci_root_intr_start(struct usbd_xfer *xfer) 2626 { 2627 struct usbd_pipe *pipe = xfer->ux_pipe; 2628 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2629 2630 if (sc->sc_dying) 2631 return USBD_IOERROR; 2632 2633 mutex_enter(&sc->sc_lock); 2634 sc->sc_intrxfer = xfer; 2635 mutex_exit(&sc->sc_lock); 2636 2637 return USBD_IN_PROGRESS; 2638 } 2639 2640 /* Abort a root interrupt request. */ 2641 Static void 2642 ehci_root_intr_abort(struct usbd_xfer *xfer) 2643 { 2644 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 2645 2646 KASSERT(mutex_owned(&sc->sc_lock)); 2647 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 2648 2649 sc->sc_intrxfer = NULL; 2650 2651 xfer->ux_status = USBD_CANCELLED; 2652 usb_transfer_complete(xfer); 2653 } 2654 2655 /* Close the root pipe. */ 2656 Static void 2657 ehci_root_intr_close(struct usbd_pipe *pipe) 2658 { 2659 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 2660 2661 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2662 2663 KASSERT(mutex_owned(&sc->sc_lock)); 2664 2665 sc->sc_intrxfer = NULL; 2666 } 2667 2668 Static void 2669 ehci_root_intr_done(struct usbd_xfer *xfer) 2670 { 2671 xfer->ux_hcpriv = NULL; 2672 } 2673 2674 /************************/ 2675 2676 Static ehci_soft_qh_t * 2677 ehci_alloc_sqh(ehci_softc_t *sc) 2678 { 2679 ehci_soft_qh_t *sqh; 2680 usbd_status err; 2681 int i, offs; 2682 usb_dma_t dma; 2683 2684 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2685 2686 if (sc->sc_freeqhs == NULL) { 2687 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2688 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK, 2689 EHCI_PAGE_SIZE, &dma); 2690 #ifdef EHCI_DEBUG 2691 if (err) 2692 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err); 2693 #endif 2694 if (err) 2695 return NULL; 2696 for (i = 0; i < EHCI_SQH_CHUNK; i++) { 2697 offs = i * EHCI_SQH_SIZE; 2698 sqh = KERNADDR(&dma, offs); 2699 sqh->physaddr = DMAADDR(&dma, offs); 2700 sqh->dma = dma; 2701 sqh->offs = offs; 2702 sqh->next = sc->sc_freeqhs; 2703 sc->sc_freeqhs = sqh; 2704 } 2705 } 2706 sqh = sc->sc_freeqhs; 2707 sc->sc_freeqhs = sqh->next; 2708 memset(&sqh->qh, 0, sizeof(ehci_qh_t)); 2709 sqh->next = NULL; 2710 return sqh; 2711 } 2712 2713 Static void 2714 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh) 2715 { 2716 sqh->next = sc->sc_freeqhs; 2717 sc->sc_freeqhs = sqh; 2718 } 2719 2720 Static ehci_soft_qtd_t * 2721 ehci_alloc_sqtd(ehci_softc_t *sc) 2722 { 2723 ehci_soft_qtd_t *sqtd = NULL; 2724 usbd_status err; 2725 int i, offs; 2726 usb_dma_t dma; 2727 2728 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2729 2730 if (sc->sc_freeqtds == NULL) { 2731 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2732 2733 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK, 2734 EHCI_PAGE_SIZE, &dma); 2735 #ifdef EHCI_DEBUG 2736 if (err) 2737 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err); 2738 #endif 2739 if (err) 2740 goto done; 2741 2742 for (i = 0; i < EHCI_SQTD_CHUNK; i++) { 2743 offs = i * EHCI_SQTD_SIZE; 2744 sqtd = KERNADDR(&dma, offs); 2745 sqtd->physaddr = DMAADDR(&dma, offs); 2746 sqtd->dma = dma; 2747 sqtd->offs = offs; 2748 2749 sqtd->nextqtd = sc->sc_freeqtds; 2750 sc->sc_freeqtds = sqtd; 2751 } 2752 } 2753 2754 sqtd = sc->sc_freeqtds; 2755 sc->sc_freeqtds = sqtd->nextqtd; 2756 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t)); 2757 sqtd->nextqtd = NULL; 2758 sqtd->xfer = NULL; 2759 2760 done: 2761 return sqtd; 2762 } 2763 2764 Static void 2765 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd) 2766 { 2767 2768 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 2769 2770 sqtd->nextqtd = sc->sc_freeqtds; 2771 sc->sc_freeqtds = sqtd; 2772 } 2773 2774 Static usbd_status 2775 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, 2776 int alen, int rd, struct usbd_xfer *xfer, 2777 ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep) 2778 { 2779 ehci_soft_qtd_t *next, *cur; 2780 ehci_physaddr_t nextphys; 2781 uint32_t qtdstatus; 2782 int len, curlen, mps; 2783 int i, tog; 2784 int pages, pageoffs; 2785 size_t curoffs; 2786 vaddr_t va, va_offs; 2787 usb_dma_t *dma = &xfer->ux_dmabuf; 2788 uint16_t flags = xfer->ux_flags; 2789 paddr_t a; 2790 2791 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2792 2793 USBHIST_LOG(ehcidebug, "start len=%d", alen, 0, 0, 0); 2794 2795 len = alen; 2796 qtdstatus = EHCI_QTD_ACTIVE | 2797 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) | 2798 EHCI_QTD_SET_CERR(3) 2799 /* IOC set below */ 2800 /* BYTES set below */ 2801 ; 2802 mps = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 2803 tog = epipe->nexttoggle; 2804 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog); 2805 2806 cur = ehci_alloc_sqtd(sc); 2807 *sp = cur; 2808 if (cur == NULL) 2809 goto nomem; 2810 2811 usb_syncmem(dma, 0, alen, 2812 rd ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 2813 curoffs = 0; 2814 for (;;) { 2815 /* The EHCI hardware can handle at most 5 pages. */ 2816 va_offs = (vaddr_t)KERNADDR(dma, curoffs); 2817 va_offs = EHCI_PAGE_OFFSET(va_offs); 2818 if (len-curoffs < EHCI_QTD_MAXTRANSFER - va_offs) { 2819 /* we can handle it in this QTD */ 2820 curlen = len - curoffs; 2821 } else { 2822 /* must use multiple TDs, fill as much as possible. */ 2823 curlen = EHCI_QTD_MAXTRANSFER - va_offs; 2824 2825 /* the length must be a multiple of the max size */ 2826 curlen -= curlen % mps; 2827 USBHIST_LOG(ehcidebug, "multiple QTDs, " 2828 "curlen=%d", curlen, 0, 0, 0); 2829 KASSERT(curlen != 0); 2830 } 2831 USBHIST_LOG(ehcidebug, "len=%d curlen=%d curoffs=%zu", 2832 len, curlen, curoffs, 0); 2833 2834 /* 2835 * Allocate another transfer if there's more data left, 2836 * or if force last short transfer flag is set and we're 2837 * allocating a multiple of the max packet size. 2838 */ 2839 2840 if (curoffs + curlen != len || 2841 ((curlen % mps) == 0 && !rd && curlen != 0 && 2842 (flags & USBD_FORCE_SHORT_XFER))) { 2843 next = ehci_alloc_sqtd(sc); 2844 if (next == NULL) 2845 goto nomem; 2846 nextphys = htole32(next->physaddr); 2847 } else { 2848 next = NULL; 2849 nextphys = EHCI_NULL; 2850 } 2851 2852 /* Find number of pages we'll be using, insert dma addresses */ 2853 pages = EHCI_NPAGES(curlen); 2854 KASSERT(pages <= EHCI_QTD_NBUFFERS); 2855 pageoffs = EHCI_PAGE(curoffs); 2856 for (i = 0; i < pages; i++) { 2857 a = DMAADDR(dma, pageoffs + i * EHCI_PAGE_SIZE); 2858 cur->qtd.qtd_buffer[i] = htole32(EHCI_PAGE(a)); 2859 /* Cast up to avoid compiler warnings */ 2860 cur->qtd.qtd_buffer_hi[i] = htole32((uint64_t)a >> 32); 2861 } 2862 2863 /* First buffer pointer requires a page offset to start at */ 2864 va = (vaddr_t)KERNADDR(dma, curoffs); 2865 cur->qtd.qtd_buffer[0] |= htole32(EHCI_PAGE_OFFSET(va)); 2866 2867 cur->nextqtd = next; 2868 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys; 2869 cur->qtd.qtd_status = 2870 htole32(qtdstatus | EHCI_QTD_SET_BYTES(curlen)); 2871 cur->xfer = xfer; 2872 cur->len = curlen; 2873 2874 USBHIST_LOG(ehcidebug, "cbp=0x%08zx end=0x%08zx", 2875 curoffs, curoffs + curlen, 0, 0); 2876 2877 /* 2878 * adjust the toggle based on the number of packets in this 2879 * qtd 2880 */ 2881 if (((curlen + mps - 1) / mps) & 1) { 2882 tog ^= 1; 2883 qtdstatus ^= EHCI_QTD_TOGGLE_MASK; 2884 } 2885 if (next == NULL) 2886 break; 2887 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2888 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2889 USBHIST_LOG(ehcidebug, "extend chain", 0, 0, 0, 0); 2890 if (len) 2891 curoffs += curlen; 2892 cur = next; 2893 } 2894 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC); 2895 usb_syncmem(&cur->dma, cur->offs, sizeof(cur->qtd), 2896 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2897 *ep = cur; 2898 epipe->nexttoggle = tog; 2899 2900 USBHIST_LOG(ehcidebug, "return sqtd=%p sqtdend=%p", 2901 *sp, *ep, 0, 0); 2902 2903 return USBD_NORMAL_COMPLETION; 2904 2905 nomem: 2906 /* XXX free chain */ 2907 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 2908 return USBD_NOMEM; 2909 } 2910 2911 Static void 2912 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd, 2913 ehci_soft_qtd_t *sqtdend) 2914 { 2915 ehci_soft_qtd_t *p; 2916 int i; 2917 2918 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2919 2920 USBHIST_LOG(ehcidebug, "sqtd=%p sqtdend=%p", 2921 sqtd, sqtdend, 0, 0); 2922 2923 for (i = 0; sqtd != sqtdend; sqtd = p, i++) { 2924 p = sqtd->nextqtd; 2925 ehci_free_sqtd(sc, sqtd); 2926 } 2927 } 2928 2929 Static ehci_soft_itd_t * 2930 ehci_alloc_itd(ehci_softc_t *sc) 2931 { 2932 struct ehci_soft_itd *itd, *freeitd; 2933 usbd_status err; 2934 int i, offs, frindex, previndex; 2935 usb_dma_t dma; 2936 2937 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 2938 2939 mutex_enter(&sc->sc_lock); 2940 2941 /* 2942 * Find an itd that wasn't freed this frame or last frame. This can 2943 * discard itds that were freed before frindex wrapped around 2944 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 2945 * interrupt and fiddling with list when that happens 2946 */ 2947 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 2948 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 2949 2950 freeitd = NULL; 2951 LIST_FOREACH(itd, &sc->sc_freeitds, u.free_list) { 2952 if (itd == NULL) 2953 break; 2954 if (itd->slot != frindex && itd->slot != previndex) { 2955 freeitd = itd; 2956 break; 2957 } 2958 } 2959 2960 if (freeitd == NULL) { 2961 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 2962 err = usb_allocmem(&sc->sc_bus, EHCI_ITD_SIZE * EHCI_ITD_CHUNK, 2963 EHCI_PAGE_SIZE, &dma); 2964 2965 if (err) { 2966 USBHIST_LOG(ehcidebug, 2967 "alloc returned %d", err, 0, 0, 0); 2968 mutex_exit(&sc->sc_lock); 2969 return NULL; 2970 } 2971 2972 for (i = 0; i < EHCI_ITD_CHUNK; i++) { 2973 offs = i * EHCI_ITD_SIZE; 2974 itd = KERNADDR(&dma, offs); 2975 itd->physaddr = DMAADDR(&dma, offs); 2976 itd->dma = dma; 2977 itd->offs = offs; 2978 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 2979 } 2980 freeitd = LIST_FIRST(&sc->sc_freeitds); 2981 } 2982 2983 itd = freeitd; 2984 LIST_REMOVE(itd, u.free_list); 2985 memset(&itd->itd, 0, sizeof(ehci_itd_t)); 2986 usb_syncmem(&itd->dma, itd->offs + offsetof(ehci_itd_t, itd_next), 2987 sizeof(itd->itd.itd_next), 2988 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2989 2990 itd->u.frame_list.next = NULL; 2991 itd->u.frame_list.prev = NULL; 2992 itd->xfer_next = NULL; 2993 itd->slot = 0; 2994 2995 mutex_exit(&sc->sc_lock); 2996 2997 return itd; 2998 } 2999 3000 Static ehci_soft_sitd_t * 3001 ehci_alloc_sitd(ehci_softc_t *sc) 3002 { 3003 struct ehci_soft_sitd *sitd, *freesitd; 3004 usbd_status err; 3005 int i, offs, frindex, previndex; 3006 usb_dma_t dma; 3007 3008 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3009 3010 mutex_enter(&sc->sc_lock); 3011 3012 /* 3013 * Find an sitd that wasn't freed this frame or last frame. This can 3014 * discard sitds that were freed before frindex wrapped around 3015 * XXX - can this lead to thrashing? Could fix by enabling wrap-around 3016 * interrupt and fiddling with list when that happens 3017 */ 3018 frindex = (EOREAD4(sc, EHCI_FRINDEX) + 1) >> 3; 3019 previndex = (frindex != 0) ? frindex - 1 : sc->sc_flsize; 3020 3021 freesitd = NULL; 3022 LIST_FOREACH(sitd, &sc->sc_freesitds, u.free_list) { 3023 if (sitd == NULL) 3024 break; 3025 if (sitd->slot != frindex && sitd->slot != previndex) { 3026 freesitd = sitd; 3027 break; 3028 } 3029 } 3030 3031 if (freesitd == NULL) { 3032 USBHIST_LOG(ehcidebug, "allocating chunk", 0, 0, 0, 0); 3033 err = usb_allocmem(&sc->sc_bus, EHCI_SITD_SIZE * EHCI_SITD_CHUNK, 3034 EHCI_PAGE_SIZE, &dma); 3035 3036 if (err) { 3037 USBHIST_LOG(ehcidebug, 3038 "alloc returned %d", err, 0, 0, 0); 3039 mutex_exit(&sc->sc_lock); 3040 return NULL; 3041 } 3042 3043 for (i = 0; i < EHCI_SITD_CHUNK; i++) { 3044 offs = i * EHCI_SITD_SIZE; 3045 sitd = KERNADDR(&dma, offs); 3046 sitd->physaddr = DMAADDR(&dma, offs); 3047 sitd->dma = dma; 3048 sitd->offs = offs; 3049 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3050 } 3051 freesitd = LIST_FIRST(&sc->sc_freesitds); 3052 } 3053 3054 sitd = freesitd; 3055 LIST_REMOVE(sitd, u.free_list); 3056 memset(&sitd->sitd, 0, sizeof(ehci_sitd_t)); 3057 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_next), 3058 sizeof(sitd->sitd.sitd_next), BUS_DMASYNC_PREWRITE | 3059 BUS_DMASYNC_PREREAD); 3060 3061 sitd->u.frame_list.next = NULL; 3062 sitd->u.frame_list.prev = NULL; 3063 sitd->xfer_next = NULL; 3064 sitd->slot = 0; 3065 3066 mutex_exit(&sc->sc_lock); 3067 3068 return sitd; 3069 } 3070 3071 Static void 3072 ehci_free_itd(ehci_softc_t *sc, ehci_soft_itd_t *itd) 3073 { 3074 3075 KASSERT(mutex_owned(&sc->sc_lock)); 3076 3077 LIST_INSERT_HEAD(&sc->sc_freeitds, itd, u.free_list); 3078 } 3079 3080 Static void 3081 ehci_free_sitd(ehci_softc_t *sc, ehci_soft_sitd_t *sitd) 3082 { 3083 3084 KASSERT(mutex_owned(&sc->sc_lock)); 3085 3086 LIST_INSERT_HEAD(&sc->sc_freesitds, sitd, u.free_list); 3087 } 3088 3089 /****************/ 3090 3091 /* 3092 * Close a reqular pipe. 3093 * Assumes that there are no pending transactions. 3094 */ 3095 Static void 3096 ehci_close_pipe(struct usbd_pipe *pipe, ehci_soft_qh_t *head) 3097 { 3098 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3099 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3100 ehci_soft_qh_t *sqh = epipe->sqh; 3101 3102 KASSERT(mutex_owned(&sc->sc_lock)); 3103 3104 ehci_rem_qh(sc, sqh, head); 3105 ehci_free_sqh(sc, epipe->sqh); 3106 } 3107 3108 /* 3109 * Abort a device request. 3110 * If this routine is called at splusb() it guarantees that the request 3111 * will be removed from the hardware scheduling and that the callback 3112 * for it will be called with USBD_CANCELLED status. 3113 * It's impossible to guarantee that the requested transfer will not 3114 * have happened since the hardware runs concurrently. 3115 * If the transaction has already happened we rely on the ordinary 3116 * interrupt processing to process it. 3117 * XXX This is most probably wrong. 3118 * XXXMRG this doesn't make sense anymore. 3119 */ 3120 Static void 3121 ehci_abort_xfer(struct usbd_xfer *xfer, usbd_status status) 3122 { 3123 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3124 struct ehci_xfer *exfer = EXFER(xfer); 3125 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3126 ehci_soft_qh_t *sqh = epipe->sqh; 3127 ehci_soft_qtd_t *sqtd; 3128 ehci_physaddr_t cur; 3129 uint32_t qhstatus; 3130 int hit; 3131 int wake; 3132 3133 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3134 3135 USBHIST_LOG(ehcidebug, "xfer=%p pipe=%p", xfer, epipe, 0, 0); 3136 3137 KASSERT(mutex_owned(&sc->sc_lock)); 3138 ASSERT_SLEEPABLE(); 3139 3140 if (sc->sc_dying) { 3141 /* If we're dying, just do the software part. */ 3142 xfer->ux_status = status; /* make software ignore it */ 3143 callout_stop(&xfer->ux_callout); 3144 usb_transfer_complete(xfer); 3145 return; 3146 } 3147 3148 /* 3149 * If an abort is already in progress then just wait for it to 3150 * complete and return. 3151 */ 3152 if (xfer->ux_hcflags & UXFER_ABORTING) { 3153 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3154 #ifdef DIAGNOSTIC 3155 if (status == USBD_TIMEOUT) 3156 printf("ehci_abort_xfer: TIMEOUT while aborting\n"); 3157 #endif 3158 /* Override the status which might be USBD_TIMEOUT. */ 3159 xfer->ux_status = status; 3160 USBHIST_LOG(ehcidebug, "waiting for abort to finish", 3161 0, 0, 0, 0); 3162 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3163 while (xfer->ux_hcflags & UXFER_ABORTING) 3164 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3165 return; 3166 } 3167 xfer->ux_hcflags |= UXFER_ABORTING; 3168 3169 /* 3170 * Step 1: Make interrupt routine and hardware ignore xfer. 3171 */ 3172 xfer->ux_status = status; /* make software ignore it */ 3173 callout_stop(&xfer->ux_callout); 3174 3175 usb_syncmem(&sqh->dma, 3176 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3177 sizeof(sqh->qh.qh_qtd.qtd_status), 3178 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3179 qhstatus = sqh->qh.qh_qtd.qtd_status; 3180 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED); 3181 usb_syncmem(&sqh->dma, 3182 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3183 sizeof(sqh->qh.qh_qtd.qtd_status), 3184 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3185 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3186 usb_syncmem(&sqtd->dma, 3187 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3188 sizeof(sqtd->qtd.qtd_status), 3189 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3190 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED); 3191 usb_syncmem(&sqtd->dma, 3192 sqtd->offs + offsetof(ehci_qtd_t, qtd_status), 3193 sizeof(sqtd->qtd.qtd_status), 3194 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3195 if (sqtd == exfer->ex_sqtdend) 3196 break; 3197 } 3198 3199 /* 3200 * Step 2: Wait until we know hardware has finished any possible 3201 * use of the xfer. Also make sure the soft interrupt routine 3202 * has run. 3203 */ 3204 ehci_sync_hc(sc); 3205 sc->sc_softwake = 1; 3206 usb_schedsoftintr(&sc->sc_bus); 3207 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3208 3209 /* 3210 * Step 3: Remove any vestiges of the xfer from the hardware. 3211 * The complication here is that the hardware may have executed 3212 * beyond the xfer we're trying to abort. So as we're scanning 3213 * the TDs of this xfer we check if the hardware points to 3214 * any of them. 3215 */ 3216 3217 usb_syncmem(&sqh->dma, 3218 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3219 sizeof(sqh->qh.qh_curqtd), 3220 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3221 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd)); 3222 hit = 0; 3223 for (sqtd = exfer->ex_sqtdstart; ; sqtd = sqtd->nextqtd) { 3224 hit |= cur == sqtd->physaddr; 3225 if (sqtd == exfer->ex_sqtdend) 3226 break; 3227 } 3228 sqtd = sqtd->nextqtd; 3229 /* Zap curqtd register if hardware pointed inside the xfer. */ 3230 if (hit && sqtd != NULL) { 3231 USBHIST_LOG(ehcidebug, "cur=0x%08x", sqtd->physaddr, 0, 0, 0); 3232 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */ 3233 usb_syncmem(&sqh->dma, 3234 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3235 sizeof(sqh->qh.qh_curqtd), 3236 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3237 sqh->qh.qh_qtd.qtd_status = qhstatus; 3238 usb_syncmem(&sqh->dma, 3239 sqh->offs + offsetof(ehci_qh_t, qh_qtd.qtd_status), 3240 sizeof(sqh->qh.qh_qtd.qtd_status), 3241 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3242 } else { 3243 USBHIST_LOG(ehcidebug, "no hit", 0, 0, 0, 0); 3244 usb_syncmem(&sqh->dma, 3245 sqh->offs + offsetof(ehci_qh_t, qh_curqtd), 3246 sizeof(sqh->qh.qh_curqtd), 3247 BUS_DMASYNC_PREREAD); 3248 } 3249 3250 /* 3251 * Step 4: Execute callback. 3252 */ 3253 #ifdef DIAGNOSTIC 3254 exfer->ex_isdone = true; 3255 #endif 3256 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3257 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3258 usb_transfer_complete(xfer); 3259 if (wake) { 3260 cv_broadcast(&xfer->ux_hccv); 3261 } 3262 3263 KASSERT(mutex_owned(&sc->sc_lock)); 3264 } 3265 3266 Static void 3267 ehci_abort_isoc_xfer(struct usbd_xfer *xfer, usbd_status status) 3268 { 3269 ehci_isoc_trans_t trans_status; 3270 struct ehci_pipe *epipe; 3271 struct ehci_xfer *exfer; 3272 ehci_softc_t *sc; 3273 struct ehci_soft_itd *itd; 3274 struct ehci_soft_sitd *sitd; 3275 int i, wake; 3276 3277 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3278 3279 epipe = (struct ehci_pipe *) xfer->ux_pipe; 3280 exfer = EXFER(xfer); 3281 sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3282 3283 USBHIST_LOG(ehcidebug, "xfer %p pipe %p", xfer, epipe, 0, 0); 3284 3285 KASSERT(mutex_owned(&sc->sc_lock)); 3286 3287 if (sc->sc_dying) { 3288 xfer->ux_status = status; 3289 callout_stop(&xfer->ux_callout); 3290 usb_transfer_complete(xfer); 3291 return; 3292 } 3293 3294 if (xfer->ux_hcflags & UXFER_ABORTING) { 3295 USBHIST_LOG(ehcidebug, "already aborting", 0, 0, 0, 0); 3296 3297 #ifdef DIAGNOSTIC 3298 if (status == USBD_TIMEOUT) 3299 printf("ehci_abort_isoc_xfer: TIMEOUT while aborting\n"); 3300 #endif 3301 3302 xfer->ux_status = status; 3303 USBHIST_LOG(ehcidebug, 3304 "waiting for abort to finish", 0, 0, 0, 0); 3305 xfer->ux_hcflags |= UXFER_ABORTWAIT; 3306 while (xfer->ux_hcflags & UXFER_ABORTING) 3307 cv_wait(&xfer->ux_hccv, &sc->sc_lock); 3308 goto done; 3309 } 3310 xfer->ux_hcflags |= UXFER_ABORTING; 3311 3312 xfer->ux_status = status; 3313 callout_stop(&xfer->ux_callout); 3314 3315 if (xfer->ux_pipe->up_dev->ud_speed == USB_SPEED_HIGH) { 3316 for (itd = exfer->ex_itdstart; itd != NULL; 3317 itd = itd->xfer_next) { 3318 usb_syncmem(&itd->dma, 3319 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3320 sizeof(itd->itd.itd_ctl), 3321 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3322 3323 for (i = 0; i < 8; i++) { 3324 trans_status = le32toh(itd->itd.itd_ctl[i]); 3325 trans_status &= ~EHCI_ITD_ACTIVE; 3326 itd->itd.itd_ctl[i] = htole32(trans_status); 3327 } 3328 3329 usb_syncmem(&itd->dma, 3330 itd->offs + offsetof(ehci_itd_t, itd_ctl), 3331 sizeof(itd->itd.itd_ctl), 3332 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3333 } 3334 } else { 3335 for (sitd = exfer->ex_sitdstart; sitd != NULL; 3336 sitd = sitd->xfer_next) { 3337 usb_syncmem(&sitd->dma, 3338 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3339 sizeof(sitd->sitd.sitd_buffer), 3340 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 3341 3342 trans_status = le32toh(sitd->sitd.sitd_trans); 3343 trans_status &= ~EHCI_SITD_ACTIVE; 3344 sitd->sitd.sitd_trans = htole32(trans_status); 3345 3346 usb_syncmem(&sitd->dma, 3347 sitd->offs + offsetof(ehci_sitd_t, sitd_buffer), 3348 sizeof(sitd->sitd.sitd_buffer), 3349 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3350 } 3351 } 3352 3353 sc->sc_softwake = 1; 3354 usb_schedsoftintr(&sc->sc_bus); 3355 cv_wait(&sc->sc_softwake_cv, &sc->sc_lock); 3356 3357 #ifdef DIAGNOSTIC 3358 exfer->ex_isdone = true; 3359 #endif 3360 wake = xfer->ux_hcflags & UXFER_ABORTWAIT; 3361 xfer->ux_hcflags &= ~(UXFER_ABORTING | UXFER_ABORTWAIT); 3362 usb_transfer_complete(xfer); 3363 if (wake) { 3364 cv_broadcast(&xfer->ux_hccv); 3365 } 3366 3367 done: 3368 KASSERT(mutex_owned(&sc->sc_lock)); 3369 return; 3370 } 3371 3372 Static void 3373 ehci_timeout(void *addr) 3374 { 3375 struct ehci_xfer *exfer = addr; 3376 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->ex_xfer.ux_pipe; 3377 ehci_softc_t *sc = epipe->pipe.up_dev->ud_bus->ub_hcpriv; 3378 3379 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3380 3381 USBHIST_LOG(ehcidebug, "exfer %p", exfer, 0, 0, 0); 3382 #ifdef EHCI_DEBUG 3383 if (ehcidebug > 1) 3384 usbd_dump_pipe(exfer->ex_xfer.ux_pipe); 3385 #endif 3386 3387 if (sc->sc_dying) { 3388 mutex_enter(&sc->sc_lock); 3389 ehci_abort_xfer(&exfer->ex_xfer, USBD_TIMEOUT); 3390 mutex_exit(&sc->sc_lock); 3391 return; 3392 } 3393 3394 /* Execute the abort in a process context. */ 3395 usb_init_task(&exfer->ex_aborttask, ehci_timeout_task, addr, 3396 USB_TASKQ_MPSAFE); 3397 usb_add_task(exfer->ex_xfer.ux_pipe->up_dev, &exfer->ex_aborttask, 3398 USB_TASKQ_HC); 3399 } 3400 3401 Static void 3402 ehci_timeout_task(void *addr) 3403 { 3404 struct usbd_xfer *xfer = addr; 3405 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3406 3407 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3408 3409 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3410 3411 mutex_enter(&sc->sc_lock); 3412 ehci_abort_xfer(xfer, USBD_TIMEOUT); 3413 mutex_exit(&sc->sc_lock); 3414 } 3415 3416 /************************/ 3417 3418 Static usbd_status 3419 ehci_device_ctrl_transfer(struct usbd_xfer *xfer) 3420 { 3421 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3422 usbd_status err; 3423 3424 /* Insert last in queue. */ 3425 mutex_enter(&sc->sc_lock); 3426 err = usb_insert_transfer(xfer); 3427 mutex_exit(&sc->sc_lock); 3428 if (err) 3429 return err; 3430 3431 /* Pipe isn't running, start first */ 3432 return ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3433 } 3434 3435 Static usbd_status 3436 ehci_device_ctrl_start(struct usbd_xfer *xfer) 3437 { 3438 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3439 usbd_status err; 3440 3441 if (sc->sc_dying) 3442 return USBD_IOERROR; 3443 3444 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3445 3446 err = ehci_device_request(xfer); 3447 if (err) { 3448 return err; 3449 } 3450 3451 if (sc->sc_bus.ub_usepolling) 3452 ehci_waitintr(sc, xfer); 3453 3454 return USBD_IN_PROGRESS; 3455 } 3456 3457 Static void 3458 ehci_device_ctrl_done(struct usbd_xfer *xfer) 3459 { 3460 struct ehci_xfer *ex = EXFER(xfer); 3461 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3462 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3463 usb_device_request_t *req = &xfer->ux_request; 3464 int len = UGETW(req->wLength); 3465 int rd = req->bmRequestType & UT_READ; 3466 3467 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3468 3469 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3470 3471 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 3472 KASSERT(xfer->ux_rqflags & URQ_REQUEST); 3473 3474 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3475 ehci_del_intr_list(sc, ex); /* remove from active list */ 3476 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3477 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof(*req), 3478 BUS_DMASYNC_POSTWRITE); 3479 if (len) 3480 usb_syncmem(&xfer->ux_dmabuf, 0, len, 3481 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3482 } 3483 3484 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3485 } 3486 3487 /* Abort a device control request. */ 3488 Static void 3489 ehci_device_ctrl_abort(struct usbd_xfer *xfer) 3490 { 3491 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3492 3493 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3494 ehci_abort_xfer(xfer, USBD_CANCELLED); 3495 } 3496 3497 /* Close a device control pipe. */ 3498 Static void 3499 ehci_device_ctrl_close(struct usbd_pipe *pipe) 3500 { 3501 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3502 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/ 3503 3504 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3505 3506 KASSERT(mutex_owned(&sc->sc_lock)); 3507 3508 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3509 3510 ehci_close_pipe(pipe, sc->sc_async_head); 3511 } 3512 3513 Static usbd_status 3514 ehci_device_request(struct usbd_xfer *xfer) 3515 { 3516 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3517 struct ehci_xfer *exfer = EXFER(xfer); 3518 usb_device_request_t *req = &xfer->ux_request; 3519 struct usbd_device *dev = epipe->pipe.up_dev; 3520 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3521 ehci_soft_qtd_t *setup, *stat, *next; 3522 ehci_soft_qh_t *sqh; 3523 int isread; 3524 int len; 3525 usbd_status err; 3526 3527 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3528 3529 isread = req->bmRequestType & UT_READ; 3530 len = UGETW(req->wLength); 3531 3532 USBHIST_LOG(ehcidebug, "type=0x%02x, request=0x%02x, " 3533 "wValue=0x%04x, wIndex=0x%04x", 3534 req->bmRequestType, req->bRequest, UGETW(req->wValue), 3535 UGETW(req->wIndex)); 3536 USBHIST_LOG(ehcidebug, "len=%d, addr=%d, endpt=%d", 3537 len, dev->ud_addr, 3538 epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress, 0); 3539 3540 setup = ehci_alloc_sqtd(sc); 3541 if (setup == NULL) { 3542 err = USBD_NOMEM; 3543 goto bad1; 3544 } 3545 stat = ehci_alloc_sqtd(sc); 3546 if (stat == NULL) { 3547 err = USBD_NOMEM; 3548 goto bad2; 3549 } 3550 3551 mutex_enter(&sc->sc_lock); 3552 3553 sqh = epipe->sqh; 3554 3555 KASSERTMSG(EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)) == dev->ud_addr, 3556 "address QH %" __PRIuBIT " pipe %d\n", 3557 EHCI_QH_GET_ADDR(le32toh(sqh->qh.qh_endp)), dev->ud_addr); 3558 KASSERTMSG(EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)) == 3559 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize), 3560 "MPS QH %" __PRIuBIT " pipe %d\n", 3561 EHCI_QH_GET_MPL(le32toh(sqh->qh.qh_endp)), 3562 UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize)); 3563 3564 /* Set up data transaction */ 3565 if (len != 0) { 3566 ehci_soft_qtd_t *end; 3567 3568 /* Start toggle at 1. */ 3569 epipe->nexttoggle = 1; 3570 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 3571 &next, &end); 3572 if (err) 3573 goto bad3; 3574 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC); 3575 end->nextqtd = stat; 3576 end->qtd.qtd_next = end->qtd.qtd_altnext = 3577 htole32(stat->physaddr); 3578 usb_syncmem(&end->dma, end->offs, sizeof(end->qtd), 3579 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3580 } else { 3581 next = stat; 3582 } 3583 3584 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req)); 3585 usb_syncmem(&epipe->u.ctl.reqdma, 0, sizeof(*req), BUS_DMASYNC_PREWRITE); 3586 3587 /* Clear toggle */ 3588 setup->qtd.qtd_status = htole32( 3589 EHCI_QTD_ACTIVE | 3590 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) | 3591 EHCI_QTD_SET_CERR(3) | 3592 EHCI_QTD_SET_TOGGLE(0) | 3593 EHCI_QTD_SET_BYTES(sizeof(*req)) 3594 ); 3595 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0)); 3596 setup->qtd.qtd_buffer_hi[0] = 0; 3597 setup->nextqtd = next; 3598 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr); 3599 setup->xfer = xfer; 3600 setup->len = sizeof(*req); 3601 usb_syncmem(&setup->dma, setup->offs, sizeof(setup->qtd), 3602 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3603 3604 stat->qtd.qtd_status = htole32( 3605 EHCI_QTD_ACTIVE | 3606 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) | 3607 EHCI_QTD_SET_CERR(3) | 3608 EHCI_QTD_SET_TOGGLE(1) | 3609 EHCI_QTD_IOC 3610 ); 3611 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */ 3612 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */ 3613 stat->nextqtd = NULL; 3614 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL; 3615 stat->xfer = xfer; 3616 stat->len = 0; 3617 usb_syncmem(&stat->dma, stat->offs, sizeof(stat->qtd), 3618 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 3619 3620 #ifdef EHCI_DEBUG 3621 USBHIST_LOGN(ehcidebug, 5, "dump:", 0, 0, 0, 0); 3622 ehci_dump_sqh(sqh); 3623 ehci_dump_sqtds(setup); 3624 #endif 3625 3626 exfer->ex_sqtdstart = setup; 3627 exfer->ex_sqtdend = stat; 3628 KASSERT(exfer->ex_isdone); 3629 #ifdef DIAGNOSTIC 3630 exfer->ex_isdone = false; 3631 #endif 3632 3633 /* Insert qTD in QH list. */ 3634 ehci_set_qh_qtd(sqh, setup); /* also does usb_syncmem(sqh) */ 3635 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3636 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3637 ehci_timeout, xfer); 3638 } 3639 ehci_add_intr_list(sc, exfer); 3640 xfer->ux_status = USBD_IN_PROGRESS; 3641 mutex_exit(&sc->sc_lock); 3642 3643 #ifdef EHCI_DEBUG 3644 USBHIST_LOGN(ehcidebug, 10, "status=%x, dump:", 3645 EOREAD4(sc, EHCI_USBSTS), 0, 0, 0); 3646 // delay(10000); 3647 ehci_dump_regs(sc); 3648 ehci_dump_sqh(sc->sc_async_head); 3649 ehci_dump_sqh(sqh); 3650 ehci_dump_sqtds(setup); 3651 #endif 3652 3653 return USBD_NORMAL_COMPLETION; 3654 3655 bad3: 3656 mutex_exit(&sc->sc_lock); 3657 ehci_free_sqtd(sc, stat); 3658 bad2: 3659 ehci_free_sqtd(sc, setup); 3660 bad1: 3661 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3662 mutex_enter(&sc->sc_lock); 3663 xfer->ux_status = err; 3664 usb_transfer_complete(xfer); 3665 mutex_exit(&sc->sc_lock); 3666 return err; 3667 } 3668 3669 /* 3670 * Some EHCI chips from VIA seem to trigger interrupts before writing back the 3671 * qTD status, or miss signalling occasionally under heavy load. If the host 3672 * machine is too fast, we we can miss transaction completion - when we scan 3673 * the active list the transaction still seems to be active. This generally 3674 * exhibits itself as a umass stall that never recovers. 3675 * 3676 * We work around this behaviour by setting up this callback after any softintr 3677 * that completes with transactions still pending, giving us another chance to 3678 * check for completion after the writeback has taken place. 3679 */ 3680 Static void 3681 ehci_intrlist_timeout(void *arg) 3682 { 3683 ehci_softc_t *sc = arg; 3684 3685 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3686 3687 usb_schedsoftintr(&sc->sc_bus); 3688 } 3689 3690 /************************/ 3691 3692 Static usbd_status 3693 ehci_device_bulk_transfer(struct usbd_xfer *xfer) 3694 { 3695 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3696 usbd_status err; 3697 3698 /* Insert last in queue. */ 3699 mutex_enter(&sc->sc_lock); 3700 err = usb_insert_transfer(xfer); 3701 mutex_exit(&sc->sc_lock); 3702 if (err) 3703 return err; 3704 3705 /* Pipe isn't running, start first */ 3706 return ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3707 } 3708 3709 Static usbd_status 3710 ehci_device_bulk_start(struct usbd_xfer *xfer) 3711 { 3712 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3713 struct ehci_xfer *exfer = EXFER(xfer); 3714 struct usbd_device *dev = epipe->pipe.up_dev; 3715 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3716 ehci_soft_qtd_t *data, *dataend; 3717 ehci_soft_qh_t *sqh; 3718 usbd_status err; 3719 int len, isread, endpt; 3720 3721 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3722 3723 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3724 xfer, xfer->ux_length, xfer->ux_flags, 0); 3725 3726 if (sc->sc_dying) 3727 return USBD_IOERROR; 3728 3729 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3730 3731 mutex_enter(&sc->sc_lock); 3732 3733 len = xfer->ux_length; 3734 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3735 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3736 sqh = epipe->sqh; 3737 3738 epipe->u.bulk.length = len; 3739 3740 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3741 &dataend); 3742 if (err) { 3743 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3744 xfer->ux_status = err; 3745 usb_transfer_complete(xfer); 3746 mutex_exit(&sc->sc_lock); 3747 return err; 3748 } 3749 3750 #ifdef EHCI_DEBUG 3751 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3752 ehci_dump_sqh(sqh); 3753 ehci_dump_sqtds(data); 3754 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3755 #endif 3756 3757 /* Set up interrupt info. */ 3758 exfer->ex_sqtdstart = data; 3759 exfer->ex_sqtdend = dataend; 3760 KASSERT(exfer->ex_isdone); 3761 #ifdef DIAGNOSTIC 3762 exfer->ex_isdone = false; 3763 #endif 3764 3765 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3766 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3767 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3768 ehci_timeout, xfer); 3769 } 3770 ehci_add_intr_list(sc, exfer); 3771 xfer->ux_status = USBD_IN_PROGRESS; 3772 mutex_exit(&sc->sc_lock); 3773 3774 #ifdef EHCI_DEBUG 3775 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3776 // delay(10000); 3777 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3778 ehci_dump_regs(sc); 3779 #if 0 3780 printf("async_head:\n"); 3781 ehci_dump_sqh(sc->sc_async_head); 3782 #endif 3783 USBHIST_LOG(ehcidebug, "sqh:", 0, 0, 0, 0); 3784 ehci_dump_sqh(sqh); 3785 ehci_dump_sqtds(data); 3786 #endif 3787 3788 if (sc->sc_bus.ub_usepolling) 3789 ehci_waitintr(sc, xfer); 3790 3791 return USBD_IN_PROGRESS; 3792 } 3793 3794 Static void 3795 ehci_device_bulk_abort(struct usbd_xfer *xfer) 3796 { 3797 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3798 3799 USBHIST_LOG(ehcidebug, "xfer %p", xfer, 0, 0, 0); 3800 ehci_abort_xfer(xfer, USBD_CANCELLED); 3801 } 3802 3803 /* 3804 * Close a device bulk pipe. 3805 */ 3806 Static void 3807 ehci_device_bulk_close(struct usbd_pipe *pipe) 3808 { 3809 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3810 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3811 3812 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3813 3814 KASSERT(mutex_owned(&sc->sc_lock)); 3815 3816 USBHIST_LOG(ehcidebug, "pipe=%p", pipe, 0, 0, 0); 3817 pipe->up_endpoint->ue_toggle = epipe->nexttoggle; 3818 ehci_close_pipe(pipe, sc->sc_async_head); 3819 } 3820 3821 Static void 3822 ehci_device_bulk_done(struct usbd_xfer *xfer) 3823 { 3824 struct ehci_xfer *ex = EXFER(xfer); 3825 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3826 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3827 int endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3828 int rd = UE_GET_DIR(endpt) == UE_DIR_IN; 3829 3830 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3831 3832 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 3833 xfer, xfer->ux_actlen, 0, 0); 3834 3835 KASSERT(mutex_owned(&sc->sc_lock)); 3836 3837 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(ex)) { 3838 ehci_del_intr_list(sc, ex); /* remove from active list */ 3839 ehci_free_sqtd_chain(sc, ex->ex_sqtdstart, NULL); 3840 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 3841 rd ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 3842 } 3843 3844 USBHIST_LOG(ehcidebug, "length=%d", xfer->ux_actlen, 0, 0, 0); 3845 } 3846 3847 /************************/ 3848 3849 Static usbd_status 3850 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival) 3851 { 3852 struct ehci_soft_islot *isp; 3853 int islot, lev; 3854 3855 /* Find a poll rate that is large enough. */ 3856 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--) 3857 if (EHCI_ILEV_IVAL(lev) <= ival) 3858 break; 3859 3860 /* Pick an interrupt slot at the right level. */ 3861 /* XXX could do better than picking at random */ 3862 sc->sc_rand = (sc->sc_rand + 191) % sc->sc_flsize; 3863 islot = EHCI_IQHIDX(lev, sc->sc_rand); 3864 3865 sqh->islot = islot; 3866 isp = &sc->sc_islots[islot]; 3867 mutex_enter(&sc->sc_lock); 3868 ehci_add_qh(sc, sqh, isp->sqh); 3869 mutex_exit(&sc->sc_lock); 3870 3871 return USBD_NORMAL_COMPLETION; 3872 } 3873 3874 Static usbd_status 3875 ehci_device_intr_transfer(struct usbd_xfer *xfer) 3876 { 3877 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 3878 usbd_status err; 3879 3880 /* Insert last in queue. */ 3881 mutex_enter(&sc->sc_lock); 3882 err = usb_insert_transfer(xfer); 3883 mutex_exit(&sc->sc_lock); 3884 if (err) 3885 return err; 3886 3887 /* 3888 * Pipe isn't running (otherwise err would be USBD_INPROG), 3889 * so start it first. 3890 */ 3891 return ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->ux_pipe->up_queue)); 3892 } 3893 3894 Static usbd_status 3895 ehci_device_intr_start(struct usbd_xfer *xfer) 3896 { 3897 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 3898 struct ehci_xfer *exfer = EXFER(xfer); 3899 struct usbd_device *dev = xfer->ux_pipe->up_dev; 3900 ehci_softc_t *sc = dev->ud_bus->ub_hcpriv; 3901 ehci_soft_qtd_t *data, *dataend; 3902 ehci_soft_qh_t *sqh; 3903 usbd_status err; 3904 int len, isread, endpt; 3905 3906 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3907 3908 USBHIST_LOG(ehcidebug, "xfer=%p len=%d flags=%d", 3909 xfer, xfer->ux_length, xfer->ux_flags, 0); 3910 3911 if (sc->sc_dying) 3912 return USBD_IOERROR; 3913 3914 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 3915 3916 mutex_enter(&sc->sc_lock); 3917 3918 len = xfer->ux_length; 3919 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 3920 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 3921 sqh = epipe->sqh; 3922 3923 epipe->u.intr.length = len; 3924 3925 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data, 3926 &dataend); 3927 if (err) { 3928 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 3929 xfer->ux_status = err; 3930 usb_transfer_complete(xfer); 3931 mutex_exit(&sc->sc_lock); 3932 return err; 3933 } 3934 3935 #ifdef EHCI_DEBUG 3936 USBHIST_LOGN(ehcidebug, 5, "--- dump start ---", 0, 0, 0, 0); 3937 ehci_dump_sqh(sqh); 3938 ehci_dump_sqtds(data); 3939 USBHIST_LOGN(ehcidebug, 5, "--- dump end ---", 0, 0, 0, 0); 3940 #endif 3941 3942 /* Set up interrupt info. */ 3943 exfer->ex_sqtdstart = data; 3944 exfer->ex_sqtdend = dataend; 3945 KASSERT(exfer->ex_isdone); 3946 #ifdef DIAGNOSTIC 3947 exfer->ex_isdone = false; 3948 #endif 3949 3950 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 3951 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 3952 callout_reset(&xfer->ux_callout, mstohz(xfer->ux_timeout), 3953 ehci_timeout, xfer); 3954 } 3955 ehci_add_intr_list(sc, exfer); 3956 xfer->ux_status = USBD_IN_PROGRESS; 3957 mutex_exit(&sc->sc_lock); 3958 3959 #ifdef EHCI_DEBUG 3960 USBHIST_LOGN(ehcidebug, 5, "data(2)", 0, 0, 0, 0); 3961 // delay(10000); 3962 USBHIST_LOGN(ehcidebug, 5, "data(3)", 0, 0, 0, 0); 3963 ehci_dump_regs(sc); 3964 USBHIST_LOGN(ehcidebug, 5, "sqh:", 0, 0, 0, 0); 3965 ehci_dump_sqh(sqh); 3966 ehci_dump_sqtds(data); 3967 #endif 3968 3969 if (sc->sc_bus.ub_usepolling) 3970 ehci_waitintr(sc, xfer); 3971 3972 return USBD_IN_PROGRESS; 3973 } 3974 3975 Static void 3976 ehci_device_intr_abort(struct usbd_xfer *xfer) 3977 { 3978 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 3979 3980 USBHIST_LOG(ehcidebug, "xfer=%p", xfer, 0, 0, 0); 3981 KASSERT(xfer->ux_pipe->up_intrxfer == xfer); 3982 3983 /* 3984 * XXX - abort_xfer uses ehci_sync_hc, which syncs via the advance 3985 * async doorbell. That's dependent on the async list, wheras 3986 * intr xfers are periodic, should not use this? 3987 */ 3988 ehci_abort_xfer(xfer, USBD_CANCELLED); 3989 } 3990 3991 Static void 3992 ehci_device_intr_close(struct usbd_pipe *pipe) 3993 { 3994 ehci_softc_t *sc = pipe->up_dev->ud_bus->ub_hcpriv; 3995 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe; 3996 struct ehci_soft_islot *isp; 3997 3998 KASSERT(mutex_owned(&sc->sc_lock)); 3999 4000 isp = &sc->sc_islots[epipe->sqh->islot]; 4001 ehci_close_pipe(pipe, isp->sqh); 4002 } 4003 4004 Static void 4005 ehci_device_intr_done(struct usbd_xfer *xfer) 4006 { 4007 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4008 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->ux_pipe; 4009 struct ehci_xfer *exfer = EXFER(xfer); 4010 ehci_soft_qtd_t *data, *dataend; 4011 ehci_soft_qh_t *sqh; 4012 usbd_status err; 4013 int len, isread, endpt; 4014 4015 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4016 4017 USBHIST_LOG(ehcidebug, "xfer=%p, actlen=%d", 4018 xfer, xfer->ux_actlen, 0, 0); 4019 4020 KASSERT(sc->sc_bus.ub_usepolling || mutex_owned(&sc->sc_lock)); 4021 4022 if (xfer->ux_pipe->up_repeat) { 4023 ehci_free_sqtd_chain(sc, exfer->ex_sqtdstart, NULL); 4024 4025 len = epipe->u.intr.length; 4026 xfer->ux_length = len; 4027 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4028 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4029 usb_syncmem(&xfer->ux_dmabuf, 0, len, 4030 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4031 sqh = epipe->sqh; 4032 4033 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, 4034 &data, &dataend); 4035 if (err) { 4036 USBHIST_LOG(ehcidebug, "no memory", 0, 0, 0, 0); 4037 xfer->ux_status = err; 4038 return; 4039 } 4040 4041 /* Set up interrupt info. */ 4042 exfer->ex_sqtdstart = data; 4043 exfer->ex_sqtdend = dataend; 4044 KASSERT(exfer->ex_isdone); 4045 #ifdef DIAGNOSTIC 4046 exfer->ex_isdone = false; 4047 #endif 4048 4049 ehci_set_qh_qtd(sqh, data); /* also does usb_syncmem(sqh) */ 4050 if (xfer->ux_timeout && !sc->sc_bus.ub_usepolling) { 4051 callout_reset(&xfer->ux_callout, 4052 mstohz(xfer->ux_timeout), ehci_timeout, xfer); 4053 } 4054 4055 xfer->ux_status = USBD_IN_PROGRESS; 4056 } else if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4057 ehci_del_intr_list(sc, exfer); /* remove from active list */ 4058 ehci_free_sqtd_chain(sc, exfer->ex_sqtdstart, NULL); 4059 endpt = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4060 isread = UE_GET_DIR(endpt) == UE_DIR_IN; 4061 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, 4062 isread ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 4063 } 4064 } 4065 4066 /************************/ 4067 4068 Static usbd_status 4069 ehci_device_fs_isoc_transfer(struct usbd_xfer *xfer) 4070 { 4071 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4072 usbd_status err; 4073 4074 mutex_enter(&sc->sc_lock); 4075 err = usb_insert_transfer(xfer); 4076 mutex_exit(&sc->sc_lock); 4077 4078 if (err && err != USBD_IN_PROGRESS) 4079 return err; 4080 4081 return ehci_device_fs_isoc_start(xfer); 4082 } 4083 4084 Static usbd_status 4085 ehci_device_fs_isoc_start(struct usbd_xfer *xfer) 4086 { 4087 struct ehci_pipe *epipe; 4088 struct usbd_device *dev; 4089 ehci_softc_t *sc; 4090 struct ehci_xfer *exfer; 4091 ehci_soft_sitd_t *sitd, *prev, *start, *stop; 4092 usb_dma_t *dma_buf; 4093 int i, j, k, frames; 4094 int offs, total_length; 4095 int frindex; 4096 u_int huba, dir; 4097 4098 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4099 4100 start = NULL; 4101 prev = NULL; 4102 sitd = NULL; 4103 total_length = 0; 4104 exfer = (struct ehci_xfer *) xfer; 4105 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4106 dev = xfer->ux_pipe->up_dev; 4107 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4108 4109 /* 4110 * To allow continuous transfers, above we start all transfers 4111 * immediately. However, we're still going to get usbd_start_next call 4112 * this when another xfer completes. So, check if this is already 4113 * in progress or not 4114 */ 4115 4116 if (exfer->ex_sitdstart != NULL) 4117 return USBD_IN_PROGRESS; 4118 4119 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4120 xfer, xfer->ux_length, xfer->ux_flags, 0); 4121 4122 if (sc->sc_dying) 4123 return USBD_IOERROR; 4124 4125 /* 4126 * To avoid complication, don't allow a request right now that'll span 4127 * the entire frame table. To within 4 frames, to allow some leeway 4128 * on either side of where the hc currently is. 4129 */ 4130 if (epipe->pipe.up_endpoint->ue_edesc->bInterval * 4131 xfer->ux_nframes >= sc->sc_flsize - 4) { 4132 printf("ehci: isoc descriptor requested that spans the entire" 4133 "frametable, too many frames\n"); 4134 return USBD_INVAL; 4135 } 4136 4137 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4138 KASSERT(exfer->ex_isdone); 4139 4140 #ifdef DIAGNOSTIC 4141 exfer->ex_isdone = false; 4142 #endif 4143 4144 /* 4145 * Step 1: Allocate and initialize sitds. 4146 */ 4147 4148 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4149 if (i > 16 || i == 0) { 4150 /* Spec page 271 says intervals > 16 are invalid */ 4151 USBHIST_LOG(ehcidebug, "bInterval %d invalid", 0, 0, 0, 0); 4152 4153 return USBD_INVAL; 4154 } 4155 4156 frames = xfer->ux_nframes; 4157 4158 if (frames == 0) { 4159 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4160 4161 return USBD_INVAL; 4162 } 4163 4164 dma_buf = &xfer->ux_dmabuf; 4165 offs = 0; 4166 4167 for (i = 0; i < frames; i++) { 4168 sitd = ehci_alloc_sitd(sc); 4169 4170 if (prev) 4171 prev->xfer_next = sitd; 4172 else 4173 start = sitd; 4174 4175 #ifdef DIAGNOSTIC 4176 if (xfer->ux_frlengths[i] > 0x3ff) { 4177 printf("ehci: invalid frame length\n"); 4178 xfer->ux_frlengths[i] = 0x3ff; 4179 } 4180 #endif 4181 4182 sitd->sitd.sitd_trans = htole32(EHCI_SITD_ACTIVE | 4183 EHCI_SITD_SET_LEN(xfer->ux_frlengths[i])); 4184 4185 /* Set page0 index and offset. */ 4186 sitd->sitd.sitd_buffer[0] = htole32(DMAADDR(dma_buf, offs)); 4187 4188 total_length += xfer->ux_frlengths[i]; 4189 offs += xfer->ux_frlengths[i]; 4190 4191 sitd->sitd.sitd_buffer[1] = 4192 htole32(EHCI_SITD_SET_BPTR(DMAADDR(dma_buf, offs - 1))); 4193 4194 huba = dev->ud_myhsport->up_parent->ud_addr; 4195 4196 /* if (sc->sc_flags & EHCIF_FREESCALE) { 4197 // Set hub address to 0 if embedded TT is used. 4198 if (huba == sc->sc_addr) 4199 huba = 0; 4200 } 4201 */ 4202 4203 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4204 dir = UE_GET_DIR(k) ? 1 : 0; 4205 sitd->sitd.sitd_endp = 4206 htole32(EHCI_SITD_SET_ENDPT(UE_GET_ADDR(k)) | 4207 EHCI_SITD_SET_DADDR(dev->ud_addr) | 4208 EHCI_SITD_SET_PORT(dev->ud_myhsport->up_portno) | 4209 EHCI_SITD_SET_HUBA(huba) | 4210 EHCI_SITD_SET_DIR(dir)); 4211 4212 sitd->sitd.sitd_back = htole32(EHCI_LINK_TERMINATE); 4213 4214 /* XXX */ 4215 u_char sa, sb; 4216 u_int temp, tlen; 4217 sa = 0; 4218 4219 if (dir == 0) { /* OUT */ 4220 temp = 0; 4221 tlen = xfer->ux_frlengths[i]; 4222 if (tlen <= 188) { 4223 temp |= 1; /* T-count = 1, TP = ALL */ 4224 tlen = 1; 4225 } else { 4226 tlen += 187; 4227 tlen /= 188; 4228 temp |= tlen; /* T-count = [1..6] */ 4229 temp |= 8; /* TP = Begin */ 4230 } 4231 sitd->sitd.sitd_buffer[1] |= htole32(temp); 4232 4233 tlen += sa; 4234 4235 if (tlen >= 8) { 4236 sb = 0; 4237 } else { 4238 sb = (1 << tlen); 4239 } 4240 4241 sa = (1 << sa); 4242 sa = (sb - sa) & 0x3F; 4243 sb = 0; 4244 } else { 4245 sb = (-(4 << sa)) & 0xFE; 4246 sa = (1 << sa) & 0x3F; 4247 sa = 0x01; 4248 sb = 0xfc; 4249 } 4250 4251 sitd->sitd.sitd_sched = htole32(EHCI_SITD_SET_SMASK(sa) | 4252 EHCI_SITD_SET_CMASK(sb)); 4253 4254 usb_syncmem(&sitd->dma, sitd->offs, sizeof(ehci_sitd_t), 4255 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4256 4257 prev = sitd; 4258 } /* End of frame */ 4259 4260 sitd->sitd.sitd_trans |= htole32(EHCI_SITD_IOC); 4261 4262 usb_syncmem(&sitd->dma, sitd->offs + offsetof(ehci_sitd_t, sitd_trans), 4263 sizeof(sitd->sitd.sitd_trans), 4264 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4265 4266 stop = sitd; 4267 stop->xfer_next = NULL; 4268 4269 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4270 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4271 4272 /* 4273 * Part 2: Transfer descriptors have now been set up, now they must 4274 * be scheduled into the periodic frame list. Erk. Not wanting to 4275 * complicate matters, transfer is denied if the transfer spans 4276 * more than the period frame list. 4277 */ 4278 4279 mutex_enter(&sc->sc_lock); 4280 4281 /* Start inserting frames */ 4282 if (epipe->u.isoc.cur_xfers > 0) { 4283 frindex = epipe->u.isoc.next_frame; 4284 } else { 4285 frindex = EOREAD4(sc, EHCI_FRINDEX); 4286 frindex = frindex >> 3; /* Erase microframe index */ 4287 frindex += 2; 4288 } 4289 4290 if (frindex >= sc->sc_flsize) 4291 frindex &= (sc->sc_flsize - 1); 4292 4293 /* Whats the frame interval? */ 4294 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4295 4296 sitd = start; 4297 for (j = 0; j < frames; j++) { 4298 if (sitd == NULL) 4299 panic("ehci: unexpectedly ran out of isoc sitds\n"); 4300 4301 usb_syncmem(&sc->sc_fldma, 4302 sizeof(ehci_link_t) * frindex, 4303 sizeof(ehci_link_t), 4304 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4305 4306 sitd->sitd.sitd_next = sc->sc_flist[frindex]; 4307 if (sitd->sitd.sitd_next == 0) 4308 /* 4309 * FIXME: frindex table gets initialized to NULL 4310 * or EHCI_NULL? 4311 */ 4312 sitd->sitd.sitd_next = EHCI_NULL; 4313 4314 usb_syncmem(&sitd->dma, 4315 sitd->offs + offsetof(ehci_sitd_t, sitd_next), 4316 sizeof(ehci_sitd_t), 4317 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4318 4319 sc->sc_flist[frindex] = 4320 htole32(EHCI_LINK_SITD | sitd->physaddr); 4321 4322 usb_syncmem(&sc->sc_fldma, 4323 sizeof(ehci_link_t) * frindex, 4324 sizeof(ehci_link_t), 4325 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4326 4327 sitd->u.frame_list.next = sc->sc_softsitds[frindex]; 4328 sc->sc_softsitds[frindex] = sitd; 4329 if (sitd->u.frame_list.next != NULL) 4330 sitd->u.frame_list.next->u.frame_list.prev = sitd; 4331 sitd->slot = frindex; 4332 sitd->u.frame_list.prev = NULL; 4333 4334 frindex += i; 4335 if (frindex >= sc->sc_flsize) 4336 frindex -= sc->sc_flsize; 4337 4338 sitd = sitd->xfer_next; 4339 } 4340 4341 epipe->u.isoc.cur_xfers++; 4342 epipe->u.isoc.next_frame = frindex; 4343 4344 exfer->ex_sitdstart = start; 4345 exfer->ex_sitdend = stop; 4346 4347 ehci_add_intr_list(sc, exfer); 4348 xfer->ux_status = USBD_IN_PROGRESS; 4349 4350 mutex_exit(&sc->sc_lock); 4351 4352 if (sc->sc_bus.ub_usepolling) { 4353 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4354 ehci_waitintr(sc, xfer); 4355 } 4356 4357 return USBD_IN_PROGRESS; 4358 } 4359 4360 Static void 4361 ehci_device_fs_isoc_abort(struct usbd_xfer *xfer) 4362 { 4363 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4364 4365 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4366 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4367 } 4368 4369 Static void 4370 ehci_device_fs_isoc_close(struct usbd_pipe *pipe) 4371 { 4372 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4373 4374 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4375 } 4376 4377 Static void 4378 ehci_device_fs_isoc_done(struct usbd_xfer *xfer) 4379 { 4380 struct ehci_xfer *exfer; 4381 ehci_softc_t *sc; 4382 struct ehci_pipe *epipe; 4383 4384 exfer = EXFER(xfer); 4385 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4386 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4387 4388 KASSERT(mutex_owned(&sc->sc_lock)); 4389 4390 epipe->u.isoc.cur_xfers--; 4391 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4392 ehci_del_intr_list(sc, exfer); 4393 ehci_rem_free_sitd_chain(sc, exfer); 4394 } 4395 4396 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4397 BUS_DMASYNC_POSTREAD); 4398 } 4399 Static usbd_status 4400 ehci_device_isoc_transfer(struct usbd_xfer *xfer) 4401 { 4402 ehci_softc_t *sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4403 usbd_status err; 4404 4405 mutex_enter(&sc->sc_lock); 4406 err = usb_insert_transfer(xfer); 4407 mutex_exit(&sc->sc_lock); 4408 if (err && err != USBD_IN_PROGRESS) 4409 return err; 4410 4411 return ehci_device_isoc_start(xfer); 4412 } 4413 4414 Static usbd_status 4415 ehci_device_isoc_start(struct usbd_xfer *xfer) 4416 { 4417 struct ehci_pipe *epipe; 4418 ehci_softc_t *sc; 4419 struct ehci_xfer *exfer; 4420 ehci_soft_itd_t *itd, *prev, *start, *stop; 4421 usb_dma_t *dma_buf; 4422 int i, j, k, frames, uframes, ufrperframe; 4423 int trans_count, offs, total_length; 4424 int frindex; 4425 4426 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4427 4428 start = NULL; 4429 prev = NULL; 4430 itd = NULL; 4431 trans_count = 0; 4432 total_length = 0; 4433 exfer = (struct ehci_xfer *) xfer; 4434 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4435 epipe = (struct ehci_pipe *)xfer->ux_pipe; 4436 4437 /* 4438 * To allow continuous transfers, above we start all transfers 4439 * immediately. However, we're still going to get usbd_start_next call 4440 * this when another xfer completes. So, check if this is already 4441 * in progress or not 4442 */ 4443 4444 if (exfer->ex_itdstart != NULL) 4445 return USBD_IN_PROGRESS; 4446 4447 USBHIST_LOG(ehcidebug, "xfer %p len %d flags %d", 4448 xfer, xfer->ux_length, xfer->ux_flags, 0); 4449 4450 if (sc->sc_dying) 4451 return USBD_IOERROR; 4452 4453 /* 4454 * To avoid complication, don't allow a request right now that'll span 4455 * the entire frame table. To within 4 frames, to allow some leeway 4456 * on either side of where the hc currently is. 4457 */ 4458 if ((1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval)) * 4459 xfer->ux_nframes >= (sc->sc_flsize - 4) * 8) { 4460 USBHIST_LOG(ehcidebug, 4461 "isoc descriptor spans entire frametable", 0, 0, 0, 0); 4462 printf("ehci: isoc descriptor requested that spans the entire frametable, too many frames\n"); 4463 return USBD_INVAL; 4464 } 4465 4466 KASSERT(!(xfer->ux_rqflags & URQ_REQUEST)); 4467 KASSERT(exfer->ex_isdone); 4468 #ifdef DIAGNOSTIC 4469 exfer->ex_isdone = false; 4470 #endif 4471 4472 /* 4473 * Step 1: Allocate and initialize itds, how many do we need? 4474 * One per transfer if interval >= 8 microframes, fewer if we use 4475 * multiple microframes per frame. 4476 */ 4477 4478 i = epipe->pipe.up_endpoint->ue_edesc->bInterval; 4479 if (i > 16 || i == 0) { 4480 /* Spec page 271 says intervals > 16 are invalid */ 4481 USBHIST_LOG(ehcidebug, "bInterval %d invalid", i, 0, 0, 0); 4482 return USBD_INVAL; 4483 } 4484 4485 ufrperframe = max(1, USB_UFRAMES_PER_FRAME / (1 << (i - 1))); 4486 frames = (xfer->ux_nframes + (ufrperframe - 1)) / ufrperframe; 4487 uframes = USB_UFRAMES_PER_FRAME / ufrperframe; 4488 4489 if (frames == 0) { 4490 USBHIST_LOG(ehcidebug, "frames == 0", 0, 0, 0, 0); 4491 return USBD_INVAL; 4492 } 4493 4494 dma_buf = &xfer->ux_dmabuf; 4495 offs = 0; 4496 4497 for (i = 0; i < frames; i++) { 4498 int froffs = offs; 4499 itd = ehci_alloc_itd(sc); 4500 4501 if (prev != NULL) { 4502 prev->itd.itd_next = 4503 htole32(itd->physaddr | EHCI_LINK_ITD); 4504 usb_syncmem(&prev->dma, 4505 prev->offs + offsetof(ehci_itd_t, itd_next), 4506 sizeof(prev->itd.itd_next), 4507 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4508 4509 prev->xfer_next = itd; 4510 } else { 4511 start = itd; 4512 } 4513 4514 /* 4515 * Step 1.5, initialize uframes 4516 */ 4517 for (j = 0; j < EHCI_ITD_NUFRAMES; j += uframes) { 4518 /* Calculate which page in the list this starts in */ 4519 int addr = DMAADDR(dma_buf, froffs); 4520 addr = EHCI_PAGE_OFFSET(addr); 4521 addr += (offs - froffs); 4522 addr = EHCI_PAGE(addr); 4523 addr /= EHCI_PAGE_SIZE; 4524 4525 /* 4526 * This gets the initial offset into the first page, 4527 * looks how far further along the current uframe 4528 * offset is. Works out how many pages that is. 4529 */ 4530 4531 itd->itd.itd_ctl[j] = htole32 ( EHCI_ITD_ACTIVE | 4532 EHCI_ITD_SET_LEN(xfer->ux_frlengths[trans_count]) | 4533 EHCI_ITD_SET_PG(addr) | 4534 EHCI_ITD_SET_OFFS(EHCI_PAGE_OFFSET(DMAADDR(dma_buf,offs)))); 4535 4536 total_length += xfer->ux_frlengths[trans_count]; 4537 offs += xfer->ux_frlengths[trans_count]; 4538 trans_count++; 4539 4540 if (trans_count >= xfer->ux_nframes) { /*Set IOC*/ 4541 itd->itd.itd_ctl[j] |= htole32(EHCI_ITD_IOC); 4542 break; 4543 } 4544 } 4545 4546 /* 4547 * Step 1.75, set buffer pointers. To simplify matters, all 4548 * pointers are filled out for the next 7 hardware pages in 4549 * the dma block, so no need to worry what pages to cover 4550 * and what to not. 4551 */ 4552 4553 for (j = 0; j < EHCI_ITD_NBUFFERS; j++) { 4554 /* 4555 * Don't try to lookup a page that's past the end 4556 * of buffer 4557 */ 4558 int page_offs = EHCI_PAGE(froffs + (EHCI_PAGE_SIZE * j)); 4559 if (page_offs >= dma_buf->udma_block->size) 4560 break; 4561 4562 unsigned long long page = DMAADDR(dma_buf, page_offs); 4563 page = EHCI_PAGE(page); 4564 itd->itd.itd_bufr[j] = 4565 htole32(EHCI_ITD_SET_BPTR(page)); 4566 itd->itd.itd_bufr_hi[j] = 4567 htole32(page >> 32); 4568 } 4569 4570 /* 4571 * Other special values 4572 */ 4573 4574 k = epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress; 4575 itd->itd.itd_bufr[0] |= htole32(EHCI_ITD_SET_EP(UE_GET_ADDR(k)) | 4576 EHCI_ITD_SET_DADDR(epipe->pipe.up_dev->ud_addr)); 4577 4578 k = (UE_GET_DIR(epipe->pipe.up_endpoint->ue_edesc->bEndpointAddress)) 4579 ? 1 : 0; 4580 j = UGETW(epipe->pipe.up_endpoint->ue_edesc->wMaxPacketSize); 4581 itd->itd.itd_bufr[1] |= htole32(EHCI_ITD_SET_DIR(k) | 4582 EHCI_ITD_SET_MAXPKT(UE_GET_SIZE(j))); 4583 4584 /* FIXME: handle invalid trans */ 4585 itd->itd.itd_bufr[2] |= 4586 htole32(EHCI_ITD_SET_MULTI(UE_GET_TRANS(j)+1)); 4587 4588 usb_syncmem(&itd->dma, itd->offs, sizeof(ehci_itd_t), 4589 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4590 4591 prev = itd; 4592 } /* End of frame */ 4593 4594 stop = itd; 4595 stop->xfer_next = NULL; 4596 4597 usb_syncmem(&exfer->ex_xfer.ux_dmabuf, 0, total_length, 4598 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4599 4600 /* 4601 * Part 2: Transfer descriptors have now been set up, now they must 4602 * be scheduled into the period frame list. Erk. Not wanting to 4603 * complicate matters, transfer is denied if the transfer spans 4604 * more than the period frame list. 4605 */ 4606 4607 mutex_enter(&sc->sc_lock); 4608 4609 /* Start inserting frames */ 4610 if (epipe->u.isoc.cur_xfers > 0) { 4611 frindex = epipe->u.isoc.next_frame; 4612 } else { 4613 frindex = EOREAD4(sc, EHCI_FRINDEX); 4614 frindex = frindex >> 3; /* Erase microframe index */ 4615 frindex += 2; 4616 } 4617 4618 if (frindex >= sc->sc_flsize) 4619 frindex &= (sc->sc_flsize - 1); 4620 4621 /* What's the frame interval? */ 4622 i = (1 << (epipe->pipe.up_endpoint->ue_edesc->bInterval - 1)); 4623 if (i / USB_UFRAMES_PER_FRAME == 0) 4624 i = 1; 4625 else 4626 i /= USB_UFRAMES_PER_FRAME; 4627 4628 itd = start; 4629 for (j = 0; j < frames; j++) { 4630 if (itd == NULL) 4631 panic("ehci: unexpectedly ran out of isoc itds, isoc_start\n"); 4632 4633 usb_syncmem(&sc->sc_fldma, 4634 sizeof(ehci_link_t) * frindex, 4635 sizeof(ehci_link_t), 4636 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD); 4637 4638 itd->itd.itd_next = sc->sc_flist[frindex]; 4639 if (itd->itd.itd_next == 0) 4640 /* FIXME: frindex table gets initialized to NULL 4641 * or EHCI_NULL? */ 4642 itd->itd.itd_next = EHCI_NULL; 4643 4644 usb_syncmem(&itd->dma, 4645 itd->offs + offsetof(ehci_itd_t, itd_next), 4646 sizeof(itd->itd.itd_next), 4647 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4648 4649 sc->sc_flist[frindex] = htole32(EHCI_LINK_ITD | itd->physaddr); 4650 4651 usb_syncmem(&sc->sc_fldma, 4652 sizeof(ehci_link_t) * frindex, 4653 sizeof(ehci_link_t), 4654 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 4655 4656 itd->u.frame_list.next = sc->sc_softitds[frindex]; 4657 sc->sc_softitds[frindex] = itd; 4658 if (itd->u.frame_list.next != NULL) 4659 itd->u.frame_list.next->u.frame_list.prev = itd; 4660 itd->slot = frindex; 4661 itd->u.frame_list.prev = NULL; 4662 4663 frindex += i; 4664 if (frindex >= sc->sc_flsize) 4665 frindex -= sc->sc_flsize; 4666 4667 itd = itd->xfer_next; 4668 } 4669 4670 epipe->u.isoc.cur_xfers++; 4671 epipe->u.isoc.next_frame = frindex; 4672 4673 exfer->ex_itdstart = start; 4674 exfer->ex_itdend = stop; 4675 4676 ehci_add_intr_list(sc, exfer); 4677 xfer->ux_status = USBD_IN_PROGRESS; 4678 mutex_exit(&sc->sc_lock); 4679 4680 if (sc->sc_bus.ub_usepolling) { 4681 printf("Starting ehci isoc xfer with polling. Bad idea?\n"); 4682 ehci_waitintr(sc, xfer); 4683 } 4684 4685 return USBD_IN_PROGRESS; 4686 } 4687 4688 Static void 4689 ehci_device_isoc_abort(struct usbd_xfer *xfer) 4690 { 4691 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4692 4693 USBHIST_LOG(ehcidebug, "xfer = %p", xfer, 0, 0, 0); 4694 ehci_abort_isoc_xfer(xfer, USBD_CANCELLED); 4695 } 4696 4697 Static void 4698 ehci_device_isoc_close(struct usbd_pipe *pipe) 4699 { 4700 USBHIST_FUNC(); USBHIST_CALLED(ehcidebug); 4701 4702 USBHIST_LOG(ehcidebug, "nothing in the pipe to free?", 0, 0, 0, 0); 4703 } 4704 4705 Static void 4706 ehci_device_isoc_done(struct usbd_xfer *xfer) 4707 { 4708 struct ehci_xfer *exfer; 4709 ehci_softc_t *sc; 4710 struct ehci_pipe *epipe; 4711 4712 exfer = EXFER(xfer); 4713 sc = xfer->ux_pipe->up_dev->ud_bus->ub_hcpriv; 4714 epipe = (struct ehci_pipe *) xfer->ux_pipe; 4715 4716 KASSERT(mutex_owned(&sc->sc_lock)); 4717 4718 epipe->u.isoc.cur_xfers--; 4719 if (xfer->ux_status != USBD_NOMEM && ehci_active_intr_list(exfer)) { 4720 ehci_del_intr_list(sc, exfer); 4721 ehci_rem_free_itd_chain(sc, exfer); 4722 } 4723 4724 usb_syncmem(&xfer->ux_dmabuf, 0, xfer->ux_length, BUS_DMASYNC_POSTWRITE | 4725 BUS_DMASYNC_POSTREAD); 4726 4727 } 4728
Indexes created Wed Oct 01 19:09:53 GMT 2025